2011 files changed, 566320 insertions, 27267 deletions

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..95d83b6
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "thirdparty/tinyprintfX"]
+	path = thirdparty/tinyprintf
+	url = https://github.com/cjlano/tinyprintf
diff --git a/CMakeLists.txt b/CMakeLists.txt
index fbc73aa..e66b70e 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -32,13 +32,13 @@ function(add_extra_commands target_name)
 endfunction()
 
 # https://github.com/cjlano/tinyprintf
-add_library(tinyprintf STATIC tinyprintf/tinyprintf.c tinyprintf/tinyprintf.h)
-target_include_directories(tinyprintf PUBLIC tinyprintf)
+add_library(tinyprintf STATIC thirdparty/tinyprintf/tinyprintf.c thirdparty/tinyprintf/tinyprintf.h)
+target_include_directories(tinyprintf PUBLIC thirdparty/tinyprintf)
 
-set(STM32F10X_STDPERIPH_LIB ${CMAKE_SOURCE_DIR}/tmp/STM32F10x_StdPeriph_Lib_V3.5.0)
+set(STM32F10X_STDPERIPH_LIB ${CMAKE_SOURCE_DIR}/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0)
 set(STM32F10X_STDPERIPH_DEFINES STM32F10X_MD USE_STDPERIPH_DRIVER)
 set(PLAYGROUND_DIR ${CMAKE_SOURCE_DIR}/playground)
-set(TINYPRINTF_DIR ${CMAKE_SOURCE_DIR}/tinyprintf)
+set(TINYPRINTF_DIR ${CMAKE_SOURCE_DIR}/thirdparty/tinyprintf)
 
 add_library(playground OBJECT
         playground/src/init_low.s playground/src/init_high.cpp
@@ -52,7 +52,7 @@ add_library(playground OBJECT
         playground/include/debug.h)
 target_include_directories(playground PUBLIC
         playground/include
-        tinyprintf
+        thirdparty/tinyprintf
         ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/CoreSupport
         ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x
         ${STM32F10X_STDPERIPH_LIB}/Libraries/STM32F10x_StdPeriph_Driver/inc
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
new file mode 100644
index 0000000..a9d3e5f
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
@@ -0,0 +1,786 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr"); 
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+  
+//   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+  
+//   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
index 7ab7b4b..7ab7b4b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
new file mode 100644
index 0000000..fde27c9
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
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+          <tr>
+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../../Release_Notes.html">Back to Release page</a></span></td>
+          </tr>
+<tr style="">
+<td style="padding: 1.5pt;">
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr>
+<td style="padding: 0cm;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+<ol style="margin-top: 0cm;" start="1" type="1">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS
+update History</a><o:p></o:p></span></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
+</ol>
+<span style="font-family: &quot;Times New Roman&quot;;"></span>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS
+update History</span></h2><br>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h
+</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt
+definition for STM32F10x High-density Value line devices.<br>
+</span></li>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file&nbsp;provided within the CMSIS folder. <br>
+</span></li>
+
+            </ul>
+
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
+- 10/15/2010</span></h3>
+
+            <ol>
+<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>
+            </ol>
+
+            <ul style="margin-top: 0in;" type="disc">
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
+for&nbsp;<b>STM32F10x High-density Value line devices</b>.</span></li>
+            </ul>
+            <ol start="2">
+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>
+            </ol>
+
+
+            
+            <ul style="margin-top: 0in;" type="disc">
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>
+                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>
+</ul>
+                <li class="MsoNormal" style="">
+
+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">All
+STM32 devices definitions are commented by default. User has to select the
+appropriate device before starting else an error will be signaled on compile
+time.</span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li>
+</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
+              <ul>
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
+<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
+to select if the user want to place the Vector Table in internal SRAM.
+An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
+                  </span></li>
+
+              </ul>
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
+startup files for STM32 High-density Value line devices:
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>
+            </ul>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
+- 04/16/2010</span></h3>
+
+<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
+for&nbsp;<b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
+
+            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices&nbsp;(remove&nbsp;comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><br>
+                  </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
+startup files for STM32 XL-density&nbsp;devices:
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ&nbsp;Handler (was missing in&nbsp;previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
+- 03/01/2010</span></h3>
+<ol style="margin-top: 0in;" start="1" type="1">
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
+</ol>
+<ul style="margin-top: 0in;" type="disc">
+
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
+                </span></li>
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
+for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
+Medium-density Value line (STM32F100x8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
+
+</ul>
+<ol style="margin-top: 0in;" start="2" type="1">
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
+            <ul>
+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
+            </ul>
+            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
+
+            </ol>
+
+            <ul style="margin-top: 0in;" type="disc">
+
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
+              </li>
+              <ul>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
+the stm32f10x.h file to support new Value line devices features: CEC
+peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
+                  </span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
+HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
+HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
+purposes.<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
+              <ul>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
+                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
+                  </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
+                  </span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
+                  </span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>
+              <ul>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
+startup files for STM32 Low-density Value line devices:
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
+files for STM32 Medium-density Value line devices:
+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
+To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
+</span></li>
+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
+</span></li>
+              </ul>
+
+            </ul>
+
+<ul style="margin-top: 0in;" type="disc">
+</ul>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
+enclosed firmware and all the related documentation are not covered by
+a License Agreement, if you need such License you can contact your
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
+THEIR PRODUCTS. <o:p></o:p></span></b></p>
+<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..d84d468
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_cl.s
@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_cl.s
+  * @author    MCD Application Team
+  * @version   V3.5.0
+  * @date      11-March-2011
+  * @brief     STM32F10x Connectivity line Devices vector table for Atollic
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR
+  *                  address.
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+  	bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+  .word CAN1_TX_IRQHandler
+  .word CAN1_RX0_IRQHandler
+ 	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	OTG_FS_WKUP_IRQHandler
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word ETH_IRQHandler
+  .word ETH_WKUP_IRQHandler
+  .word CAN2_TX_IRQHandler
+  .word CAN2_RX0_IRQHandler
+  .word CAN2_RX1_IRQHandler
+  .word CAN2_SCE_IRQHandler
+  .word OTG_FS_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
+                         STM32F10x Connectivity line Devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	OTG_FS_WKUP_IRQHandler
+	.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	ETH_IRQHandler
+	.thumb_set ETH_IRQHandler,Default_Handler
+
+	.weak	ETH_WKUP_IRQHandler
+	.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+	.weak	CAN2_TX_IRQHandler
+	.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX0_IRQHandler
+	.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX1_IRQHandler
+	.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN2_SCE_IRQHandler
+	.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler ,Default_Handler
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s
index 4945a70..4945a70 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s
index 5f9df3d..5f9df3d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s
index baf697b..baf697b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s
index 833ece4..833ece4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s
index 8a19827..8a19827 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd.s
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..2768298
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,346 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x High Density Value Line Devices vector table  
+;*                      for MDK-ARM toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                 ; Window Watchdog
+                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler               ; Tamper
+                DCD     RTC_IRQHandler                  ; RTC
+                DCD     FLASH_IRQHandler                ; Flash
+                DCD     RCC_IRQHandler                  ; RCC
+                DCD     EXTI0_IRQHandler                ; EXTI Line 0
+                DCD     EXTI1_IRQHandler                ; EXTI Line 1
+                DCD     EXTI2_IRQHandler                ; EXTI Line 2
+                DCD     EXTI3_IRQHandler                ; EXTI Line 3
+                DCD     EXTI4_IRQHandler                ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                 ; ADC1
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                 ; TIM2
+                DCD     TIM3_IRQHandler                 ; TIM3
+                DCD     TIM4_IRQHandler                 ; TIM4
+                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
+                DCD     SPI1_IRQHandler                 ; SPI1
+                DCD     SPI2_IRQHandler                 ; SPI2
+                DCD     USART1_IRQHandler               ; USART1
+                DCD     USART2_IRQHandler               ; USART2
+                DCD     USART3_IRQHandler               ; USART3
+                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
+                DCD     CEC_IRQHandler                  ; HDMI-CEC
+                DCD     TIM12_IRQHandler                ; TIM12
+                DCD     TIM13_IRQHandler                ; TIM13 
+                DCD     TIM14_IRQHandler                ; TIM14
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     TIM5_IRQHandler                 ; TIM5
+                DCD     SPI3_IRQHandler                 ; SPI3
+                DCD     UART4_IRQHandler                ; UART4
+                DCD     UART5_IRQHandler                ; UART5
+                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
+                DCD     TIM7_IRQHandler                 ; TIM7
+                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
+                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_IRQHandler                   [WEAK]
+                EXPORT  TAMPER_IRQHandler                [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  EXTI9_5_IRQHandler               [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  EXTI15_10_IRQHandler             [WEAK]
+                EXPORT  RTCAlarm_IRQHandler              [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]                
+                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler         [WEAK]                
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+DMA2_Channel5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s
index f18be4b..f18be4b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s
index f7240dc..f7240dc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_ld_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s
index 09291a5..09291a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s
index 460f06c..460f06c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_hd_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s
index d771126..d771126 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_ld.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s
index 7333b16..7333b16 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_md.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s
index 3bc91f8..3bc91f8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_xl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s
index 0c87160..0c87160 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..401d67e
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,461 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 11-March-2011
+;* Description        : STM32F10x High Density Value Line Devices vector table 
+;*                      for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Configure the clock system and the external SRAM 
+;*                        mounted on STM32100E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler               ; Window Watchdog
+        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler             ; Tamper
+        DCD     RTC_IRQHandler                ; RTC
+        DCD     FLASH_IRQHandler              ; Flash
+        DCD     RCC_IRQHandler                ; RCC
+        DCD     EXTI0_IRQHandler              ; EXTI Line 0
+        DCD     EXTI1_IRQHandler              ; EXTI Line 1
+        DCD     EXTI2_IRQHandler              ; EXTI Line 2
+        DCD     EXTI3_IRQHandler              ; EXTI Line 3
+        DCD     EXTI4_IRQHandler              ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler               ; ADC1
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
+        DCD     TIM1_BRK_TIM15_IRQHandler     ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler      ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler               ; TIM2
+        DCD     TIM3_IRQHandler               ; TIM3
+        DCD     TIM4_IRQHandler               ; TIM4
+        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
+        DCD     SPI1_IRQHandler               ; SPI1
+        DCD     SPI2_IRQHandler               ; SPI2
+        DCD     USART1_IRQHandler             ; USART1
+        DCD     USART2_IRQHandler             ; USART2
+        DCD     USART3_IRQHandler             ; USART3
+        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
+        DCD     CEC_IRQHandler                ; HDMI-CEC
+        DCD     TIM12_IRQHandler              ; TIM12
+        DCD     TIM13_IRQHandler              ; TIM13
+        DCD     TIM14_IRQHandler              ; TIM14
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     TIM5_IRQHandler               ; TIM5
+        DCD     SPI3_IRQHandler               ; SPI3
+        DCD     UART4_IRQHandler              ; UART4
+        DCD     UART5_IRQHandler              ; UART5                       
+        DCD     TIM6_DAC_IRQHandler           ; TIM6 and DAC underrun
+        DCD     TIM7_IRQHandler               ; TIM7     
+        DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
+        DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
+        DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
+        DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5                   
+        DCD     DMA2_Channel5_IRQHandler      ; DMA2 Channel5
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM13_IRQHandler
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+        
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler                
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+        B DMA2_Channel4_5_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+                
+        END
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s
index 1c0a3e1..1c0a3e1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s
index 85531c5..85531c5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s
index 7a25707..7a25707 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
index 8bf7624..8bf7624 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/stm32f10x.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
new file mode 100644
index 0000000..71efc85
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h
index f6ca7ce..54bc1ab 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.h
@@ -1,10 +1,10 @@
 /**
   ******************************************************************************
-  * @file    fonts.h
+  * @file    system_stm32f10x.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   Header for fonts.c
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
   ******************************************************************************
   * @attention
   *
@@ -16,75 +16,68 @@
   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
 
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __FONTS_H
-#define __FONTS_H
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
 
 #ifdef __cplusplus
  extern "C" {
-#endif
+#endif 
 
-/* Includes ------------------------------------------------------------------*/
-#include <stdint.h>
-
-/** @addtogroup Utilities
+/** @addtogroup STM32F10x_System_Includes
   * @{
   */
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
 
-/** @addtogroup Common
-  * @{
+/**
+  * @}
   */
 
-/** @addtogroup FONTS
-  * @{
-  */ 
 
-/** @defgroup FONTS_Exported_Types
+/** @addtogroup STM32F10x_System_Exported_types
   * @{
-  */ 
-typedef struct _tFont
-{    
-  const uint16_t *table;
-  uint16_t Width;
-  uint16_t Height;
-  
-} sFONT;
+  */
 
-extern sFONT Font16x24;
-extern sFONT Font12x12;
-extern sFONT Font8x12;
-extern sFONT Font8x8;
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup FONTS_Exported_Constants
+/** @addtogroup STM32F10x_System_Exported_Constants
   * @{
-  */ 
-#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))
+  */
 
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup FONTS_Exported_Macros
+/** @addtogroup STM32F10x_System_Exported_Macros
   * @{
-  */ 
+  */
+
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup FONTS_Exported_Functions
+/** @addtogroup STM32F10x_System_Exported_Functions
   * @{
-  */ 
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
 /**
   * @}
   */
@@ -92,27 +85,14 @@ extern sFONT Font8x8;
 #ifdef __cplusplus
 }
 #endif
-  
-#endif /* __FONTS_H */
- 
-/**
-  * @}
-  */
 
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
+#endif /*__SYSTEM_STM32F10X_H */
 
 /**
   * @}
   */
-
+  
 /**
   * @}
-  */      
-
+  */  
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm
index 36e0446..36e0446 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS debug support.htm
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm
new file mode 100644
index 0000000..b8acb53
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Documentation/CMSIS_Core.htm
@@ -0,0 +1,1337 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:p="urn:schemas-microsoft-com:office:powerpoint" xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office"><head>
+  
+  <title>CMSIS: Cortex Microcontroller Software Interface Standard</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
+  <meta name="ProgId" content="FrontPage.Editor.Document">
+  <style>
+<!--
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+h2 { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
+h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
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+code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; line-height: 120%; font-style: normal }
+/*-----------------------------------------------------------Notes
+-----------------------------------------------------------*/
+p.note { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
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+-----------------------------------------------------------*/
+#expand { text-decoration: none; margin-bottom: 3pt }
+img.expand { border-style: none; border-width: medium }
+div.expand { display: none; margin-left: 9pt; margin-top: 0 }
+/*-----------------------------------------------------------Where List Tags
+-----------------------------------------------------------*/
+p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
+table.wh { width: 100% }
+td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 6pt }
+td.whDesc { padding-bottom: 6pt }
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+	background-color: #E0E0E0;
+}
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+  </style></head>
+<body>
+<h1>Cortex Microcontroller Software Interface Standard</h1>
+
+<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
+<p align="center">Version: 1.30 - 30. October 2009</p>
+
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
+                 Copyright © ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
+<ul>
+	<li>Version 1.00: initial release. </li>
+	<li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
+	<li>Version 1.02: added Cortex-M0. </li>
+	<li>Version 1.10: second review. </li>
+	<li>Version 1.20: third review. </li>
+	<li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
+	<li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
+	<li>Version 1.30: updated Device Support Packages.</li>
+</ul>
+
+<hr>
+
+<h2>Contents</h2>
+
+<ol>
+  <li class="LI2"><a href="#1">About</a></li>
+  <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
+  <li class="LI2"><a href="#3">CMSIS Files</a></li>
+  <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
+  <li class="LI2"><a href="#5">CMSIS Example</a></li>
+</ol>
+
+<h2><a name="1"></a>About</h2>
+
+<p>
+  The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
+  that are faced when software components are deployed to physical microcontroller devices based on a
+  Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M 
+  processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
+  with various silicon and software vendors and provides a common approach to interface to peripherals, 
+  real-time operating systems, and middleware components.
+</p>
+
+<p>ARM provides as part of the CMSIS the following software layers that are
+available for various compiler implementations:</p>
+<ul>
+  <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, 
+    address definitions and helper functions to
+    access core registers and peripherals. It defines also a device
+    independent interface for RTOS Kernels that includes debug channel
+    definitions.</li>
+</ul>
+
+<p>These software layers are expanded by Silicon partners with:</p>
+<ul>
+  <li><strong>Device Peripheral Access Layer</strong>: provides definitions
+    for all device peripherals</li>
+  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
+    additional helper functions for peripherals</li>
+</ul>
+
+<p>CMSIS defines for a Cortex-M Microcontroller System:</p>
+<ul>
+  <li style="text-align: left;">A common way to access peripheral registers
+    and a common way to define exception vectors.</li>
+  <li style="text-align: left;">The register names of the <strong>Core
+    Peripherals</strong> and<strong> </strong>the names of the <strong>Core
+    Exception Vectors</strong>.</li>
+  <li>An device independent interface for RTOS Kernels including a debug
+    channel.</li>
+</ul>
+
+<p>
+  By using CMSIS compliant software components, the user can easier re-use template code. 
+  CMSIS is intended to enable the combination of software components from multiple middleware vendors.
+</p>
+
+<h2><a name="2"></a>Coding Rules and Conventions</h2>
+
+<p>
+  The following section describes the coding rules and conventions used in the CMSIS 
+  implementation. It contains also information about data types and version number information.
+</p>
+
+<h3>Essentials</h3>
+<ul>
+  <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, 
+      there are disable and enable sequences for PC-LINT inserted.</li>
+  <li>ANSI standard data types defined in the ANSI C header file
+    <strong>&lt;stdint.h&gt;</strong> are used.</li>
+  <li>#define constants that include expressions must be enclosed by
+    parenthesis.</li>
+  <li>Variables and parameters have a complete data type.</li>
+  <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
+    re-entrant.</li>
+  <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
+    (which means that wait/query loops are done at other software layers).</li>
+  <li>For each exception/interrupt there is definition for:
+  <ul>
+    <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
+	(for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
+    <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
+    <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
+  </ul></li>
+</ul>
+
+<h3>Recommendations</h3>
+
+<p>The CMSIS recommends the following conventions for identifiers.</p>
+<ul>
+  <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
+  <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
+  <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
+  <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
+</ul>
+
+<b>Comments</b>
+
+<ul>
+  <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style 
+  (<em>// comment</em>). It is assumed that the programming tools support today 
+	consistently the C++ comment style.</li>
+  <li><strong>Function Comments</strong> provide for each function the following information:
+  <ul>
+    <li>one-line brief function overview.</li>
+    <li>detailed parameter explanation.</li>
+    <li>detailed information about return values.</li>
+    <li>detailed description of the actual function.</li>
+  </ul>
+  <p><b>Doxygen Example:</b></p>
+  <pre>
+/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */</pre>
+  </li>
+</ul>
+
+<h3>Data Types and IO Type Qualifiers</h3>
+
+<p>
+  The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
+  <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
+  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of 
+  debug information of peripheral registers.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
+      <th class="kt">#define</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__I</td>
+      <td class="kt">volatile const</td>
+      <td class="kt">Read access only</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__O</td>
+      <td class="kt">volatile</td>
+      <td class="kt">Write access only</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__IO</td>
+      <td class="kt">volatile</td>
+      <td class="kt">Read and write access</td>
+    </tr>
+  </tbody>
+</table>
+
+<h3>CMSIS Version Number</h3>
+<p>
+  File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
+</p>
+
+<pre>
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>
+
+<p>
+  File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
+</p>
+
+<pre>
+#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x30)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>
+
+
+<h3>CMSIS Cortex Core</h3>
+<p>
+  File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
+</p>
+
+<pre>
+#define __CORTEX_M                (0x03)</pre>
+
+<p>
+  File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
+</p>
+
+<pre>
+#define __CORTEX_M                (0x00)</pre>
+
+
+<h2><a name="3"></a>CMSIS Files</h2>
+<p>
+  This section describes the Files provided in context with the CMSIS to access the Cortex-M
+  hardware and peripherals.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">File</th>
+      <th class="kt">Provider</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap"><i>device.h</i></td>
+      <td class="kt">Device specific (provided by silicon partner)</td>
+      <td class="kt">Defines the peripherals for the actual device. The file may use 
+        several other include files to define the peripherals of the actual device.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">core_cm0.h</td>
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+      <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">core_cm3.h</td>
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+      <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">core_cm0.c</td>
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+      <td class="kt">Provides helper functions that access core registers.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">core_cm3.c</td>
+      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+      <td class="kt">Provides helper functions that access core registers.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
+      <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
+      <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">system<i>_device</i></td>
+      <td class="kt">ARM (adapted by silicon partner)</td>
+      <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes 
+        typically the oscillator (PLL) that is part of the microcontroller device</td>
+    </tr>
+  </tbody>
+</table>
+
+<h3><em>device.h</em></h3>
+
+<p>
+  The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the 
+  <u><strong>central include file</strong></u> that the application programmer is using in 
+  the C source code. This file contains:
+</p>
+<ul>
+  <li>
+	<p><strong>Interrupt Number Definition</strong>: provides interrupt numbers 
+	(IRQn) for all core and device specific exceptions and interrupts.</p>
+	</li>
+	<li>
+	<p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the 
+	actual configuration of the Cortex-M processor that is part of the actual 
+	device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that 
+	implements access to processor registers and core peripherals. </p>
+	</li>
+	<li>
+	<p><strong>Device Peripheral Access Layer</strong>: provides definitions
+    for all device peripherals. It contains all data structures and the address 
+	mapping for the device specific peripherals. </p>
+	</li>
+  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
+    additional helper functions for peripherals that are useful for programming 
+	of these peripherals. Access Functions may be provided as inline functions 
+	or can be extern references to a device specific library provided by the 
+	silicon vendor.</li>
+</ul>
+
+
+<h4><strong>Interrupt Number Definition</strong></h4>
+
+<p>To access the device specific interrupts the device.h file defines IRQn 
+numbers for the complete device using a enum typedef as shown below:</p>
+<pre>
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!&lt; 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!&lt; 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!&lt; 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!&lt; 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!&lt; 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!&lt; 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!&lt; 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!&lt; 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!&lt; Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!&lt; PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;</pre>
+
+
+<h4>Configuration for core_cm0.h / core_cm3.h</h4>
+<p>
+  The Cortex-M core configuration options which are defined for each device implementation. Some 
+  configuration options are reflected in the CMSIS layer using the #define settings described below.
+</p>
+<p>
+  To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
+  Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be 
+  defined before <strong>#include &lt;core_cm0.h&gt;</strong> / <strong>#include &lt;core_cm3.h&gt;</strong>
+  preprocessor command.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">#define</th>
+      <th class="kt" nowrap="nowrap">File</th>
+      <th class="kt" nowrap="nowrap">Value</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
+      <td class="kt">core_cm0.h</td>
+      <td class="kt" nowrap="nowrap">(2)</td>
+      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
+      <td class="kt">core_cm3.h</td>
+      <td class="kt" nowrap="nowrap">(2 ... 8)</td>
+      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
+      <td class="kt">core_cm0.h, core_cm3.h</td>
+      <td class="kt" nowrap="nowrap">(0, 1)</td>
+      <td class="kt">Defines if an MPU is present or not</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
+      <td class="kt">core_cm0.h, core_cm3.h</td>
+      <td class="kt" nowrap="nowrap">(1)</td>
+      <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function 
+		in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> 
+		file must contain a vendor specific implementation of this function.</td>
+    </tr>
+  </tbody>
+</table>
+
+
+<h4>Device Peripheral Access Layer</h4>
+<p>
+  Each peripheral uses a prefix which consists of <strong>&lt;device abbreviation&gt;_</strong> 
+  and <strong>&lt;peripheral name&gt;_</strong> to identify peripheral registers that access this 
+  specific peripheral. The intention of this is to avoid name collisions caused
+  due to short names. If more than one peripheral of the same type exists, 
+  identifiers have a postfix (digit or letter). For example:
+</p>
+<ul>
+	<li>&lt;device abbreviation&gt;_UART_Type: defines the generic register layout for all UART channels in a device.
+      <pre>
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000   Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000   Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000   Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004   Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004   Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008   Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008   FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C   Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014   Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C   Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020   Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024   IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028   Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030   Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058   FIFO Level Register         */
+} LPC_UART_TypeDef;</pre>
+  </li>
+	<li>&lt;device abbreviation&gt;_UART1: is a pointer to a register structure that refers to a specific UART. 
+      For example UART1-&gt;DR is the data register of UART1.
+      <pre>
+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</pre>
+  </li>
+</ul>
+
+<h5>Minimal Requiements</h5>
+<p>
+  To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> 
+  and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
+</p>
+<ul>
+  <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
+      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
+      the peripheral registers. For example:
+      <pre>
+typedef struct {
+  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
+  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
+  __IO uint32_t VAL;       /* SysTick Current Value Register      */
+  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
+  } SysTick_Type;</pre>
+  </li>
+
+  <li>
+    <strong>Base Address</strong> for each peripheral (in case of multiple peripherals 
+    that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
+    <pre>
+#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */</pre>
+  </li>
+
+  <li>
+    <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use 
+    the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0, 
+    LPC_UART2). For Example:
+    <pre>
+#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */</pre>
+  </li>
+</ul>
+
+<p>
+  These definitions allow to access the peripheral registers from user code with simple assignments like:
+</p>
+<pre>SysTick-&gt;CTRL = 0;</pre>
+
+<h5>Optional Features</h5>
+<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
+<ul>
+	<li>
+    #define constants that simplify access to the peripheral registers. 
+	  These constant define bit-positions or other specific patterns are that required for the 
+    programming of the peripheral registers. The identifiers used start with 
+    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. 
+    It is recommended to use CAPITAL letters for such #define constants.
+  </li>
+	<li>
+    Functions that perform more complex functions with the peripheral (i.e. status query before 
+    a sending register is accessed). Again these function start with 
+    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. 
+  </li>
+</ul>
+
+<h3>core_cm0.h and core_cm0.c</h3>
+<p>
+  File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers 
+  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
+</p>
+<p>
+  File <b>core_cm0.c</b> defines several helper functions that access processor registers.
+</p>
+<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
+
+<h3>core_cm3.h and core_cm3.c</h3>
+<p>
+  File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers 
+  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
+</p>
+<p>
+  File <b>core_cm3.c</b> defines several helper functions that access processor registers.
+</p>
+<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
+
+<h3>startup_<em>device</em></h3>
+<p>
+  A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
+  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific 
+  interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function 
+  to an dummy handler. Therefore the interrupt handler can be directly used in application software 
+  without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
+</p>
+<p>
+  The following exception names are fixed and define the start of the vector table for a Cortex-M0:
+</p>
+<pre>
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler</pre>
+
+<p>
+  The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+</p>
+<pre>
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler</pre>
+
+<p>
+  In the following examples for device specific interrupts are shown:
+</p>
+<pre>
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper</pre>
+
+<p>
+  Device specific interrupts must have a dummy function that can be overwritten in user code. 
+  Below is an example for this dummy function.
+</p>
+<pre>
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP</pre>
+                
+<p>
+  The user application may simply define an interrupt handler function by using the handler name
+  as shown below.
+</p>
+<pre>
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}</pre>
+
+
+<h3><a name="4"></a>system_<em>device</em>.c</h3>
+<p>
+  A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by 
+  the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> 
+  this file must provide a device specific system configuration function and a global variable 
+  that contains the system frequency. It configures the device and initializes typically the 
+  oscillator (PLL) that is part of the microcontroller device.
+</p>
+<p>
+  The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
+  as a minimum requirement the SystemInit function as shown below.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt">Function Definition</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
+      <td class="kt">Setup the microcontroller system. Typically this function configures the 
+                     oscillator (PLL) that is part of the microcontroller device. For systems 
+                     with variable clock speed it also updates the variable SystemCoreClock.<br>
+                     SystemInit is called from startup<i>_device</i> file.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
+      <td class="kt">Updates the variable SystemCoreClock and must be called whenever the 
+                     core clock is changed during program execution. SystemCoreClockUpdate()
+                     evaluates the clock register settings and calculates the current core clock.
+</td>
+    </tr>
+  </tbody>
+</table>
+
+<p>
+  Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> 
+  is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt">Variable Definition</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
+      <td class="kt">Contains the system core clock (which is the system clock	frequency supplied 
+                     to the SysTick timer and the processor core clock). This variable can be 
+                     used by the user application to setup the SysTick timer or configure other 
+                     parameters. It may also be used by debugger to query the frequency of the 
+                     debug timer or configure the trace clock speed.<br>
+                     SystemCoreClock is initialized with a correct predefined value.<br><br>
+		                 The compiler must be configured to avoid the removal of this variable in 
+		                 case that the application program is not using it. It is important for 
+		                 debug systems that the variable is physically present in memory so that 
+		                 it can be examined to configure the debugger.</td>
+    </tr>
+  </tbody>
+</table>
+
+<p class="Note">Note</p>
+<ul>
+  <li><p>The above definitions are the minimum requirements for the file <strong>
+	system_</strong><em><strong>device</strong></em><strong>.c</strong>. This 
+	file may export more functions or variables that provide a more flexible 
+	configuration of the microcontroller system.</p>
+  </li>
+</ul>
+
+
+<h2>Core Peripheral Access Layer</h2>
+
+<h3>Cortex-M Core Register Access</h3>
+<p>
+  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
+  and provide access to Cortex-M core registers.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt">Function Definition</th>
+      <th class="kt">Core</th>
+      <th class="kt">Core Register</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">PRIMASK = 0</td>
+      <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE 
+		i</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">PRIMASK = 1</td>
+      <td class="kt">Global Interrupt disable (using the instruction <strong>
+		CPSID i</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">PRIMASK = value</td>
+      <td class="kt">Assign value to Priority Mask Register (using the instruction 
+		<strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">return PRIMASK</td>
+      <td class="kt">Return Priority Mask Register (using the instruction 
+		<strong>MRS</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">FAULTMASK = 0</td>
+      <td class="kt">Global Fault exception and Interrupt enable (using the 
+		instruction <strong>CPSIE 
+		f</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">FAULTMASK = 1</td>
+      <td class="kt">Global Fault exception and Interrupt disable (using the 
+		instruction <strong>CPSID f</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
+      <td class="kt">M3</td>
+      <td class="kt">FAULTMASK = value</td>
+      <td class="kt">Assign value to Fault Mask Register (using the instruction 
+		<strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">return FAULTMASK</td>
+      <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
+      <td class="kt">M3</td>
+      <td class="kt">BASEPRI = value</td>
+      <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">return BASEPRI</td>
+      <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">CONTROL = value</td>
+      <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">return CONTROL</td>
+      <td class="kt">Return Control Register Value (using the instruction
+		<strong>MRS</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">PSP = TopOfProcStack</td>
+      <td class="kt">Set Process Stack Pointer value (using the instruction
+		<strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">return PSP</td>
+      <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">MSP = TopOfMainStack</td>
+      <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">return MSP</td>
+      <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
+    </tr>
+  </tbody>
+</table>
+
+<h3>Cortex-M Instruction Access</h3>
+<p>
+  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
+  generate specific Cortex-M instructions. The functions are implemented in the file 
+  <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt">Name</th>
+      <th class="kt">Core</th>
+      <th class="kt">Generated CPU Instruction</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __NOP (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">NOP</td>
+      <td class="kt">No Operation</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __WFI (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">WFI</td>
+      <td class="kt">Wait for Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __WFE (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">WFE</td>
+      <td class="kt">Wait for Event</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __SEV (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">SEV</td>
+      <td class="kt">Set Event</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __ISB (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">ISB</td>
+      <td class="kt">Instruction Synchronization Barrier</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __DSB (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">DSB</td>
+      <td class="kt">Data Synchronization Barrier</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void __DMB (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">DMB</td>
+      <td class="kt">Data Memory Barrier</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">REV</td>
+      <td class="kt">Reverse byte order in integer value.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">REV16</td>
+      <td class="kt">Reverse byte order in unsigned short value. </td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">REVSH</td>
+      <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
+      <td class="kt">M3</td>
+      <td class="kt">RBIT</td>
+      <td class="kt">Reverse bit order of value</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">LDREXB</td>
+      <td class="kt">Load exclusive byte</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">LDREXH</td>
+      <td class="kt">Load exclusive half-word</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">LDREXW</td>
+      <td class="kt">Load exclusive word</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">STREXB</td>
+      <td class="kt">Store exclusive byte</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">STREXH</td>
+      <td class="kt">Store exclusive half-word</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
+      <td class="kt">M3</td>
+      <td class="kt">STREXW</td>
+      <td class="kt">Store exclusive word</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void  __CLREX (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">CLREX</td>
+      <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
+    </tr>
+  </tbody>
+</table>
+
+
+<h3>NVIC Access Functions</h3>
+<p>
+  The CMSIS provides access to the NVIC via the register interface structure and several helper
+  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to 
+  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative 
+  IRQn values are used for processor core exceptions.
+</p>
+<p>
+  For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides 
+  the following enum names.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
+      <th class="kt">Core</th>
+      <th class="kt">IRQn</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">-14</td>
+      <td class="kt">Cortex-M Non Maskable Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">-13</td>
+      <td class="kt">Cortex-M Hard Fault Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
+      <td class="kt">M3</td>
+      <td class="kt">-12</td>
+      <td class="kt">Cortex-M Memory Management Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
+      <td class="kt">M3</td>
+      <td class="kt">-11</td>
+      <td class="kt">Cortex-M Bus Fault Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
+      <td class="kt">M3</td>
+      <td class="kt">-10</td>
+      <td class="kt">Cortex-M Usage Fault Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">-5</td>
+      <td class="kt">Cortex-M SV Call Interrupt </td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
+      <td class="kt">M3</td>
+      <td class="kt">-4</td>
+      <td class="kt">Cortex-M Debug Monitor Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">-2</td>
+      <td class="kt">Cortex-M Pend SV Interrupt</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">-1</td>
+      <td class="kt">Cortex-M System Tick Interrupt</td>
+    </tr>
+  </tbody>
+</table>
+
+<p>The following functions simplify the setup of the NVIC.
+The functions are defined as <strong>static inline</strong>.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">Name</th>
+      <th class="kt">Core</th>
+      <th class="kt">Parameter</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
+      <td class="kt">M3</td>
+      <td class="kt">Priority Grouping Value</td>
+      <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
+      <td class="kt">M3</td>
+      <td class="kt">(void)</td>
+      <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Enable IRQn</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Disable IRQn</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Return 1 if IRQn is pending else 0</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Set IRQn Pending</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Clear IRQn Pending Status</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
+      <td class="kt">M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Return 1 if IRQn is active else 0</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number, Priority</td>
+      <td class="kt">Set Priority for IRQn<br>
+                     (not threadsafe for Cortex-M0)</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">IRQ Number</td>
+      <td class="kt">Get Priority for IRQn</td>
+    </tr>
+    <tr>
+<!--      <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
+      <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
+      <td class="kt">M3</td>
+      <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>
+      <td class="kt">Encode priority for given group, preemptive and sub priority</td>
+    </tr>
+<!--      <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
+      <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
+      <td class="kt">M3</td>
+      <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>
+      <td class="kt">Deccode given priority to group, preemptive and sub priority</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
+      <td class="kt">M0, M3</td>
+      <td class="kt">(void)</td>
+      <td class="kt">Resets the System</td>
+    </tr>
+  </tbody>
+</table>
+<p class="Note">Note</p>
+<ul>
+  <li><p>The processor exceptions have negative enum values. Device specific interrupts 
+	       have positive enum values and start with 0. The values are defined in
+         <b><em>device.h</em></b> file.
+      </p>
+  </li>
+  <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
+         used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
+         depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
+      </p>
+  </li>
+</ul>
+
+
+<h3>SysTick Configuration Function</h3>
+
+<p>The following function is used to configure the SysTick timer and start the 
+SysTick interrupt.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">Name</th>
+      <th class="kt">Parameter</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig 
+		(uint32_t ticks)</span></td>
+      <td class="kt">ticks is SysTick counter reload value</td>
+      <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this 
+		call the SysTick timer creates interrupts with the specified time 
+		interval. <br>
+		<br>
+		Return: 0 when successful, 1 on failure.<br>
+		</td>
+    </tr>
+  </tbody>
+</table>
+
+
+<h3>Cortex-M3 ITM Debug Access</h3>
+
+<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that 
+provides together with the Serial Viewer Output trace capabilities for the 
+microcontroller system. The ITM has 32 communication channels; two ITM 
+communication channels are used by CMSIS to output the following information:</p>
+<ul>
+	<li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function 
+	which can be used for printf-style output via the debug interface.</li>
+	<li>ITM Channel 31: is reserved for the RTOS kernel and can be used for 
+	kernel awareness debugging.</li>
+</ul>
+<p class="Note">Note</p>
+<ul>
+  <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels 
+	may use the Privileged level for program execution. ITM 
+	channels have 4 groups with 8 channels each, whereby each group can be 
+	configured for access rights in the Unprivileged level. The ITM channel 0 
+	may be therefore enabled for the user task whereas ITM channel 31 may be 
+	accessible only in Privileged level from the RTOS kernel itself.</p>
+  </li>
+</ul>
+
+<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the 
+table below.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">Name</th>
+      <th class="kt">Parameter</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
+      <td class="kt">character to output</td>
+      <td class="kt">The function outputs a character via the ITM channel 0. The 
+		                 function returns when no debugger is connected that has booked the 
+		                 output. It is blocking when a debugger is connected, but the 
+		                 previous character send is not transmitted. <br><br>
+		                 Return: the input character 'chr'.</td>
+    </tr>
+  </tbody>
+</table>
+
+<p>
+  Example for the usage of the ITM Channel 31 for RTOS Kernels:
+</p>
+<pre>
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;
+  (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;
+  (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {
+    // transmit trace data
+    while (ITM-&gt;PORT31_U32 == 0);
+    ITM-&gt;PORT[31].u8 = task_id;      // id of next task
+    while (ITM-&gt;PORT[31].u32 == 0);
+    ITM-&gt;PORT[31].u32 = task_status; // status information
+  }</pre>
+
+
+<h3>Cortex-M3 additional Debug Access</h3>
+
+<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
+Data can be transmitted via a certain global buffer variable towards the target system.</p>
+
+<p>The buffer variable and the prototypes of the additional functions are shown in the 
+table below.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+  <tbody>
+    <tr>
+      <th class="kt" nowrap="nowrap">Name</th>
+      <th class="kt">Parameter</th>
+      <th class="kt">Description</th>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
+      <td class="kt"> </td>
+      <td class="kt">Buffer to transmit data towards debug system. <br><br>
+		                 Value 0x5AA55AA5 indicates that buffer is empty.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
+      <td class="kt">none</td>
+      <td class="kt">The nonblocking functions returns the character stored in 
+                     ITM_RxBuffer. <br><br>
+		                 Return: -1 indicates that no character was received.</td>
+    </tr>
+    <tr>
+      <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
+      <td class="kt">none</td>
+      <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
+		                 Return: 1 indicates that a character is available, 0 indicates that
+                     no character is available.</td>
+    </tr>
+  </tbody>
+</table>
+
+
+<h2><a name="5"></a>CMSIS Example</h2>
+<p>
+  The following section shows a typical example for using the CMSIS layer in user applications.
+  The example is based on a STM32F10x Device.
+</p>
+<pre>
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) &lt; dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}</pre>
+
+
+</body></html>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc
index b6b8ace..b6b8ace 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/License.doc
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..c465d33
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in independent or
+                                               dual mode. 
+                                               This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannels) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode 
+  * @{
+  */
+
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                    ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig               ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl            ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl            ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                       ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                         ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                        ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                        ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                         ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_Mode_RegInjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+                           ((MODE) == ADC_Mode_InjecSimult) || \
+                           ((MODE) == ADC_Mode_RegSimult) || \
+                           ((MODE) == ADC_Mode_FastInterl) || \
+                           ((MODE) == ADC_Mode_SlowInterl) || \
+                           ((MODE) == ADC_Mode_AlterTrig))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO    ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                   ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                   ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_JEOC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..275c5e1
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level 
+  * @{
+  */
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
+  * @{
+  */
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register 
+  * @{
+  */
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
index d185aa2..d185aa2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
new file mode 100644
index 0000000..7ce6896
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+  
+
+/** @defgroup CEC_Exported_Types
+  * @{
+  */
+   
+/** 
+  * @brief  CEC Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
+                               This parameter can be a value of @ref CEC_BitTiming_Mode */
+  uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
+                               This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup CEC_BitTiming_Mode 
+  * @{
+  */ 
+#define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+                                            ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitPeriod_Mode 
+  * @{
+  */ 
+#define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+                                            ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_interrupts_definition 
+  * @{
+  */ 
+#define CEC_IT_TERR                              CEC_CSR_TERR
+#define CEC_IT_TBTRF                             CEC_CSR_TBTRF
+#define CEC_IT_RERR                              CEC_CSR_RERR
+#define CEC_IT_RBTF                              CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Own_Address 
+  * @{
+  */ 
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Prescaler 
+  * @{
+  */ 
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_flags_definition 
+  * @{
+  */
+   
+/** 
+  * @brief  ESR register flags  
+  */ 
+#define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
+
+/** 
+  * @brief  CSR register flags  
+  */ 
+#define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
+#define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+                               
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Exported_Macros
+  * @{
+  */
+ 
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions
+  * @{
+  */ 
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
index 3362fca..3362fca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
new file mode 100644
index 0000000..174773c
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dac.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in High-density devices*/
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                       only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 
+                                                                       only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)  || defined (STM32F10X_HD_VL)
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */ 
+  
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions
+  * @{
+  */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+#endif
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
index 14275fe..14275fe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..bb9d7f6
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
@@ -0,0 +1,184 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_exti.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+                                                   Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                            ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                            ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                            ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                            ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                            ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                            ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                            ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                            ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                            ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions
+  * @{
+  */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
new file mode 100644
index 0000000..63720de
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
@@ -0,0 +1,426 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_flash.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  FLASH Status  
+  */
+
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Flash_Latency 
+  * @{
+  */
+
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2))
+/**
+  * @}
+  */
+
+/** @defgroup Half_Cycle_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+                                               ((STATE) == FLASH_HalfCycleAccess_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+                                              ((STATE) == FLASH_PrefetchBuffer_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127      ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+#define FLASH_WRProt_Pages62to511      ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
+
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+#ifdef STM32F10X_XL
+/**
+  * @}
+  */
+/** @defgroup FLASH_Boot
+  * @{
+  */
+#define FLASH_BOOT_Bank1  ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_Bank2  ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank 2 or Bank 1,
+                                                  depending on the activation of the bank */
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
+#endif
+/**
+  * @}
+  */
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_IT_BANK2_ERROR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
+#define FLASH_IT_BANK2_EOP                   ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
+
+#define FLASH_IT_BANK1_ERROR                 FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP                   FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#else
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_FLAG_BANK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BANK2_EOP                 ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BANK2_PGERR               ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BANK2_WRPRTERR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR)|| \
+                                  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
+#else
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+								  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+/*------------ Functions used for all STM32F10x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/*------------ New function used for all STM32F10x devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef STM32F10X_XL
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseAllBank2Pages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
index dd28da8..dd28da8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
new file mode 100644
index 0000000..60e4b14
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
@@ -0,0 +1,684 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_i2c.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2))
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_NCAK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/*========================================
+     
+                     I2C Master Events (Events grouped in order of communication)
+                                                        ==========================================*/
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *  managed before the current byte end of transfer, then user may check on EV7 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *  In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+     
+                     I2C Slave Events (Events grouped in order of communication)
+                                                        ==========================================*/
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *  managed before the current byte end of transfer, then user may check on EV2 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  * In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*===========================      End of Events Description           ==========================================*/
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *                       
+ ****************************************************************************************   
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *        
+ *  
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags 
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup 
+ *      activity since the events are fully described in the product reference manual 
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state. 
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *        
+ *        @note 
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ *            in order to determine which error occurred.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *            
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status 
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the limitations of I2C_GetFlagStatus() function (see below).
+ *         The returned value could be compared to events already defined in the 
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no 
+ *         other flags are set or just when the needed flags are set like 
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this 
+ *         function if user decides to check only regular communication flags (and 
+ *         ignores error flags).
+ *     
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of 
+ *     one single flag (ie. I2C_FLAG_RXNE ...). 
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events 
+ *          are monitored through multiple flags).
+ *     - Limitations: 
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one 
+ *          single event.
+ *            
+ */
+
+/**
+ * 
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/**
+ * 
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/**
+ * 
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_I2C_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..25b0bb5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
@@ -0,0 +1,140 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_iwdg.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions
+  * @{
+  */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..1c025e2
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
@@ -0,0 +1,156 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_pwr.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+  * @}
+  */
+
+/** @defgroup Regulator_state_is_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions
+  * @{
+  */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
index 1149c34..1149c34 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
new file mode 100644
index 0000000..fd8beb5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
@@ -0,0 +1,135 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rtc.h
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RTC_interrupts_define 
+  * @{
+  */
+
+#define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+                           ((IT) == RTC_IT_SEC))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_interrupts_flags 
+  * @{
+  */
+
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+                               ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+                               ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Exported_Functions
+  * @{
+  */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RTC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
index 81c058a..81c058a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
index 23cc26d..23cc26d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
index 162fa87..162fa87 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
index c0a5e11..c0a5e11 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
new file mode 100644
index 0000000..8155dc9
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
@@ -0,0 +1,1307 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the ADC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset           ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set              ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset            ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set               ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset             ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set             ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset           ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset             ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset           ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask              ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set                ((uint32_t)0x00000001)
+#define CR2_ADON_Reset              ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set                 ((uint32_t)0x00000100)
+#define CR2_DMA_Reset               ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set              ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set                 ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set             ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set             ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset           ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set     ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset   ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset           ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set            ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset          ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set            ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set   ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set             ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset           ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask              ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set                 ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask             ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set                ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set                 ((uint32_t)0x00300000)
+#define JSQR_JL_Reset               ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set               ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set               ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset                  ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS                  ((uint32_t)0x4001244C)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  if (ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+  else if (ADCx == ADC2)
+  {
+    /* Enable ADC2 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+    /* Release ADC2 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+  }
+  else
+  {
+    if (ADCx == ADC3)
+    {
+      /* Enable ADC3 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+      /* Release ADC3 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear DUALMOD and SCAN bits */
+  tmpreg1 &= CR1_CLEAR_Mask;
+  /* Configure ADCx: Dual mode and scan conversion mode */
+  /* Set DUALMOD bits according to ADC_Mode value */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN and EXTSEL bits */
+  tmpreg1 &= CR2_CLEAR_Mask;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= SQR1_CLEAR_Mask;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+  tmpreg1 |= (uint32_t)tmpreg2 << 20;
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= CR2_ADON_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= CR2_ADON_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 or 3 to select the ADC peripheral.
+  *   Note: ADC2 hasn't a DMA capability.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= CR2_DMA_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= CR2_DMA_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @param  NewState: new state of the specified ADC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Resets the selected ADC calibration registers.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Resets the selected ADC calibration registers */  
+  ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC reset calibration registers status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC reset calibration registers (SET or RESET).
+  */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Starts the selected ADC calibration process.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC calibration process */  
+  ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC calibration status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC calibration (SET or RESET).
+  */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of CAL bit */
+  if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC software start conversion .
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event and start the selected
+       ADC conversion */
+    ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event and stop the selected
+       ADC conversion */
+    ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel
+  *         count value. This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_Reset;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on regular group channel.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= CR1_DISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= CR1_DISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADCx conversion through external trigger.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CR2 |= CR2_EXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CR2 &= CR2_EXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @brief  Returns the last ADC1 and ADC2 conversion result data in dual mode.
+  * @retval The Data conversion value.
+  */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+  /* Return the dual mode conversion value */
+  return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= CR1_JAUTO_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= CR1_JAUTO_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= CR1_JDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= CR1_JDISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+  *                                                       capture compare4 event selected (for ADC1 and ADC2)                       
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)                        
+  *     @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+  *                                          by external trigger (for ADC1, ADC2 and ADC3)
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_Reset;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADCx injected channels conversion through
+  *         external trigger
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of
+  *         injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CR2 |= CR2_JEXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC start of the injected 
+  *         channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion for injected group on external event and start the selected
+       ADC injected conversion */
+    ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event for injected group and stop the selected
+       ADC injected conversion */
+    ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JL_Set)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Length: The sequencer length. 
+  *   This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequnence lenght JL bits */
+  tmpreg1 &= JSQR_JL_Reset;
+  /* Set the injected sequnence lenght JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));  
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDR_Offset;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp);   
+}
+
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+  *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+  *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on  all regular channel
+  *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on  all injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= CR1_AWDMode_Reset;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *   This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_Reset;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 |= CR2_TSVREFE_Set;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 &= CR2_TSVREFE_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = ADC_IT >> 8;
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
index 997eecc..997eecc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
index 4dc615f..4dc615f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
new file mode 100644
index 0000000..6501728
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
new file mode 100644
index 0000000..1cfc71d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
@@ -0,0 +1,571 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dac.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the DAC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/** @defgroup DAC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Defines
+  * @{
+  */
+
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified 
+  *         parameters in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+  *        contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
+  }
+}
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                      
+  * @param  NewState: new state of the specified DAC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+#endif
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *   triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Wave_Noise: noise wave generation
+  *     @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel
+  *   DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *   holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *   holding register.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: thee selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *   This parameter can be only of the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                                                 
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channelx's pending flags.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *   This parameter can be of the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                       
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channelx's interrupt pending bits.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
index 96a8fde..96a8fde 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
index cdff9e9..cdff9e9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
new file mode 100644
index 0000000..51669ee
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
@@ -0,0 +1,866 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_fsmc.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    11-March-2011
+  * @brief   This file provides all the FSMC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */ 
+
+/** @defgroup FSMC_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Defines
+  * @{
+  */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set                       ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set                      ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set                       ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set                       ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *         reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval None
+  */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  
+  /* FSMC_Bank1_NORSRAM1 */
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+  {
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+  else
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
+
+/**
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
+  * @retval None
+  */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Set the FSMC_Bank2 registers to their reset values */
+    FSMC_Bank2->PCR2 = 0x00000018;
+    FSMC_Bank2->SR2 = 0x00000040;
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FSMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FSMC_Bank3 registers to their reset values */
+    FSMC_Bank3->PCR3 = 0x00000018;
+    FSMC_Bank3->SR3 = 0x00000040;
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
+  }  
+}
+
+/**
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+  * @param  None                       
+  * @retval None
+  */
+void FSMC_PCCARDDeInit(void)
+{
+  /* Set the FSMC_Bank4 registers to their reset values */
+  FSMC_Bank4->PCR4 = 0x00000018; 
+  FSMC_Bank4->SR4 = 0x00000000;	
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
+  *         parameters in the FSMC_NORSRAMInitStruct.
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+  *         structure that contains the configuration information for 
+  *        the FSMC NOR/SRAM specified Banks.                       
+  * @retval None
+  */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+  {
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+  }
+  
+  /* Bank1 NOR/SRAM timing register configuration */
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+  {
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+  }
+  else
+  {
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC NAND Banks according to the specified 
+  *         parameters in the FSMC_NANDInitStruct.
+  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef 
+  *         structure that contains the configuration information for the FSMC 
+  *         NAND specified Banks.                       
+  * @retval None
+  */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
+    
+  /* Check the parameters */
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+            PCR_MemoryType_NAND |
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NANDInitStruct->FSMC_ECC |
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+  
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* FSMC_Bank2_NAND registers configuration */
+    FSMC_Bank2->PCR2 = tmppcr;
+    FSMC_Bank2->PMEM2 = tmppmem;
+    FSMC_Bank2->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* FSMC_Bank3_NAND registers configuration */
+    FSMC_Bank3->PCR3 = tmppcr;
+    FSMC_Bank3->PMEM3 = tmppmem;
+    FSMC_Bank3->PATT3 = tmppatt;
+  }
+}
+
+/**
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified 
+  *         parameters in the FSMC_PCCARDInitStruct.
+  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+  *         structure that contains the configuration information for the FSMC 
+  *         PCCARD Bank.                       
+  * @retval None
+  */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+ 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+                     FSMC_MemoryDataWidth_16b |  
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
+            
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
+}
+
+/**
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
+  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{ 
+  /* Reset NAND Init structure parameters values */
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
+}
+
+/**
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
+  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param  NewState: new state of the PCCARD Memory Bank.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the FSMC NAND ECC feature.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC NAND ECC feature.  
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @retval The Error Correction Code (ECC) value.
+  */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Get the ECCR2 register value */
+    eccval = FSMC_Bank2->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    eccval = FSMC_Bank3->ECCR3;
+  }
+  /* Return the error correction code value */
+  return(eccval);
+}
+
+/**
+  * @brief  Enables or disables the specified FSMC interrupts.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @param  NewState: new state of the specified FSMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));	
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->SR2 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 |= FSMC_IT;    
+    }
+  }
+  else
+  {
+    /* Disable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC flag is set or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
+  * @retval The new state of FSMC_FLAG (SET or RESET).
+  */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  /* Get the flag status */
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FSMC's pending flags.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+  *     @arg FSMC_FLAG_Level: Level detection Flag.
+  *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+  * @retval None
+  */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
+  * @retval The new state of FSMC_IT (SET or RESET).
+  */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  itstatus = tmpsr & FSMC_IT;
+  
+  itenable = tmpsr & (FSMC_IT >> 3);
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FSMC's interrupt pending bits.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *     @arg FSMC_IT_Level: Level edge detection interrupt.
+  *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @retval None
+  */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
index 457ff11..457ff11 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
index 4ea321c..4ea321c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
index c7cbf7e..c7cbf7e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
index a5a5c57..a5a5c57 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
index f05aef5..f05aef5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
index bfb4dd1..bfb4dd1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
index e794eae..e794eae 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
index 4a901e4..4a901e4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
index fe7d71e..fe7d71e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/readme.txt
index fdf3f25..36e0386 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page FSMC_NOR FSMC NOR example
+  @page ADC_3ADCs_DMA 3 ADCs DMA example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NOR/readme.txt 
+  * @file    ADC/3ADCs_DMA/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the FSMC NOR example.
+  * @brief   Description of the 3ADCs DMA example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,27 +20,50 @@
 
 @par Example Description 
 
-This example provides a basic example of how to use the FSMC firmware library and
-an associate driver to perform erase/read/write operations on the M29W128FL,
-M29W128GL or S29GL128P NOR memories mounted on the STM3210E-EVAL board.
+This example describes how to use the 3 ADCs in independent conversions. 
+Two of them; ADC1 and ADC3 are transferring continuously converted data using DMA
+while ADC2 converted data are stored using End of conversion interrupt.
+
+ADC1 is configured to convert continuously ADC channel14. Each time an end of
+conversion occurs the DMA1 transfers, in circular mode, the converted data from 
+ADC1 DR register to the ADC1_ConvertedValue variable.
+
+ADC2 is configured to convert continuously ADC channel13. Each time an end of
+conversion occurs an end of conversion interrupt is generated and inside the
+interrupt routine the converted data are read from ADC2 DR register and stored
+into the ADC2_ConvertedValue variable.
+
+ADC3 is configured to convert continuously ADC channel12. Each time an end of
+conversion occurs the DMA2 transfers, in circular mode, the converted data from
+ADC3 DR register to the ADC3_ConvertedValue variable.
+
+The ADCs clocks are set to 14 MHz.
+
+The result of ADC1, ADC2 and ADC3 conversion is monitored through the three
+variables: ADC1ConvertedValue, ADC2ConvertedValue and ADC3ConvertedValue.
 
 @par Directory contents 
 
-  - FSMC/NOR/stm32f10x_conf.h    Library Configuration file
-  - FSMC/NOR/stm32f10x_it.c      Interrupt handlers
-  - FSMC/NOR/stm32f10x_it.h      Header for stm32f10x_it.c
-  - FSMC/NOR/main.c              Main program
-  - FSMC/NOR/system_stm32f10x.c  STM32F10x system source file  
+  - ADC/3ADCs_DMA/stm32f10x_conf.h    Library Configuration file
+  - ADC/3ADCs_DMA/stm32f10x_it.c      Interrupt handlers
+  - ADC/3ADCs_DMA/stm32f10x_it.h      Interrupt handlers header file
+  - ADC/3ADCs_DMA/system_stm32f10x.c  STM32F10x system source file
+  - ADC/3ADCs_DMA/main.c              Main program
 
 @par Hardware and Software environment 
 
   - This example runs only on STM32F10x High-Density and XL-Density Devices.
   
   - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-    
+    and XL-Density) evaluation board and can be easily tailored to any other 
+    supported device and development board.
+
+  - STM3210E-EVAL Set-up 
+    - Connect a variable power supply 0-3.3V to ADC3 Channel12 mapped on pin PC.02
+    - Connect a variable power supply 0-3.3V to ADC2 Channel13 mapped on pin PC.03
+    - Connect a variable power supply 0-3.3V to ADC1 Channel14 mapped on pin PC.04
+      (potentiometer RV1 on STM3210E-EVAL board)
+      
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
@@ -60,7 +83,7 @@ In order to make the program work, you must do the following :
  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
    microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
+   the Flash memory density ranges between 256 and 512 Kbytes.  
  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
    the Flash memory density ranges between 256 and 512 Kbytes.
  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h
index 02db464..02db464 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
index 3dd4e41..3dd4e41 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h
index fc8479d..fc8479d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
index f41af14..f41af14 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/3ADCs_DMA/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
index bc9bd02..bc9bd02 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt
index 19d9a7d..19d9a7d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h
index 0f04fd0..6fa8d72 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CAN/DualCAN/stm32f10x_conf.h 
+  * @file    ADC/ADC1_DMA/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c
index c2c3659..c2c3659 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c
index bc2b6ee..dc60ca0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/main.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CEC/DataExchangeInterrupt/main.c 
+  * @file    ADC/AnalogWatchdog/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -27,35 +27,25 @@
   * @{
   */
 
-/** @addtogroup CEC_DataExchangeInterrupt
+/** @addtogroup ADC_AnalogWatchdog
   * @{
-  */  
-
+  */ 
 
 /* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-CEC_InitTypeDef CEC_InitStructure;
-
-uint8_t ByteNumber = 10;
-volatile TestStatus TransferStatus = FAILED;
-extern uint8_t TransmitBuffer[10];
-extern uint8_t ReceiveBuffer[10];
-extern __IO uint8_t ReceivedFrame;
-
+ADC_InitTypeDef  ADC_InitStructure;
+    
 /* Private function prototypes -----------------------------------------------*/
 void RCC_Configuration(void);
-void NVIC_Configuration(void);
 void GPIO_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-  
+void NVIC_Configuration(void);
+
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  Main program
+  * @brief   Main program
   * @param  None
   * @retval None
   */
@@ -68,57 +58,57 @@ int main(void)
        system_stm32f10x.c file
      */     
        
-  /* RCC configuration */
+  /* System clocks configuration ---------------------------------------------*/
   RCC_Configuration();
 
-  /* NVIC configuration */
+  /* NVIC configuration ------------------------------------------------------*/
   NVIC_Configuration();
 
-  /* GPIO configuration */
+  /* GPIO configuration ------------------------------------------------------*/
   GPIO_Configuration();
 
-  /* Configure the CEC peripheral */
-  CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
-  CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
-  CEC_Init(&CEC_InitStructure);
+  /* Configure LED GPIO Pin ------------------------------------------------- */
+  STM_EVAL_LEDInit(LED1);
 
-  /* Set Prescaler value for APB1 clock PCLK1 = 24MHz */ 
-  CEC_SetPrescaler(0x4AF);
+  /* ADC1 Configuration ------------------------------------------------------*/
+  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
+  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
+  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
+  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_NbrOfChannel = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
 
-  /* Set the CEC initiator address */
-  CEC_OwnAddressConfig(MY_DEVICE_ADDRESS);
-  
-  /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
-  CEC_ITConfig(ENABLE);
+  /* ADC1 regular channel14 configuration */ 
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_13Cycles5);
 
-  /* Enable CEC */
-  CEC_Cmd(ENABLE);
+  /* Configure high and low analog watchdog thresholds */
+  ADC_AnalogWatchdogThresholdsConfig(ADC1, 0x0B00, 0x0300);
+  /* Configure channel14 as the single analog watchdog guarded channel */
+  ADC_AnalogWatchdogSingleChannelConfig(ADC1, ADC_Channel_14);
+  /* Enable analog watchdog on one regular channel */
+  ADC_AnalogWatchdogCmd(ADC1, ADC_AnalogWatchdog_SingleRegEnable);
 
-  /* If a frame has been received */
-  while(ReceivedFrame == 0)
-  {
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus = Buffercmp(TransmitBuffer, ReceiveBuffer, ByteNumber);
-  /* TransferStatus = PASSED, if the data transmitted from CEC Device1 and  
-     received by CEC Device2 are the same */
-  /* TransferStatus = FAILED, if the data transmitted from CEC Device1 and 
-     received by CEC Device2 are different */
- 
-  if (TransferStatus == PASSED)
-  { 
-    /* OK */
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  { 
-    /* KO */
-    /* Turn on LED2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-  while(1)
+  /* Enable AWD interrupt */
+  ADC_ITConfig(ADC1, ADC_IT_AWD, ENABLE);
+
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+
+  /* Enable ADC1 reset calibration register */   
+  ADC_ResetCalibration(ADC1);
+  /* Check the end of ADC1 reset calibration register */
+  while(ADC_GetResetCalibrationStatus(ADC1));
+
+  /* Start ADC1 calibration */
+  ADC_StartCalibration(ADC1);
+  /* Check the end of ADC1 calibration */
+  while(ADC_GetCalibrationStatus(ADC1));
+
+  /* Start ADC1 Software Conversion */ 
+  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+
+  while (1)
   {
   }
 }
@@ -130,38 +120,16 @@ int main(void)
   */
 void RCC_Configuration(void)
 {
-  /* Enable CEC clock */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
-
-  /* Initialize LEDs and Key Button available on STM32F100B-EVAL board ***/
-  /* Configure LED1, LED2, LED3 and LED4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Configure the Key Push button and its associated EXTI Line */
-  STM_EVAL_PBInit(Button_KEY, Mode_EXTI);
-}
-
-/**
-  * @brief  Configures the different NVIC interrupts.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure two bits for preemption priority */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-
-  /* Enable the CEC global Interrupt (with higher priority) */
-  NVIC_InitStructure.NVIC_IRQChannel = CEC_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  /* ADCCLK = PCLK2/2 */
+  RCC_ADCCLKConfig(RCC_PCLK2_Div2);
+#else
+  /* ADCCLK = PCLK2/4 */
+  RCC_ADCCLKConfig(RCC_PCLK2_Div4); 
+#endif
+/* Enable peripheral clocks --------------------------------------------------*/
+  /* Enable ADC1 and GPIO_LED clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
 }
 
 /**
@@ -173,37 +141,31 @@ void GPIO_Configuration(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
 
-  /* Enable GPIOB  clocks */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
- 
-  /* Configure GPIOB Pin 8 (CEC line) as Output open drain */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
+  /* Configure PC.04 (ADC Channel14) as analog input -------------------------*/
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
 }
 
 /**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
+  * @brief  Configures NVIC and Vector Table base location.
+  * @param  None
+  * @retval None
   */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
+void NVIC_Configuration(void)
 {
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
+  NVIC_InitTypeDef NVIC_InitStructure;
 
-  return PASSED;  
+  /* Configure and enable ADC interrupt */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  NVIC_InitStructure.NVIC_IRQChannel = ADC1_IRQn;
+#else
+  NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn;
+#endif
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
 }
 
 #ifdef  USE_FULL_ASSERT
@@ -216,7 +178,7 @@ TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength
   * @retval None
   */
 void assert_failed(uint8_t* file, uint32_t line)
-{
+{ 
   /* User can add his own implementation to report the file name and line number,
      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/readme.txt
index fa9a2a9..1e85db4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page USART_Interrupt USART Interrupts example
+  @page ADC_AnalogWatchdog ADC analog watchdog example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/Interrupt/readme.txt 
+  * @file    ADC/AnalogWatchdog/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the USART Interrupts example.
+  * @brief   Description of the ADC analog watchdog example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,31 +20,26 @@
 
 @par Example Description 
 
-This example provides a basic communication between USARTy and USARTz using 
-interrupts. USARTy and USARTz can be USART1 and USART2 or USART2 and USART3, 
-depending on the STMicroelectronics EVAL board you are using.
+This example describes how to use the ADC analog watchdog to guard continuously  
+an ADC channel.
+The ADC1 is configured to convert continuously ADC channel14. The analog watchdog
+is configured and enabled to guard a single regular channel.
+Each time the channel14 converted value exceeds programmed analog watchdog high 
+threshold (value 0x0B00) or goes down analog watchdog low threshold (value 0x0300)
+an AWD interrupt is generated and the output pin connected to LED1 is toggled. The
+LED will bright as long as the AWD interrupt is generated which means that the 
+converted value of regular ADC channel14 is outside the range limited by high and 
+low analog watchdog thresholds.
+The ADC1 clock is set to 12 MHz on Value line devices and to 14 MHz on other 
+devices.
 
-USARTz sends TxBuffer2 to USARTy which sends TxBuffer1 to USARTz. The data received 
-by USARTy and USARTz are stored respectively in RxBuffer1 and RxBuffer2. The data
-transfer is managed in USARTy_IRQHandler and USARTz_IRQHandler in stm32f10x_it.c file.
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 9600 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled       
-
-        
 @par Directory contents 
 
-  - USART/Interrupt/platform_config.h    Evaluation board specific configuration file
-  - USART/Interrupt/stm32f10x_conf.h     Library Configuration file
-  - USART/Interrupt/stm32f10x_it.h       Interrupt handlers header file
-  - USART/Interrupt/stm32f10x_it.c       Interrupt handlers
-  - USART/Interrupt/main.c               Main program
-  - USART/Interrupt/system_stm32f10x.c   STM32F10x system source file
+  - ADC/AnalogWatchdog/stm32f10x_conf.h     Library Configuration file
+  - ADC/AnalogWatchdog/stm32f10x_it.c       Interrupt handlers
+  - ADC/AnalogWatchdog/stm32f10x_it.h       Interrupt handlers header file
+  - ADC/AnalogWatchdog/system_stm32f10x.c   STM32F10x system source file
+  - ADC/AnalogWatchdog/main.c               Main program
 
 @par Hardware and Software environment 
 
@@ -52,41 +47,39 @@ USARTy and USARTz configured as follow:
     Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
   
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
     Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
     STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
     evaluation boards and can be easily tailored to any other supported device 
     and development board.
     To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/Interrupt/platform_config.h file
-
-  - STM32100E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN5 (USART2).
-      @note Make sure that jumper JP5 is not open.
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
 
+ - STM32100E-EVAL  
+    - Use LD1 led connected to PF.06 pin
+    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
+      (potentiometer RV1) 
+      
   - STM32100B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN10 (USART1) and 
-      CN9 (USART2).
-      @note In this case USART2 Tx and Rx pins are remapped by software on PD.05
-            and PD.06 respectively. 
-            
+    - Use LED1 led connected to PC.06 pin
+    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
+      (potentiometer RV2)
+
   - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-              
+    - Use LED1 led connected to PD.07 pin
+    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
+      (potentiometer RV1)   
+            
   - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 (USART1) and 
-      CN8 (USART2).
-    
-  - STM3210B-EVAL Set-up
-    - Connect a null-modem female/female RS232 cable between CN6 (USART1) and 
-      CN5 (USART2).
-      - In this case USART2 Tx and Rx pins are remapped by software on PD.05
-        and PD.06 respectively. 
-  
+    - Use LD1 led connected to PF.06 pin
+    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
+      (potentiometer RV1)     
+
+ - STM3210B-EVAL  
+    - Use LD1 led connected to PC.06 pin
+    - Connect a variable power supply 0-3.3V to ADC Channel14 mapped on pin PC.04
+      (potentiometer RV1) 
+
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
@@ -106,12 +99,12 @@ In order to make the program work, you must do the following :
  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
    microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
+   the Flash memory density ranges between 256 and 512 Kbytes.
  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes. 
+   the Flash memory density ranges between 256 and 512 Kbytes.
  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
    the Flash memory density ranges between 512 and 1024 Kbytes.
  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
+
  * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
  */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c
index d482d69..d482d69 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h
index 59a502e..59a502e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c
index 64f1272..64f1272 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
index 8118c04..8118c04 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h
index fc282f0..fc282f0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
index fa7bccc..fa7bccc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h
index 2a0c5b1..2a0c5b1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c
index 7770570..7770570 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
index c6d474d..c6d474d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/main.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/readme.txt
new file mode 100644
index 0000000..b0e70e0
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/readme.txt
@@ -0,0 +1,98 @@
+/**
+  @page ADC_RegSimul_DualMode ADC regular simultaneous dual mode example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    ADC/RegSimul_DualMode/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the ADC regular simultaneous dual mode example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example describes how to use ADC1 and ADC2 in regular simultaneous dual mode.
+ADC1 is configured to convert channel14 and channel17 regular channels continuously.
+ADC2 is configured to convert channel11 and channel12 regular channels continuously.
+The connection between internal Vref and channel17 is enabled for ADC1.
+
+Once the regular channels conversion is started by software, channel14 is converted
+on ADC1 and channel11 is converted on ADC2 on the same time. The 32bits conversion 
+result is then stored on ADC1 DR register. The DMA will transfer this data which
+will be stored ADC_DualConvertedValueTab table. Consecutively to those conversion,
+channel17 is converted on ADC1 and channel12 on ADC2. The combined conversion
+result is also transferred by DMA to the same destination buffer. 
+
+The same procedure is repeated until the specified number of data to be transferred
+by DMA is reached.
+
+The ADCs clocks are set to 14 MHz.
+
+@par Directory contents 
+
+  - ADC/RegSimul_DualMode/stm32f10x_conf.h     Library Configuration file
+  - ADC/RegSimul_DualMode/stm32f10x_it.c       Interrupt handlers
+  - ADC/RegSimul_DualMode/stm32f10x_it.h       Interrupt handlers header file
+  - ADC/RegSimul_DualMode/system_stm32f10x.c   STM32F10x system source file
+  - ADC/RegSimul_DualMode/main.c               Main program
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
+    XL-Density and Low-Density Devices.
+
+  - This example has been tested with STMicroelectronics STM3210C-EVAL 
+    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and
+    STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored
+    to any other supported device and development board.
+
+  - STM3210C-EVAL Set-up 
+    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
+      PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC 
+      Channel12 mapped on pin PC.02.
+
+  - STM3210E-EVAL Set-up 
+    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
+      PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC 
+      Channel12 mapped on pin PC.02.
+
+  - STM3210B-EVAL Set-up 
+    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
+      PC.04 (potentiometer RV1), ADC Channel11 mapped on pin PC.01 and ADC 
+      Channel12 mapped on pin PC.02.          
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+    
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c
index ec6e131..ec6e131 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h
index 9e9b0b8..9e9b0b8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c
new file mode 100644
index 0000000..ff4b942
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    ADC/RegSimul_DualMode/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+#define SYSCLK_FREQ_56MHz  56000000
+/* #define SYSCLK_FREQ_72MHz  72000000 */
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt
index ae21baa..ae21baa 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
index 9650010..9650010 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
index 9780049..9780049 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
index 90aa163..90aa163 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/TIMTrigger_AutoInjection/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c
new file mode 100644
index 0000000..a063733
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/main.c
@@ -0,0 +1,201 @@
+/**
+  ******************************************************************************
+  * @file    BKP/Backup_Data/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup BKP_Backup_Data
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
+  #define BKP_DR_NUMBER              10   
+#else
+  #define BKP_DR_NUMBER              42
+#endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+#if defined USE_STM3210B_EVAL || defined USE_STM32100B_EVAL
+uint16_t BKPDataReg[BKP_DR_NUMBER] =
+  {
+    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
+    BKP_DR9, BKP_DR10
+  };
+#else
+uint16_t BKPDataReg[BKP_DR_NUMBER] =
+  {
+    BKP_DR1, BKP_DR2, BKP_DR3, BKP_DR4, BKP_DR5, BKP_DR6, BKP_DR7, BKP_DR8,
+    BKP_DR9, BKP_DR10, BKP_DR11, BKP_DR12, BKP_DR13, BKP_DR14, BKP_DR15, BKP_DR16,
+    BKP_DR17, BKP_DR18, BKP_DR19, BKP_DR20, BKP_DR21, BKP_DR22, BKP_DR23, BKP_DR24,
+    BKP_DR25, BKP_DR26, BKP_DR27, BKP_DR28, BKP_DR29, BKP_DR30, BKP_DR31, BKP_DR32,
+    BKP_DR33, BKP_DR34, BKP_DR35, BKP_DR36, BKP_DR37, BKP_DR38, BKP_DR39, BKP_DR40,
+    BKP_DR41, BKP_DR42
+  };  
+#endif /* USE_STM3210B_EVAL or USE_STM32100B_EVAL */
+
+/* Private function prototypes -----------------------------------------------*/
+void WriteToBackupReg(uint16_t FirstBackupData);
+uint8_t CheckBackupReg(uint16_t FirstBackupData);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* Initialize Leds mounted on STM3210X-EVAL board */
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+  
+  /* Enable PWR and BKP clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
+
+  /* Enable write access to Backup domain */
+  PWR_BackupAccessCmd(ENABLE);
+
+  /* Clear Tamper pin Event(TE) pending flag */
+  BKP_ClearFlag();
+
+  /* Check if the Power On Reset flag is set */
+  if(RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET)
+  {
+    /* Clear reset flags */
+    RCC_ClearFlag();
+
+    /* Turn on LED3 */
+    STM_EVAL_LEDOn(LED3);
+   
+    /* Check if Backup data registers are programmed */
+    if(CheckBackupReg(0x3210) == 0x00)
+    { /* Backup data registers values are correct */
+
+      /* Turn on LED1 */
+      STM_EVAL_LEDOn(LED1);
+    }
+    else
+    { /* Backup data registers values are not correct or they are not yet
+         programmed (when the first time the program is executed) */
+
+      /* Write data to Backup data registers */
+      WriteToBackupReg(0x3210);
+
+      /* Turn on LED2 */
+      STM_EVAL_LEDOn(LED2);
+    }
+  }
+
+  /* Turn on LED4 */
+  STM_EVAL_LEDOn(LED4);
+       
+  while (1)
+  {    
+  }
+}
+
+/**
+  * @brief  Writes data Backup DRx registers.
+  * @param  FirstBackupData: data to be written to Backup data registers.
+  * @retval None
+  */
+void WriteToBackupReg(uint16_t FirstBackupData)
+{
+  uint32_t index = 0;
+
+  for (index = 0; index < BKP_DR_NUMBER; index++)
+  {
+    BKP_WriteBackupRegister(BKPDataReg[index], FirstBackupData + (index * 0x5A));
+  }  
+}
+
+/**
+  * @brief  Checks if the Backup DRx registers values are correct or not.
+  * @param  FirstBackupData: data to be compared with Backup data registers.
+  * @retval 
+  *          - 0: All Backup DRx registers values are correct
+  *          - Value different from 0: Number of the first Backup register
+  *            which value is not correct
+  */
+uint8_t CheckBackupReg(uint16_t FirstBackupData)
+{
+  uint32_t index = 0;
+
+  for (index = 0; index < BKP_DR_NUMBER; index++)
+  {
+    if (BKP_ReadBackupRegister(BKPDataReg[index]) != (FirstBackupData + (index * 0x5A)))
+    {
+      return (index + 1);
+    }
+  }
+
+  return 0;
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt
index fc4cf9b..fc4cf9b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
index 781b64b..781b64b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
index c6ba787..c6ba787 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h
index e4015fe..e4015fe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/main.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c
index eb3764d..df9d49b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    I2S/Interrupt/stm32f10x_it.c 
+  * @file    BKP/Tamper/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -23,12 +23,13 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
+#include "main.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup I2S_Interrupt
+/** @addtogroup BKP_Tamper
   * @{
   */ 
 
@@ -36,10 +37,6 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-extern const uint16_t I2S3_Buffer_Tx[32];
-extern uint16_t I2S2_Buffer_Rx[32];
-extern  __IO uint32_t TxIdx, RxIdx;
-
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
@@ -65,7 +62,8 @@ void HardFault_Handler(void)
 {
   /* Go to infinite loop when Hard Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -77,7 +75,8 @@ void MemManage_Handler(void)
 {
   /* Go to infinite loop when Memory Manage exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -89,7 +88,8 @@ void BusFault_Handler(void)
 {
   /* Go to infinite loop when Bus Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -101,24 +101,25 @@ void UsageFault_Handler(void)
 {
   /* Go to infinite loop when Usage Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
-  * @brief  This function handles Debug Monitor exception.
+  * @brief  This function handles SVCall exception.
   * @param  None
   * @retval None
   */
-void DebugMon_Handler(void)
+void SVC_Handler(void)
 {
 }
 
 /**
-  * @brief  This function handles SVCall exception.
+  * @brief  This function handles Debug Monitor exception.
   * @param  None
   * @retval None
   */
-void SVC_Handler(void)
+void DebugMon_Handler(void)
 {
 }
 
@@ -145,39 +146,40 @@ void SysTick_Handler(void)
 /******************************************************************************/
 
 /**
-  * @brief  This function handles SPI3 global interrupt request.
+  * @brief  This function handles Tamper interrupt request. 
   * @param  None
   * @retval None
   */
-void SPI3_IRQHandler(void)
+void TAMPER_IRQHandler(void)
 {
-  /* Check the interrupt source */
-  if (SPI_I2S_GetITStatus(SPI3, SPI_I2S_IT_TXE) == SET)
-  {
-    /* Send a data from I2S3 */
-    SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
-  }
-
-  /* Check the end of buffer transfer */
-  if (RxIdx == 32)
-  {
-    /* Disable the I2S3 TXE interrupt to end the communication */
-    SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, DISABLE);
-  }
-}
-
-/**
-  * @brief  This function handles SPI2 global interrupt request.
-  * @param  None
-  * @retval None
-  */
-void SPI2_IRQHandler(void)
-{
-  /* Check the interrupt source */
-  if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_RXNE) == SET)
-  {
-    /* Store the I2S2 received data in the relative data table */
-    I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
+  if(BKP_GetITStatus() != RESET)
+  { /* Tamper detection event occurred */
+
+    /* Check if Backup registers are cleared */
+    if(IsBackupRegReset() == 0)
+    {/* OK, Backup registers are reset as expected */
+
+      /* Turn on LED3 */
+      STM_EVAL_LEDOn(LED3);
+    }
+    else
+    {/* Backup registers are not reset */
+      /* Turn on LED4 */
+      STM_EVAL_LEDOn(LED4);
+    }
+
+    /* Clear Tamper pin interrupt pending bit */
+    BKP_ClearITPendingBit();
+
+    /* Clear Tamper pin Event(TE) pending flag */
+    BKP_ClearFlag();
+
+    /* Disable Tamper pin */
+    BKP_TamperPinCmd(DISABLE);
+    
+    /* Enable Tamper pin */
+    BKP_TamperPinCmd(ENABLE);
+      
   }
 }
 
@@ -199,10 +201,10 @@ void SPI2_IRQHandler(void)
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h
new file mode 100644
index 0000000..9b883f5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_it.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    BKP/Tamper/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TAMPER_IRQHandler(void);
+					 
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c
index 9bb6e44..9bb6e44 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
index f38297f..f38297f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt
index 3473f5d..3473f5d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
index 322d003..322d003 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
index 20cb493..20cb493 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c
index 6dea15f..6dea15f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/DualCAN/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt
index e662598..e662598 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h
index ecf7661..ecf7661 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
index 28dec5c..28dec5c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h
index c0dce57..c0dce57 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt
index 1533e0f..1533e0f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
index 3008991..3008991 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h
index a897363..a897363 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt
index 6832fc5..6832fc5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
index 2612de7..2612de7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
index 07e58f3..07e58f3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
index 02e3af3..02e3af3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c
index 2067bfb..2067bfb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CEC/DataExchangeInterrupt/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt
index ff4a85b..ff4a85b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h
index a54a62f..a54a62f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c
index 6b66ab0..6b66ab0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
index 3074221..3074221 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h
index edeeb40..edeeb40 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c
index 31da44f..31da44f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c
index 6ebd060..6ebd060 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld
index edc22c0..edc22c0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/RIDE/stm32F_flash_ROAarray.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
index 8fb838f..8fb838f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h
index 925cfb1..925cfb1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/main.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c
index b341b17..b341b17 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h
index d4790c5..d4790c5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/readme.txt
index 560b636..30738a3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page CortexM3_BitBand CortexM3 BitBand example
+  @page CortexM3_Mode_Privilege CortexM3 Mode Privilege example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    CortexM3/BitBand/readme.txt 
+  * @file    CortexM3/Mode_Privilege/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the CortexM3 BitBand example.
+  * @brief   Description of the CortexM3 Mode Privilege example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,21 +20,35 @@
 
 @par Example Description 
 
-This example shows how to use CortexM3 Bit-Band access to perform atomic 
-read-modify-write and read operations on a variable in SRAM.
+This example shows how to modify CortexM3 Thread mode privilege access and stack.
+CortexM3 Thread mode is entered on Reset, and can be entered as a result of an
+exception return.  
+
+The associated program is used to:
+
+1. Switch the Thread mode stack from Main stack to Process stack
+
+2. Switch the Thread mode from Privileged to Unprivileged
+
+3. Switch the Thread mode from Unprivileged back to Privileged
+
+To monitor the stack used and the privileged or unprivileged access level of code
+in Thread mode, a set of variables is available within the program. It is also
+possible to use the 'Cortex register' window of the debugger.
 
 @par Directory contents 
 
-  - CortexM3/BitBand/stm32f10x_conf.h    Library Configuration file
-  - CortexM3/BitBand/stm32f10x_it.c      Interrupt handlers
-  - CortexM3/BitBand/stm32f10x_it.h      Header for stm32f10x_it.c
-  - CortexM3/BitBand/main.c              Main program
-  - CortexM3/BitBand/system_stm32f10x.c  STM32F10x system source file
+  - CortexM3/Mode_Privilege/stm32f10x_conf.h    Library Configuration file
+  - CortexM3/Mode_Privilege/stm32f10x_it.c      Interrupt handlers
+  - CortexM3/Mode_Privilege/stm32f10x_it.h      Header for stm32f10x_it.c
+  - CortexM3/Mode_Privilege/main.c              Main program
+  - CortexM3/Mode_Privilege/system_stm32f10x.c  STM32F10x system source file
+  
   
 @par Hardware and Software environment 
 
   - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
+    High-Density Value line, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
   
   - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c
index 607e36c..607e36c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h
index 4910999..4910999 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c
new file mode 100644
index 0000000..6bb7840
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    CortexM3/Mode_Privilege/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
new file mode 100644
index 0000000..6d0ed97
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/main.c
@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    DAC/DualModeDMA_SineWave/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup DAC_DualModeDMA_SineWave
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DAC_DHR12RD_Address      0x40007420
+
+/* Init Structure definition */
+DAC_InitTypeDef            DAC_InitStructure;
+DMA_InitTypeDef            DMA_InitStructure;
+TIM_TimeBaseInitTypeDef    TIM_TimeBaseStructure;
+uint32_t Idx = 0;  
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+const uint16_t Sine12bit[32] = {
+                      2047, 2447, 2831, 3185, 3498, 3750, 3939, 4056, 4095, 4056,
+                      3939, 3750, 3495, 3185, 2831, 2447, 2047, 1647, 1263, 909, 
+                      599, 344, 155, 38, 0, 38, 155, 344, 599, 909, 1263, 1647};
+
+uint32_t DualSine12bit[32];
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+void Delay(__IO uint32_t nCount);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+	  
+  
+  /* System Clocks Configuration */
+  RCC_Configuration();   
+
+  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
+     connected to the DAC converter. In order to avoid parasitic consumption, 
+     the GPIO pin should be configured in analog */
+  GPIO_Configuration();
+
+  /* TIM2 Configuration */
+  /* Time base configuration */
+  TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); 
+  TIM_TimeBaseStructure.TIM_Period = 0x19;          
+  TIM_TimeBaseStructure.TIM_Prescaler = 0x0;       
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
+  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+
+  /* TIM2 TRGO selection */
+  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
+
+  /* DAC channel1 Configuration */
+  DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
+  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
+  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
+  DAC_Init(DAC_Channel_1, &DAC_InitStructure);
+
+  /* DAC channel2 Configuration */
+  DAC_Init(DAC_Channel_2, &DAC_InitStructure);
+
+  /* Fill Sine32bit table */
+  for (Idx = 0; Idx < 32; Idx++)
+  {
+    DualSine12bit[Idx] = (Sine12bit[Idx] << 16) + (Sine12bit[Idx]);
+  }
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
+  /* DMA2 channel4 configuration */
+  DMA_DeInit(DMA2_Channel4);
+#else
+  /* DMA1 channel4 configuration */
+  DMA_DeInit(DMA1_Channel4);
+#endif
+  DMA_InitStructure.DMA_PeripheralBaseAddr = DAC_DHR12RD_Address;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&DualSine12bit;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = 32;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
+  DMA_Init(DMA2_Channel4, &DMA_InitStructure);
+  /* Enable DMA2 Channel4 */
+  DMA_Cmd(DMA2_Channel4, ENABLE);
+#else
+  DMA_Init(DMA1_Channel4, &DMA_InitStructure);
+  /* Enable DMA1 Channel4 */
+  DMA_Cmd(DMA1_Channel4, ENABLE);
+#endif
+
+  /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is 
+     automatically connected to the DAC converter. */
+  DAC_Cmd(DAC_Channel_1, ENABLE);
+  /* Enable DAC Channel2: Once the DAC channel2 is enabled, PA.05 is 
+     automatically connected to the DAC converter. */
+  DAC_Cmd(DAC_Channel_2, ENABLE);
+
+  /* Enable DMA for DAC Channel2 */
+  DAC_DMACmd(DAC_Channel_2, ENABLE);
+
+  /* TIM2 enable counter */
+  TIM_Cmd(TIM2, ENABLE);
+
+  while (1)
+  {
+  }
+}
+
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{   
+  /* Enable peripheral clocks ------------------------------------------------*/
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
+  /* DMA2 clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
+#else
+  /* DMA1 clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+#endif
+  /* GPIOA Periph clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+  /* DAC Periph clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* TIM2 Periph clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
+}
+
+
+/**
+  * @brief  Configures the different GPIO ports.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
+     connected to the DAC converter. In order to avoid parasitic consumption, 
+     the GPIO pin should be configured in analog */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+void Delay(__IO uint32_t nCount)
+{
+  for(; nCount != 0; nCount--);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt
index 1e5c19e..1e5c19e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h
index 9f785ca..9f785ca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c
index fb01774..fb01774 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/DualModeDMA_SineWave/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
index e445ebb..e445ebb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt
index 90fd74a..90fd74a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h
index 7239750..f0ae13c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/RegSimul_DualMode/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    ADC/RegSimul_DualMode/stm32f10x_conf.h 
+  * @file    DAC/OneChannelDMA_Escalator/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c
new file mode 100644
index 0000000..bb118e6
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.c
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    DAC/OneChannelDMA_Escalator/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup DAC_OneChannelDMA_Escalator
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h
index b7643cf..e7d83cd 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_it.h 
+  * @file    DAC/OneChannelDMA_Escalator/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c
new file mode 100644
index 0000000..3e6f2de
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannelDMA_Escalator/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    DAC/OneChannelDMA_Escalator/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt
index 80d045b..80d045b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h
index b418306..b418306 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c
index 927e739..927e739 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c
index 896dc50..7b5773d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/OneChannel_NoiseWave/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/main.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    DAC/OneChannel_NoiseWave/main.c 
+  * @file    DAC/TwoChannels_TriangleWave/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -26,7 +26,7 @@
   * @{
   */
 
-/** @addtogroup DAC_OneChannel_NoiseWave
+/** @addtogroup DAC_TwoChannels_TriangleWave
   * @{
   */ 
 
@@ -34,6 +34,7 @@
 /* Private define ------------------------------------------------------------*/
 /* Init Structure definition */
 DAC_InitTypeDef            DAC_InitStructure;
+TIM_TimeBaseInitTypeDef    TIM_TimeBaseStructure;
 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
@@ -66,24 +67,44 @@ int main(void)
      the GPIO pin should be configured in analog */
   GPIO_Configuration();
 
+  /* TIM2 Configuration */
+  TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
+  TIM_TimeBaseStructure.TIM_Period = 0xF;          
+  TIM_TimeBaseStructure.TIM_Prescaler = 0xF;       
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
+  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+
+  /* TIM2 TRGO selection */
+  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
+
   /* DAC channel1 Configuration */
-  DAC_InitStructure.DAC_Trigger = DAC_Trigger_Software;
-  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Noise;
-  DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bits8_0;
-  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+  DAC_InitStructure.DAC_Trigger = DAC_Trigger_T2_TRGO;
+  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle;
+  DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_2047;
+  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
   DAC_Init(DAC_Channel_1, &DAC_InitStructure);
 
+  /* DAC channel2 Configuration */
+  DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1023;
+  DAC_Init(DAC_Channel_2, &DAC_InitStructure);
+
   /* Enable DAC Channel1: Once the DAC channel1 is enabled, PA.04 is 
      automatically connected to the DAC converter. */
   DAC_Cmd(DAC_Channel_1, ENABLE);
 
-  /* Set DAC Channel1 DHR12L register */
-  DAC_SetChannel1Data(DAC_Align_12b_L, 0x7FF0);
+  /* Enable DAC Channel2: Once the DAC channel2 is enabled, PA.05 is 
+     automatically connected to the DAC converter. */
+  DAC_Cmd(DAC_Channel_2, ENABLE);
+
+  /* Set DAC dual channel DHR12RD register */
+  DAC_SetDualChannelData(DAC_Align_12b_R, 0x100, 0x100);
+
+  /* TIM2 enable counter */
+  TIM_Cmd(TIM2, ENABLE);
 
   while (1)
   {
-    /* Start DAC Channel1 conversion by software */
-    DAC_SoftwareTriggerCmd(DAC_Channel_1, ENABLE);
   }
 }
 
@@ -99,6 +120,8 @@ void RCC_Configuration(void)
   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
   /* DAC Periph clock enable */
   RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* TIM2 Periph clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
 }
 
 /**
@@ -113,7 +136,7 @@ void GPIO_Configuration(void)
   /* Once the DAC channel is enabled, the corresponding GPIO pin is automatically 
      connected to the DAC converter. In order to avoid parasitic consumption, 
      the GPIO pin should be configured in analog */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4;
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_4 | GPIO_Pin_5;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
   GPIO_Init(GPIOA, &GPIO_InitStructure);
 }
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/readme.txt
new file mode 100644
index 0000000..fb3dd97
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/readme.txt
@@ -0,0 +1,105 @@
+/**
+  @page DAC_TwoChannels_TriangleWave DAC two channels triangle wave example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    DAC/TwoChannels_TriangleWave/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the DAC two channels triangle wave example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example describes how to use two DAC channels to generate two different
+signals with triangle waves on each DAC Channel output.
+
+DAC channels conversion are configured to be triggered by TIM2 TRGO with triangle
+wave generation. 12bit right data alignment is selected since we choose to access
+both DAC_DHR12R1 and DAC_DHR12R2 registers.
+A triangle amplitude of 2047 is selected for DAC channel1 and 1023 for DAC channel2.
+Both DAC channels are then enabled. DAC Channel1 DHR12R1 and DAC channel2 DHR12R2
+registers are set to have a base output voltage of VREF/16 on each output.
+
+Once TIM2 is enabled, each TIM2 TRGO update event trigger both DAC channels start
+of conversion. The triangle counter is incremented, added to the base value and
+applied to the corresponding DAC channel output. The same calculation is repeated
+on each trigger.
+The triangle waves can be visualized by connecting both PA.04 and PA.05 pins to
+an oscilloscope.
+
+
+@par Directory contents 
+
+  - DAC/TwoChannels_TriangleWave/stm32f10x_conf.h     Library Configuration file
+  - DAC/TwoChannels_TriangleWave/stm32f10x_it.c       Interrupt handlers
+  - DAC/TwoChannels_TriangleWave/stm32f10x_it.h       Header for stm32f10x_it.c
+  - DAC/TwoChannels_TriangleWave/main.c               Main program
+  - DAC/TwoChannels_TriangleWave/system_stm32f10x.c   STM32F10x system source file
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, XL-Density,
+    Medium-Density Value line, High-Density Value line and Low-Density Value 
+    line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100B-EVAL 
+    (Medium-Density Value line), STM3210C-EVAL (Connectivity line), STM32100E-EVAL 
+    (High-Density Value line) and STM3210E-EVAL (High-Density and XL-Density) 
+    evaluation boards and can be easily tailored to any other supported device 
+    and development board.  
+
+  - STM32100B-EVAL Set-up  
+    - Connect PA.04 and PA.05 pins to an oscilloscope 
+    @note JP2 should be open
+    
+  - STM3210C-EVAL Set-up  
+    - Only PA.04 can be monitored on an oscilloscope, PA.05 is used by other
+      module (Motor control connector) that prevents to have DAC channel output
+      on it. However, if you don't use Motor control connector, you can remove
+      the 0ohm resistor R84 and thus PA.05 can be used for DAC output.
+    @note Make shure that jumper JP15 is open.
+    
+  - STM3210E-EVAL Set-up 
+    - Connect PA.04 and PA.05 pins to an oscilloscope  
+	
+  - STM32100E-EVAL Set-up 
+    - Connect PA.04 and PA.05 pins to an oscilloscope      
+    
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+    
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c
new file mode 100644
index 0000000..b38697d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.c
@@ -0,0 +1,168 @@
+/**
+  ******************************************************************************
+  * @file    DAC/TwoChannels_TriangleWave/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup DAC_TwoChannels_TriangleWave
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h
index df6a0ee..df6a0ee 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c
index c68050a..c68050a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
new file mode 100644
index 0000000..fbf4cbf
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/main.c
@@ -0,0 +1,212 @@
+/**
+  ******************************************************************************
+  * @file    DMA/ADC_TIM1/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup DMA_ADC_TIM1
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define ADC1_DR_Address     0x4001244C
+#define TIM1_CCR1_Address   0x40012C34
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ADC_InitTypeDef           ADC_InitStructure;
+TIM_TimeBaseInitTypeDef   TIM_TimeBaseStructure;
+TIM_OCInitTypeDef         TIM_OCInitStructure;
+DMA_InitTypeDef           DMA_InitStructure;
+  
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+   
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* Configure the GPIO ports */
+  GPIO_Configuration();
+
+  /* DMA1 Channel5 configuration ----------------------------------------------*/
+  DMA_DeInit(DMA1_Channel5);
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR1_Address;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)ADC1_DR_Address;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = 1;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(DMA1_Channel5, &DMA_InitStructure);
+  /* Enable DMA1 Channel5 */
+  DMA_Cmd(DMA1_Channel5, ENABLE);
+
+  /* ADC1 configuration ------------------------------------------------------*/
+  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
+  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
+  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
+  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_NbrOfChannel = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
+
+  /* ADC1 RegularChannelConfig Test */ 
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);
+
+  /* TIM1 configuration ------------------------------------------------------*/
+  /* Time Base configuration */
+  TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); 
+  TIM_TimeBaseStructure.TIM_Period = 0xFF0;
+  TIM_TimeBaseStructure.TIM_Prescaler = 0x0;
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
+  /* Channel1 Configuration in PWM mode */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; 
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OC1Init(TIM1, &TIM_OCInitStructure);
+
+  /* Enable TIM1 */  
+  TIM_Cmd(TIM1, ENABLE);
+  /* Enable TIM1 outputs */
+  TIM_CtrlPWMOutputs(TIM1, ENABLE);
+
+  /* Enable TIM1 DMA interface */
+  TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
+
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+
+  /* Enable ADC1 reset calibration register */
+  ADC_ResetCalibration(ADC1);
+  /* Check the end of ADC1 reset calibration register */
+  while(ADC_GetResetCalibrationStatus(ADC1));
+
+  /* Start ADC1 calibration */
+  ADC_StartCalibration(ADC1);
+  /* Check the end of ADC1 calibration */
+  while(ADC_GetCalibrationStatus(ADC1));
+
+  /* Start ADC1 conversion */ 
+  ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* ADCCLK = PCLK2/8 */
+  RCC_ADCCLKConfig(RCC_PCLK2_Div8);   
+
+  /* Enable peripheral clocks ------------------------------------------------*/
+  /* Enable DMA1 clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+  /* Enable GPIOA, GPIOC, ADC1 and TIM1 Periph clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC |
+                         RCC_APB2Periph_ADC1 | RCC_APB2Periph_TIM1, ENABLE);
+}
+
+/**
+  * @brief  Configures the different GPIO ports.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Configure TIM1 Channel1 output */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* Configure ADC Channel14 as analog input */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4  ;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt
index dd93e41..dd93e41 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h
index 8e13530..8e13530 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c
index 2670e7b..2670e7b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt
new file mode 100644
index 0000000..caa5689
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/readme.txt
@@ -0,0 +1,87 @@
+/**
+  @page DMA_FLASH_RAM DMA FLASH to RAM example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    DMA/FLASH_RAM/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the DMA FLASH to RAM example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example provides a description of how to use a DMA channel to transfer 
+a word data buffer from FLASH memory to embedded SRAM memory.
+
+DMA1 Channel6 is configured to transfer the contents of a 32-word data buffer
+stored in Flash memory to the reception buffer declared in RAM.
+
+The start of transfer is triggered by software. DMA1 Channel6 memory-to-memory
+transfer is enabled. Source and destination addresses incrementing is also enabled.
+The transfer is started by setting the Channel enable bit for DMA1 Channel6.
+At the end of the transfer a Transfer Complete interrupt is generated since it
+is enabled. Once interrupt is generated, the remaining data to be transferred is
+read which must be equal to 0. The Transfer Complete Interrupt pending bit is
+then cleared. A comparison between the source and destination buffers is done to
+check that all data have been correctly transferred.
+
+
+@par Directory contents 
+
+  - DMA/FLASH_RAM/stm32f10x_conf.h    Library Configuration file
+  - DMA/FLASH_RAM/stm32f10x_it.c      Interrupt handlers
+  - DMA/FLASH_RAM/stm32f10x_it.h      Interrupt handlers header file
+  - DMA/FLASH_RAM/main.c              Main program
+  - DMA/FLASH_RAM/system_stm32f10x.c  STM32F10x system source file
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
+    XL-Density,High-Density Value line, Medium-Density Value line, Low-Density 
+    and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density
+    Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density 
+    and XL-Density), STM32100E-EVAL (High-Density Value line) and STM3210B-EVAL 
+    (Medium-Density) evaluation boards and can be easily tailored to any other 
+    supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
index 4288f07..4288f07 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h
index e90099f..e90099f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c
new file mode 100644
index 0000000..8e7f882
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    DMA/FLASH_RAM/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
index d982167..d982167 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/main.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/readme.txt
new file mode 100644
index 0000000..d53bfe6
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/readme.txt
@@ -0,0 +1,92 @@
+/**
+  @page DMA_FSMC DMA FSMC example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    DMA/FSMC/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the DMA FSMC example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example provides a description of how to use two DMA channels to transfer
+a word data buffer from Flash memory to external SRAM memory and to recuperate
+the written data from external SRAM to be stored in internal SRAM.
+
+DMA2 Channel5 is configured to transfer, word by word, the contents of a 32-word data 
+buffer stored in Flash memory to the external SRAM memory interfaced by FSMC.
+The start of transfer is triggered by software. DMA2 Channel5 memory-to-memory
+transfer is enabled.
+Source and destination address incrementing is also enabled. The transfer is started
+by setting the Channel enable bit for DMA2 Channel5. A polling on the Transfer Complete
+flag is done to check the end of transfer. The DMA2 Channel5 Transfer complete flag
+is then cleared.
+
+DMA1 Channel3 is configured to transfer, byte by byte, the contents of the first
+128Bytes of external SRAM to the internal SRAM memory. The start of transfer is
+triggered by software. DMA1 Channel3 memory-to-memory transfer is enabled.
+Source and destination address incrementing is also enabled. The transfer is started
+by setting the Channel enable bit for DMA1 Channel3. A polling on the Transfer Complete
+flag is done to check the end of transfer.
+
+A comparison between the source and destination buffers is done to check that all data
+have been correctly transferred.
+
+
+@par Directory contents 
+
+  - DMA/FSMC/stm32f10x_conf.h     Library Configuration file
+  - DMA/FSMC/stm32f10x_it.c       Interrupt handlers
+  - DMA/FSMC/stm32f10x_it.h       Interrupt handlers header file
+  - DMA/FSMC/main.c               Main program  
+  - DMA/FSMC/system_stm32f10x.c   STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs only on STM32F10x High-Density, High-Density Value line
+    and XL-Density Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards 
+    and can be easily tailored to any other supported device and development board.
+
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.   
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+      
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h
index d9edf7c..119260e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file DMA/SPI_RAM/stm32f10x_conf.h 
+  * @file    DMA/FSMC/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c
index 0db2022..2ac6698 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    PWR/STOP/system_stm32f10x.c
+  * @file    DMA/FSMC/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
index 56a6480..56a6480 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h
index 84b2d00..2926b30 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/DMA/stm32f10x_conf.h 
+  * @file DMA/I2C_RAM/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c
index 1c69e80..9536c56 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    ADC/ADC1_DMA/stm32f10x_it.c 
+  * @file    DMA/I2C_RAM/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup ADC_ADC1_DMA
+/** @addtogroup DMA_I2C_RAM
   * @{
   */ 
 
@@ -158,10 +158,10 @@ void SysTick_Handler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h
index 7de2e62..94c49d4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    DMA/FSMC/stm32f10x_it.h 
+  * @file DMA/I2C_RAM/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c
index f281d1a..f281d1a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
index 2448236..2448236 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h
index a9e96a5..a9e96a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt
index 7bcbeb8..7bcbeb8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c
index 24834be..758668e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    FSMC/NAND/stm32f10x_it.c 
+  * @file    DMA/SPI_RAM/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup FSMC_NAND
+/** @addtogroup DMA_SPI_RAM
   * @{
   */ 
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h
index 54b35d9..2f4dfa4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file SPI/DMA/stm32f10x_it.h 
+  * @file DMA/SPI_RAM/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
index 33a0bc0..33a0bc0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/SPI_RAM/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
index 46f52f1..46f52f1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/readme.txt
index 4e9c8f7..6e779d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page GPIO_JTAG_Remap GPIO JTAG Remap example
+  @page EXTI_Config EXTI configuration example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    GPIO/JTAG_Remap/readme.txt 
+  * @file    EXTI/EXTI_Config/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the GPIO JTAG Remap example.
+  * @brief   Description of the EXTI configuration example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,31 +20,39 @@
 
 @par Example Description 
 
-This example provides a short description of how to use the JTAG IOs as standard 
-GPIOs and gives a configuration sequence. 
+This example shows how to configure external interrupt lines.
+In this example, 2 EXTI lines (EXTI0 and EXTI8 or EXTI9) are configured 
+to generate an interrupt on each rising or falling edge. In the interrupt routine 
+a led connected to a specific GPIO pin is toggled.
 
-First, the SWJ-DP is disabled. The SWJ-DP pins are configured as output push-pull.
-Five LEDs connected to the PA.13(JTMS/SWDAT), PA.14(JTCK/SWCLK), PA.15(JTDI), 
-PB.03(JTDO) and PB.04(JTRST) pins are toggled in an infinite loop.
+In this example:
+  - EXTI0 is mapped to PA.00
+  - EXTI8 is mapped to PG.08
+  - EXTI9 is mapped to PB.09
 
-Note that once the JTAG IOs are disabled, the connection with the host debugger is
-lost and cannot be re-established as long as the JTAG IOs remain disabled. 
+After EXTI configuration, a software interrupt is generated on the EXTI0 toggles LED1.
+After that,
+  when rising edge is detected on EXTI0, LED1 toggles
+  when falling edge is detected on EXTI8, LED2 toggles
+  when falling edge is detected on EXTI9, LED2 toggles
 
-To avoid this situation, a specified pin is connected to a push-button that is used
-to disable or not the JTAG IOs:
- 1. push-button pressed at reset: JTAG IOs disabled	and LED1 turned on
- 2. push-button not pressed at reset: JTAG IOs unchanged and LED2 turned on
 
-Before starting this example, you should disconnect your tool chain debugging probe
-and run the example in standalone mode.
+If any STM3210XX-EVAL is used,
+  when Wakeup push-button is pressed, LED1 toggles
+  when Key push-button is pressed, LED2 toggles
+
+In this example, EXTI0_Config() function can be substituted by 
+STM_EVAL_PBInit(Button_WAKEUP, Mode_EXTI) and EXTI9_5_Config() by 
+STM_EVAL_PBInit(Button_KEY, Mode_EXTI) provided in the STM3210XX-EVAL driver.
+
 
 @par Directory contents 
 
-  - GPIO/JTAG_Remap/stm32f10x_conf.h     Library Configuration file
-  - GPIO/JTAG_Remap/stm32f10x_it.c       Interrupt handlers
-  - GPIO/JTAG_Remap/stm32f10x_it.h       Header for stm32f10x_it.c
-  - GPIO/JTAG_Remap/main.c               Main program
-  - GPIO/JTAG_Remap/system_stm32f10x.c   STM32F10x system source file
+  - EXTI/EXTI_Config/stm32f10x_conf.h    Library Configuration file
+  - EXTI/EXTI_Config/stm32f10x_it.h      Interrupt handlers header file
+  - EXTI/EXTI_Config/stm32f10x_it.c      Interrupt handlers
+  - EXTI/EXTI_Config/main.c              Main program
+  - EXTI/EXTI_Config/system_stm32f10x.c  STM32F10x system source file
   
 @par Hardware and Software environment 
 
@@ -55,36 +63,39 @@ and run the example in standalone mode.
   - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
     Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
     (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other
+    (Medium-Density) evaluation boards and can be easily tailored to any other 
     supported device and development board.
     To select the STMicroelectronics evaluation board used to run the example, 
     uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
 
   - STM32100E-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use LD1 and LD2 connected respectively to PF.06 and PF.07
-    
-  - STM32100B-EVAL Set-up  
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
-    
+    - Use LED1 and LED2 connected to PF.06 and PF.07 pin
+    - Use the Key push-button connected to pin PG.08 (EXTI Line8). 
+    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
+    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button
+        
+  - STM32100B-EVAL Set-up 
+    - Use LED1 and LED2 connected to PC.06 and PC.07 pin
+    - Use the Key push-button connected to pin PB.09 (EXTI Line9). 
+    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
+        
   - STM3210C-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
+    - Use LED1 and LED2 connected to PD.07 and PD.13 pin
     - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
-
+    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0). Make sure 
+      that the Jumper 14 is in position 2<->3.
+      
   - STM3210E-EVAL Set-up 
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PG.08 (EXTI Line8).
-    - Use LD1 and LD2 connected respectively to PF.06 and PF.07
+    - Use LED1 and LED2 connected to PF.06 and PF.07 pin
+    - Use the Key push-button connected to pin PG.08 (EXTI Line8). 
+    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
+    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button
+    
+  - STM3210B-EVAL Set-up 
+    - Use LED1 and LED2 connected to PC.06 and PC.07 pin
+    - Use the Key push-button connected to pin PB.09 (EXTI Line9).     
+    - Use the Wakeup push-button connected to pin PA.00 (EXTI Line0).
     
-  - STM3210B-EVAL Set-up  
-    - Connect five leds to pins PA.13, PA.14, PA.15, PB.03 and PB.04. 
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    - Use LD1 and LD2 connected respectively to PC.06 and PC.07
- 
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
@@ -104,7 +115,7 @@ In order to make the program work, you must do the following :
  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
    microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
+   the Flash memory density ranges between 256 and 512 Kbytes.   
  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
    the Flash memory density ranges between 256 and 512 Kbytes.
  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h
index 0afac1b..692a588 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CAN/Networking/stm32f10x_conf.h 
+  * @file    EXTI/EXTI_Config/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c
index 0a507d7..0a507d7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h
index 893a2c9..893a2c9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c
index 1c27fac..1c27fac 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/EXTI/EXTI_Config/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd
index 505bd47..505bd47 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewd
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp
index 2e02b84..2e02b84 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.ewp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww
index e0fd14b..e0fd14b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/Project.eww
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_nor.icf b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank1.icf
index 99c15be..2c2e0d6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_nor.icf
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank1.icf
@@ -2,12 +2,12 @@
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x64000000;
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x64000000 ;
-define symbol __ICFEDIT_region_ROM_end__     = 0x64FFFFFF;
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
 define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__     = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__   = 0x400;
 define symbol __ICFEDIT_size_heap__     = 0x200;
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf
index 2d868e1..2d868e1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/EWARM/stm32f10x_flash_xl_bank2.icf
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp
index 9eb095c..9eb095c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/STM3210X-XL_BANK1.htp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr
index e3dbe23..e3dbe23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/StartupScript.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk
index 423d253..423d253 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/link.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_go_main.scr
index 3e9c066..3e9c066 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_go_main.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp
index 96444cb..96444cb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/STM3210X-XL_BANK2.htp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl
index 3e6d303..3e6d303 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/arm_arch.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk
index a3b94a1..a3b94a1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/link.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr
index 3e9c066..3e9c066 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_go_main.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/setstack.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm
index 2c11b4c..2c11b4c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/setstack.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt
index eca625f..eca625f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvopt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj
index d63a62b..d63a62b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/MDK-ARM/Project.uvproj
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.cproject b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.cproject
index 8134951..8ff64a1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.cproject
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.cproject
@@ -14,7 +14,7 @@
 </extensions>
 </storageModule>
 <storageModule moduleId="cdtBuildSystem" version="4.0.0">
-<configuration artifactExtension="elf" artifactName="STM32F10X_XL_BANK2" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+<configuration artifactExtension="elf" artifactName="STM32F10X_XL_BANK1" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
 <folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
 <toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
 <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
@@ -31,15 +31,15 @@
 <listOptionValue builtIn="false" value="../../../../../../../Libraries/CMSIS/CM3/CoreSupport"/>
 <listOptionValue builtIn="false" value="../../../../../../../Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x"/>
 <listOptionValue builtIn="false" value="../../../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
-<listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL"/>
 <listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL/Common"/>
 <listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+<listOptionValue builtIn="false" value="../../../../../../../Utilities/STM32_EVAL"/>
 </option>
 <option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
 <listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
 <listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
 <listOptionValue builtIn="false" value="STM32F10X_XL"/>
-<listOptionValue builtIn="false" value="BOOT_FROM_BANK2"/>
+<listOptionValue builtIn="false" value="BOOT_FROM_BANK1"/>
 </option>
 <option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
 <option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
@@ -53,7 +53,7 @@
 <option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
 <option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
 <option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
-<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32F10X_XL_BANK2\stm32f10x_flash_xl_bank2.ld}" valueType="string"/>
+<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32F10X_XL_BANK1\stm32f10x_flash_xl_bank1.ld}" valueType="string"/>
 <option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
 <inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
 <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
@@ -88,6 +88,7 @@
 </storageModule>
 <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
 <storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
 <storageModule moduleId="scannerConfiguration">
 <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
 <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
@@ -253,8 +254,90 @@
 </scannerInfoProvider>
 </profile>
 </scannerConfigBuildInfo>
+<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.200587476;com.atollic.truestudio.exe.debug.toolchain.gcc.475959125;com.atollic.truestudio.gcc.input.910049069">
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+</scannerConfigBuildInfo>
 </storageModule>
-<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
 </cconfiguration>
 </storageModule>
 <storageModule moduleId="cdtBuildSystem" version="4.0.0">
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project
index cb11100..cb11100 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/.project
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld
index f9c3fbf..f9c3fbf 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK1/stm32f10x_flash_xl_bank1.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project
index d32fbd6..d32fbd6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.project
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index a3b6606..a3b6606 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/.settings/com.atollic.truestudio.debug.hardware_device.prefs
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld
index 2b96afe..2b96afe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/TrueSTUDIO/STM32F10X_XL_BANK2/stm32f10x_flash_xl_bank2.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
index 9a1b53e..9a1b53e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h
index dd55adf..dd55adf 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/main.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h
index c4654a7..c4654a7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c
new file mode 100644
index 0000000..03dedc2
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.c
@@ -0,0 +1,169 @@
+/**
+  ******************************************************************************
+  * @file    FLASH/Dual_Boot/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "main.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup Dual_Boot
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+  TimingDelay_Decrement();
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h
index 7932911..1050471 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_it.h 
+  * @file    FLASH/Dual_Boot/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c
index d495771..6fccb6d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CAN/Networking/system_stm32f10x.c
+  * @file    FLASH/Dual_Boot/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
new file mode 100644
index 0000000..fe05bb2
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/main.c
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    FLASH/Program/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup FLASH_Program
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
+
+/* Private define ------------------------------------------------------------*/
+/* Define the STM32F10x FLASH Page Size depending on the used STM32 device */
+#if defined (STM32F10X_HD) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
+  #define FLASH_PAGE_SIZE    ((uint16_t)0x800)
+#else
+  #define FLASH_PAGE_SIZE    ((uint16_t)0x400)
+#endif
+
+#define BANK1_WRITE_START_ADDR  ((uint32_t)0x08008000)
+#define BANK1_WRITE_END_ADDR    ((uint32_t)0x0800C000)
+
+#ifdef STM32F10X_XL
+ #define BANK2_WRITE_START_ADDR   ((uint32_t)0x08088000)
+ #define BANK2_WRITE_END_ADDR     ((uint32_t)0x0808C000)
+#endif /* STM32F10X_XL */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/  
+uint32_t EraseCounter = 0x00, Address = 0x00;
+uint32_t Data = 0x3210ABCD;
+uint32_t NbrOfPage = 0x00;
+volatile FLASH_Status FLASHStatus = FLASH_COMPLETE;
+volatile TestStatus MemoryProgramStatus = PASSED;
+
+#ifdef STM32F10X_XL
+volatile TestStatus MemoryProgramStatus2 = PASSED;
+#endif /* STM32F10X_XL */
+
+/* Private function prototypes -----------------------------------------------*/   
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+
+/* Porgram FLASH Bank1 ********************************************************/       
+  /* Unlock the Flash Bank1 Program Erase controller */
+  FLASH_UnlockBank1();
+
+  /* Define the number of page to be erased */
+  NbrOfPage = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
+
+  /* Clear All pending flags */
+  FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);	
+
+  /* Erase the FLASH pages */
+  for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
+  {
+    FLASHStatus = FLASH_ErasePage(BANK1_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
+  }
+  
+  /* Program Flash Bank1 */
+  Address = BANK1_WRITE_START_ADDR;
+
+  while((Address < BANK1_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
+  {
+    FLASHStatus = FLASH_ProgramWord(Address, Data);
+    Address = Address + 4;
+  }
+
+  FLASH_LockBank1();
+  
+  /* Check the correctness of written data */
+  Address = BANK1_WRITE_START_ADDR;
+
+  while((Address < BANK1_WRITE_END_ADDR) && (MemoryProgramStatus != FAILED))
+  {
+    if((*(__IO uint32_t*) Address) != Data)
+    {
+      MemoryProgramStatus = FAILED;
+    }
+    Address += 4;
+  }
+
+#ifdef STM32F10X_XL
+/* Program FLASH Bank2 ********************************************************/  
+  /* Unlock the Flash Bank2 Program Erase controller */
+  FLASH_UnlockBank2();
+
+  /* Define the number of page to be erased */
+  NbrOfPage = (BANK2_WRITE_END_ADDR - BANK2_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
+
+  /* Clear All pending flags */
+  FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);	
+
+  /* Erase the FLASH pages */
+  for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
+  {
+    FLASHStatus = FLASH_ErasePage(BANK2_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
+  }
+  
+  /* Program Flash Bank2 */
+  Address = BANK2_WRITE_START_ADDR;
+
+  while((Address < BANK2_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
+  {
+    FLASHStatus = FLASH_ProgramWord(Address, Data);
+    Address = Address + 4;
+  }
+
+  FLASH_LockBank2();
+    
+  /* Check the correctness of written data */
+  Address = BANK2_WRITE_START_ADDR;
+
+  while((Address < BANK2_WRITE_END_ADDR) && (MemoryProgramStatus2 != FAILED))
+  {
+    if((*(__IO uint32_t*) Address) != Data)
+    {
+      MemoryProgramStatus2 = FAILED;
+    }
+    Address += 4;
+  }
+
+#endif /* STM32F10X_XL */ 
+  
+  while (1)
+  {
+  }
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h
new file mode 100644
index 0000000..cdd6f26
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    FLASH/Program/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_cec.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h
index 2596f20..2596f20 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c
new file mode 100644
index 0000000..14f36f0
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    FLASH/Program/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
new file mode 100644
index 0000000..ddc1076
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/main.c
@@ -0,0 +1,211 @@
+/**
+  ******************************************************************************
+  * @file    FLASH/Write_Protection/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup FLASH_Write_Protection
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
+
+/* Private define ------------------------------------------------------------*/
+/* Define the STM32F10x FLASH Page Size depending on the used device */
+#if defined (STM32F10X_HD) || defined (STM32F10X_HD_VL) || (STM32F10X_CL) || defined (STM32F10X_XL)
+  #define FLASH_PAGE_SIZE    ((uint16_t)0x800)
+  #define FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages12to13 | FLASH_WRProt_Pages14to15)  
+#else
+  #define FLASH_PAGE_SIZE    ((uint16_t)0x400)
+  #define FLASH_PAGES_TO_BE_PROTECTED (FLASH_WRProt_Pages24to27 | FLASH_WRProt_Pages28to31)  
+#endif
+
+#define BANK1_WRITE_START_ADDR  ((uint32_t)0x08006000)
+#define BANK1_WRITE_END_ADDR    ((uint32_t)0x08008000)
+ 
+/* Uncomment this line to program the Falsh pages */
+//#define FLASH_PAGE_PROGRAM
+/* Uncomment this line to Enable Write Protection */
+//#define WRITE_PROTECTION_ENABLE
+/* Uncomment this line to Disable Write Protection */
+#define WRITE_PROTECTION_DISABLE
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/  
+uint32_t EraseCounter = 0x0, Address = 0x0;
+uint16_t Data = 0x1753;
+uint32_t WRPR_Value = 0xFFFFFFFF, ProtectedPages = 0x0;
+uint32_t NbrOfPage;
+volatile FLASH_Status FLASHStatus = FLASH_COMPLETE;
+volatile TestStatus MemoryProgramStatus = PASSED;
+
+/* Private function prototypes -----------------------------------------------*/  
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+  
+  /* Unlock the Flash Program Erase controller */  
+  FLASH_Unlock();
+
+  /* Get pages write protection status */
+  WRPR_Value = FLASH_GetWriteProtectionOptionByte();
+
+#ifdef WRITE_PROTECTION_DISABLE
+  
+  /* Get pages already write protected */
+  ProtectedPages = ~(WRPR_Value | FLASH_PAGES_TO_BE_PROTECTED);
+  
+  /* Check if desired pages are already write protected */
+  if((WRPR_Value | (~FLASH_PAGES_TO_BE_PROTECTED)) != 0xFFFFFFFF )
+  {
+    /* Erase all the option Bytes */
+    FLASHStatus = FLASH_EraseOptionBytes();
+    
+  /* Check if there is write protected pages */
+  if(ProtectedPages != 0x0)
+  {
+      /* Restore write protected pages */
+      FLASHStatus = FLASH_EnableWriteProtection(ProtectedPages);
+    }
+    /* Generate System Reset to load the new option byte values */
+    NVIC_SystemReset();
+  }
+
+#elif defined WRITE_PROTECTION_ENABLE
+
+  /* Get current write protected pages and the new pages to be protected */
+  ProtectedPages =  (~WRPR_Value) | FLASH_PAGES_TO_BE_PROTECTED; 
+  
+  /* Check if desired pages are not yet write protected */
+  if(((~WRPR_Value) & FLASH_PAGES_TO_BE_PROTECTED )!= FLASH_PAGES_TO_BE_PROTECTED)
+  {
+  
+    /* Erase all the option Bytes because if a program operation is 
+      performed on a protected page, the Flash memory returns a 
+      protection error */
+    FLASHStatus = FLASH_EraseOptionBytes();
+
+    /* Enable the pages write protection */
+    FLASHStatus = FLASH_EnableWriteProtection(ProtectedPages);
+  
+    /* Generate System Reset to load the new option byte values */
+    NVIC_SystemReset();
+  }
+  
+#endif
+
+#ifdef FLASH_PAGE_PROGRAM  
+  /* Get the number of pages to be erased */
+  NbrOfPage = (BANK1_WRITE_END_ADDR - BANK1_WRITE_START_ADDR) / FLASH_PAGE_SIZE;
+
+  /* The selected pages are not write protected */
+  if ( (WRPR_Value & FLASH_PAGES_TO_BE_PROTECTED) != 0x00)
+  {
+    /* Clear All pending flags */
+    FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP|FLASH_FLAG_PGERR |FLASH_FLAG_WRPRTERR);	
+
+    /* erase the FLASH pages */
+    for(EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
+    {
+      FLASHStatus = FLASH_ErasePage(BANK1_WRITE_START_ADDR + (FLASH_PAGE_SIZE * EraseCounter));
+    }
+  
+    /* FLASH Half Word program of data 0x1753 at addresses defined by  BANK1_WRITE_START_ADDR and BANK1_WRITE_END_ADDR */
+    Address = BANK1_WRITE_START_ADDR;
+
+    while((Address < BANK1_WRITE_END_ADDR) && (FLASHStatus == FLASH_COMPLETE))
+    {
+      FLASHStatus = FLASH_ProgramHalfWord(Address, Data);
+      Address = Address + 2;
+    }
+
+    /* Check the correctness of written data */
+    Address = BANK1_WRITE_START_ADDR;
+
+    while((Address < BANK1_WRITE_END_ADDR) && (MemoryProgramStatus != FAILED))
+    {
+      if((*(__IO uint16_t*) Address) != Data)
+      {
+        MemoryProgramStatus = FAILED;
+      }
+      Address += 2;
+    }
+  }
+  else
+  { 
+    /* Error to program the flash : The desired pages are write protected */ 
+    MemoryProgramStatus = FAILED;
+  }
+ 
+#endif
+
+  while (1)
+  {
+  }
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt
index 0d0d2a5..0d0d2a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c
index c8862d6..c8862d6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h
index 3ee053b..3ee053b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
index 687ed68..8bdf486 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/main.c
@@ -1,10 +1,10 @@
 /**
   ******************************************************************************
-  * @file    SysTick/TimeBase/main.c 
+  * @file    FSMC/NAND/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Main program body.
+  * @brief   Main program body 
   ******************************************************************************
   * @attention
   *
@@ -20,29 +20,38 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "main.h"
+#include "stm3210e_eval_fsmc_nand.h"
+#include "stm32_eval.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup SysTick_TimeBase
+/** @addtogroup FSMC_NAND
   * @{
   */ 
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+#define BUFFER_SIZE         0x400
+#define NAND_ST_MakerID     0x20
+#define NAND_ST_DeviceID    0x76
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-static __IO uint32_t TimingDelay;
+NAND_IDTypeDef NAND_ID;
+NAND_ADDRESS WriteReadAddr;
+uint8_t TxBuffer[BUFFER_SIZE], RxBuffer[BUFFER_SIZE];
+uint32_t PageNumber = 2, WriteReadStatus = 0, status= 0;
+uint32_t j = 0;
 
 /* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nTime);
+void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
 
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  Main program.
+  * @brief   Main program.
   * @param  None
   * @retval None
   */
@@ -59,84 +68,84 @@ int main(void)
   STM_EVAL_LEDInit(LED1);
   STM_EVAL_LEDInit(LED2);
   STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-
-  /* Turn on LED1 and LED3 */
-  STM_EVAL_LEDOn(LED1);
-  STM_EVAL_LEDOn(LED3);
-
-  /* Setup SysTick Timer for 1 msec interrupts.
-     ------------------------------------------
-    1. The SysTick_Config() function is a CMSIS function which configure:
-       - The SysTick Reload register with value passed as function parameter.
-       - Configure the SysTick IRQ priority to the lowest value (0x0F).
-       - Reset the SysTick Counter register.
-       - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
-       - Enable the SysTick Interrupt.
-       - Start the SysTick Counter.
-    
-    2. You can change the SysTick Clock source to be HCLK_Div8 by calling the
-       SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8) just after the
-       SysTick_Config() function call. The SysTick_CLKSourceConfig() is defined
-       inside the misc.c file.
-
-    3. You can change the SysTick IRQ priority by calling the
-       NVIC_SetPriority(SysTick_IRQn,...) just after the SysTick_Config() function 
-       call. The NVIC_SetPriority() is defined inside the core_cm3.h file.
-
-    4. To adjust the SysTick time base, use the following formula:
-                            
-         Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-    
-       - Reload Value is the parameter to be passed for SysTick_Config() function
-       - Reload Value should not exceed 0xFFFFFF
-   */
-  if (SysTick_Config(SystemCoreClock / 1000))
-  { 
-    /* Capture error */ 
-    while (1);
-  }
-
-  while (1)
+  
+  /* Enable the FSMC Clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+  
+  /* FSMC Initialization */
+  NAND_Init();
+
+  /* NAND read ID command */
+  NAND_ReadID(&NAND_ID);
+
+  /* Verify the NAND ID */
+  if((NAND_ID.Maker_ID == NAND_ST_MakerID) && (NAND_ID.Device_ID == NAND_ST_DeviceID))
   {
-    /* Toggle LED2 and LED4 */
-    STM_EVAL_LEDToggle(LED2);
-    STM_EVAL_LEDToggle(LED4);
-
-    /* Insert 50 ms delay */
-    Delay(50);
-
-    /* Toggle LED1 and LED3 */
-    STM_EVAL_LEDToggle(LED1);
-    STM_EVAL_LEDToggle(LED3);
 
-    /* Insert 100 ms delay */
-    Delay(100);
+    /* NAND memory address to write to */
+    WriteReadAddr.Zone = 0x00;
+    WriteReadAddr.Block = 0x00;
+    WriteReadAddr.Page = 0x00;
+
+    /* Erase the NAND first Block */
+    status = NAND_EraseBlock(WriteReadAddr);
+
+    /* Write data to FSMC NAND memory */
+    /* Fill the buffer to send */
+    Fill_Buffer(TxBuffer, BUFFER_SIZE , 0x66);
+
+    status = NAND_WriteSmallPage(TxBuffer, WriteReadAddr, PageNumber);
+
+    /* Read back the written data */
+    status = NAND_ReadSmallPage (RxBuffer, WriteReadAddr, PageNumber);
+   
+    /* Verify the written data */
+    for(j = 0; j < BUFFER_SIZE; j++)
+    {
+      if(TxBuffer[j] != RxBuffer[j])
+      {
+        WriteReadStatus++;
+      }
+    }
+
+    if (WriteReadStatus == 0)
+    { 
+      /* OK */
+      /* Turn on LED1 */
+      STM_EVAL_LEDOn(LED1);
+    }
+    else
+    { 
+      /* KO */
+      /* Turn on LED2 */
+      STM_EVAL_LEDOn(LED2);
+    }
+  }
+  else
+  {
+    /* Turn on LED3 */
+    STM_EVAL_LEDOn(LED3);
   }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nTime: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void Delay(__IO uint32_t nTime)
-{ 
-  TimingDelay = nTime;
 
-  while(TimingDelay != 0);
+  while(1)
+  {
+  }
 }
 
 /**
-  * @brief  Decrements the TimingDelay variable.
-  * @param  None
-  * @retval None
+  * @brief  Fill the buffer
+  * @param  pBuffer: pointer on the Buffer to fill
+  * @param  BufferSize: size of the buffer to fill
+  * @param  Offset: first value to fill on the Buffer
   */
-void TimingDelay_Decrement(void)
+void Fill_Buffer(uint8_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
 {
-  if (TimingDelay != 0x00)
-  { 
-    TimingDelay--;
+  uint16_t IndexTmp = 0;
+
+  /* Put in global buffer same values */
+  for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
+  {
+    pBuffer[IndexTmp] = IndexTmp + Offset;
   }
 }
 
@@ -161,10 +170,9 @@ void assert_failed(uint8_t* file, uint32_t line)
 }
 
 #endif
-
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt
index 46fb146..46fb146 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h
index be40441..be40441 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c
index 3777114..d239faa 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    FSMC/SRAM/system_stm32f10x.c
+  * @file    FSMC/NAND/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
index 8a3e123..8a3e123 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h
index 534ca2f..534ca2f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c
index 1fd54a1..1fd54a1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h
index 13906bc..13906bc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c
index be27213..dd12636 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/6Steps/system_stm32f10x.c
+  * @file    FSMC/NOR/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini
index 109757e..109757e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/FLASH_NOR.ini
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/STM3210E-EVAL_NOR.FLM b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/STM3210E-EVAL_NOR.FLM
new file mode 100644
index 0000000..f8be719
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/STM3210E-EVAL_NOR.FLM
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt
index a06bbdc..a06bbdc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
index f63a140..f63a140 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
index 9a0d596..9a0d596 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
index eaff5dd..e23d3c2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/main.c
@@ -1,10 +1,10 @@
 /**
   ******************************************************************************
-  * @file    FSMC/SRAM_DataMemory/main.c 
+  * @file    FSMC/NOR_CodeExecute/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Main program body
+  * @brief   Main program body.
   ******************************************************************************
   * @attention
   *
@@ -20,22 +20,26 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "stm3210e_eval_fsmc_nor.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup FSMC_SRAM_DataMemory
+/** @addtogroup FSMC_NOR_CodeExecute
   * @{
   */ 
 
 /* Private typedef -----------------------------------------------------------*/
+typedef  void (*pFunction)(void);
+
 /* Private define ------------------------------------------------------------*/
+#define ApplicationAddress       ((uint32_t)0x64000000)
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-uint32_t Tab[1024], Index;
-__IO uint32_t TabAddr, MSPValue = 0;
+pFunction Jump_To_Application;
+__IO uint32_t JumpAddress;
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -54,17 +58,22 @@ int main(void)
        system_stm32f10x.c file
      */     
 
-  for (Index = 0; Index <1024 ; Index++)
-  {
-     Tab[Index] =Index;
-  }
+  /* FSMC NOR configuration  **************************************************/
+  /* Enable the FSMC Clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
 
-  TabAddr = (uint32_t)Tab; /* should be 0x680xxxxx */
+  /* Configure FSMC Bank1 NOR/SRAM2 */
+  NOR_Init();
 
-  /* Get main stack pointer value */
-  MSPValue = __get_MSP(); /* should be 0x680xxxxx */
+  /* Jump to code loaded in NOR memory and execute it *************************/
+  JumpAddress = *(__IO uint32_t*) (ApplicationAddress + 4);
+  Jump_To_Application = (pFunction) JumpAddress;
+
+  /* Initialize user application's Stack Pointer */
+  __set_MSP(*(__IO uint32_t*) ApplicationAddress); 
+
+  Jump_To_Application();
 
-  /* Infinite loop */
   while (1)
   {
   }
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c
index 9a5bfab..9a5bfab 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h
index 1cb267f..1cb267f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c
index 80c04af..80c04af 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt
index ae132d3..ae132d3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/readme.txt
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h
new file mode 100644
index 0000000..bec91f4
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    FSMC/OneNAND/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_cec.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c
index 0bf6afe..0bf6afe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h
index 5f0cc04..c80099f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    DMA/ADC_TIM1/stm32f10x_it.h 
+  * @file    FSMC/OneNAND/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c
index ffd831d..ffd831d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c
new file mode 100644
index 0000000..b1a6e84
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.c
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    FSMC/SRAM/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup FSMC_SRAM
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h
index bccefcf..bccefcf 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd.s
index 11ccfe3..6a71435 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd.s
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
 ;* File Name          : startup_stm32f10x_hd.s
 ;* Author             : MCD Application Team
 ;* Version            : V3.5.0
-;* Date               : 11-March-2011
+;* Date               : 08-April-2011
 ;* Description        : STM32F10x High Density Devices vector table for EWARM 
 ;*                      toolchain.
 ;*                      This module performs:
@@ -21,7 +21,7 @@
 ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
 ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
 ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*******************************************************************************
+;*******************************************************************************/
 ;
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -37,7 +37,9 @@
 ; table register (VTOR) is initialized to this address if != 0.
 ;
 ; Cortex-M version
-;     
+;  
+   
+__initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
   
     MODULE  ?cstartup
         
@@ -53,7 +55,7 @@
         DATA
        
 __vector_table
-        DCD     sfe(CSTACK)
+        DCD     __initial_spTop           ; Use internal RAM for stack for calling SystemInit. 
         DCD     Reset_Handler             ; Reset Handler
         DCD     NMI_Handler               ; NMI Handler
         DCD     HardFault_Handler         ; Hard Fault Handler
@@ -140,10 +142,13 @@ __vector_table
         PUBWEAK Reset_Handler
         SECTION .text:CODE:REORDER(2)
 Reset_Handler
+
         LDR     R0, =SystemInit
-        BLX     R0
+        BLX     R0   
+        LDR     R0, =sfe(CSTACK)          ; restore original stack pointer
+        MSR     MSP, R0             
         LDR     R0, =__iar_program_start
-        BX      R0
+        BX      R0                 
                
         PUBWEAK NMI_Handler
         SECTION .text:CODE:REORDER(1)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s
index 48be84c..48be84c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s
index 580307f..580307f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm
index 21e11b0..21e11b0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..61ffe84
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd.s
@@ -0,0 +1,363 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd.s
+;* Author             : MCD Application Team
+;* Version            : V3.5.0
+;* Date               : 08-April-2011
+;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+__initial_spTop EQU    0x20000400                 ; stack used for SystemInit & SystemInit_ExtMemCtl
+                                                  
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_spTop            ; use internal RAM for stack for calling SystemInit
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler            ; ADC3
+                DCD     FSMC_IRQHandler            ; FSMC
+                DCD     SDIO_IRQHandler            ; SDIO
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     SPI3_IRQHandler            ; SPI3
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+                
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+
+                LDR     R0, =SystemInit
+                BLX     R0  
+                LDR     R0, =__initial_sp          ; restore original stack pointer
+                MSR     MSP, R0  
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM8_UP_IRQHandler         [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM8_CC_IRQHandler         [WEAK]
+                EXPORT  ADC3_IRQHandler            [WEAK]
+                EXPORT  FSMC_IRQHandler            [WEAK]
+                EXPORT  SDIO_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s
index c028799..c028799 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s
index b9227a6..b9227a6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd.s
index cf0531e..ac7a8d2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/startup_stm32f10x_cl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd.s
@@ -1,16 +1,17 @@
 /**
   ******************************************************************************
-  * @file      startup_stm32f10x_cl.s
+  * @file      startup_stm32f10x_hd.s
   * @author    MCD Application Team
   * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
+  * @date      08-April-2011
+  * @brief     STM32F10x High Density Devices vector table for RIDE7 toolchain. 
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR 
-  *                  address.
-  *                - Configure the clock system    
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3210E-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M3 processor is in Thread mode,
@@ -27,7 +28,7 @@
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */
+  */ 
     
   .syntax unified
   .cpu cortex-m3
@@ -48,8 +49,9 @@ defined in linker script */
 .word  _sbss
 /* end address for the .bss section. defined in linker script */
 .word  _ebss
-
-.equ  BootRAM, 0xF1E0F85F
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+.equ __initial_spTop, 0x20000400
+.equ  BootRAM,        0xF1E0F85F
 /**
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
@@ -62,56 +64,58 @@ defined in linker script */
     .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
-Reset_Handler:
+Reset_Handler:  
 
-/* Copy the data segment initializers from flash to SRAM */
+/* Copy the data segment initializers from flash to SRAM */  
   movs  r1, #0
-  b     LoopCopyDataInit
+  b  LoopCopyDataInit
 
 CopyDataInit:
-  ldr   r3, =_sidata
-  ldr   r3, [r3, r1]
-  str   r3, [r0, r1]
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
   adds  r1, r1, #4
     
 LoopCopyDataInit:
-  ldr   r0, =_sdata
-  ldr   r3, =_edata
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
   adds  r2, r0, r1
-  cmp   r2, r3
-  bcc   CopyDataInit
-  ldr   r2, =_sbss
-  b     LoopFillZerobss
-
-/* Zero fill the bss segment. */
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
 FillZerobss:
   movs  r3, #0
-  str   r3, [r2], #4
+  str  r3, [r2], #4
     
 LoopFillZerobss:
-  ldr   r3, = _ebss
-  cmp   r2, r3
-  bcc   FillZerobss
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
 /* Call the clock system intitialization function.*/
-  bl  SystemInit  
+  bl  SystemInit 
+/* Restore original stack pointer. */
+  ldr     r0, =_estack          
+  msr     MSP, r0 
 /* Call the application's entry point.*/
   bl    main
-  bx    lr
+  bx    lr    
 .size   Reset_Handler, .-Reset_Handler
 
 /**
  * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt. This simply enters an infinite loop, preserving
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
- * @param  None
- * @retval None
+ * @param  None     
+ * @retval None       
 */
     .section  .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b  Infinite_Loop
   .size  Default_Handler, .-Default_Handler
-
 /******************************************************************************
 *
 * The minimal vector table for a Cortex M3. Note that the proper constructs
@@ -119,13 +123,13 @@ Infinite_Loop:
 * 0x0000.0000.
 * 
 *******************************************************************************/
-  .section  .isr_vector,"a",%progbits
+   .section  .isr_vector,"a",%progbits
   .type  g_pfnVectors, %object
   .size  g_pfnVectors, .-g_pfnVectors
     
     
 g_pfnVectors:
-  .word  _estack
+  .word  __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
   .word  Reset_Handler
   .word  NMI_Handler
   .word  HardFault_Handler
@@ -160,8 +164,8 @@ g_pfnVectors:
   .word  DMA1_Channel6_IRQHandler
   .word  DMA1_Channel7_IRQHandler
   .word  ADC1_2_IRQHandler
-  .word  CAN1_TX_IRQHandler
-  .word  CAN1_RX0_IRQHandler
+  .word  USB_HP_CAN1_TX_IRQHandler
+  .word  USB_LP_CAN1_RX0_IRQHandler
   .word  CAN1_RX1_IRQHandler
   .word  CAN1_SCE_IRQHandler
   .word  EXTI9_5_IRQHandler
@@ -183,14 +187,14 @@ g_pfnVectors:
   .word  USART3_IRQHandler
   .word  EXTI15_10_IRQHandler
   .word  RTCAlarm_IRQHandler
-  .word  OTG_FS_WKUP_IRQHandler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
+  .word  USBWakeUp_IRQHandler
+  .word  TIM8_BRK_IRQHandler
+  .word  TIM8_UP_IRQHandler
+  .word  TIM8_TRG_COM_IRQHandler
+  .word  TIM8_CC_IRQHandler
+  .word  ADC3_IRQHandler
+  .word  FSMC_IRQHandler
+  .word  SDIO_IRQHandler
   .word  TIM5_IRQHandler
   .word  SPI3_IRQHandler
   .word  UART4_IRQHandler
@@ -200,15 +204,7 @@ g_pfnVectors:
   .word  DMA2_Channel1_IRQHandler
   .word  DMA2_Channel2_IRQHandler
   .word  DMA2_Channel3_IRQHandler
-  .word  DMA2_Channel4_IRQHandler
-  .word  DMA2_Channel5_IRQHandler
-  .word  ETH_IRQHandler
-  .word  ETH_WKUP_IRQHandler
-  .word  CAN2_TX_IRQHandler
-  .word  CAN2_RX0_IRQHandler
-  .word  CAN2_RX1_IRQHandler
-  .word  CAN2_SCE_IRQHandler
-  .word  OTG_FS_IRQHandler
+  .word  DMA2_Channel4_5_IRQHandler
   .word  0
   .word  0
   .word  0
@@ -245,16 +241,24 @@ g_pfnVectors:
   .word  0
   .word  0
   .word  0
-  .word  BootRAM     /* @0x1E0. This is for boot in RAM mode for 
-                         STM32F10x Connectivity line Devices. */
-
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x High Density devices. */
 /*******************************************************************************
 *
 * Provide weak aliases for each Exception handler to the Default_Handler. 
 * As they are weak aliases, any function with the same name will override 
 * this definition.
-*
+* 
 *******************************************************************************/
+    
   .weak  NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
   
@@ -339,11 +343,11 @@ g_pfnVectors:
   .weak  ADC1_2_IRQHandler
   .thumb_set ADC1_2_IRQHandler,Default_Handler
 
-  .weak  CAN1_TX_IRQHandler
-  .thumb_set CAN1_TX_IRQHandler,Default_Handler
+  .weak  USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
 
-  .weak  CAN1_RX0_IRQHandler
-  .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+  .weak  USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
 
   .weak  CAN1_RX1_IRQHandler
   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
@@ -408,61 +412,58 @@ g_pfnVectors:
   .weak  RTCAlarm_IRQHandler
   .thumb_set RTCAlarm_IRQHandler,Default_Handler
 
-  .weak  OTG_FS_WKUP_IRQHandler
-  .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+  .weak  USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+  .weak  TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+  .weak  TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+  .weak  TIM8_CC_IRQHandler
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+  .weak  ADC3_IRQHandler
+  .thumb_set ADC3_IRQHandler,Default_Handler
+
+  .weak  FSMC_IRQHandler
+  .thumb_set FSMC_IRQHandler,Default_Handler
+
+  .weak  SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
 
   .weak  TIM5_IRQHandler
   .thumb_set TIM5_IRQHandler,Default_Handler
 
-  .weak  SPI3_IRQHandler  
+  .weak  SPI3_IRQHandler
   .thumb_set SPI3_IRQHandler,Default_Handler
 
-  .weak  UART4_IRQHandler  
+  .weak  UART4_IRQHandler
   .thumb_set UART4_IRQHandler,Default_Handler
 
-  .weak  UART5_IRQHandler  
+  .weak  UART5_IRQHandler
   .thumb_set UART5_IRQHandler,Default_Handler
 
-  .weak  TIM6_IRQHandler  
+  .weak  TIM6_IRQHandler
   .thumb_set TIM6_IRQHandler,Default_Handler
 
-  .weak  TIM7_IRQHandler  
+  .weak  TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler
 
-  .weak  DMA2_Channel1_IRQHandler  
+  .weak  DMA2_Channel1_IRQHandler
   .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
 
-  .weak  DMA2_Channel2_IRQHandler  
+  .weak  DMA2_Channel2_IRQHandler
   .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
 
-  .weak  DMA2_Channel3_IRQHandler  
+  .weak  DMA2_Channel3_IRQHandler
   .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
 
-  .weak  DMA2_Channel4_IRQHandler  
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak  DMA2_Channel5_IRQHandler  
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak  ETH_IRQHandler  
-  .thumb_set ETH_IRQHandler,Default_Handler
-
-  .weak  ETH_WKUP_IRQHandler  
-  .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
-  .weak  CAN2_TX_IRQHandler  
-  .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX0_IRQHandler  
-  .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-  .weak  CAN2_RX1_IRQHandler  
-  .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-  .weak  CAN2_SCE_IRQHandler  
-  .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
 
-  .weak  OTG_FS_IRQHandler  
-  .thumb_set OTG_FS_IRQHandler ,Default_Handler
- 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s
index ace5557..ace5557 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s
index 63f88fe..63f88fe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s
index 720297a..720297a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..c4aeaab
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_hd_vl.s
+  * @author    MCD Application Team
+  * @version   V3.5.0
+  * @date      08-April-2011
+  * @brief     STM32F10x High Density Value Line Devices vector table for Atollic 
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system  
+  *                - Configure external SRAM mounted on STM32100E-EVAL board
+  *                  to be used as data memory (optional, to be enabled by user)  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+/* ; stack used for SystemInit & SystemInit_ExtMemCtl*/
+.equ __initial_spTop,    0x20000400 
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+	            
+/* Call the clock system intitialization function.*/
+  bl  SystemInit 
+/* Restore original stack pointer. */
+  ldr     r0, =_estack          
+  msr     MSP, r0 
+/* Call static constructors */
+  bl __libc_init_array  
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word   __initial_spTop /* Use internal RAM for stack for calling SystemInit. */
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	CEC_IRQHandler
+  .word TIM12_IRQHandler
+  .word TIM13_IRQHandler
+  .word TIM14_COM_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word TIM6_DAC_IRQHandler
+  .word TIM7_IRQHandler  
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_5_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x High Density Value line devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM15_IRQHandler
+  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  CEC_IRQHandler
+  .thumb_set CEC_IRQHandler,Default_Handler
+
+  .weak  TIM12_IRQHandler
+  .thumb_set TIM12_IRQHandler,Default_Handler
+
+  .weak  TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak  TIM14_COM_IRQHandler
+  .thumb_set TIM14_COM_IRQHandler,Default_Handler
+
+  .weak  TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+
+  .weak  SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak  UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak  UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+  
+  .weak  TIM6_DAC_IRQHandler
+  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler 
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s
index 7526cf3..7526cf3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt
new file mode 100644
index 0000000..dece978
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/readme.txt
@@ -0,0 +1,115 @@
+/**
+  @page FSMC_SRAM_DataMemory FSMC SRAM DataMemory example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    FSMC/SRAM_DataMemory/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the FSMC SRAM DataMemory example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example shows how to use the external SRAM mounted on STM3210E-EVAL or 
+STM32100E-EVAL board as program data memory and internal SRAM for Stack.
+This example doesn't use the default library startup files. Use the EWARM, MDK-ARM,
+HiTOP, RIDE or TrueSTUDIO startup files provided within this folder.
+
+@par Directory contents 
+
+  - FSMC/SRAM_DataMemory/stm32f10x_conf.h                       Library Configuration file
+  - FSMC/SRAM_DataMemory/stm32f10x_it.c                         Interrupt handlers
+  - FSMC/SRAM_DataMemory/stm32f10x_it.h                         Header for stm32f10x_it.c  
+  - FSMC/SRAM_DataMemory/main.c                                 Main program
+  - FSMC/SRAM_DataMemory/system_stm32f10x.c                     STM32F10x system source file
+  - FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd.s           STM32F10x High-density EWARM startup file
+  - FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_hd_vl.s        STM32F10x High-density Value line EWARM startup file
+  - FSMC/SRAM_DataMemory/EWARM/startup_stm32f10x_xl.s           STM32F10x XL-density EWARM startup file
+  - FSMC/SRAM_DataMemory/HiTOP/cstart_thumb2.asm                STM32F10x XL-density EWARM startup file
+  - FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd.s         STM32F10x High-density MDK-ARM startup file
+  - FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_hd_vl.s      STM32F10x High-density Value line MDK-ARM startup file
+  - FSMC/SRAM_DataMemory/MDK-ARM/startup_stm32f10x_xl.s         STM32F10x XL-density MDK-ARM startup file
+  - FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd.s            STM32F10x High-density RIDE startup file
+  - FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_hd_vl.s         STM32F10x High-density Value line RIDE startup file
+  - FSMC/SRAM_DataMemory/RIDE/startup_stm32f10x_xl.s            STM32F10x XL-density RIDE startup file
+  - FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd.s      STM32F10x High-density TrueSTUDIO startup file
+  - FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_hd_vl.s   STM32F10x High-density Value line TrueSTUDIO startup file
+  - FSMC/SRAM_DataMemory/TrueSTUDIO/startup_stm32f10x_xl.s      STM32F10x XL-density TrueSTUDIO startup file
+  
+@par Hardware and Software environment 
+
+  - This example runs only on STM32F10x High-Density and XL-Density Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line) and STM3210E-EVAL (High-Density and XL-Density) evaluation boards
+    and can be easily tailored to any other supported device and development board.
+    
+@par How to use it ? 
+
+In order to make the program work, you must do the following:
+- Create a project and setup all project configuration:
+<ul>
+ <li> MDK-ARM 
+    - in Project->Options for Target window, select 'RAM1'and enter 0x68000000 
+      as start address with size of 0x100000 (IRAM1 must be un-checked)
+    - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file               
+
+ <li> EWARM 
+    - use "stm32f10x_flash_extsram.icf" as linker file
+    - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file
+
+ <li> RIDE 
+    - In the Application options -> script menu, set "Use Default Script File" 
+      to "No" and use "stm32f10x_flash_extsram.ld" as Script File.
+    - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file
+
+<li> HiTOP 
+    - use "link_extsram" as linker file
+    - Add the file "setstack.asm" to the workspace.
+    - Use the "cstart_thumb2.asm" file  provided with this example instead of 
+      the default one in the workspace.
+    - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file
+
+  
+ <li> TrueSTUDIO 
+    - In the project properties window, select 'C/C++ Build'->settings node then 
+      the 'C Linker'->General node and use "stm32f10x_flash_extsram.ld" as Script File.
+    - uncomment "#define DATA_IN_ExtSRAM " in the "system_stm32f10x.c" file
+      
+</ul>
+
+- Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+- Open your preferred toolchain 
+- Rebuild all files and load your image into target memory
+- Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+    
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h
index f83d30d..f83d30d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c
new file mode 100644
index 0000000..2f4e783
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.c
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    FSMC/SRAM_DataMemory/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup FSMC_SRAM_DataMemory
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h
index 457981c..457981c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c
index 5e8a158..5e8a158 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM_DataMemory/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c
index 449bd2f..449bd2f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/readme.txt
index 095d3d0..bdaa5d7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page FLASH_Program FLASH Program example
+  @page GPIO_IOToggle GPIO IO Toggle example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FLASH/Program/readme.txt 
+  * @file    GPIO/IOToggle/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the FLASH Program example.
+  * @brief   Description of the GPIO IO Toggle example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,39 +20,43 @@
 
 @par Example Description 
 
-This example provides a description of how to program the STM32F10x FLASH.
+GPIO ports are connected on APB2 bus, using BSRRH and BSRRL registers 2 cycles 
+are required to set a pin and another cycle to reset it. So GPIO pins can toggle 
+at AHB clock divided by 4.
 
-After Reset, the Flash memory Program/Erase Controller is locked. To unlock it,
-the FLASH_Unlock function is used.
-Before programming the desired addresses, an erase operation is performed using 
-the flash erase page feature. The erase procedure starts with the calculation of
-the number of pages to be used. Then all these pages will be erased one by one by
-calling FLASH_ErasePage function. 
+This example describes how to use BSRR and BRR (Port Bit Set/Reset Register
+and Port Bit Reset Register) for maximum IO toggling.
 
-Once this operation is finished, the programming operation will be performed by 
-using the FLASH_ProgramWord function. The written data is then checked and the
-result of the programming operation is stored into the MemoryProgramStatus variable.
+PD0 and PD2 (configured in output pushpull mode) toggles in a forever loop:
+ - Set PD0 and PD2 by setting corresponding bits in BSRR register
+ - Reset PD0 and PD2 by setting corresponding bits in BRR register
+
+In this example, HCLK is configured at 72 MHz so PD0 and PD2 toggles at 18MHz.
+To achieve the maximum IO toggling frequency, you have to configure your compiler
+options for high speed optimization.
 
 @par Directory contents 
 
-  - FLASH/Program/stm32f10x_conf.h    Library Configuration file
-  - FLASH/Program/stm32f10x_it.h      Interrupt handlers header file
-  - FLASH/Program/stm32f10x_it.c      Interrupt handlers
-  - FLASH/Program/main.c              Main program
-  - FLASH/Program/system_stm32f10x.c  STM32F10x system source file
+  - GPIO/IOToggle/stm32f10x_conf.h     Library Configuration file
+  - GPIO/IOToggle/stm32f10x_it.c       Interrupt handlers
+  - GPIO/IOToggle/stm32f10x_it.h       Header for stm32f10x_it.c
+  - GPIO/IOToggle/main.c               Main program
+  - GPIO/IOToggle/system_stm32f10x.c   STM32F10x system source file
   
 @par Hardware and Software environment 
 
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
   
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL
     (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and 
     STM3210B-EVAL (Medium-Density) evaluation boards and can be easily tailored 
-    to any other supported device and development board. 
- 
+    to any other supported device and development board.
+    To select the STMicroelectronics evaluation board used to run the example, 
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
@@ -60,7 +64,7 @@ In order to make the program work, you must do the following :
    Project\STM32F10x_StdPeriph_Template
  - Open your preferred toolchain 
  - Rebuild all files and load your image into target memory
- - Run the example 
+ - Run the example
 
 @note
  - Low-density Value line devices are STM32F100xx microcontrollers where the 
@@ -72,12 +76,12 @@ In order to make the program work, you must do the following :
  - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
    microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
  - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
+   the Flash memory density ranges between 256 and 512 Kbytes. 
  - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
+   the Flash memory density ranges between 256 and 512 Kbytes.  
  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
    the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.  
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
    
  * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
  */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c
index 7d9f58e..56fbc9b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/ADC_TIM1/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    DMA/ADC_TIM1/stm32f10x_it.c 
+  * @file    GPIO/IOToggle/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -19,7 +19,7 @@
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
@@ -28,9 +28,9 @@
   * @{
   */
 
-/** @addtogroup DMA_ADC_TIM1
+/** @addtogroup GPIO_IOToggle
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -52,8 +52,6 @@ void NMI_Handler(void)
 {
 }
 
-
-
 /**
   * @brief  This function handles Hard Fault exception.
   * @param  None
@@ -160,10 +158,10 @@ void SysTick_Handler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h
index 900c7c1..900c7c1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c
index 4242895..4242895 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/IOToggle/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c
index 3f2d562..3f2d562 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c
index 65e24ee..c15c9e1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Program/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    FLASH/Program/stm32f10x_it.c 
+  * @file    GPIO/JTAG_Remap/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup FLASH_Program
+/** @addtogroup GPIO_JTAG_Remap
   * @{
   */ 
 
@@ -158,10 +158,10 @@ void SysTick_Handler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h
new file mode 100644
index 0000000..0ddf6d2
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_it.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/JTAG_Remap/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c
index bfd9fac..bfd9fac 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt
index e928351..e928351 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
index e25eef8..e25eef8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c
index 4e76f63..4e76f63 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h
index 5b97d9d..5b97d9d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c
index 748cac7..748cac7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
index f417dea..f417dea 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h
index ce6e6ae..ce6e6ae 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
index 1ab4f75..1ab4f75 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
index 86b6e1b..86b6e1b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c
index cf56f60..cf56f60 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/I2C_TSENSOR/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
index 67d0244..67d0244 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h
index b14ffb0..b14ffb0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/main.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt
index 9a187de..9a187de 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h
index 4a42998..4a42998 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c
index a4c77be..a4c77be 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h
index 91e8742..91e8742 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/readme.txt
new file mode 100644
index 0000000..a913145
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/readme.txt
@@ -0,0 +1,117 @@
+/**
+  @page I2S_Interrupt I2S Interrupt example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    I2S/Interrupt/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the I2S Interrupt example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example provides a description of how to set a communication between two
+SPIs in I2S mode using interrupts and performing a transfer from Master to Slave.
+
+In the first step, I2S3 is configured as master transmitter and I2S2 as slave 
+reliever and both are in Philips standard configuration with 16bit extended to 
+32 bit data packet and 48KHz audio frequency. 
+
+The I2S3 transmit interrupt and the I2S2 receive interrupt are both enabled. And
+in these interrupts subroutines, the I2S3_Buffer_Tx is transmitted and the received
+values are loaded in the I2S2_Buffer_Rx buffer. Only the significant 16 MSBs are
+sent and received, while the 32 packet remaining 16 LSBs are filled with 0 values
+and don't generate any interrupt.
+
+Once the transfer is completed a comparison is done and TransferStatus1 gives the 
+data transfer status where it is PASSED if transmitted and received data are the 
+same otherwise it is FAILED.
+
+In the second step both peripherals are configured in I2S Philips standard 24 bits
+data length in 32 bits packets and 16KHz audio frequency. The interrupts are
+enabled and the transfer is performed from the I2S3 master to the I2S2 slave.
+The 24 bits are transmitted then the 8 remaining LSBs are filled automatically
+with 0 values.
+
+Once the transfer is completed a comparison is done (on the 24 MSBs only, the 8 
+LSBs are replaced by 0) and TransferStatus2 gives the data transfer status where 
+it is PASSED if transmitted and received data are the same otherwise it is FAILED.
+
+@par Directory contents 
+
+  - I2S/Interrupt/stm32f10x_conf.h     Library Configuration file
+  - I2S/Interrupt/stm32f10x_it.c       Interrupt handlers
+  - I2S/Interrupt/stm32f10x_it.h       Header for stm32f10x_it.c
+  - I2S/Interrupt/main.c               Main program
+  - I2S/Interrupt/system_stm32f10x.c   STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x High-Density, XL-Density and Connectivity Line 
+    Devices.
+  
+  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
+    and XL-Density) and STM3210C-EVAL (Connectivity Line) evaluation boards 
+    and can be easily tailored to any other supported device and development board.
+
+  - STM3210C-EVAL Set-up 
+     - Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.04) pin
+     - Connect I2S2 CK (PB.13) pin to I2S3 CK (PC.10) pin
+     - Connect I2S2 SD (PB.15) pin to I2S3 SD (PC.12) pin
+
+  - STM3210E-EVAL Set-up 
+     - Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.15) pin
+     - Connect I2S2 CK (PB.13) pin to I2S3 CK (PB.03) pin
+     - Connect I2S2 SD (PB.15) pin to I2S3 SD (PB.05) pin
+
+Since some SPI3/I2S3 pins are shared with JTAG pins (SPI3_NSS/I2S3_WS with JTDI 
+and SPI3_SCK/I2S3_CK with JTDO), they are not controlled by the I/O controller
+and are reserved for JTAG usage (after each Reset).
+For this purpose prior to configure the SPI3/I2S3 pins: 
+- For STM32F10x High-Density devices, the user has to disable the JTAG and use 
+  the SWD interface (when debugging the application), or disable both JTAG/SWD 
+  interfaces (for standalone application).
+- For STM32F10x Connectivity Line devices, the user can use the solution above 
+  (SWD or disable both JTAG and SWD), or it is possible to remap the SPI3 pins 
+  on {PC10, PC11, PC12, PA4} GPIO pins in order to avoid the conflict with JTAG 
+  pins (and it is possible in this case to use JTAG interface). This remap is 
+  used for STM3210C-EVAL evaluation boards in this example.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h
index f7f98b6..f7f98b6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c
index e8b2dd4..e8b2dd4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
index c79a83e..e701e6f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/main.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    I2S/Interrupt/main.c 
+  * @file    I2S/SPI_I2S_Switch/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -22,11 +22,13 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"
 
+/* Local includes ------------------------------------------------------------*/
+
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup I2S_Interrupt
+/** @addtogroup I2S_SPI_I2S_Switch
   * @{
   */ 
 
@@ -34,32 +36,40 @@
 typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
 
 /* Private define ------------------------------------------------------------*/
+#define BufferSize   32
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 I2S_InitTypeDef I2S_InitStructure;
-const uint16_t I2S3_Buffer_Tx[32] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
-                                     0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
-                                     0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
-                                     0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
-                                     0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
-                                     0x3D3E, 0x3F40};
-
-uint16_t I2S2_Buffer_Rx[32];
-__IO uint32_t TxIdx = 0, RxIdx = 0;
-TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
+SPI_InitTypeDef SPI_InitStructure;
+uint16_t I2S3_Buffer_Tx[BufferSize] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
+                                  0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
+                                  0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
+                                  0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
+                                  0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
+                                  0x3D3E, 0x3F40};
+
+uint16_t SPI3_Buffer_Tx[BufferSize] = {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
+                                  0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
+                                  0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
+                                  0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
+                                  0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
+                                  0x8D8E, 0x8F90};
+
+__IO uint16_t I2S2_Buffer_Rx[BufferSize];
+__IO uint16_t SPI2_Buffer_Rx[BufferSize];
+__IO uint8_t TxIdx = 0, RxIdx = 0;
+volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
+volatile TestStatus TransferStatus3 = FAILED;
 ErrorStatus HSEStartUpStatus;
 
-/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
 void RCC_Configuration(void);
 void GPIO_Configuration(void);
-void NVIC_Configuration(void);
 TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  Main program
+  * @brief   Main program
   * @param  None
   * @retval None
   */
@@ -75,14 +85,12 @@ int main(void)
   /* System clocks configuration ---------------------------------------------*/
   RCC_Configuration();
 
-  /* NVIC configuration ------------------------------------------------------*/
-  NVIC_Configuration();
-
   /* GPIO configuration ------------------------------------------------------*/
   GPIO_Configuration();
-
-  SPI_I2S_DeInit(SPI3);
+ 
+  /* Deinitializes the SPI2 and SPI3 peripheral registers --------------------*/
   SPI_I2S_DeInit(SPI2);
+  SPI_I2S_DeInit(SPI3);
   
   /* I2S peripheral configuration */
   I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
@@ -91,7 +99,7 @@ int main(void)
   I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_48k;
   I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
 
-  /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
+  /* I2S3 Master Transmitter to I2S2 Slave Receiver communication ------------*/
   /* I2S3 configuration */
   I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
   I2S_Init(SPI3, &I2S_InitStructure);
@@ -100,81 +108,137 @@ int main(void)
   I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
   I2S_Init(SPI2, &I2S_InitStructure);
 
-  /* Enable the I2S3 TxE interrupt */
-  SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
-
-  /* Enable the I2S2 RxNE interrupt */
-  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
-
   /* Enable the I2S2 */
   I2S_Cmd(SPI2, ENABLE);
 
   /* Enable the I2S3 */
   I2S_Cmd(SPI3, ENABLE);
 
-  /* Wait the end of communication */
-  while (RxIdx < 32)
-  {}
+  /* Begin the communication in I2S mode */
+  while (RxIdx < BufferSize)
+  {
+    /* Wait the Tx buffer to be empty */
+    while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
+    {}
+    /* Send a data from I2S3 */
+    SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
+
+    /* Wait the Rx buffer to be full */
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
+    {}
+    /* Store the I2S2 received data in the relative data table */
+    I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
+  }
 
-  TransferStatus1 = Buffercmp(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
+  TransferStatus1 = Buffercmp((uint16_t *)I2S2_Buffer_Rx, I2S3_Buffer_Tx, BufferSize);
   /* TransferStatus1 = PASSED, if the data transmitted from I2S3 and received by
-                               I2S2 are the same
+                               I2S2 are the same 
      TransferStatus1 = FAILED, if the data transmitted from I2S3 and received by
                                I2S2 are different */
+
+  /* Reset TxIdx, RxIdx indexes */
+  TxIdx = 0;
+  RxIdx = 0;
   
-  /* Reinitialize the buffers */
-  for (RxIdx = 0; RxIdx < 32; RxIdx++)
+  /* Switch to SPI mode communication ----------------------------------------*/
+  /* SPI3 configuration */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_1Line_Tx;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(SPI3, &SPI_InitStructure);
+
+  /* SPI2 configuration ------------------------------------------------------*/
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_RxOnly;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
+  SPI_Init(SPI2, &SPI_InitStructure);
+
+  /* Enable SPI2 */
+  SPI_Cmd(SPI2, ENABLE);
+  /* Enable SPI3 */
+  SPI_Cmd(SPI3, ENABLE);
+
+  /* Begin the communication in SPI mode */
+  while (RxIdx < BufferSize)
   {
-    I2S2_Buffer_Rx[RxIdx] = 0;
+    /* Wait the Tx buffer to be empty */
+    while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
+    {}
+    /* Send a data from SPI3 */
+    SPI_I2S_SendData(SPI3, SPI3_Buffer_Tx[TxIdx++]);
+
+    /* Wait the Rx buffer to be full */
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
+    {}
+    /* Store the SPI2 received data in the relative data table */
+    SPI2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
   }
-  TxIdx = 0;
-  RxIdx = 0;
 
-  SPI_I2S_DeInit(SPI3);
-  SPI_I2S_DeInit(SPI2);  
-  
-  /* I2S peripheral configuration */
-  I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
-  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_24b;
-  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-  I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_16k;
-  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  TransferStatus2 = Buffercmp((uint16_t *)SPI2_Buffer_Rx, SPI3_Buffer_Tx, BufferSize);
+  /* TransferStatus2 = PASSED, if the data transmitted from SPI3 and received by
+                               SPI2 are the same
+     TransferStatus2 = FAILED, if the data transmitted from SPI3 and received by
+                               SPI2 are different */
 
-  /* I2S3 Master Transmitter to I2S2 Slave Receiver communication -----------*/
+  /* Reset TxIdx, RxIdx indexes and receive table values */
+  for (TxIdx = 0; TxIdx < BufferSize; TxIdx++)
+  {
+    I2S2_Buffer_Rx[TxIdx] = 0;
+  }
+  
+  TxIdx = 0;
+  RxIdx = 0;
+      
+  /* I2S3 Slave Transmitter to I2S2 Master Receiver communication ------------*/
   /* I2S3 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+  I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
   I2S_Init(SPI3, &I2S_InitStructure);
 
   /* I2S2 configuration */
-  I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveRx;
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
   I2S_Init(SPI2, &I2S_InitStructure);
 
-  /* Enable the I2S3 TxE interrupt */
-  SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE);
+  /* Wait the Tx buffer to be empty */
+  while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
+  {}
+  /* Prepare the first data to be sent from the slave */
+  SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
 
-  /* Enable the I2S2 RxNE interrupt */
-  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_RXNE, ENABLE);
+  /* Enable the I2S3 */
+  I2S_Cmd(SPI3, ENABLE);
 
   /* Enable the I2S2 */
   I2S_Cmd(SPI2, ENABLE);
 
-  /* Enable the I2S3 */
-  I2S_Cmd(SPI3, ENABLE);
-
-  /* Wait the end of communication */
-  while (RxIdx < 32)
+  /* Begin the communication in I2S mode */
+  while (RxIdx < BufferSize)
   {
+    /* Wait the Rx buffer to be full */
+    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET)
+    {}
+    /* Store the I2S2 received data in the relative data table */
+    I2S2_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI2);
+
+    /* Wait the Tx buffer to be empty */
+    while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET)
+    {}
+    /* Send a data from I2S3 */
+    SPI_I2S_SendData(SPI3, I2S3_Buffer_Tx[TxIdx++]);
   }
 
-  TransferStatus2 = Buffercmp24bits(I2S2_Buffer_Rx, (uint16_t*)I2S3_Buffer_Tx, 32);
-  /* TransferStatus2 = PASSED, if the data transmitted from I2S3 and received by
+  TransferStatus3 = Buffercmp((uint16_t *)I2S2_Buffer_Rx, I2S3_Buffer_Tx, BufferSize);
+  /* TransferStatus3 = PASSED, if the data transmitted from I2S3 and received by
                                I2S2 are the same
-     TransferStatus2 = FAILED, if the data transmitted from I2S3 and received by
-                               I2S2 are different */     
-
+     TransferStatus3 = FAILED, if the data transmitted from I2S3 and received by
+                               I2S2 are different */
+ 
   while (1)
-  {
-  }
+  {}
 }
 
 /**
@@ -234,7 +298,7 @@ void RCC_Configuration(void)
     RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5);
     RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9);
 
-    /* PLL3 configuration: PLL3CLK = (HSE / 5) * 11 => PLL3_VCO = 110 MHz */
+    /* PPL3 configuration: PLL3CLK = (HSE / 5) * 11 = PLL3_VCO = 110 MHz */
     RCC_PLL3Config(RCC_PLL3Mul_11);
     /* Enable PLL3 */
     RCC_PLL3Cmd(ENABLE);    
@@ -266,7 +330,7 @@ void RCC_Configuration(void)
     }
   }  
   
-  /* Enable peripheral clocks ------------------------------------------------*/
+  /* Enable peripheral clocks --------------------------------------------------*/
   /* GPIOA, GPIOB and AFIO clocks enable */
   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
                          RCC_APB2Periph_AFIO, ENABLE);
@@ -274,10 +338,10 @@ void RCC_Configuration(void)
 #ifdef USE_STM3210C_EVAL 
   /* GPIOC Clock enable (for the SPI3 remapped pins)  */
   RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);  
-#endif /* USE_STM3210C_EVAL */
+#endif /* USE_STM3210C_EVAL */  
   
-  /* SPI3 and SPI2 clocks enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3 | RCC_APB1Periph_SPI2, ENABLE);
+  /* SPI2 and SPI3 clocks enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3, ENABLE);  
 }
 
 /**
@@ -299,7 +363,7 @@ void GPIO_Configuration(void)
   /* Configure SPI2 pins: CK, WS and SD ---------------------------------*/
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
   GPIO_Init(GPIOB, &GPIO_InitStructure);
 
 #ifdef USE_STM3210C_EVAL
@@ -309,8 +373,7 @@ void GPIO_Configuration(void)
   
   /* Configure SPI3 pins: CK and SD ------------------------------------*/
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_12;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);  
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
 
   /* Configure SPI3 pins: WS -------------------------------------------*/
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
@@ -320,38 +383,13 @@ void GPIO_Configuration(void)
   
   /* Configure SPI3 pins: CK and SD ------------------------------------*/
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
   GPIO_Init(GPIOB, &GPIO_InitStructure);
 
   /* Configure SPI3 pins: WS -------------------------------------------*/
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
   GPIO_Init(GPIOA, &GPIO_InitStructure);
   
-#endif /* USE_STM3210C_EVAL */  
-}
-
-/**
-  * @brief  Configure the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-
-  /* SPI3 IRQ Channel configuration */
-  NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* SPI2 IRQ channel configuration */
-  NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_Init(&NVIC_InitStructure);
+#endif /* USE_STM3210C_EVAL */ 
 }
 
 /**
@@ -377,32 +415,6 @@ TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLeng
   return PASSED;
 }
 
-/**
-  * @brief  Compares two buffers in 24 bits data format.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp24bits(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      if (*pBuffer1 != (*pBuffer2 & 0xFF00))
-      {
-        return FAILED;
-      }
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
 #ifdef  USE_FULL_ASSERT
 
 /**
@@ -430,6 +442,6 @@ void assert_failed(uint8_t* file, uint32_t line)
 
 /**
   * @}
-  */
+  */ 
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/readme.txt
new file mode 100644
index 0000000..a5b4d23
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/readme.txt
@@ -0,0 +1,120 @@
+/**
+  @page I2S_SPI_I2S_Switch SPI_I2S_Switch example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    I2S/SPI_I2S_Switch/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the SPI_I2S_Switch example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example provides a description of how to set a communication between two
+SPIs in I2S mode, and how to switch between SPI and I2S modes, performing a 
+transfer from Master to Slave in I2S modes then a transfer from master to slave 
+in SPI mode and finally a transfer from Slave to Master in I2S mode.
+
+I2S2 is configured as master transmitter and I2S3 as slave receiver and both are 
+in Philips standard configuration with 16bit data size in 32bit packet length 
+and 48KHz audio frequency.
+
+In the first phase, the master I2S2 starts the I2S2_Buffer_Tx transfer while the 
+slave I2S3 receives and loads the values in I2S3_Buffer_Rx. Once the transfer is 
+completed a comparison is done and TransferStatus1 gives the data transfer status 
+where it is PASSED if transmitted and received data are the same otherwise it is 
+FAILED.
+
+In the second step, both peripherals are configured in SPI modes (simplex 
+communication) and SPI2_Buffer_Tx transfer is performed in simplex mode from SPI2 to
+SPI3.Once the transfer is completed a comparison is done and TransferStatus2 gives 
+the data transfer status where it is PASSED if transmitted and received data are 
+the same otherwise it is FAILED.
+As the master/slave mode is managed by software (the master is the clock (CK and WS) 
+generator), this allows to I2S2 to become slave transmitter and I2S3 to become master 
+receiver without hardware modification. 
+
+In the third step, the slave I2S2 prepares the first data to be sent before the 
+master is enabled. Once the master is enabled, the clocks are released from the 
+master and the data are released on the slave. Once the transfer is completed 
+a comparison is done and TransferStatus3 gives the data transfer status where it 
+is PASSED if transmitted and received data are the same otherwise it is FAILED.
+
+@par Directory contents 
+
+  - I2S/SPI_I2S_Switch/stm32f10x_conf.h     Library Configuration file
+  - I2S/SPI_I2S_Switch/stm32f10x_it.c       Interrupt handlers
+  - I2S/SPI_I2S_Switch/stm32f10x_it.h       Header for stm32f10x_it.c
+  - I2S/SPI_I2S_Switch/main.c               Main program
+  - I2S/SPI_I2S_Switch/system_stm32f10x.c   STM32F10x system source file  
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x High-Density, XL-Density and Connectivity Line 
+    Devices.
+  
+  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
+    and XL-Density) and STM3210C-EVAL (Connectivity Line) evaluation boards 
+    and can be easily tailored to any other supported device and development board.
+
+  - STM3210C-EVAL Set-up 
+     - Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.04) pin
+     - Connect I2S2 CK (PB.13) pin to I2S3 CK (PC.10) pin
+     - Connect I2S2 SD (PB.15) pin to I2S3 SD (PC.12) pin
+
+  - STM3210E-EVAL Set-up 
+     - Connect I2S2 WS (PB.12) pin to I2S3 WS (PA.15) pin
+     - Connect I2S2 CK (PB.13) pin to I2S3 CK (PB.03) pin
+     - Connect I2S2 SD (PB.15) pin to I2S3 SD (PB.05) pin
+
+Since some SPI3/I2S3 pins are shared with JTAG pins (SPI3_NSS/I2S3_WS with JTDI 
+and SPI3_SCK/I2S3_CK with JTDO), they are not controlled by the I/O controller
+and are reserved for JTAG usage (after each Reset).
+For this purpose prior to configure the SPI3/I2S3 pins: 
+- For STM32F10x High-Density devices, the user has to disable the JTAG and use 
+  the SWD interface (when debugging the application), or disable both JTAG/SWD 
+  interfaces (for standalone application).
+- For STM32F10x Connectivity Line devices, the user can use the solution above 
+  (SWD or disable bothe JTAG and SWD), or it is possible to remap the SPI3 pins 
+  on {PC10, PC11, PC12, PA4} GPIO pins in order to avoid the conflict with JTAG 
+  pins (and it is possible in this case to use JTAG interface). This remap is 
+  used for STM3210C-EVAL evaluation boards in this example.
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes. 
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c
index 3a0c3d5..3a0c3d5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h
index 9a9d957..9a9d957 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c
index e34f002..e34f002 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/SPI_I2S_Switch/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt
index 667f562..667f562 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h
index 0424491..0424491 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
new file mode 100644
index 0000000..5788ef4
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.c
@@ -0,0 +1,233 @@
+/**
+  ******************************************************************************
+  * @file    IWDG/IWDG_Reset/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup IWDG_Reset
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern __IO uint32_t TimingDelay;
+__IO uint16_t IC1ReadValue1 = 0, IC1ReadValue2 = 0;
+__IO uint16_t CaptureNumber = 0;
+__IO uint32_t Capture = 0;
+extern uint32_t LsiFreq;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {}
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+  TimingDelay--;
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles External lines 9 to 5 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI9_5_IRQHandler(void)
+{
+  if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {
+    /* Clear the Key Button EXTI Line Pending Bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+    
+    /* As the following address is invalid (not mapped), a Hardfault exception
+	  will be generated with an infinite loop and when the IWDG counter reaches 0
+    the IWDG reset occurs */
+ 	  *(__IO uint32_t *) 0x000000FF = 0xFF;
+  }
+}
+
+/**
+  * @brief  This function handles TIM5 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM5_IRQHandler(void)
+{
+  if (TIM_GetITStatus(TIM5, TIM_IT_CC4) != RESET)
+  {    
+    if(CaptureNumber == 0)
+    {
+      /* Get the Input Capture value */
+      IC1ReadValue1 = TIM_GetCapture4(TIM5);
+    }
+    else if(CaptureNumber == 1)
+    {
+      /* Get the Input Capture value */
+      IC1ReadValue2 = TIM_GetCapture4(TIM5); 
+      
+      /* Capture computation */
+      if (IC1ReadValue2 > IC1ReadValue1)
+      {
+        Capture = (IC1ReadValue2 - IC1ReadValue1); 
+      }
+      else
+      {
+        Capture = ((0xFFFF - IC1ReadValue1) + IC1ReadValue2); 
+      }
+      /* Frequency computation */ 
+      LsiFreq = (uint32_t) SystemCoreClock / Capture;
+      LsiFreq *= 8;
+    }
+    
+    CaptureNumber++;
+    
+    /* Clear TIM5 Capture compare interrupt pending bit */
+    TIM_ClearITPendingBit(TIM5, TIM_IT_CC4);
+  }
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h
index d961b1d..0f461ca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    PWR/STANDBY/stm32f10x_it.h 
+  * @file    IWDG/IWDG_Reset/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -17,7 +17,7 @@
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F10x_IT_H
@@ -41,6 +41,7 @@ void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
 void EXTI9_5_IRQHandler(void);
+void TIM5_IRQHandler(void);
 
 #endif /* __STM32F10x_IT_H */
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c
index 1b359b2..1b359b2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/readme.txt
new file mode 100644
index 0000000..f7eea16
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/readme.txt
@@ -0,0 +1,132 @@
+/**
+  @page Lib_DEBUG_RunTime_Check Lib_DEBUG Run Time Checking example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    Lib_DEBUG/RunTime_Check/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the Lib_DEBUG Run Time Checking example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example demonstrates how to declare a dynamic peripherals pointers used for
+Debug mode.  
+
+To use Debug mode you have to add the stm32f10x_ip_dbg.c file to your application.
+This creates a pointer to the peripheral structure in SRAM. Debugging consequently
+becomes easier and all register settings can be obtained by dumping a peripheral 
+variable.
+
+When the "USE_FULL_ASSERT" label is uncommented (in stm32f10x_conf.h file),
+the assert_param macro is expanded and runtime checking is enabled in the firmware
+library code. The runtime checking allows checking that all the library functions
+input value lies within the parameter allowed values.
+
+The associated program simulates wrong parameter passed to library function and the
+source of the error is printed on HyperTerminal (through USART).
+
+@note
+The Debug mode increases the code size and reduces the code performance. For this
+reason, it is recommended to used it only when debugging the application and to
+remove it from the final application code.
+
+
+@par Directory contents 
+
+  - Lib_DEBUG/RunTime_Check/stm32f10x_conf.h             Library Configuration file
+  - Lib_DEBUG/RunTime_Check/stm32f10x_it.c               Interrupt handlers
+  - Lib_DEBUG/RunTime_Check/stm32f10x_it.h               Header for stm32f10x_it.c
+  - Lib_DEBUG/RunTime_Check/main.c                       Main program
+  - Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c           Peripherals pointers initialization
+  - Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h           Header for lib_dbg.c 
+  - Lib_DEBUG/RunTime_Check/system_stm32f10x.c           STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
+    Value line, Medium-Density, XL-Density, High-Density Value line, Medium-Density 
+    Value line, Low-Density and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
+    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
+    (Medium-Density) evaluation boards and can be easily tailored to any other 
+    supported device and development board.
+    To select the STMicroelectronics evaluation board used to run the example, 
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+
+  - STM32100E-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN10 and PC serial port.
+      
+  - STM32100B-EVAL Set-up  
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN10 and PC serial port.
+      
+  - STM3210C-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6 and PC serial port.
+      @note Make sure that jumpers JP19 and JP18 are open.      
+    
+  - STM3210E-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN12 and PC serial port.
+
+  - STM3210B-EVAL Set-up  
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6 and PC serial port.
+ 
+  - Hyperterminal configuration:
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - No parity
+    - BaudRate = 115200 baud
+    - flow control: None
+
+      
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Add the required example files
+   - stm32f10x_ip_dbg.c
+
+@note 
+  - The free Lite version of TrueSTUDIO do not support printf() redirection.
+    For more information, see "note.txt" under "STM32F10x_StdPeriph_Template\TrueSTUDIO".
+     
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes. 
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c
new file mode 100644
index 0000000..7e5e51b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c
@@ -0,0 +1,282 @@
+/**
+  ******************************************************************************
+  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file provides all peripherals pointers initialization.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_ip_dbg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup Lib_DEBUG_RunTime_Check
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_TypeDef             *TIM2_DBG;
+TIM_TypeDef             *TIM3_DBG;
+TIM_TypeDef             *TIM4_DBG;
+TIM_TypeDef             *TIM5_DBG;
+TIM_TypeDef             *TIM6_DBG;
+TIM_TypeDef             *TIM7_DBG;
+RTC_TypeDef             *RTC_DBG;
+WWDG_TypeDef            *WWDG_DBG;
+IWDG_TypeDef            *IWDG_DBG;
+SPI_TypeDef             *SPI2_DBG;
+SPI_TypeDef             *SPI3_DBG;
+USART_TypeDef           *USART2_DBG;
+USART_TypeDef           *USART3_DBG;
+USART_TypeDef           *UART4_DBG;
+USART_TypeDef           *UART5_DBG;
+I2C_TypeDef             *I2C1_DBG;
+I2C_TypeDef             *I2C2_DBG;
+CAN_TypeDef             *CAN1_DBG;
+BKP_TypeDef             *BKP_DBG;
+PWR_TypeDef             *PWR_DBG;
+DAC_TypeDef             *DAC_DBG;
+CEC_TypeDef             *CEC_DBG;
+AFIO_TypeDef            *AFIO_DBG;
+EXTI_TypeDef            *EXTI_DBG;
+GPIO_TypeDef            *GPIOA_DBG;
+GPIO_TypeDef            *GPIOB_DBG;
+GPIO_TypeDef            *GPIOC_DBG;
+GPIO_TypeDef            *GPIOD_DBG;
+GPIO_TypeDef            *GPIOE_DBG;
+GPIO_TypeDef            *GPIOF_DBG;
+GPIO_TypeDef            *GPIOG_DBG;
+ADC_TypeDef             *ADC1_DBG;
+ADC_TypeDef             *ADC2_DBG;
+TIM_TypeDef             *TIM1_DBG;
+SPI_TypeDef             *SPI1_DBG;
+TIM_TypeDef             *TIM8_DBG;
+USART_TypeDef           *USART1_DBG;
+ADC_TypeDef             *ADC3_DBG;
+TIM_TypeDef             *TIM15_DBG;
+TIM_TypeDef             *TIM16_DBG;
+TIM_TypeDef             *TIM17_DBG;
+SDIO_TypeDef            *SDIO_DBG;
+DMA_TypeDef             *DMA1_DBG;
+DMA_TypeDef             *DMA2_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel1_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel2_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel3_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel4_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel5_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel6_DBG;
+DMA_Channel_TypeDef     *DMA1_Channel7_DBG;
+DMA_Channel_TypeDef     *DMA2_Channel1_DBG;
+DMA_Channel_TypeDef     *DMA2_Channel2_DBG;
+DMA_Channel_TypeDef     *DMA2_Channel3_DBG;
+DMA_Channel_TypeDef     *DMA2_Channel4_DBG;
+DMA_Channel_TypeDef     *DMA2_Channel5_DBG;
+RCC_TypeDef             *RCC_DBG;
+CRC_TypeDef             *CRC_DBG;
+FLASH_TypeDef           *FLASH_DBG;
+OB_TypeDef              *OB_DBG;  
+FSMC_Bank1_TypeDef      *FSMC_Bank1_DBG;
+FSMC_Bank1E_TypeDef     *FSMC_Bank1E_DBG;
+FSMC_Bank2_TypeDef      *FSMC_Bank2_DBG;
+FSMC_Bank3_TypeDef      *FSMC_Bank3_DBG;
+FSMC_Bank4_TypeDef      *FSMC_Bank4_DBG;
+DBGMCU_TypeDef          *DBGMCU_DBG;
+SysTick_Type            *SysTick_DBG;
+NVIC_Type               *NVIC_DBG;
+SCB_Type                *SCB_DBG;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  This function initialize peripherals pointers.
+  * @param  None
+  * @retval None
+  */
+void debug(void)
+{
+/************************************* ADC ************************************/
+  ADC1_DBG = (ADC_TypeDef *)  ADC1_BASE;
+
+  ADC2_DBG = (ADC_TypeDef *)  ADC2_BASE;
+
+  ADC3_DBG = (ADC_TypeDef *)  ADC3_BASE;
+
+/************************************* BKP ************************************/
+  BKP_DBG = (BKP_TypeDef *)  BKP_BASE;
+
+/************************************* CAN ************************************/			
+  CAN1_DBG = (CAN_TypeDef *)  CAN1_BASE;			
+
+/************************************* CEC ************************************/			
+  CEC_DBG = (CEC_TypeDef *)  CEC_BASE;	
+  
+/************************************* CRC ************************************/
+  CRC_DBG = (CRC_TypeDef *)  CRC_BASE;
+
+/************************************* DAC ************************************/
+  DAC_DBG = (DAC_TypeDef *)  DAC_BASE;
+
+/************************************* DBGMCU**********************************/
+  DBGMCU_DBG = (DBGMCU_TypeDef *)  DBGMCU_BASE;
+
+
+/************************************* DMA ************************************/
+  DMA1_DBG = (DMA_TypeDef *)  DMA1_BASE;
+  DMA2_DBG = (DMA_TypeDef *)  DMA2_BASE;
+
+  DMA1_Channel1_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel1_BASE;
+
+  DMA1_Channel2_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel2_BASE;
+
+  DMA1_Channel3_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel3_BASE;
+
+  DMA1_Channel4_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel4_BASE;
+
+  DMA1_Channel5_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel5_BASE;
+
+  DMA1_Channel6_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel6_BASE;
+
+  DMA1_Channel7_DBG = (DMA_Channel_TypeDef *)  DMA1_Channel7_BASE;
+
+  DMA2_Channel1_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel1_BASE;
+
+  DMA2_Channel2_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel2_BASE;
+
+  DMA2_Channel3_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel3_BASE;
+
+  DMA2_Channel4_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel4_BASE;
+
+  DMA2_Channel5_DBG = (DMA_Channel_TypeDef *)  DMA2_Channel5_BASE;
+
+/************************************* EXTI ***********************************/
+  EXTI_DBG = (EXTI_TypeDef *)  EXTI_BASE;
+
+/************************************* FLASH and Option Bytes *****************/
+  FLASH_DBG = (FLASH_TypeDef *)  FLASH_R_BASE;
+  OB_DBG = (OB_TypeDef *)        OB_BASE;
+
+/************************************* FSMC ***********************************/
+  FSMC_Bank1_DBG = (FSMC_Bank1_TypeDef *)    FSMC_Bank1_R_BASE;
+  FSMC_Bank1E_DBG = (FSMC_Bank1E_TypeDef *)  FSMC_Bank1E_R_BASE;  
+  FSMC_Bank2_DBG = (FSMC_Bank2_TypeDef *)    FSMC_Bank2_R_BASE; 
+  FSMC_Bank3_DBG = (FSMC_Bank3_TypeDef *)    FSMC_Bank3_R_BASE;
+  FSMC_Bank4_DBG = (FSMC_Bank4_TypeDef *)    FSMC_Bank4_R_BASE;
+
+/************************************* GPIO ***********************************/
+  GPIOA_DBG = (GPIO_TypeDef *)  GPIOA_BASE;
+
+  GPIOB_DBG = (GPIO_TypeDef *)  GPIOB_BASE;
+
+  GPIOC_DBG = (GPIO_TypeDef *)  GPIOC_BASE;
+
+  GPIOD_DBG = (GPIO_TypeDef *)  GPIOD_BASE;
+
+  GPIOE_DBG = (GPIO_TypeDef *)  GPIOE_BASE;
+
+  GPIOF_DBG = (GPIO_TypeDef *)  GPIOF_BASE;
+
+  GPIOG_DBG = (GPIO_TypeDef *)  GPIOG_BASE;
+  
+  AFIO_DBG = (AFIO_TypeDef *)  AFIO_BASE;
+
+/************************************* I2C ************************************/
+  I2C1_DBG = (I2C_TypeDef *)  I2C1_BASE;
+
+  I2C2_DBG = (I2C_TypeDef *)  I2C2_BASE;
+
+/************************************* IWDG ***********************************/
+  IWDG_DBG = (IWDG_TypeDef *) IWDG_BASE;
+
+/************************************* NVIC ***********************************/
+  NVIC_DBG = (NVIC_Type *)  NVIC_BASE;
+  SCB_DBG = (SCB_Type *)  SCB_BASE;
+
+/************************************* PWR ************************************/
+  PWR_DBG = (PWR_TypeDef *)  PWR_BASE;
+
+/************************************* RCC ************************************/
+  RCC_DBG = (RCC_TypeDef *)  RCC_BASE;
+
+/************************************* RTC ************************************/
+  RTC_DBG = (RTC_TypeDef *)  RTC_BASE;
+
+/************************************* SDIO ***********************************/
+  SDIO_DBG = (SDIO_TypeDef *)  SDIO_BASE;
+
+/************************************* SPI ************************************/
+  SPI1_DBG = (SPI_TypeDef *)  SPI1_BASE;
+
+  SPI2_DBG = (SPI_TypeDef *)  SPI2_BASE;
+
+  SPI3_DBG = (SPI_TypeDef *)  SPI3_BASE;
+
+/************************************* SysTick ********************************/
+  SysTick_DBG = (SysTick_Type *)  SysTick_BASE;
+
+/************************************* TIM ************************************/
+  TIM1_DBG = (TIM_TypeDef *)  TIM1_BASE;
+
+  TIM2_DBG = (TIM_TypeDef *)  TIM2_BASE;
+
+  TIM3_DBG = (TIM_TypeDef *)  TIM3_BASE;
+
+  TIM4_DBG = (TIM_TypeDef *)  TIM4_BASE;
+
+  TIM5_DBG = (TIM_TypeDef *)  TIM5_BASE;
+
+  TIM6_DBG = (TIM_TypeDef *)  TIM6_BASE;
+
+  TIM7_DBG = (TIM_TypeDef *)  TIM7_BASE;
+
+  TIM8_DBG = (TIM_TypeDef *)  TIM8_BASE;
+  
+  TIM15_DBG = (TIM_TypeDef *)  TIM15_BASE;
+
+  TIM16_DBG = (TIM_TypeDef *)  TIM16_BASE;
+
+  TIM17_DBG = (TIM_TypeDef *)  TIM17_BASE;      
+
+/************************************* USART **********************************/
+  USART1_DBG = (USART_TypeDef *) USART1_BASE;
+
+  USART2_DBG = (USART_TypeDef *) USART2_BASE;
+
+  USART3_DBG = (USART_TypeDef *) USART3_BASE;
+
+  UART4_DBG = (USART_TypeDef *) UART4_BASE;
+
+  UART5_DBG = (USART_TypeDef *) UART5_BASE;
+
+/************************************* WWDG ***********************************/
+  WWDG_DBG = (WWDG_TypeDef *)  WWDG_BASE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
index 84bc179..84bc179 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_ip_dbg.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c
index 2deaafa..67c2c50 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/TIM10_PWMOutput/stm32f10x_it.c 
+  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,9 +28,9 @@
   * @{
   */
 
-/** @addtogroup TIM10_PWMOutput
+/** @addtogroup Lib_DEBUG_RunTime_Check
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -61,7 +61,8 @@ void HardFault_Handler(void)
 {
   /* Go to infinite loop when Hard Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -73,7 +74,8 @@ void MemManage_Handler(void)
 {
   /* Go to infinite loop when Memory Manage exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -85,7 +87,8 @@ void BusFault_Handler(void)
 {
   /* Go to infinite loop when Bus Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -97,24 +100,27 @@ void UsageFault_Handler(void)
 {
   /* Go to infinite loop when Usage Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
-  * @brief  This function handles Debug Monitor exception.
+  * @brief  This function handles SVCall exception.
   * @param  None
   * @retval None
   */
-void DebugMon_Handler(void)
-{}
+void SVC_Handler(void)
+{
+}
 
 /**
-  * @brief  This function handles SVCall exception.
+  * @brief  This function handles Debug Monitor exception.
   * @param  None
   * @retval None
   */
-void SVC_Handler(void)
-{}
+void DebugMon_Handler(void)
+{
+}
 
 /**
   * @brief  This function handles PendSV_Handler exception.
@@ -122,7 +128,8 @@ void SVC_Handler(void)
   * @retval None
   */
 void PendSV_Handler(void)
-{}
+{
+}
 
 /**
   * @brief  This function handles SysTick Handler.
@@ -130,7 +137,8 @@ void PendSV_Handler(void)
   * @retval None
   */
 void SysTick_Handler(void)
-{}
+{
+}
 
 /******************************************************************************/
 /*                 STM32F10x Peripherals Interrupt Handlers                   */
@@ -150,10 +158,10 @@ void SysTick_Handler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h
new file mode 100644
index 0000000..aac63a9
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_it.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c
new file mode 100644
index 0000000..8de9a7b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    Lib_DEBUG/RunTime_Check/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html
index 643c366..643c366 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Library_Examples.html
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
index f056195..f056195 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt
index 3a1b997..3a1b997 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
index 2d4a7ed..9766aca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/TimeBase/stm32f10x_it.c 
+  * @file    NVIC/DMA_WFIMode/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -19,28 +19,30 @@
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
+#include "stm32_eval.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup TIM_TimeBase
+/** @addtogroup NVIC_DMA_WFIMode
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-uint16_t capture = 0;
-extern __IO uint16_t CCR1_Val;
-extern __IO uint16_t CCR2_Val;
-extern __IO uint16_t CCR3_Val;
-extern __IO uint16_t CCR4_Val;
+uint8_t TestStatus = 0;
+uint16_t SRC_Buffer[10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39};
+extern uint16_t DST_Buffer[10];
+extern __IO uint32_t LowPowerMode;
+extern uint8_t Buffercmp16(uint16_t*, uint16_t*, uint16_t);
+extern void DMA_Configuration(void);
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -67,7 +69,8 @@ void HardFault_Handler(void)
 {
   /* Go to infinite loop when Hard Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -79,7 +82,8 @@ void MemManage_Handler(void)
 {
   /* Go to infinite loop when Memory Manage exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -91,7 +95,8 @@ void BusFault_Handler(void)
 {
   /* Go to infinite loop when Bus Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -103,24 +108,27 @@ void UsageFault_Handler(void)
 {
   /* Go to infinite loop when Usage Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
-  * @brief  This function handles Debug Monitor exception.
+  * @brief  This function handles SVCall exception.
   * @param  None
   * @retval None
   */
-void DebugMon_Handler(void)
-{}
+void SVC_Handler(void)
+{
+}
 
 /**
-  * @brief  This function handles SVCall exception.
+  * @brief  This function handles Debug Monitor exception.
   * @param  None
   * @retval None
   */
-void SVC_Handler(void)
-{}
+void DebugMon_Handler(void)
+{
+}
 
 /**
   * @brief  This function handles PendSV_Handler exception.
@@ -128,7 +136,8 @@ void SVC_Handler(void)
   * @retval None
   */
 void PendSV_Handler(void)
-{}
+{
+}
 
 /**
   * @brief  This function handles SysTick Handler.
@@ -136,55 +145,76 @@ void PendSV_Handler(void)
   * @retval None
   */
 void SysTick_Handler(void)
-{}
+{
+}
 
 /******************************************************************************/
 /*            STM32F10x Peripherals Interrupt Handlers                        */
 /******************************************************************************/
 
 /**
-  * @brief  This function handles TIM2 global interrupt request.
+  * @brief  This function handles DMA1 Channel 5 interrupt request.
   * @param  None
   * @retval None
   */
-void TIM2_IRQHandler(void)
+void DMA1_Channel5_IRQHandler(void)
 {
-  if (TIM_GetITStatus(TIM2, TIM_IT_CC1) != RESET)
+  if(DMA_GetITStatus(DMA1_IT_TC5))
   {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC1);
-
-    /* Pin PC.06 toggling with frequency = 73.24 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_6, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_6)));
-    capture = TIM_GetCapture1(TIM2);
-    TIM_SetCompare1(TIM2, capture + CCR1_Val);
+    DMA_ClearITPendingBit(DMA1_IT_GL5);
+
+    /* Check the received buffer */
+    TestStatus = Buffercmp16(SRC_Buffer, DST_Buffer, 10);
+
+    if(TestStatus == 0)
+    {
+      STM_EVAL_LEDToggle(LED2);
+    }
+    else
+    {
+      STM_EVAL_LEDToggle(LED3);
+    }
   }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC2) != RESET)
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC2);
+}
 
-    /* Pin PC.07 toggling with frequency = 109.8 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_7, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_7)));
-    capture = TIM_GetCapture2(TIM2);
-    TIM_SetCompare2(TIM2, capture + CCR2_Val);
-  }
-  else if (TIM_GetITStatus(TIM2, TIM_IT_CC3) != RESET)
+/**
+  * @brief  This function handles DMA1 Channel 6 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void DMA1_Channel6_IRQHandler(void)
+{
+  if(DMA_GetITStatus(DMA1_IT_TC6))
   {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC3);
-
-    /* Pin PC.08 toggling with frequency = 219.7 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_8, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_8)));
-    capture = TIM_GetCapture3(TIM2);
-    TIM_SetCompare3(TIM2, capture + CCR3_Val);
+    DMA_ClearITPendingBit(DMA1_IT_GL6);
+
+    /* Check the received buffer */
+    TestStatus = Buffercmp16(SRC_Buffer, DST_Buffer, 10);
+
+    if(TestStatus == 0)
+    {
+      STM_EVAL_LEDToggle(LED2);
+    }
+    else
+    {
+      STM_EVAL_LEDToggle(LED3);
+    }
   }
-  else
-  {
-    TIM_ClearITPendingBit(TIM2, TIM_IT_CC4);
+}
 
-    /* Pin PC.09 toggling with frequency = 439.4 Hz */
-    GPIO_WriteBit(GPIOC, GPIO_Pin_9, (BitAction)(1 - GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_9)));
-    capture = TIM_GetCapture4(TIM2);
-    TIM_SetCompare4(TIM2, capture + CCR4_Val);
-  }
+/**
+  * @brief  This function handles External lines 9 to 5 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI9_5_IRQHandler(void)
+{
+  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  
+    LowPowerMode = 1;
+  }  
 }
 
 /******************************************************************************/
@@ -205,10 +235,10 @@ void TIM2_IRQHandler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h
new file mode 100644
index 0000000..b6fd2e1
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_it.h
@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file    NVIC/DMA_WFIMode/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Channel5_IRQHandler(void);
+void DMA1_Channel6_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c
index 4b0bf3e..4b0bf3e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c
new file mode 100644
index 0000000..faa11de
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/main.c
@@ -0,0 +1,219 @@
+/**
+  ******************************************************************************
+  * @file    NVIC/IRQ_Mask/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup IRQ_Mask
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+void TIM_Config(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */
+
+  /* Initialize Leds mounted on STM3210X-EVAL board */
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+
+  /* Initialize the KEY and WAKEUP buttons mounted on STM3210X-EVAL board */
+  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO);
+  STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI);
+    
+  /* TIM configuration -------------------------------------------------------*/
+  TIM_Config();
+
+  while (1)
+  { 
+    /* Wait until KEY button is pressed. */
+    while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET)
+    {
+    }
+    while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET)
+    {
+    }
+
+    /* This instruction raises the execution priority to 0. This prevents all 
+       exceptions with configurable priority from activating, other than through 
+       the HardFault fault escalation mechanism. */
+    __disable_irq();
+
+    /* Turn LED4 ON */
+    STM_EVAL_LEDOn(LED4);
+
+    /* Wait until KEY button is pressed. */
+    while(STM_EVAL_PBGetState(BUTTON_KEY) == RESET)
+    {
+    }
+    while(STM_EVAL_PBGetState(BUTTON_KEY) != RESET)
+    {
+    }
+
+    /* This instruction will allow all exceptions with configurable priority to 
+       be activated. */
+    __enable_irq();
+
+    /* Turn LED4 OFF */
+    STM_EVAL_LEDOff(LED4);
+  }
+}
+
+/**
+  * @brief  Configures the used Timers.
+  * @param  None
+  * @retval None
+  */
+void TIM_Config(void)
+{ 
+  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+  TIM_OCInitTypeDef  TIM_OCInitStructure;
+  NVIC_InitTypeDef  NVIC_InitStructure;
+
+  /* Enable TIM2, TIM3 and TIM4 clocks */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
+                         RCC_APB1Periph_TIM4, ENABLE);
+
+  /* TIM2 configuration */
+  TIM_TimeBaseStructure.TIM_Period = 0x4AF;          
+  TIM_TimeBaseStructure.TIM_Prescaler = ((SystemCoreClock/1200) - 1);
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
+  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+  TIM_OCStructInit(&TIM_OCInitStructure);
+  
+  /* Output Compare Timing Mode configuration: Channel1 */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStructure.TIM_Pulse = 0x0;  
+  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
+  
+  /* TIM3 configuration */
+  TIM_TimeBaseStructure.TIM_Period = 0x95F;    
+  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
+  
+  /* Output Compare Timing Mode configuration: Channel1 */
+  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
+  
+  /* TIM4 configuration */
+  TIM_TimeBaseStructure.TIM_Period = 0xE0F;  
+  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+  
+  /* Output Compare Timing Mode configuration: Channel1 */
+  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
+
+  /* Immediate load of TIM2,TIM3 and TIM4 Precaler values */
+  TIM_PrescalerConfig(TIM2, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
+  TIM_PrescalerConfig(TIM3, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
+  TIM_PrescalerConfig(TIM4, ((SystemCoreClock/1200) - 1), TIM_PSCReloadMode_Immediate);
+
+  /* Clear TIM2, TIM3 and TIM4 update pending flags */
+  TIM_ClearFlag(TIM2, TIM_FLAG_Update);
+  TIM_ClearFlag(TIM3, TIM_FLAG_Update);
+  TIM_ClearFlag(TIM4, TIM_FLAG_Update);
+
+  /* Configure two bits for preemption priority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+
+  /* Enable the TIM2 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the TIM3 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable the TIM4 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable TIM2, TIM3 and TIM4 Update interrupts */
+  TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
+  TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE);
+  TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
+
+  /* TIM2, TIM3 and TIM4 enable counters */
+  TIM_Cmd(TIM2, ENABLE);
+  TIM_Cmd(TIM3, ENABLE);
+  TIM_Cmd(TIM4, ENABLE);
+}
+
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt
index 082a709..082a709 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h
index fc54fb1..fc54fb1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c
new file mode 100644
index 0000000..54a55c6
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.c
@@ -0,0 +1,247 @@
+/**
+  ******************************************************************************
+  * @file    NVIC/IRQ_Mask/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup IRQ_Mask
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t index = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles EXTI Lines 0 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  if(EXTI_GetITStatus(WAKEUP_BUTTON_EXTI_LINE) != RESET)
+  {
+    if(index == 0)
+    {
+      /* Configure the BASEPRI register to 0x40 (Preemption priority = 1). 
+         Only IRQ with higher preemption priority than 1 are permitted. 
+         This will mask TIM3 and TIM4 IRQ from generation. */
+      __set_BASEPRI(0x40);
+      index++;
+    }
+    else
+    {
+      /* Configure the BASEPRI register to 0x00 (Preemption priority = 0). 
+         When this BASEPRI register is set to 0, it has no effect on the current 
+         priority.
+         TIM2, TIM3 and TIM4 generation is controlled by NVIC priority registers. */
+      __set_BASEPRI(0x00);
+      index = 0;
+    }
+    /* Clears the SEL Button EXTI line pending bits. */
+    EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE);  
+  }
+} 
+
+/**
+  * @brief  This function handles TIM2 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM2_IRQHandler(void)
+{
+  /* Clear TIM2 update interrupt */
+  TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
+  
+  /* Toggle LED1 */
+  STM_EVAL_LEDToggle(LED1);
+}
+
+/**
+  * @brief  This function handles TIM3 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM3_IRQHandler(void)
+{
+  /* Clear TIM3 update interrupt */
+  TIM_ClearITPendingBit(TIM3, TIM_IT_Update);
+  
+  /* Toggle LED2 */
+  STM_EVAL_LEDToggle(LED2);
+}
+
+/**
+  * @brief  This function handles TIM4 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM4_IRQHandler(void)
+{
+  /* Clear TIM4 update interrupt */
+  TIM_ClearITPendingBit(TIM4, TIM_IT_Update);
+  
+  /* Toggle LED3 */
+  STM_EVAL_LEDToggle(LED3);
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h
index 7009cc3..cceaa0e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/TimeBase/stm32f10x_it.h 
+  * @file    NVIC/IRQ_Mask/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -40,8 +40,11 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
 void TIM2_IRQHandler(void);
-					 
+void TIM3_IRQHandler(void);
+void TIM4_IRQHandler(void);
+
 #endif /* __STM32F10x_IT_H */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c
index 67293b9..67293b9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Mask/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
index 33b3007..33b3007 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt
index cd86c9b..cd86c9b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h
index 0566ac2..0566ac2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
new file mode 100644
index 0000000..3065d98
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.c
@@ -0,0 +1,223 @@
+/**
+  ******************************************************************************
+  * @file    NVIC/IRQ_Priority/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup IRQ_Priority
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern uint8_t PreemptionOccured;
+extern uint8_t PreemptionPriorityValue; 
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+  /* If the EXTI0 IRQ Handler was preempted by SysTick Handler */
+  if(NVIC_GetActive(WAKEUP_BUTTON_EXTI_IRQn) != 0)
+  {
+    PreemptionOccured = 1;
+  }
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles External interrupt Line 0 request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* Generate SysTick exception */
+  SCB->ICSR |= 0x04000000;
+  
+  /* Clear WAKEUP_BUTTON_EXTI_LINE pending bit */
+  EXTI_ClearITPendingBit(WAKEUP_BUTTON_EXTI_LINE);
+}
+
+/**
+  * @brief  This function handles External lines 9 to 5 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI9_5_IRQHandler(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+  
+  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {
+    PreemptionPriorityValue = !PreemptionPriorityValue;
+    PreemptionOccured = 0;
+
+    /* Modify the WAKEUP_BUTTON_EXTI_IRQn Interrupt Preemption Priority */
+    NVIC_InitStructure.NVIC_IRQChannel = WAKEUP_BUTTON_EXTI_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = PreemptionPriorityValue;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+    
+    /* Configure the SysTick Handler Priority: Preemption priority and subpriority */
+    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), !PreemptionPriorityValue, 0));    
+
+    /* Clear KEY_BUTTON_EXTI_LINE pending bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  }
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h
index a3a3aff..a3a3aff 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c
new file mode 100644
index 0000000..406c857
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/IRQ_Priority/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    NVIC/IRQ_Priority/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl
index a3adbc0..a3adbc0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/STM32F10x_offset.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl
index c0c6865..c0c6865 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/STM32F10x_offset.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk
index 2d9c35c..2d9c35c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100B-EVAL/link_offset.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl
index 7d95809..7d95809 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/STM32F10x_offset.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/link_offset.lnk
index 2d9c35c..2d9c35c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM32100E-EVAL/link_offset.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210B-EVAL/link_offset.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/STM32F10x_offset.lsl
index 65789ce..461cf60 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/STM32F10x_offset.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/STM32F10x_offset.lsl
@@ -19,7 +19,7 @@
 // We do not want the vectors as defined in arm_arch.lsl
 //
 #define __NO_DEFAULT_AUTO_VECTORS       1
-#define __NR_OF_VECTORS                 76
+#define __NR_OF_VECTORS                 83
 
 
 #ifndef __STACK
@@ -57,8 +57,8 @@ memory stm32f103flash
 {
     mau = 8;
     type = rom;
-    size = 504k;
-    map ( size = 504k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+    size = 248k;
+    map ( size = 248k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
 }
 
 memory stm32f103ram
@@ -96,7 +96,7 @@ section_setup ::linear
                                               no_inline
                                             )
                 {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
+                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
                         vector ( id = 1, fill = "_START" );
                         vector ( id = 2, optional, fill = "NMI_Handler" );
                         vector ( id = 3, optional, fill = "HardFault_Handler" );
@@ -128,8 +128,8 @@ section_setup ::linear
                         vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
                         vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
                         vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
-                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
-                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              //  CAN1 TX
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0
                         vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
                         vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
                         vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
@@ -151,14 +151,7 @@ section_setup ::linear
                         vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
                         vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
                         vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
-                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
-                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
-                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
-                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
-                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
-                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
-                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
-                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 58, optional, fill = "OTG_FS_WKUP_IRQHandler" );          // USB OTG FS Wakeup through EXTI line
                         vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
                         vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
                         vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
@@ -168,7 +161,14 @@ section_setup ::linear
                         vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
                         vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
                         vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
-                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );      // DMA2 Channel4 
+			vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );      // DMA2 Channel5 
+			vector ( id = 77, optional, fill = "ETH_IRQHandler" );                  // Ethernet
+			vector ( id = 78, optional, fill = "CAN2_TX_IRQHandler " );              // CAN2 TX
+			vector ( id = 79, optional, fill = "CAN2_RX0_IRQHandler" );              // CAN2 RX0
+			vector ( id = 80, optional, fill = "CAN2_RX1_IRQHandler" );              // CAN2 RX1
+			vector ( id = 81, optional, fill = "CAN2_SCE_IRQHandler" );              // CAN2 SCE
+			vector ( id = 82, optional, fill = "OTG_FS_IRQHandler" );                // USB OTG FS
                 }
 }
 # endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk
index 2d9c35c..2d9c35c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210E-EVAL/link_offset.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl
index 3046e73..3046e73 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/STM32F10x_offset.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld
index 9349b62..9349b62 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/TrueSTUDIO/stm32f10x_flash_offset.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
index 849726c..849726c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h
index 6ad4c41..6ad4c41 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/main.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt
new file mode 100644
index 0000000..ded8147
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/readme.txt
@@ -0,0 +1,149 @@
+/**
+  @page NVIC_VectorTable_Relocation NVIC VectorTable Relocation example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    NVIC/VectorTable_Relocation/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the NVIC VectorTable Relocation example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example describes how to set the CortexM3 vector table in a specific 
+address other than default using the NVIC_SetVectorTable function from the 
+misc.h/.c driver.
+
+This can be used to build program which will be loaded into Flash memory by an
+application previously programmed from the Flash memory base address. 
+Such application can be In-Application Programming (IAP, through USART) or
+Device Firmware Upgrade (DFU, through USB).
+
+These applications are available for download from the ST microcontrollers 
+website: www.st.com/stm32
+
+The associated program implements a "Delay" function based on SysTick end of count
+interrupt, and toggles four leds with timing defined by the "Delay" function.
+
+When using the IAP to load your porgram, the vector table must be relocated at
+address 0x08003000.
+
+When using the DFU to load your porgram, the vector table must be relocated at
+address 0x08003000.
+
+@par Directory contents 
+
+ - NVIC/VectorTable_Relocation/linker: modified linker to be used for this project 
+ - NVIC/VectorTable_Relocation/stm32f10x_conf.h     Library Configuration file 
+ - NVIC/VectorTable_Relocation/stm32f10x_it.c       Interrupt handlers 
+ - NVIC/VectorTable_Relocation/stm32f10x_it.h       Interrupt handlers header file 
+ - NVIC/VectorTable_Relocation/main.c               Main program 
+ - NVIC/VectorTable_Relocation/main.h               Header for main.c 
+ - NVIC/VectorTable_Relocation/system_stm32f10x.c   STM32F10x system source file
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
+    and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
+    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
+    evaluation boards and can be easily tailored to any other supported device 
+    and development board.
+    To select the STMicroelectronics evaluation board used to run the example, 
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+
+  - STM32100E-EVAL Set-up 
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08
+      and PF.09 pins
+      
+  - STM32100B-EVAL Set-up   
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08
+      and PC.09 pins
+      
+  - STM3210C-EVAL Set-up 
+    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PD.07, PD.13, PF.03
+      and PD.04 pins
+    
+  - STM3210E-EVAL Set-up 
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, PF.08
+      and PF.09 pins
+
+  - STM3210B-EVAL Set-up   
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08
+      and PC.09 pins
+     
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+- Create a project and setup all project configuration:
+<ul>
+    <li> MDK-ARM 
+         - In the project option menu, select 'Target' window and enter 0x08003000 
+           as IROM start address
+         - In the project option menu, select 'Linker' window and enter 0x08003000 
+           as R/O base address                    
+
+    <li> EWARM
+         - Use "stm32f10x_flash_offset.icf" as linker file
+
+    <li> RIDE 
+         - In the Application options -> script menu, set "Use Default Script File" 
+           to "No" and use "stm32f10x_flash_offset.ld" as Script File. 
+           This linker is configured for STM32 XL-density devices. To use it with
+           other STM32 devices, this linker should be updated.
+    
+    <li> HiTOP 
+         - From linker\HiTOP\[target], copy the "link_offset" and "STM32F10x_offset.lsl"
+           to "Settings" folder.
+         - In project -> settings -> project -> tool settings ->linker 
+             use "link_offset.lnk" as linker file. 
+         - Add the "setstack.asm" to the workspace.
+         
+    <li> TrueSTUDIO 
+         - In the project properties window, select 'C/C++ Build'->settings node then 
+           the 'C Linker'->General node and use "stm32f10x_flash_offset.ld" as Script File.
+           This linker is configured for STM32 STM32F10x XL-density devices. To use it with
+           other STM32 devices, this linker should be updated. 
+         
+</ul>        
+- Copy all source files from this example folder to the template folder under
+  Project\STM32F10x_StdPeriph_Template
+      
+- In the main.c and linker files, the vector table is relocated at address 0x08003000.
+  You can modify this address depending on the requirement of your application.    
+- Rebuild all files 
+- Convert the program image to a binary file, *.bin, then you can download and
+  run it using the IAP or DFU application.
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+    
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h
index e823189..e823189 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c
index 6b81deb..6b81deb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h
index f649072..f649072 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c
index 0672dd3..0672dd3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt
index 3668412..3668412 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h
index 945ae07..945ae07 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c
index 66ded33..4e3e5c7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.c
@@ -1,12 +1,12 @@
 /**
   ******************************************************************************
-  * @file    SDIO/uSDCard/stm32f10x_it.c 
+  * @file    PWR/PVD/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
   * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
   ******************************************************************************
   * @attention
   *
@@ -23,13 +23,13 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
-#include "stm32_eval_sdio_sd.h"
+#include "stm32_eval.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup SDIO_uSDCard
+/** @addtogroup PWR_PVD
   * @{
   */
 
@@ -62,7 +62,8 @@ void HardFault_Handler(void)
 {
   /* Go to infinite loop when Hard Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -74,7 +75,8 @@ void MemManage_Handler(void)
 {
   /* Go to infinite loop when Memory Manage exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -86,7 +88,8 @@ void BusFault_Handler(void)
 {
   /* Go to infinite loop when Bus Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
@@ -98,24 +101,25 @@ void UsageFault_Handler(void)
 {
   /* Go to infinite loop when Usage Fault exception occurs */
   while (1)
-  {}
+  {
+  }
 }
 
 /**
-  * @brief  This function handles Debug Monitor exception.
+  * @brief  This function handles SVCall exception.
   * @param  None
   * @retval None
   */
-void DebugMon_Handler(void)
+void SVC_Handler(void)
 {
 }
 
 /**
-  * @brief  This function handles SVCall exception.
+  * @brief  This function handles Debug Monitor exception.
   * @param  None
   * @retval None
   */
-void SVC_Handler(void)
+void DebugMon_Handler(void)
 {
 }
 
@@ -142,16 +146,23 @@ void SysTick_Handler(void)
 /******************************************************************************/
 
 /**
-  * @brief  This function handles SDIO global interrupt request.
+  * @brief  This function handles the PVD Output interrupt request.
   * @param  None
   * @retval None
   */
-void SDIO_IRQHandler(void)
+void PVD_IRQHandler(void)
 {
-  /* Process All SDIO Interrupt Sources */
-  SD_ProcessIRQSrc();
+  if(EXTI_GetITStatus(EXTI_Line16) != RESET)
+  {
+    /* Toggle LED1 */
+    STM_EVAL_LEDToggle(LED1);
+
+    /* Clear the Key Button EXTI line pending bit */
+    EXTI_ClearITPendingBit(EXTI_Line16);
+  }
 }
 
+
 /******************************************************************************/
 /*                 STM32F10x Peripherals Interrupt Handlers                   */
 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
@@ -170,10 +181,10 @@ void SDIO_IRQHandler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h
new file mode 100644
index 0000000..262377f
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/stm32f10x_it.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    PWR/PVD/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void PVD_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c
index 9cd98b1..9cd98b1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/PVD/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c
index bb32524..bb32524 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/readme.txt
index 962c3a0..6e65472 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page PWR_STOP PWR STOP example
+  @page PWR_STANDBY PWR STANDBY example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    PWR/STOP/readme.txt 
+  * @file    PWR/STANDBY/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the PWR STOP example.
+  * @brief   Description of the PWR STANDBY example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,40 +20,40 @@
 
 @par Example Description 
 
-This example shows how to enter the system to STOP mode and wake-up using EXTI
-Line interrupts. The EXTI Line sources are PB.09/PG.08 and RTC Alarm.
+This example shows how to enters the system to STANDBY mode and wake-up from this
+mode using: external RESET, RTC Alarm or WKUP pin.
 
-The EXTI line9/8 is configured to generate interrupt on falling edge.
-The EXTI line17(RTC Alarm) is configured to generate interrupt on rising edge and
-the RTC time base is set to 1 second using the external low speed oscillator(LSE).
+In the associated software, the system clock is set to 24 MHz on Value line devices 
+and to 72 MHz on other devices using the external high speed oscillator(HSE), an EXTI line
+is configured to generate an interrupt on falling edge and the SysTick is programmed
+to generate an interrupt each 250 ms. In the SysTick interrupt handler, the LED1 is
+toggled, this is used to indicate whether the MCU is in STANDBY or RUN mode.
 
-The system clock is set to 24 MHz on Value line devices and to 72 MHz on other 
-devices using the external high speed oscillator(HSE).
+When a falling edge is detected on the EXTI line an interrupt is generated. In the 
+EXTI handler routine the RTC is configured to generate an Alarm event in 3 second
+then the system enters STANDBY mode causing the LED1 to stop toggling. 
+A rising edge on WKUP pin or an external RESET will wake-up the system from
+STANDBY. If within 3 second neither rising edge on WKUP pin nor external RESET
+are generated, the RTC Alarm will wake-up the system. 
 
-The system enters and exits STOP mode as following:
-After 2 second from system start-up, the RTC is configured to generate an Alarm
-event in 3 second then the system enters STOP mode. To wake-up from STOP mode you
-have to apply a rising edge on EXTI line9/8, otherwise the  RTC Alarm will wake-up
-the system within 3 second. After exit from STOP the system clock is reconfigured
-to its previous state (as HSE and PLL are disabled in STOP mode).
-Then after a delay the system will enter again in STOP mode and exit in the way
-described above. This behavior is repeated in an infinite loop.
-
-Three leds LED1, LED2 and LED3 are used to monitor the system state as following:
- - LED1 on: system in RUN mode
- - LED1 off: system in STOP mode
- - LED2 is toggled if EXTI Line9/8 is used to exit from STOP 
- - LED3 is toggled if EXTI line17(RTC Alarm) is used to exit from STOP 
+After wake-up from STANDBY mode, program execution restarts in the same way as after
+a RESET, the LED1 restarts toggling, LED2 is turned on and the RTC configuration
+(clock source, enable, prescaler,...) is kept.
+As result there is no need to configure the RTC.
 
+Two leds LED1 and LED2 are used to monitor the system state as following:
+ - LED1 toggling: system in RUN mode
+ - LED1 off / LED2 off: system in STANDBY mode
+ - LED2 on: system resumed from STANDBY mode
 
 @par Directory contents 
 
-  - PWR/STOP/stm32f10x_conf.h     Library Configuration file
-  - PWR/STOP/stm32f10x_it.c       Interrupt handlers
-  - PWR/STOP/stm32f10x_it.h       Header for stm32f10x_it.c
-  - PWR/STOP/main.c               Main program
-  - PWR/STOP/system_stm32f10x.c   STM32F10x system source file
-
+  - PWR/STANDBY/stm32f10x_conf.h     Library Configuration file
+  - PWR/STANDBY/stm32f10x_it.c       Interrupt handlers
+  - PWR/STANDBY/stm32f10x_it.h       Header for stm32f10x_it.c
+  - PWR/STANDBY/main.c               Main program
+  - PWR/STANDBY/system_stm32f10x.c   STM32F10x system source file
+  
 @par Hardware and Software environment 
 
   - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
@@ -61,7 +61,7 @@ Three leds LED1, LED2 and LED3 are used to monitor the system state as following
     and Low-Density Value line Devices.
   
   - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line),STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
     STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
     evaluation boards and can be easily tailored to any other supported device 
     and development board.
@@ -69,31 +69,35 @@ Three leds LED1, LED2 and LED3 are used to monitor the system state as following
     uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
 
   - STM32100E-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
+    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
     - Use the Key push-button connected to pin PG.08 (EXTI Line8).
+    - Use the Wakeup push-button connected to WKUP(PA.00) pin
     
-  - STM32100B-EVAL Set-up  
-    - Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
+  - STM32100B-EVAL Set-up 
+    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins    
     - Use the Key push-button connected to pin PB.09 (EXTI Line9).
+    - Use the Wakeup push-button connected to WKUP(PA.00) pin  
     
   - STM3210C-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PD.07, PD.13 and PF.03 pins
+    - Use LED1 and LED2 connected respectively to PD.07 and PD.13 pins
     - Use the Key push-button connected to pin PB.09 (EXTI Line9).
+    - Use the Wakeup push-button connected to WKUP(PA.00) pin, make sure
+      that jumper JP14 is in position 2-3.
 
   - STM3210E-EVAL Set-up 
-    - Use LED1, LED2 and LED3 leds connected respectively to PF.06, PF0.7 and PF.08 pins
+    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
     - Use the Key push-button connected to pin PG.08 (EXTI Line8).
+    - Use the Wakeup push-button connected to WKUP(PA.00) pin
+    @note  the jumper JP4 must be not fit to be able to use the Wakeup push-button
 
-  - STM3210B-EVAL Set-up  
-    - Use LED1, LED2 and LED3 leds connected respectively to PC.06, PC.07 and PC.08 pins
+  - STM3210B-EVAL Set-up 
+    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins    
     - Use the Key push-button connected to pin PB.09 (EXTI Line9).
+    - Use the Wakeup push-button connected to WKUP(PA.00) pin        
 	
-@note For power consumption measurement in STOP mode you have to: 
-- Modify the example to configure all unused GPIO port pins in Analog Input mode
-  (floating input trigger OFF). Refer to GPIO\IOToggle example for more details. 
-- Replace jumper JP9 in the STM3210B-EVAL board, JP12 in the STM3210E-EVAL, 
-  JP23 (position 1-2) in the STM3210C-EVAL board or JP8 (position 1-2) in the 
-  STM32100B-EVAL board by an amperemeter.
+@note For power consumption measurement in STANDBY mode, you have to replace
+      jumper JP9 in the STM3210B-EVAL board, JP12 in the STM3210E-EVAL or 
+      JP23 (position 1-2) in the STM3210C-EVAL board by an amperemeter.
 
          
 @par How to use it ? 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h
index 48e5a4f..21bf291 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    BKP/Tamper/stm32f10x_conf.h 
+  * @file    PWR/STANDBY/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c
index 25cae00..2db96a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CortexM3/MPU/system_stm32f10x.c
+  * @file    PWR/STANDBY/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
new file mode 100644
index 0000000..6646098
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/main.c
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    PWR/STOP/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup PWR_STOP
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern __IO uint32_t TimingDelay;
+ErrorStatus HSEStartUpStatus;
+
+/* Private function prototypes -----------------------------------------------*/
+void SYSCLKConfig_STOP(void);
+void EXTI_Configuration(void);
+void RTC_Configuration(void);
+void NVIC_Configuration(void);
+void SysTick_Configuration(void);
+void Delay(__IO uint32_t nTime);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+
+  /* Initialize LEDs and Key Button mounted on STM3210X-EVAL board */       
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);
+
+  /* Enable PWR and BKP clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
+
+  /* Configure EXTI Line to generate an interrupt on falling edge */
+  EXTI_Configuration();
+
+  /* Configure RTC clock source and prescaler */
+  RTC_Configuration();
+
+  /* NVIC configuration */
+  NVIC_Configuration();
+
+  /* Configure the SysTick to generate an interrupt each 1 millisecond */
+  SysTick_Configuration();
+
+  /* Turn on LED1 */
+  STM_EVAL_LEDOn(LED1);
+  
+  while (1)
+  {
+    /* Insert 1.5 second delay */
+    Delay(1500);
+
+    /* Wait till RTC Second event occurs */
+    RTC_ClearFlag(RTC_FLAG_SEC);
+    while(RTC_GetFlagStatus(RTC_FLAG_SEC) == RESET);
+
+    /* Alarm in 3 second */
+    RTC_SetAlarm(RTC_GetCounter()+ 3);
+    /* Wait until last write operation on RTC registers has finished */
+    RTC_WaitForLastTask();
+
+    /* Turn off LED1 */
+    STM_EVAL_LEDOff(LED1);
+
+    /* Request to enter STOP mode with regulator in low power mode*/
+    PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+    
+    /* At this stage the system has resumed from STOP mode -------------------*/
+    /* Turn on LED1 */
+    STM_EVAL_LEDOn(LED1);
+
+    /* Configures system clock after wake-up from STOP: enable HSE, PLL and select 
+       PLL as system clock source (HSE and PLL are disabled in STOP mode) */
+    SYSCLKConfig_STOP();
+  }
+}
+
+/**
+  * @brief  Configures system clock after wake-up from STOP: enable HSE, PLL
+  *         and select PLL as system clock source.
+  * @param  None
+  * @retval None
+  */
+void SYSCLKConfig_STOP(void)
+{
+  /* Enable HSE */
+  RCC_HSEConfig(RCC_HSE_ON);
+
+  /* Wait till HSE is ready */
+  HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+  if(HSEStartUpStatus == SUCCESS)
+  {
+
+#ifdef STM32F10X_CL
+    /* Enable PLL2 */ 
+    RCC_PLL2Cmd(ENABLE);
+
+    /* Wait till PLL2 is ready */
+    while(RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET)
+    {
+    }
+
+#endif
+
+    /* Enable PLL */ 
+    RCC_PLLCmd(ENABLE);
+
+    /* Wait till PLL is ready */
+    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+    /* Wait till PLL is used as system clock source */
+    while(RCC_GetSYSCLKSource() != 0x08)
+    {
+    }
+  }
+}
+
+/**
+  * @brief  Configures EXTI Lines.
+  * @param  None
+  * @retval None
+  */
+void EXTI_Configuration(void)
+{
+  EXTI_InitTypeDef EXTI_InitStructure;
+
+  /* Configure EXTI Line17(RTC Alarm) to generate an interrupt on rising edge */
+  EXTI_ClearITPendingBit(EXTI_Line17);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line17;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+}
+
+/**
+  * @brief  Configures RTC clock source and prescaler.
+  * @param  None
+  * @retval None
+  */
+void RTC_Configuration(void)
+{
+  /* RTC clock source configuration ------------------------------------------*/
+  /* Allow access to BKP Domain */
+  PWR_BackupAccessCmd(ENABLE);
+
+  /* Reset Backup Domain */
+  BKP_DeInit();
+  
+  /* Enable the LSE OSC */
+  RCC_LSEConfig(RCC_LSE_ON);
+  /* Wait till LSE is ready */
+  while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
+  {
+  }
+
+  /* Select the RTC Clock Source */
+  RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+
+  /* Enable the RTC Clock */
+  RCC_RTCCLKCmd(ENABLE);
+
+  /* RTC configuration -------------------------------------------------------*/
+  /* Wait for RTC APB registers synchronisation */
+  RTC_WaitForSynchro();
+
+  /* Set the RTC time base to 1s */
+  RTC_SetPrescaler(32767);  
+  /* Wait until last write operation on RTC registers has finished */
+  RTC_WaitForLastTask();
+
+  /* Enable the RTC Alarm interrupt */
+  RTC_ITConfig(RTC_IT_ALR, ENABLE);
+  /* Wait until last write operation on RTC registers has finished */
+  RTC_WaitForLastTask();
+}
+
+/**
+  * @brief  Configures NVIC and Vector Table base location.
+  * @param  None
+  * @retval None
+  */
+void NVIC_Configuration(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* 2 bits for Preemption Priority and 2 bits for Sub Priority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+
+  NVIC_InitStructure.NVIC_IRQChannel = RTCAlarm_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+/**
+  * @brief  Configures the SysTick to generate an interrupt each 1 millisecond.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Configuration(void)
+{
+  /* Setup SysTick Timer for 1 msec interrupts  */
+  if (SysTick_Config(SystemCoreClock / 1000))
+  { 
+    /* Capture error */ 
+    while (1);
+  }
+  /* Set SysTick Priority to 3 */
+  NVIC_SetPriority(SysTick_IRQn, 0x0C);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nTime: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void Delay(__IO uint32_t nTime)
+{
+  TimingDelay = nTime;
+
+  while(TimingDelay != 0);
+
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h
index 2dc3aa3..2dc3aa3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
index 5682ad3..5682ad3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h
index 7ca57f1..7ca57f1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STOP/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
index 8dba3b1..8dba3b1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h
index b3a67d8..b3a67d8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/main.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt
index 8bfbccd..8bfbccd 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/readme.txt
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c
new file mode 100644
index 0000000..6e79c77
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.c
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "main.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup RCC_ClockConfig
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+  /* This interrupt is generated when HSE clock fails */
+
+  if (RCC_GetITStatus(RCC_IT_CSS) != RESET)
+  {/* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI
+       is selected as system clock source */
+
+    /* Enable HSE */
+    RCC_HSEConfig(RCC_HSE_ON);
+
+    /* Enable HSE Ready interrupt */
+    RCC_ITConfig(RCC_IT_HSERDY, ENABLE);
+
+#ifndef SYSCLK_HSE
+ #ifdef STM32F10X_CL
+    /* Enable PLL and PLL2 Ready interrupts */
+    RCC_ITConfig(RCC_IT_PLLRDY | RCC_IT_PLL2RDY, ENABLE);
+ #else
+    /* Enable PLL Ready interrupt */
+    RCC_ITConfig(RCC_IT_PLLRDY, ENABLE);
+ #endif	/* STM32F10X_CL */
+#endif /* SYSCLK_HSE */
+
+    /* Clear Clock Security System interrupt pending bit */
+    RCC_ClearITPendingBit(RCC_IT_CSS);
+
+    /* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR
+       routine the system clock will be reconfigured to its previous state (before
+       HSE clock failure) */
+  }
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles RCC interrupt request. 
+  * @param  None
+  * @retval None
+  */
+void RCC_IRQHandler(void)
+{
+  if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET)
+  { 
+    /* Clear HSERDY interrupt pending bit */
+    RCC_ClearITPendingBit(RCC_IT_HSERDY);
+
+    /* Check if the HSE clock is still available */
+    if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+    { 
+#ifdef SYSCLK_HSE
+      /* Select HSE as system clock source */
+      RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);
+#else
+ #ifdef STM32F10X_CL
+      /* Enable PLL2 */
+      RCC_PLL2Cmd(ENABLE);
+ #else
+      /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ 
+      RCC_PLLCmd(ENABLE);
+ #endif	/* STM32F10X_CL */
+#endif /* SYSCLK_HSE */      
+    }
+  }
+
+#ifdef STM32F10X_CL
+  if(RCC_GetITStatus(RCC_IT_PLL2RDY) != RESET)
+  { 
+    /* Clear PLL2RDY interrupt pending bit */
+    RCC_ClearITPendingBit(RCC_IT_PLL2RDY);
+
+    /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ 
+    RCC_PLLCmd(ENABLE);
+  }
+#endif /* STM32F10X_CL */   
+
+  if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET)
+  { 
+    /* Clear PLLRDY interrupt pending bit */
+    RCC_ClearITPendingBit(RCC_IT_PLLRDY);
+
+    /* Check if the PLL is still locked */
+    if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET)
+    { 
+      /* Select PLL as system clock source */
+      RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+    }
+  }
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h
new file mode 100644
index 0000000..7bd8a6a
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_it.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    RCC/RCC_ClockConfig/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void RCC_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/readme.txt
new file mode 100644
index 0000000..e63a786
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/readme.txt
@@ -0,0 +1,150 @@
+/**
+  @page RTC_Calendar RTC Calendar example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    RTC/Calendar/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the RTC Calendar example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example demonstrates and explains how to use the RTC peripheral. 
+As an application example, it demonstrates how to setup the RTC peripheral, in terms
+of prescaler and interrupts, to be used to keep time and to generate Second interrupt. 
+
+The Low Speed External (LSE) clock is used as RTC clock source. 
+The RTC clock can be output on the Tamper pin (PC.13). To enable this functionality,
+uncomment the corresponding line: #define RTCClockOutput_Enable in the main.c file.
+
+The RTC is in the backup (BKP) domain, still powered by VBAT when VDD is switched off,
+so the RTC configuration is not lost if a battery is connected to the VBAT pin. 
+A key value is written in backup data register1 (BKP_DR1) to indicate if the RTC
+is already configured.
+
+The program behaves as follows:
+
+1. After startup the program checks the backup data register1 value:
+    - register1 value not correct: (BKP_DR1 value is not correct or has not yet
+      been programmed when the program is executed for the first time) the RTC is
+      configured and the user is asked to set the time (entered on HyperTerminal).
+    
+    - register1 value correct: this means that the RTC is configured and the time
+      is displayed on HyperTerminal.
+
+2. When an External Reset occurs the BKP domain is not reset and the RTC configuration
+   is not lost.
+
+3. When power on reset occurs:
+    - If a battery is connected to the VBAT pin: the BKP domain is not reset and
+      the RTC configuration is not lost.
+      
+    - If no battery is connected to the VBAT pin: the BKP domain is reset and the
+      RTC configuration is lost.
+
+In the RTC interrupt service routine, the LED1 toggles every 1 s.
+The C library printf function is retargeted to the USART, that is, the printf
+message is output to the HyperTerminal using USART1 or USART2 depending on the 
+EVAL board you are using.
+
+ 
+@par Directory contents 
+
+  - RTC/Calendar/stm32f10x_conf.h     Library Configuration file
+  - RTC/Calendar/stm32f10x_it.c       Interrupt handlers
+  - RTC/Calendar/stm32f10x_it.h       Header for stm32f10x_it.c
+  - RTC/Calendar/main.c               Main program
+  - RTC/Calendar/system_stm32f10x.c   STM32F10x system source file
+
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
+    and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
+    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
+    evaluation boards and can be easily tailored to any other supported device 
+    and development board.
+    To select the STMicroelectronics evaluation board used to run the example, 
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+
+  - STM32100E-EVAL Set-up 
+    - Use LED1 connected to PF.06.
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN10(when USART1 is used) and PC serial port. 
+    - Make sure that jumper JP1 is in position 1-2 to connect the 3V battery to VBAT pin
+    
+  - STM32100B-EVAL Set-up   
+    - Use LED1 connected to PC.06.
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN10(when USART1 is used) and PC serial port.
+    - Make sure that jumper JP9 is in position 1-2 to connect the 3V battery to VBAT pin
+    
+  - STM3210C-EVAL Set-up 
+    - Use LED1 connected to PD.07.
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6 (USART2) and PC serial port .
+    @note Make sure that jumpers JP19 and JP18 are open.    
+    - Make sure that jumper JP24 is in position 1-2 to connect the 3V battery to VBAT pin
+    
+  - STM3210E-EVAL Set-up 
+    - Use LED1 connected to PF.06.
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN12(when USART1 is used) and PC serial port. 
+    - Make sure that jumper JP1 is in position 1-2 to connect the 3V battery to VBAT pin
+    
+  - STM3210B-EVAL Set-up   
+    - Use LED1 connected to PC.06.
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6(when USART1 is used) and PC serial port.
+    - Make sure that jumper JP11 is in position 1-2 to connect the 3V battery to VBAT pin
+
+  - Hyperterminal configuration:
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - No parity
+    - BaudRate = 115200 baud
+    - flow control: None
+
+       
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h
index 01155f6..01155f6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c
index 4b8b7a9..1d3e909 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CAN/LoopBack/system_stm32f10x.c
+  * @file    RTC/Calendar/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h
index b6cd4ef..b6cd4ef 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
index d9218cb..d9218cb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
index 9131767..9131767 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c
new file mode 100644
index 0000000..36d0f65
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    RTC/LSI_Calib/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html
index 8b0640c..8b0640c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Release_Notes.html
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt
index 9659113..9659113 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h
index 385772d..385772d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt
index e3311a5..e3311a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h
index 8331a3f..8331a3f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h
index 9c67ba1..9c67ba1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c
index dc6cd30..dc6cd30 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
index 985e800..985e800 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h
index a628e14..a628e14 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt
index 726061f..726061f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c
index d8e98db..d8e98db 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c
index 34c34c7..34c34c7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
index 8e34cbd..8e34cbd 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/main.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/platform_config.h
new file mode 100644
index 0000000..1440c52
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/platform_config.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    SPI/FullDuplex_SoftNSS/platform_config.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100E_EVAL)
+ //#define USE_STM32100B_EVAL
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM32100E_EVAL
+ #define USE_STM3210C_EVAL
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#if defined (USE_STM3210B_EVAL) || defined (USE_STM3210E_EVAL) || defined(USE_STM32100B_EVAL) || defined (USE_STM32100E_EVAL)
+  #define SPIy                   SPI1
+  #define SPIy_CLK               RCC_APB2Periph_SPI1
+  #define SPIy_GPIO              GPIOA
+  #define SPIy_GPIO_CLK          RCC_APB2Periph_GPIOA  
+  #define SPIy_PIN_SCK           GPIO_Pin_5
+  #define SPIy_PIN_MISO          GPIO_Pin_6
+  #define SPIy_PIN_MOSI          GPIO_Pin_7
+  
+  #define SPIz                    SPI2
+  #define SPIz_CLK                RCC_APB1Periph_SPI2
+  #define SPIz_GPIO               GPIOB
+  #define SPIz_GPIO_CLK           RCC_APB2Periph_GPIOB 
+  #define SPIz_PIN_SCK            GPIO_Pin_13
+  #define SPIz_PIN_MISO           GPIO_Pin_14
+  #define SPIz_PIN_MOSI           GPIO_Pin_15 
+          
+#elif defined (USE_STM3210C_EVAL)
+  #define SPIy                   SPI3   /* SPI pins are remapped by software */
+  #define SPIy_CLK               RCC_APB1Periph_SPI3
+  #define SPIy_GPIO              GPIOC
+  #define SPIy_GPIO_CLK          RCC_APB2Periph_GPIOC  
+  #define SPIy_PIN_SCK           GPIO_Pin_10
+  #define SPIy_PIN_MISO          GPIO_Pin_11
+  #define SPIy_PIN_MOSI          GPIO_Pin_12
+  
+  #define SPIz                    SPI2
+  #define SPIz_CLK                RCC_APB1Periph_SPI2
+  #define SPIz_GPIO               GPIOB
+  #define SPIz_GPIO_CLK           RCC_APB2Periph_GPIOB
+  #define SPIz_PIN_SCK            GPIO_Pin_13
+  #define SPIz_PIN_MISO           GPIO_Pin_14
+  #define SPIz_PIN_MOSI           GPIO_Pin_15
+
+#endif
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt
index 5468227..5468227 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
index 45a1e9c..45a1e9c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c
index 4649493..4649493 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h
index 50d395b..50d395b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
index f2a0a05..f2a0a05 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c
index 9914252..9914252 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h
index 7b857ba..7b857ba 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt
index 09e717c..09e717c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
index 8960329..8960329 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
index 12f829a..12f829a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/readme.txt
new file mode 100644
index 0000000..2268912
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/readme.txt
@@ -0,0 +1,101 @@
+/**
+  @page SysTick_TimeBase SysTick Time Base example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    SysTick/TimeBase/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the SysTick Time Base example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example shows how to configure the SysTick to generate a time base equal to
+1 ms. The system clock is set to 24 MHz on Value line devices and to 72 MHz on 
+other devices, the SysTick is clocked by the AHB clock (HCLK).
+
+A "Delay" function is implemented based on the SysTick end-of-count event.
+Four LEDs are toggled with a timing defined by the Delay function.
+
+@par Directory contents 
+
+  - SysTick/TimeBase/stm32f10x_conf.h     Library Configuration file
+  - SysTick/TimeBase/stm32f10x_it.c       Interrupt handlers
+  - SysTick/TimeBase/stm32f10x_it.h       Header for stm32f10x_it.c
+  - SysTick/TimeBase/main.c               Main program
+  - SysTick/TimeBase/main.h               Header for main.c
+  - SysTick/TimeBase/system_stm32f10x.c   STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, 
+    Low-Density and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
+    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) 
+    and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily
+    tailored to any other supported device and development board.
+    To select the STMicroelectronics evaluation board used to run the example, 
+    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+
+  - STM32100E-EVAL Set-up 
+    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08
+      and PF.09 pins
+      
+  - STM32100B-EVAL Set-up  
+    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
+      and PC.09 pins
+      
+  - STM3210C-EVAL Set-up 
+    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
+      and PD.04 pins
+    
+  - STM3210E-EVAL Set-up 
+    - Use LED1, LED2, LED3 and LED4 connected respectively to PF.06, PF0.7, PF.08
+      and PF.09 pins
+
+  - STM3210B-EVAL Set-up  
+    - Use LED1, LED2, LED3 and LED4 connected respectively to PC.06, PC.07, PC.08
+      and PC.09 pins
+
+          
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.   
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h
index f032f0e..f032f0e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c
index 7100fdc..7100fdc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h
index 7f3aa14..7f3aa14 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
index c6bc875..c6bc875 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
index c3fa83c..c3fa83c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt
index 2fc3977..2fc3977 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h
index 474afcc..53e2221 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FLASH_RAM/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file DMA/FLASH_RAM/stm32f10x_conf.h 
+  * @file    TIM/6Steps/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
index f90cc9f..f90cc9f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
index 12ed6f1..12ed6f1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/6Steps/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
index 7f23815..7f23815 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/readme.txt
index 7e3f72b..d2c3069 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page TIM_Input_Capture TIM Input Capture example 
+  @page TIM_7PWM_Output TIM 7 PWM Output example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/InputCapture/readme.txt 
+  * @file    TIM/7PWM_Output/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the TIM Input Capture example.
+  * @brief   Description of the TIM 7 PWM Output example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,35 +20,32 @@
 
 @par Example Description 
 
-This example shows how to use the TIM peripheral to measure the frequency of an 
-external signal.
+This example shows how to configure the TIM1 peripheral to generate 7 PWM signals 
+with 4 different duty cycles (50%, 37.5%, 25% and 12.5%).
 
-The TIMxCLK frequency is set to SystemCoreClock (Hz), the Prescaler is 0 so the 
-TIM3 counter clock is SystemCoreClock (Hz).
+TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
-and Connectivity line devices. For Low-Density Value line and Medium-Density 
-Value line devices, SystemCoreClock is set to 24 MHz.
+and Connectivity line devices. For Low-Density Value line, Medium-Density and
+High-density Value line devices, SystemCoreClock is set to 24 MHz.
 
-TIM3 is configured in Input Capture Mode: the external signal is connected to 
-TIM3 Channel2 used as input pin.
-To measure the frequency we use the TIM3 CC2 interrupt request,
-so In the TIM3_IRQHandler routine, the frequency of the external signal is computed. 
-The "TIM3Freq" variable contains the external signal frequency:
-TIM3Freq = TIM3 counter clock / Capture in Hz,
-where the Capture is the difference between two consecutive TIM3 captures. 
+The objective is to generate 7 PWM signal at 17.57 KHz:
+  - TIM1_Period = (SystemCoreClock / 17570) - 1
+The channel 1 and channel 1N duty cycle is set to 50%
+The channel 2 and channel 2N duty cycle is set to 37.5%
+The channel 3 and channel 3N duty cycle is set to 25%
+The channel 4 duty cycle is set to 12.5%
+The Timer pulse is calculated as follows:
+  - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
 
-For Low-density, Medium-density, High-density and Connectivity line devices, 
-the minimum frequency value to measure is 1100 Hz. 
-For Low-Density Value line, Medium-Density and High-Density Value line devices, 
-the minimum frequency value to measure is 366 Hz.
+The TIM1 waveform can be displayed using an oscilloscope.
 
 @par Directory contents 
 
-  - TIM/InputCapture/stm32f10x_conf.h    Library Configuration file
-  - TIM/InputCapture/stm32f10x_it.c      Interrupt handlers
-  - TIM/InputCapture/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/InputCapture/main.c              Main program 
-  - TIM/InputCapture/system_stm32f10x.c  STM32F10x system source file
+  - TIM/7PWM_Output/stm32f10x_conf.h    Library Configuration file
+  - TIM/7PWM_Output/stm32f10x_it.c      Interrupt handlers
+  - TIM/7PWM_Output/stm32f10x_it.h      Interrupt handlers header file
+  - TIM/7PWM_Output/main.c              Main program
+  - TIM/7PWM_Output/system_stm32f10x.c  STM32F10x system source file
   
 @par Hardware and Software environment 
 
@@ -61,9 +58,27 @@ the minimum frequency value to measure is 366 Hz.
     STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
     evaluation boards and can be easily tailored to any other supported device 
     and development board.
+    
 
-  - STM32100E-EVAL, STM32100B-EVAL, STM3210C-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up 
-    - Connect the external signal to measure to the TIM3 CH2 pin (PA.07).   
+  - STM3210C-EVAL Set-up 
+    - Connect the TIM1 pins(TIM1 full remapped pins) to an oscilloscope to monitor the different waveforms:
+      - TIM1_CH1  pin (PE.08)  
+      - TIM1_CH1N pin (PE.09)  
+      - TIM1_CH2  pin (PE.10)  
+      - TIM1_CH2N pin (PE.11)  
+      - TIM1_CH3  pin (PE.12)  
+      - TIM1_CH3N pin (PE.13)
+      - TIM1_CH4  pin (PE.14)      
+
+  - STM3210E-EVAL, STM3210B-EVAL, STM32100B-EVAL and STM32100E-EVAL Set-up 
+    - Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
+      - TIM1_CH1  pin (PA.08)  
+      - TIM1_CH1N pin (PB.13)  
+      - TIM1_CH2  pin (PA.09)  
+      - TIM1_CH2N pin (PB.14)  
+      - TIM1_CH3  pin (PA.10)  
+      - TIM1_CH3N pin (PB.15)
+      - TIM1_CH4  pin (PA.11)    
   
 @par How to use it ? 
 
@@ -72,7 +87,7 @@ In order to make the program work, you must do the following :
    Project\STM32F10x_StdPeriph_Template
  - Open your preferred toolchain 
  - Rebuild all files and load your image into target memory
- - Run the example
+ - Run the example 
 
 @note
  - Low-density Value line devices are STM32F100xx microcontrollers where the 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h
index 9827ef8..9827ef8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
index bf0b15b..bf0b15b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h
index 4f1bba1..4f1bba1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c
index 19c5e51..19c5e51 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/7PWM_Output/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c
index 172f3ee..172f3ee 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt
index c842531..c842531 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h
index e42fe40..e42fe40 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c
index 0e0b5bb..0e0b5bb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h
index ea41bc8..ea41bc8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c
index 4a408b6..4a408b6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Cascade_Synchro/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
index 8095899..8095899 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt
index 4174001..4174001 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c
index 4ebbc9b..4ebbc9b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
new file mode 100644
index 0000000..f1266dd
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/main.c
@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file    TIM/DMA/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup TIM_DMA
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TIM1_CCR3_Address    0x40012C3C
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+TIM_OCInitTypeDef  TIM_OCInitStructure;
+uint16_t SRC_Buffer[3] = {0, 0, 0};
+uint16_t TimerPeriod = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+void DMA_Configuration(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* GPIO Configuration */
+  GPIO_Configuration();
+
+  /* DMA Configuration */
+  DMA_Configuration();
+
+  /* TIM1 DMA Transfer example -------------------------------------------------
+  TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
+  SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
+  and Connectivity line devices and to 24 MHz for Low-Density Value line and
+  Medium-Density Value line devices.
+
+  The objective is to configure TIM1 channel 3 to generate complementary PWM
+  signal with a frequency equal to 17.57 KHz:
+     - TIM1_Period = (SystemCoreClock / 17570) - 1
+  and a variable duty cycle that is changed by the DMA after a specific number of
+  Update DMA request.
+
+  The number of this repetitive requests is defined by the TIM1 Repetition counter,
+  each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new 
+  value defined by the SRC_Buffer . 
+  -----------------------------------------------------------------------------*/
+  /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
+  TimerPeriod = (SystemCoreClock / 17570 ) - 1;
+  /* Compute CCR1 value to generate a duty cycle at 50% */
+  SRC_Buffer[0] = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
+  /* Compute CCR1 value to generate a duty cycle at 37.5% */
+  SRC_Buffer[1] = (uint16_t) (((uint32_t) 375 * (TimerPeriod - 1)) / 1000);
+  /* Compute CCR1 value to generate a duty cycle at 25% */
+  SRC_Buffer[2] = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
+
+  /* TIM1 Peripheral Configuration --------------------------------------------*/
+  /* Time Base configuration */
+  TIM_TimeBaseStructure.TIM_Prescaler = 0;
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+  TIM_TimeBaseStructure.TIM_RepetitionCounter = 2;
+
+  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
+
+  /* Channel 3 Configuration in PWM mode */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = SRC_Buffer[0];
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
+  TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
+  TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
+  TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
+
+  TIM_OC3Init(TIM1, &TIM_OCInitStructure);
+
+  /* TIM1 Update DMA Request enable */
+  TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
+
+  /* TIM1 counter enable */
+  TIM_Cmd(TIM1, ENABLE);
+
+  /* Main Output Enable */
+  TIM_CtrlPWMOutputs(TIM1, ENABLE);
+
+  while (1)
+  {}
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* TIM1, GPIOA and GPIOB clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA |
+                         RCC_APB2Periph_GPIOB, ENABLE);
+  /* DMA clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+}
+
+/**
+  * @brief  Configure the TIM1 Pins.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* GPIOA Configuration: Channel 3 as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* GPIOB Configuration: Channel 3N as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Configures the DMA.
+  * @param  None
+  * @retval None
+  */
+void DMA_Configuration(void)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+
+  /* DMA1 Channel5 Config */
+  DMA_DeInit(DMA1_Channel5);
+
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_CCR3_Address;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = 3;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+
+  DMA_Init(DMA1_Channel5, &DMA_InitStructure);
+
+  /* DMA1 Channel5 enable */
+  DMA_Cmd(DMA1_Channel5, ENABLE);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {}
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt
index 436b3fb..436b3fb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
index 7fca938..7fca938 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h
index e5284ca..e5284ca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c
index ed65f3b..ed65f3b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMA/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c
new file mode 100644
index 0000000..af8bbf8
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/main.c
@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    TIM/DMABurst/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup TIM_DMABurst
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TIM1_DMAR_ADDRESS ((uint32_t)0x40012C4C) /* TIM ARR (Auto Reload Register) address */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+GPIO_InitTypeDef         GPIO_InitStructure;
+DMA_InitTypeDef          DMA_InitStructure;
+TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+TIM_OCInitTypeDef        TIM_OCInitStructure;
+uint16_t SRC_Buffer[6] = {0x0FFF, 0x0000, 0x0555};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* TIM1 and GPIOA clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+  /* DMA clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+  
+  /* GPIOA Configuration: Channel 1 as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_8;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);  
+
+  /* TIM1 DeInit */
+  TIM_DeInit(TIM1);
+
+  /* DMA1 Channel5 Config */
+  DMA_DeInit(DMA1_Channel5);
+
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_DMAR_ADDRESS; 
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer; 
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = 3;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(DMA1_Channel5, &DMA_InitStructure);
+  
+  /* Time base configuration */
+  /* -----------------------------------------------------------------------
+    TIM1 Configuration: generate 1 PWM signal using the DMA burst mode:
+    The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
+    clock at 24 MHz the Prescaler is computed as following:
+     - Prescaler = (TIM1CLK / TIM1 counter clock) - 1
+    SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
+    and Connectivity line devices and to 24 MHz for Low-Density Value line and
+    Medium-Density Value line devices
+
+    The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
+                                               = 24 MHz / 4096 = 5.8KHz KHz
+    TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33%
+  ----------------------------------------------------------------------- */  
+  TIM_TimeBaseStructure.TIM_Period = 0xFFFF;          
+  TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1;       
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;    
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;   
+  TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
+
+  /* TIM Configuration in PWM Mode */
+  TIM_OCInitStructure.TIM_OCMode =  TIM_OCMode_PWM1;    
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;          
+  TIM_OCInitStructure.TIM_Pulse = 0xFFF;  
+  TIM_OC1Init(TIM1, &TIM_OCInitStructure); 
+
+  /* TIM1 DMAR Base register and DMA Burst Length Config */
+  TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers);
+
+  /* TIM1 DMA Update enable */
+  TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
+
+  /* TIM1 enable */
+  TIM_Cmd(TIM1, ENABLE);
+  
+  /* TIM1 PWM Outputs Enable */
+  TIM_CtrlPWMOutputs(TIM1, ENABLE);
+
+  /* DMA1 Channel5 enable */
+  DMA_Cmd(DMA1_Channel5, ENABLE);
+
+  /* Wait until DMA1 Channel5 end of Transfer */
+  while (!DMA_GetFlagStatus(DMA1_FLAG_TC5))
+  {
+  }
+
+  /* Infinite loop */ 
+  while(1)
+  {
+  }
+}
+
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {}
+}
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c
index b5ab495..d63d587 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/FSMC/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    DMA/FSMC/stm32f10x_it.c 
+  * @file    TIM/DMABurst/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup DMA_FSMC
+/** @addtogroup TIM_DMABurst
   * @{
   */ 
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h
index 658cd79..d8fbfd4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ADC1_DMA/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    ADC/ADC1_DMA/stm32f10x_it.h 
+  * @file    TIM/DMABurst/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c
new file mode 100644
index 0000000..6bd940a
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    TIM/DMABurst/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
index 13e96b4..13e96b4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/main.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt
new file mode 100644
index 0000000..cb3db14
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/readme.txt
@@ -0,0 +1,138 @@
+/**
+  @page TIM_ExtTrigger_Synchro TIM External Trigger Synchro example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    TIM/ExtTrigger_Synchro/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the TIM External Trigger Synchro example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example shows how to synchronize TIM peripherals in cascade mode with an
+external trigger.
+In this example three timers are used:
+
+1/TIM1 is configured as Master Timer:
+  - Toggle Mode is used
+  - The TIM1 Enable event is used as Trigger Output 
+
+2/TIM1 is configured as Slave Timer for an external Trigger connected to TIM1 
+  TI2 pin (TIM1 CH2 configured as input pin):
+  - The TIM1 TI2FP2 is used as Trigger Input
+  - Rising edge is used to start and stop the TIM1: Gated Mode.
+
+3/TIM3 is slave for TIM1 and Master for TIM4,
+  - Toggle Mode is used
+  - The ITR1(TIM1) is used as input trigger 
+  - Gated mode is used, so start and stop of slave counter
+    are controlled by the Master trigger output signal(TIM1 enable event).
+  - The TIM3 enable event is used as Trigger Output. 
+
+4/TIM4 is slave for TIM3,
+  - Toggle Mode is used
+  - The ITR2(TIM3) is used as input trigger
+  - Gated mode is used, so start and stop of slave counter
+    are controlled by the Master trigger output signal(TIM3 enable event).
+
+  * For Low-density, Medium-density, High-density and Connectivity line devices:
+    The TIMxCLK is fixed to 72 MHZ, the Prescaler is equal to 2 so the TIMx clock 
+    counter is equal to 24 MHz.
+    The Three Timers are running at: 
+    TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz.
+
+  * For Low-Density Value line, Medium-Density Value line and High-Density Value line devices:
+    The TIMxCLK is fixed to 24 MHz, the Prescaler is equal to 2 so the TIMx clock 
+    counter is equal to 8 MHz.
+    TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 54 KHz.
+
+The starts and stops of the TIM1 counters are controlled by the external trigger.
+The TIM3 starts and stops are controlled by the TIM1, and the TIM4 starts and 
+stops are controlled by the TIM3.  
+
+@par Directory contents 
+
+  - TIM/ExtTrigger_Synchro/stm32f10x_conf.h    Library Configuration file
+  - TIM/ExtTrigger_Synchro/stm32f10x_it.c      Interrupt handlers
+  - TIM/ExtTrigger_Synchro/stm32f10x_it.h      Interrupt handlers header file
+  - TIM/ExtTrigger_Synchro/main.c              Main program 
+  - TIM/ExtTrigger_Synchro/system_stm32f10x.c  STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
+    and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
+    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
+    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
+    evaluation boards and can be easily tailored to any other supported device 
+    and development board.
+
+  - STM32100B-EVAL Set-up 
+    - Connect an external trigger, with a frequency <=  xx KHz, to the TIM1 CH2 
+      pin (PA.09). In this example the frequency is equal to x KHz.
+
+    - Connect the following pins to an oscilloscope to monitor the different waveforms:
+      - TIM1 CH1 (PA.08)
+      - TIM3 CH1 (PA.06)
+      - TIM4 CH1 (PB.06)
+      
+  - STM3210C-EVAL Set-up 
+    - Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2 
+      pin (PE.11). In this example the frequency is equal to 5 KHz.
+
+    - Connect the following pins to an oscilloscope to monitor the different waveforms:
+      - TIM1 CH1 (PE.09)
+      - TIM3 CH1 (PC.06)
+      - TIM4 CH1 (PB.06)   
+
+  - STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
+    - Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2 
+      pin (PA.09). In this example the frequency is equal to 5 KHz.
+
+    - Connect the following pins to an oscilloscope to monitor the different waveforms:
+      - TIM1 CH1 (PA.08)
+      - TIM3 CH1 (PA.06)
+      - TIM4 CH1 (PB.06)    
+  
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h
index 2481540..2481540 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c
index a0540f0..a0540f0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h
index be90925..fa673a8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CRC/CRC_Calculation/stm32f10x_it.h 
+  * @file    TIM/ExtTrigger_Synchro/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c
index 584f560..cea3764 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ExtTrigger_Synchro/system_stm32f10x.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    FLASH/Write_Protection/system_stm32f10x.c
+  * @file    TIM/ExtTrigger_Synchro/system_stm32f10x.c
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h
index a1620b0..a1620b0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
index 61a3258..61a3258 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h
index 8ad4cc3..8ad4cc3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
index 8691aa2..8691aa2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h
index df1947d..df1947d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c
index 822ef7d..822ef7d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h
index 8dd2f45..8dd2f45 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c
index 0f6a448..0f6a448 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c
index 98e6bc1..98e6bc1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt
index c0ea6a0..c0ea6a0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h
index 156e993..156e993 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c
index a6d417f..a6d417f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
index 02716ff..02716ff 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCInactive/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c
index 6f70494..5498f0f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/main.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/main.c 
+  * @file    TIM/OCToggle/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -26,7 +26,7 @@
   * @{
   */
 
-/** @addtogroup TIM9_OCToggle
+/** @addtogroup TIM_OCToggle
   * @{
   */ 
 
@@ -36,11 +36,14 @@
 /* Private variables ---------------------------------------------------------*/
 TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
 TIM_OCInitTypeDef  TIM_OCInitStructure;
-__IO uint16_t CCR1Val = 32768;
-__IO uint16_t CCR2Val = 16384;
+__IO uint16_t CCR1_Val = 32768;
+__IO uint16_t CCR2_Val = 16384;
+__IO uint16_t CCR3_Val = 8192;
+__IO uint16_t CCR4_Val = 4096;
 uint16_t PrescalerValue = 0;
 
 /* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
 void GPIO_Configuration(void);
 void NVIC_Configuration(void);
 
@@ -60,19 +63,24 @@ int main(void)
        system_stm32f10x.c file
      */     
        
-  /* Configure TIM9 pins */
-  GPIO_Configuration();
+  /* System Clocks Configuration */
+  RCC_Configuration();
 
   /* NVIC Configuration */
   NVIC_Configuration();
 
+  /* GPIO Configuration */
+  GPIO_Configuration();
+
   /* ---------------------------------------------------------------------------
-    TIM9 Configuration: Output Compare Toggle Mode:
-    TIM9CLK = SystemCoreClock (72MHz),
-    The objective is to get TIM9 counter clock at 24 MHz:
-     - Prescaler = (TIM9CLK / TIM9 counter clock) - 1
-    CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz
-    CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8 Hz
+    TIM3 Configuration: Output Compare Toggle Mode:
+    TIM3CLK = SystemCoreClock / 2,
+    The objective is to get TIM3 counter clock at 12 MHz:
+     - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
+    CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz
+    CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz
+    CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz
+    CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz
   ----------------------------------------------------------------------------*/
   /* Compute the prescaler value */
   PrescalerValue = (uint16_t) (SystemCoreClock / 24000000) - 1;
@@ -83,38 +91,71 @@ int main(void)
   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
 
-  TIM_TimeBaseInit(TIM9, &TIM_TimeBaseStructure);
+  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
 
   /* Output Compare Toggle Mode configuration: Channel1 */
   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR1Val;
+  TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
-  TIM_OC1Init(TIM9, &TIM_OCInitStructure);
+  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
 
-  TIM_OC1PreloadConfig(TIM9, TIM_OCPreload_Disable);
+  TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable);
 
   /* Output Compare Toggle Mode configuration: Channel2 */
   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = CCR2Val;
+  TIM_OCInitStructure.TIM_Pulse = CCR2_Val;
+
+  TIM_OC2Init(TIM3, &TIM_OCInitStructure);
+
+  TIM_OC2PreloadConfig(TIM3, TIM_OCPreload_Disable);
+
+  /* Output Compare Toggle Mode configuration: Channel3 */
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = CCR3_Val;
 
-  TIM_OC2Init(TIM9, &TIM_OCInitStructure);
+  TIM_OC3Init(TIM3, &TIM_OCInitStructure);
 
-  TIM_OC2PreloadConfig(TIM9, TIM_OCPreload_Disable);
+  TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable);
+
+  /* Output Compare Toggle Mode configuration: Channel4 */
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;
+
+  TIM_OC4Init(TIM3, &TIM_OCInitStructure);
+
+  TIM_OC4PreloadConfig(TIM3, TIM_OCPreload_Disable);
 
   /* TIM enable counter */
-  TIM_Cmd(TIM9, ENABLE);
+  TIM_Cmd(TIM3, ENABLE);
 
   /* TIM IT enable */
-  TIM_ITConfig(TIM9, TIM_IT_CC1 | TIM_IT_CC2, ENABLE);
+  TIM_ITConfig(TIM3, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
 
   while (1)
-  {
-  }
+  {}
 }
 
 /**
-  * @brief  Configure TIM9 pins.
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* PCLK1 = HCLK/4 */
+  RCC_PCLK1Config(RCC_HCLK_Div4);
+
+  /* TIM3 clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
+
+  /* GPIOA clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB|
+                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
+}
+
+/**
+  * @brief  Configure the TIM3 Pins.
   * @param  None
   * @retval None
   */
@@ -122,15 +163,27 @@ void GPIO_Configuration(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
 
-  /* Enable TIM9 and GPIOA clock  */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9 | RCC_APB2Periph_GPIOA, ENABLE);
-  
-  /* GPIOA Configuration:TIM9 Channel1 and 2 as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
+#ifdef STM32F10X_CL
+  /*GPIOB Configuration: TIM3 channel1, 2, 3 and 4 */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
+
+#else
+  /* GPIOA Configuration:TIM3 Channel1, 2, 3 and 4 as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  
+
   GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+#endif
 }
 
 /**
@@ -142,8 +195,8 @@ void NVIC_Configuration(void)
 {
   NVIC_InitTypeDef NVIC_InitStructure;
 
-  /* Enable the TIM9 global Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel =  TIM1_BRK_TIM9_IRQn;
+  /* Enable the TIM3 global Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
   NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
   NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
   NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/readme.txt
index e285817..06d8bb6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCActive/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page TIM_OCActive TIM OC Active example
+  @page TIM_OCToggle TIM OC Toggle example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/OCActive/readme.txt 
+  * @file    TIM/OCToggle/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the TIM OC Active example.
+  * @brief   Description of the TIM OC Toggle example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,50 +20,42 @@
 
 @par Example Description 
 
-This example shows how to configure the TIM peripheral to generate four different 
-signals with four different delays.
+This example shows how to configure the TIM3 peripheral to generate four different 
+signals with four different frequencies.
 
-The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
-to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following:
+The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and we want to get TIM3
+counter clock at 12 MHz so the Prescaler is computed as following:
    - Prescaler = (TIM3CLK / TIM3 counter clock) - 1
 SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
 and Connectivity line devices and to 24 MHz for Low-Density Value line,
-Medium-Density Value line and High-Density Value line devices.
+Medium-Density Value line and High-Density devices.
 
-The TIM3 CCR1 register value is equal to 1000:
-TIM3_CH1 delay = CCR1_Val/TIM3 counter clock  = 1000 ms
-so the TIM3 Channel 1 generates a signal with a delay equal to 1000 ms.
+The TIM3 CCR1 register value is equal to 32768: 
+CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz,
+so the TIM3 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz.
 
-The TIM3 CCR2 register value is equal to 500:
-TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms
-so the TIM3 Channel 2 generates a signal with a delay equal to 500 ms.
+The TIM3 CCR2 register is equal to 16384:
+CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz
+so the TIM3 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz.
 
-The TIM3 CCR3 register value is equal to 250:
-TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms
-so the TIM3 Channel 3 generates a signal with a delay equal to 250 ms.
+The TIM3 CCR3 register is equal to 8192:
+CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz
+so the TIM3 channel 3 generates a periodic signal with a frequency equal to 732.4 Hz.
 
-The TIM3 CCR4 register value is equal to 125:
-TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms
-so the TIM3 Channel 4 generates a signal with a delay equal to 125 ms.
-
-The delay correspond to the time difference between PC.06 and 
-TIM3_CHx signal rising edges in case of STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL 
-and STM3210B-EVAL 
-
-The delay correspond to the time difference between PD.07 and 
-TIM3_CHx signal rising edges in case of STM3210C-EVAL
+The TIM3 CCR4 register is equal to 4096:
+CC4 update rate = TIM3 counter clock / CCR4_Val =  2929.6 Hz
+so the TIM3 channel 4 generates a periodic signal with a frequency equal to 1464.8 Hz.
 
 @par Directory contents 
 
-  - TIM/OCActive/stm32f10x_conf.h    Library Configuration file
-  - TIM/OCActive/stm32f10x_it.c      Interrupt handlers
-  - TIM/OCActive/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/OCActive/main.c              Main program 
-  - TIM/OCActive/system_stm32f10x.c  STM32F10x system source file
+  - TIM/OCToggle/stm32f10x_conf.h    Library Configuration file
+  - TIM/OCToggle/stm32f10x_it.c      Interrupt handlers
+  - TIM/OCToggle/stm32f10x_it.h      Interrupt handlers header file
+  - TIM/OCToggle/main.c              Main program
+  - TIM/OCToggle/system_stm32f10x.c  STM32F10x system source file
   
 @par Hardware and Software environment 
 
-
   - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
     Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
@@ -76,22 +68,20 @@ TIM3_CHx signal rising edges in case of STM3210C-EVAL
     
 
   - STM3210C-EVAL Set-up 
-    - Connect the TIM3 pins(TIM3 full remapped pins) to an oscilloscope to
-      monitor the different waveforms:
-       - PD.07
+    - Connect the TIM1 pins(TIM3 full remapped pins) to an oscilloscope to monitor 
+      the different waveforms:
        - PC.06 (TIM3_CH1)
        - PC.07 (TIM3_CH2)
        - PC.08 (TIM3_CH3)
        - PC.09 (TIM3_CH4)
 
-  - STM32100E-EVAL, STM32100B-EVAL, STM3210E-EVAL and STM3210B-EVAL Set-up 
+  - STM32100B-EVAL, STM3210E-EVAL, STM32100E-EVAL and STM3210B-EVAL Set-up 
     - Connect the following pins to an oscilloscope to monitor the different 
       waveforms:
-       - PC.06
        - PA.06 (TIM3_CH1)
        - PA.07 (TIM3_CH2)
        - PB.00 (TIM3_CH3)
-       - PB.01 (TIM3_CH4)
+       - PB.01 (TIM3_CH4) 
   
 @par How to use it ? 
 
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h
new file mode 100644
index 0000000..47fca7d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    TIM/OCToggle/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_cec.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
index a5bac39..a5bac39 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h
index 93e159b..93e159b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c
new file mode 100644
index 0000000..d53ad96
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OCToggle/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    TIM/OCToggle/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c
index 75ccc2f..75ccc2f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt
index 2c01dca..2c01dca 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c
index eca0ad8..eca0ad8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c
new file mode 100644
index 0000000..b430f26
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/main.c
@@ -0,0 +1,178 @@
+/**
+  ******************************************************************************
+  * @file    TIM/PWM_Input/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup TIM_PWM_Input
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_ICInitTypeDef  TIM_ICInitStructure;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+void NVIC_Configuration(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* NVIC configuration */
+  NVIC_Configuration();
+
+  /* Configure the GPIO ports */
+  GPIO_Configuration();
+
+  /* TIM3 configuration: PWM Input mode ------------------------
+     The external signal is connected to TIM3 CH2 pin (PA.01), 
+     The Rising edge is used as active edge,
+     The TIM3 CCR2 is used to compute the frequency value 
+     The TIM3 CCR1 is used to compute the duty cycle value
+  ------------------------------------------------------------ */
+
+  TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
+  TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStructure.TIM_ICFilter = 0x0;
+
+  TIM_PWMIConfig(TIM3, &TIM_ICInitStructure);
+
+  /* Select the TIM3 Input Trigger: TI2FP2 */
+  TIM_SelectInputTrigger(TIM3, TIM_TS_TI2FP2);
+
+  /* Select the slave Mode: Reset Mode */
+  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Reset);
+
+  /* Enable the Master/Slave Mode */
+  TIM_SelectMasterSlaveMode(TIM3, TIM_MasterSlaveMode_Enable);
+
+  /* TIM enable counter */
+  TIM_Cmd(TIM3, ENABLE);
+
+  /* Enable the CC2 Interrupt Request */
+  TIM_ITConfig(TIM3, TIM_IT_CC2, ENABLE);
+
+  while (1);
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* TIM3 clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
+
+  /* GPIOA clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+}
+
+/**
+  * @brief  Configure the GPIO Pins.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* TIM3 channel 2 pin (PA.07) configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Configure the nested vectored interrupt controller.
+  * @param  None
+  * @retval None
+  */
+void NVIC_Configuration(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* Enable the TIM3 global Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  while (1)
+  {}
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt
index 10772aa..10772aa 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h
index 37b05f7..37b05f7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
index f22491d..994ff18 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.c
@@ -1,12 +1,12 @@
 /**
   ******************************************************************************
-  * @file    RTC/Calendar/stm32f10x_it.c 
+  * @file    TIM/PWM_Input/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
   * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and
-  *          peripherals interrupt service routine.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
   ******************************************************************************
   * @attention
   *
@@ -19,17 +19,16 @@
   *
   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */
+  */ 
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
-#include "stm32_eval.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
 
-/** @addtogroup RTC_Calendar
+/** @addtogroup TIM_PWM_Input
   * @{
   */ 
 
@@ -37,7 +36,9 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-extern __IO uint32_t TimeDisplay;
+__IO uint16_t IC2Value = 0;
+__IO uint16_t DutyCycle = 0;
+__IO uint32_t Frequency = 0;
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -109,8 +110,7 @@ void UsageFault_Handler(void)
   * @retval None
   */
 void DebugMon_Handler(void)
-{
-}
+{}
 
 /**
   * @brief  This function handles SVCall exception.
@@ -118,8 +118,7 @@ void DebugMon_Handler(void)
   * @retval None
   */
 void SVC_Handler(void)
-{
-}
+{}
 
 /**
   * @brief  This function handles PendSV_Handler exception.
@@ -127,8 +126,7 @@ void SVC_Handler(void)
   * @retval None
   */
 void PendSV_Handler(void)
-{
-}
+{}
 
 /**
   * @brief  This function handles SysTick Handler.
@@ -136,34 +134,37 @@ void PendSV_Handler(void)
   * @retval None
   */
 void SysTick_Handler(void)
-{
-}
+{}
 
 /******************************************************************************/
 /*            STM32F10x Peripherals Interrupt Handlers                        */
 /******************************************************************************/
 
 /**
-  * @brief  This function handles RTC global interrupt request.
+  * @brief  This function handles TIM3 global interrupt request.
   * @param  None
   * @retval None
   */
-void RTC_IRQHandler(void)
+void TIM3_IRQHandler(void)
 {
-  if (RTC_GetITStatus(RTC_IT_SEC) != RESET)
-  {
-    /* Clear the RTC Second interrupt */
-    RTC_ClearITPendingBit(RTC_IT_SEC);
+  /* Clear TIM3 Capture compare interrupt pending bit */
+  TIM_ClearITPendingBit(TIM3, TIM_IT_CC2);
 
-    /* Toggle LED1 */
-    STM_EVAL_LEDToggle(LED1);
+  /* Get the Input Capture value */
+  IC2Value = TIM_GetCapture2(TIM3);
 
-    /* Enable time update */
-    TimeDisplay = 1;
+  if (IC2Value != 0)
+  {
+    /* Duty cycle computation */
+    DutyCycle = (TIM_GetCapture1(TIM3) * 100) / IC2Value;
 
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-    
+    /* Frequency computation */
+    Frequency = SystemCoreClock / IC2Value;
+  }
+  else
+  {
+    DutyCycle = 0;
+    Frequency = 0;
   }
 }
 
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h
new file mode 100644
index 0000000..2f22517
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/stm32f10x_it.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    TIM/PWM_Input/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM3_IRQHandler(void);
+					 
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c
index 00a2f82..00a2f82 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Input/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt
index 469aa30..469aa30 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h
index 605b2ad..605b2ad 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c
index 01c4cb1..01c4cb1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h
index bfcc9ea..bfcc9ea 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/PWM_Output/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt
index 4629719..4629719 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/readme.txt
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h
new file mode 100644
index 0000000..9e78b79
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_conf.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    TIM/Parallel_Synchro/stm32f10x_conf.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_cec.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
index c0c16e2..c0c16e2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c
index edfb4ad..edfb4ad 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
index 4647dfb..4647dfb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/readme.txt
index 8503879..0282e23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page TIM9_OCToggle TIM9 OC Toggle example
+  @page TIM10_PWMOutput TIM10 PWM Output example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    TIM/TIM9_OCToggle/readme.txt 
+  * @file    TIM/TIM10_PWMOutput/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the TIM9 OC Toggle example.
+  * @brief   Description of the  TIM10 PWM Output example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -18,32 +18,32 @@
   ******************************************************************************
    @endverbatim
 
-@par Example Description 
+@par Example Description
 
-This example shows how to configure the TIM9 peripheral to generate two different 
-signals with two different frequencies.
+This example shows how to configure the TIM10 peripheral in PWM (Pulse Width Modulation) 
+mode.
 
-The TIM9CLK frequency is set to SystemCoreClock (72 MHz), and we want to get TIM9
-counter clock at 24 MHz so the Prescaler is computed as following:
-   - Prescaler = (TIM9CLK / TIM9 counter clock) - 1
+The TIM10CLK frequency is set to SystemCoreClock (72 MHz), to get TIM10 counter
+clock at 24 MHz the Prescaler is computed as following:
+   - Prescaler = (TIM10CLK / TIM10 counter clock) - 1
 
-The TIM9 CCR1 register value is equal to 32768: 
-CC1 update rate = TIM9 counter clock / CCR1Val = 732.4 Hz,
-so the TIM9 Channel 1 generates a periodic signal with a frequency equal to 366.2 Hz.
+The TIM10 is running at 36 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1)
+                                                = 24 MHz / 666 = 36 KHz
+The TIM10 CCR1 register value is equal to 500, so the TIM10 Channel 1 generates a 
+PWM signal with a frequency equal to 36 KHz and a duty cycle equal to 37.5%:
+TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR + 1)* 100 = 37.5%
 
-The TIM9 CCR2 register is equal to 16384:
-CC2 update rate = TIM9 counter clock / CCR2Val = 1464.8
-so the TIM9 channel 2 generates a periodic signal with a frequency equal to 732.4 Hz.
+The PWM waveform can be displayed using an oscilloscope.
 
 
 @par Directory contents 
 
-  - TIM/TIM9_OCToggle/stm32f10x_conf.h    Library Configuration file
-  - TIM/TIM9_OCToggle/stm32f10x_it.c      Interrupt handlers
-  - TIM/TIM9_OCToggle/stm32f10x_it.h      Interrupt handlers header file
-  - TIM/TIM9_OCToggle/main.c              Main program
-  - TIM/TIM9_OCToggle/system_stm32f10x.c  STM32F10x system source file
-  
+  - TIM/TIM10_PWMOutput/stm32f10x_conf.h    Library Configuration file
+  - TIM/TIM10_PWMOutput/stm32f10x_it.c      Interrupt handlers
+  - TIM/TIM10_PWMOutput/stm32f10x_it.h      Interrupt handlers header file
+  - TIM/TIM10_PWMOutput/main.c              Main program 
+  - TIM/TIM10_PWMOutput/system_stm32f10x.c  STM32F10x system source file
+
 @par Hardware and Software environment 
 
   - This example runs only on STM32F10x XL-Density Devices.
@@ -52,11 +52,9 @@ so the TIM9 channel 2 generates a periodic signal with a frequency equal to 732.
     evaluation board and can be easily tailored to any development board.    
 
   - STM3210E-EVAL Set-up 
-    - Connect the TIM9 pins to an oscilloscope to monitor the different waveforms:
-       - PA.02 (TIM9_CH1)
-       - PA.03 (TIM9_CH2)
-  
+    - Connect PF.06 (TIM10_CH1 remapped pin) to an oscilloscope to monitor the PWM waveform
 
+  
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h
index de24e23..49f4048 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/AnalogWatchdog/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    ADC/AnalogWatchdog/stm32f10x_conf.h 
+  * @file    TIM/TIM10_PWMOutput/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h
index 9bc9dae..9bc9dae 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
index d04db27..d04db27 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM10_PWMOutput/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/readme.txt
new file mode 100644
index 0000000..c531058
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/readme.txt
@@ -0,0 +1,97 @@
+/**
+  @page TIM15_ComplementarySignals TIM15 Complementary Signals example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    TIM/TIM15_ComplementarySignals/readme.txt 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Description of the TIM15 Complementary Signals example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example shows how to configure the TIM15 peripheral to generate one 
+complementary TIM15 signal, to insert a defined dead time value, to use the break 
+feature and to lock the desired parameters.
+
+TIM15CLK is fixed to 24 MHz, the TIM15 Prescaler is equal to 0 so the TIM15 counter
+clock used is 24 MHz.
+
+TIM15 frequency is defined as follow:
+TIM15 frequency = TIM15 counter clock / (TIM15_Period + 1) = 366 Hz.
+
+The Duty cycles is computed as the following description: 
+
+- TIM15 Channel1 duty cycle = TIM15_CCR1 / (TIM15_Period + 1) = 50% 
+- TIM15 Channel1N duty cycle = (TIM15_Period - TIM15_CCR1) / (TIM15_Period + 1) = 50%
+
+A dead time of 1.62 us is inserted between the different complementary signals, 
+and the Lock level 1 is selected.
+The break Polarity is used at High level.
+
+The TIM15 waveform can be displayed using an oscilloscope.
+
+@par Directory contents 
+
+  - TIM/TIM15_ComplementarySignals/stm32f10x_conf.h    Library Configuration file
+  - TIM/TIM15_ComplementarySignals/stm32f10x_it.c      Interrupt handlers
+  - TIM/TIM15_ComplementarySignals/stm32f10x_it.h      Interrupt handlers header file
+  - TIM/TIM15_ComplementarySignals/main.c              Main program
+  - TIM/TIM15_ComplementarySignals/system_stm32f10x.c  STM32F10x system source file
+  
+@par Hardware and Software environment 
+
+  - This example runs on High-Density Value line, STM32F10x Medium-Density Value 
+    line and Low-Density Value line Devices.
+  
+  - This example has been tested with STMicroelectronics STM32100E-EVAL 
+    (STM32F10x High-Density Value line) and STM32100B-EVAL (Medium-Density Value 
+    line) evaluation boards and can be easily tailored to any other supported 
+    device and development board.
+    
+  - STM32100E-EVAL and STM32100B-EVAL Set-up 
+    - Connect the TIM15 pins to an oscilloscope to monitor the different waveforms:
+      - TIM15_CH1  pin (PA.02)  
+      - TIM15_CH1N pin (PB.15)  
+
+    - Connect the TIM15 break pin TIM15_BKIN pin (PA.09) to the GND. To generate 
+      a break event, switch this pin level from 0V to 3.3V.  
+  
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+ - Copy all source files from this example folder to the template folder under
+   Project\STM32F10x_StdPeriph_Template
+ - Open your preferred toolchain 
+ - Rebuild all files and load your image into target memory
+ - Run the example 
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 64 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+   
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
index 63f89d0..63f89d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c
index e8d9453..e8d9453 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h
index 65efd6f..65efd6f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c
new file mode 100644
index 0000000..07dbdbb
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM15_ComplementarySignals/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    TIM/TIM15_ComplementarySignals/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
index 4b7a836..4b7a836 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt
index cefbfa3..cefbfa3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h
index 7473e1b..7473e1b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c
index c825c9e..c825c9e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h
index 1dae652..1dae652 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c
index 80962ef..80962ef 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM1_Synchro/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
index 86fd78c..86fd78c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h
new file mode 100644
index 0000000..6eef077
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_it.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    TIM/TIM9_OCToggle/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void TIM3_IRQHandler(void);
+					 
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c
index 082a454..082a454 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
index d142cfb..d142cfb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt
index f893802..f893802 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h
index c591b11..c591b11 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c
new file mode 100644
index 0000000..4be629f
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TimeBase/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    TIM/TimeBase/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
index 9755d00..9755d00 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt
index 0d6da30..0d6da30 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h
index 71d01ea..71d01ea 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
index 7dd43d3..7dd43d3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h
index 9f6a0d7..9f6a0d7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/stm32f10x_it.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c
new file mode 100644
index 0000000..d8696d9
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    USART/DMA_Interrupt/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
index c1fd617..c1fd617 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h
index 2a4cf2f..2a4cf2f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt
index 5f83a83..5f83a83 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h
index af84449..af84449 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c
index cd3a452..6a94664 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CRC/CRC_Calculation/stm32f10x_it.c 
+  * @file    USART/DMA_Polling/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup CRC_Calculation
+/** @addtogroup USART_DMA_Polling
   * @{
   */ 
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h
index cd40698..f459a8c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/BitBand/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CortexM3/BitBand/stm32f10x_it.h 
+  * @file    USART/DMA_Polling/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c
new file mode 100644
index 0000000..77a3608
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Polling/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    USART/DMA_Polling/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
index a9425cf..a9425cf 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt
index 9c74140..9c74140 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h
index b3cb77f..b3cb77f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c
index c17e8dc..2ae5127 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_it.c 
+  * @file    USART/HalfDuplex/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -28,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup BKP_Backup_Data
+/** @addtogroup USART_HalfDuplex
   * @{
   */ 
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h
index f5bb61c..0fc3f35 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NAND/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    FSMC/NAND/stm32f10x_it.h 
+  * @file    USART/HalfDuplex/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c
new file mode 100644
index 0000000..6f3916c
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/main.c
@@ -0,0 +1,191 @@
+/**
+  ******************************************************************************
+  * @file    USART/HyperTerminal_HwFlowControl/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "platform_config.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup USART_HyperTerminal_HwFlowControl
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TxBufferSize   (countof(TxBuffer) - 1)
+#define RxBufferSize   0xFF
+
+/* Private macro -------------------------------------------------------------*/
+#define countof(a)   (sizeof(a) / sizeof(*(a)))
+
+/* Private variables ---------------------------------------------------------*/
+USART_InitTypeDef USART_InitStructure;
+uint8_t TxBuffer[] = "\n\rUSART Hyperterminal Hardware Flow Control Example: USART - \
+Hyperterminal communication using hardware flow control\n\r";
+uint8_t RxBuffer[RxBufferSize];
+uint8_t NbrOfDataToTransfer = TxBufferSize;
+uint8_t TxCounter = 0;
+uint8_t RxCounter = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+  
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief   Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* Configure the GPIO ports */
+  GPIO_Configuration();
+  
+/* USART2 configuration ------------------------------------------------------*/
+  /* USART2 configured as follow:
+        - BaudRate = 115200 baud  
+        - Word Length = 8 Bits
+        - One Stop Bit
+        - No parity
+        - Hardware flow control enabled (RTS and CTS signals)
+        - Receive and transmit enabled
+  */
+  USART_InitStructure.USART_BaudRate = 115200;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No ;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+  USART_Init(USART2, &USART_InitStructure);
+  /* Enable the USART2 */
+  USART_Cmd(USART2, ENABLE);
+
+/* Communication hyperterminal-USART2 using hardware flow control -------------*/
+  /* Send a buffer from USART to hyperterminal */  
+  while(NbrOfDataToTransfer--)
+  {
+    USART_SendData(USART2, TxBuffer[TxCounter++]);
+    while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET);          
+  }
+  
+  /* Receive a string (Max RxBufferSize bytes) from the Hyperterminal ended by '\r' (Enter key) */
+  do
+  { 
+    if((USART_GetFlagStatus(USART2, USART_FLAG_RXNE) != RESET)&&(RxCounter < RxBufferSize))
+    {
+       RxBuffer[RxCounter] = USART_ReceiveData(USART2);
+       USART_SendData(USART2, RxBuffer[RxCounter++]);
+    }   
+ 
+  }while((RxBuffer[RxCounter - 1] != '\r')&&(RxCounter != RxBufferSize));
+
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{    
+  /* Enable GPIOx and AFIO clocks */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOx | RCC_APB2Periph_AFIO, ENABLE);
+
+  /* Enable USART2 clocks */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+}
+
+/**
+  * @brief  Configures the different GPIO ports.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
+  /* Enable the USART2 Pins Software Remapping */
+  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+#endif
+
+  /* Configure USART2 RTS and USART2 Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_RTSPin | GPIO_TxPin;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOx, &GPIO_InitStructure);
+
+  /* Configure USART2 CTS and USART2 Rx as input floating */
+  GPIO_InitStructure.GPIO_Pin = GPIO_CTSPin | GPIO_RxPin;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(GPIOx, &GPIO_InitStructure);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h
index 886b100..886b100 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/readme.txt
index 7d8dffd..3562811 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/readme.txt
@@ -1,13 +1,14 @@
 /**
-  @page USART_Synchronous USART Synchronous example
+  @page USART_HyperTerminal_HwFlowControl USART Hyperterminal Hardware Flow Control example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/Synchronous/readme.txt 
+  * @file    USART/HyperTerminal_HwFlowControl/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the USART Synchronous example.
+  * @brief   Description of the USART Hyperterminal Hardware Flow Control
+  *          example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,55 +21,37 @@
 
 @par Example Description 
 
-This example provides a basic communication between USARTy (Synchronous mode) 
-and SPIy using flags. USARTy and SPIy can be USART1 and SPI1 or USART2 and SPI3,
-depending on the STMicroelectronics EVAL board you are using.
-
-First, the USARTy sends data from TxBuffer1 buffer to SPIy using USARTy TXE flag.
-Data received, using RXNE flag, by SPIy is stored in RxBuffer2 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus1" 
-variable.
- 
-Then, the SPIy sends data from TxBuffer2 buffer to USARTy using SPIy TXE flag.
-Data received, using RXNE flag, by USARTy is stored in RxBuffer1 then compared with
-the sent ones and the result of this comparison is stored in the "TransferStatus2" 
-variable.
-
-USARTy configured as follow:
-  - BaudRate = 115200 baud  
-  - Word Length = 8 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled
-  - USART Clock enabled
-  - USART CPOL: Clock is active high
-  - USART CPHA: Data is captured on the second edge 
-  - USART LastBit: The clock pulse of the last data bit is output to the SCLK pin
-
-SPIy configured as follow:
-  - Direction = 2 Lines FullDuplex
-  - Mode = Slave Mode
-  - DataSize = 8 Bits
-  - CPOL = Clock is active high
-  - CPHA = Data is captured on the second edge 
-  - NSS = NSS Software
-  - First Bit = First Bit is the LSB  
+This example provides a description of how to use the USART with hardware flow
+control and communicate with the Hyperterminal.
+First, the USART2 sends the TxBuffer to the hyperterminal and still waiting for
+a string from the hyperterminal that you must enter which must end by '\r'
+character (keypad ENTER button). The communication will end if received data exceed
+255 without sending the '\r' character. Each byte received is retransmitted to the
+Hyperterminal.
+The string that you have entered is stored in the RxBuffer array. The receive
+buffer have a RxBufferSize bytes as maximum.
 
+The USART2 is configured as follow:
+    - BaudRate = 115200 baud  
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - No parity
+    - Hardware flow control enabled (RTS and CTS signals)
+    - Receive and transmit enabled
 
 @par Directory contents 
-  
-  - USART/Synchronous/platform_config.h    Evaluation board specific configuration file
-  - USART/Synchronous/stm32f10x_conf.h     Library Configuration file
-  - USART/Synchronous/stm32f10x_it.h       Interrupt handlers header file
-  - USART/Synchronous/stm32f10x_it.c       Interrupt handlers
-  - USART/Synchronous/main.c               Main program
-  - USART/Synchronous/system_stm32f10x.c   STM32F10x system source file
 
+  - USART/HyperTerminal_HwFlowControl/platform_config.h    Evaluation board specific configuration file
+  - USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h     Library Configuration file
+  - USART/HyperTerminal_HwFlowControl/stm32f10x_it.h       Interrupt handlers header file
+  - USART/HyperTerminal_HwFlowControl/stm32f10x_it.c       Interrupt handlers
+  - USART/HyperTerminal_HwFlowControl/main.c               Main program
+  - USART/HyperTerminal_HwFlowControl/system_stm32f10x.c   STM32F10x system source file
+  
 @par Hardware and Software environment 
 
   - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
+    Value line,Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
   
   - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
@@ -76,27 +59,40 @@ SPIy configured as follow:
     (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation 
     boards and can be easily tailored to any other supported device and development 
     board.
-    This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation
-    board since the USART CK pins are already used by other on-board modules.
+    This example can't be tested with STM3210C-EVAL (Connectivity Line) evaluation board.
     To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/Synchronous/platform_config.h file
+    uncomment the corresponding line in USART/HyperTerminal_HwFlowControl/platform_config.h file
 
   - STM32100E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).  
+    - Connect a null-modem female/female RS232 cable between CN10 and PC serial 
+      port.
+      @note Make sure the Jumper 5 (JP5) is not open.
       
   - STM32100B-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).      
+    - Connect a null-modem female/female RS232 cable between CN9 and PC serial 
+      port.
+      @note In this case USART2 Tx, Rx, RTS and CTS pins are remapped by software
+            on PD.05, PD.06, PD.04 and PD.03 respectively. 
 
   - STM3210E-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).
+    - Connect a null-modem female/female RS232 cable between CN8 and PC serial 
+      port.
+      @note Make sure the Jumper 4 (JP4) is in position 2<-->3.  
 
   - STM3210B-EVAL Set-up 
-    - Connect USART1_Tx(PA.09) to SPI1_MOSI(PA.07), USART1_Rx(PA.10) to 
-      SPI1_MISO(PA.06) and USART1_CK(PA.08) to SPI1_SCK(PA.05).        
+    - Connect a null-modem female/female RS232 cable between CN5 and PC serial 
+      port.
+      @note In this case USART2 Tx, Rx, RTS and CTS pins are remapped by software
+            on PD.05, PD.06, PD.04 and PD.03 respectively. 
+
  
+  - Hyperterminal configuration: 
+    - Word Length = 8 Bits
+    - One Stop Bit
+    - No parity
+    - BaudRate = 115200 baud
+    - flow control: Hardware 
+    
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
index f3355b9..f3355b9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
index 901616e..901616e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
index bd194dc..bd194dc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
index 73e2770..73e2770 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/readme.txt
index 269ff89..ab00029 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/readme.txt
@@ -1,13 +1,13 @@
 /**
-  @page WWDG_Reset WWDG Reset example
+  @page USART_HyperTerminal_Interrupt USART Hyperterminal interrupt example
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    WWDG/WWDG_Reset/readme.txt 
+  * @file    USART/HyperTerminal_Interrupt/readme.txt 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
-  * @brief   Description of the WWDG Reset example.
+  * @brief   Description of the USART Hyperterminal interrupt example.
   ******************************************************************************
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -20,75 +20,79 @@
 
 @par Example Description 
 
-This example shows how to update at regular period the WWDG counter and how to
-simulate a software fault generating an MCU WWDG reset on expiry of a programmed 
-time period.
+This example provides a description of how to use the EVAL_COM1 Transmit and Receive 
+interrupts to communicate with the hyperterminal.
+EVAL_COM1 can be USART1 or USART2 depending on the STMicroelectronics EVAL board
+you are using.
 
-The WWDG timeout is set to 65.53ms and the refresh window is set to 80. 
-The WWDG counter is refreshed each 50ms in the main program infinite loop to 
-prevent a WWDG reset.
-LED2 is also toggled each 50ms indicating that the program is running.
+First, the EVAL_COM1 sends the TxBuffer to the hyperterminal and still waiting for
+a string from the hyperterminal that you must enter.
+The string that you have entered is stored in the RxBuffer array. The receive
+buffer have a RxBufferSize bytes as maximum (the reception is stopped when this
+maximum receive value is reached).
 
-An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
-on the rising edge of the signal.
+The EVAL_COM1 is configured as follow:
+    - BaudRate = 9600 baud  
+    - Word Length = 8 Bits (7 data bit + 1 parity bit)
+    - Two Stop Bit
+    - Odd parity
+    - Hardware flow control disabled (RTS and CTS signals)
+    - Receive and transmit enabled
 
-The EXTI Line is used to simulate a software failure: once the EXTI Line event 
-occurs, by pressing the Key push-button, the corresponding interrupt is served.
-In the ISR, a write to invalid address generates a Hardfault exception containing
-an infinite loop and preventing to return to main program (the WWDG counter is 
-not refreshed).
-As a result, when the WWDG counter falls to 63, the WWDG reset occurs.
-If the WWDG reset is generated, after the system resumes from reset, LED1 turns on.
-
-If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed
-in the main program infinite loop, and there is no WWDG reset.
-
-In this example the system clock is set to 24 MHz on Value line devices and to 
-72 MHz on other devices.
-
-
-@par Directory contents
+@note When the parity is enabled, the computed parity is inserted at the MSB
+position of the transmitted data.
  
-  - WWDG/WWDG_Reset/stm32f10x_conf.h     Library Configuration file
-  - WWDG/WWDG_Reset/stm32f10x_it.c       Interrupt handlers
-  - WWDG/WWDG_Reset/stm32f10x_it.h       Header for stm32f10x_it.c
-  - WWDG/WWDG_Reset/main.c               Main program
-  - WWDG/WWDG_Reset/system_stm32f10x.c   STM32F10x system source file
+  
+@par Directory contents 
+
+  - USART/HyperTerminal_Interrupt/stm32f10x_conf.h    Library Configuration file
+  - USART/HyperTerminal_Interrupt/stm32f10x_it.h      Interrupt handlers header file
+  - USART/HyperTerminal_Interrupt/stm32f10x_it.c      Interrupt handlers source file
+  - USART/HyperTerminal_Interrupt/main.c              Main program
+  - USART/HyperTerminal_Interrupt/system_stm32f10x.c  STM32F10x system source file
 
 @par Hardware and Software environment 
 
   - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
+    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
     and Low-Density Value line Devices.
   
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
+  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
     Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density)and STM3210B-EVAL (Medium-Density) 
+    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
     evaluation boards and can be easily tailored to any other supported device 
     and development board.
     To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
+    uncomment the corresponding line in stm32_eval.h file
+
+  - STM32100B-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+     CN10 and PC serial port.  
 
-  - STM32100E-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
-    
-  - STM32100B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-    
   - STM3210C-EVAL Set-up 
-    - Use LD1 and LD2 connected respectively to PD.07 and PD.13 pins
-    - Use the Key push-button connected to pin PB.09 (EXTI Line9).
-    
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6 and PC serial port.
+      @note Make sure that jumpers JP19 and JP18 are open.
+
   - STM3210E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the KEY push button connected to PG.08 pin (EXTI Line8).
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+     CN12 and PC serial port.  
+
+  - STM3210B-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+     CN6 and PC serial port.  
 
-  - STM3210B-EVAL Set-up  
-    - Use LD1 and LD2 leds connected respectively to PC.06 and PC.07 pins
-    - Use the KEY push button connected to PB.09 pin (EXTI Line9).
-     
+  - STM32100E-EVAL Set-up 
+    - Connect a null-modem female/female RS232 cable between the DB9 connector 
+     CN10 and PC serial port. 
+           
+  - Hyperterminal configuration:
+    - Word Length = 7 Bits
+    - Two Stop Bit
+    - Odd parity
+    - BaudRate = 9600 baud
+    - flow control: None 
+      
 @par How to use it ? 
 
 In order to make the program work, you must do the following :
@@ -114,6 +118,6 @@ In order to make the program work, you must do the following :
  - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
    the Flash memory density ranges between 512 and 1024 Kbytes.
  - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
+    
  * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
  */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h
index 5c11070..5c11070 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_conf.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
new file mode 100644
index 0000000..9ab0f19
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.c
@@ -0,0 +1,223 @@
+/**
+  ******************************************************************************
+  * @file    USART/HyperTerminal_Interrupt/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "stm32_eval.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup USART_HyperTerminal_Interrupt
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#ifdef USE_STM3210C_EVAL
+  #define USARTx_IRQHandler   USART2_IRQHandler
+#else
+  #define USARTx_IRQHandler   USART1_IRQHandler
+#endif
+
+#define TxBufferSize   (countof(TxBuffer) - 1)
+#define RxBufferSize   0x20
+
+/* Private macro -------------------------------------------------------------*/
+#define countof(a)   (sizeof(a) / sizeof(*(a)))
+
+/* Private variables ---------------------------------------------------------*/
+uint8_t TxBuffer[] = "\n\rUSART Hyperterminal Interrupts Example: USART-Hyperterminal\
+ communication using Interrupt\n\r";
+uint8_t RxBuffer[RxBufferSize];
+uint8_t NbrOfDataToTransfer = TxBufferSize;
+uint8_t NbrOfDataToRead = RxBufferSize;
+uint8_t TxCounter = 0; 
+uint16_t RxCounter = 0; 
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles USARTx global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void USARTx_IRQHandler(void)
+{
+  if(USART_GetITStatus(EVAL_COM1, USART_IT_RXNE) != RESET)
+  {
+    /* Read one byte from the receive data register */
+    RxBuffer[RxCounter++] = (USART_ReceiveData(EVAL_COM1) & 0x7F);
+
+    if(RxCounter == NbrOfDataToRead)
+    {
+      /* Disable the EVAL_COM1 Receive interrupt */
+      USART_ITConfig(EVAL_COM1, USART_IT_RXNE, DISABLE);
+    }
+  }
+
+  if(USART_GetITStatus(EVAL_COM1, USART_IT_TXE) != RESET)
+  {   
+    /* Write one byte to the transmit data register */
+    USART_SendData(EVAL_COM1, TxBuffer[TxCounter++]);
+
+    if(TxCounter == NbrOfDataToTransfer)
+    {
+      /* Disable the EVAL_COM1 Transmit interrupt */
+      USART_ITConfig(EVAL_COM1, USART_IT_TXE, DISABLE);
+    }
+  }
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h
new file mode 100644
index 0000000..d4c63a5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/stm32f10x_it.h
@@ -0,0 +1,48 @@
+/**
+  ******************************************************************************
+  * @file    USART/HyperTerminal_Interrupt/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USART1_IRQHandler(void);
+void USART2_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c
index 6670253..6670253 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_Interrupt/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
index c2e1295..c2e1295 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
index 91a5c96..91a5c96 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
index b60caac..b60caac 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c
index a422301..a422301 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c
new file mode 100644
index 0000000..6ce1d06
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/main.c
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    USART/IrDA/Receive/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "platform_config.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup USART_IrDA_Receive
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+USART_InitTypeDef USART_InitStructure;
+JOYState_TypeDef ReceivedData = JOY_NONE;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+
+  /* Configure the GPIO ports */
+  GPIO_Configuration();
+
+  /* Initialize Leds mounted on STM3210X-EVAL board */
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+  
+/* USARTy configuration ------------------------------------------------------*/
+  /* USARTy configured as follow:
+        - BaudRate = 115200 baud  
+        - Word Length = 8 Bits
+        - One Stop Bit
+        - No parity
+        - Hardware flow control disabled (RTS and CTS signals)
+        - Receive and transmit enabled
+  */
+  USART_InitStructure.USART_BaudRate = 115200;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No ;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  
+  /* Configure the USARTy */
+  USART_Init(USARTy, &USART_InitStructure);
+  /* Enable the USARTy */
+  USART_Cmd(USARTy, ENABLE);
+
+  /* Set the USARTy prescaler */
+  USART_SetPrescaler(USARTy, 0x1);
+  /* Configure the USARTy IrDA mode */
+  USART_IrDAConfig(USARTy, USART_IrDAMode_Normal);
+
+  /* Enable the USARTy IrDA mode */
+  USART_IrDACmd(USARTy, ENABLE);
+
+  while (1)
+  {
+    /* Wait until a byte is received */
+    while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
+    {
+    }
+    /* Read the received byte */
+    ReceivedData = (JOYState_TypeDef)USART_ReceiveData(USARTy);
+
+    switch(ReceivedData)
+    {
+      case JOY_UP:
+        STM_EVAL_LEDOn(LED1);
+        STM_EVAL_LEDOff(LED2);
+        STM_EVAL_LEDOff(LED3);
+        STM_EVAL_LEDOff(LED4);     
+        break;
+      case JOY_DOWN:
+        STM_EVAL_LEDOn(LED2);
+        STM_EVAL_LEDOff(LED1);
+        STM_EVAL_LEDOff(LED3);
+        STM_EVAL_LEDOff(LED4); 
+        break;
+      case JOY_LEFT:
+        STM_EVAL_LEDOn(LED3);
+        STM_EVAL_LEDOff(LED1);
+        STM_EVAL_LEDOff(LED2);
+        STM_EVAL_LEDOff(LED4);
+        break;
+      case JOY_RIGHT:
+        STM_EVAL_LEDOn(LED4);
+        STM_EVAL_LEDOff(LED1);
+        STM_EVAL_LEDOff(LED2);
+        STM_EVAL_LEDOff(LED3);        
+        break;
+      case JOY_SEL:
+        STM_EVAL_LEDOn(LED1);
+        STM_EVAL_LEDOn(LED2);
+        STM_EVAL_LEDOn(LED3);
+        STM_EVAL_LEDOn(LED4);
+        break;
+      case JOY_NONE:
+        break;
+      default:
+        break;
+    }
+  }
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{   
+  /* Enable GPIO clock */
+  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Enable USARTy clocks */
+  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE);
+}
+
+/**
+  * @brief  Configures the different GPIO ports.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#ifndef USE_STM3210C_EVAL
+  /* Enable the USART3 Pins Partial Software Remapping */
+  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
+#else
+  /* Enable the USART2 Pins Software Remapping */
+  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+#endif  
+
+  /* Configure USARTy Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
+  
+  /* Configure USARTy Rx as input floating */
+  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/platform_config.h
index 68680e2..4b77212 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/platform_config.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    CAN/Networking/platform_config.h 
+  * @file    USART/IrDA/Receive/platform_config.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -30,39 +30,42 @@
 /* Exported constants --------------------------------------------------------*/
 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
    used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM32100E_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL)
+ //#define USE_STM32100B_EVAL
  //#define USE_STM3210B_EVAL
  //#define USE_STM3210E_EVAL
- #define USE_STM3210C_EVAL
+ //#define USE_STM32100E_EVAL
+ #define USE_STM3210C_EVAL 
 #endif
 
 /* Define the STM32F10x hardware depending on the used evaluation board */
-#ifdef USE_STM3210B_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
-  #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
-  #define GPIO_CAN1                   GPIOD  
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
+#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
 
-#elif defined USE_STM3210E_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOB
-  #define GPIO_Remapping_CAN1         GPIO_Remap1_CAN1
-  #define GPIO_CAN1                   GPIOB
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_8
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_9
+  #define USARTy                   USART3
+  #define USARTy_GPIO              GPIOC
+  #define USARTy_CLK               RCC_APB1Periph_USART3
+  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
+  #define USARTy_RxPin             GPIO_Pin_11
+  #define USARTy_TxPin             GPIO_Pin_10
 
-#elif defined USE_STM3210C_EVAL
-  #define RCC_APB2Periph_GPIO_CAN1    RCC_APB2Periph_GPIOD
-  #define GPIO_Remapping_CAN1         GPIO_Remap2_CAN1
-  #define GPIO_CAN1                   GPIOD  
-  #define GPIO_Pin_CAN1_RX            GPIO_Pin_0
-  #define GPIO_Pin_CAN1_TX            GPIO_Pin_1
+#elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
+
+  #define USARTy                   USART3
+  #define USARTy_GPIO              GPIOC
+  #define USARTy_CLK               RCC_APB1Periph_USART3
+  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOC
+  #define USARTy_RxPin             GPIO_Pin_11
+  #define USARTy_TxPin             GPIO_Pin_10
   
-  #define RCC_APB2Periph_GPIO_CAN2    RCC_APB2Periph_GPIOB
-  #define GPIO_Remapping_CAN2         GPIO_Remap_CAN2
-  #define GPIO_CAN2                   GPIOB  
-  #define GPIO_Pin_CAN2_RX            GPIO_Pin_5
-  #define GPIO_Pin_CAN2_TX            GPIO_Pin_6
+#elif defined USE_STM3210C_EVAL
+
+  #define USARTy                   USART2
+  #define USARTy_GPIO              GPIOD
+  #define USARTy_CLK               RCC_APB1Periph_USART2
+  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
+  #define USARTy_RxPin             GPIO_Pin_6
+  #define USARTy_TxPin             GPIO_Pin_5
+
 #endif /* USE_STM3210B_EVAL */
 
 /* Exported macro ------------------------------------------------------------*/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt
index 9b9494b..9b9494b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h
index 6131b68..6131b68 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c
index 15ed3e7..15ed3e7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h
index 68af1d3..68af1d3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
index b4158f7..b4158f7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h
index cdc0844..cdc0844 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt
index c9ea1a8..c9ea1a8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c
index e7d47c8..e7d47c8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/system_stm32f10x.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c
new file mode 100644
index 0000000..7983890
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/main.c
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    USART/MultiProcessor/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "platform_config.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup USART_MultiProcessor
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+USART_InitTypeDef USART_InitStructure;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void GPIO_Configuration(void);
+void Delay(__IO uint32_t nCount);
+
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+       
+  /* System Clocks Configuration */
+  RCC_Configuration();
+       
+  /* Configure the GPIO ports */
+  GPIO_Configuration();
+
+  /* Initialize Leds, Wakeup and Key Buttons mounted on STM3210X-EVAL board */ 
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+  STM_EVAL_PBInit(BUTTON_WAKEUP, BUTTON_MODE_EXTI);          
+  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_EXTI);  
+
+/* USARTy and USARTz configuration -------------------------------------------*/
+  /* USARTy and USARTz configured as follow:
+        - BaudRate = 9600 baud  
+        - Word Length = 9 Bits
+        - One Stop Bit
+        - No parity
+        - Hardware flow control disabled (RTS and CTS signals)
+        - Receive and transmit enabled
+  */
+  USART_InitStructure.USART_BaudRate = 9600;
+  USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  
+  /* Configure USARTy */
+  USART_Init(USARTy, &USART_InitStructure);
+  /* Configure USARTz */
+  USART_Init(USARTz, &USART_InitStructure);
+  
+  /* Enable the USARTy */
+  USART_Cmd(USARTy, ENABLE);
+  /* Enable the USARTz */
+  USART_Cmd(USARTz, ENABLE);
+
+  /* Set the USARTy Address */
+  USART_SetAddress(USARTy, 0x1);
+  /* Set the USARTz Address */
+  USART_SetAddress(USARTz, 0x2);
+
+  /* Select the USARTz WakeUp Method */
+  USART_WakeUpConfig(USARTz, USART_WakeUp_AddressMark);
+  
+  while (1)
+  {
+    /* Send one byte from USARTy to USARTz */
+    USART_SendData(USARTy, 0x33);
+    
+    /* Wait while USART1 TXE = 0 */
+    while(USART_GetFlagStatus(USARTz, USART_FLAG_TXE) == RESET)
+    {
+    }
+    
+    if(USART_GetFlagStatus(USARTz, USART_FLAG_RXNE) != RESET)
+    {
+      if(USART_ReceiveData(USARTz) == 0x33)
+      {
+        STM_EVAL_LEDToggle(LED1);
+        Delay(0x5FFFF);
+        STM_EVAL_LEDToggle(LED2);
+        Delay(0x5FFFF);
+        STM_EVAL_LEDToggle(LED3);
+        Delay(0x5FFFF);
+        STM_EVAL_LEDToggle(LED4);
+        Delay(0x5FFFF);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Configures the different system clocks.
+  * @param  None
+  * @retval None
+  */
+void RCC_Configuration(void)
+{
+  /* Enable GPIO clock */
+  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+
+#ifndef USE_STM3210C_EVAL
+  /* Enable USARTy Clock */
+  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
+#else
+  /* Enable USARTy Clock */
+  RCC_APB1PeriphClockCmd(USARTy_CLK, ENABLE); 
+#endif
+  /* Enable USARTz Clock */
+  RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE);  
+}
+
+/**
+  * @brief  Configures the different GPIO ports.
+  * @param  None
+  * @retval None
+  */
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#ifdef USE_STM3210C_EVAL
+  /* Enable the USART3 Pins Software Remapping */
+  GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
+  
+  /* Enable the USART2 Pins Software Remapping */
+  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);  
+#elif defined(USE_STM3210B_EVAL) || defined(USE_STM32100B_EVAL)
+  /* Enable the USART2 Pins Software Remapping */
+  GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+#endif
+
+  /* Configure USARTy Rx as input floating */
+  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
+  
+  /* Configure USARTz Rx as input floating */
+  GPIO_InitStructure.GPIO_Pin = USARTz_RxPin;
+  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
+  
+  /* Configure USARTy Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
+
+  /* Configure USARTz Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = USARTz_TxPin;
+  GPIO_Init(USARTz_GPIO, &GPIO_InitStructure);  
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+void Delay(__IO uint32_t nCount)
+{
+  /* Decrement nCount value */
+  for(; nCount != 0; nCount--);
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/platform_config.h
index 33a58b9..2835317 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/platform_config.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    USART/HalfDuplex/platform_config.h 
+  * @file    USART/MultiProcessor/platform_config.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -24,6 +24,7 @@
 #define __PLATFORM_CONFIG_H
 
 /* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -38,18 +39,20 @@
 #endif
 
 /* Define the STM32F10x hardware depending on the used evaluation board */
-#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL)
+#if defined(USE_STM3210B_EVAL) || defined (USE_STM32100B_EVAL) 
 
   #define USARTy                   USART1
   #define USARTy_GPIO              GPIOA
   #define USARTy_CLK               RCC_APB2Periph_USART1
   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
+  #define USARTy_RxPin             GPIO_Pin_10
   #define USARTy_TxPin             GPIO_Pin_9
 
   #define USARTz                   USART2
   #define USARTz_GPIO              GPIOD
   #define USARTz_CLK               RCC_APB1Periph_USART2
   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
+  #define USARTz_RxPin             GPIO_Pin_6
   #define USARTz_TxPin             GPIO_Pin_5
 
 #elif defined USE_STM3210E_EVAL || defined (USE_STM32100E_EVAL)
@@ -58,12 +61,14 @@
   #define USARTy_GPIO              GPIOA
   #define USARTy_CLK               RCC_APB2Periph_USART1
   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
+  #define USARTy_RxPin             GPIO_Pin_10
   #define USARTy_TxPin             GPIO_Pin_9
 
   #define USARTz                   USART2
   #define USARTz_GPIO              GPIOA
   #define USARTz_CLK               RCC_APB1Periph_USART2
   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
+  #define USARTz_RxPin             GPIO_Pin_3
   #define USARTz_TxPin             GPIO_Pin_2
 
 #elif defined USE_STM3210C_EVAL
@@ -72,17 +77,18 @@
   #define USARTy_GPIO              GPIOD
   #define USARTy_CLK               RCC_APB1Periph_USART2
   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
+  #define USARTy_RxPin             GPIO_Pin_6
   #define USARTy_TxPin             GPIO_Pin_5
 
   #define USARTz                   USART3
   #define USARTz_GPIO              GPIOC
   #define USARTz_CLK               RCC_APB1Periph_USART3
   #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
+  #define USARTz_RxPin             GPIO_Pin_11
   #define USARTz_TxPin             GPIO_Pin_10
 
 #endif /* USE_STM3210B_EVAL */
 
-
 /* Exported macro ------------------------------------------------------------*/
 /* Exported functions ------------------------------------------------------- */
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h
index e6f5a21..e6f5a21 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c
index 6358763..2cbd686 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/PWR/STANDBY/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    PWR/STANDBY/stm32f10x_it.c 
+  * @file    USART/MultiProcessor/stm32f10x_it.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -23,13 +23,13 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
-#include "stm32_eval.h"
+#include "platform_config.h"
 
 /** @addtogroup STM32F10x_StdPeriph_Examples
   * @{
   */
-
-/** @addtogroup PWR_STANDBY
+  
+/** @addtogroup USART_MultiProcessor
   * @{
   */ 
 
@@ -139,8 +139,6 @@ void PendSV_Handler(void)
   */
 void SysTick_Handler(void)
 {
-  /* Toggle LED1 */
-  STM_EVAL_LEDToggle(LED1);
 }
 
 /******************************************************************************/
@@ -148,6 +146,25 @@ void SysTick_Handler(void)
 /******************************************************************************/
 
 /**
+  * @brief  This function handles External interrupt Line 0 request.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  /* Send the address mark (0x102) to wakeup USARTz */
+  USART_SendData(USARTy, 0x102);
+
+  /* Wait while USARTy TXE = 0 */
+  while(USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET)
+  {
+  }
+
+  /* Clear EXTI Line 0 Pending Bit */
+  EXTI_ClearITPendingBit(EXTI_Line0);
+}
+
+/**
   * @brief  This function handles External lines 9 to 5 interrupt request.
   * @param  None
   * @retval None
@@ -155,24 +172,15 @@ void SysTick_Handler(void)
 void EXTI9_5_IRQHandler(void)
 {
   if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
-  { 
-    /* Clear the Key Button EXTI line pending bit */  
-    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
-
-    /* Turn on LED1 */
-    STM_EVAL_LEDOn(LED1);
-
-    /* Wait till RTC Second event occurs */
-    RTC_ClearFlag(RTC_FLAG_SEC);
-    while(RTC_GetFlagStatus(RTC_FLAG_SEC) == RESET);
+  {
+    /* Flush DR register and clear the USARTz RXNE flag */
+    USART_ReceiveData(USARTz);
 
-    /* Set the RTC Alarm after 3s */
-    RTC_SetAlarm(RTC_GetCounter()+ 3);
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
+    /* Enable the USARTz mute mode*/
+    USART_ReceiverWakeUpCmd(USARTz, ENABLE);
 
-    /* Request to enter STANDBY mode (Wake Up flag is cleared in PWR_EnterSTANDBYMode function) */
-    PWR_EnterSTANDBYMode();
+    /* Clear Key Button EXTI Line Pending Bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE); 
   }
 }
 
@@ -194,10 +202,10 @@ void EXTI9_5_IRQHandler(void)
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h
index b0bad82..5f3b882 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/stm32f10x_it.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    USART/Smartcard/stm32f10x_it.h 
+  * @file    USART/MultiProcessor/stm32f10x_it.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -40,9 +40,8 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+void EXTI0_IRQHandler(void);
 void EXTI9_5_IRQHandler(void);
-void USART3_IRQHandler(void);
-void EXTI15_10_IRQHandler(void);
 
 #endif /* __STM32F10x_IT_H */
 
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c
new file mode 100644
index 0000000..63d39d3
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/system_stm32f10x.c
@@ -0,0 +1,1094 @@
+/**
+  ******************************************************************************
+  * @file    USART/MultiProcessor/system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *          and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c
index cbd7c97..cbd7c97 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h
index 6537dfe..6537dfe 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h
index ec079bb..ec079bb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c
index d5f4697..d5f4697 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/main.c
index aa882ef..e253b50 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/main.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    Lib_DEBUG/RunTime_Check/main.c 
+  * @file    USART/Printf/main.c 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -21,7 +21,6 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"
-#include "stm32f10x_ip_dbg.h"
 #include "stm32_eval.h"
 #include <stdio.h>
 
@@ -29,7 +28,7 @@
   * @{
   */
 
-/** @addtogroup Lib_DEBUG_RunTime_Check
+/** @addtogroup USART_Printf
   * @{
   */ 
 
@@ -37,9 +36,10 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
- USART_InitTypeDef USART_InitStructure;
+USART_InitTypeDef USART_InitStructure;
 
 /* Private function prototypes -----------------------------------------------*/
+
 #ifdef __GNUC__
   /* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
      set to 'Yes') calls __io_putchar() */
@@ -47,11 +47,11 @@
 #else
   #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
 #endif /* __GNUC__ */
-
+  
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  Main program.
+  * @brief  Main program
   * @param  None
   * @retval None
   */
@@ -64,8 +64,6 @@ int main(void)
        system_stm32f10x.c file
      */     
        
-  GPIO_InitTypeDef GPIOA_InitStructure;
-
   /* USARTx configured as follow:
         - BaudRate = 115200 baud  
         - Word Length = 8 Bits
@@ -83,27 +81,30 @@ int main(void)
 
   STM_EVAL_COMInit(COM1, &USART_InitStructure);
 
-  /* Initialize all peripherals pointers */
-  debug();
-  
-  printf("\r\n STM32F10x Firmware Library compiled with FULL ASSERT function... \n\r");
-  printf("...Run-time checking enabled  \n\r");
+  /* Output a message on Hyperterminal using printf function */
+  printf("\n\rUSART Printf Example: retarget the C library printf function to the USART\n\r");
 
-  /* Simulate wrong parameter passed to library function ---------------------*/
-  /* To enable SPI1 clock, RCC_APB2PeriphClockCmd function must be used and
-     not RCC_APB1PeriphClockCmd */
-  RCC_APB1PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
-  
-  /* Some member of GPIOA_InitStructure structure are not initialized */
-  GPIOA_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIOA_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  /* GPIOA_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; */
-  GPIO_Init(GPIOA, &GPIOA_InitStructure);
-  
   while (1)
   {
   }
+}
 
+/**
+  * @brief  Retargets the C library printf function to the USART.
+  * @param  None
+  * @retval None
+  */
+PUTCHAR_PROTOTYPE
+{
+  /* Place your implementation of fputc here */
+  /* e.g. write a character to the USART */
+  USART_SendData(EVAL_COM1, (uint8_t) ch);
+
+  /* Loop until the end of transmission */
+  while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
+  {}
+
+  return ch;
 }
 
 #ifdef  USE_FULL_ASSERT
@@ -117,45 +118,23 @@ int main(void)
   */
 void assert_failed(uint8_t* file, uint32_t line)
 { 
-  /* User can add his own implementation to report the file name and line number */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
 
-  printf("\n\r Wrong parameter value detected on\r\n");
-  printf("       file  %s\r\n", file);
-  printf("       line  %d\r\n", line);
-    
   /* Infinite loop */
-  /* while (1)
+  while (1)
   {
-  } */
+  }
 }
 
 #endif
 
 /**
-  * @brief  Retargets the C library printf function to the USART.
-  * @param  None
-  * @retval None
-  */
-PUTCHAR_PROTOTYPE
-{
-  /* Place your implementation of fputc here */
-  /* e.g. write a character to the USART */
-  USART_SendData(EVAL_COM1, (uint8_t) ch);
-
-  /* Loop until the end of transmission */
-  while(USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
-  {
-  }
-
-  return ch;
-}
-
-/**
   * @}
-  */
+  */ 
 
 /**
   * @}
-  */
+  */ 
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c
index 98947eb..98947eb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h
index b87cab2..b87cab2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c
index 7d87bc2..7d87bc2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
index dc1832a..dc1832a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h
index e90404d..e90404d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/platform_config.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h
index a1f8a0d..938cc84 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Backup_Data/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_conf.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    BKP/Backup_Data/stm32f10x_conf.h 
+  * @file    USART/Smartcard/stm32f10x_conf.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c
new file mode 100644
index 0000000..f69365d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/stm32f10x_it.c
@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    USART/Smartcard/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "platform_config.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Examples
+  * @{
+  */
+
+/** @addtogroup USART_Smartcard
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern __IO uint32_t CardInserted; 
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSV_Handler exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32F10x Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles External lines 9 to 5 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI9_5_IRQHandler(void)
+{
+  /* Select Smart Card CMDVCC */  
+  GPIO_ResetBits(GPIO_CMDVCC, SC_CMDVCC);
+
+  /* Set RSTIN LOW */  
+  GPIO_ResetBits(GPIO_RESET, SC_RESET);
+
+  /* Set RSTIN HIGH */  
+  GPIO_SetBits(GPIO_RESET, SC_RESET);
+    
+  /* Clear SC EXTIT Line Pending Bit */
+  EXTI_ClearITPendingBit(SC_EXTI);
+
+  /* Smart card detected */
+  CardInserted = 1;
+}
+
+/**
+  * @brief  This function handles SC_USART global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void SC_USART_IRQHandler(void)
+{
+  /* If the SC_USART detects a parity error */
+  if(USART_GetITStatus(SC_USART, USART_IT_PE) != RESET)
+  {
+    /* Enable SC_USART RXNE Interrupt (until receiving the corrupted byte) */
+    USART_ITConfig(SC_USART, USART_IT_RXNE, ENABLE);
+    /* Flush the SC_USART DR register */
+    USART_ReceiveData(SC_USART);
+  }
+  
+  if(USART_GetITStatus(SC_USART, USART_IT_RXNE) != RESET)
+  {
+    /* Disable SC_USART RXNE Interrupt */
+    USART_ITConfig(SC_USART, USART_IT_RXNE, DISABLE);
+    USART_ReceiveData(SC_USART);
+  }
+}
+
+/**
+  * @brief  This function handles External lines 15 to 10 interrupt request.
+  * @param  None
+  * @retval None
+  */
+void EXTI15_10_IRQHandler(void)
+{
+  /* Select Smart Card CMDVCC */  
+  GPIO_ResetBits(GPIO_CMDVCC, SC_CMDVCC);
+
+  /* Set RSTIN LOW */  
+  GPIO_ResetBits(GPIO_RESET, SC_RESET);
+
+  /* Set RSTIN HIGH */  
+  GPIO_SetBits(GPIO_RESET, SC_RESET);
+    
+  /* Clear SC EXTIT Line Pending Bit */
+  EXTI_ClearITPendingBit(SC_EXTI);
+
+  /* Smart card detected */
+  CardInserted = 1;
+}
+
+/******************************************************************************/
+/*                 STM32F10x Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f10x_xx.s).                                            */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c
index 0a043eb..0a043eb 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Smartcard/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/platform_config.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/platform_config.h
index 9474a3f..9317b58 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/DMA_Interrupt/platform_config.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/platform_config.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    USART/DMA_Interrupt/platform_config.h 
+  * @file    USART/Synchronous/platform_config.h 
   * @author  MCD Application Team
   * @version V3.5.0
   * @date    08-April-2011
@@ -29,12 +29,11 @@
 /* Exported constants --------------------------------------------------------*/
 /* Uncomment the line corresponding to the STMicroelectronics evaluation board
    used to run the example */
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL) 
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32100E_EVAL)
  //#define USE_STM32100B_EVAL
  //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM32100E_EVAL
- #define USE_STM3210C_EVAL 
+ //#define USE_STM32100E_EVAL 
+ #define USE_STM3210E_EVAL 
 #endif
 
 /* Define the STM32F10x hardware depending on the used evaluation board */
@@ -46,22 +45,17 @@
   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
   #define USARTy_RxPin             GPIO_Pin_10
   #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_DR_Base           0x40004404
-  #define USARTz_IRQn              USART2_IRQn
-
-#elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
+  #define USARTy_ClkPin            GPIO_Pin_8
+  
+  #define SPIy                     SPI1
+  #define SPIy_GPIO                GPIOA
+  #define SPIy_CLK                 RCC_APB2Periph_SPI1
+  #define SPIy_GPIO_CLK            RCC_APB2Periph_GPIOA
+  #define SPIy_SCKPin              GPIO_Pin_5
+  #define SPIy_MISOPin             GPIO_Pin_6
+  #define SPIy_MOSIPin             GPIO_Pin_7
+
+#elif defined USE_STM3210E_EVAL || defined USE_STM32100E_EVAL
 
   #define USARTy                   USART1
   #define USARTy_GPIO              GPIOA
@@ -69,43 +63,15 @@
   #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
   #define USARTy_RxPin             GPIO_Pin_10
   #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel4
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC4
-  #define USARTy_DR_Base           0x40013804
-
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTz_DR_Base           0x40004404
-  #define USARTz_IRQn              USART2_IRQn
-
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-  #define USARTy_Tx_DMA_Channel    DMA1_Channel7
-  #define USARTy_Tx_DMA_FLAG       DMA1_FLAG_TC7
-  #define USARTy_DR_Base           0x40004404
-
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-  #define USARTz_Tx_DMA_Channel    DMA1_Channel2
-  #define USARTz_Tx_DMA_FLAG       DMA1_FLAG_TC2
-  #define USARTz_DR_Base           0x40004804
-  #define USARTz_IRQn              USART3_IRQn
+  #define USARTy_ClkPin            GPIO_Pin_8
+  
+  #define SPIy                     SPI1
+  #define SPIy_GPIO                GPIOA
+  #define SPIy_CLK                 RCC_APB2Periph_SPI1
+  #define SPIy_GPIO_CLK            RCC_APB2Periph_GPIOA
+  #define SPIy_SCKPin              GPIO_Pin_5
+  #define SPIy_MISOPin             GPIO_Pin_6
+  #define SPIy_MOSIPin             GPIO_Pin_7
 
 #endif /* USE_STM3210B_EVAL */
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c
index 619e4e9..619e4e9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h
index fd123d0..fd123d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c
index ba73f42..ba73f42 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
index e95ba1f..e95ba1f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/main.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h
index 3ec9eee..3ec9eee 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_conf.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
index 55a2615..55a2615 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
index 8fc68df..8fc68df 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/stm32f10x_it.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c
index 8607cd2..8607cd2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/WWDG/WWDG_Reset/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd
index 8a9044b..8a9044b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewd
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp
index a3650ae..a3650ae 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.ewp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww
index e0fd14b..e0fd14b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/Project.eww
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash_extsram.icf b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash.icf
index 5e0a239..6721a0d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash_extsram.icf
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_flash.icf
@@ -4,11 +4,10 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x08000000;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__       = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__         = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__       = 0x68000000;
-define symbol __ICFEDIT_region_RAM_end__         = 0x680FFFFF;
-
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__   = 0x400;
 define symbol __ICFEDIT_size_heap__     = 0x200;
@@ -16,8 +15,8 @@ define symbol __ICFEDIT_size_heap__     = 0x200;
 
 
 define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__]; /* EXTSRAM_region */
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
 
 define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
 define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
@@ -28,6 +27,5 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   {readwrite, block CSTACK, block HEAP }; /* EXTSRAM_region */
-
-                        
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf
index 6aeaf65..6aeaf65 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/stm32f10x_ram.icf
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp
index b85d35a..b85d35a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Project.htp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/StartupScript.scr
index e3dbe23..e3dbe23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/StartupScript.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/StartupScript.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/arm_arch.lsl
index 3e6d303..3e6d303 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/arm_arch.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk
index 038235e..038235e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/link.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_appl.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr
index 3e9c066..3e9c066 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/reset_go_main.scr
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/stm32f10x_MD_VL.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/stm32f10x_MD_VL.lsl
new file mode 100644
index 0000000..cabbd2d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/Settings/stm32f10x_MD_VL.lsl
@@ -0,0 +1,146 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f10x_MD_VL.lsl
+//
+//  Version     :  @(#)stm32f10x_MD_VL.lsl      1.2  19/02/2010
+//
+//  Description :  LSL file for the STMicroelectronics STM32F100VB, CMSIS version
+//
+//  COPYRIGHT 2010 STMicroelectronics   
+//
+//  NOTE:
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 72
+
+
+#ifndef __STACK
+#  define __STACK                       1k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        1k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    map ( size = 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
+                        vector ( id = 1, fill = "_START" );
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1                        
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break and TIM15
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );       // TIM1 Update and TIM16
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation and TIM17
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // HDMI-CEC                   
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 and DAC underrun
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                }
+}
+# endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp
index eedf13a..eedf13a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Project.htp
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr
index e3dbe23..e3dbe23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/StartupScript.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl
index 3e6d303..3e6d303 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/arm_arch.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk
index a253595..a253595 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/reset_appl.scr
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/reset_go_main.scr
new file mode 100644
index 0000000..db5f753
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/reset_go_main.scr
@@ -0,0 +1,12 @@
+// Hitex/Lue/11.02.2008 
+// Executable Script file for HiTOP Debugger
+// Reset application & Go main 
+
+//Reset    
+RESET TARGET
+
+
+// execute program till main
+Go UNTIL main
+wait
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl
index 9038512..9038512 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/readme.txt
index 54aaec8..79c70bc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100B-EVAL/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/readme.txt
@@ -1,5 +1,5 @@
 /**
-  @page HiTOP5_STM32100B HiTOP Project Template for STM32F10x Medium-density Value line devices
+  @page HiTOP5_STM32100E HiTOP Project Template for STM32F10x High-density Value line devices
   
   @verbatim
   ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
@@ -35,8 +35,10 @@
                      in internal FLASH and data (readwrite, Stack and Heap)
                      in internal SRAM.
 
-     - link.lnk: This file is the HiTOP linker it invokes the stm32f10x_MD_VL.lsl.
-                                   
+     - link.lnk: This file is the HiTOP linker it invokes the stm32f10x_hd_vl.lsl
+
+     - linkextsram.lnk: This file is the HiTOP linker it invokes the stm32f10x_hd_vl_extsram.lsl
+                                        
      - reset_appl.scr: This file is a HiTOP script it performs a target reset.
      
      - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
@@ -45,12 +47,21 @@
      - StartupScript.scr: This file is a HiTOP script and it performs a target 
                           reset before loading The executable image.
 
-     - stm32f10x_MD_VL.lsl: This file is used to place program code (readonly)
+     - stm32f10x_hd_vl.lsl: This file is used to place program code (readonly)
                             in internal FLASH and data (readwrite, Stack and Heap)
                             in internal SRAM.
                             It contains also the vector table of the STM32 
-                            Medium-density Value line devices.
-                            You can customize this file to your need.                                                              
+                            High-density Value line devices.
+                            You can customize this file to your need.
+
+     - stm32f10x_hd_vl_extsram.lsl: This file  used to place program code (readonly) in 
+                                    internal FLASH and data (readwrite, Stack and Heap)
+                                    in external SRAM.
+                                    It contains also the vector table of the STM32 High-density
+                                    Value line devices. 
+                                    You can customize this file to your need. 
+                                    This file is used only with STM32 High-density 
+                                    Value line devices.                                                                         
 
 @par How to use it ?
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
index 2c11b4c..2c11b4c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/setstack.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl
index 0eab7a9..0eab7a9 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/STM32F10x_md.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr
index e3dbe23..e3dbe23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/StartupScript.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl
index 3e6d303..3e6d303 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/arm_arch.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/arm_arch.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/link.lnk
index 6451b8c..f95945a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/link.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/link.lnk
@@ -1,4 +1,4 @@
--d"./settings/STM32F10x_XL.lsl"
+-d"./settings/STM32F10x_md.lsl"
 --optimize=0
 --map-file-format=2
 $(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_appl.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr
index 3e9c066..3e9c066 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Settings/reset_go_main.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Project.htp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Project.htp
index 28de448..bf71088 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Project.htp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Project.htp
@@ -1,11 +1,14 @@
 <?xml version="1.0" encoding="UTF-8"?>
 
+<!-- ======================================================================= -->
+<!-- ** DON'T EDIT THIS FILE! IT WILL BE AUTOMATICALY GENERATED BY HITOP! ** -->
+<!-- ======================================================================= -->
 
 <HiTOPProject>
 	<Windows>
 		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
 		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103ZG.xsfr"/>
+			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F107VC.xsfr"/>
 			<WindowState State="Normal"/>
 			<Rectangle State="Normal">
 				<Size cx="497" cy="278"/>
@@ -38,11 +41,12 @@
 				<Position x="0" y="0"></Position>
 			</Rectangle>
 			<Rectangle State="Maximized">
-				<Size cx="844" cy="623"></Size>
+				<Size cx="844" cy="579"></Size>
 				<Position x="-4" y="-23"></Position>
 			</Rectangle>
-			<Tabs Count="1" Active="0">
-				<Tab Pos="0" PosX="0" PosY="0" Module="readme.txt" TopLine="1" FilePath="$(PROJECTDIR)\readme.txt" Application="Project"/>
+			<Tabs Count="2" Active="0">
+				<Tab Pos="0" PosX="24" PosY="9" Module="readme.txt" TopLine="1" FilePath="$(PROJECTDIR)\readme.txt" Application="Project"/>
+				<Tab Pos="1" PosX="0" PosY="36" Module="cstart_thumb2" TopLine="27" FilePath="$(PROJECTDIR)\cstart_thumb2.asm" Application="Project"/>
 			</Tabs>
 		</Window>
 		<Window Id="Watch">
@@ -196,9 +200,6 @@
 				<Folder Id="Doc" State="Not_Expanded">
 					<File Id=".\readme.txt"/>
 				</Folder>
-				<Folder Id="HiTOP" State="Not_Expanded">
-					<File Id=".\cstart_thumb2.asm"/>
-				</Folder>
 				<Folder Id="StdPeriph_Driver" State="Not_Expanded">
 					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c"/>
 					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c"/>
@@ -225,19 +226,18 @@
 					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c"/>
 				</Folder>
 				<Folder Id="STM32_EVAL" State="Not_Expanded">
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nand.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nor.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_sram.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_lcd.c"/>
+					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c"/>
+					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.c"/>
 					<File Id="..\..\..\..\Utilities\STM32_EVAL\stm32_eval.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_sdio_sd.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c"/>
+					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c"/>
 				</Folder>
 				<Folder Id="User" State="Not_Expanded">
 					<File Id="..\..\main.c"/>
 					<File Id="..\..\stm32f10x_it.c"/>
 				</Folder>
+				<Folder Id="HiTOP" State="Not_Expanded">
+					<File Id=".\cstart_thumb2.asm"/>
+				</Folder>
 				<Folder Id="Source Files" State="Not_Expanded" RelativePath=""/>
 			</ApplFolder>
 		</Window>
@@ -245,9 +245,9 @@
 	<Version>V5.20</Version>
 	<DebugDevice>
 		<TargetProcessor Id="PARM"/>
-		<Derivative Id="STM32F103ZG" File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\.\..\Arm\Default.drv" Vendor="ST Microelectronics">
+		<Derivative Id="STM32F107VC" File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\.\..\Arm\Default.drv" Vendor="ST Microelectronics">
 			<InternalFlash Count="1">
-				<Device Id="STM32F103xG" Index="0" Manufacturer="ST"></Device>
+				<Device Id="STM32F107VC" Index="0" Manufacturer="ST"></Device>
 			</InternalFlash>
 		</Derivative>
 		<Communication>
@@ -257,8 +257,8 @@
 			<BaudRate Value="0"/>
 		</Communication>
 		<SystemDir Path="C:\Program Files\Hitex\HiTOP54-CTX\Tantino-Cortex"/>TANTINO_CORTEX_M3
-		<RecentDerivative SWJDP="1" Vendor="ST Microelectronics" ProcType="30" Endianess="0" Derivative="STM32F103ZG"/>
-		<ARMConfiguration Id="STM32F103ZG" SWJDP="1" Vendor="ST Microelectronics" EMB_ICE="0" Endianes="0" ProcType="30" ETM_EXIST="0" MCUFamily="STM32" RTCK_USED="0" Exceptions="STM32xxx_C_D_E" TRACE_AVAIL="1" DeviceToTest="2" ExtMemoryItf="YES" OnChipRAMAdr="0x20000000" OnChipRAMSize="0x18000" EndianessFixed="1" OnChipFlashAdr="0x8000000" OnChipFlashSize="0x100000" IR_CountBitsOfTD="4" CountDevicesInChain="2" IR_CountBitsBeforeTD="5" IR_CountBitsBehindTD="0"/>
+		<RecentDerivative SWJDP="2" Vendor="ST Microelectronics" ProcType="30" Endianess="0" Derivative="STM32F107VC"/>
+		<ARMConfiguration Id="STM32F107VC" SWJDP="2" Vendor="ST Microelectronics" EMB_ICE="0" Endianes="0" ProcType="30" ETM_EXIST="0" MCUFamily="STM32" RTCK_USED="0" Exceptions="STM32xxx_Conn" TRACE_AVAIL="1" DeviceToTest="2" ExtMemoryItf="NO" OnChipRAMAdr="0x20000000" OnChipRAMSize="0x10000" EndianessFixed="1" OnChipFlashAdr="0x8000000" OnChipFlashSize="0x40000" IR_CountBitsOfTD="4" CountDevicesInChain="2" IR_CountBitsBeforeTD="5" IR_CountBitsBehindTD="0"/>
 	</DebugDevice>
 	<StartupScript File=".\Settings\StartupScript.scr" Execute="1" ProjRelative="1"/>
 	<EditorOptions Version="1">
@@ -290,26 +290,22 @@
 			<EmulatorSetting Id="UPDWRCTI" Value="1000" Element=""/>
 			<EmulatorSetting Id="SWVFeat" Value="0" Element="OFF"/>
 			<EmulatorSetting Id="SysClock" Value="0" Element=""/>
+			<EmulatorSetting Id="TSPRESC" Value="1" Element="064"/>
 			<EmulatorSetting Id="IMASK_1" Value="-1" Element=""/>
 			<EmulatorSetting Id="IMASK_2" Value="-1" Element=""/>
 			<EmulatorSetting Id="IMASK_3" Value="-1" Element=""/>
-			<EmulatorSetting Id="IMASK_4" Value="-1" Element=""/>
-			<EmulatorSetting Id="IMASK_5" Value="-1" Element=""/>
-			<EmulatorSetting Id="IMASK_6" Value="-1" Element=""/>
-			<EmulatorSetting Id="IMASK_7" Value="-1" Element=""/>
-			<EmulatorSetting Id="IMASK_8" Value="-1" Element=""/>
 			<EmulatorSetting Id="EXCSEL" Value="0" Element="IENTER"/>
-			<EmulatorSetting Id="TSPRESC" Value="1" Element="064"/>
 			<EmulatorSetting Id="PCAFTERD" Value="0" Element="no"/>
+			<EmulatorSetting Id="IMASK_4" Value="-1" Element=""/>
 			<EmulatorSetting Id="SWOFrequ" Value="1" Element="2MHZ"/>
 		</EmulatorSettings>
 		<GeneralSettings>
-			<GeneralSetting Id="TraceRecordingMode" Value="0" Element=""/>
-			<GeneralSetting Id="TraceRegionMode" Value="0" Element=""/>
-			<GeneralSetting Id="TraceInitialState" Value="0" Element=""/>
-			<GeneralSetting Id="TraceBufferOnStart" Value="0" Element=""/>
-			<GeneralSetting Id="TraceOnOverflow" Value="0" Element=""/>
-			<GeneralSetting Id="TraceDisplayMode" Value="0" Element=""/>
+			<GeneralSetting Id="TraceRecordingMode" Value="0" Element="Cycles"/>
+			<GeneralSetting Id="TraceRegionMode" Value="0" Element="Disable"/>
+			<GeneralSetting Id="TraceInitialState" Value="0" Element="On"/>
+			<GeneralSetting Id="TraceBufferOnStart" Value="0" Element="Refill"/>
+			<GeneralSetting Id="TraceOnOverflow" Value="0" Element="Overwrite"/>
+			<GeneralSetting Id="TraceDisplayMode" Value="0" Element="Backward"/>
 			<GeneralSetting Id="TraceBusState" Value="0" Element=""/>
 			<GeneralSetting Id="TriggerBusState" Value="0" Element=""/>
 			<GeneralSetting Id="TriggerDataType" Value="0" Element=""/>
@@ -416,63 +412,6 @@
 					</Rectangle>
 				</Window>
 			</Windows>
-			<CommandBars>
-				<CommandBars>
-					<CommandBar BarID="10066" Class="CScriptToolBar" Flags="63" Style="4194304" Title="Execute Script" MRUWidth="32767">
-						<Controls OriginalControls="1">
-							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."/>
-							<Control Id="40398" Class="CXTPControlButton"/>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter=".\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText=".\\Settings\\reset_appl.scr"/>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter=".\\Settings\\reset_go_main.scr" TooltipText=".\\Settings\\reset_go_main.scr"/>
-							<Control Id="10053" Class="CControlScriptButton"/>
-							<Control Id="10054" Class="CControlScriptButton"/>
-							<Control Id="10055" Class="CControlScriptButton"/>
-							<Control Id="10056" Class="CControlScriptButton"/>
-							<Control Id="10057" Class="CControlScriptButton"/>
-							<Control Id="10058" Class="CControlScriptButton"/>
-							<Control Id="10059" Class="CControlScriptButton"/>
-							<Control Id="10060" Class="CControlScriptButton"/>
-							<OriginalControls>
-								<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777217" DescriptionText="Execute a HiSCRIPT script file."/>
-								<Control Id="40398" Class="CXTPControlButton"/>
-								<Control Id="10051" Class="CControlScriptButton" BeginGroup="1"/>
-								<Control Id="10052" Class="CControlScriptButton"/>
-								<Control Id="10053" Class="CControlScriptButton"/>
-								<Control Id="10054" Class="CControlScriptButton"/>
-								<Control Id="10055" Class="CControlScriptButton"/>
-								<Control Id="10056" Class="CControlScriptButton"/>
-								<Control Id="10057" Class="CControlScriptButton"/>
-								<Control Id="10058" Class="CControlScriptButton"/>
-								<Control Id="10059" Class="CControlScriptButton"/>
-								<Control Id="10060" Class="CControlScriptButton"/>
-							</OriginalControls>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777216" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-					<CommandBar Type="2" BarID="16777217" Class="CXTPPopupBar" Style="4194304" Position="5">
-						<Controls>
-							<Control Id="40399" Class="CControlExecScript" Caption="[Exec]"/>
-						</Controls>
-					</CommandBar>
-				</CommandBars>
-				<Layout>
-					<DockState Count="6" Version="32" ScreenSize="1024, 768">
-						<BarInfo0 BarId="1" MRUWidth="32767" MRUDockPos="0, 1, 1024, 24"/>
-						<BarInfo1 BarId="10066" MRUWidth="32767" PointPos="333, 49" MRUDockPos="318, 54, 634, 81"/>
-						<BarInfo2 BarId="9025" MRUWidth="32767" PointPos="455, 23" MRUDockPos="522, 21, 758, 48"/>
-						<BarInfo3 BarId="9017" MRUWidth="32767" PointPos="683, 23" MRUDockPos="600, 18, 761, 45"/>
-						<BarInfo4 BarId="4004" MRUWidth="32767" PointPos="0, 49" MRUDockPos="-4, 57, 319, 84"/>
-						<BarInfo5 BarId="1053" MRUWidth="32767" PointPos="0, 23" MRUDockPos="17, 26, 472, 52"/>
-					</DockState>
-					<DockBars>
-						<DockBar0 Id1="1" Id3="1053" Id4="9017" Id5="9025" Id7="10066" Id8="4004" Count="10"/>
-					</DockBars>
-				</Layout>
-			</CommandBars>
 		</Layout>
 	</ScreenLayouts>
 	<HitopObjects>
@@ -666,7 +605,145 @@
 			<IRQ Name="RTC ALARM" Number="41"/>
 			<IRQ Name="USB Wakeup" Number="42"/>
 		</Interrupts>
-		<Exceptions Id="STM32xxx_C_D_E" Count="0"/>
+		<Interrupts Id="STM32xxx_Conn_NVIC" Count="68" VectorCount="68">
+			<Vector Number="0" Enabled="0"/>
+			<Vector Number="1" Enabled="0"/>
+			<Vector Number="2" Enabled="0"/>
+			<Vector Number="3" Enabled="0"/>
+			<Vector Number="4" Enabled="0"/>
+			<Vector Number="5" Enabled="0"/>
+			<Vector Number="6" Enabled="0"/>
+			<Vector Number="7" Enabled="0"/>
+			<Vector Number="8" Enabled="0"/>
+			<Vector Number="9" Enabled="0"/>
+			<Vector Number="10" Enabled="0"/>
+			<Vector Number="11" Enabled="0"/>
+			<Vector Number="12" Enabled="0"/>
+			<Vector Number="13" Enabled="0"/>
+			<Vector Number="14" Enabled="0"/>
+			<Vector Number="15" Enabled="0"/>
+			<Vector Number="16" Enabled="0"/>
+			<Vector Number="17" Enabled="0"/>
+			<Vector Number="18" Enabled="0"/>
+			<Vector Number="19" Enabled="0"/>
+			<Vector Number="20" Enabled="0"/>
+			<Vector Number="21" Enabled="0"/>
+			<Vector Number="22" Enabled="0"/>
+			<Vector Number="23" Enabled="0"/>
+			<Vector Number="24" Enabled="0"/>
+			<Vector Number="25" Enabled="0"/>
+			<Vector Number="26" Enabled="0"/>
+			<Vector Number="27" Enabled="0"/>
+			<Vector Number="28" Enabled="0"/>
+			<Vector Number="29" Enabled="0"/>
+			<Vector Number="30" Enabled="0"/>
+			<Vector Number="31" Enabled="0"/>
+			<Vector Number="32" Enabled="0"/>
+			<Vector Number="33" Enabled="0"/>
+			<Vector Number="34" Enabled="0"/>
+			<Vector Number="35" Enabled="0"/>
+			<Vector Number="36" Enabled="0"/>
+			<Vector Number="37" Enabled="0"/>
+			<Vector Number="38" Enabled="0"/>
+			<Vector Number="39" Enabled="0"/>
+			<Vector Number="40" Enabled="0"/>
+			<Vector Number="41" Enabled="0"/>
+			<Vector Number="42" Enabled="0"/>
+			<Vector Number="43" Enabled="0"/>
+			<Vector Number="44" Enabled="0"/>
+			<Vector Number="45" Enabled="0"/>
+			<Vector Number="46" Enabled="0"/>
+			<Vector Number="47" Enabled="0"/>
+			<Vector Number="48" Enabled="0"/>
+			<Vector Number="49" Enabled="0"/>
+			<Vector Number="50" Enabled="0"/>
+			<Vector Number="51" Enabled="0"/>
+			<Vector Number="52" Enabled="0"/>
+			<Vector Number="53" Enabled="0"/>
+			<Vector Number="54" Enabled="0"/>
+			<Vector Number="55" Enabled="0"/>
+			<Vector Number="56" Enabled="0"/>
+			<Vector Number="57" Enabled="0"/>
+			<Vector Number="58" Enabled="0"/>
+			<Vector Number="59" Enabled="0"/>
+			<Vector Number="60" Enabled="0"/>
+			<Vector Number="61" Enabled="0"/>
+			<Vector Number="62" Enabled="0"/>
+			<Vector Number="63" Enabled="0"/>
+			<Vector Number="64" Enabled="0"/>
+			<Vector Number="65" Enabled="0"/>
+			<Vector Number="66" Enabled="0"/>
+			<Vector Number="67" Enabled="0"/>
+			<IRQ Name="WWDG" Number="0"/>
+			<IRQ Name="PVD" Number="1"/>
+			<IRQ Name="TAMPER" Number="2"/>
+			<IRQ Name="RTC" Number="3"/>
+			<IRQ Name="FLASH" Number="4"/>
+			<IRQ Name="RCC" Number="5"/>
+			<IRQ Name="EXTI 0" Number="6"/>
+			<IRQ Name="EXTI 1" Number="7"/>
+			<IRQ Name="EXTI 2" Number="8"/>
+			<IRQ Name="EXTI 3" Number="9"/>
+			<IRQ Name="EXTI 4" Number="10"/>
+			<IRQ Name="DMA Channel 1" Number="11"/>
+			<IRQ Name="DMA Channel 2" Number="12"/>
+			<IRQ Name="DMA Channel 3" Number="13"/>
+			<IRQ Name="DMA Channel 4" Number="14"/>
+			<IRQ Name="DMA Channel 5" Number="15"/>
+			<IRQ Name="DMA Channel 6" Number="16"/>
+			<IRQ Name="DMA Channel 7" Number="17"/>
+			<IRQ Name="ADC" Number="18"/>
+			<IRQ Name="CAN1 TX" Number="19"/>
+			<IRQ Name="CAN1 RX 0" Number="20"/>
+			<IRQ Name="CAN1 RX 1" Number="21"/>
+			<IRQ Name="CAN_SCE" Number="22"/>
+			<IRQ Name="EXTI 5-9" Number="23"/>
+			<IRQ Name="TIM 1 BRK" Number="24"/>
+			<IRQ Name="TIM 1 UP" Number="25"/>
+			<IRQ Name="TIM 1 TRG COM" Number="26"/>
+			<IRQ Name="TIM 1 CC" Number="27"/>
+			<IRQ Name="TIM 2" Number="28"/>
+			<IRQ Name="TIM 3" Number="29"/>
+			<IRQ Name="TIM 4" Number="30"/>
+			<IRQ Name="I2C 1 EV" Number="31"/>
+			<IRQ Name="I2C 1 ER" Number="32"/>
+			<IRQ Name="I2C 2 EV" Number="33"/>
+			<IRQ Name="I2C 2 ER" Number="34"/>
+			<IRQ Name="SPI 1" Number="35"/>
+			<IRQ Name="SPI 2" Number="36"/>
+			<IRQ Name="USART 1" Number="37"/>
+			<IRQ Name="USART 2" Number="38"/>
+			<IRQ Name="USART 3" Number="39"/>
+			<IRQ Name="EXTI 10-15" Number="40"/>
+			<IRQ Name="RTC ALARM" Number="41"/>
+			<IRQ Name="USB OTG Wakeup" Number="42"/>
+			<IRQ Name="Reserved" Number="43"/>
+			<IRQ Name="Reserved" Number="44"/>
+			<IRQ Name="Reserved" Number="45"/>
+			<IRQ Name="Reserved" Number="46"/>
+			<IRQ Name="Reserved" Number="47"/>
+			<IRQ Name="Reserved" Number="48"/>
+			<IRQ Name="Reserved" Number="49"/>
+			<IRQ Name="TIM 5" Number="50"/>
+			<IRQ Name="SPI 3" Number="51"/>
+			<IRQ Name="UART 4" Number="52"/>
+			<IRQ Name="UART 5" Number="53"/>
+			<IRQ Name="TIM 6" Number="54"/>
+			<IRQ Name="TIM 7" Number="55"/>
+			<IRQ Name="DMA2 Channel 1" Number="56"/>
+			<IRQ Name="DMA2 Channel 2" Number="57"/>
+			<IRQ Name="DMA2 Channel 3" Number="58"/>
+			<IRQ Name="DMA2 Channel 4" Number="59"/>
+			<IRQ Name="DMA2 Channel 5" Number="60"/>
+			<IRQ Name="ETH" Number="61"/>
+			<IRQ Name="ETH_WKUP" Number="62"/>
+			<IRQ Name="CAN 2 TX" Number="63"/>
+			<IRQ Name="CAN 2 RX0" Number="64"/>
+			<IRQ Name="CAN 2 RX1" Number="65"/>
+			<IRQ Name="CAN 2 SCE" Number="66"/>
+			<IRQ Name="OTG FS" Number="67"/>
+		</Interrupts>
+		<Exceptions Id="STM32xxx_Conn" Count="0"/>
 	</ExceptionAssistant>
 	<HiTOPOpen ComponentId="Semihosting">
 		<Configuration>
@@ -674,18 +751,17 @@
 		</Configuration>
 	</HiTOPOpen>
 	<Directories>
-		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210E-EVAL_XL\objects\Project.abs"/>
+		<Directory Id="ProjectAddApplication" Dir="C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210C-EVAL\objects\Project.abs"/>
 	</Directories>
 	<Applications>
 		<AppPath Id="STM32F103_Tasking">.\objects\</AppPath>
-		<AppPath Id="Project">C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210E-EVAL_XL\objects\</AppPath>
+		<AppPath Id="Project">C:\PWA_2007\INTROPACK\PROJECT\STM32F10x_StdPeriph_Template\HiTOP\STM3210C-EVAL\objects\</AppPath>
 	</Applications>
 	<FlashProgramming RAMBase="0x20000000" NumDevices="1" SaveRestoreRAM="1" EnableProgramming="1">
-		<FlashDevice Type="STM32F103xG" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x8000000" Manufacturer="ST">
+		<FlashDevice Type="STM32F107VC" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x8000000" Manufacturer="ST">
 			<Sectors/>
 		</FlashDevice>
 	</FlashProgramming>
-	<Component Id="DataTrace"/>
 	<HiTOPOpen ComponentId="SemiHosting">
 		<Configuration>
 			<General Showed="0"/>
@@ -731,9 +807,9 @@
 				<DebugMode>
 					<Summary Panes="45" Client="25" TopContainer="16"></Summary>
 					<Pane-1 ID="40364" Tag="13194360" Type="0" Title="Workspace - ModuleView\nModuleView\n" DockingCX="200" DockingCY="120" LastHolder="22" DockingHolder="22" FloatingHolder="42"></Pane-1>
-					<Pane-2 ID="40365" Tag="63430216" Type="0" Title="Workspace - FileView\nFileView\n" DockingCX="200" DockingCY="120" LastHolder="22" DockingHolder="22" FloatingHolder="42"></Pane-2>
-					<Pane-3 ID="40100" Tag="72851504" Type="0" Title="Register\n\n" DockingCX="200" DockingCY="120" LastHolder="27" DockingHolder="27"></Pane-3>
-					<Pane-4 ID="40932" Tag="74684808" Type="0" Title="Emulator State\n\n" DockingCX="200" DockingCY="120" LastHolder="28" DockingHolder="28"></Pane-4>
+					<Pane-2 ID="40365" Tag="36995920" Type="0" Title="Workspace - FileView\nFileView\n" DockingCX="200" DockingCY="120" LastHolder="22" DockingHolder="22" FloatingHolder="42"></Pane-2>
+					<Pane-3 ID="40100" Tag="74880280" Type="0" Title="Register\n\n" DockingCX="200" DockingCY="120" LastHolder="27" DockingHolder="27"></Pane-3>
+					<Pane-4 ID="40932" Tag="76360064" Type="0" Title="Emulator State\n\n" DockingCX="200" DockingCY="120" LastHolder="28" DockingHolder="28"></Pane-4>
 					<Pane-5 ID="40000" Type="0" Title="Watch - Locals\nLocals\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="33"></Pane-5>
 					<Pane-6 ID="40001" Type="0" Title="Watch - Watch1\nWatch1\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="33"></Pane-6>
 					<Pane-7 ID="40050" Tag="42486464" Type="0" Title="Memory - Mem0\nMem0\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30"></Pane-7>
@@ -741,12 +817,12 @@
 					<Pane-9 ID="40051" Type="0" Title="Memory - Flash\nFlash\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="36"></Pane-9>
 					<Pane-10 ID="40052" Type="0" Title="Memory - RAM\nRAM\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30"></Pane-10>
 					<Pane-11 ID="40053" Type="0" Title="Memory - Base\nBase\n" DockingCX="200" DockingCY="120" LastHolder="30" DockingHolder="30" FloatingHolder="39"></Pane-11>
-					<Pane-12 ID="40110" Tag="38001472" Type="0" Title="Callstack\n\n" DockingCX="200" DockingCY="120" LastHolder="23" DockingHolder="23" FloatingHolder="45"></Pane-12>
+					<Pane-12 ID="40110" Tag="38329752" Type="0" Title="Callstack\n\n" DockingCX="200" DockingCY="120" LastHolder="23" DockingHolder="23" FloatingHolder="45"></Pane-12>
 					<Pane-13 Type="5" Panes="0" Direction="0"></Pane-13>
 					<Pane-14 Type="5" Panes="0" Direction="1"></Pane-14>
 					<Pane-15 Type="5" Panes="0" Direction="3"></Pane-15>
 					<Pane-16 Type="2" Panes="2" Pane-1="17" Pane-2="29" DockingCY="873"></Pane-16>
-					<Pane-17 Type="2" Horiz="1" Panes="1" Pane-1="18" DockingCY="589"></Pane-17>
+					<Pane-17 Type="2" Horiz="1" Panes="1" Pane-1="18" DockingCY="545"></Pane-17>
 					<Pane-18 Type="2" Horiz="1" Panes="2" Pane-1="19" Pane-2="26" DockingCX="1024" DockingCY="388"></Pane-18>
 					<Pane-19 Type="2" Panes="1" Pane-1="20" DockingCX="1032"></Pane-19>
 					<Pane-20 Type="2" Horiz="1" Panes="2" Pane-1="21" Pane-2="24" DockingCX="853" DockingCY="342"></Pane-20>
@@ -758,7 +834,7 @@
 					<Pane-26 Type="2" Panes="2" Pane-1="27" Pane-2="28" DockingCX="244" DockingCY="454"></Pane-26>
 					<Pane-27 Type="1" Panes="1" Pane-1="3" Selected="3" DockingCX="200" DockingCY="319"></Pane-27>
 					<Pane-28 Type="1" Panes="1" Pane-1="4" Selected="4" DockingCX="287" DockingCY="131"></Pane-28>
-					<Pane-29 Type="2" Horiz="1" Panes="1" Pane-1="30" DockingCX="1280" DockingCY="280"></Pane-29>
+					<Pane-29 Type="2" Horiz="1" Panes="1" Pane-1="30" DockingCX="1280" DockingCY="324"></Pane-29>
 					<Pane-30 Type="1" Panes="4" Pane-1="5" Pane-2="7" Pane-3="6" Pane-4="8" Selected="8" DockingCX="1103" DockingCY="101"></Pane-30>
 					<Pane-31 Type="3" TopContaner="32" WindowRectTopPos="486" WindowRectLeftPos="608" WindowRectRightPos="1246" WindowRectBottomPos="691"></Pane-31>
 					<Pane-32 Type="2" Horiz="1" Panes="1" Pane-1="33" DockingCX="200" DockingCY="120"></Pane-32>
@@ -794,7 +870,7 @@
 						<Position x="0" y="0"></Position>
 					</Rectangle>
 					<Rectangle State="Maximized">
-						<Size cx="844" cy="623"></Size>
+						<Size cx="844" cy="579"></Size>
 						<Position x="-4" y="-23"></Position>
 					</Rectangle>
 				</Window>
@@ -816,8 +892,8 @@
 						<Controls OriginalControls="1">
 							<Control Id="10065" Type="4" Class="CXTPControlPopup" Caption="Execute script" TooltipText="Execute script file" CommandBarId="16777216" DescriptionText="Execute a HiSCRIPT script file."></Control>
 							<Control Id="40398" Class="CXTPControlButton" Caption="Abort script file execution" TooltipText="Abort script file execution" DescriptionText="Abort script file execution."></Control>
-							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_appl.scr"></Control>
-							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210E-EVAL_XL\\Settings\\reset_go_main.scr"></Control>
+							<Control Id="10051" Class="CControlScriptButton" Style="3" Caption="RESET_APPL" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210C-EVAL\\Settings\\reset_appl.scr" BeginGroup="1" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210C-EVAL\\Settings\\reset_appl.scr"></Control>
+							<Control Id="10052" Class="CControlScriptButton" Style="3" Caption="RESET_GO_MAIN" Parameter="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210C-EVAL\\Settings\\reset_go_main.scr" TooltipText="C:\\PWA_2007\\INTROPACK\\PROJECT\\STM32F10x_StdPeriph_Template\\HiTOP\\STM3210C-EVAL\\Settings\\reset_go_main.scr"></Control>
 							<Control Id="10053" Class="CControlScriptButton"></Control>
 							<Control Id="10054" Class="CControlScriptButton"></Control>
 							<Control Id="10055" Class="CControlScriptButton"></Control>
@@ -933,20 +1009,22 @@
 			</CommandBars>
 		</Layout>
 	</RecentScreenLayouts>
+	<Component Id="DataTrace"/>
 	<PowerScale EnableInstrumentation="0"/>
 	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="Project" AutoDetectChanges="1">
 		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM32F10X_XL">
+		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM3210C-EVAL">
 			<SymbolLoader ProjRel="1" MessageFile="" NeedsSymprepRun="0">
 				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
 					<SourcePath>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text=".\"/>
+						<Path Text="..\..\..\..\Libraries\CMSIS\Core\CM3\"/>
 						<Path Text="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
 						<Path Text="..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\"/>
+						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\"/>
 						<Path Text="..\..\"/>
+						<Path Text=".\"/>
+						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
+						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
 						<Path Text="..\..\..\..\Utilities\STM32_EVAL\Common\"/>
 					</SourcePath>
 					<ProcessorSpecific>
@@ -956,18 +1034,18 @@
 				</Options>
 			</SymbolLoader>
 			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM32F10X_XL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
+			<BuildConfiguration Id="STM3210C-EVAL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
 				<General OutputPath=".\objects\" TargetName="Project.abs" StopBuildOnError="1">
 					<IncludePath Path="..\..\" Position="0"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="1"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="2"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="4"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="5"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\" Position="6"></IncludePath>
+					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="1"></IncludePath>
+					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="2"></IncludePath>
+					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\" Position="3"></IncludePath>
+					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="4"></IncludePath>
+					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="5"></IncludePath>
+					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="6"></IncludePath>
 				</General>
 				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_XL;USE_STM3210E_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -v -Wa-L1 -Wc-t4   -Wc-w560 -Wc-w557 -Wc-w523 "></Compiler>
+				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_CL;USE_STM3210C_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -Wc-I&quot;$(TARGETDIR)\..\library\inc&quot; -v -Wa-L1 -Wc-t4  -Wc-w560 -Wc-w557 -Wc-w523  "></Compiler>
 				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
 			</BuildConfiguration>
 		</Application>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl
index a85d784..a85d784 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/STM32F10x_cl.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr
index e3dbe23..e3dbe23 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/StartupScript.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/arm_arch.lsl
index 3e6d303..3e6d303 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/arm_arch.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_appl.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr
index 3e9c066..3e9c066 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_go_main.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/Settings/reset_go_main.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt
index 33c0957..33c0957 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210C-EVAL/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl
index 77a6526..77a6526 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_extsram.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10xnor.lsl
index adaac37..5b781d8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_extsram.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10xnor.lsl
@@ -29,7 +29,7 @@
 #  define __HEAP                        2k
 #endif
 #ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR        0x08000000
+#  define __VECTOR_TABLE_ROM_ADDR        0x64000000
 #endif
 #ifndef __XVWBUF
 #define __XVWBUF                        256             /* buffer used by CrossView */
@@ -57,28 +57,19 @@ memory stm32f103flash
 {
     mau = 8;
     type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset= 0x08000000, dest=bus:ARM:local_bus);
+    size = 8192k;
+    map ( size = 512k, dest_offset= 0x64000000, dest=bus:ARM:local_bus);
 }
 
 memory stm32f103ram
 {
     mau = 8;
     type = ram;
-    size = 1024k;
-    map ( size = 1024k, dest_offset=0x68000000, dest=bus:ARM:local_bus);
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
 }
 
 #endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
-
 
 
 //
@@ -96,7 +87,7 @@ section_setup ::linear
                                               no_inline
                                             )
                 {
-                         vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
+                         vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
                         vector ( id = 1, fill = "_START" );
                         vector ( id = 2, optional, fill = "NMI_Handler" );
                         vector ( id = 3, optional, fill = "HardFault_Handler" );
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr
new file mode 100644
index 0000000..e3dbe23
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr
@@ -0,0 +1,9 @@
+// Hitex/Lue/11.02.2008 
+// Executable Script file for HiTOP Debugger
+// Reset application 
+
+// Reset    
+RESET TARGET
+
+
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr
index 4dbe250..4dbe250 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/link.lnk
index 2d9c35c..b4d7818 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210X-XL/link_offset.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/link.lnk
@@ -1,4 +1,4 @@
--d"./settings/STM32F10x_offset.lsl"
+-d"./settings/STM32F10x_hd.lsl"
 --optimize=0
 --map-file-format=2
 $(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk
index c14afff..c14afff 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr
index d90eb15..d90eb15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/reset_appl.scr
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr
new file mode 100644
index 0000000..3e9c066
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr
@@ -0,0 +1,12 @@
+// Hitex/Lue/11.02.2008 
+// Executable Script file for HiTOP Debugger
+// Reset application & Go main 
+
+// Reset    
+RESET TARGET
+
+
+// execute program till main
+Go UNTIL main
+wait
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/cstart_thumb2.asm
index 12dc0d0..12dc0d0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/cstart_thumb2.asm
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt
index 7e4c10b..7e4c10b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl
index 2cddf36..2cddf36 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_XL.lsl
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl
index 5bf6ca2..5bf6ca2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/STM32F10x_xl_extsram.lsl
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/StartupScript.scr
new file mode 100644
index 0000000..e3dbe23
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/StartupScript.scr
@@ -0,0 +1,9 @@
+// Hitex/Lue/11.02.2008 
+// Executable Script file for HiTOP Debugger
+// Reset application 
+
+// Reset    
+RESET TARGET
+
+
+
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl
new file mode 100644
index 0000000..3e6d303
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/arm_arch.lsl
@@ -0,0 +1,287 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  arm_arch.lsl
+//
+//  Version     :  @(#)arm_arch.lsl     1.4  09/04/17
+//
+//  Description :  Generic LSL file for ARM architectures
+//
+//  Copyright 2008-2009 Altium BV
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __STACK
+#  define __STACK                       32k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        32k
+#endif
+#ifndef __STACK_FIQ
+#  define __STACK_FIQ                   8
+#endif
+#ifndef __STACK_IRQ
+#  define __STACK_IRQ                   8
+#endif
+#ifndef __STACK_SVC
+#  define __STACK_SVC                   8
+#endif
+#ifndef __STACK_ABT
+#  define __STACK_ABT                   8
+#endif
+#ifndef __STACK_UND
+#  define __STACK_UND                   8
+#endif
+#ifndef __PROCESSOR_MODE
+#  define __PROCESSOR_MODE              0x1F            /* SYS mode */
+#endif
+#ifndef __IRQ_BIT
+#  define __IRQ_BIT                     0x80            /* IRQ interrupts disabled */
+#endif
+#ifndef __FIQ_BIT
+#  define __FIQ_BIT                     0x40            /* FIQ interrupts disabled */
+#endif
+
+#define __APPLICATION_MODE              (__PROCESSOR_MODE | __IRQ_BIT | __FIQ_BIT)
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x00000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+#if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
+#  ifndef __NR_OF_VECTORS
+#    define __NR_OF_VECTORS             16
+#  endif
+#  define __VECTOR_TABLE_SIZE           (__NR_OF_VECTORS * 4)
+#else
+#  ifdef __PIC_VECTORS
+#    define __VECTOR_TABLE_SIZE         64
+#  else
+#    ifdef __FIQ_HANDLER_INLINE
+#      define __VECTOR_TABLE_SIZE       28
+#      define __NR_OF_VECTORS           7
+#    else
+#      define __VECTOR_TABLE_SIZE       32
+#      define __NR_OF_VECTORS           8
+#    endif
+#  endif
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_SPACE
+#  undef __VECTOR_TABLE_RAM_COPY
+#endif
+
+#ifndef __XVWBUF
+#  define __XVWBUF                      0               /* buffer used by CrossView Pro */
+#endif
+
+#define BOUNDS_GROUP_NAME       grp_bounds
+#define BOUNDS_GROUP_SELECT     "bounds"
+
+architecture ARM
+{
+        endianness
+        {
+                little;
+                big;
+        }
+
+        space linear
+        {
+                id = 1;
+                mau = 8;
+                map (size = 4G, dest = bus:local_bus);
+
+                copytable
+                (
+                        align = 4,
+                        copy_unit = 1,
+                        dest = linear
+                );
+
+                start_address
+                (
+                        // It is not strictly necessary to define a run_addr for _START
+                        // because hardware starts execution at address 0x0 which should
+                        // be the vector table with a jump to the relocatable _START, but
+                        // an absolute address can prevent the branch to be out-of-range.
+                        // Or _START may be the entry point at reset and the reset handler
+                        // copies the vector table to address 0x0 after some ROM/RAM memory
+                        // re-mapping. In that case _START should be at a fixed address
+                        // in ROM, specifically the alias of address 0x0 before memory
+                        // re-mapping.
+#ifdef __START
+                        run_addr = __START,
+#endif
+                        symbol = "_START"
+                );
+
+                stack "stack"
+                (
+#ifdef __STACK_FIXED
+                        fixed,
+#endif
+                        align = 4,
+                        min_size = __STACK,
+                        grows = high_to_low
+                );
+
+                heap "heap"
+                (
+#ifdef __HEAP_FIXED
+                        fixed,
+#endif
+                        align = 4,
+                        min_size=__HEAP
+                );
+
+#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
+                stack "stack_fiq"
+                (
+                        fixed,
+                        align = 4,
+                        min_size = __STACK_FIQ,
+                        grows = high_to_low
+                );
+                stack "stack_irq"
+                (
+                        fixed,
+                        align = 4,
+                        min_size = __STACK_IRQ,
+                        grows = high_to_low
+                );
+                stack "stack_svc"
+                (
+                        fixed,
+                        align = 4,
+                        min_size = __STACK_SVC,
+                        grows = high_to_low
+                );
+                stack "stack_abt"
+                (
+                        fixed,
+                        align = 4,
+                        min_size = __STACK_ABT,
+                        grows = high_to_low
+                );
+                stack "stack_und"
+                (
+                        fixed,
+                        align = 4,
+                        min_size = __STACK_UND,
+                        grows = high_to_low
+                );
+#endif
+
+#if !defined(__NO_AUTO_VECTORS) && !defined(__NO_DEFAULT_AUTO_VECTORS)
+# if defined(__CPU_ARMV7M__) || defined(__CPU_ARMV6M__)
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work
+                        vector ( id = 1, fill = "_START" );
+                }
+#  else
+#    ifdef __PIC_VECTORS
+                // vector table with ldrpc instructions from handler table
+                vector_table "vector_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.vector_ldrpc",
+                                              template_symbol = "_lc_vector_ldrpc",
+                                              vector_prefix = "_vector_ldrpc_",
+                                              fill = loop
+                                            )
+                {
+                }
+                // subsequent vector table (data pool) with addresses of handlers
+                vector_table "handler_table" ( vector_size = 4, size = 8, run_addr = __VECTOR_TABLE_ROM_ADDR + 32,
+                                               template = ".text.handler_address",
+                                               template_symbol = "_lc_vector_handler",
+                                               vector_prefix = "_vector_",
+                                               fill = loop[-32],
+                                               no_inline
+                                             )
+                {
+                        vector ( id = 0, fill = "_START" );
+                }
+#    else
+                // vector table with branch instructions to handlers
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.vector_branch",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop
+                                            )
+                {
+                        vector ( id = 0, fill = "_START" );
+                }
+#    endif
+#  endif
+#endif
+                section_layout
+                {
+#if defined(__NO_AUTO_VECTORS)
+                        "_lc_ub_vector_table" = __VECTOR_TABLE_ROM_ADDR;
+                        "_lc_ue_vector_table" = __VECTOR_TABLE_ROM_ADDR + __VECTOR_TABLE_SIZE;
+#endif
+#ifdef __VECTOR_TABLE_RAM_SPACE
+                        // reserve space to copy vector table from ROM to RAM
+                        group ( ordered, run_addr = __VECTOR_TABLE_RAM_ADDR )
+                                reserved "vector_table_space" ( size = __VECTOR_TABLE_SIZE, attributes = rwx );
+#endif
+#ifdef __VECTOR_TABLE_RAM_COPY
+                        // provide copy address symbols for copy routine
+                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table_space";
+                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table_space";
+#else
+                        // prevent copy: copy address equals orig address
+                        "_lc_ub_vector_table_copy" := "_lc_ub_vector_table";
+                        "_lc_ue_vector_table_copy" := "_lc_ue_vector_table";
+#endif
+                        // define buffer for string input via Crossview Pro debugger
+                        group ( align = 4 ) reserved "xvwbuffer"  (size=__XVWBUF, attributes=rw );
+
+                        // define labels for bounds begin and end as used in C library
+#ifndef BOUNDS_GROUP_REDEFINED
+                        group BOUNDS_GROUP_NAME (ordered, contiguous)
+                        {
+                                select BOUNDS_GROUP_SELECT;
+                        }
+#endif
+                        "_lc_ub_bounds" := addressof(group:BOUNDS_GROUP_NAME);
+                        "_lc_ue_bounds" := addressof(group:BOUNDS_GROUP_NAME) + sizeof(group:BOUNDS_GROUP_NAME);
+
+#ifdef __HEAPADDR
+                        group ( ordered, run_addr=__HEAPADDR )
+                        {
+                                select "heap";
+                        }
+#endif
+#ifdef __STACKADDR
+                        group ( ordered, run_addr=__STACKADDR )
+                        {
+                                select "stack";
+                        }
+#endif
+#if !defined(__CPU_ARMV7M__) && !defined(__CPU_ARMV6M__)
+                        // symbol to set mode bits and interrupt disable bits
+                        // in cstart module before calling the application (main)
+                        "_APPLICATION_MODE_" = __APPLICATION_MODE;
+#endif
+                }
+        }
+
+        bus local_bus
+        {
+                mau = 8;
+                width = 32;
+        }
+}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linkextsram.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/linkextsram.lnk
index 6dbf95a..b42fed0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linkextsram.lnk
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/Settings/linkextsram.lnk
@@ -1,4 +1,4 @@
--d"./settings/STM32F10x_extsram.lsl"
+-d"./settings/STM32F10x_xl_extsram.lsl"
 --optimize=0
 --map-file-format=2
 $(LinkObjects)
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm
new file mode 100644
index 0000000..12dc0d0
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/cstart_thumb2.asm
@@ -0,0 +1,148 @@
+
+
+;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;;        we will only use 16-bit Thumb intructions.
+
+        .extern _lc_ub_stack            ; usr/sys mode stack pointer
+        .extern _lc_ue_stack            ; symbol required by debugger
+        .extern _lc_ub_table            ; ROM to RAM copy table
+        .extern main
+        .extern _Exit
+        .extern exit
+        .weak   exit
+        .global __get_argcv
+        .weak   __get_argcv
+        .extern __argcvbuf
+        .weak   __argcvbuf
+        .extern __init_hardware
+        .extern __init_vector_table
+		.extern  SystemInit
+        
+    .if @defined('__PROF_ENABLE__')
+        .extern __prof_init
+    .endif
+    .if @defined('__POSIX__')
+        .extern posix_main
+        .extern _posix_boot_stack_top
+    .endif
+
+        .global _START
+
+        .section .text.cstart
+
+        .thumb
+_START: 
+        ;; anticipate possible ROM/RAM remapping
+        ;; by loading the 'real' program address
+        ldr     r1,=_Next
+        bx      r1
+_Next:
+        ;; initialize the stack pointer
+        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
+        mov     sp,r1
+
+        ;; call a user function which initializes hardware
+        ;; such as ROM/RAM re-mapping or MMU configuration
+        bl      __init_hardware
+
+		;ldr    r0, =SystemInit
+        ;bx     r0
+		bl  SystemInit
+
+        ;; copy initialized sections from ROM to RAM
+        ;; and clear uninitialized data sections in RAM
+
+        ldr     r3,=_lc_ub_table
+        movs    r0,#0
+cploop:
+        ldr     r4,[r3,#0]      ; load type
+        ldr     r5,[r3,#4]      ; dst address
+        ldr     r6,[r3,#8]      ; src address
+        ldr     r7,[r3,#12]     ; size
+
+        cmp     r4,#1
+        beq     copy
+        cmp     r4,#2
+        beq     clear
+        b       done
+
+copy:
+        subs    r7,r7,#1
+        ldrb    r1,[r6,r7]
+        strb    r1,[r5,r7]
+        bne     copy
+
+        adds    r3,r3,#16
+        b       cploop
+
+clear:
+        subs    r7,r7,#1
+        strb    r0,[r5,r7]
+        bne     clear
+        
+        adds    r3,r3,#16
+        b       cploop
+        
+done:   
+        ;; initialize or copy the vector table
+        bl      __init_vector_table
+ 
+      .if @defined('__POSIX__')
+        
+        ;; posix stack buffer for system upbringing
+        ldr     r0,=_posix_boot_stack_top
+        ldr     r0, [r0]
+        mov     sp,r0
+     
+     .else
+        
+        ;; load r10 with end of USR/SYS stack, which is
+        ;; needed in case stack overflow checking is on
+        ;; NOTE: use 16-bit instructions only, for ARMv6M
+        ldr     r0,=_lc_ue_stack
+        mov     r10,r0
+     
+     .endif
+
+    .if @defined('__PROF_ENABLE__')
+        bl      __prof_init
+    .endif
+
+    .if @defined('__POSIX__')
+        ;; call posix_main with no arguments
+        bl      posix_main
+    .else
+        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+        bl      __get_argcv
+        ldr     r1,=__argcvbuf
+        ;; call main
+        bl       main
+    .endif
+
+        ;; call exit using the return value from main()
+        ;; Note. Calling exit will also run all functions
+        ;; that were supplied through atexit().
+        bl      exit
+        
+__get_argcv:                    ; weak definition
+        movs     r0,#0
+        bx      lr
+
+        .ltorg
+        .endsec
+
+        .calls  '_START','__init_hardware'
+        .calls  '_START','__init_vector_table'
+    .if @defined('__PROF_ENABLE__')
+        .calls  '_START','__prof_init'
+    .endif
+    .if @defined('__POSIX__')
+        .calls  '_START','posix_main'
+    .else
+        .calls  '_START','__get_argcv'
+        .calls  '_START','main'
+    .endif
+        .calls  '_START','exit'
+        .calls  '_START','',0
+
+        .end
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
index 2c11b4c..2c11b4c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/setstack.asm
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvopt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvopt
new file mode 100644
index 0000000..f9313c5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvopt
@@ -0,0 +1,1817 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM32100E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32100E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments></SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments></TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O14 -O2062 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32100B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32100B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F100B</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F100B</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0172U9E -O2062 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06430041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128_8k -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210C-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210C-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>7</Title>
+          <Path>DATASHTS\ST\STM32F105</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F107VC</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F107VC</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O14 -O2062 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0391M9E -O2062 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06414041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0172U9E -O2062 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06410041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC5000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>User</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>23</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>6</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\stm32f10x_it.c</PathWithFileName>
+      <FilenameWithoutPath>stm32f10x_it.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>23</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>85</TopLine>
+      <CurrentLine>85</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <WindowPosition>
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diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt
index c647c15..c647c15 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp
index 20cb2fa..20cb2fa 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rapp
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rprj b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rprj
new file mode 100644
index 0000000..321679a
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/Project.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'Project'" Path=".\Project.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="Project" AsyncBuild="" >
+	<ApplicationBuild Header="Project" Extern=".\Project.rapp" Path=".\Project.rapp" OutputFile=".\STM32100E-EVAL\Project.elf" sate="98" Config="STM32100E-EVAL" AsyncBuild="" />
+</Project>
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/RIDE/readme.txt
index ddbe3c5..ddbe3c5 100644
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index 4131fd2..4131fd2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.cproject
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.cproject
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index 04e9dba..04e9dba 100644
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diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/readme.txt
new file mode 100644
index 0000000..170d00f
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/readme.txt
@@ -0,0 +1,72 @@
+/**
+  @page TrueSTUDIO_STM32100B TrueSTUDIO Project Template for Medium-density Value line devices
+ 
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This sub directory contains all the user modifiable files 
+  *          needed to create a new project linked with the STM32F10x  
+  *          Standard Peripheral Library and working with TrueSTUDIO software 
+  *          toolchain (Version 2.0.1 and later)
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+  @endverbatim
+ 
+ @par Directory contents
+ 
+ - project .cproject/.project: A pre-configured project file with the provided 
+                               library structure that produces an executable 
+                               image with TrueSTUDIO.
+
+ - stm32_flash.ld: 			       This file is the TrueSTUDIO linker script used to 
+                               place program code (readonly) in internal FLASH 
+                               and data (readwrite, Stack and Heap)in internal 
+                               SRAM. 
+                               You can customize this file to your need.
+                           
+ @par How to use it ?
+
+ - Open the TrueSTUDIO toolchain.
+ - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+   directory.
+ - Click on File->Import, select General->'Existing Projects into Workspace' 
+   and then click "Next". 
+ - Browse to the TrueSTUDIO workspace directory and select the project: 
+   - STM32100B-EVAL: to configure the project for STM32 Medium-density Value 
+     line devices.
+ - Under Windows->Preferences->General->Workspace->Linked Resources, add 
+   a variable path named "CurPath" which points to the folder containing
+   "Libraries", "Project" and "Utilities" folders.
+ - Rebuild all project files: Select the project in the "Project explorer" 
+   window then click on Project->build project menu.
+ - Run program: Select the project in the "Project explorer" window then click 
+   Run->Debug (F11)
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 32 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld
index 747dfd0..747dfd0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100B-EVAL/stm32_flash.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project
index b09714a..b09714a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.project
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index 34b3d6f..34b3d6f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt
index 04b0397..04b0397 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld
index aa77c9f..aa77c9f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM32100E-EVAL/stm32_flash.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject
index fa5f17b..fa5f17b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.cproject
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.project
index 04467fa..04467fa 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.project
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index 5667d56..5667d56 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt
index 0038a2e..0038a2e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210B-EVAL/readme.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject
index f746548..f746548 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.cproject
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project
index e181d6d..e181d6d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.project
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index 2e8d862..2e8d862 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/readme.txt
new file mode 100644
index 0000000..d7c5931
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/readme.txt
@@ -0,0 +1,71 @@
+/**
+  @page TrueSTUDIO_STM3210C TrueSTUDIO Project Template for Connectivity line devices
+ 
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This sub directory contains all the user modifiable files 
+  *          needed to create a new project linked with the STM32F10x  
+  *          Standard Peripheral Library and working with TrueSTUDIO software 
+  *          toolchain (Version 2.0.1 and later)
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+  @endverbatim
+ 
+ @par Directory contents
+ 
+ - project .cproject/.project: A pre-configured project file with the provided 
+                               library structure that produces an executable 
+                               image with TrueSTUDIO.
+
+ - stm32_flash.ld: 			       This file is the TrueSTUDIO linker script used to 
+                               place program code (readonly) in internal FLASH 
+                               and data (readwrite, Stack and Heap)in internal 
+                               SRAM. 
+                               You can customize this file to your need.
+                           
+ @par How to use it ?
+
+ - Open the TrueSTUDIO toolchain.
+ - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+   directory.
+ - Click on File->Import, select General->'Existing Projects into Workspace' 
+   and then click "Next". 
+ - Browse to the TrueSTUDIO workspace directory and select the project: 
+   - STM3210C-EVAL: to configure the project for STM32 Connectivity line devices.
+ - Under Windows->Preferences->General->Workspace->Linked Resources, add 
+   a variable path named "CurPath" which points to the folder containing
+   "Libraries", "Project" and "Utilities" folders.
+ - Rebuild all project files: Select the project in the "Project explorer" 
+   window then click on Project->build project menu.
+ - Run program: Select the project in the "Project explorer" window then click 
+   Run->Debug (F11)
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 32 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld
index aa88229..aa88229 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210C-EVAL/stm32_flash.ld
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject
index f53986f..f53986f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.cproject
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
index 79946f6..79946f6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..869a4f8
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,269 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210E-EVAL_XL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1578134158" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1314431980" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../..\..\&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\CMSIS\CM3\CoreSupport&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1997653104" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.586288316" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1820971968" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.377284588" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL_XL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.26443420" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.1289217812" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.144019967" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1807046025" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.704598245" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.478811538" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.864630601" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1692358135" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.820544888" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.710897842" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZE" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.160897551" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.417308276" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1343613995" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM32F103ZG\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1472309260" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<fileInfo id="com.atollic.truestudio.exe.debug.189815562.776930028" name="stm3210e_eval_lcd.c" rcbsApplicability="disable" resourcePath="STM32_EVAL/stm3210e_eval_lcd.c" toolsToInvoke="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113.387076145">
+						<tool id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113.387076145" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113">
+							<option id="com.atollic.truestudio.gcc.misc.otherflags.1830093020" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os -w" valueType="string"/>
+							<inputType id="com.atollic.truestudio.gcc.input.745829787" superClass="com.atollic.truestudio.gcc.input"/>
+						</tool>
+					</fileInfo>
+					<sourceEntries>
+						<entry excluding="STM32_EVAL/stm32_eval_spi_sd.c|STM32_EVAL/stm32_eval_i2c_ee.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.;com.atollic.truestudio.exe.debug.toolchain.gcc.486923113;com.atollic.truestudio.gcc.input.377284588">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.project b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.project
index bb77738..c5f433c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/.project
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>STM3210E-EVAL</name>
+	<name>STM3210E-EVAL_XL</name>
 	<comment></comment>
 	<projects>
 	</projects>
@@ -10,10 +10,6 @@
 			<triggers>clean,full,incremental,</triggers>
 			<arguments>
 				<dictionary>
-					<key>?children?</key>
-					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
-				</dictionary>
-				<dictionary>
 					<key>?name?</key>
 					<value></value>
 				</dictionary>
@@ -31,7 +27,7 @@
 				</dictionary>
 				<dictionary>
 					<key>org.eclipse.cdt.make.core.buildLocation</key>
-					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
 				</dictionary>
 				<dictionary>
 					<key>org.eclipse.cdt.make.core.contents</key>
@@ -114,7 +110,7 @@
 		<link>
 			<name>Doc/readme.txt</name>
 			<type>1</type>
-			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL/readme.txt</locationURI>
+			<locationURI>CurPath/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/readme.txt</locationURI>
 		</link>
 		<link>
 			<name>STM32_EVAL/stm3210e_eval_fsmc_nand.c</name>
@@ -282,9 +278,9 @@
 			<locationURI>CurPath/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c</locationURI>
 		</link>
 		<link>
-			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
 			<type>1</type>
-			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
+			<locationURI>CurPath/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
 		</link>
 		<link>
 			<name>User/main.c</name>
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..a3b6606
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,11 @@
+#Tue Jul 13 09:06:52 GMT+01:00 2010
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=1
+TARGET=STM32
+VERSION=1.4.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/readme.txt
new file mode 100644
index 0000000..0fd565f
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/readme.txt
@@ -0,0 +1,71 @@
+/**
+  @page TrueSTUDIO_STM3210E_XL TrueSTUDIO Project Template for XL-density devices
+ 
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   This sub directory contains all the user modifiable files 
+  *          needed to create a new project linked with the STM32F10x  
+  *          Standard Peripheral Library and working with TrueSTUDIO software 
+  *          toolchain (Version 2.0.1 and later)
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+  @endverbatim
+ 
+ @par Directory contents
+ 
+ - project .cproject/.project: A pre-configured project file with the provided 
+                               library structure that produces an executable 
+                               image with TrueSTUDIO.
+
+ - stm32_flash.ld: 			       This file is the TrueSTUDIO linker script used to 
+                               place program code (readonly) in internal FLASH 
+                               and data (readwrite, Stack and Heap)in internal 
+                               SRAM. 
+                               You can customize this file to your need.
+                           
+ @par How to use it ?
+
+ - Open the TrueSTUDIO toolchain.
+ - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+   directory.
+ - Click on File->Import, select General->'Existing Projects into Workspace' 
+   and then click "Next". 
+ - Browse to the TrueSTUDIO workspace directory and select the project: 
+   - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices.
+ - Under Windows->Preferences->General->Workspace->Linked Resources, add 
+   a variable path named "CurPath" which points to the folder containing
+   "Libraries", "Project" and "Utilities" folders.
+ - Rebuild all project files: Select the project in the "Project explorer" 
+   window then click on Project->build project menu.
+ - Run program: Select the project in the "Project explorer" window then click 
+   Run->Debug (F11)
+
+@note
+ - Low-density Value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 32 and 128 Kbytes.  
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
+ - High-density Value line devices are STM32F100xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
new file mode 100644
index 0000000..ecf6646
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of 96K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes : { *(.ARM.attributes) } > FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt
index 90e46d2..90e46d2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/note.txt
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld
index 1431182..1431182 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/TrueSTUDIO/stm32f10x_flash_extsram.ld
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/main.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/main.c
new file mode 100644
index 0000000..350eaa5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/main.c
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    Project/STM32F10x_StdPeriph_Template/main.c 
+  * @author  MCD Application Team
+  * @version V3.5.0
+  * @date    08-April-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */  
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "stm32_eval.h"
+#include <stdio.h>
+
+#ifdef USE_STM32100B_EVAL
+ #include "stm32100b_eval_lcd.h"
+#elif defined USE_STM3210B_EVAL
+ #include "stm3210b_eval_lcd.h"
+#elif defined USE_STM3210E_EVAL
+ #include "stm3210e_eval_lcd.h" 
+#elif defined USE_STM3210C_EVAL
+ #include "stm3210c_eval_lcd.h"
+#elif defined USE_STM32100E_EVAL
+ #include "stm32100e_eval_lcd.h"
+#endif
+
+/** @addtogroup STM32F10x_StdPeriph_Template
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#ifdef USE_STM32100B_EVAL
+  #define MESSAGE1   "STM32 MD Value Line " 
+  #define MESSAGE2   " Device running on  " 
+  #define MESSAGE3   "  STM32100B-EVAL    " 
+#elif defined (USE_STM3210B_EVAL)
+  #define MESSAGE1   "STM32 Medium Density" 
+  #define MESSAGE2   " Device running on  " 
+  #define MESSAGE3   "   STM3210B-EVAL    " 
+#elif defined (STM32F10X_XL) && defined (USE_STM3210E_EVAL)
+  #define MESSAGE1   "  STM32 XL Density  " 
+  #define MESSAGE2   " Device running on  " 
+  #define MESSAGE3   "   STM3210E-EVAL    "
+#elif defined (USE_STM3210E_EVAL)
+  #define MESSAGE1   " STM32 High Density " 
+  #define MESSAGE2   " Device running on  " 
+  #define MESSAGE3   "   STM3210E-EVAL    " 
+#elif defined (USE_STM3210C_EVAL)
+  #define MESSAGE1   " STM32 Connectivity " 
+  #define MESSAGE2   " Line Device running" 
+  #define MESSAGE3   " on STM3210C-EVAL   "
+#elif defined (USE_STM32100E_EVAL)
+  #define MESSAGE1   "STM32 HD Value Line " 
+  #define MESSAGE2   " Device running on  " 
+  #define MESSAGE3   "  STM32100E-EVAL    "   
+#endif
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ USART_InitTypeDef USART_InitStructure;
+
+/* Private function prototypes -----------------------------------------------*/
+#ifdef __GNUC__
+/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
+   set to 'Yes') calls __io_putchar() */
+#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
+#else
+#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */     
+
+  /* Initialize LEDs, Key Button, LCD and COM port(USART) available on
+     STM3210X-EVAL board ******************************************************/
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+
+  /* USARTx configured as follow:
+        - BaudRate = 115200 baud  
+        - Word Length = 8 Bits
+        - One Stop Bit
+        - No parity
+        - Hardware flow control disabled (RTS and CTS signals)
+        - Receive and transmit enabled
+  */
+  USART_InitStructure.USART_BaudRate = 115200;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+  STM_EVAL_COMInit(COM1, &USART_InitStructure);
+
+  /* Initialize the LCD */
+#ifdef USE_STM32100B_EVAL
+  STM32100B_LCD_Init();
+#elif defined (USE_STM3210B_EVAL)
+  STM3210B_LCD_Init();
+#elif defined (USE_STM3210E_EVAL)
+  STM3210E_LCD_Init();
+#elif defined (USE_STM3210C_EVAL)
+  STM3210C_LCD_Init();
+#elif defined (USE_STM32100E_EVAL)
+  STM32100E_LCD_Init();  
+#endif
+
+  /* Display message on STM3210X-EVAL LCD *************************************/
+  /* Clear the LCD */ 
+  LCD_Clear(LCD_COLOR_WHITE);
+
+  /* Set the LCD Back Color */
+  LCD_SetBackColor(LCD_COLOR_BLUE);
+  /* Set the LCD Text Color */
+  LCD_SetTextColor(LCD_COLOR_WHITE);
+  LCD_DisplayStringLine(LCD_LINE_0, (uint8_t *)MESSAGE1);
+  LCD_DisplayStringLine(LCD_LINE_1, (uint8_t *)MESSAGE2);
+  LCD_DisplayStringLine(LCD_LINE_2, (uint8_t *)MESSAGE3);
+
+  /* Retarget the C library printf function to the USARTx, can be USART1 or USART2
+     depending on the EVAL board you are using ********************************/
+  printf("\n\r %s", MESSAGE1);
+  printf(" %s", MESSAGE2);
+  printf(" %s\n\r", MESSAGE3);
+
+  /* Turn on leds available on STM3210X-EVAL **********************************/
+  STM_EVAL_LEDOn(LED1);
+  STM_EVAL_LEDOn(LED2);
+  STM_EVAL_LEDOn(LED3);
+  STM_EVAL_LEDOn(LED4);
+
+  /* Add your application code here
+     */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  Retargets the C library printf function to the USART.
+  * @param  None
+  * @retval None
+  */
+PUTCHAR_PROTOTYPE
+{
+  /* Place your implementation of fputc here */
+  /* e.g. write a character to the USART */
+  USART_SendData(EVAL_COM1, (uint8_t) ch);
+
+  /* Loop until the end of transmission */
+  while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
+  {}
+
+  return ch;
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
index d6875a3..d6875a3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/system_stm32f10x.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html
index bb906bc..bb906bc 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Release_Notes.html
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c
index 2db762e..2db762e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h
new file mode 100644
index 0000000..67b4689
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_tsensor.h
@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eval_i2c_tsensor.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32_eval_i2c_tsensor firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_I2C_TSENSOR_H
+#define __STM32_EVAL_I2C_TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL_I2C_TSENSOR
+  * @{
+  */  
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Types
+  * @{
+  */
+   
+ /** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  LM75_DMA_TX = 0,
+  LM75_DMA_RX = 1
+}LM75_DMADirection_TypeDef;
+
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  LM75_OK = 0,
+  LM75_FAIL
+}LM75_Status_TypDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Constants
+  * @{
+  */ 
+    
+/* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback(). 
+   If This Callback is enabled, it should be implemented by user in main function .
+   LM75_TimeoutUserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_TIMEOUT_USER_CALLBACK */    
+    
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define LM75_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define LM75_LONG_TIMEOUT         ((uint32_t)(10 * LM75_FLAG_TIMEOUT))    
+    
+
+/**
+  * @brief  Block Size
+  */
+#define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
+#define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
+#define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
+#define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
+#define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
+#define LM75_ADDR           0x90   /*!< LM75 address */
+#define LM75_I2C_SPEED      100000 /*!< I2C Speed */
+  
+   
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32_EVAL_I2C_TSENSOR_Exported_Functions
+  * @{
+  */ 
+void LM75_DeInit(void);
+void LM75_Init(void);
+ErrorStatus LM75_GetStatus(void);
+uint16_t LM75_ReadTemp(void);
+uint16_t LM75_ReadReg(uint8_t RegName);
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t LM75_ReadConfReg(void);
+uint8_t LM75_WriteConfReg(uint8_t RegValue);
+uint8_t LM75_ShutDown(FunctionalState NewState);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t LM75_TIMEOUT_UserCallback(void);
+#else
+ #define LM75_TIMEOUT_UserCallback()  LM75_FAIL
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_EVAL_I2C_TSENSOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c
index 424d2d3..424d2d3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h
index d673165..d673165 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_sdio_sd.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c
index 878144d..878144d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h
index 74a10a3..74a10a3 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_flash.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c
index f652e71..f652e71 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h
index 4a63f3a..4a63f3a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_spi_sd.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c
index 3172b63..3172b63 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h
index 4bec71a..4bec71a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_cec.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c
index bbf774d..bbf774d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h
index 638c9a0..638c9a0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval_lcd.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c
new file mode 100644
index 0000000..2e0b76d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.c
@@ -0,0 +1,1722 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_cec.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file provides all the STM32100E-EVAL HDMI-CEC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_cec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @defgroup STM32100E_EVAL_CEC
+  * @brief This file includes the CEC Stack driver for HDMI-CEC Module
+  *        of STM32100E-EVAL board.
+  * @{
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Defines
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Variables
+  * @{
+  */
+
+__IO uint32_t ReceivedFrame = 0;
+__IO uint32_t SendFrame = 0;
+__IO uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
+__IO uint8_t BufferPointer[15];
+__IO uint32_t ReceiveStatus = 0;
+__IO uint32_t SendStatus = 0;
+__IO uint8_t TransErrorCode = 0;
+__IO uint8_t RecepErrorCode = 0;
+__IO uint8_t MyLogicalAddress = 0;
+__IO uint16_t MyPhysicalAddress = 0;
+__IO uint8_t DeviceType = 0;
+#ifdef HDMI_CEC_USE_DDC
+__IO uint8_t pBuffer[256];
+__IO uint16_t NumByteToRead = 255;
+#endif
+__IO uint8_t CECDevicesNumber = 0;
+
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
+
+__IO uint8_t FeatureOpcode = 0;
+__IO uint8_t AbortReason = 0;
+__IO uint8_t DeviceCount = 0;
+
+HDMI_CEC_Map HDMI_CEC_MapStruct;
+HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
+
+/* CEC follower addresses */
+uint8_t* HDMI_CEC_Follower_String[13][2] =
+  {
+    {(uint8_t*)"         TV         ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 1  ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 2  ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 1         ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 1  ", (uint8_t*)"0"},
+    {(uint8_t*)"   Audio System     ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 2         ", (uint8_t*)"0"},
+    {(uint8_t*)"    Tuner 3         ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 2  ", (uint8_t*)"0"},
+    {(uint8_t*)"Recording Device 3  ", (uint8_t*)"0"},
+    {(uint8_t*)"      Tuner 4       ", (uint8_t*)"0"},
+    {(uint8_t*)" Playback Device 3  ", (uint8_t*)"0"},
+    {(uint8_t*)"     Broadcast      ", (uint8_t*)"1"}
+  };
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Function_Prototypes
+  * @{
+  */
+static HDMI_CEC_Error PhysicalAddressDiscovery(void);
+static HDMI_CEC_Error LogicalAddressAllocation(void);
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM32100E_EVAL_CEC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HDMI CEC.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  CEC_InitTypeDef CEC_InitStructure;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint8_t sendcount = 0;
+
+#ifdef HDMI_CEC_USE_DDC
+  I2C_InitTypeDef  I2C_InitStructure;
+  /* Enable CEC_I2C clocks */
+  RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
+
+  /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
+  RCC_APB2PeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK | HDMI_CEC_HPD_GPIO_CLK, ENABLE);
+#endif
+
+  /* Enable CEC clocks */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC, ENABLE);
+
+  /* Enable CEC_LINE_GPIO clocks */
+  RCC_APB2PeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
+
+  /* Configure CEC_LINE_GPIO as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
+
+#ifdef HDMI_CEC_USE_DDC
+  /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN | HDMI_CEC_I2C_SDA_PIN;
+  GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
+
+/* This configuration is only when the HDMI CEC is configured as source.
+   The HDMI source has to provide the +5V Power signal to the sink. 
+   On STM32100E-EVAL borad, you have to solder the SB4 Solder bridge.
+   Then, the source will wait for HPD signal to be asserted from the sink.
+   Once the HPD signal is detected the source shall read the EDID structure 
+   throuhgh the DDC channel. */
+  /* Configure CEC_HPD_GPIO as Input pull down */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
+  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
+
+
+/* This configuration is only when the HDMI CEC is configured as sink.
+   The HDMI sink has to wait for the +5V Power signal from the source. 
+   On STM32100E-EVAL borad, SB4 Solder bridge should be open (default configuration).
+   Then, the sink will assert the HPD signal to inform the source that the EDID
+   is ready for read through DDC channel. In this implementation, the EDID structure
+   is not implemented. */
+/*  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(HDMI_CEC_HPD_GPIO_PORT, &GPIO_InitStructure);
+
+  HDMI_CEC_HPD_HIGH(); // Set the Hot plug detect signal */
+  
+  /* Enable CEC_I2C */
+  I2C_Cmd(HDMI_CEC_I2C, ENABLE);
+
+  /* I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = HDMI_CEC_I2C_CLOCK_SPEED;
+  I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
+#endif
+
+  /* Physical Address discovery */
+  errorstatus = PhysicalAddressDiscovery();
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device not connected (Physical Address lost) */
+    return(errorstatus);
+  }
+
+
+  /* CEC DeInit */
+  CEC_DeInit();
+
+  /* Configure CEC */
+  CEC_InitStructure.CEC_BitTimingMode = CEC_BitTimingStdMode;
+  CEC_InitStructure.CEC_BitPeriodMode = CEC_BitPeriodStdMode;
+  CEC_Init(&CEC_InitStructure);
+
+  /* Set Prescaler value for APB1 clock = 24MHz */
+  CEC_SetPrescaler(0x4AF);
+
+  /* Enable CEC */
+  CEC_Cmd(ENABLE);
+
+  /* Logical Address Allocation */
+  sendcount = 0;
+  errorstatus = LogicalAddressAllocation();
+
+  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+  {
+    sendcount++;
+    errorstatus = LogicalAddressAllocation();
+  }
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device Unregistred */
+    return(errorstatus);
+  }
+
+  HDMI_CEC_CheckConnectedDevices();
+  
+  /* Set the CEC initiator address */
+  CEC_OwnAddressConfig(MyLogicalAddress);
+
+  /* Activate CEC interrupts associated to the set of RBTF,RERR, TBTF, TERR flags */
+  CEC_ITConfig(ENABLE);
+
+  /* Report physical address*/
+  errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  sendcount = 0;
+
+  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+  {
+    sendcount++;
+    errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  }
+
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device Unregistred */
+    return(errorstatus);
+  }
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Transmit message by taking  data from typedef struct CEC_Meassage
+  * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
+  *         the message to be sent.
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  __IO uint32_t count = 0, j = 0;
+
+  SendFrame = 0;
+  SendStatus = 0;
+  TxCounter = 0;
+  BufferCount = 0;
+
+  HDMI_CEC_TX_MessageStructPrivate =  *HDMI_CEC_TX_MessageStructure;
+
+  /* Initialize BufferPointer */
+  for (j = 0; j < 15; j++)
+  {
+    BufferPointer[j] = 0;
+  }
+
+  BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
+
+  for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
+  {
+    BufferPointer[BufferCount] =  HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount-1];
+  }
+
+  CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+  /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
+  CEC_SendDataByte(HDMI_CEC_TX_MessageStructPrivate.Header);
+
+  /* Initiate Message Transmission */
+  CEC_StartOfMessage();
+
+  while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (SendStatus == 0)
+  {
+    errorstatus = (HDMI_CEC_Error) TransErrorCode;
+  }
+
+  return errorstatus;
+}
+
+
+/**
+  * @brief  Get the ESR register status.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+
+  /* Bit timing error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_BTE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BIT_TIMING;
+  }
+  /* Bit period error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_BPE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BIT_PERIOD;
+  }
+  /* Recieve error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_RBTFE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_BLOCK_FINISHED;
+  }
+  /* Start bit error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_SBE) != RESET)
+  {
+    errorstatus = HDMI_CEC_START_BIT;
+  }
+  /* Acknowledge error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_ACKE) != RESET)
+  {
+    errorstatus = HDMI_CEC_BLOCK_ACKNOWLEDGE;
+  }
+  /* Line error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_LINE) != RESET)
+  {
+    errorstatus = HDMI_CEC_LINE;
+  }
+  /* Transfert error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_TBTFE) != RESET)
+  {
+    errorstatus = HDMI_CEC_TX_BLOCK_FINISHED;
+  }
+  /* Clear All errors */
+  CEC_ClearFlag(CEC_FLAG_RERR);
+  CEC_ClearFlag(CEC_FLAG_TERR);
+  return errorstatus;
+}
+
+/**
+  * @brief  Allows to process all the interrupts that are high.
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_ProcessIRQSrc(void)
+{
+  /********************** Reception *********************************************/
+  /* Check if a reception error occured */
+  if (CEC_GetFlagStatus(CEC_FLAG_RERR))
+  {
+    /* Set receive status bit (Error) */
+    ReceiveStatus  = 0;
+    ReceivedFrame  = 1;
+    RecepErrorCode = HDMI_CEC_GetErrorStatus();
+    CEC_ClearFlag(CEC_FLAG_RERR | CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
+  }
+  else if (CEC_GetFlagStatus(CEC_FLAG_RBTF))
+  {
+    /* Check if the byte received is the last one of the message */
+    if (CEC_GetFlagStatus(CEC_FLAG_REOM))
+    {
+      HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
+      HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter;
+      ReceiveStatus = SUCCESS;
+      ReceivedFrame = 1;
+    }
+    /* Check if the byte received is a Header */
+    else if (CEC_GetFlagStatus(CEC_FLAG_RSOM))
+    {
+      ReceiveStatus = 0;
+      HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveDataByte();
+      RxCounter = 0;
+    }
+    /* Receive each byte except header in the reception buffer */
+    else
+    {
+      if (RxCounter != 0)
+      {
+        HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-1] = CEC_ReceiveDataByte();
+        RxCounter++;
+      }
+      else
+      {
+        HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveDataByte();
+        RxCounter++;
+      }
+      
+    }
+    /* Clear all reception flags */
+    CEC_ClearFlag(CEC_FLAG_RSOM | CEC_FLAG_REOM  | CEC_FLAG_RBTF);
+  }
+
+  /********************** Transmission ******************************************/
+  /* Check if a transmission error occured */
+  if (CEC_GetFlagStatus(CEC_FLAG_TERR))
+  {
+    TransErrorCode = HDMI_CEC_GetErrorStatus();
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    SendFrame = 1;
+    SendStatus = 0;
+  }
+  /* Check if end of message bit is set in the data to be transmitted */
+  else if (CEC_GetFlagStatus(CEC_FLAG_TEOM))
+  {
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_RBTF);
+    CEC_EndOfMessageCmd(DISABLE);
+    SendFrame = 1;
+    SendStatus = SUCCESS;
+  }
+  /* Check if data byte has been sent */
+  else if (CEC_GetFlagStatus(CEC_FLAG_TBTRF))
+  {
+    /* Set EOM bit if the byte to be transmitted is the last one of the TransmitBuffer */
+    if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
+    {
+      CEC_SendDataByte(BufferPointer[TxCounter]);
+      TxCounter++;
+      CEC_ClearFlag(CEC_FLAG_TBTRF);
+      CEC_EndOfMessageCmd(ENABLE);
+    }
+    else
+    {
+      /* Put the byte in the TX Buffer */
+      CEC_SendDataByte(BufferPointer[TxCounter]);
+      TxCounter++;
+      CEC_ClearFlag(CEC_FLAG_TBTRF);
+    }
+  }
+}
+
+/**
+  * @brief  Report physical address to all other devices thus allowing any
+            device to create a map of the network.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  HDMI_CEC_Message HDMI_CEC_TX_Message;
+
+  HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
+  HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
+  HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
+  HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
+  HDMI_CEC_TX_Message.Operande[2] = DeviceType;
+  HDMI_CEC_TX_Message.TxMessageLength = 0x03;
+
+  errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
+
+  return  errorstatus;
+}
+
+/**
+  * @brief  Handle CEC command receive callback.
+  *         When receiving the STANDBY Opcode commande, the system is entred in
+  *         Stop mode and when wakeup, the PLL is configured as system clock and
+  *         the HSI is selected as PLL source.      
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_CommandCallBack(void)
+{
+  uint8_t i = 0, sendcount = 0;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  EXTI_InitTypeDef EXTI_InitStructure;
+
+  switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
+  {
+    case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
+      HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
+      HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
+      HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+      HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+      HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
+      HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t*)"1";
+      DeviceCount++;
+      break;
+
+    case HDMI_CEC_OPCODE_STANDBY:
+      /* CEC Line */
+      GPIO_EXTILineConfig(GPIO_PortSourceGPIOB, GPIO_PinSource8);
+      /* Configure the CEC Line as EXTI Line on Falling Edge */
+      EXTI_ClearITPendingBit(EXTI_Line8);
+      EXTI_InitStructure.EXTI_Line = EXTI_Line8;
+      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+      EXTI_Init(&EXTI_InitStructure);
+      /* Request to enter Stop mode */
+      PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
+
+      /* Disable the CEC EXTI Line */
+      EXTI_InitStructure.EXTI_LineCmd = DISABLE;
+      EXTI_Init(&EXTI_InitStructure);
+      /* Configure the PLL Source */
+      RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
+
+      /* Enable PLL */ 
+      RCC_PLLCmd(ENABLE);
+
+      /* Wait till PLL is ready */
+      while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+      {
+      }
+
+      /* Select PLL as system clock source */
+      RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+      /* Wait till PLL is used as system clock source */
+      while(RCC_GetSYSCLKSource() != 0x08)
+      {
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GET_CEC_VERSION:
+      /* Send the Used CEC version */
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
+      /* Send the Physical address */
+      errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_FEATURE_ABORT:
+      /* The device doesn't support the requested message type, or that it cannot
+      execute it at the present time. */
+      FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
+      AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
+      /* Send the OSD name = STM32100E CEC*/
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
+      /* STM32100E*/
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x31;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x30;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x30;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x45;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
+      /* CEC */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_ROUTING_CHANGE:
+      for (i = 0;i < 0x14;i++)
+      {
+        if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F))
+        {
+          HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+          HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+          HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
+        }
+      }
+      break;
+
+    default:
+      /* Send Abort feature*/
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* defines command to be performed */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+  }
+}
+
+/**
+  * @brief  Check the connected CEC devices.
+  * @param  None
+  * @retval HDMI_CEC_Error
+  */
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0, i = 1;
+ 
+  /*----------------------------- TV device  ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x0);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[0][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Recording device 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x1);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[1][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Recording device 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x2);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[2][1] = (uint8_t*)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x3);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Playback device 1 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x4);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Audio system ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x5);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x6);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Tuner 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x7);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Playback device 2 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x8);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  /*----------------------------- Recording device 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0x9);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Tuner 4 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0xA);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+  /*----------------------------- Playback device 3 ---------------------------*/
+  CEC_OwnAddressConfig(MyLogicalAddress); /* Own address = MyLogicalAddress */
+
+  CEC_EndOfMessageCmd(ENABLE);
+
+  CEC_SendDataByte((MyLogicalAddress << 4) | 0xB);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  errorstatus = HDMI_CEC_GetErrorStatus();
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC CSR register */
+  CEC_ClearFlag(CEC_FLAG_TBTRF);
+  CEC_EndOfMessageCmd(DISABLE);
+
+  CECDevicesNumber = i - 1;
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Physical address discovery.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error PhysicalAddressDiscovery(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+#ifdef HDMI_CEC_USE_DDC
+  uint32_t index = 0, i = 0;
+#endif
+
+  /*------------------------------ Physical address discovery -----------------*/
+  if (HDMI_CEC_ROOT == 0x1)
+  {
+    MyPhysicalAddress = 0x0000;
+    /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
+       of the +5V power signal and the HPD should be well configured.
+       Implement here the EDID Structure to be sent to the HDMI source.
+       For more details please refer to the HDMI specification. 
+       The EDID structure should be sent to the device source using the DDC Channel
+       and using the HPD signal. */
+  }
+  else
+  {
+  
+#ifdef HDMI_CEC_USE_DDC  
+    /* The HDMI-CEC here is configured as source or as a repeater. The configuration
+       of the +5V power signal and the HPD should be well configured.
+       The source should wait for HPD and then read the EDID structure. */
+    while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN) == RESET)
+    {
+    }
+    /* Wait for 100 ms after HPD was received */
+    for(i = 0; i < 0x5FFFF; i++)
+    {
+    }
+
+    /* Return the physical address using the I2C  by reading the 2 bytes 24 and
+      25 form the EDID */
+    /* Read the EDID Block 0 and EDID Block 1 at address 0xA0 */
+    /*!< While the bus is busy */
+    while(I2C_GetFlagStatus(HDMI_CEC_I2C, I2C_FLAG_BUSY))
+    {
+    }
+  
+    /*!< Send START condition */
+    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
+  
+    /*!< Test on EV5 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+    {
+    }
+   
+    /*!< Send EEPROM address for write */
+    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA0, I2C_Direction_Transmitter);
+ 
+
+    /*!< Test on EV6 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+    {
+    }
+
+    /*!< Send the EEPROM's internal address to read from: Only one byte address */
+    I2C_SendData(HDMI_CEC_I2C, 0x00);  
+
+    /*!< Test on EV8 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+    {
+    }
+  
+    /*!< Send STRAT condition a second time */  
+    I2C_GenerateSTART(HDMI_CEC_I2C, ENABLE);
+  
+    /*!< Test on EV5 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+    {
+    }
+  
+    /*!< Send EEPROM address for read */
+    I2C_Send7bitAddress(HDMI_CEC_I2C, 0xA1, I2C_Direction_Receiver);
+  
+    /*!< Test on EV6 and clear it */
+    while(!I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+    {
+    }
+
+    /* While there is data to be read */
+    while (NumByteToRead-- > 1)
+    {
+      while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
+      {
+      }
+      for(i = 0; i < 0xFFF; i++)
+      {
+      }
+      pBuffer[index++] = I2C_ReceiveData(HDMI_CEC_I2C);
+    }
+
+    /* Disable Acknowledgement */
+    I2C_AcknowledgeConfig(HDMI_CEC_I2C, DISABLE);
+
+    /* Send STOP Condition */
+    I2C_GenerateSTOP(HDMI_CEC_I2C, ENABLE);
+
+    while(I2C_CheckEvent(HDMI_CEC_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED));
+    pBuffer[index] = I2C_ReceiveData(HDMI_CEC_I2C);
+
+    /* Enable Acknowledgement to be ready for another reception */
+    I2C_AcknowledgeConfig(HDMI_CEC_I2C, ENABLE);
+    MyPhysicalAddress = ((pBuffer[138] << 8) | pBuffer[137]);
+#else
+    MyPhysicalAddress = 0x1000;
+#endif
+  }
+
+  return errorstatus;
+}
+/**
+  * @brief  Allocate the logical address.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error LogicalAddressAllocation(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0;
+
+  /*------------------ Logical address allocation -----------------------------*/
+  /* Get the device type */
+  /* Device type = CEC_TV */
+  if (DeviceType == HDMI_CEC_TV)
+  {
+    if (HDMI_CEC_ROOT)
+    {
+      MyLogicalAddress = 0x00;
+    }
+    else
+    {
+      CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0xEE);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      /* Wait till the polling message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x0E;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        MyLogicalAddress = 0x0F;
+        errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_RECORDING */
+  if (DeviceType == HDMI_CEC_RECORDING)
+  {
+    CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x11);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x01;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x22);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x02;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0x99);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x09;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_TUNER */
+  if (DeviceType == HDMI_CEC_TUNER)
+  {
+    CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x33);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x03;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x66);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x06;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0x77);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x07;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          /* Clear CEC CSR register */
+          CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+          CEC_EndOfMessageCmd(DISABLE);
+
+          CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
+
+          CEC_EndOfMessageCmd(ENABLE);
+
+          CEC_SendDataByte(0xAA);
+
+          /* Start of message */
+          CEC_StartOfMessage();
+
+          count = 0;
+
+          /* Wait till the header message is sent */
+          while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+          {
+            count++;
+          }
+
+          if (count >= HDMI_CEC_TIMEOUT_VALUE)
+          {
+            errorstatus = HDMI_CEC_TIMEOUT;
+            return(errorstatus);
+          }
+          errorstatus = HDMI_CEC_GetErrorStatus();
+
+          if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+          {
+            MyLogicalAddress = 0x0A;
+            errorstatus = HDMI_CEC_OK;
+          }
+          else if (errorstatus == HDMI_CEC_OK)
+          {
+            MyLogicalAddress = 0x0F;
+            errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+          }
+        }
+      }
+    }
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC_PLAYBACK */
+  if (DeviceType == HDMI_CEC_PLAYBACK)
+  {
+    CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x44);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x04;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC CSR register */
+      CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+      CEC_EndOfMessageCmd(DISABLE);
+
+      CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
+
+      CEC_EndOfMessageCmd(ENABLE);
+
+      CEC_SendDataByte(0x88);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x08;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC CSR register */
+        CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+
+        CEC_EndOfMessageCmd(DISABLE);
+
+        CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
+
+        CEC_EndOfMessageCmd(ENABLE);
+
+        CEC_SendDataByte(0xBB);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x0B;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  /* Device type = CEC Audio System */
+  if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
+  {
+    CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
+
+    CEC_EndOfMessageCmd(ENABLE);
+
+    CEC_SendDataByte(0x55);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TBTRF) == RESET) && (CEC_GetFlagStatus(CEC_FLAG_TERR) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_BLOCK_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x05;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      MyLogicalAddress = 0x0F;
+      errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+    }
+
+    /* Clear CEC CSR register */
+    CEC_ClearFlag(CEC_FLAG_TBTRF | CEC_FLAG_TERR);
+    CEC_EndOfMessageCmd(DISABLE);
+  }
+
+  return errorstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
+
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h
new file mode 100644
index 0000000..a899acf
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_cec.h
@@ -0,0 +1,290 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_cec.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the stm32100e_eval_cec
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_CEC_H
+#define __STM32100E_EVAL_CEC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */  
+
+/** @defgroup STM32100E_EVAL_CEC
+  * @{
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Types
+  * @{
+  */
+typedef enum
+{
+  HDMI_CEC_BIT_TIMING              = (1), /*!< CEC Bit Timing Error */
+  HDMI_CEC_BIT_PERIOD              = (2), /*!< CEC Bit Period Error */
+  HDMI_CEC_RX_BLOCK_FINISHED       = (3), /*!< CEC Receive Block finished Error */
+  HDMI_CEC_START_BIT               = (4), /*!< CEC Start Bit Error */
+  HDMI_CEC_BLOCK_ACKNOWLEDGE       = (5), /*!< CEC Block Acknowledge Error */
+  HDMI_CEC_LINE                    = (6), /*!< CEC Line Error */
+  HDMI_CEC_TX_BLOCK_FINISHED       = (7), /*!< CEC Transmit Block Transfer finished Error */
+  HDMI_CEC_DEVICE_UNREGISTRED      = (8), /*!< CEC Device Unregistred */
+  HDMI_CEC_TIMEOUT                 = (9), /*!< CEC TimeOut */
+  HDMI_CEC_OK                      = (10)  /*!< CEC OK */
+}HDMI_CEC_Error;
+
+typedef struct
+{
+  __IO uint8_t PhysicalAddress_A;
+  __IO uint8_t PhysicalAddress_B;
+  __IO uint8_t PhysicalAddress_C;
+  __IO uint8_t PhysicalAddress_D;
+  __IO uint8_t LogicalAddress;
+  __IO uint8_t DeviceType;
+}HDMI_CEC_Map;
+
+
+#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
+#define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
+
+/**
+* @brief  CEC Init Structure definition
+*/
+typedef struct
+{
+  __IO uint8_t Header;
+  __IO uint8_t Opcode;
+  __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
+  __IO uint8_t TxMessageLength;
+  __IO uint8_t RxMessageLength;
+}HDMI_CEC_Message;
+
+/**
+* @}
+*/
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @brief CEC device types
+  */
+#define HDMI_CEC_TV                                         0x00
+#define HDMI_CEC_RECORDING                                  0x01
+#define HDMI_CEC_TUNER                                      0x03
+#define HDMI_CEC_PLAYBACK                                   0x04
+#define HDMI_CEC_AUDIOSYSTEM                                0x05
+
+
+/**
+  * @brief  HDMI CEC I2C Interface pins
+  */
+#define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_6
+#define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_7
+#define HDMI_CEC_I2C_GPIO_PORT                              GPIOB
+#define HDMI_CEC_I2C_GPIO_CLK                               RCC_APB2Periph_GPIOB
+#define HDMI_CEC_I2C                                        I2C1
+#define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C1
+
+/**
+  * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
+  */
+#define HDMI_CEC_HPD_PIN                                    GPIO_Pin_9
+#define HDMI_CEC_HPD_GPIO_PORT                              GPIOB
+#define HDMI_CEC_HPD_GPIO_CLK                               RCC_APB2Periph_GPIOB
+
+/**
+  * @brief  HDMI CEC Interface pin
+  */
+#define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
+#define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
+#define HDMI_CEC_LINE_GPIO_CLK                              RCC_APB2Periph_GPIOB
+
+#define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
+#define HDMI_CEC_I2C_CLOCK_SPEED                            100000
+
+/**
+  * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
+  *         If you want to configure the STM32100E-EVAL board as CEC Root (Sink)
+  *         change the following define to 0x1    
+  */
+#define HDMI_CEC_ROOT                                       0x00
+
+/**
+  * @brief  To select if the DDC Channel will be used for physical address discovery
+  *         or not. To use the DDC Channel to read the EDID structure uncomment
+  *         the following line.   
+  *         If the device is configured as HMDI source it should read his own physical
+  *         address from the sink that is connected to.         
+  */
+/* #define HDMI_CEC_USE_DDC */                                    
+
+/**
+  * @brief  CEC version: V1.3a
+  */
+#define HDMI_CEC_VERSION                                    0x04
+
+/**
+  * @brief  Reason for Abort feature
+  */
+#define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
+#define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
+#define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
+#define HDMI_CEC_INVALID_OPERAND                            0x03
+#define HDMI_CEC_REFUSED                                    0x04
+
+/**
+  * @brief  HDMI CEC specific commands
+  */
+#define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
+#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
+#define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
+#define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
+#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
+#define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
+#define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
+#define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
+#define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
+#define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
+#define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
+#define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
+#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
+#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
+#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
+#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
+#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
+#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
+#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
+#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
+#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
+#define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
+#define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
+#define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
+#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
+#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
+#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
+#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
+#define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
+#define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
+#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
+#define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
+#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
+#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
+#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
+#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
+#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
+#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
+#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
+#define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
+#define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
+#define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
+#define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
+#define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
+#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
+#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
+#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
+#define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
+#define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
+#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
+#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
+#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
+#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
+#define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Macros
+  * @{
+  */
+/* HDMI_CEC_HPD: HDMI HPD pin low  */
+#define HDMI_CEC_HPD_LOW()       GPIO_ResetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
+/* HDMI_CEC_HPD: HDMI HPD pin high  */
+#define HDMI_CEC_HPD_HIGH()      GPIO_SetBits(HDMI_CEC_HPD_GPIO_PORT, HDMI_CEC_HPD_PIN)
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32100E_EVAL_CEC_Exported_Functions
+  * @{
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void);
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
+void HDMI_CEC_ProcessIRQSrc(void);
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
+void HDMI_CEC_CommandCallBack(void);
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32100E_EVAL_CEC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c
new file mode 100644
index 0000000..735827b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.c
@@ -0,0 +1,482 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_fsmc_onenand.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file provides a set of functions needed to drive the
+  *          KFG1216U2A/B-DIB6 OneNAND memory mounted on STM32100E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_fsmc_onenand.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32100E_EVAL_FSMC_ONENAND
+  * @brief      This file provides a set of functions needed to drive the
+  *             KFG1216x2A-xxB5 OneNAND memory mounted on STM32100E-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Defines
+  * @{
+  */ 
+#define BANK1_ONENAND1_ADDR           ((uint32_t)0x60000000)
+#define ONENAND_BOOTPARTITION_ADDR    ((uint32_t)BANK1_ONENAND1_ADDR)
+
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Macros
+  * @{
+  */
+#define OneNAND_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
+  
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the OneNAND memory.
+  *         This function must be called before any write/read operation on the 
+  *         OneNAND.
+  * @param  None
+  * @retval None
+  */
+void OneNAND_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); 
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /* OneNAND Data lines configuration */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /*!< OneNAND Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+  
+  /*!< OneNAND Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | 
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+     
+  /*!< CLK, NOE and NWE configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 |GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  
+  /*!< NE1 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /*!< NL configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; 
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+  GPIO_PinRemapConfig(GPIO_Remap_FSMC_NADV, DISABLE);
+
+  /*!< NWAIT configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+    
+  /*-- FSMC Configuration ----------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0x01;
+  p.FSMC_AddressHoldTime = 0x00;
+  p.FSMC_DataSetupTime = 0x05;
+  p.FSMC_BusTurnAroundDuration = 0x02;
+  p.FSMC_CLKDivision = 0x1;
+  p.FSMC_DataLatency = 0x01;
+  p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;	
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE); 
+}
+
+/**
+  * @brief  Resets the OneNAND memory.
+  * @param  None
+  * @retval None
+  */
+void OneNAND_Reset(void)
+{
+  OneNAND_WRITE(ONENAND_BOOTPARTITION_ADDR, OneNAND_CMD_RESET);
+}
+
+/**
+  * @brief  Reads OneNAND memory's Manufacturer and Device Code.
+  * @param  OneNAND_ID: pointer to a OneNAND_IDTypeDef structure which will hold
+  *         the Manufacturer and Device Code.  
+  * @retval None
+  */
+void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID)
+{
+  uint16_t status = 0x0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  /* Read ID data */
+  OneNAND_ID->Manufacturer_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_MANUFACTERID);
+  OneNAND_ID->Device_ID = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_DEVICEID);
+
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION) = 0x40E0;
+}
+
+/**
+  * @brief  Unlocks the specified OneNAND memory block (128Kb).
+  * @param  BlockNumber: specifies the block number to be erased. This parameter
+  *         should be between 0 and 511.
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber)
+{
+  uint16_t  status = 0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBLOCKADDRESS) = BlockNumber;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_UNLOCK;
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Erases the specified OneNAND memory block (128Kb).
+  * @param  BlockNumber: specifies the block number to be erased. This parameter
+  *         should be between 0 and 511.
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_EraseBlock(uint32_t BlockNumber)
+{
+  uint16_t status = 0x0;
+  
+  /* Wait till no ongoing operation */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x8000) == 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+
+  /* Erase operation */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = BlockNumber;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_ERASE;
+
+  /* Wait till no error is generated */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  while((status & 0x0400) == 0x0400)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  }
+  
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Writes a Half-word buffer to the OneNAND memory. 
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: OneNAND memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of half-words to write. 
+  * @retval OneNAND memory Controller Status.
+  */
+uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite)
+{
+  uint32_t datacounter = 0;
+  uint16_t status = 0;
+
+  /* Load the buffer to be written into the DATA RAM0*/ 
+  for(datacounter = 0; datacounter < NumHalfwordToWrite; datacounter++)
+  {
+    *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_0_0_ADD) + (2*datacounter)) = pBuffer[datacounter];
+  } 
+
+  /* Write operation from DATA RAM0 to NAND address*/ 
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);  /* NAND Flash start page address */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_0_0_REG;/* BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_PROGRAM; /* Command */ 
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Wait till the write interrupt is set */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x40) != 0x40)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Get the Controller Status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+  
+  return (status);
+}
+
+/**
+  * @brief  Reads a block of data from the OneNAND memory using asynchronous mode.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         OneNAND memory.
+  * @param  ReadAddr: OneNAND memory internal address to read from.
+  * @param  NumHalfwordToRead: number of half-words to read.
+  * @retval None
+  */
+void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
+{
+  uint16_t datatmp = 0x0, index = 0;
+  uint16_t status = 0;
+
+  datatmp = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION); 
+
+  /* Set the asynchronous read mode */
+  OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, (datatmp& 0x7FFF));
+
+  /* Load data from the read address to the DATA RAM 1 setor 1 */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Read Controller status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+
+  /* Read data */
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
+  {
+    /* Read a Halfword from the memory */
+    *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD)+ 2*index);
+    index++;
+  } 
+}
+
+/**
+  * @brief  Reads a block of data from the OneNAND memory using synchronous mode.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         OneNAND memory.
+  * @param  ReadAddr: OneNAND memory internal address to read from.
+  * @param  NumHalfwordToRead: number of half-words to read.
+  * @retval None
+  */
+void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead)
+{
+  uint16_t index = 0;
+  uint16_t status = 0;
+
+  /* Set the asynchronous read mode */
+  OneNAND_WRITE(BANK1_ONENAND1_ADDR + OneNAND_REG_SYSTEMCONFIGURATION, 0xB4C0);
+  
+
+  /* Load data from the read address to the DATA RAM 1 setor 1 */
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESS1) = Address.Block; /* NAND Flash block address*/
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTADDRESINT8_T) = (uint16_t)(Address.Page << 2);
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_STARTBUFFER) = OneNAND_DATA_RAM_1_0_REG;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT) = 0x0000;
+  *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_COMMAND) = OneNAND_CMD_LOAD; /* Command */
+
+  /* Wait till the command is completed */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+
+  while((status & 0x8000) != 0x8000)
+  {
+    status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT);
+  }
+
+  /* Read Controller status */
+  status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS);
+
+  /* Read data */
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* While there is data to read */
+  {
+   *pBuffer++ = *(__IO uint16_t *)((BANK1_ONENAND1_ADDR + OneNAND_DATA_RAM_1_0_ADD + 2*index));
+    index++;
+  }
+}
+
+/**
+  * @brief  Reads the OneNAND memory Interrupt status. 
+  * @param  None
+  * @retval OneNAND memory Interrupt Status.
+  */
+uint16_t OneNAND_ReadStatus(void)
+{
+  __IO uint16_t status = 0x0;
+
+  /* Read Status */
+  return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_INTERRUPT));
+}
+
+/**
+  * @brief  Reads the OneNAND Controller status. 
+  * @param  None
+  * @retval OneNAND Controller Status.
+  */
+uint16_t OneNAND_ReadControllerStatus(void)
+{
+  __IO uint16_t status = 0x0;
+
+  /* Read Controller Status */
+  return (status = *(__IO uint16_t *)(BANK1_ONENAND1_ADDR + OneNAND_REG_CONTROLSTATUS));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h
new file mode 100644
index 0000000..3e4340d
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_onenand.h
@@ -0,0 +1,189 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_fsmc_onenand.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32100e_eval_fsmc_onenand firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+   
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_FSMC_ONENAND_H
+#define __STM32100E_EVAL_FSMC_ONENAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32100E_EVAL_FSMC_ONENAND
+  * @{
+  */  
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Types
+  * @{
+  */
+typedef struct
+{
+  uint16_t Manufacturer_ID;
+  uint16_t Device_ID;
+}OneNAND_IDTypeDef;
+
+/* OneNand Status */
+typedef enum
+{
+  OneNAND_SUCCESS = 0,
+  OneNAND_ONGOING,
+  OneNAND_ERROR,
+  OneNAND_TIMEOUT
+}OneNAND_Status;
+
+typedef struct 
+{
+  uint16_t Block;
+  uint16_t Page;
+} OneNAND_ADDRESS; 
+/**
+  * @}
+  */
+  
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Constants
+  * @{
+  */
+/** 
+  * @brief  OneNAND memory command  
+  */  
+#define OneNAND_CMD_ERASE                    ((uint16_t)0x0094)
+#define OneNAND_CMD_PROGRAM                  ((uint16_t)0x0080)
+#define OneNAND_CMD_RESET                    ((uint16_t)0x00F0)
+#define OneNAND_CMD_READ_ID                  ((uint16_t)0x0090)
+#define OneNAND_CMD_UNLOCK                   ((uint16_t)0x0023)
+#define OneNAND_CMD_LOAD                     ((uint16_t)0x0000)
+
+/** 
+  * @brief OneNand Register description  
+  */  
+#define OneNAND_REG_MANUFACTERID             ((uint32_t)0x1E000) /* Manufacturer identification */
+#define OneNAND_REG_DEVICEID                 ((uint32_t)0x1E002) /* Device identification */
+#define OneNAND_REG_DATABUFFERSIZE           ((uint32_t)0x1E006) /* Data Buffer size */
+#define OneNAND_REG_BOOTBUFFERSIZE           ((uint32_t)0x1E008) /* Boot Buffer size */
+#define OneNAND_REG_AMOUNTOFBUFFERS          ((uint32_t)0x1E00A) /* Amount of data/boot buffers */
+#define OneNAND_REG_TECHNOLOGY               ((uint32_t)0x1E00C) /* Info about technology */
+#define OneNAND_REG_STARTADDRESS1            ((uint32_t)0x1E200) /* Nand Flash Block Address */
+#define OneNAND_REG_STARTADDRESS3            ((uint32_t)0x1E204) /* Destination Block address for copy back program */
+#define OneNAND_REG_STARTADDRESS4            ((uint32_t)0x1E206) /* Destination Page & sector address for copy back program */
+#define OneNAND_REG_STARTADDRESINT8_T        ((uint32_t)0x1E20E) /* Nand Flash Page & sector address */
+#define OneNAND_REG_STARTBUFFER              ((uint32_t)0x1E400) /* The meaning is with which buffer to start and how many
+                                                                     buffers to use for the data transfer */
+#define OneNAND_REG_COMMAND                  ((uint32_t)0x1E440) /* Host control and memory operation commands*/
+#define OneNAND_REG_SYSTEMCONFIGURATION      ((uint32_t)0x1E442) /* Memory and host interface configuration */
+#define OneNAND_REG_CONTROLSTATUS            ((uint32_t)0x1E480) /* Control status and result of memory operation */
+#define OneNAND_REG_INTERRUPT                ((uint32_t)0x1E482) /* Memory Command Completion Interrupt Status */
+#define OneNAND_REG_STARTBLOCKADDRESS        ((uint32_t)0x1E498) /* Start memory block address in Write Protection mode */
+#define OneNAND_REG_WRITEPROTECTIONSTATUS    ((uint32_t)0x1E49C) /* Current memory Write Protection status */
+
+/** 
+  * @brief OneNand Memory partition description  
+  */
+#define OneNAND_DATA_RAM_0_0_ADD            ((uint32_t)0x0400) /* DataRAM Main page0/sector0 */
+#define OneNAND_DATA_RAM_0_0_REG            ((uint32_t)0x0800) /* DataRAM 0_0 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_1_ADD            ((uint32_t)0x0600) /* DataRAM Main page0/sector1 */
+#define OneNAND_DATA_RAM_0_1_REG            ((uint32_t)0x0900) /* DataRAM 0_1 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_2_ADD            ((uint32_t)0x0800) /* DataRAM Main page0/sector2 */
+#define OneNAND_DATA_RAM_0_2_REG            ((uint32_t)0x0A00) /* DataRAM 0_2 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_0_3_ADD            ((uint32_t)0x0A00) /* DataRAM Main page0/sector3 */
+#define OneNAND_DATA_RAM_0_3_REG            ((uint32_t)0x0B00) /* DataRAM 0_3 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_0_ADD            ((uint32_t)0x0C00) /* DataRAM Main page1/sector0 */
+#define OneNAND_DATA_RAM_1_0_REG            ((uint32_t)0x0C00) /* DataRAM 1_0 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_1_ADD            ((uint32_t)0x0E00) /* DataRAM Main page1/sector1 */
+#define OneNAND_DATA_RAM_1_1_REG            ((uint32_t)0x0D00) /* DataRAM 1_1 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_2_ADD            ((uint32_t)0x1000) /* DataRAM Main page1/sector2 */
+#define OneNAND_DATA_RAM_1_2_REG            ((uint32_t)0x0E00) /* DataRAM 1_2 is selected with 4 sector */
+
+#define OneNAND_DATA_RAM_1_3_ADD            ((uint32_t)0x1200) /* DataRAM Main page1/sector3 */
+#define OneNAND_DATA_RAM_1_3_REG            ((uint32_t)0x0F00) /* DataRAM 1_3 is selected with 4 sector */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_FSMC_ONENAND_Exported_Functions
+  * @{
+  */ 
+void OneNAND_Init(void);
+void OneNAND_Reset(void);
+void OneNAND_ReadID(OneNAND_IDTypeDef* OneNAND_ID);
+uint16_t OneNAND_UnlockBlock(uint32_t BlockNumber);
+uint16_t OneNAND_EraseBlock(uint32_t BlockNumber);
+uint16_t OneNAND_WriteBuffer(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToWrite);
+void OneNAND_AsynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
+void OneNAND_SynchronousRead(uint16_t* pBuffer, OneNAND_ADDRESS Address, uint32_t NumHalfwordToRead);
+uint16_t OneNAND_ReadStatus(void);
+uint16_t OneNAND_ReadControllerStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32100E_EVAL_FSMC_ONENAND_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c
new file mode 100644
index 0000000..e45fc96
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.c
@@ -0,0 +1,1405 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_ioe.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file includes the IO Expander driver for STMPE811 IO Expander 
+  *          devices.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+  
+    Note:
+    -----
+    - This driver uses the DMA method for sending and receiving data on I2C bus
+      which allow higher efficiency and reliability of the communication.
+    
+    SUPPORTED FEATURES:
+      - Touch Screen Features: Single point mode (Polling/Interrupt).     
+      - TempSensor Feature: accuracy not determined (Polling).
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt).
+      
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
+      - Joystick: config and Read (Polling/Interrupt)     
+  ----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32100e_eval_ioe.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+    
+/** @defgroup STM32100E_EVAL_IOE 
+  * @brief  This file includes the IO Expander driver for STMPE811 IO Expander 
+  *         devices.
+  * @{
+  */   
+
+/** @defgroup STM32100E_EVAL_IOE_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Defines
+  * @{
+  */ 
+#define TIMEOUT_MAX    0x1000 /*<! The value of the maximal timeout for I2C waiting loops */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Variables
+  * @{
+  */ 
+TS_STATE TS_State;              /*<! The global structure holding the TS state */
+
+uint32_t IOE_TimeOut = TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_FunctionPrototypes
+  * @{
+  */ 
+static uint16_t IOE_TS_Read_X(void);
+static uint16_t IOE_TS_Read_Y(void);
+static uint16_t IOE_TS_Read_Z(void);
+
+static void IOE_GPIO_Config(void);
+static void IOE_I2C_Config(void);
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer);
+static void IOE_EXTI_Config(void);
+
+#ifndef USE_Delay
+static void delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32100E_EVAL_IOE_Private_Functions
+  * @{
+  */ 
+
+
+/**
+  * @brief  Initializes and Configures the IO_Expanders Functionalities 
+  *         (Touch Screen ..) and configures all STM32100E-EVAL necessary
+  *         hardware (GPIOs, APB clocks ..).
+  * @param  None
+  * @retval IOE_OK if all initializations done correctly. Other value if error.
+  */
+uint8_t IOE_Config(void)
+{
+  /* Configure the needed pins */
+  IOE_GPIO_Config();
+  
+  /* Configure I2C peripheral */
+  IOE_I2C_Config();
+  
+  /* Read IO Expander 1 ID  */
+  if(IOE_IsOperational(IOE_1_ADDR))
+  {
+    return IOE1_NOT_OPERATIONAL;
+  } 
+  
+  /* Generate IOExpander Software reset */
+  IOE_Reset(IOE_1_ADDR); 
+  
+  /* ---------------------- IO Expander configuration --------------------- */
+  /* Enable the GPIO, Touch Screen and ADC functionalities */
+  IOE_FnctCmd(IOE_1_ADDR, IOE_TS_FCT | IOE_ADC_FCT | IOE_IO_FCT | IOE_TEMPSENS_FCT  , ENABLE);
+   
+  /* Touch Screen controller configuration */
+  IOE_TS_Config();
+  
+  /* Temperature Sensor configuration */
+  IOE_TempSens_Config();
+ 
+  /* ------------------------------------------------------------------------ */
+  
+  /* Configuration is OK */
+  return IOE_OK; 
+}
+
+/**
+  * @brief  Configures The selected interrupts on the IO Expanders.
+  * @param  IOE_ITSRC_Source: the source of the interrupts. Could be one or a 
+  *         combination of the following parameters:
+  *   @arg  IOE_ITSRC_TSC: Touch Screen interrupts.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source)
+{   
+  /* Configure the Interrupt output pin to generate low level (INT_CTRL) */
+  IOE_ITOutConfig(Polarity_Low, Type_Level);    
+  
+  /* Manage the Touch Screen Interrupts */  
+  if (IOE_ITSRC_Source & IOE_ITSRC_TSC)
+  {   
+    /* Enable the Global interrupt */  
+    IOE_GITCmd(IOE_1_ADDR, ENABLE);     
+           
+    /* Enable the Global GPIO Interrupt */
+    IOE_GITConfig(IOE_1_ADDR, (uint8_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV), ENABLE);    
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA); 
+  }
+  
+  /* Configure the Interrupt line as EXTI source */
+  IOE_EXTI_Config();    
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Writes a bit value to an output IO pin.
+  * @param IO_Pin: The output pin to be set or reset. 
+  *                IO_Pin_x: Where x can be from 0 to 7. 
+  * @param BitVal: The value to be set. This parameter can be one of the
+  *        following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
+  * @retval IOE_OK or PARAM_ERROR
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
+{
+  uint8_t DeviceAddr = 0;
+  
+  /* Get the IO expander Address according to which pin is to be controlled */
+  if (IO_Pin & IO1_OUT_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+  else
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Apply the bit value to the selected pin */
+  if (BitVal == BitReset)
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_CLR_PIN, IO_Pin);
+  }
+  else
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_SET_PIN, IO_Pin);
+  }
+  
+  return IOE_OK;
+}
+
+
+/**
+  * @brief  Returns the status of the selected input IO pin.
+  * @param IO_Pin: The input pin to be read. 
+  *                IO_Pin_x: Where x can be from 0 to 7.
+  *   @arg  JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)  
+  * @retval None
+  */
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin)
+{
+  uint8_t DeviceAddr = 0;
+  uint8_t tmp = 0;  
+  if (IO_Pin & IO1_IN_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+   else 
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Get all the Pins status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_MP_STA);
+  if ((tmp & (uint8_t)IO_Pin) != 0)
+  {
+    return BitSet;
+  }  
+  else 
+  {
+    return BitReset;
+  }
+}
+
+
+/**
+  * @brief  Returns Status and positions of the Touch screen.
+  * @param  None
+  * @retval Pointer to TS_STATE structure holding Touch Screen information.
+  */
+TS_STATE* IOE_TS_GetState(void)
+{
+  uint32_t xDiff, yDiff , x , y;
+  static uint32_t _x = 0, _y = 0;
+  
+  /* Check if the Touch detect event happenned */
+  TS_State.TouchDetected = (I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL) & 0x80);
+  if(TS_State.TouchDetected) 
+  {
+    x = IOE_TS_Read_X();
+    y = IOE_TS_Read_Y();
+    xDiff = x > _x? (x - _x): (_x - x);
+    yDiff = y > _y? (y - _y): (_y - y);       
+    if (xDiff + yDiff > 5)
+    {
+      _x = x;
+      _y = y;       
+    }
+  }  
+  /* Update the X position */
+  TS_State.X = _x;
+    
+  /* Update the Y position */  
+  TS_State.Y = _y;
+  /* Update the Z Pression index */  
+  TS_State.Z = IOE_TS_Read_Z();  
+  
+  /* Clear the interrupt pending bit and enable the FIFO again */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* Return pointer to the updated structure */
+  return &TS_State; 
+}
+
+/**
+  * @brief  Returns the temperature row value (in 16 bit format).
+  * @param  None
+  * @retval The temperature row value.
+  */
+uint32_t IOE_TempSens_GetData(void)
+{  
+  static __IO uint32_t tmp = 0;  
+    
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x03);
+  
+  /* Enable the TEMPSENS module */
+  tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); 
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_DATA + 1); 
+  
+  tmp = (uint32_t)((33 * tmp * 100) / 751);
+  tmp = (uint32_t)((tmp + 5) / 10);
+  
+  /* return the temprature row value */
+  return tmp;
+}
+
+/**
+  * @brief  Checks the selected Global interrupt source pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Global_IT: the Global interrupt source to be checked, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt      
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  __IO uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
+  
+  if ((tmp & (uint8_t)Global_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected Global interrupt pending bit(s)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Global_IT: the Global interrupt to be cleared, could be any combination
+  *         of the following values:   
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); 
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Checks the status of the selected IO interrupt pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.             
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
+  
+  if ((tmp & (uint8_t)IO_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected IO interrupt pending bit(s).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.              
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);  
+  
+  /* Clear the Edge detection pending bit*/
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_ED, IO_IT);
+
+  /* Clear the Rising edge pending bit */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, IO_IT);
+
+  /* Clear the Falling edge pending bit */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, IO_IT); 
+
+  return IOE_OK;
+  
+}
+/**
+  * @brief  Checks if the selected device is correctly configured and 
+  *         communicates correctly ont the I2C bus.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval IOE_OK if IOE is operational. Other value if failure.
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr)
+{
+  /* Return Error if the ID is not correct */
+  if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
+  {
+    /* Check if a Timeout occured */
+    if (IOE_TimeOut == 0)
+    {
+      return(IOE_TimeoutUserCallback());
+    }
+    else
+    {
+      return IOE_FAILURE; /* ID is not Correct */
+    }
+  } 
+  else 
+  {
+    return IOE_OK; /* ID is correct */
+  }
+}
+
+/**
+  * @brief  Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_Reset(uint8_t DeviceAddr)
+{
+  /* Power Down the IO_Expander */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
+
+  /* wait for a delay to insure registers erasing */
+  _delay_(2); 
+  
+  /* Power On the Codec after the power off => all registers are reinitialized*/
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Reads the selected device's ID.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @retval The Device ID (two bytes).
+  */
+uint16_t IOE_ReadID(uint8_t DeviceAddr)
+{
+  uint16_t tmp = 0;
+
+  /* Read device ID  */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
+  tmp = (uint32_t)(tmp << 8);
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
+  
+  /* Return the ID */
+  return (uint16_t)tmp;
+}
+
+/**
+  * @brief  Configures the selcted IO Expander functionalities.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  Fct: the functions to be configured. could be any 
+  *         combination of the following values:
+  *   @arg  IOE_IO_FCT : IO function
+  *   @arg  IOE_TS_FCT : Touch Screen function
+  *   @arg  IOE_ADC_FCT : ADC function
+  *   @arg  IOE_TEMPSENS_FCT : Tempreature Sensor function
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the register value */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the Functionalities to be Enabled */    
+    tmp &= ~(uint8_t)Fct;
+  }
+  else
+  {
+    /* Set the Functionalities to be Disabled */    
+    tmp |= (uint8_t)Fct;  
+  }
+  
+  /* Set the register value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Configures the selected pin direction (to be an input or an output)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x: Where x can be from 0 to 7.   
+  * @param  Direction: could be Direction_IN or Direction_OUT.      
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
+{
+  uint8_t tmp = 0;   
+  
+  /* Get all the Pins direction */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
+  
+  if (Direction != Direction_IN)
+  {
+    tmp |= (uint8_t)IO_Pin;
+  }  
+  else 
+  {
+    tmp &= ~(uint8_t)IO_Pin;
+  }
+  
+  /* Write the register new value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;      
+}
+
+/**
+  * @brief  Enables or disables the Global interrupt.
+  * @param  DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR.
+  * @param  NewState: could be ENABLE or DISABLE.        
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Read the Interrupt Control register  */
+  I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the global interrupts to be Enabled */    
+    tmp |= (uint8_t)IOE_GIT_EN;
+  }
+  else
+  {
+    /* Set the global interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IOE_GIT_EN;
+  }  
+  
+  /* Write Back the Interrupt Control register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;     
+}
+
+/**
+  * @brief  Configures the selected source to generate or not a global interrupt
+  * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  * @param Global_IT: the interrupt source to be configured, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts  
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current value of the INT_EN register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)Global_IT;  
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)Global_IT;
+  }
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures the selected pins to generate an interrupt or not.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_IT: The IO interrupt to be configured. This parameter could be any
+  *         combination of the following values:
+  *   @arg  IO_IT_x: where x can be from 0 to 7.
+  * @param  NewState: could be ENABLE or DISABLE.  
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+ 
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)IO_IT;
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IO_IT;
+  }
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;   
+}
+
+/**
+  * @brief  Configures the touch Screen Controller (Single point detection)
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TS_Config(void)
+{
+  uint8_t tmp = 0;  
+  
+  /* Enable TSC Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); 
+  
+  /* Enable the TSC gloabl interrupts */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
+  tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); 
+  
+  /* Select Sample Time, bit number and ADC Reference */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
+  
+  /* Wait for ~20 ms */
+  _delay_(2);  
+  
+  /* Select the ADC clock speed: 3.25 MHz */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
+  
+  /* Select TSC pins in non default mode */  
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
+  tmp &= ~(uint8_t)TOUCH_IO_ALL;
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); 
+  
+  /* Select 2 nF filter capacitor */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);   
+  
+  /* Select single point reading  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
+  
+  /* Write 0x01 to clear the FIFO memory content. */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  
+  /* Write 0x00 to put the FIFO back into operation mode  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* set the data format for Z value: 7 fractional part and 1 whole part */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
+  
+  /* set the driving capability of the device for TSC pins: 50mA */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
+  
+  /* Use no tracking index, touchscreen controller operation mode (XYZ) and 
+     enable the TSC */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
+  
+  /*  Clear all the status pending bits */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); 
+  
+  /* Initialize the TS structure to their default values */ 
+  TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
+  
+  /* All configuration done */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures and enables the Temperature sensor module.
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TempSens_Config(void)
+{
+  __IO uint8_t tmp = 0;
+  
+  /* Enable Temperature Sensor Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);  
+  
+  /* Enable the TEMPSENS module */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x01);
+  
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TEMP_CTRL, 0x3);
+  
+  /* All configuration done */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the selected pin to be in Alternate function or not
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  NewState: State of the AF for the selected pin, could be 
+  *         ENABLE or DISABLE.       
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current state of the GPIO_AF register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected pins alternate function */
+    tmp |= (uint8_t)IO_Pin;
+  }
+  else
+  {
+    /* Disable the selected pins alternate function */   
+    tmp &= ~(uint8_t)IO_Pin;   
+  }
+  
+  /* Write back the new valu in GPIO_AF register */  
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);  
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Edge for which a transition is detectable for the
+  *         the selected pin.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  Edge: The edge which will be detected. This parameter can be one or a
+  *         a combination of follwing values: EDGE_FALLING and EDGE_RISING .
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
+{
+  uint8_t tmp1 = 0, tmp2 = 0;   
+  
+  /* Get the registers values */
+  tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
+  tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
+
+  /* Disable the Falling Edge */
+  tmp1 &= ~(uint8_t)IO_Pin;
+  /* Disable the Falling Edge */
+  tmp2 &= ~(uint8_t)IO_Pin;
+
+  /* Enable the Falling edge if selected */
+  if (Edge & EDGE_FALLING)
+  {
+    tmp1 |= (uint8_t)IO_Pin;
+  }
+
+  /* Enable the Rising edge if selected */
+  if (Edge & EDGE_RISING)
+  {
+    tmp2 |= (uint8_t)IO_Pin;
+  }
+
+  /* Write back the registers values */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
+  
+  /* if OK return 0 */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Interrupt line active state and format (level/edge)
+  * @param  Polarity: could be
+  *   @arg  Polarity_Low: Interrupt line is active Low/Falling edge      
+  *   @arg  Polarity_High: Interrupt line is active High/Rising edge      
+  * @param  Type: Interrupt line activity type, could be one of the following values
+  *   @arg  Type_Level: Interrupt line is active in level model         
+  *   @arg  Type_Edge: Interrupt line is active in edge model           
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
+{
+  uint8_t tmp = 0;
+  
+  /*  Get the register IOE_REG_INT_CTRL value */ 
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
+  
+  /* Mask the polarity and type bits */
+  tmp &= ~(uint8_t)0x06;
+    
+  /* Modify the Interrupt Output line configuration */
+  tmp |= (uint8_t)(Polarity | Type);
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
+    
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Writes a value in a register of the device through I2C.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR. 
+  * @param  RegisterAddr: The target register adress
+  * @param  RegisterValue: The target register value to be written 
+  * @retval IOE_OK: if all operations are OK. Other value if error.
+  */
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t read_verif = 0;  
+  uint8_t IOE_BufferTX = 0;
+  
+  /* Get Value to be written */
+  IOE_BufferTX = RegisterValue;
+  
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX));
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+   
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(IOE_I2C, RegisterAddr);
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_TX_TCFLAG);
+  
+#ifdef VERIFY_WRITTENDATA
+  /* Verify (if needed) that the loaded data is correct  */
+  
+  /* Read the just written register*/
+  read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
+  /* Load the register and verify its value  */
+  if (read_verif != RegisterValue)
+  {
+    /* Control data wrongly tranfered */
+    read_verif = IOE_FAILURE;
+  }
+  else
+  {
+    /* Control data correctly transfered */
+    read_verif = 0;
+  }
+#endif
+  
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return read_verif;
+}
+
+/**
+  * @brief  Reads a register of the device through I2C.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval The value of the read register (0xAA if Timout occured)   
+  */
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
+{
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+    
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+    
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* return a pointer to the IOE_Buffer */
+  return (uint8_t)IOE_BufferRX[0];  
+}
+
+
+/**
+  * @brief  Reads a buffer of 2 bytes from the device registers.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR.
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval A pointer to the buffer containing the two returned bytes (in halfword).  
+  */
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
+{  
+  uint8_t tmp= 0;
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+   
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* Reorganize received data */  
+  tmp = IOE_BufferRX[0];
+  IOE_BufferRX[0] = IOE_BufferRX[1];
+  IOE_BufferRX[1] = tmp;
+  
+  /* return a pointer to the IOE_Buffer */
+  return *(uint16_t *)IOE_BufferRX;  
+}
+
+/**
+  * @brief  Return Touch Screen X position value
+  * @param  None
+  * @retval X position.
+  */
+static uint16_t IOE_TS_Read_X(void)
+{
+  int32_t x, xr;
+ 
+  x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
+  
+  /* first correction */
+  xr =  (x * 320) >> 12;
+  /* second correction */
+  xr = ((xr * 32)/29) - 17;
+  
+  if(xr <= 0)
+    xr = 0;
+  
+  return (uint16_t)(xr); 
+}
+
+/**
+  * @brief  Return Touch Screen Y position value
+  * @param  None
+  * @retval Y position.
+  */
+static uint16_t IOE_TS_Read_Y(void)
+{
+  int32_t y, yr;
+  y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
+  
+  yr= (y * 240) >> 12;
+  yr = ((yr * 240) / 217) - 12;
+  
+  if(yr <= 0)
+    yr = 0;
+  
+  return (uint16_t)(yr); 
+}
+
+/**
+  * @brief  Return Touch Screen Z position value
+  * @param  None
+  * @retval Z position.
+  */
+static uint16_t IOE_TS_Read_Z(void)
+{
+  uint32_t z;
+  z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
+  
+  
+  if(z <= 0)
+    z = 0;
+  
+  return (uint16_t)(z); 
+}
+
+/**
+  * @brief  Initializes the GPIO pins used by the IO expander.
+  * @param  None
+  * @retval None
+  */
+static void IOE_GPIO_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
+  RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE);
+  RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK
+                         | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Reset IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE);
+  
+  /* Release reset signal of IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE);
+  
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN;
+  GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Set EXTI pin as Input PullUp - IO_Expander_INT */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Connect IO Expander IT line to EXTI line */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
+}
+
+
+/**
+  * @brief  Configure the I2C Peripheral used to communicate with IO_Expanders.
+  * @param  None
+  * @retval None
+  */
+static void IOE_I2C_Config(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* IOE_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
+  
+  I2C_Init(IOE_I2C, &I2C_InitStructure);
+}
+
+
+/**
+  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
+  * @param  None
+  * @retval None
+  */
+
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+  
+  RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE);
+  
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
+   /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  
+  /* If using DMA for Reception */
+  if (Direction == IOE_DMA_RX)
+  {
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 2;
+    
+    DMA_DeInit(IOE_DMA_RX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure);
+  }
+   /* If using DMA for Transmission */
+  else if (Direction == IOE_DMA_TX)
+  { 
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 1;
+    
+    DMA_DeInit(IOE_DMA_TX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure);
+  }
+}
+
+/**
+  * @brief  Configures the IO expander Interrupt line and GPIO in EXTI mode.
+  * @param  None        
+  * @retval None
+  */
+static void IOE_EXTI_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+ 
+  /* Enable Button GPIO clock */
+  RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Configure Button pin as input floating */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Connect Button EXTI Line to Button GPIO Pin */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);  
+  
+  /* Configure Button EXTI line */
+  EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;  
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Enable and set Button EXTI Interrupt to the lowest priority */
+  NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = (100000 * nCount); index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+   
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h
new file mode 100644
index 0000000..76adb3b
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_ioe.h
@@ -0,0 +1,491 @@
+/**
+  ******************************************************************************
+  * @file    stm32100e_eval_ioe.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the IO Expander
+  *   firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+    SUPPORTED FEATURES:
+      - Touch Screen Features: Single point mode (Polling/Interrupt).     
+      - TempSensor Feature: accuracy not determined (Polling).
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt).
+      
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM32100E-EVAL board)
+      - Joystick: config and Read (Polling/Interrupt) 
+----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32100E_EVAL_IOE_H
+#define __STM32100E_EVAL_IOE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32100E_EVAL
+  * @{
+  */
+    
+/** @defgroup STM32100E_EVAL_IOE 
+  * @{
+  */ 
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  Touch Screen Information structure  
+  */ 
+typedef struct
+{
+  uint16_t TouchDetected;
+  uint16_t X;
+  uint16_t Y;
+  uint16_t Z;
+}TS_STATE; 
+  
+
+/** 
+  * @brief  IO_Expander Error codes  
+  */ 
+typedef enum
+{
+  IOE_OK = 0,
+  IOE_FAILURE, 
+  IOE_TIMEOUT,
+  PARAM_ERROR,
+  IOE1_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/** 
+  * @brief  IO bit values  
+  */ 
+typedef enum
+{
+  BitReset = 0,
+  BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  IOE_DMA_TX = 0,
+  IOE_DMA_RX = 1
+}IOE_DMADirection_TypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ *        operation. The I2C_WriteDeviceRegister() function will then compare the
+ *        written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+/**
+ * @brief Uncomment the line below if you want to use user timeout callback.
+ *        Function prototypes is declared in this file but function body may be
+ *        implemented into user application.  
+ */
+/* #define USE_TIMEOUT_USER_CALLBACK */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif    
+
+/*------------------------------------------------------------------------------
+    Hardware Configuration 
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  I2C port definitions  
+  */
+#define IOE_I2C                          I2C2
+#define IOE_I2C_CLK                      RCC_APB1Periph_I2C2
+#define IOE_I2C_SCL_PIN                  GPIO_Pin_10
+#define IOE_I2C_SCL_GPIO_PORT            GPIOB
+#define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_SDA_PIN                  GPIO_Pin_11
+#define IOE_I2C_SDA_GPIO_PORT            GPIOB
+#define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_DR                       ((uint32_t)0x40005810)
+#define IOE_I2C_SPEED                    300000  
+
+/** 
+  * @brief  IOE DMA definitions  
+  */
+#define IOE_DMA                          DMA1
+#define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
+#define IOE_DMA_TX_CHANNEL               DMA1_Channel4
+#define IOE_DMA_RX_CHANNEL               DMA1_Channel5
+#define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC4
+#define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC5
+  
+
+/** 
+  * @brief  IO Expander Interrupt line on EXTI  
+  */ 
+#define IOE_IT_PIN                       GPIO_Pin_12
+#define IOE_IT_GPIO_PORT                 GPIOA
+#define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOA
+#define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOA
+#define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource12
+#define IOE_IT_EXTI_LINE                 EXTI_Line12
+#define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn       
+
+
+/** 
+  * @brief  The 7 bits IO Expanders adresses and chip IDs  
+  */ 
+#define IOE_1_ADDR                 0x82    
+#define STMPE811_ID                0x0811
+
+
+/*------------------------------------------------------------------------------
+    Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  IO Expander Functionalities definitions  
+  */ 
+#define IOE_ADC_FCT              0x01
+#define IOE_TS_FCT               0x02
+#define IOE_IO_FCT               0x04
+#define IOE_TEMPSENS_FCT         0x08
+
+/** 
+  * @brief  Interrupt source configuration definitons  
+  */ 
+#define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
+#define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 1 */
+
+/** 
+  * @brief  Glaobal Interrupts definitions  
+  */ 
+#define IOE_GIT_GPIO             0x80
+#define IOE_GIT_ADC              0x40
+#define IOE_GIT_TEMP             0x20
+#define IOE_GIT_FE               0x10
+#define IOE_GIT_FF               0x08
+#define IOE_GIT_FOV              0x04
+#define IOE_GIT_FTH              0x02
+#define IOE_GIT_TOUCH            0x01
+
+/**
+  * @brief IO Exapanders Pins definition 
+  */ 
+#define IO1_IN_ALL_PINS          (uint32_t)(IO_Pin_ALL)
+#define IO1_OUT_ALL_PINS         (uint32_t)(IO_Pin_ALL)
+
+
+/*------------------------------------------------------------------------------
+    STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  Identification registers  
+  */ 
+#define IOE_REG_CHP_ID             0x00
+#define IOE_REG_ID_VER             0x02
+
+/** 
+  * @brief  General Control Registers  
+  */ 
+#define IOE_REG_SYS_CTRL1          0x03
+#define IOE_REG_SYS_CTRL2          0x04
+#define IOE_REG_SPI_CFG            0x08 
+
+/** 
+  * @brief  Interrupt Control register  
+  */ 
+#define IOE_REG_INT_CTRL           0x09
+#define IOE_REG_INT_EN             0x0A
+#define IOE_REG_INT_STA            0x0B
+#define IOE_REG_GPIO_INT_EN        0x0C
+#define IOE_REG_GPIO_INT_STA       0x0D
+
+/** 
+  * @brief  GPIO Registers  
+  */ 
+#define IOE_REG_GPIO_SET_PIN       0x10
+#define IOE_REG_GPIO_CLR_PIN       0x11
+#define IOE_REG_GPIO_MP_STA        0x12
+#define IOE_REG_GPIO_DIR           0x13
+#define IOE_REG_GPIO_ED            0x14
+#define IOE_REG_GPIO_RE            0x15
+#define IOE_REG_GPIO_FE            0x16
+#define IOE_REG_GPIO_AF            0x17
+
+/** 
+  * @brief  ADC Registers  
+  */ 
+#define IOE_REG_ADC_INT_EN         0x0E
+#define IOE_REG_ADC_INT_STA        0x0F
+#define IOE_REG_ADC_CTRL1          0x20
+#define IOE_REG_ADC_CTRL2          0x21
+#define IOE_REG_ADC_CAPT           0x22
+#define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */ 
+
+/** 
+  * @brief  TouchScreen Registers  
+  */ 
+#define IOE_REG_TSC_CTRL           0x40
+#define IOE_REG_TSC_CFG            0x41
+#define IOE_REG_WDM_TR_X           0x42 
+#define IOE_REG_WDM_TR_Y           0x44
+#define IOE_REG_WDM_BL_X           0x46
+#define IOE_REG_WDM_BL_Y           0x48
+#define IOE_REG_FIFO_TH            0x4A
+#define IOE_REG_FIFO_STA           0x4B
+#define IOE_REG_FIFO_SIZE          0x4C
+#define IOE_REG_TSC_DATA_X         0x4D 
+#define IOE_REG_TSC_DATA_Y         0x4F
+#define IOE_REG_TSC_DATA_Z         0x51
+#define IOE_REG_TSC_DATA_XYZ       0x52 
+#define IOE_REG_TSC_FRACT_XYZ      0x56
+#define IOE_REG_TSC_DATA           0x57
+#define IOE_REG_TSC_I_DRIVE        0x58
+#define IOE_REG_TSC_SHIELD         0x59
+
+/** 
+  * @brief  Temperature Sensor registers  
+  */ 
+#define IOE_REG_TEMP_CTRL          0x60
+#define IOE_REG_TEMP_DATA          0x61
+#define IOE_REG_TEMP_TH            0x62
+
+/*------------------------------------------------------------------------------
+    Functions parameters defines
+------------------------------------------------------------------------------*/
+/**
+  * @brief Touch Screen Pins definition 
+  */ 
+#define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/** 
+  * @brief  IO Pins  
+  */ 
+#define IO_Pin_0                 0x01
+#define IO_Pin_1                 0x02
+#define IO_Pin_2                 0x04
+#define IO_Pin_3                 0x08
+#define IO_Pin_4                 0x10
+#define IO_Pin_5                 0x20
+#define IO_Pin_6                 0x40
+#define IO_Pin_7                 0x80
+#define IO_Pin_ALL               0xFF
+
+/** 
+  * @brief  IO Pin directions  
+  */ 
+#define Direction_IN             0x00
+#define Direction_OUT            0x01
+
+/** 
+  * @brief  Interrupt Line output parameters  
+  */ 
+#define Polarity_Low             0x00
+#define Polarity_High            0x04
+#define Type_Level               0x00
+#define Type_Edge                0x02
+
+/** 
+  * @brief IO Interrupts  
+  */ 
+#define IO_IT_0                  0x01
+#define IO_IT_1                  0x02
+#define IO_IT_2                  0x04
+#define IO_IT_3                  0x08
+#define IO_IT_4                  0x10
+#define IO_IT_5                  0x20
+#define IO_IT_6                  0x40
+#define IO_IT_7                  0x80
+#define ALL_IT                   0xFF
+#define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
+
+/** 
+  * @brief  Edge detection value  
+  */ 
+#define EDGE_FALLING              0x01
+#define EDGE_RISING               0x02
+
+/** 
+  * @brief  Global interrupt Enable bit  
+  */ 
+#define IOE_GIT_EN                0x01
+
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM32100E_EVAL_IOE_Exported_Functions
+  * @{
+  */ 
+
+/** 
+  * @brief  Configuration and initialization functions  
+  */
+uint8_t IOE_Config(void);
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t IOE_TimeoutUserCallback(void);
+#else
+ #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+
+/** 
+  * @brief IO pins control functions
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
+
+/** 
+  * @brief Touch Screen controller functions
+  */
+TS_STATE* IOE_TS_GetState(void);
+
+/** 
+  * @brief Interrupts Mangement functions
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+
+
+/** 
+  * @brief Temperature Sensor functions
+  */
+uint32_t IOE_TempSens_GetData(void);
+
+
+/** 
+  * @brief IO-Expander Control functions
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr);
+uint8_t IOE_Reset(uint8_t DeviceAddr);
+uint16_t IOE_ReadID(uint8_t DeviceAddr);
+
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
+
+/** 
+  * @brief Low Layer functions
+  */
+uint8_t IOE_TS_Config(void);
+uint8_t IOE_TempSens_Config(void);
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
+
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
+#ifdef __cplusplus
+}
+
+#endif
+#endif /* __STM32100E_EVAL_IOE_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */     
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c
index 947329d..80e5787 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    stm32100b_eval.c
+  * @file    stm3210b_eval.c
   * @author  MCD Application Team
   * @version V4.5.0
   * @date    07-March-2011
@@ -8,7 +8,7 @@
   *            - set of firmware functions to manage Leds, push-button and COM ports
   *            - low level initialization functions for SD card (on SPI), SPI serial
   *              flash (sFLASH) and temperature sensor (LM75)
-  *          available on STM32100B-EVAL evaluation board from STMicroelectronics. 
+  *          available on STM3210B-EVAL evaluation board from STMicroelectronics.    
   ******************************************************************************
   * @attention
   *
@@ -24,9 +24,7 @@
   */ 
   
 /* Includes ------------------------------------------------------------------*/
-#include "stm32100b_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
+#include "stm3210b_eval.h"
 
 /** @addtogroup Utilities
   * @{
@@ -36,19 +34,19 @@
   * @{
   */ 
 
-/** @addtogroup STM32100B_EVAL
+/** @addtogroup STM3210B_EVAL
   * @{
-  */
+  */ 
       
-/** @defgroup STM32100B_EVAL_LOW_LEVEL 
+/** @defgroup STM3210B_EVAL_LOW_LEVEL 
   * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SPI, serial flash (sFLASH) and temperature 
-  *        sensor (LM75) available on STM32100B-EVAL evaluation board from 
-  *        STMicroelectronics.
+  *        COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) 
+  *        and temperature sensor (LM75) available on STM3210B-EVAL evaluation
+  *        board from STMicroelectronics.
   * @{
   */ 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_TypesDefinitions
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions
   * @{
   */ 
 /**
@@ -56,7 +54,7 @@
   */ 
 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Defines
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Defines
   * @{
   */ 
 /**
@@ -64,7 +62,7 @@
   */ 
 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Macros
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Macros
   * @{
   */ 
 /**
@@ -72,7 +70,7 @@
   */ 
 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Variables
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Variables
   * @{
   */ 
 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
@@ -145,12 +143,13 @@ const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
 
 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
 
+
 /**
   * @}
   */ 
 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
   * @{
   */ 
 
@@ -159,7 +158,7 @@ const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
   */ 
 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Private_Functions
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Functions
   * @{
   */ 
 
@@ -182,9 +181,9 @@ void STM_EVAL_LEDInit(Led_TypeDef Led)
 
   /* Configure the GPIO_LED pin */
   GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
-  
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
   GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
 }
 
@@ -200,7 +199,7 @@ void STM_EVAL_LEDInit(Led_TypeDef Led)
   */
 void STM_EVAL_LEDOn(Led_TypeDef Led)
 {
-  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];   
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];     
 }
 
 /**
@@ -215,7 +214,7 @@ void STM_EVAL_LEDOn(Led_TypeDef Led)
   */
 void STM_EVAL_LEDOff(Led_TypeDef Led)
 {
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];   
+  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];  
 }
 
 /**
@@ -316,7 +315,6 @@ uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
   return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
 }
 
-
 /**
   * @brief  Configures COM port.
   * @param  COM: Specifies the COM port to be configured.
@@ -334,8 +332,6 @@ void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
   /* Enable GPIO clock */
   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
 
-
-  /* Enable UART clock */
   if (COM == COM1)
   {
     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
@@ -353,6 +349,7 @@ void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
 
+
   /* Configure USART Rx as input floating */
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
@@ -379,7 +376,7 @@ void SD_LowLevel_DeInit(void)
   
   /*!< SD_SPI Periph clock disable */
   RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); 
-
+  
   /*!< Configure SD_SPI pins: SCK */
   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@@ -453,8 +450,7 @@ void SD_LowLevel_Init(void)
   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
   SPI_InitStructure.SPI_CRCPolynomial = 7;
   SPI_Init(SD_SPI, &SPI_InitStructure);
@@ -568,7 +564,7 @@ void LM75_LowLevel_DeInit(void)
 }
 
 /**
-  * @brief  Initializes the LM75_I2C..
+  * @brief  Initializes the LM75_I2C.
   * @param  None
   * @retval None
   */
@@ -599,7 +595,7 @@ void LM75_LowLevel_Init(void)
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
 }
-
+  
 /**
   * @}
   */ 
@@ -612,13 +608,13 @@ void LM75_LowLevel_Init(void)
 /**
   * @}
   */
-
+ 
 /**
   * @}
   */  
 
 /**
   * @}
-  */ 
-     
+  */  
+    
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h
index b6c4ccb..dd5cb4b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100B_EVAL/stm32100b_eval.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h
@@ -1,12 +1,12 @@
 /**
   ******************************************************************************
-  * @file    stm32100b_eval.h
+  * @file    stm3210b_eval.h
   * @author  MCD Application Team
   * @version V4.5.0
   * @date    07-March-2011
-  * @brief   This file contains definitions for STM32100B_EVAL's Leds, push-buttons
-  *          COM ports, SD Card on SPI, sFLASH on SPI and Temperature Sensor LM75 on I2C
-  *          hardware resources.
+  * @brief   This file contains definitions for STM3210B_EVAL's Leds, push-buttons
+  *          COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor 
+  *          LM75 (on I2C) hardware resources.
   ******************************************************************************
   * @attention
   *
@@ -22,8 +22,8 @@
   */ 
   
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100B_EVAL_H
-#define __STM32100B_EVAL_H
+#ifndef __STM3210B_EVAL_H
+#define __STM3210B_EVAL_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -31,6 +31,8 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32_eval.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_i2c.h"
 
 /** @addtogroup Utilities
   * @{
@@ -38,27 +40,28 @@
 
 /** @addtogroup STM32_EVAL
   * @{
-  */ 
-
-/** @addtogroup STM32100B_EVAL
+  */
+    
+/** @addtogroup STM3210B_EVAL
   * @{
   */ 
 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL
   * @{
-  */   
-
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Types
+  */
+  
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Types
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
+
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Constants
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Constants
   * @{
   */ 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_LED
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_LED
   * @{
   */
 #define LEDn                             4
@@ -68,13 +71,13 @@
   
 #define LED2_PIN                         GPIO_Pin_7
 #define LED2_GPIO_PORT                   GPIOC
-#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC
+#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC  
 
 #define LED3_PIN                         GPIO_Pin_8  
 #define LED3_GPIO_PORT                   GPIOC
 #define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOC  
-
-#define LED4_PIN                         GPIO_Pin_9  
+  
+#define LED4_PIN                         GPIO_Pin_9
 #define LED4_GPIO_PORT                   GPIOC
 #define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOC  
 
@@ -82,7 +85,7 @@
   * @}
   */ 
   
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_BUTTON
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_BUTTON
   * @{
   */  
 #define BUTTONn                          8
@@ -120,23 +123,23 @@
 /**
  * @brief Joystick Right push-button
  */
-#define RIGHT_BUTTON_PIN                 GPIO_Pin_1
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_0
 #define RIGHT_BUTTON_GPIO_PORT           GPIOE
 #define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOE
-#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line1
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line0
 #define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOE
-#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource1
-#define RIGHT_BUTTON_EXTI_IRQn           EXTI1_IRQn
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource0
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI0_IRQn
 /**
  * @brief Joystick Left push-button
  */
-#define LEFT_BUTTON_PIN                  GPIO_Pin_0
+#define LEFT_BUTTON_PIN                  GPIO_Pin_1
 #define LEFT_BUTTON_GPIO_PORT            GPIOE
 #define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOE
-#define LEFT_BUTTON_EXTI_LINE            EXTI_Line0
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line1
 #define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOE
-#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource0
-#define LEFT_BUTTON_EXTI_IRQn            EXTI0_IRQn  
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource1
+#define LEFT_BUTTON_EXTI_IRQn            EXTI1_IRQn  
 /**
  * @brief Joystick Up push-button
  */
@@ -171,7 +174,7 @@
   * @}
   */ 
 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_COM
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_COM
   * @{
   */
 #define COMn                             2
@@ -206,7 +209,7 @@
   * @}
   */ 
 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_SD_SPI
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_SD_SPI
   * @{
   */
 /**
@@ -234,7 +237,7 @@
   * @}
   */
 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
   * @{
   */
 /**
@@ -251,15 +254,15 @@
 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_CS_PIN                    GPIO_Pin_9                  /* PD.09 */
-#define sFLASH_CS_GPIO_PORT              GPIOD                       /* GPIOD */
-#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOD
+#define sFLASH_CS_PIN                    GPIO_Pin_4                  /* PA.04 */
+#define sFLASH_CS_GPIO_PORT              GPIOA                       /* GPIOA */
+#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOA 
 
 /**
   * @}
   */
 
-/** @addtogroup STM32100B_EVAL_LOW_LEVEL_TSENSOR_I2C
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C
   * @{
   */
 /**
@@ -282,22 +285,24 @@
 #define LM75_DMA_TX_CHANNEL              DMA1_Channel6
 #define LM75_DMA_RX_CHANNEL              DMA1_Channel7
 #define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
-#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7 
+
 /**
   * @}
-  */     
+  */
+    
 /**
   * @}
   */ 
   
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Macros
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Macros
   * @{
   */ 
 /**
   * @}
   */ 
 
-/** @defgroup STM32100B_EVAL_LOW_LEVEL_Exported_Functions
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Functions
   * @{
   */ 
 void STM_EVAL_LEDInit(Led_TypeDef Led);
@@ -313,6 +318,7 @@ void sFLASH_LowLevel_DeInit(void);
 void sFLASH_LowLevel_Init(void); 
 void LM75_LowLevel_DeInit(void);
 void LM75_LowLevel_Init(void); 
+ 
 /**
   * @}
   */ 
@@ -321,7 +327,7 @@ void LM75_LowLevel_Init(void);
 }
 #endif
   
-#endif /* __STM32100B_EVAL_H */
+#endif /* __STM3210B_EVAL_H */
 /**
   * @}
   */ 
@@ -332,10 +338,10 @@ void LM75_LowLevel_Init(void);
 
 /**
   * @}
-  */
+  */  
 
 /**
   * @}
-  */  
+  */    
 
 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
index b9995a5..b9995a5 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
index 0b7577c..0b7577c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c
index b256930..b256930 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
index 469693f..469693f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c
new file mode 100644
index 0000000..6fd8136
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c
@@ -0,0 +1,1594 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval_ioe.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file includes the IO Expander driver for STMPE811 IO Expander 
+  *          devices.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+  
+    Note:
+    -----
+    - This driver uses the DMA method for sending and receiving data on I2C bus
+      which allow higher efficiency and reliability of the communication.  
+  
+    SUPPORTED FEATURES:
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+      - Joystick: config and Read (Polling/Interrupt)
+      - Touch Screen Features: Single point mode (Polling/Interrupt)
+      - TempSensor Feature: accuracy not determined (Polling).
+
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+  ----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210c_eval_ioe.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */
+    
+/** @defgroup STM3210C_EVAL_IOE 
+  * @brief  This file includes the IO Expander driver for STMPE811 IO Expander 
+  *         devices.
+  * @{
+  */   
+
+/** @defgroup STM3210C_EVAL_IOE_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Private_Defines
+  * @{
+  */ 
+#define TIMEOUT_MAX             0x1000   /*<! The value of the maximal timeout for I2C waiting loops */
+
+#define TS_CONVERSION_DELAY     0x10000  /*<! The application should wait before ADC end of conversion. 
+                                              This delay depends on the system clock frequency, the value 0x10000
+                                              is selected for system clock equal to 72 MHz. For lower frequencies
+                                              please modify the delay accordingly. */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Private_Variables
+  * @{
+  */ 
+TS_STATE TS_State;              /*<! The global structure holding the TS state */
+
+uint32_t IOE_TimeOut = TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Private_FunctionPrototypes
+  * @{
+  */ 
+static uint16_t IOE_TS_Read_X(void);
+static uint16_t IOE_TS_Read_Y(void);
+static uint16_t IOE_TS_Read_Z(void);
+
+static void IOE_GPIO_Config(void);
+static void IOE_I2C_Config(void);
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer);
+static void IOE_EXTI_Config(void);
+
+#ifndef USE_Delay
+static void delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Private_Functions
+  * @{
+  */ 
+
+
+/**
+  * @brief  Initializes and Configures the two IO_Expanders Functionalities 
+  *         (IOs, Touch Screen ..) and configures all STM3210C-EVAL necessary
+  *         hardware (GPIOs, APB clocks ..).
+  * @param  None
+  * @retval IOE_OK if all initializations done correctly. Other value if error.
+  */
+uint8_t IOE_Config(void)
+{
+  /* Configure the needed pins */
+  IOE_GPIO_Config(); 
+  
+  /* Configure the I2C peripheral */
+  IOE_I2C_Config();
+  
+  /* Read IO Expander 1 ID  */
+  if(IOE_IsOperational(IOE_1_ADDR))
+  {
+    return IOE1_NOT_OPERATIONAL;
+  }
+  if(IOE_IsOperational(IOE_2_ADDR))
+  {
+    return IOE2_NOT_OPERATIONAL;
+  }
+  
+  /* Generate IOExpander Software reset */
+  IOE_Reset(IOE_1_ADDR); 
+  IOE_Reset(IOE_2_ADDR);
+  
+  /* ---------------------- IO Expander 1 configuration --------------------- */
+  /* Enable the GPIO, Touch Screen and ADC functionalities */
+  IOE_FnctCmd(IOE_1_ADDR, IOE_IO_FCT | IOE_TS_FCT | IOE_ADC_FCT, ENABLE);
+  /* Configure the VBAT pin in output mode pin*/
+  IOE_IOPinConfig(IOE_1_ADDR, VBAT_DIV_PIN , Direction_OUT);  
+  /* ENABLE the alternate function for IN1 pin */
+  IOE_IOAFConfig(IOE_1_ADDR, VBAT_DIV_PIN, ENABLE);
+  
+  /* Apply the default state for the out pins */
+  IOE_WriteIOPin(VBAT_DIV_PIN, BitReset);
+  /* Configure the MEMS interrupt pins in Input mode */
+  IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), Direction_IN); 
+  
+  /* ENABLE the alternate function for the Joystick pins */
+  IOE_IOAFConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), ENABLE);
+  /* Configure the IOs to detect Falling and Rising Edges */
+  IOE_IOEdgeConfig(IOE_2_ADDR, (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN), (uint32_t)(EDGE_FALLING | EDGE_RISING));
+  /* Touch Screen controller configuration */
+  IOE_TS_Config();
+  
+  /* ------------------------------------------------------------------------ */
+  
+  /* ---------------------- IO Expander 2 configuration --------------------- */
+  /* Enable the GPIO, Temperature Sensor and ADC functionalities */
+  IOE_FnctCmd(IOE_2_ADDR, IOE_IO_FCT | IOE_TEMPSENS_FCT | IOE_ADC_FCT, ENABLE);
+  
+  /* Configure the Audio Codec Reset pin in output mode pin*/
+  IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(AUDIO_RESET_PIN), Direction_OUT);
+  IOE_IOPinConfig(IOE_2_ADDR, (uint32_t)(MII_INT_PIN), Direction_IN);
+      
+  /* ENABLE the alternate function for IN1 pin */
+  IOE_IOAFConfig(IOE_2_ADDR, (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN), ENABLE);
+    
+  /* Apply the default state for the out pins */
+  IOE_WriteIOPin(AUDIO_RESET_PIN, BitReset);
+  IOE_WriteIOPin(MII_INT_PIN, BitReset);
+  /* Configure the Joystick pins in Input mode */
+  IOE_IOPinConfig(IOE_2_ADDR, JOY_IO_PINS , Direction_IN); 
+  
+  /* ENABLE the alternate function for the Joystick pins */
+  IOE_IOAFConfig(IOE_2_ADDR, JOY_IO_PINS, ENABLE);
+  /* Configure the IOs to detect Falling and Rising Edges */
+  IOE_IOEdgeConfig(IOE_2_ADDR, JOY_IO_PINS, (uint8_t)(EDGE_FALLING | EDGE_RISING));
+  
+  /* Temperature Sensor module configuration */
+  IOE_TempSens_Config();
+  /* ------------------------------------------------------------------------ */
+  
+  /* Configuration is OK */
+  return IOE_OK; 
+}
+
+/**
+  * @brief  Configures The selected interrupts on the IO Expanders.
+  * @param  IOE_ITSRC_Source: the source of the interrupts. Could be one or a 
+  *         combination of the following parameters:
+  *   @arg  IOE_ITSRC_JOYSTICK: Joystick IO intputs.
+  *   @arg  IOE_ITSRC_TSC: Touch Screen interrupts.
+  *   @arg  IOE_ITSRC_INMEMS: MEMS interrupt lines.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source)
+{   
+  /* Configure the Interrupt output pin to generate low level (INT_CTRL) */
+  IOE_ITOutConfig(Polarity_High, Type_Level);  
+  
+  /* Manage the Joystick Interrupts */  
+  if (IOE_ITSRC_Source & IOE_ITSRC_JOYSTICK)
+  {   
+    /* Enable the Global interrupt */  
+    IOE_GITCmd(IOE_2_ADDR, ENABLE);     
+        
+    /* Enable the Joystick pins to generate interrupt (GPIO_INT_EN) */
+    IOE_IOITConfig(IOE_2_ADDR, IOE_JOY_IT, ENABLE);   
+    
+    /* Enable the Global GPIO Interrupt */
+    IOE_GITConfig(IOE_2_ADDR, IOE_GIT_GPIO, ENABLE);    
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_INT_STA);    
+    
+    /* Enable the Joystick pins to generate interrupt */
+    IOE_IOITConfig(IOE_2_ADDR, IOE_JOY_IT, ENABLE);  
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_INT_STA);     
+  }
+
+  /* Manage the MEMS Interrupts lines  */  
+  if (IOE_ITSRC_Source & IOE_ITSRC_INMEMS)
+  {   
+    /* Enable the Global interrupt */  
+    IOE_GITCmd(IOE_1_ADDR, ENABLE);     
+        
+    /* Enable the pins to generate interrupt (GPIO_INT_EN) */
+    IOE_IOITConfig(IOE_1_ADDR, IOE_INMEMS_IT, ENABLE);   
+    
+    /* Enable the Global GPIO Interrupt */
+    IOE_GITConfig(IOE_1_ADDR, IOE_GIT_GPIO, ENABLE);    
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);    
+    
+    /* Enable the pins to generate interrupt */
+    IOE_IOITConfig(IOE_1_ADDR, IOE_INMEMS_IT, ENABLE);  
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA);     
+  }  
+  
+  /* Manage the Touch Screen Interrupts */  
+  if (IOE_ITSRC_Source & IOE_ITSRC_TSC)
+  {   
+    /* Enable the Global interrupt */  
+    IOE_GITCmd(IOE_1_ADDR, ENABLE);     
+           
+    /* Enable the Global GPIO Interrupt */
+    IOE_GITConfig(IOE_1_ADDR, (uint8_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV), ENABLE);    
+    
+    /* Read the GPIO_IT_STA to clear all pending bits if any */
+    I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_INT_STA); 
+  }
+  
+  /* Configure the Interrupt line as EXTI source */
+  IOE_EXTI_Config();    
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Writes a bit value to an output IO pin.
+  * @param IO_Pin: The output pin to be set or reset. This parameter can be one 
+  *        of the following values:
+  *   @arg  AUDIO_RESET_PIN: Audio codec reset pin
+  *   @arg  MII_INT_PIN: Ethernet Phy MII interrupt pin
+  *   @arg  VBAT_DIV_PIN: Battery devider pin
+  * @param BitVal: The value to be set. This parameter can be one of the
+  *        following values: BitSet or BitReset. See IOE_BitVal_TypeDef.
+  * @retval IOE_OK or PARAM_ERROR
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal)
+{
+  uint8_t DeviceAddr = 0;
+  
+  /* Get the IO expander Address according to which pin is to be controlled */
+  if (IO_Pin & IO1_OUT_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+  else if (IO_Pin & IO2_OUT_ALL_PINS)
+  {
+    DeviceAddr = IOE_2_ADDR;
+  }
+  else
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Apply the bit value to the selected pin */
+  if (BitVal == BitReset)
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_CLR_PIN, IO_Pin);
+  }
+  else
+  {
+    /* Set the register */
+    I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_SET_PIN, IO_Pin);
+  }
+  
+  return IOE_OK;
+}
+
+
+/**
+  * @brief  Returns the status of the selected input IO pin.
+  * @param IO_Pin: The input pin to be read. This parameter can be one 
+  *  of the following values:
+  *   @arg  MEMS_INT1_PIN: MEMS interrupt line 1.
+  *   @arg  MEMS_INT2_PIN: MEMS interrupt line 2.
+  *   @arg  JOY_IO_PINS: Joystick IO pins (use IOE_JoyStickGetState for these pins)  
+  * @retval None
+  */
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin)
+{
+  uint8_t DeviceAddr = 0;
+  uint8_t tmp = 0;  
+  if (IO_Pin & IO1_IN_ALL_PINS)
+  {
+    DeviceAddr = IOE_1_ADDR;
+  }
+  else if (IO_Pin & IO2_IN_ALL_PINS)
+  {
+    DeviceAddr = IOE_2_ADDR;
+  }
+  else 
+  {
+    return PARAM_ERROR;
+  }
+  
+  /* Get all the Pins status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_MP_STA);
+  if ((tmp & (uint8_t)IO_Pin) != 0)
+  {
+    return BitSet;
+  }  
+  else 
+  {
+    return BitReset;
+  }
+}
+
+
+/**
+  * @brief  Returns the current Joystick status.
+  * @param  None
+  * @retval The code of the Joystick key pressed: 
+  *   @arg  JOY_NONE
+  *   @arg  JOY_SEL
+  *   @arg  JOY_DOWN
+  *   @arg  JOY_LEFT
+  *   @arg  JOY_RIGHT
+  *   @arg  JOY_UP
+  */
+JOYState_TypeDef
+ IOE_JoyStickGetState(void)
+{
+  uint8_t tmp = 0;
+  /* Read the status of all pins */
+  tmp = (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_MP_STA);
+   
+  /* Check the pressed keys */
+  if ((tmp & JOY_IO_NONE) == JOY_IO_NONE)
+  {
+    return (JOYState_TypeDef) JOY_NONE;
+  }
+  else if (!(tmp & JOY_IO_SEL))
+  {
+    return (JOYState_TypeDef) JOY_SEL;
+  }
+  else if (!(tmp & JOY_IO_DOWN))
+  {
+    return (JOYState_TypeDef) JOY_DOWN;
+  }
+  else if (!(tmp & JOY_IO_LEFT))
+  {
+    return (JOYState_TypeDef) JOY_LEFT;
+  }
+  else if (!(tmp & JOY_IO_RIGHT))
+  {
+    return (JOYState_TypeDef) JOY_RIGHT;
+  }
+  else if (!(tmp & JOY_IO_UP))
+  {
+    return (JOYState_TypeDef) JOY_UP;
+  }
+  else
+  { 
+    return (JOYState_TypeDef) JOY_NONE;
+  }
+}
+
+/**
+  * @brief  Returns Status and positions of the Touch screen.
+  * @param  None
+  * @retval Pointer to TS_STATE structure holding Touch Screen information.
+  */
+TS_STATE* IOE_TS_GetState(void)
+{
+  uint32_t xDiff, yDiff , x , y, count;
+  static uint32_t _x = 0, _y = 0;
+  
+  /* Check if the Touch detect event happenned */
+  TS_State.TouchDetected = (I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL) & 0x80);
+
+  /* Wait till end of ADC conversion */
+  for (count = TS_CONVERSION_DELAY; count > 0; count--);
+
+  if(TS_State.TouchDetected) 
+  {
+    x = IOE_TS_Read_X();
+    y = IOE_TS_Read_Y();
+    xDiff = x > _x? (x - _x): (_x - x);
+    yDiff = y > _y? (y - _y): (_y - y);       
+    if (xDiff + yDiff > 5)
+    {
+      _x = x;
+      _y = y;       
+    }
+  }  
+  /* Update the X position */
+  TS_State.X = _x;
+    
+  /* Update the Y position */  
+  TS_State.Y = _y;
+
+  /* Update the Z Pression index */  
+  TS_State.Z = IOE_TS_Read_Z();  
+  
+  /* Clear the interrupt pending bit and enable the FIFO again */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* Return pointer to the updated structure */
+  return &TS_State; 
+}
+
+/**
+  * @brief  Returns the temperature row value (in 16 bit format).
+  * @param  None
+  * @retval The temperature row value.
+  */
+uint32_t IOE_TempSens_GetData(void)
+{  
+  static __IO uint32_t tmp = 0;  
+    
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x03);
+  
+  /* Enable the TEMPSENS module */
+  tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8); 
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA + 1); 
+  
+  tmp = (uint32_t)((33 * tmp * 100) / 751);
+  tmp = (uint32_t)((tmp + 5) / 10);
+  
+  /* return the temprature row value */
+  return tmp;
+}
+
+/**
+  * @brief  Checks the selected Global interrupt source pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  Global_IT: the Global interrupt source to be checked, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt      
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  __IO uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
+    
+  if ((tmp & (uint8_t)Global_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected Global interrupt pending bit(s)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  Global_IT: the Global interrupt to be cleared, could be any combination
+  *         of the following values:   
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT); 
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Checks the status of the selected IO interrupt pending bit
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.             
+  * @retval Status of the checked flag. Could be SET or RESET.
+  */
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  uint8_t tmp = 0;
+ 
+  /* get the Interrupt status */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
+  
+  if ((tmp & (uint8_t)IO_IT) != 0)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  Clears the selected IO interrupt pending bit(s).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be 
+  *         from 0 to 7.              
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+  /* Write 1 to the bits that have to be cleared */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);  
+
+  /* Clear the Edge detection pending bit*/
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_ED, IO_IT);
+
+  /* Clear the Rising edge pending bit */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_RE, IO_IT);
+
+  /* Clear the Falling edge pending bit */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_FE, IO_IT);  
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Checks if the selected device is correctly configured and 
+  *         communicates correctly ont the I2C bus.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @retval IOE_OK if IOE is operational. Other value if failure.
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr)
+{
+  /* Return Error if the ID is not correct */
+  if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
+  {
+    /* Check if a Timeout occured */
+    if (IOE_TimeOut == 0)
+    {
+      return (IOE_TimeoutUserCallback());
+    }
+    else
+    {
+      return IOE_FAILURE; /* ID is not Correct */
+    }
+  } 
+  else 
+  {
+    return IOE_OK; /* ID is correct */
+  }
+}
+
+/**
+  * @brief  Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_Reset(uint8_t DeviceAddr)
+{
+  /* Power Down the IO_Expander */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
+
+  /* wait for a delay to insure registers erasing */
+  _delay_(2); 
+  
+  /* Power On the Codec after the power off => all registers are reinitialized*/
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Reads the selected device's ID.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @retval The Device ID (two bytes).
+  */
+uint16_t IOE_ReadID(uint8_t DeviceAddr)
+{
+  uint16_t tmp = 0;
+
+  /* Read device ID  */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
+  tmp = (uint32_t)(tmp << 8);
+  tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
+  
+  /* Return the ID */
+  return (uint16_t)tmp;
+}
+
+/**
+  * @brief  Configures the selcted IO Expander functionalities.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IOE_TEMPSENS_FCT: the functions to be configured. could be any 
+  *         combination of the following values:
+  *   @arg  IOE_IO_FCT : IO function
+  *   @arg  IOE_TS_FCT : Touch Screen function
+  *   @arg  IOE_ADC_FCT : ADC function
+  *   @arg  IOE_TEMPSENS_FCT : Tempreature Sensor function
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the register value */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the Functionalities to be Enabled */    
+    tmp &= ~(uint8_t)Fct;
+  }
+  else
+  {
+    /* Set the Functionalities to be Disabled */    
+    tmp |= (uint8_t)Fct;  
+  }
+  
+  /* Set the register value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;    
+}
+
+/**
+  * @brief  Configures the selected pin direction (to be an input or an output)
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_Pin: IO_Pin_x: Where x can be from 0 to 7.   
+  * @param  Direction: could be Direction_IN or Direction_OUT.      
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
+{
+  uint8_t tmp = 0;   
+  
+  /* Get all the Pins direction */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
+  
+  if (Direction != Direction_IN)
+  {
+    tmp |= (uint8_t)IO_Pin;
+  }  
+  else 
+  {
+    tmp &= ~(uint8_t)IO_Pin;
+  }
+  
+  /* Write the register new value */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;      
+}
+
+/**
+  * @brief  Enables or disables the Global interrupt.
+  * @param  DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  NewState: could be ENABLE or DISABLE.        
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Read the Interrupt Control register  */
+  I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the global interrupts to be Enabled */    
+    tmp |= (uint8_t)IOE_GIT_EN;
+  }
+  else
+  {
+    /* Set the global interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IOE_GIT_EN;
+  }  
+  
+  /* Write Back the Interrupt Control register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;     
+}
+
+/**
+  * @brief  Configures the selected source to generate or not a global interrupt
+  * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *        or IOE_2_ADDR.
+  * @param Global_IT: the interrupt source to be configured, could be:
+  *   @arg  Global_IT_GPIO : All IOs interrupt
+  *   @arg  Global_IT_ADC : ADC interrupt
+  *   @arg  Global_IT_TEMP : Temperature Sensor interrupts      
+  *   @arg  Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+  *   @arg  Global_IT_FF : Touch Screen Controller FIFO Full interrupt      
+  *   @arg  Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt     
+  *   @arg  Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt   
+  *   @arg  Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt 
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current value of the INT_EN register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)Global_IT;  
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)Global_IT;
+  }
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures the selected pins to generate an interrupt or not.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_IT: The IO interrupt to be configured. This parameter could be any
+  *         combination of the following values:
+  *   @arg  IO_IT_x: where x can be from 0 to 7.
+  * @param  NewState: could be ENABLE or DISABLE.  
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+ 
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the interrupts to be Enabled */    
+    tmp |= (uint8_t)IO_IT;
+  }
+  else
+  {
+    /* Set the interrupts to be Disabled */    
+    tmp &= ~(uint8_t)IO_IT;
+  }
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;   
+}
+
+/**
+  * @brief  Configures the touch Screen Controller (Single point detection)
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TS_Config(void)
+{
+  uint8_t tmp = 0;  
+  
+  /* Enable TSC Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp); 
+  
+  /* Enable the TSC gloabl interrupts */
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
+  tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp); 
+  
+  /* Select Sample Time, bit number and ADC Reference */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
+  
+  /* Wait for ~20 ms */
+  _delay_(2);  
+  
+  /* Select the ADC clock speed: 3.25 MHz */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
+  
+  /* Select TSC pins in non default mode */  
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
+  tmp &= ~(uint8_t)TOUCH_IO_ALL;
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp); 
+  
+  /* Select 2 nF filter capacitor */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);   
+  
+  /* Select single point reading  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
+  
+  /* Write 0x01 to clear the FIFO memory content. */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+  
+  /* Write 0x00 to put the FIFO back into operation mode  */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+  
+  /* set the data format for Z value: 7 fractional part and 1 whole part */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
+  
+  /* set the driving capability of the device for TSC pins: 50mA */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
+  
+  /* Use no tracking index, touchscreen controller operation mode (XYZ) and 
+     enable the TSC */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
+  
+  /*  Clear all the status pending bits */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF); 
+  
+  /* Initialize the TS structure to their default values */ 
+  TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
+  
+  /* All configuration done */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Configures and enables the Temperature sensor module.
+  * @param  None
+  * @retval IOE_OK if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_TempSens_Config(void)
+{
+  __IO uint8_t tmp = 0;
+  
+  /* Enable Temperature Sensor Fct: already done in IOE_Config */
+  tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2);
+  tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2, tmp);  
+  
+  /* Enable the TEMPSENS module */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x01);
+  
+  /* Aquire data enable */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x3);
+  
+  /* All configuration done */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the selected pin to be in Alternate function or not
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  NewState: State of the AF for the selected pin, could be 
+  *         ENABLE or DISABLE.       
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
+{
+  uint8_t tmp = 0;
+  
+  /* Get the current state of the GPIO_AF register */
+  tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected pins alternate function */
+    tmp |= (uint8_t)IO_Pin;
+  }
+  else
+  {
+    /* Disable the selected pins alternate function */   
+    tmp &= ~(uint8_t)IO_Pin;   
+  }
+  
+  /* Write back the new valu in GPIO_AF register */  
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);  
+
+  /* If all OK return IOE_OK */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Edge for which a transition is detectable for the
+  *         the selected pin.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR.
+  * @param  IO_Pin: IO_Pin_x, Where x can be from 0 to 7.   
+  * @param  Edge: The edge which will be detected. This parameter can be one or a
+  *         a combination of follwing values: EDGE_FALLING and EDGE_RISING .
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
+{
+  uint8_t tmp1 = 0, tmp2 = 0;   
+  
+  /* Get the registers values */
+  tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
+  tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
+
+  /* Disable the Falling Edge */
+  tmp1 &= ~(uint8_t)IO_Pin;
+  /* Disable the Falling Edge */
+  tmp2 &= ~(uint8_t)IO_Pin;
+
+  /* Enable the Falling edge if selected */
+  if (Edge & EDGE_FALLING)
+  {
+    tmp1 |= (uint8_t)IO_Pin;
+  }
+
+  /* Enable the Rising edge if selected */
+  if (Edge & EDGE_RISING)
+  {
+    tmp2 |= (uint8_t)IO_Pin;
+  }
+
+  /* Write back the registers values */
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
+  I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
+  
+  /* if OK return 0 */
+  return IOE_OK;
+}
+
+/**
+  * @brief  Configures the Interrupt line active state and format (level/edge)
+  * @param  Polarity: could be
+  *   @arg  Polarity_Low: Interrupt line is active Low/Falling edge      
+  *   @arg  Polarity_High: Interrupt line is active High/Rising edge      
+  * @param  Type: Interrupt line activity type, could be one of the following values
+  *   @arg  Type_Level: Interrupt line is active in level model         
+  *   @arg  Type_Edge: Interrupt line is active in edge model           
+  * @retval IOE_OK: if all initializations are OK. Other value if error.
+  */
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
+{
+  uint8_t tmp = 0;
+  
+  /*  Get the register IOE_REG_INT_CTRL value */ 
+  tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
+  
+  /* Mask the polarity and type bits */
+  tmp &= ~(uint8_t)0x06;
+    
+  /* Modify the Interrupt Output line configuration */
+  tmp |= (uint8_t)(Polarity | Type);
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
+  
+  
+  /*  Get the register IOE_REG_INT_CTRL value */ 
+  tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL);
+  /* Mask the polarity and type bits */
+  tmp &= ~(uint8_t)0x06;
+    
+  /* Modify the Interrupt Output line configuration */
+  tmp |= (uint8_t)(Polarity | Type);
+  
+  /* Set the register */
+  I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL, tmp);  
+  
+  /* If all OK return IOE_OK */
+  return IOE_OK;  
+}
+
+/**
+  * @brief  Writes a value in a register of the device through I2C.
+  * @param  DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR. 
+  * @param  RegisterAddr: The target register adress
+  * @param  RegisterValue: The target register value to be written 
+  * @retval IOE_OK: if all operations are OK. Other value if error.
+  */
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t read_verif = 0;  
+  uint8_t IOE_BufferTX = 0;
+  
+  /* Get Value to be written */
+  IOE_BufferTX = RegisterValue;
+  
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_TX, (uint8_t*)(&IOE_BufferTX));
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+   
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(IOE_I2C, RegisterAddr);
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_TX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(IOE_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_TX_TCFLAG);
+  
+#ifdef VERIFY_WRITTENDATA
+  /* Verify (if needed) that the loaded data is correct  */
+  
+  /* Read the just written register*/
+  read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
+  /* Load the register and verify its value  */
+  if (read_verif != RegisterValue)
+  {
+    /* Control data wrongly tranfered */
+    read_verif = IOE_FAILURE;
+  }
+  else
+  {
+    /* Control data correctly transfered */
+    read_verif = 0;
+  }
+#endif
+  
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return read_verif;
+}
+
+/**
+  * @brief  Reads a register of the device through I2C.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR. 
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval The value of the read register (0xAA if Timout occured)   
+  */
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
+{
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+  
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+    
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* return a pointer to the IOE_Buffer */
+  return (uint8_t)IOE_BufferRX[0];  
+}
+
+
+/**
+  * @brief  Reads a buffer of 2 bytes from the device registers.
+  * @param  DeviceAddr: The address of the device, could be : IOE_1_ADDR
+  *         or IOE_2_ADDR. 
+  * @param  RegisterAddr: The target register adress (between 00x and 0x24)
+  * @retval A pointer to the buffer containing the two returned bytes (in halfword).  
+  */
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
+{  
+  uint8_t tmp= 0;
+  uint8_t IOE_BufferRX[2] = {0x00, 0x00};  
+  
+  /* Configure DMA Peripheral */
+  IOE_DMA_Config(IOE_DMA_RX, (uint8_t*)IOE_BufferRX);
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(IOE_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(IOE_I2C, RegisterAddr);  
+  
+  /* Test on TXE FLag (data dent) */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while ((!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_BTF)))  
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(IOE_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_GetFlagStatus(IOE_I2C,I2C_FLAG_SB)) 
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Send IOExpander address for read */
+  I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  IOE_TimeOut = TIMEOUT_MAX;
+  while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(IOE_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  IOE_TimeOut = 2 * TIMEOUT_MAX;
+  while (!DMA_GetFlagStatus(IOE_DMA_RX_TCFLAG))
+  {
+    if (IOE_TimeOut-- == 0) return(IOE_TimeoutUserCallback());
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(IOE_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(IOE_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(IOE_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(IOE_DMA_RX_TCFLAG);
+  
+  /* Reorganize received data */  
+  tmp = IOE_BufferRX[0];
+  IOE_BufferRX[0] = IOE_BufferRX[1];
+  IOE_BufferRX[1] = tmp;
+  
+  /* return a pointer to the IOE_Buffer */
+  return *(uint16_t *)IOE_BufferRX;  
+}
+
+/**
+  * @brief  Return Touch Screen X position value
+  * @param  None
+  * @retval X position.
+  */
+static uint16_t IOE_TS_Read_X(void)
+{
+  int32_t x, xr;
+ 
+  x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
+  
+  /* first correction */
+  xr =  (x * 320) >> 12;
+  /* second correction */
+  xr = ((xr * 32)/29) - 17;
+  
+  if(xr <= 0)
+    xr = 0;
+  
+  return (uint16_t)(xr); 
+}
+
+/**
+  * @brief  Return Touch Screen Y position value
+  * @param  None
+  * @retval Y position.
+  */
+static uint16_t IOE_TS_Read_Y(void)
+{
+  int32_t y, yr;
+  y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
+  
+  yr= (y * 240) >> 12;
+  yr = ((yr * 240) / 217) - 12;
+  
+  if(yr <= 0)
+    yr = 0;
+  
+  return (uint16_t)(yr); 
+}
+
+/**
+  * @brief  Return Touch Screen Z position value
+  * @param  None
+  * @retval Z position.
+  */
+static uint16_t IOE_TS_Read_Z(void)
+{
+  uint32_t z;
+  z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
+  
+  
+  if(z <= 0)
+    z = 0;
+  
+  return (uint16_t)(z); 
+}
+
+/**
+  * @brief  Initializes the GPIO pins used by the IO expander.
+  * @param  None
+  * @retval None
+  */
+static void IOE_GPIO_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
+  RCC_APB1PeriphClockCmd(IOE_I2C_CLK, ENABLE);
+  RCC_APB2PeriphClockCmd(IOE_I2C_SCL_GPIO_CLK | IOE_I2C_SDA_GPIO_CLK | IOE_IT_GPIO_CLK
+                         | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Reset IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, ENABLE);
+  
+  /* Release reset signal of IOE_I2C IP */
+  RCC_APB1PeriphResetCmd(IOE_I2C_CLK, DISABLE);
+  
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(IOE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* IOE_I2C SCL and SDA pins configuration */
+  GPIO_InitStructure.GPIO_Pin = IOE_I2C_SDA_PIN;
+  GPIO_Init(IOE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Set EXTI pin as Input PullUp - IO_Expander_INT */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Connect IO Expander IT line to EXTI line */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);
+}
+
+
+/**
+  * @brief  Configure the I2C Peripheral used to communicate with IO_Expanders.
+  * @param  None
+  * @retval None
+  */
+static void IOE_I2C_Config(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* IOE_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
+  
+  I2C_Init(IOE_I2C, &I2C_InitStructure);
+}
+
+/**
+  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
+  * @param  None
+  * @retval None
+  */
+
+static void IOE_DMA_Config(IOE_DMADirection_TypeDef Direction, uint8_t* buffer)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+  
+  RCC_AHBPeriphClockCmd(IOE_DMA_CLK, ENABLE);
+  
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = IOE_I2C_DR;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
+   /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  
+  /* If using DMA for Reception */
+  if (Direction == IOE_DMA_RX)
+  {
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 2;
+    
+    DMA_DeInit(IOE_DMA_RX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_RX_CHANNEL, &DMA_InitStructure);
+  }
+   /* If using DMA for Transmission */
+  else if (Direction == IOE_DMA_TX)
+  { 
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = 1;
+    
+    DMA_DeInit(IOE_DMA_TX_CHANNEL);
+    
+    DMA_Init(IOE_DMA_TX_CHANNEL, &DMA_InitStructure);
+  }
+}
+
+/**
+  * @brief  Configures the IO expander Interrupt line and GPIO in EXTI mode.
+  * @param  None        
+  * @retval None
+  */
+static void IOE_EXTI_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+ 
+  /* Enable Button GPIO clock */
+  RCC_APB2PeriphClockCmd(IOE_IT_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+  
+  /* Configure Button pin as input floating */
+  GPIO_InitStructure.GPIO_Pin = IOE_IT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(IOE_IT_GPIO_PORT, &GPIO_InitStructure);  
+  
+  /* Connect Button EXTI Line to Button GPIO Pin */
+  GPIO_EXTILineConfig(IOE_IT_EXTI_PORT_SOURCE, IOE_IT_EXTI_PIN_SOURCE);  
+  
+  /* Configure Button EXTI line */
+  EXTI_InitStructure.EXTI_Line = IOE_IT_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;  
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Enable and set Button EXTI Interrupt to the lowest priority */
+  NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = (100000 * nCount); index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+   
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h
new file mode 100644
index 0000000..bde01e5
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h
@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm3210c_eval_ioe.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the IO Expander
+  *   firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+  /* File Info : ---------------------------------------------------------------
+    SUPPORTED FEATURES:
+      - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+      - Joystick: config and Read (Polling/Interrupt)
+      - Touch Screen Features: Single point mode (Polling/Interrupt)
+      - TempSensor Feature: accuracy not determined (Polling).
+
+    UNSUPPORTED FEATURES:
+      - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+  ----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_IOE_H
+#define __STM3210C_EVAL_IOE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210C_EVAL
+  * @{
+  */
+    
+/** @defgroup STM3210C_EVAL_IOE 
+  * @{
+  */ 
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  Touch Screen Information structure  
+  */ 
+typedef struct
+{
+  uint16_t TouchDetected;
+  uint16_t X;
+  uint16_t Y;
+  uint16_t Z;
+}TS_STATE; 
+  
+/** 
+  * @brief  Joystick State definitions  
+  */ 
+#ifndef __STM32_EVAL_H
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+#endif /* __STM32_EVAL_H */
+ 
+/** 
+  * @brief  IO_Expander Error codes  
+  */ 
+typedef enum
+{
+  IOE_OK = 0,
+  IOE_FAILURE, 
+  IOE_TIMEOUT,
+  PARAM_ERROR,
+  IOE1_NOT_OPERATIONAL, 
+  IOE2_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/** 
+  * @brief  IO bit values  
+  */ 
+typedef enum
+{
+  BitReset = 0,
+  BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  IOE_DMA_TX = 0,
+  IOE_DMA_RX = 1
+}IOE_DMADirection_TypeDef;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Constants
+  * @{
+  */ 
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ *        operation. The I2C_WriteDeviceRegister() function will then compare the
+ *        written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _delay_ function defined within
+ *         this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+/**
+ * @brief Uncomment the line below if you want to use user timeout callback.
+ *        Function prototypes is declared in this file but function body may be
+ *        implemented into user application.  
+ */
+/* #define USE_TIMEOUT_USER_CALLBACK */
+
+#ifdef USE_Delay
+#include "main.h"
+ 
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
+                                   (with 10ms time base), using SysTick for example */
+#else
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
+#endif    
+
+/*------------------------------------------------------------------------------
+    Hardware Configuration 
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  I2C port definitions  
+  */
+#define IOE_I2C                          I2C1
+#define IOE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define IOE_I2C_SCL_PIN                  GPIO_Pin_6
+#define IOE_I2C_SCL_GPIO_PORT            GPIOB
+#define IOE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_SDA_PIN                  GPIO_Pin_7
+#define IOE_I2C_SDA_GPIO_PORT            GPIOB
+#define IOE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
+#define IOE_I2C_DR                       ((uint32_t)0x40005410)
+#define IOE_I2C_SPEED                    300000  
+
+/** 
+  * @brief  IOE DMA definitions  
+  */
+#define IOE_DMA                          DMA1
+#define IOE_DMA_CLK                      RCC_AHBPeriph_DMA1
+#define IOE_DMA_TX_CHANNEL               DMA1_Channel6
+#define IOE_DMA_RX_CHANNEL               DMA1_Channel7
+#define IOE_DMA_TX_TCFLAG                DMA1_FLAG_TC6
+#define IOE_DMA_RX_TCFLAG                DMA1_FLAG_TC7
+
+
+/** 
+  * @brief  IO Expander Interrupt line on EXTI  
+  */ 
+#define IOE_IT_PIN                       GPIO_Pin_14
+#define IOE_IT_GPIO_PORT                 GPIOB
+#define IOE_IT_GPIO_CLK                  RCC_APB2Periph_GPIOB
+#define IOE_IT_EXTI_PORT_SOURCE          GPIO_PortSourceGPIOB
+#define IOE_IT_EXTI_PIN_SOURCE           GPIO_PinSource14
+#define IOE_IT_EXTI_LINE                 EXTI_Line14
+#define IOE_IT_EXTI_IRQn                 EXTI15_10_IRQn       
+
+/**
+  * @brief Eval Board IO Pins definition 
+  */ 
+#define AUDIO_RESET_PIN             IO_Pin_2 /* IO_Exapnader_2 */ /* Output */
+#define MII_INT_PIN                 IO_Pin_0 /* IO_Exapnader_2 */ /* Output */
+#define VBAT_DIV_PIN                IO_Pin_0 /* IO_Exapnader_1 */ /* Output */
+#define MEMS_INT1_PIN               IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define MEMS_INT2_PIN               IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+
+ 
+/**
+  * @brief Eval Board both IO Exapanders Pins definition 
+  */ 
+#define IO1_IN_ALL_PINS          (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
+#define IO2_IN_ALL_PINS          (uint32_t)(JOY_IO_PINS)
+#define IO1_OUT_ALL_PINS         (uint32_t)(VBAT_DIV_PIN)
+#define IO2_OUT_ALL_PINS         (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
+
+/** 
+  * @brief  The 7 bits IO Expanders adresses and chip IDs  
+  */ 
+#define IOE_1_ADDR                 0x82    
+#define IOE_2_ADDR                 0x88    
+#define STMPE811_ID                0x0811
+
+
+/*------------------------------------------------------------------------------
+    Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  IO Expander Functionalities definitions  
+  */ 
+#define IOE_ADC_FCT              0x01
+#define IOE_TS_FCT               0x02
+#define IOE_IO_FCT               0x04
+#define IOE_TEMPSENS_FCT         0x08
+
+/** 
+  * @brief  Interrupt source configuration definitons  
+  */ 
+#define IOE_ITSRC_TSC           0x01  /* IO_Exapnder 1 */
+#define IOE_ITSRC_INMEMS        0x02  /* IO_Exapnder 1 */
+#define IOE_ITSRC_JOYSTICK      0x04  /* IO_Exapnder 2 */
+#define IOE_ITSRC_TEMPSENS      0x08  /* IO_Exapnder 2 */
+
+/** 
+  * @brief  Glaobal Interrupts definitions  
+  */ 
+#define IOE_GIT_GPIO             0x80
+#define IOE_GIT_ADC              0x40
+#define IOE_GIT_TEMP             0x20
+#define IOE_GIT_FE               0x10
+#define IOE_GIT_FF               0x08
+#define IOE_GIT_FOV              0x04
+#define IOE_GIT_FTH              0x02
+#define IOE_GIT_TOUCH            0x01
+
+
+/*------------------------------------------------------------------------------
+    STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/** 
+  * @brief  Identification registers  
+  */ 
+#define IOE_REG_CHP_ID             0x00
+#define IOE_REG_ID_VER             0x02
+
+/** 
+  * @brief  General Control Registers  
+  */ 
+#define IOE_REG_SYS_CTRL1          0x03
+#define IOE_REG_SYS_CTRL2          0x04
+#define IOE_REG_SPI_CFG            0x08 
+
+/** 
+  * @brief  Interrupt Control register  
+  */ 
+#define IOE_REG_INT_CTRL           0x09
+#define IOE_REG_INT_EN             0x0A
+#define IOE_REG_INT_STA            0x0B
+#define IOE_REG_GPIO_INT_EN        0x0C
+#define IOE_REG_GPIO_INT_STA       0x0D
+
+/** 
+  * @brief  GPIO Registers  
+  */ 
+#define IOE_REG_GPIO_SET_PIN       0x10
+#define IOE_REG_GPIO_CLR_PIN       0x11
+#define IOE_REG_GPIO_MP_STA        0x12
+#define IOE_REG_GPIO_DIR           0x13
+#define IOE_REG_GPIO_ED            0x14
+#define IOE_REG_GPIO_RE            0x15
+#define IOE_REG_GPIO_FE            0x16
+#define IOE_REG_GPIO_AF            0x17
+
+/** 
+  * @brief  ADC Registers  
+  */ 
+#define IOE_REG_ADC_INT_EN         0x0E
+#define IOE_REG_ADC_INT_STA        0x0F
+#define IOE_REG_ADC_CTRL1          0x20
+#define IOE_REG_ADC_CTRL2          0x21
+#define IOE_REG_ADC_CAPT           0x22
+#define IOE_REG_ADC_DATA_CH0       0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1       0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2       0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3       0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4       0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5       0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6       0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7       0x3C /* 16-Bit register */ 
+
+/** 
+  * @brief  TouchScreen Registers  
+  */ 
+#define IOE_REG_TSC_CTRL           0x40
+#define IOE_REG_TSC_CFG            0x41
+#define IOE_REG_WDM_TR_X           0x42 
+#define IOE_REG_WDM_TR_Y           0x44
+#define IOE_REG_WDM_BL_X           0x46
+#define IOE_REG_WDM_BL_Y           0x48
+#define IOE_REG_FIFO_TH            0x4A
+#define IOE_REG_FIFO_STA           0x4B
+#define IOE_REG_FIFO_SIZE          0x4C
+#define IOE_REG_TSC_DATA_X         0x4D 
+#define IOE_REG_TSC_DATA_Y         0x4F
+#define IOE_REG_TSC_DATA_Z         0x51
+#define IOE_REG_TSC_DATA_XYZ       0x52 
+#define IOE_REG_TSC_FRACT_XYZ      0x56
+#define IOE_REG_TSC_DATA           0x57
+#define IOE_REG_TSC_I_DRIVE        0x58
+#define IOE_REG_TSC_SHIELD         0x59
+
+/** 
+  * @brief  Temperature Sensor registers  
+  */ 
+#define IOE_REG_TEMP_CTRL          0x60
+#define IOE_REG_TEMP_DATA          0x61
+#define IOE_REG_TEMP_TH            0x62
+
+
+/*------------------------------------------------------------------------------
+    Functions parameters defines
+------------------------------------------------------------------------------*/
+/**
+  * @brief Touch Screen Pins definition 
+  */ 
+#define TOUCH_YD                    IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD                    IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU                    IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU                    IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL                (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/**
+  * @brief  JOYSTICK Pins definition 
+  */ 
+#define JOY_IO_SEL                   IO_Pin_7
+#define JOY_IO_DOWN                  IO_Pin_6
+#define JOY_IO_LEFT                  IO_Pin_5
+#define JOY_IO_RIGHT                 IO_Pin_4
+#define JOY_IO_UP                    IO_Pin_3
+#define JOY_IO_NONE                  JOY_IO_PINS
+#define JOY_IO_PINS                  (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
+
+/** 
+  * @brief  IO Pins  
+  */ 
+#define IO_Pin_0                 0x01
+#define IO_Pin_1                 0x02
+#define IO_Pin_2                 0x04
+#define IO_Pin_3                 0x08
+#define IO_Pin_4                 0x10
+#define IO_Pin_5                 0x20
+#define IO_Pin_6                 0x40
+#define IO_Pin_7                 0x80
+#define IO_Pin_ALL               0xFF
+
+/** 
+  * @brief  IO Pin directions  
+  */ 
+#define Direction_IN             0x00
+#define Direction_OUT            0x01
+
+/** 
+  * @brief  Interrupt Line output parameters  
+  */ 
+#define Polarity_Low             0x00
+#define Polarity_High            0x04
+#define Type_Level               0x00
+#define Type_Edge                0x02
+
+/** 
+  * @brief IO Interrupts  
+  */ 
+#define IO_IT_0                  0x01
+#define IO_IT_1                  0x02
+#define IO_IT_2                  0x04
+#define IO_IT_3                  0x08
+#define IO_IT_4                  0x10
+#define IO_IT_5                  0x20
+#define IO_IT_6                  0x40
+#define IO_IT_7                  0x80
+#define ALL_IT                   0xFF
+#define IOE_JOY_IT               (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
+#define IOE_TS_IT                (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
+#define IOE_INMEMS_IT            (uint8_t)(IO_IT_2 | IO_IT_3)
+
+/** 
+  * @brief  Edge detection value  
+  */ 
+#define EDGE_FALLING              0x01
+#define EDGE_RISING               0x02
+
+/** 
+  * @brief  Global interrupt Enable bit  
+  */ 
+#define IOE_GIT_EN                0x01
+
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup STM3210C_EVAL_IOE_Exported_Functions
+  * @{
+  */ 
+
+/** 
+  * @brief  Configuration and initialization functions  
+  */
+uint8_t IOE_Config(void);
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t IOE_TimeoutUserCallback(void);
+#else
+ #define IOE_TimeoutUserCallback()  IOE_TIMEOUT
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+
+/** 
+  * @brief IO pins control functions
+  */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
+JOYState_TypeDef
+ IOE_JoyStickGetState(void);
+
+/** 
+  * @brief Touch Screen controller functions
+  */
+TS_STATE* IOE_TS_GetState(void);
+
+/** 
+  * @brief Interrupts Mangement functions
+  */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+
+/** 
+  * @brief Temperature Sensor functions
+  */
+uint32_t IOE_TempSens_GetData(void);
+
+/** 
+  * @brief IO-Expander Control functions
+  */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr);
+uint8_t IOE_Reset(uint8_t DeviceAddr);
+uint16_t IOE_ReadID(uint8_t DeviceAddr);
+
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
+
+/** 
+  * @brief Low Layer functions
+  */
+uint8_t IOE_TS_Config(void);
+uint8_t IOE_TempSens_Config(void);
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
+
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
+uint16_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
+
+#ifdef __cplusplus
+}
+
+#endif
+#endif /* __STM3210C_EVAL_IOE_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */     
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
index 0e345e4..0e345e4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
index 69dcff1..69dcff1 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
index 97f1022..97f1022 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h
new file mode 100644
index 0000000..a93b966
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h
@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_nand.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210e_eval_fsmc_nand firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */
+   
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210E_EVAL_FSMC_NAND_H
+#define __STM3210E_EVAL_FSMC_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_NAND
+  * @{
+  */  
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Types
+  * @{
+  */
+typedef struct
+{
+  uint8_t Maker_ID;
+  uint8_t Device_ID;
+  uint8_t Third_ID;
+  uint8_t Fourth_ID;
+}NAND_IDTypeDef;
+
+typedef struct 
+{
+  uint16_t Zone;
+  uint16_t Block;
+  uint16_t Page;
+} NAND_ADDRESS;  
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Constants
+  * @{
+  */
+/** 
+  * @brief  NAND Area definition  for STM3210E-EVAL Board RevD  
+  */  
+#define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE  high */
+#define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
+
+#define DATA_AREA                  ((uint32_t)0x00000000) 
+
+/** 
+  * @brief  FSMC NAND memory command  
+  */  
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)
+
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/** 
+  * @brief  NAND memory status  
+  */  
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/** 
+  * @brief  FSMC NAND memory parameters  
+  */  
+#define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
+#define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
+#define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
+#define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
+#define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
+
+/** 
+  * @brief  FSMC NAND memory address computation  
+  */  
+#define ADDR_1st_CYCLE(ADDR)       (uint8_t)((ADDR)& 0xFF)               /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF00) >> 8)      /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Functions
+  * @{
+  */ 
+void NAND_Init(void);
+void NAND_ReadID(NAND_IDTypeDef* NAND_ID);
+uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite);
+uint32_t NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead);
+uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
+uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
+uint32_t NAND_EraseBlock(NAND_ADDRESS Address);
+uint32_t NAND_Reset(void);
+uint32_t NAND_GetStatus(void);
+uint32_t NAND_ReadStatus(void);
+uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210E_EVAL_FSMC_NAND_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
index e3a03d8..e3a03d8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
index 7423f49..7423f49 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c
new file mode 100644
index 0000000..b4d4f81
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.c
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_sram.c
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file provides a set of functions needed to drive the 
+  *          IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval_fsmc_sram.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_SRAM
+  * @brief      This file provides a set of functions needed to drive the 
+  *             IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Defines
+  * @{
+  */ 
+/** 
+  * @brief  FSMC Bank 1 NOR/SRAM3  
+  */
+#define Bank1_SRAM3_ADDR    ((uint32_t)0x68000000)     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the SRAM memory.
+  *         This function must be called before any write/read operation
+  *         on the SRAM.
+  * @param  None 
+  * @retval None
+  */
+void SRAM_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+  GPIO_InitTypeDef GPIO_InitStructure; 
+  
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE |
+                         RCC_APB2Periph_GPIOF, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /*!< SRAM Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+  
+  /*!< SRAM Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | 
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; 
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+   
+  /*!< NOE and NWE configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  
+  /*!< NE3 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  
+  /*!< NBL0, NBL1 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1; 
+  GPIO_Init(GPIOE, &GPIO_InitStructure); 
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 1;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  /*!< Enable FSMC Bank1_SRAM Bank */
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);  
+}
+
+/**
+  * @brief  Writes a Half-word buffer to the FSMC SRAM memory. 
+  * @param  pBuffer : pointer to buffer. 
+  * @param  WriteAddr : SRAM memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite : number of half-words to write. 
+  * @retval None
+  */
+void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  for(; NumHalfwordToWrite != 0; NumHalfwordToWrite--) /*!< while there is data to write */
+  {
+    /*!< Transfer data to the memory */
+    *(uint16_t *) (Bank1_SRAM3_ADDR + WriteAddr) = *pBuffer++;
+    
+    /*!< Increment the address*/  
+    WriteAddr += 2;
+  }   
+}
+
+/**
+  * @brief  Reads a block of data from the FSMC SRAM memory.
+  * @param  pBuffer : pointer to the buffer that receives the data read from the 
+  *         SRAM memory.
+  * @param  ReadAddr : SRAM memory internal address to read from.
+  * @param  NumHalfwordToRead : number of half-words to read.
+  * @retval None
+  */
+void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
+{
+  for(; NumHalfwordToRead != 0; NumHalfwordToRead--) /*!< while there is data to read */
+  {
+    /*!< Read a half-word from the memory */
+    *pBuffer++ = *(__IO uint16_t*) (Bank1_SRAM3_ADDR + ReadAddr);
+
+    /*!< Increment the address*/  
+    ReadAddr += 2;
+  }  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.h
index 117afd0..1ad749c 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_fsmc_sram.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_sram.h
@@ -1,11 +1,11 @@
 /**
   ******************************************************************************
-  * @file    stm32100e_eval_fsmc_sram.h
+  * @file    stm3210e_eval_fsmc_sram.h
   * @author  MCD Application Team
   * @version V4.5.0
   * @date    07-March-2011
   * @brief   This file contains all the functions prototypes for the 
-  *          stm32100e_eval_fsmc_sram firmware driver.
+  *          stm3210e_eval_fsmc_sram firmware driver.
   ******************************************************************************
   * @attention
   *
@@ -21,8 +21,8 @@
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_FSMC_SRAM_H
-#define __STM32100E_EVAL_FSMC_SRAM_H
+#ifndef __STM3210E_EVAL_FSMC_SRAM_H
+#define __STM3210E_EVAL_FSMC_SRAM_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -39,36 +39,36 @@
   * @{
   */ 
 
-/** @addtogroup STM32100E_EVAL
+/** @addtogroup STM3210E_EVAL
   * @{
   */
   
-/** @addtogroup STM32100E_EVAL_FSMC_SRAM
+/** @addtogroup STM3210E_EVAL_FSMC_SRAM
   * @{
   */  
 
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Types
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Types
   * @{
   */
 /**
   * @}
   */
   
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Constants
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Constants
   * @{
   */ 
 /**
   * @}
   */ 
   
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Macros
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Macros
   * @{
   */ 
 /**
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_FSMC_SRAM_Exported_Functions
+/** @defgroup STM3210E_EVAL_FSMC_SRAM_Exported_Functions
   * @{
   */      
 
@@ -80,7 +80,7 @@ void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordT
 }
 #endif
 
-#endif /* __STM32100E_EVAL_FSMC_SRAM_H */
+#endif /* __STM3210E_EVAL_FSMC_SRAM_H */
 /**
   * @}
   */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c
index f9277af..f9277af 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
index 0209e69..0209e69 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h
new file mode 100644
index 0000000..c5439c2
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h
@@ -0,0 +1,403 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval.h
+  * @author  MCD Application Team
+  * @version V4.5.0
+  * @date    07-March-2011
+  * @brief   This file contains definitions for STM32L152_EVAL's Leds, push-buttons
+  *          and COM ports hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152_EVAL_H
+#define __STM32L152_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+      
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_0
+#define LED1_GPIO_PORT                   GPIOD
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED2_PIN                         GPIO_Pin_1
+#define LED2_GPIO_PORT                   GPIOD
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED3_PIN                         GPIO_Pin_4
+#define LED3_GPIO_PORT                   GPIOD
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED4_PIN                         GPIO_Pin_5
+#define LED4_GPIO_PORT                   GPIOD
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOD
+
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          6 
+/* On STM32L152-EVAL board, the KEY button is connected to PC.13 and it can
+be use as Tamper and Wakeup pin buttons. */
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_0
+#define KEY_BUTTON_GPIO_PORT             GPIOA
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOA
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line0
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOA
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource0
+#define KEY_BUTTON_EXTI_IRQn             EXTI0_IRQn
+
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_11
+#define RIGHT_BUTTON_GPIO_PORT           GPIOE
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOE
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line11
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOE
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource11
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
+
+/**
+ * @brief Joystick Left push-button
+ */
+#define LEFT_BUTTON_PIN                  GPIO_Pin_12
+#define LEFT_BUTTON_GPIO_PORT            GPIOE
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line12
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource12
+#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_9
+#define UP_BUTTON_GPIO_PORT              GPIOE
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define UP_BUTTON_EXTI_LINE              EXTI_Line9
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource9
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Down push-button
+ */  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_10
+#define DOWN_BUTTON_GPIO_PORT            GPIOE
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line10
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource10
+#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Sel push-button
+ */
+#define SEL_BUTTON_PIN                   GPIO_Pin_8
+#define SEL_BUTTON_GPIO_PORT             GPIOE
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line8
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource8
+#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn 
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             2
+
+/**
+ * @brief Definition for COM port1, connected to USART2
+ */ 
+#define EVAL_COM1                        USART2
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
+
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource5
+#define EVAL_COM1_TX_AF                  GPIO_AF_USART2
+
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource6
+#define EVAL_COM1_RX_AF                  GPIO_AF_USART2
+
+#define EVAL_COM1_RTS_PIN                GPIO_Pin_4
+#define EVAL_COM1_RTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_RTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RTS_SOURCE             GPIO_PinSource4
+#define EVAL_COM1_RTS_AF                 GPIO_AF_USART2
+
+#define EVAL_COM1_CTS_PIN                GPIO_Pin_3
+#define EVAL_COM1_CTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_CTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_CTS_SOURCE             GPIO_PinSource3
+#define EVAL_COM1_CTS_AF                 GPIO_AF_USART2
+
+#define EVAL_COM1_IRQn                   USART2_IRQn
+
+/**
+ * @brief Definition for COM port2, connected to USART3
+ */ 
+#define EVAL_COM2                        USART3
+#define EVAL_COM2_CLK                    RCC_APB1Periph_USART3
+
+#define EVAL_COM2_TX_PIN                 GPIO_Pin_10
+#define EVAL_COM2_TX_GPIO_PORT           GPIOC
+#define EVAL_COM2_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC
+#define EVAL_COM2_TX_SOURCE              GPIO_PinSource10
+#define EVAL_COM2_TX_AF                  GPIO_AF_USART3
+
+#define EVAL_COM2_RX_PIN                 GPIO_Pin_11
+#define EVAL_COM2_RX_GPIO_PORT           GPIOC
+#define EVAL_COM2_RX_GPIO_CLK            RCC_AHBPeriph_GPIOC
+#define EVAL_COM2_RX_SOURCE              GPIO_PinSource11
+#define EVAL_COM2_RX_AF                  GPIO_AF_USART3
+
+#define EVAL_COM2_IRQn                   USART3_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH
+  * @{
+  */ 
+/**
+  * @brief  SD Card SPI Interface
+  */  
+#define SD_SPI                           SPI2
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI2
+#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PB.13 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOB
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource13
+#define SD_SPI_SCK_AF                    GPIO_AF_SPI2
+#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PB.14 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource14
+#define SD_SPI_MISO_AF                   GPIO_AF_SPI2
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource15
+#define SD_SPI_MOSI_AF                   GPIO_AF_SPI2
+#define SD_CS_PIN                        GPIO_Pin_7                  /* PD.07 */
+#define SD_CS_GPIO_PORT                  GPIOD                       /* GPIOD */
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOD
+#define SD_DETECT_PIN                    GPIO_Pin_6                  /* PE.06 */
+#define SD_DETECT_EXTI_LINE              EXTI_Line6
+#define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource6
+
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define SD_DETECT_EXTI_IRQn              EXTI9_5_IRQn 
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  LM75 Temperature Sensor I2C Interface pins
+  */  
+#define LM75_I2C                         I2C1
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource6
+#define LM75_I2C_SCL_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource7
+#define LM75_I2C_SDA_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1
+#define LM75_I2C_DR                      ((uint32_t)0x40005410)
+
+#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
+#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
+#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
+#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
+
+/**
+  * @}
+  */  
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+
+#define sEE_I2C                          I2C1
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SCL_SOURCE               GPIO_PinSource6
+#define sEE_I2C_SCL_AF                   GPIO_AF_I2C1
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SDA_SOURCE               GPIO_PinSource7
+#define sEE_I2C_SDA_AF                   GPIO_AF_I2C1
+#define sEE_M24C64_32
+
+#define sEE_I2C_DMA                      DMA1   
+#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
+#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
+#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
+#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
+#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
+#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
+#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
+#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
+#define sEE_USE_DMA
+   
+#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
+#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
+#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
+#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler  
+#define sEE_I2C_DMA_PREPRIO              0
+#define sEE_I2C_DMA_SUBPRIO              0
+ 
+#define sEE_DIRECTION_TX                 0
+#define sEE_DIRECTION_RX                 1 
+
+/* Time constant for the delay caclulation allowing to have a millisecond 
+   incrementing counter. This value should be equal to (System Clock / 1000).
+   ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */
+#define sEE_TIME_CONST          24 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); 
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void LM75_LowLevel_DeInit(void);
+void LM75_LowLevel_Init(void);  
+void sEE_LowLevel_DeInit(void);
+void sEE_LowLevel_Init(void);
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
index 27c1638..27c1638 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
index f0ad428..f0ad428 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
index 8170595..8170595 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/logo.bmp b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/logo.bmp
new file mode 100644
index 0000000..18a621e
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/logo.bmp
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/stm32f10x_stdperiph_lib_um.chm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/stm32f10x_stdperiph_lib_um.chm
new file mode 100644
index 0000000..8d9d3d7
--- /dev/null
+++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/stm32f10x_stdperiph_lib_um.chm
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
index 0000000..c8feab4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h
new file mode 100644
index 0000000..2a6f12a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h
@@ -0,0 +1,8388 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    09-March-2012
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F10x Connectivity line, 
+  *          High density, High density value line, Medium density, 
+  *          Medium density Value line, Low density, Low density Value line 
+  *          and XL-density devices.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x
+  * @{
+  */
+    
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) 
+  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
+  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
+  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
+  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
+  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */
+  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  
+  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
+  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
+   memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+   where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 64 and 128 Kbytes.   
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the 
+   Flash memory density ranges between 256 and 512 Kbytes.   
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+  */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  HSE_VALUE
+ #ifdef STM32F10X_CL   
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0500)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE)   
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+   */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x06) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32F10X_STDPERIPH_VERSION        ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F10X_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
+ */
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT             1      /*!< STM32 XL-density devices provide an MPU      */
+#else
+ #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */
+#endif /* STM32F10X_XL */
+#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */
+#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+/******  STM32 specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
+  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
+  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
+
+#ifdef STM32F10X_LD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    
+#endif /* STM32F10X_LD */  
+
+#ifdef STM32F10X_LD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_LD_VL */
+
+#ifdef STM32F10X_MD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  
+#endif /* STM32F10X_MD */  
+
+#ifdef STM32F10X_MD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       
+#endif /* STM32F10X_MD_VL */
+
+#ifdef STM32F10X_HD
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_HD */  
+
+#ifdef STM32F10X_HD_VL
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
+  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */
+  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */
+  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
+  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 
+                                             mapped at position 60 only if the MISC_REMAP bit in 
+                                             the AFIO_MAPR2 register is set)                      */       
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_XL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
+#endif /* STM32F10X_XL */  
+
+#ifdef STM32F10X_CL
+  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
+  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
+  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
+  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */
+  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */
+#endif /* STM32F10X_CL */     
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+#define HSE_Value            HSE_VALUE
+#define HSI_Value            HSI_VALUE
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;
+  __IO uint32_t CR1;
+  __IO uint32_t CR2;
+  __IO uint32_t SMPR1;
+  __IO uint32_t SMPR2;
+  __IO uint32_t JOFR1;
+  __IO uint32_t JOFR2;
+  __IO uint32_t JOFR3;
+  __IO uint32_t JOFR4;
+  __IO uint32_t HTR;
+  __IO uint32_t LTR;
+  __IO uint32_t SQR1;
+  __IO uint32_t SQR2;
+  __IO uint32_t SQR3;
+  __IO uint32_t JSQR;
+  __IO uint32_t JDR1;
+  __IO uint32_t JDR2;
+  __IO uint32_t JDR3;
+  __IO uint32_t JDR4;
+  __IO uint32_t DR;
+} ADC_TypeDef;
+
+/** 
+  * @brief Backup Registers  
+  */
+
+typedef struct
+{
+  uint32_t  RESERVED0;
+  __IO uint16_t DR1;
+  uint16_t  RESERVED1;
+  __IO uint16_t DR2;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR3;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR4;
+  uint16_t  RESERVED4;
+  __IO uint16_t DR5;
+  uint16_t  RESERVED5;
+  __IO uint16_t DR6;
+  uint16_t  RESERVED6;
+  __IO uint16_t DR7;
+  uint16_t  RESERVED7;
+  __IO uint16_t DR8;
+  uint16_t  RESERVED8;
+  __IO uint16_t DR9;
+  uint16_t  RESERVED9;
+  __IO uint16_t DR10;
+  uint16_t  RESERVED10; 
+  __IO uint16_t RTCCR;
+  uint16_t  RESERVED11;
+  __IO uint16_t CR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CSR;
+  uint16_t  RESERVED13[5];
+  __IO uint16_t DR11;
+  uint16_t  RESERVED14;
+  __IO uint16_t DR12;
+  uint16_t  RESERVED15;
+  __IO uint16_t DR13;
+  uint16_t  RESERVED16;
+  __IO uint16_t DR14;
+  uint16_t  RESERVED17;
+  __IO uint16_t DR15;
+  uint16_t  RESERVED18;
+  __IO uint16_t DR16;
+  uint16_t  RESERVED19;
+  __IO uint16_t DR17;
+  uint16_t  RESERVED20;
+  __IO uint16_t DR18;
+  uint16_t  RESERVED21;
+  __IO uint16_t DR19;
+  uint16_t  RESERVED22;
+  __IO uint16_t DR20;
+  uint16_t  RESERVED23;
+  __IO uint16_t DR21;
+  uint16_t  RESERVED24;
+  __IO uint16_t DR22;
+  uint16_t  RESERVED25;
+  __IO uint16_t DR23;
+  uint16_t  RESERVED26;
+  __IO uint16_t DR24;
+  uint16_t  RESERVED27;
+  __IO uint16_t DR25;
+  uint16_t  RESERVED28;
+  __IO uint16_t DR26;
+  uint16_t  RESERVED29;
+  __IO uint16_t DR27;
+  uint16_t  RESERVED30;
+  __IO uint16_t DR28;
+  uint16_t  RESERVED31;
+  __IO uint16_t DR29;
+  uint16_t  RESERVED32;
+  __IO uint16_t DR30;
+  uint16_t  RESERVED33; 
+  __IO uint16_t DR31;
+  uint16_t  RESERVED34;
+  __IO uint16_t DR32;
+  uint16_t  RESERVED35;
+  __IO uint16_t DR33;
+  uint16_t  RESERVED36;
+  __IO uint16_t DR34;
+  uint16_t  RESERVED37;
+  __IO uint16_t DR35;
+  uint16_t  RESERVED38;
+  __IO uint16_t DR36;
+  uint16_t  RESERVED39;
+  __IO uint16_t DR37;
+  uint16_t  RESERVED40;
+  __IO uint16_t DR38;
+  uint16_t  RESERVED41;
+  __IO uint16_t DR39;
+  uint16_t  RESERVED42;
+  __IO uint16_t DR40;
+  uint16_t  RESERVED43;
+  __IO uint16_t DR41;
+  uint16_t  RESERVED44;
+  __IO uint16_t DR42;
+  uint16_t  RESERVED45;    
+} BKP_TypeDef;
+  
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;
+  __IO uint32_t TDTR;
+  __IO uint32_t TDLR;
+  __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;
+  __IO uint32_t RDTR;
+  __IO uint32_t RDLR;
+  __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1;
+  __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t MCR;
+  __IO uint32_t MSR;
+  __IO uint32_t TSR;
+  __IO uint32_t RF0R;
+  __IO uint32_t RF1R;
+  __IO uint32_t IER;
+  __IO uint32_t ESR;
+  __IO uint32_t BTR;
+  uint32_t  RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  uint32_t  RESERVED1[12];
+  __IO uint32_t FMR;
+  __IO uint32_t FM1R;
+  uint32_t  RESERVED2;
+  __IO uint32_t FS1R;
+  uint32_t  RESERVED3;
+  __IO uint32_t FFA1R;
+  uint32_t  RESERVED4;
+  __IO uint32_t FA1R;
+  uint32_t  RESERVED5[8];
+#ifndef STM32F10X_CL
+  CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+  CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */  
+} CAN_TypeDef;
+
+/** 
+  * @brief Consumer Electronics Control (CEC)
+  */
+typedef struct
+{
+  __IO uint32_t CFGR;
+  __IO uint32_t OAR;
+  __IO uint32_t PRES;
+  __IO uint32_t ESR;
+  __IO uint32_t CSR;
+  __IO uint32_t TXD;
+  __IO uint32_t RXD;  
+} CEC_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;
+  __IO uint8_t  IDR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  __IO uint32_t CR;
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t SWTRIGR;
+  __IO uint32_t DHR12R1;
+  __IO uint32_t DHR12L1;
+  __IO uint32_t DHR8R1;
+  __IO uint32_t DHR12R2;
+  __IO uint32_t DHR12L2;
+  __IO uint32_t DHR8R2;
+  __IO uint32_t DHR12RD;
+  __IO uint32_t DHR12LD;
+  __IO uint32_t DHR8RD;
+  __IO uint32_t DOR1;
+  __IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  __IO uint32_t SR;
+#endif
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;
+  __IO uint32_t CR;	
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;
+  __IO uint32_t CNDTR;
+  __IO uint32_t CPAR;
+  __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;
+  __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;
+  __IO uint32_t EMR;
+  __IO uint32_t RTSR;
+  __IO uint32_t FTSR;
+  __IO uint32_t SWIER;
+  __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;
+  __IO uint32_t KEYR;
+  __IO uint32_t OPTKEYR;
+  __IO uint32_t SR;
+  __IO uint32_t CR;
+  __IO uint32_t AR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t OBR;
+  __IO uint32_t WRPR;
+#ifdef STM32F10X_XL
+  uint32_t RESERVED1[8]; 
+  __IO uint32_t KEYR2;
+  uint32_t RESERVED2;   
+  __IO uint32_t SR2;
+  __IO uint32_t CR2;
+  __IO uint32_t AR2; 
+#endif /* STM32F10X_XL */  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+  
+typedef struct
+{
+  __IO uint16_t RDP;
+  __IO uint16_t USER;
+  __IO uint16_t Data0;
+  __IO uint16_t Data1;
+  __IO uint16_t WRP0;
+  __IO uint16_t WRP1;
+  __IO uint16_t WRP2;
+  __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;
+  __IO uint32_t SR2;
+  __IO uint32_t PMEM2;
+  __IO uint32_t PATT2;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR2; 
+} FSMC_Bank2_TypeDef;  
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;
+  __IO uint32_t SR3;
+  __IO uint32_t PMEM3;
+  __IO uint32_t PATT3;
+  uint32_t  RESERVED0;   
+  __IO uint32_t ECCR3; 
+} FSMC_Bank3_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;
+  __IO uint32_t SR4;
+  __IO uint32_t PMEM4;
+  __IO uint32_t PATT4;
+  __IO uint32_t PIO4; 
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t CRL;
+  __IO uint32_t CRH;
+  __IO uint32_t IDR;
+  __IO uint32_t ODR;
+  __IO uint32_t BSRR;
+  __IO uint32_t BRR;
+  __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/** 
+  * @brief Alternate Function I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t EVCR;
+  __IO uint32_t MAPR;
+  __IO uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  __IO uint32_t MAPR2;  
+} AFIO_TypeDef;
+/** 
+  * @brief Inter Integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t OAR1;
+  uint16_t  RESERVED2;
+  __IO uint16_t OAR2;
+  uint16_t  RESERVED3;
+  __IO uint16_t DR;
+  uint16_t  RESERVED4;
+  __IO uint16_t SR1;
+  uint16_t  RESERVED5;
+  __IO uint16_t SR2;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCR;
+  uint16_t  RESERVED7;
+  __IO uint16_t TRISE;
+  uint16_t  RESERVED8;
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;
+  __IO uint32_t PR;
+  __IO uint32_t RLR;
+  __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFGR;
+  __IO uint32_t CIR;
+  __IO uint32_t APB2RSTR;
+  __IO uint32_t APB1RSTR;
+  __IO uint32_t AHBENR;
+  __IO uint32_t APB2ENR;
+  __IO uint32_t APB1ENR;
+  __IO uint32_t BDCR;
+  __IO uint32_t CSR;
+
+#ifdef STM32F10X_CL  
+  __IO uint32_t AHBRSTR;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */ 
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
+  uint32_t RESERVED0;
+  __IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint16_t CRH;
+  uint16_t  RESERVED0;
+  __IO uint16_t CRL;
+  uint16_t  RESERVED1;
+  __IO uint16_t PRLH;
+  uint16_t  RESERVED2;
+  __IO uint16_t PRLL;
+  uint16_t  RESERVED3;
+  __IO uint16_t DIVH;
+  uint16_t  RESERVED4;
+  __IO uint16_t DIVL;
+  uint16_t  RESERVED5;
+  __IO uint16_t CNTH;
+  uint16_t  RESERVED6;
+  __IO uint16_t CNTL;
+  uint16_t  RESERVED7;
+  __IO uint16_t ALRH;
+  uint16_t  RESERVED8;
+  __IO uint16_t ALRL;
+  uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLKCR;
+  __IO uint32_t ARG;
+  __IO uint32_t CMD;
+  __I uint32_t RESPCMD;
+  __I uint32_t RESP1;
+  __I uint32_t RESP2;
+  __I uint32_t RESP3;
+  __I uint32_t RESP4;
+  __IO uint32_t DTIMER;
+  __IO uint32_t DLEN;
+  __IO uint32_t DCTRL;
+  __I uint32_t DCOUNT;
+  __I uint32_t STA;
+  __IO uint32_t ICR;
+  __IO uint32_t MASK;
+  uint32_t  RESERVED0[2];
+  __I uint32_t FIFOCNT;
+  uint32_t  RESERVED1[13];
+  __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DR;
+  uint16_t  RESERVED3;
+  __IO uint16_t CRCPR;
+  uint16_t  RESERVED4;
+  __IO uint16_t RXCRCR;
+  uint16_t  RESERVED5;
+  __IO uint16_t TXCRCR;
+  uint16_t  RESERVED6;
+  __IO uint16_t I2SCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t I2SPR;
+  uint16_t  RESERVED8;  
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SMCR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DIER;
+  uint16_t  RESERVED3;
+  __IO uint16_t SR;
+  uint16_t  RESERVED4;
+  __IO uint16_t EGR;
+  uint16_t  RESERVED5;
+  __IO uint16_t CCMR1;
+  uint16_t  RESERVED6;
+  __IO uint16_t CCMR2;
+  uint16_t  RESERVED7;
+  __IO uint16_t CCER;
+  uint16_t  RESERVED8;
+  __IO uint16_t CNT;
+  uint16_t  RESERVED9;
+  __IO uint16_t PSC;
+  uint16_t  RESERVED10;
+  __IO uint16_t ARR;
+  uint16_t  RESERVED11;
+  __IO uint16_t RCR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CCR1;
+  uint16_t  RESERVED13;
+  __IO uint16_t CCR2;
+  uint16_t  RESERVED14;
+  __IO uint16_t CCR3;
+  uint16_t  RESERVED15;
+  __IO uint16_t CCR4;
+  uint16_t  RESERVED16;
+  __IO uint16_t BDTR;
+  uint16_t  RESERVED17;
+  __IO uint16_t DCR;
+  uint16_t  RESERVED18;
+  __IO uint16_t DMAR;
+  uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;
+  uint16_t  RESERVED0;
+  __IO uint16_t DR;
+  uint16_t  RESERVED1;
+  __IO uint16_t BRR;
+  uint16_t  RESERVED2;
+  __IO uint16_t CR1;
+  uint16_t  RESERVED3;
+  __IO uint16_t CR2;
+  uint16_t  RESERVED4;
+  __IO uint16_t CR3;
+  uint16_t  RESERVED5;
+  __IO uint16_t GTPR;
+  uint16_t  RESERVED6;
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t CFR;
+  __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE             (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */
+#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */
+#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */
+#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */
+#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */
+#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */
+#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */
+#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Backup registers                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DR1 register  ********************/
+#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR2 register  ********************/
+#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR3 register  ********************/
+#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR4 register  ********************/
+#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR5 register  ********************/
+#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR6 register  ********************/
+#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR7 register  ********************/
+#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR8 register  ********************/
+#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR9 register  ********************/
+#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR10 register  *******************/
+#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR11 register  *******************/
+#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR12 register  *******************/
+#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR13 register  *******************/
+#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR14 register  *******************/
+#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR15 register  *******************/
+#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR16 register  *******************/
+#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR17 register  *******************/
+#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_DR18 register  ********************/
+#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR19 register  *******************/
+#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR20 register  *******************/
+#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR21 register  *******************/
+#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR22 register  *******************/
+#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR23 register  *******************/
+#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR24 register  *******************/
+#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR25 register  *******************/
+#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR26 register  *******************/
+#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR27 register  *******************/
+#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR28 register  *******************/
+#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR29 register  *******************/
+#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR30 register  *******************/
+#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR31 register  *******************/
+#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR32 register  *******************/
+#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR33 register  *******************/
+#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR34 register  *******************/
+#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR35 register  *******************/
+#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR36 register  *******************/
+#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR37 register  *******************/
+#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR38 register  *******************/
+#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR39 register  *******************/
+#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR40 register  *******************/
+#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR41 register  *******************/
+#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR42 register  *******************/
+#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/******************  Bit definition for BKP_RTCCR register  *******************/
+#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
+#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
+#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
+#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_CR register  ********************/
+#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
+#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
+
+/*******************  Bit definition for BKP_CSR register  ********************/
+#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
+#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
+#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
+#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
+#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */
+ #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */
+ #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */
+ #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
+#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
+#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */
+ #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */
+ 
+ #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */
+ 
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+ #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/
+ #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#else
+ #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */
+
+ #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */
+ #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */
+
+ #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+ #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+ #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+ #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+ #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+ #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+ #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+ #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+ #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+ #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+ #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+ #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+ #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+ #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+ #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+ #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
+ #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
+ #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+ #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
+ #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+ #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+ #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */
+ #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */
+ #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */
+ #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */
+ #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
+#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
+#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
+#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
+#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */
+#endif
+
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+ #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */
+ #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */
+ #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */
+ #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */
+ #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */
+#endif /* STM32F10X_XL */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */
+#endif
+
+#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+ #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+ #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
+ #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+ #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+ #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+ #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ 
+#endif
+
+#if defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */
+ #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ 
+ #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+ #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ 
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */
+ #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */
+ #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */
+#endif /* STM32F10X_XL */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+ #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */
+ #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */
+ #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */
+ #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
+#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
+#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
+#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
+#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */
+#endif
+
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+ #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */
+ #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */
+ #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */
+#endif
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */
+ #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */
+#endif
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */
+#endif
+
+#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+ #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+ #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+ #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)
+ #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)
+ #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+ #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+ #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+ #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ 
+#endif
+
+#ifdef STM32F10X_HD_VL
+ #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+ #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+ #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+ #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ 
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_CL
+ #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */
+ #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */
+#endif /* STM32F10X_XL */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+ #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */
+ #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */
+ #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */
+ #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */
+ #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */
+ #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */
+ #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */
+ #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */
+ #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */
+ #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */
+ #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */
+ #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */
+ #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */
+ #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */
+ #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */
+ #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */
+ #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */
+ #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */
+ #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */
+ #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */
+ #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */
+
+ #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */
+ #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */
+ #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+ #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+ #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+ #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+ #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+ #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+ #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+ #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+ #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+ #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+ #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+ #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+ #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+ #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+ #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+ #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+ #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+ #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+ #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+ #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+ #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+ #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+#endif
+ 
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function I/O                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CRL register  *******************/
+#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for GPIO_CRH register  *******************/
+#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*!<******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRR register  *******************/
+#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRR register  *******************/
+#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for AFIO_EVCR register  *******************/
+#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */
+
+/******************  Bit definition for AFIO_MAPR register  *******************/
+#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */  
+#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */  
+#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */  
+#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */  
+#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
+#endif
+
+#ifdef STM32F10X_HD_VL
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */
+#endif
+
+#ifdef STM32F10X_XL 
+/******************  Bit definition for AFIO_MAPR2 register  ******************/
+#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
+#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
+
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
+#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define  DAC_CR_DMAUDRIE1                   ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun interrupt enable */
+ #define  DAC_CR_DMAUDRIE2                   ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun interrupt enable */
+#endif
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    CEC                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CEC_CFGR register  ******************/
+#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */
+#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */
+#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */
+#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */
+
+/********************  Bit definition for CEC_OAR register  ******************/
+#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */
+#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */
+#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */
+#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */
+#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */
+
+/********************  Bit definition for CEC_PRES register  ******************/
+#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */
+
+/********************  Bit definition for CEC_ESR register  ******************/
+#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */
+#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */
+#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */
+#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */
+#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */
+#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */
+#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */
+
+/********************  Bit definition for CEC_CSR register  ******************/
+#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */
+#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */
+#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */
+#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
+#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */
+#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */
+#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */
+#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */
+
+/********************  Bit definition for CEC_TXD register  ******************/
+#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */
+
+/********************  Bit definition for CEC_RXD register  ******************/
+#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Real-Time Clock                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CRH register  ********************/
+#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */
+#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */
+#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CRL register  ********************/
+#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */
+#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */
+#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */
+#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */
+#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */
+#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */
+
+/*******************  Bit definition for RTC_PRLH register  *******************/
+#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRH register  *******************/
+#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRL register  *******************/
+#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */
+
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */
+
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */
+
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */
+
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB Device FS                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */
+
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */
+
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */
+
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */
+
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/    
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/******************  FLASH Keys  **********************************************/
+#define RDP_Key                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */
+#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */
+
+#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */
+#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */
+#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for FLASH_RDP register  *******************/
+#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
+#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
+#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/*                Ethernet MAC Registers bits definitions                     */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */
+  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ 
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ 
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ 
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM 	  ((uint32_t)0x00000010)  /* Pass all mutlicast */ 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ 
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ 
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ 
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ 
+  
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F10x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h
new file mode 100644
index 0000000..01daf13
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    09-March-2012
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm
new file mode 100644
index 0000000..f363bdd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TASKING/cstart_thumb2.asm
@@ -0,0 +1,140 @@
+
+
+;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;;        we will only use 16-bit Thumb intructions.
+
+        .extern _lc_ub_stack            ; usr/sys mode stack pointer
+        .extern _lc_ue_stack            ; symbol required by debugger
+        .extern _lc_ub_table            ; ROM to RAM copy table
+        .extern main
+        .extern _Exit
+        .extern exit
+        .weak   exit
+        .global __get_argcv
+        .weak   __get_argcv
+        .extern __argcvbuf
+        .weak   __argcvbuf
+        ;;.extern __init_hardware
+		.extern  SystemInit
+        
+    .if @defined('__PROF_ENABLE__')
+        .extern __prof_init
+    .endif
+    .if @defined('__POSIX__')
+        .extern posix_main
+        .extern _posix_boot_stack_top
+    .endif
+
+        .global _START
+
+        .section .text.cstart
+
+        .thumb
+_START: 
+        ;; anticipate possible ROM/RAM remapping
+        ;; by loading the 'real' program address
+        ldr     r1,=_Next
+        bx      r1
+_Next:
+        ;; initialize the stack pointer
+        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
+        mov     sp,r1
+
+        ;; call a user function which initializes function.
+		bl  SystemInit
+
+        ;; copy initialized sections from ROM to RAM
+        ;; and clear uninitialized data sections in RAM
+
+        ldr     r3,=_lc_ub_table
+        movs    r0,#0
+cploop:
+        ldr     r4,[r3,#0]      ; load type
+        ldr     r5,[r3,#4]      ; dst address
+        ldr     r6,[r3,#8]      ; src address
+        ldr     r7,[r3,#12]     ; size
+
+        cmp     r4,#1
+        beq     copy
+        cmp     r4,#2
+        beq     clear
+        b       done
+
+copy:
+        subs    r7,r7,#1
+        ldrb    r1,[r6,r7]
+        strb    r1,[r5,r7]
+        bne     copy
+
+        adds    r3,r3,#16
+        b       cploop
+
+clear:
+        subs    r7,r7,#1
+        strb    r0,[r5,r7]
+        bne     clear
+        
+        adds    r3,r3,#16
+        b       cploop
+        
+done:   
+
+      .if @defined('__POSIX__')
+        
+        ;; posix stack buffer for system upbringing
+        ldr     r0,=_posix_boot_stack_top
+        ldr     r0, [r0]
+        mov     sp,r0
+     
+     .else
+        
+        ;; load r10 with end of USR/SYS stack, which is
+        ;; needed in case stack overflow checking is on
+        ;; NOTE: use 16-bit instructions only, for ARMv6M
+        ldr     r0,=_lc_ue_stack
+        mov     r10,r0
+     
+     .endif
+
+    .if @defined('__PROF_ENABLE__')
+        bl      __prof_init
+    .endif
+
+    .if @defined('__POSIX__')
+        ;; call posix_main with no arguments
+        bl      posix_main
+    .else
+        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+        bl      __get_argcv
+        ldr     r1,=__argcvbuf
+        ;; call main
+        bl       main
+    .endif
+
+        ;; call exit using the return value from main()
+        ;; Note. Calling exit will also run all functions
+        ;; that were supplied through atexit().
+        bl      exit
+        
+__get_argcv:                    ; weak definition
+        movs     r0,#0
+        bx      lr
+
+        .ltorg
+        .endsec
+
+        .calls  '_START', '  '
+        .calls  '_START','__init_vector_table'
+    .if @defined('__PROF_ENABLE__')
+        .calls  '_START','__prof_init'
+    .endif
+    .if @defined('__POSIX__')
+        .calls  '_START','posix_main'
+    .else
+        .calls  '_START','__get_argcv'
+        .calls  '_START','main'
+    .endif
+        .calls  '_START','exit'
+        .calls  '_START','',0
+
+        .end
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..fea24d8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_cl.s
@@ -0,0 +1,479 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_cl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Connectivity line Devices vector table for Atollic
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR
+  *                  address.
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+  	bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+  .word CAN1_TX_IRQHandler
+  .word CAN1_RX0_IRQHandler
+ 	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	OTG_FS_WKUP_IRQHandler
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word ETH_IRQHandler
+  .word ETH_WKUP_IRQHandler
+  .word CAN2_TX_IRQHandler
+  .word CAN2_RX0_IRQHandler
+  .word CAN2_RX1_IRQHandler
+  .word CAN2_SCE_IRQHandler
+  .word OTG_FS_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM     /* @0x1E0. This is for boot in RAM mode for
+                         STM32F10x Connectivity line Devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	OTG_FS_WKUP_IRQHandler
+	.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	ETH_IRQHandler
+	.thumb_set ETH_IRQHandler,Default_Handler
+
+	.weak	ETH_WKUP_IRQHandler
+	.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+	.weak	CAN2_TX_IRQHandler
+	.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX0_IRQHandler
+	.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX1_IRQHandler
+	.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN2_SCE_IRQHandler
+	.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler ,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s
index a93e59b..7994bd6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_hd.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f10x_hd.s
   * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
+  * @version   V3.6.1
+  * @date      09-March-2012
   * @brief     STM32F10x High Density Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -19,14 +19,20 @@
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -466,4 +472,4 @@ g_pfnVectors:
 	.weak	DMA2_Channel4_5_IRQHandler
 	.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..8deb6a2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_hd_vl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x High Density Value Line Devices vector table for Atollic 
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system  
+  *                - Configure external SRAM mounted on STM32100E-EVAL board
+  *                  to be used as data memory (optional, to be enabled by user)   
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+	
+/* Call the clock system intitialization function.*/
+  bl  SystemInit 
+/* Call static constructors */
+  bl __libc_init_array  
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	CEC_IRQHandler
+  .word TIM12_IRQHandler
+  .word TIM13_IRQHandler
+  .word TIM14_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word TIM6_DAC_IRQHandler
+  .word TIM7_IRQHandler  
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_5_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x High Density Value line devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM15_IRQHandler
+  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  CEC_IRQHandler
+  .thumb_set CEC_IRQHandler,Default_Handler
+
+  .weak  TIM12_IRQHandler
+  .thumb_set TIM12_IRQHandler,Default_Handler
+
+  .weak  TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak  TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak  TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+
+  .weak  SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak  UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak  UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+  
+  .weak  TIM6_DAC_IRQHandler
+  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler 
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
+
+  .weak  DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..19a6724
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld.s
@@ -0,0 +1,353 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_ld.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Low Density Devices vector table for Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address.
+  *                - Configure the clock system 
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+  .word TIM1_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word 0
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word 0
+  .word 0
+  .word SPI1_IRQHandler
+  .word 0
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word 0
+  .word EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	USBWakeUp_IRQHandler
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	BootRAM        /* @0x108. This is for boot in RAM mode for
+                          STM32F10x Low Density devices.*/
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s
index 3224b40..a5f6850 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_ld_vl.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_ld_vl.s
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f10x_ld_vl.s
   * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
+  * @version   V3.6.1
+  * @date      09-March-2012
   * @brief     STM32F10x Low Density Value Line Devices vector table for Atollic toolchain.
   *            This module performs:
   *                - Set the initial SP
@@ -17,14 +17,20 @@
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -388,5 +394,5 @@ g_pfnVectors:
   .weak  TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler  
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s
index b2fd0db..2427331 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md_vl.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md_vl.s
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file      startup_stm32f10x_md_vl.s
   * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
+  * @version   V3.6.1
+  * @date      09-March-2012
   * @brief     STM32F10x Medium Density Value Line Devices vector table for Atollic 
   *            toolchain.
   *            This module performs:
@@ -18,14 +18,20 @@
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -404,5 +410,5 @@ g_pfnVectors:
   .weak  TIM7_IRQHandler
   .thumb_set TIM7_IRQHandler,Default_Handler  
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s
new file mode 100644
index 0000000..366a965
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s
@@ -0,0 +1,473 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_xl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x XL-Density Devices vector table for TrueSTUDIO toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3210E-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler
+  .word  PVD_IRQHandler
+  .word  TAMPER_IRQHandler
+  .word  RTC_IRQHandler
+  .word  FLASH_IRQHandler
+  .word  RCC_IRQHandler
+  .word  EXTI0_IRQHandler
+  .word  EXTI1_IRQHandler
+  .word  EXTI2_IRQHandler
+  .word  EXTI3_IRQHandler
+  .word  EXTI4_IRQHandler
+  .word  DMA1_Channel1_IRQHandler
+  .word  DMA1_Channel2_IRQHandler
+  .word  DMA1_Channel3_IRQHandler
+  .word  DMA1_Channel4_IRQHandler
+  .word  DMA1_Channel5_IRQHandler
+  .word  DMA1_Channel6_IRQHandler
+  .word  DMA1_Channel7_IRQHandler
+  .word  ADC1_2_IRQHandler
+  .word  USB_HP_CAN1_TX_IRQHandler
+  .word  USB_LP_CAN1_RX0_IRQHandler
+  .word  CAN1_RX1_IRQHandler
+  .word  CAN1_SCE_IRQHandler
+  .word  EXTI9_5_IRQHandler
+  .word  TIM1_BRK_TIM9_IRQHandler
+  .word  TIM1_UP_TIM10_IRQHandler
+  .word  TIM1_TRG_COM_TIM11_IRQHandler
+  .word  TIM1_CC_IRQHandler
+  .word  TIM2_IRQHandler
+  .word  TIM3_IRQHandler
+  .word  TIM4_IRQHandler
+  .word  I2C1_EV_IRQHandler
+  .word  I2C1_ER_IRQHandler
+  .word  I2C2_EV_IRQHandler
+  .word  I2C2_ER_IRQHandler
+  .word  SPI1_IRQHandler
+  .word  SPI2_IRQHandler
+  .word  USART1_IRQHandler
+  .word  USART2_IRQHandler
+  .word  USART3_IRQHandler
+  .word  EXTI15_10_IRQHandler
+  .word  RTCAlarm_IRQHandler
+  .word  USBWakeUp_IRQHandler
+  .word  TIM8_BRK_TIM12_IRQHandler
+  .word  TIM8_UP_TIM13_IRQHandler
+  .word  TIM8_TRG_COM_TIM14_IRQHandler
+  .word  TIM8_CC_IRQHandler
+  .word  ADC3_IRQHandler
+  .word  FSMC_IRQHandler
+  .word  SDIO_IRQHandler
+  .word  TIM5_IRQHandler
+  .word  SPI3_IRQHandler
+  .word  UART4_IRQHandler
+  .word  UART5_IRQHandler
+  .word  TIM6_IRQHandler
+  .word  TIM7_IRQHandler
+  .word  DMA2_Channel1_IRQHandler
+  .word  DMA2_Channel2_IRQHandler
+  .word  DMA2_Channel3_IRQHandler
+  .word  DMA2_Channel4_5_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x XL-Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak  USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak  USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak  CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak  CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM9_IRQHandler
+  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM10_IRQHandler
+  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM11_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+  .weak  TIM8_BRK_TIM12_IRQHandler
+  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+  .weak  TIM8_UP_TIM13_IRQHandler
+  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+  .weak  TIM8_TRG_COM_TIM14_IRQHandler
+  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+  .weak  TIM8_CC_IRQHandler
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+  .weak  ADC3_IRQHandler
+  .thumb_set ADC3_IRQHandler,Default_Handler
+
+  .weak  FSMC_IRQHandler
+  .thumb_set FSMC_IRQHandler,Default_Handler
+
+  .weak  SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak  TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+
+  .weak  SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak  UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak  UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak  TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..2ced3f4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd.s
@@ -0,0 +1,365 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+                                                  
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1 & ADC2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+                DCD     TIM8_BRK_IRQHandler        ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler         ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler    ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler         ; TIM8 Capture Compare
+                DCD     ADC3_IRQHandler            ; ADC3
+                DCD     FSMC_IRQHandler            ; FSMC
+                DCD     SDIO_IRQHandler            ; SDIO
+                DCD     TIM5_IRQHandler            ; TIM5
+                DCD     SPI3_IRQHandler            ; SPI3
+                DCD     UART4_IRQHandler           ; UART4
+                DCD     UART5_IRQHandler           ; UART5
+                DCD     TIM6_IRQHandler            ; TIM6
+                DCD     TIM7_IRQHandler            ; TIM7
+                DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+                
+; Reset handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+                IMPORT  SystemInit
+                LDR     R0, =SystemInit
+                BLX     R0               
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+                
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM8_UP_IRQHandler         [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM8_CC_IRQHandler         [WEAK]
+                EXPORT  ADC3_IRQHandler            [WEAK]
+                EXPORT  FSMC_IRQHandler            [WEAK]
+                EXPORT  SDIO_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  UART4_IRQHandler           [WEAK]
+                EXPORT  UART5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..d6ac20c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,353 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x High Density Value Line Devices vector table  
+;*                      for MDK-ARM toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system and also configure the external 
+;*                        SRAM mounted on STM32100E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                 ; Window Watchdog
+                DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler               ; Tamper
+                DCD     RTC_IRQHandler                  ; RTC
+                DCD     FLASH_IRQHandler                ; Flash
+                DCD     RCC_IRQHandler                  ; RCC
+                DCD     EXTI0_IRQHandler                ; EXTI Line 0
+                DCD     EXTI1_IRQHandler                ; EXTI Line 1
+                DCD     EXTI2_IRQHandler                ; EXTI Line 2
+                DCD     EXTI3_IRQHandler                ; EXTI Line 3
+                DCD     EXTI4_IRQHandler                ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                 ; ADC1
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5
+                DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                 ; TIM2
+                DCD     TIM3_IRQHandler                 ; TIM3
+                DCD     TIM4_IRQHandler                 ; TIM4
+                DCD     I2C1_EV_IRQHandler              ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler              ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler              ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler              ; I2C2 Error
+                DCD     SPI1_IRQHandler                 ; SPI1
+                DCD     SPI2_IRQHandler                 ; SPI2
+                DCD     USART1_IRQHandler               ; USART1
+                DCD     USART2_IRQHandler               ; USART2
+                DCD     USART3_IRQHandler               ; USART3
+                DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line
+                DCD     CEC_IRQHandler                  ; HDMI-CEC
+                DCD     TIM12_IRQHandler                ; TIM12
+                DCD     TIM13_IRQHandler                ; TIM13 
+                DCD     TIM14_IRQHandler                ; TIM14
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     TIM5_IRQHandler                 ; TIM5
+                DCD     SPI3_IRQHandler                 ; SPI3
+                DCD     UART4_IRQHandler                ; UART4
+                DCD     UART5_IRQHandler                ; UART5
+                DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun
+                DCD     TIM7_IRQHandler                 ; TIM7
+                DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1
+                DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2
+                DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3
+                DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5
+                DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                 [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                   [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                  [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                  [WEAK]
+                EXPORT  PVD_IRQHandler                   [WEAK]
+                EXPORT  TAMPER_IRQHandler                [WEAK]
+                EXPORT  RTC_IRQHandler                   [WEAK]
+                EXPORT  FLASH_IRQHandler                 [WEAK]
+                EXPORT  RCC_IRQHandler                   [WEAK]
+                EXPORT  EXTI0_IRQHandler                 [WEAK]
+                EXPORT  EXTI1_IRQHandler                 [WEAK]
+                EXPORT  EXTI2_IRQHandler                 [WEAK]
+                EXPORT  EXTI3_IRQHandler                 [WEAK]
+                EXPORT  EXTI4_IRQHandler                 [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler         [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler                  [WEAK]
+                EXPORT  EXTI9_5_IRQHandler               [WEAK]
+                EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler               [WEAK]
+                EXPORT  TIM2_IRQHandler                  [WEAK]
+                EXPORT  TIM3_IRQHandler                  [WEAK]
+                EXPORT  TIM4_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler               [WEAK]
+                EXPORT  I2C1_ER_IRQHandler               [WEAK]
+                EXPORT  I2C2_EV_IRQHandler               [WEAK]
+                EXPORT  I2C2_ER_IRQHandler               [WEAK]
+                EXPORT  SPI1_IRQHandler                  [WEAK]
+                EXPORT  SPI2_IRQHandler                  [WEAK]
+                EXPORT  USART1_IRQHandler                [WEAK]
+                EXPORT  USART2_IRQHandler                [WEAK]
+                EXPORT  USART3_IRQHandler                [WEAK]
+                EXPORT  EXTI15_10_IRQHandler             [WEAK]
+                EXPORT  RTCAlarm_IRQHandler              [WEAK]
+                EXPORT  CEC_IRQHandler                   [WEAK]
+                EXPORT  TIM12_IRQHandler                 [WEAK]
+                EXPORT  TIM13_IRQHandler                 [WEAK]
+                EXPORT  TIM14_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                  [WEAK]
+                EXPORT  SPI3_IRQHandler                  [WEAK]
+                EXPORT  UART4_IRQHandler                 [WEAK]
+                EXPORT  UART5_IRQHandler                 [WEAK]                
+                EXPORT  TIM6_DAC_IRQHandler              [WEAK]
+                EXPORT  TIM7_IRQHandler                  [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler         [WEAK]                
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+DMA2_Channel5_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..4d9b5ce
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_ld.s
@@ -0,0 +1,304 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_ld.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x Low Density Devices vector table for MDK-ARM 
+;*                      toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     0                          ; Reserved
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     0                          ; Reserved
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     0                          ; Reserved
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s
new file mode 100644
index 0000000..84ae671
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md.s
@@ -0,0 +1,314 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x Medium Density Devices vector table for MDK-ARM 
+;*                      toolchain.  
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     USART1_IRQHandler          ; USART1
+                DCD     USART2_IRQHandler          ; USART2
+                DCD     USART3_IRQHandler          ; USART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md_vl.s
index 076aa7f..0d1f84f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_md_vl.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_md_vl.s
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
 ;* File Name          : startup_stm32f10x_md_vl.s
 ;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
 ;* Description        : STM32F10x Medium Density Value Line Devices vector table  
 ;*                      for MDK-ARM toolchain.  
 ;*                      This module performs:
@@ -16,12 +16,19 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
 ;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
 ;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
@@ -312,4 +319,4 @@ __user_initial_stackheap
 
                  END
 
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_xl.s
index 9fbc640..85dab64 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/arm/startup_stm32f10x_xl.s
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
 ;* File Name          : startup_stm32f10x_xl.s
 ;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
 ;* Description        : STM32F10x XL-Density Devices vector table for MDK-ARM 
 ;*                      toolchain. 
 ;*                      This module performs:
@@ -18,12 +18,19 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
 ;*******************************************************************************
-; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
 ;*******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
@@ -355,4 +362,4 @@ __user_initial_stackheap
 
                  END
 
-;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..f312d2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_hd.s
@@ -0,0 +1,471 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_hd.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x High Density Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3210E-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler
+  .word  PVD_IRQHandler
+  .word  TAMPER_IRQHandler
+  .word  RTC_IRQHandler
+  .word  FLASH_IRQHandler
+  .word  RCC_IRQHandler
+  .word  EXTI0_IRQHandler
+  .word  EXTI1_IRQHandler
+  .word  EXTI2_IRQHandler
+  .word  EXTI3_IRQHandler
+  .word  EXTI4_IRQHandler
+  .word  DMA1_Channel1_IRQHandler
+  .word  DMA1_Channel2_IRQHandler
+  .word  DMA1_Channel3_IRQHandler
+  .word  DMA1_Channel4_IRQHandler
+  .word  DMA1_Channel5_IRQHandler
+  .word  DMA1_Channel6_IRQHandler
+  .word  DMA1_Channel7_IRQHandler
+  .word  ADC1_2_IRQHandler
+  .word  USB_HP_CAN1_TX_IRQHandler
+  .word  USB_LP_CAN1_RX0_IRQHandler
+  .word  CAN1_RX1_IRQHandler
+  .word  CAN1_SCE_IRQHandler
+  .word  EXTI9_5_IRQHandler
+  .word  TIM1_BRK_IRQHandler
+  .word  TIM1_UP_IRQHandler
+  .word  TIM1_TRG_COM_IRQHandler
+  .word  TIM1_CC_IRQHandler
+  .word  TIM2_IRQHandler
+  .word  TIM3_IRQHandler
+  .word  TIM4_IRQHandler
+  .word  I2C1_EV_IRQHandler
+  .word  I2C1_ER_IRQHandler
+  .word  I2C2_EV_IRQHandler
+  .word  I2C2_ER_IRQHandler
+  .word  SPI1_IRQHandler
+  .word  SPI2_IRQHandler
+  .word  USART1_IRQHandler
+  .word  USART2_IRQHandler
+  .word  USART3_IRQHandler
+  .word  EXTI15_10_IRQHandler
+  .word  RTCAlarm_IRQHandler
+  .word  USBWakeUp_IRQHandler
+  .word  TIM8_BRK_IRQHandler
+  .word  TIM8_UP_IRQHandler
+  .word  TIM8_TRG_COM_IRQHandler
+  .word  TIM8_CC_IRQHandler
+  .word  ADC3_IRQHandler
+  .word  FSMC_IRQHandler
+  .word  SDIO_IRQHandler
+  .word  TIM5_IRQHandler
+  .word  SPI3_IRQHandler
+  .word  UART4_IRQHandler
+  .word  UART5_IRQHandler
+  .word  TIM6_IRQHandler
+  .word  TIM7_IRQHandler
+  .word  DMA2_Channel1_IRQHandler
+  .word  DMA2_Channel2_IRQHandler
+  .word  DMA2_Channel3_IRQHandler
+  .word  DMA2_Channel4_5_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x High Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak  USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak  USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak  CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak  CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+  .weak  TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+  .weak  TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+  .weak  TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+  .weak  TIM8_CC_IRQHandler
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+  .weak  ADC3_IRQHandler
+  .thumb_set ADC3_IRQHandler,Default_Handler
+
+  .weak  FSMC_IRQHandler
+  .thumb_set FSMC_IRQHandler,Default_Handler
+
+  .weak  SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak  TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+
+  .weak  SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak  UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak  UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak  TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..e370a4c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld.s
@@ -0,0 +1,349 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_ld.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */	
+    
+  .syntax unified
+	.cpu cortex-m3
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */  
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:	
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+    
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+    
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit  
+/* Call the application's entry point.*/
+	bl	main
+	bx	lr    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/    
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_IRQHandler
+	.word	RTC_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	0
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	0
+	.word	0
+	.word	SPI1_IRQHandler
+	.word	0
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	0
+	.word	EXTI15_10_IRQHandler
+	.word	RTCAlarm_IRQHandler
+	.word	USBWakeUp_IRQHandler	
+  .word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	BootRAM        /* @0x108. This is for boot in RAM mode for 
+                          STM32F10x Low Density devices.*/
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+	
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+	
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+	
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_IRQHandler
+	.thumb_set TAMPER_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTCAlarm_IRQHandler
+	.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s
new file mode 100644
index 0000000..cba97a4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_ld_vl.s
@@ -0,0 +1,389 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_ld_vl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Low Density Value Line Devices vector table for RIDE7
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system 
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval None
+*/
+
+  .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b     LoopCopyDataInit
+
+CopyDataInit:
+  ldr   r3, =_sidata
+  ldr   r3, [r3, r1]
+  str   r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr   r0, =_sdata
+  ldr   r3, =_edata
+  adds  r2, r0, r1
+  cmp   r2, r3
+  bcc   CopyDataInit
+  ldr   r2, =_sbss
+  b     LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str   r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr   r3, = _ebss
+  cmp   r2, r3
+  bcc   FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl    main
+  bx    lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt. This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+  .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+******************************************************************************/    
+  .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler
+  .word  PVD_IRQHandler
+  .word  TAMPER_IRQHandler
+  .word  RTC_IRQHandler
+  .word  FLASH_IRQHandler
+  .word  RCC_IRQHandler
+  .word  EXTI0_IRQHandler
+  .word  EXTI1_IRQHandler
+  .word  EXTI2_IRQHandler
+  .word  EXTI3_IRQHandler
+  .word  EXTI4_IRQHandler
+  .word  DMA1_Channel1_IRQHandler
+  .word  DMA1_Channel2_IRQHandler
+  .word  DMA1_Channel3_IRQHandler
+  .word  DMA1_Channel4_IRQHandler
+  .word  DMA1_Channel5_IRQHandler
+  .word  DMA1_Channel6_IRQHandler
+  .word  DMA1_Channel7_IRQHandler
+  .word  ADC1_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  EXTI9_5_IRQHandler
+  .word  TIM1_BRK_TIM15_IRQHandler
+  .word  TIM1_UP_TIM16_IRQHandler
+  .word  TIM1_TRG_COM_TIM17_IRQHandler
+  .word  TIM1_CC_IRQHandler
+  .word  TIM2_IRQHandler
+  .word  TIM3_IRQHandler
+  .word  0
+  .word  I2C1_EV_IRQHandler
+  .word  I2C1_ER_IRQHandler
+  .word  0
+  .word  0
+  .word  SPI1_IRQHandler
+  .word  0
+  .word  USART1_IRQHandler
+  .word  USART2_IRQHandler
+  .word  0
+  .word  EXTI15_10_IRQHandler
+  .word  RTCAlarm_IRQHandler
+  .word  CEC_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  TIM6_DAC_IRQHandler
+  .word  TIM7_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM          /* @0x01CC. This is for boot in RAM mode for 
+                            STM32F10x Low Density Value Line devices. */
+   
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*******************************************************************************/
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM15_IRQHandler
+  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  CEC_IRQHandler
+  .thumb_set CEC_IRQHandler,Default_Handler
+
+  .weak  TIM6_DAC_IRQHandler
+  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler  
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s
index bec2639..34c987d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/TrueSTUDIO/startup_stm32f10x_md.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md.s
@@ -2,14 +2,14 @@
   ******************************************************************************
   * @file      startup_stm32f10x_md.s
   * @author    MCD Application Team
-  * @version   V3.5.0
-  * @date      11-March-2011
-  * @brief     STM32F10x Medium Density Devices vector table for Atollic toolchain.
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
   *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
+  *                - Configure the clock system 
   *                - Branches to main in the C library (which eventually
   *                  calls main()).
   *            After Reset the Cortex-M3 processor is in Thread mode,
@@ -17,17 +17,23 @@
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
-
+    
   .syntax unified
 	.cpu cortex-m3
 	.fpu softvfp
@@ -36,10 +42,10 @@
 .global	g_pfnVectors
 .global	Default_Handler
 
-/* start address for the initialization values of the .data section.
+/* start address for the initialization values of the .data section. 
 defined in linker script */
 .word	_sidata
-/* start address for the .data section. defined in linker script */
+/* start address for the .data section. defined in linker script */  
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
@@ -53,7 +59,7 @@ defined in linker script */
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
- *          supplied main() routine is called.
+ *          supplied main() routine is called. 
  * @param  None
  * @retval : None
 */
@@ -61,9 +67,9 @@ defined in linker script */
     .section	.text.Reset_Handler
 	.weak	Reset_Handler
 	.type	Reset_Handler, %function
-Reset_Handler:
+Reset_Handler:	
 
-/* Copy the data segment initializers from flash to SRAM */
+/* Copy the data segment initializers from flash to SRAM */  
   movs	r1, #0
   b	LoopCopyDataInit
 
@@ -72,7 +78,7 @@ CopyDataInit:
 	ldr	r3, [r3, r1]
 	str	r3, [r0, r1]
 	adds	r1, r1, #4
-
+    
 LoopCopyDataInit:
 	ldr	r0, =_sdata
 	ldr	r3, =_edata
@@ -81,32 +87,28 @@ LoopCopyDataInit:
 	bcc	CopyDataInit
 	ldr	r2, =_sbss
 	b	LoopFillZerobss
-/* Zero fill the bss segment. */
+/* Zero fill the bss segment. */  
 FillZerobss:
 	movs	r3, #0
 	str	r3, [r2], #4
-
+    
 LoopFillZerobss:
 	ldr	r3, = _ebss
 	cmp	r2, r3
 	bcc	FillZerobss
-
 /* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
+  bl  SystemInit 	
 /* Call the application's entry point.*/
 	bl	main
-	bx	lr
+	bx	lr    
 .size	Reset_Handler, .-Reset_Handler
 
 /**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt. This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
+ * @param  None     
+ * @retval None       
 */
     .section	.text.Default_Handler,"ax",%progbits
 Default_Handler:
@@ -119,12 +121,12 @@ Infinite_Loop:
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
 *
-******************************************************************************/
+******************************************************************************/    
  	.section	.isr_vector,"a",%progbits
 	.type	g_pfnVectors, %object
 	.size	g_pfnVectors, .-g_pfnVectors
-
-
+    
+    
 g_pfnVectors:
 	.word	_estack
 	.word	Reset_Handler
@@ -184,7 +186,7 @@ g_pfnVectors:
 	.word	USART3_IRQHandler
 	.word	EXTI15_10_IRQHandler
 	.word	RTCAlarm_IRQHandler
-	.word	USBWakeUp_IRQHandler
+	.word	USBWakeUp_IRQHandler	
   .word	0
 	.word	0
 	.word	0
@@ -192,26 +194,26 @@ g_pfnVectors:
 	.word	0
 	.word	0
 	.word	0
-	.word	BootRAM          /* @0x108. This is for boot in RAM mode for
+	.word	BootRAM          /* @0x108. This is for boot in RAM mode for 
                             STM32F10x Medium Density devices. */
-
+   
 /*******************************************************************************
 *
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
 * this definition.
 *
 *******************************************************************************/
-
+    
   .weak	NMI_Handler
 	.thumb_set NMI_Handler,Default_Handler
-
+	
   .weak	HardFault_Handler
 	.thumb_set HardFault_Handler,Default_Handler
-
+	
   .weak	MemManage_Handler
 	.thumb_set MemManage_Handler,Default_Handler
-
+	
   .weak	BusFault_Handler
 	.thumb_set BusFault_Handler,Default_Handler
 
@@ -359,5 +361,4 @@ g_pfnVectors:
 	.weak	USBWakeUp_IRQHandler
 	.thumb_set USBWakeUp_IRQHandler,Default_Handler
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
-
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s
new file mode 100644
index 0000000..896bb79
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_md_vl.s
@@ -0,0 +1,405 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_md_vl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x Medium Density Value Line Devices vector table for RIDE7
+  *            toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system                 
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval None
+*/
+
+  .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b     LoopCopyDataInit
+
+CopyDataInit:
+  ldr   r3, =_sidata
+  ldr   r3, [r3, r1]
+  str   r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr   r0, =_sdata
+  ldr   r3, =_edata
+  adds  r2, r0, r1
+  cmp   r2, r3
+  bcc   CopyDataInit
+  ldr   r2, =_sbss
+  b     LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str   r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr   r3, = _ebss
+  cmp   r2, r3
+  bcc   FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl    main
+  bx    lr    
+.size   Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt. This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+  .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+******************************************************************************/    
+  .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler
+  .word  PVD_IRQHandler
+  .word  TAMPER_IRQHandler
+  .word  RTC_IRQHandler
+  .word  FLASH_IRQHandler
+  .word  RCC_IRQHandler
+  .word  EXTI0_IRQHandler
+  .word  EXTI1_IRQHandler
+  .word  EXTI2_IRQHandler
+  .word  EXTI3_IRQHandler
+  .word  EXTI4_IRQHandler
+  .word  DMA1_Channel1_IRQHandler
+  .word  DMA1_Channel2_IRQHandler
+  .word  DMA1_Channel3_IRQHandler
+  .word  DMA1_Channel4_IRQHandler
+  .word  DMA1_Channel5_IRQHandler
+  .word  DMA1_Channel6_IRQHandler
+  .word  DMA1_Channel7_IRQHandler
+  .word  ADC1_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  EXTI9_5_IRQHandler
+  .word  TIM1_BRK_TIM15_IRQHandler
+  .word  TIM1_UP_TIM16_IRQHandler
+  .word  TIM1_TRG_COM_TIM17_IRQHandler
+  .word  TIM1_CC_IRQHandler
+  .word  TIM2_IRQHandler
+  .word  TIM3_IRQHandler
+  .word  TIM4_IRQHandler
+  .word  I2C1_EV_IRQHandler
+  .word  I2C1_ER_IRQHandler
+  .word  I2C2_EV_IRQHandler
+  .word  I2C2_ER_IRQHandler
+  .word  SPI1_IRQHandler
+  .word  SPI2_IRQHandler
+  .word  USART1_IRQHandler
+  .word  USART2_IRQHandler
+  .word  USART3_IRQHandler
+  .word  EXTI15_10_IRQHandler
+  .word  RTCAlarm_IRQHandler
+  .word  CEC_IRQHandler  
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0  
+  .word  0
+  .word  0
+  .word  0
+  .word  TIM6_DAC_IRQHandler
+  .word  TIM7_IRQHandler  
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM          /* @0x01CC. This is for boot in RAM mode for 
+                            STM32F10x Medium Value Line Density devices. */
+   
+/*******************************************************************************
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*******************************************************************************/
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM15_IRQHandler
+  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM16_IRQHandler
+  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM17_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  CEC_IRQHandler
+  .thumb_set CEC_IRQHandler,Default_Handler
+
+  .weak  TIM6_DAC_IRQHandler
+  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler  
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s
new file mode 100644
index 0000000..a0fa498
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/gcc_ride7/startup_stm32f10x_xl.s
@@ -0,0 +1,471 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f10x_xl.s
+  * @author    MCD Application Team
+  * @version   V3.6.1
+  * @date      09-March-2012
+  * @brief     STM32F10x XL-Density Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3210E-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler
+  .word  PVD_IRQHandler
+  .word  TAMPER_IRQHandler
+  .word  RTC_IRQHandler
+  .word  FLASH_IRQHandler
+  .word  RCC_IRQHandler
+  .word  EXTI0_IRQHandler
+  .word  EXTI1_IRQHandler
+  .word  EXTI2_IRQHandler
+  .word  EXTI3_IRQHandler
+  .word  EXTI4_IRQHandler
+  .word  DMA1_Channel1_IRQHandler
+  .word  DMA1_Channel2_IRQHandler
+  .word  DMA1_Channel3_IRQHandler
+  .word  DMA1_Channel4_IRQHandler
+  .word  DMA1_Channel5_IRQHandler
+  .word  DMA1_Channel6_IRQHandler
+  .word  DMA1_Channel7_IRQHandler
+  .word  ADC1_2_IRQHandler
+  .word  USB_HP_CAN1_TX_IRQHandler
+  .word  USB_LP_CAN1_RX0_IRQHandler
+  .word  CAN1_RX1_IRQHandler
+  .word  CAN1_SCE_IRQHandler
+  .word  EXTI9_5_IRQHandler
+  .word  TIM1_BRK_TIM9_IRQHandler
+  .word  TIM1_UP_TIM10_IRQHandler
+  .word  TIM1_TRG_COM_TIM11_IRQHandler
+  .word  TIM1_CC_IRQHandler
+  .word  TIM2_IRQHandler
+  .word  TIM3_IRQHandler
+  .word  TIM4_IRQHandler
+  .word  I2C1_EV_IRQHandler
+  .word  I2C1_ER_IRQHandler
+  .word  I2C2_EV_IRQHandler
+  .word  I2C2_ER_IRQHandler
+  .word  SPI1_IRQHandler
+  .word  SPI2_IRQHandler
+  .word  USART1_IRQHandler
+  .word  USART2_IRQHandler
+  .word  USART3_IRQHandler
+  .word  EXTI15_10_IRQHandler
+  .word  RTCAlarm_IRQHandler
+  .word  USBWakeUp_IRQHandler
+  .word  TIM8_BRK_TIM12_IRQHandler
+  .word  TIM8_UP_TIM13_IRQHandler
+  .word  TIM8_TRG_COM_TIM14_IRQHandler
+  .word  TIM8_CC_IRQHandler
+  .word  ADC3_IRQHandler
+  .word  FSMC_IRQHandler
+  .word  SDIO_IRQHandler
+  .word  TIM5_IRQHandler
+  .word  SPI3_IRQHandler
+  .word  UART4_IRQHandler
+  .word  UART5_IRQHandler
+  .word  TIM6_IRQHandler
+  .word  TIM7_IRQHandler
+  .word  DMA2_Channel1_IRQHandler
+  .word  DMA2_Channel2_IRQHandler
+  .word  DMA2_Channel3_IRQHandler
+  .word  DMA2_Channel4_5_IRQHandler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
+                         STM32F10x XL Density devices. */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+    
+  .weak  NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+  
+  .weak  HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+  
+  .weak  MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+  
+  .weak  BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak  UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak  SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak  DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak  PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak  SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak  WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak  PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak  TAMPER_IRQHandler
+  .thumb_set TAMPER_IRQHandler,Default_Handler
+
+  .weak  RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak  FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak  RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak  EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak  EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak  EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak  EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak  EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak  DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak  ADC1_2_IRQHandler
+  .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+  .weak  USB_HP_CAN1_TX_IRQHandler
+  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+  .weak  USB_LP_CAN1_RX0_IRQHandler
+  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+  .weak  CAN1_RX1_IRQHandler
+  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+  .weak  CAN1_SCE_IRQHandler
+  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+  .weak  EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak  TIM1_BRK_TIM9_IRQHandler
+  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+  .weak  TIM1_UP_TIM10_IRQHandler
+  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+  .weak  TIM1_TRG_COM_TIM11_IRQHandler
+  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+  .weak  TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak  TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak  TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak  TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak  I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak  I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak  I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak  I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak  SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak  SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak  USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak  USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak  USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak  EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak  RTCAlarm_IRQHandler
+  .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+  .weak  USBWakeUp_IRQHandler
+  .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+  .weak  TIM8_BRK_TIM12_IRQHandler
+  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+  .weak  TIM8_UP_TIM13_IRQHandler
+  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+  .weak  TIM8_TRG_COM_TIM14_IRQHandler
+  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+  .weak  TIM8_CC_IRQHandler
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+  .weak  ADC3_IRQHandler
+  .thumb_set ADC3_IRQHandler,Default_Handler
+
+  .weak  FSMC_IRQHandler
+  .thumb_set FSMC_IRQHandler,Default_Handler
+
+  .weak  SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak  TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+
+  .weak  SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak  UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak  UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+
+  .weak  TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak  TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak  DMA2_Channel4_5_IRQHandler
+  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..4af1336
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd.s
@@ -0,0 +1,503 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x High Density Devices vector table for EWARM 
+;*                      toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Configure the clock system and the external SRAM 
+;*                        mounted on STM3210E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR address,
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;     
+  
+    MODULE  ?cstartup
+        
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+       
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler         ; Tamper
+        DCD     RTC_IRQHandler            ; RTC
+        DCD     FLASH_IRQHandler          ; Flash
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+        DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
+        DCD     TIM8_UP_IRQHandler        ; TIM8 Update
+        DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
+        DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
+        DCD     ADC3_IRQHandler           ; ADC3
+        DCD     FSMC_IRQHandler           ; FSMC
+        DCD     SDIO_IRQHandler           ; SDIO
+        DCD     TIM5_IRQHandler           ; TIM5
+        DCD     SPI3_IRQHandler           ; SPI3
+        DCD     UART4_IRQHandler          ; UART4
+        DCD     UART5_IRQHandler          ; UART5
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel1
+        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel2
+        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel3
+        DCD     DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+               
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USB_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+        B USB_HP_CAN1_TX_IRQHandler
+
+        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+        B USB_LP_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK FSMC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler
+        B FSMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+        B DMA2_Channel4_5_IRQHandler
+        
+        
+        END
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s
new file mode 100644
index 0000000..7390a93
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_hd_vl.s
@@ -0,0 +1,468 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_hd_vl.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x High Density Value Line Devices vector table 
+;*                      for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Configure the clock system and the external SRAM 
+;*                        mounted on STM32100E-EVAL board to be used as data 
+;*                        memory (optional, to be enabled by user)
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler               ; Window Watchdog
+        DCD     PVD_IRQHandler                ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler             ; Tamper
+        DCD     RTC_IRQHandler                ; RTC
+        DCD     FLASH_IRQHandler              ; Flash
+        DCD     RCC_IRQHandler                ; RCC
+        DCD     EXTI0_IRQHandler              ; EXTI Line 0
+        DCD     EXTI1_IRQHandler              ; EXTI Line 1
+        DCD     EXTI2_IRQHandler              ; EXTI Line 2
+        DCD     EXTI3_IRQHandler              ; EXTI Line 3
+        DCD     EXTI4_IRQHandler              ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler      ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler      ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler      ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler      ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler      ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler      ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler      ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler               ; ADC1
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     EXTI9_5_IRQHandler            ; EXTI Line 9..5
+        DCD     TIM1_BRK_TIM15_IRQHandler     ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler      ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler            ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler               ; TIM2
+        DCD     TIM3_IRQHandler               ; TIM3
+        DCD     TIM4_IRQHandler               ; TIM4
+        DCD     I2C1_EV_IRQHandler            ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler            ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler            ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler            ; I2C2 Error
+        DCD     SPI1_IRQHandler               ; SPI1
+        DCD     SPI2_IRQHandler               ; SPI2
+        DCD     USART1_IRQHandler             ; USART1
+        DCD     USART2_IRQHandler             ; USART2
+        DCD     USART3_IRQHandler             ; USART3
+        DCD     EXTI15_10_IRQHandler          ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler           ; RTC Alarm through EXTI Line
+        DCD     CEC_IRQHandler                ; HDMI-CEC
+        DCD     TIM12_IRQHandler              ; TIM12
+        DCD     TIM13_IRQHandler              ; TIM13
+        DCD     TIM14_IRQHandler              ; TIM14
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     0                             ; Reserved
+        DCD     TIM5_IRQHandler               ; TIM5
+        DCD     SPI3_IRQHandler               ; SPI3
+        DCD     UART4_IRQHandler              ; UART4
+        DCD     UART5_IRQHandler              ; UART5                       
+        DCD     TIM6_DAC_IRQHandler           ; TIM6 and DAC underrun
+        DCD     TIM7_IRQHandler               ; TIM7     
+        DCD     DMA2_Channel1_IRQHandler      ; DMA2 Channel1
+        DCD     DMA2_Channel2_IRQHandler      ; DMA2 Channel2
+        DCD     DMA2_Channel3_IRQHandler      ; DMA2 Channel3
+        DCD     DMA2_Channel4_5_IRQHandler    ; DMA2 Channel4 & Channel5                   
+        DCD     DMA2_Channel5_IRQHandler      ; DMA2 Channel5
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM12_IRQHandler
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM13_IRQHandler
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+        
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler                
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+        B DMA2_Channel4_5_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+                
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..cfbaa95
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_ld.s
@@ -0,0 +1,373 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_ld.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x Low Density Devices vector table for EWARM
+;*                      toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Configure the clock system
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler         ; Tamper
+        DCD     RTC_IRQHandler            ; RTC
+        DCD     FLASH_IRQHandler          ; Flash
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     0                         ; Reserved
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     0                         ; Reserved
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     0                         ; Reserved
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+        
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+        
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+        
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+        
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+        
+        PUBWEAK USB_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+        B USB_HP_CAN1_TX_IRQHandler
+        
+        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+        B USB_LP_CAN1_RX0_IRQHandler
+        
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+        
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+        
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+        
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+        
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+        
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+                      
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s
new file mode 100644
index 0000000..db28cda
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_md.s
@@ -0,0 +1,398 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f10x_md.s
+;* Author             : MCD Application Team
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
+;* Description        : STM32F10x Medium Density Devices vector table for 
+;*                      EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Configure the clock system
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler         ; Tamper
+        DCD     RTC_IRQHandler            ; RTC
+        DCD     FLASH_IRQHandler          ; Flash
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USB_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+        B USB_HP_CAN1_TX_IRQHandler
+
+        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+        B USB_LP_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s
index 029761a..c85fb39 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/iar/startup_stm32f10x_xl.s
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
 ;* File Name          : startup_stm32f10x_xl.s
 ;* Author             : MCD Application Team
-;* Version            : V3.5.0
-;* Date               : 11-March-2011
+;* Version            : V3.6.1
+;* Date               : 09-March-2012
 ;* Description        : STM32F10x XL-Density Devices vector table for EWARM 
 ;*                      toolchain.
 ;*                      This module performs:
@@ -15,12 +15,19 @@
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
 ;*******************************************************************************
 ;
 ;
@@ -493,4 +500,4 @@ DMA2_Channel4_5_IRQHandler
         
         END
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/system_stm32f30x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/system_stm32f30x.h
new file mode 100644
index 0000000..678740a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include/system_stm32f30x.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    04-September-2012
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F30x devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F30X_H
+#define __SYSTEM_STM32F30X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F30x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F30x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F30X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s
new file mode 100644
index 0000000..4acbed8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s
@@ -0,0 +1,469 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f30x.s
+  * @author    MCD Application Team
+  * @version   V1.0.0
+  * @date      04-September-2012
+  * @brief     stm32f30x vector table for Atollic TrueSTUDIO toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_TS_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	USBWakeUp_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	ADC4_IRQHandler
+	.word	0
+	.word	0
+	.word	COMP1_2_3_IRQHandler
+	.word	COMP4_5_6_IRQHandler
+	.word	COMP7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	USB_HP_IRQHandler
+	.word	USB_LP_IRQHandler
+	.word	USBWakeUp_RMP_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_STAMP_IRQHandler
+	.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_TS_IRQHandler
+	.thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	ADC4_IRQHandler
+	.thumb_set ADC4_IRQHandler,Default_Handler	
+	
+	.weak	COMP1_2_3_IRQHandler
+	.thumb_set COMP1_2_3_IRQHandler,Default_Handler
+	
+	.weak	COMP4_5_6_IRQHandler
+	.thumb_set COMP4_5_6_IRQHandler,Default_Handler
+	
+	.weak	COMP7_IRQHandler
+	.thumb_set COMP7_IRQHandler,Default_Handler	
+	
+	.weak	USB_HP_IRQHandler
+	.thumb_set USB_HP_IRQHandler,Default_Handler
+	
+	.weak	USB_LP_IRQHandler
+	.thumb_set USB_LP_IRQHandler,Default_Handler
+	
+	.weak	USBWakeUp_RMP_IRQHandler
+	.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s
new file mode 100644
index 0000000..897368a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s
@@ -0,0 +1,399 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f30x.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 04-September-2012
+;* Description        : STM32F30x devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMPER_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_TS_IRQHandler               ; EXTI Line2 and Touch                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1                                   
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2                                   
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3                                   
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4                                   
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5                                   
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6                                   
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7                                   
+                DCD     ADC1_2_IRQHandler                 ; ADC1 and ADC2                            
+                DCD     USB_HP_CAN1_TX_IRQHandler         ; USB Device High Priority or CAN1 TX 
+                DCD     USB_LP_CAN1_RX0_IRQHandler        ; USB Device Low Priority or CAN1 RX0 
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15                   
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16                 
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     USBWakeUp_IRQHandler              ; USB Wakeup through EXTI line                        
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break                  
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update                
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     ADC3_IRQHandler                   ; ADC3                                           
+                DCD     0                                 ; Reserved                                            
+                DCD     0                                 ; Reserved                                            
+                DCD     0                                 ; Reserved                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1                                   
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2                                   
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3                                   
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4                                   
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5                                   
+                DCD     ADC4_IRQHandler                   ; ADC4                                        
+                DCD     0                                 ; Reserved                      
+                DCD     0                                 ; Reserved                                               
+                DCD     COMP1_2_3_IRQHandler              ; COMP1, COMP2 and COMP3                                               
+                DCD     COMP4_5_6_IRQHandler              ; COMP4, COMP5 and COMP6                                              
+                DCD     COMP7_IRQHandler                  ; COMP7                                               
+                DCD     0                                 ; Reserved                                      
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                           
+                DCD     0                                 ; Reserved                                             
+                DCD     0                                 ; Reserved                                             
+                DCD     USB_HP_IRQHandler                 ; USB High Priority remap                        
+                DCD     USB_LP_IRQHandler                 ; USB Low Priority remap                     
+                DCD     USBWakeUp_RMP_IRQHandler          ; USB Wakeup remap through EXTI                         
+                DCD     0                                 ; Reserved                                       
+                DCD     0                                 ; Reserved                                        
+                DCD     0                                 ; Reserved                                      
+                DCD     0                                 ; Reserved 
+                DCD     FPU_IRQHandler                    ; FPU
+                         
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMPER_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_TS_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]                                
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]                                   
+                EXPORT  ADC1_2_IRQHandler                 [WEAK]                         
+                EXPORT  USB_HP_CAN1_TX_IRQHandler         [WEAK]                                                
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler        [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM15_IRQHandler         [WEAK]                  
+                EXPORT  TIM1_UP_TIM16_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM17_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  USBWakeUp_IRQHandler               [WEAK]                        
+                EXPORT  TIM8_BRK_IRQHandler               [WEAK]                 
+                EXPORT  TIM8_UP_IRQHandler                [WEAK]                 
+                EXPORT  TIM8_TRG_COM_IRQHandler           [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  ADC3_IRQHandler                   [WEAK]                                   
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]                                  
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]                                   
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]                                    
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]                                    
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  ADC4_IRQHandler                   [WEAK]                                 
+                EXPORT  COMP1_2_3_IRQHandler              [WEAK]                                               
+                EXPORT  COMP4_5_6_IRQHandler              [WEAK]                                               
+                EXPORT  COMP7_IRQHandler                  [WEAK]                                               
+                EXPORT  USB_HP_IRQHandler                 [WEAK]                      
+                EXPORT  USB_LP_IRQHandler                 [WEAK]                      
+                EXPORT  USBWakeUp_RMP_IRQHandler              [WEAK]                        
+                EXPORT  FPU_IRQHandler                    [WEAK]                
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMPER_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_TS_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Channel1_IRQHandler                                       
+DMA1_Channel2_IRQHandler                                          
+DMA1_Channel3_IRQHandler                                          
+DMA1_Channel4_IRQHandler                                          
+DMA1_Channel5_IRQHandler                                          
+DMA1_Channel6_IRQHandler                                          
+DMA1_Channel7_IRQHandler                                          
+ADC1_2_IRQHandler                                         
+USB_HP_CAN1_TX_IRQHandler                                                            
+USB_LP_CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM15_IRQHandler                        
+TIM1_UP_TIM16_IRQHandler                      
+TIM1_TRG_COM_TIM17_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+USBWakeUp_IRQHandler                                
+TIM8_BRK_IRQHandler                      
+TIM8_UP_IRQHandler                       
+TIM8_TRG_COM_IRQHandler  
+TIM8_CC_IRQHandler  
+ADC3_IRQHandler                                             
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Channel1_IRQHandler                                          
+DMA2_Channel2_IRQHandler                                           
+DMA2_Channel3_IRQHandler                                           
+DMA2_Channel4_IRQHandler                                        
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler                                                          
+COMP4_5_6_IRQHandler                                                          
+COMP7_IRQHandler                                                          
+USB_HP_IRQHandler                           
+USB_LP_IRQHandler                            
+USBWakeUp_RMP_IRQHandler                                
+FPU_IRQHandler                                                 
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s
new file mode 100644
index 0000000..77efbdf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s
@@ -0,0 +1,465 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f30x.s
+  * @author    MCD Application Team
+  * @version   V1.0.0
+  * @date      04-Spetember-2012
+  * @brief     STM32F30x Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3230C-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_TS_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	USB_HP_CAN1_TX_IRQHandler
+	.word	USB_LP_CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	USBWakeUp_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	ADC4_IRQHandler
+	.word	0
+	.word	0
+	.word	COMP1_2_3_IRQHandler
+	.word	COMP4_5_6_IRQHandler
+	.word	COMP7_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	USB_HP_IRQHandler
+	.word	USB_LP_IRQHandler
+	.word	USBWakeUp_RMP_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_STAMP_IRQHandler
+	.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_TS_IRQHandler
+	.thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	USB_HP_CAN1_TX_IRQHandler
+	.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	USB_LP_CAN1_RX0_IRQHandler
+	.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	ADC4_IRQHandler
+	.thumb_set ADC4_IRQHandler,Default_Handler	
+	
+	.weak	COMP1_2_3_IRQHandler
+	.thumb_set COMP1_2_3_IRQHandler,Default_Handler
+	
+	.weak	COMP4_5_6_IRQHandler
+	.thumb_set COMP4_5_6_IRQHandler,Default_Handler
+	
+	.weak	COMP7_IRQHandler
+	.thumb_set COMP7_IRQHandler,Default_Handler	
+	
+	.weak	USB_HP_IRQHandler
+	.thumb_set USB_HP_IRQHandler,Default_Handler
+	
+	.weak	USB_LP_IRQHandler
+	.thumb_set USB_LP_IRQHandler,Default_Handler
+	
+	.weak	USBWakeUp_RMP_IRQHandler
+	.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s
new file mode 100644
index 0000000..d8db7d0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s
@@ -0,0 +1,554 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f30x.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 04-Sptember-2012
+;* Description        : STM32F30x devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMPER_STAMP_IRQHandler           ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_TS_IRQHandler               ; EXTI Line2 and Touch Sense                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1                                   
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2                                   
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3                                   
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4                                   
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5                                   
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6                                   
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7                                   
+                DCD     ADC1_2_IRQHandler                 ; ADC1 and ADC2                            
+                DCD     USB_HP_CAN1_TX_IRQHandler         ; USB Device High Priority or CAN1 TX                                               
+                DCD     USB_LP_CAN1_RX0_IRQHandler        ; USB Device Low Priority or CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15                   
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16                 
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     USBWakeUp_IRQHandler              ; USB Wakeup through EXTI line                        
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break                  
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update                
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     ADC3_IRQHandler                   ; ADC3                                           
+                DCD     0                                 ; Reserved                                            
+                DCD     0                                 ; Reserved                                            
+                DCD     0                                 ; Reserved                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1                                   
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2                                   
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3                                   
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4                                   
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5                                   
+                DCD     ADC4_IRQHandler                   ; ADC4                                        
+                DCD     0                                 ; Reserved                      
+                DCD     0                                 ; Reserved                                               
+                DCD     COMP1_2_3_IRQHandler              ; COMP1, COMP2 and COMP3                                               
+                DCD     COMP4_5_6_IRQHandler              ; COMP4, COMP5 and COMP6                                              
+                DCD     COMP7_IRQHandler                  ; COMP7                                               
+                DCD     0                                 ; Reserved                                      
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                   
+                DCD     0                                 ; Reserved                                           
+                DCD     0                                 ; Reserved                                             
+                DCD     0                                 ; Reserved                                             
+                DCD     USB_HP_IRQHandler                 ; USB High Priority remap                       
+                DCD     USB_LP_IRQHandler                 ; USB Low Priority remap                    
+                DCD     USBWakeUp_RMP_IRQHandler          ; USB Wakeup remap through EXTI                         
+                DCD     0                                 ; Reserved                                       
+                DCD     0                                 ; Reserved                                        
+                DCD     0                                 ; Reserved                                      
+                DCD     0                                 ; Reserved 
+                DCD     FPU_IRQHandler                    ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TAMPER_STAMP_IRQHandler  
+        B TAMPER_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_TS_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_TS_IRQHandler  
+        B EXTI2_TS_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel1_IRQHandler  
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel2_IRQHandler  
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel3_IRQHandler  
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel4_IRQHandler  
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel5_IRQHandler  
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel6_IRQHandler  
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel7_IRQHandler  
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler  
+        B ADC1_2_IRQHandler
+
+        PUBWEAK USB_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+USB_HP_CAN1_TX_IRQHandler  
+        B USB_HP_CAN1_TX_IRQHandler
+
+        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+USB_LP_CAN1_RX0_IRQHandler  
+        B USB_LP_CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_BRK_TIM15_IRQHandler  
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_UP_TIM16_IRQHandler  
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_TRG_COM_TIM17_IRQHandler  
+        B TIM1_TRG_COM_TIM17_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+USBWakeUp_IRQHandler  
+        B USBWakeUp_IRQHandler
+      
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_BRK_IRQHandler  
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_UP_IRQHandler  
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_TRG_COM_IRQHandler  
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+ADC3_IRQHandler  
+        B ADC3_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel1_IRQHandler  
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel2_IRQHandler  
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel3_IRQHandler  
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel4_IRQHandler  
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel5_IRQHandler  
+        B DMA2_Channel5_IRQHandler
+
+
+        PUBWEAK ADC4_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+ADC4_IRQHandler  
+        B ADC4_IRQHandler
+
+        PUBWEAK COMP1_2_3_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+COMP1_2_3_IRQHandler  
+        B COMP1_2_3_IRQHandler
+
+        PUBWEAK COMP4_5_6_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+COMP4_5_6_IRQHandler  
+        B COMP4_5_6_IRQHandler
+
+        PUBWEAK COMP7_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+COMP7_IRQHandler  
+        B COMP7_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler  
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+USB_LP_IRQHandler  
+        B USB_LP_IRQHandler
+
+        PUBWEAK USBWakeUp_RMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+USBWakeUp_RMP_IRQHandler  
+        B USBWakeUp_RMP_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h
new file mode 100644
index 0000000..9cbd5ae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include/stm32f37x.h
@@ -0,0 +1,5438 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral registers definitions, bits 
+  *          definitions and memory mapping for STM32F37x devices.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral registers declarations and bits definition
+  *           - Macros to access peripheral registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+  * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f37x
+  * @{
+  */
+    
+#ifndef __STM32F37x_H
+#define __STM32F37x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F37X) 
+  #define STM32F37X
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32F37X)
+ #error "Please select first the target STM32F37X device used in your application (in stm32f37x.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+#if !defined  (HSE_VALUE) 
+ #define HSE_VALUE            ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+ #define HSE_STARTUP_TIMEOUT  ((uint16_t)0x0500)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+
+#if !defined  (HSI_VALUE) 
+ #define HSI_VALUE  ((uint32_t)8000000)
+#endif /* HSI_VALUE */                      /*!< Value of the Internal High Speed oscillator in Hz.
+                                            The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)40000)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+/**
+ * @brief STM32F37x Standard Peripherals Library version number V1.0.0
+   */
+#define __STM32F37X_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F37X_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F37X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F37X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F37X_STDPERIPH_VERSION       ( (__STM32F37X_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F37X_STDPERIPH_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1         /*!< STM32F37X provide an MPU */
+#define __NVIC_PRIO_BITS          4         /*!< STM32F37X uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1         /*!< STM32F37X provide an FPU */
+
+
+/**
+ * @brief STM32F37X Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line 19          */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line 20                     */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_TS_IRQn               = 8,      /*!< EXTI Line2 Interrupt and Touch Sense Interrupt                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
+  ADC1_IRQn                   = 18,     /*!< ADC1 Interrupts                                                   */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                  */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                 */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                 */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                 */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM15_IRQn                  = 24,     /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 25,     /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 26,     /*!< TIM17 global Interrupt                                            */
+  TIM18_DAC2_IRQn             = 27,     /*!< TIM18 global Interrupt and DAC2 underrun Interrupt                */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  CEC_IRQn                    = 42,     /*!< CEC Interrupt                                                     */    
+  TIM12_IRQn                  = 43,     /*!< TIM12 global interrupt                                            */
+  TIM13_IRQn                  = 44,     /*!< TIM13 global interrupt                                            */
+  TIM14_IRQn                  = 45,     /*!< TIM14 global interrupt                                            */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  TIM6_DAC1_IRQn              = 54,     /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
+  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  SDADC1_IRQn                 = 61,     /*!< ADC Sigma Delta 1 global Interrupt                                */
+  SDADC2_IRQn                 = 62,     /*!< ADC Sigma Delta 2 global Interrupt                                */
+  SDADC3_IRQn                 = 63,     /*!< ADC Sigma Delta 1 global Interrupt                                */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 global Interrupt                                  */
+  USB_HP_IRQn                 = 74,     /*!< USB High Priority global Interrupt                                */
+  USB_LP_IRQn                 = 75,     /*!< USB Low Priority global Interrupt                                 */
+  USBWakeUp_IRQn              = 76,     /*!< USB Wakeup Interrupt                                              */
+  TIM19_IRQn                  = 78,     /*!< TIM19 global Interrupt                                            */
+  FPU_IRQn                    = 81      /*!< Floating point Interrupt                                          */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"            /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f37x.h"    /* STM32F37x System Header */
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;    /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;   /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;   /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1; /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2; /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;   /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;   /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;  /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;  /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;  /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;  /*!< ADC injected sequence register,              Address offset: 0x38 */
+  __IO uint32_t JDR1;  /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;  /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;  /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;  /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;    /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+  
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+  
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief Consumer Electronics Control     
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/** 
+  * @brief Analog Comparators 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< FLASH access control register,              Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!< FLASH key register,                         Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!< FLASH option key register,                  Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< FLASH status register,                      Address offset: 0x0C */
+  __IO uint32_t CR;           /*!< FLASH control register,                     Address offset: 0x10 */
+  __IO uint32_t AR;           /*!< FLASH address register,                     Address offset: 0x14 */
+  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                   */
+  __IO uint32_t OBR;          /*!< FLASH Option byte register,                 Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!< FLASH Write register,                       Address offset: 0x20 */
+  
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+  __IO uint16_t WRP2;         /*!<FLASH option byte write protection 2,          Address offset: 0x10 */
+  __IO uint16_t WRP3;         /*!<FLASH option byte write protection 3,          Address offset: 0x12 */
+} OB_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                      Address offset: 0x00 */
+       uint32_t RESERVED;    /*!< Reserved,                                                             0x04 */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG control register,                              Adress offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                      Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  
+}I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */ 
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */ 
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+  
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  uint32_t RESERVED0;       /*!< Reserved, 0x18                                                                 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                   Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                   Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                   Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                   Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                   Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                   Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                   Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                   Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                   Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                   Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                   Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                   Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                   Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Sigma-Delta Analog to Digital Converter (SDADC)  
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;          /*!< SDADC control register 1,                        Address offset: 0x00 */
+  __IO uint32_t CR2;          /*!< SDADC control register 2,                        Address offset: 0x04 */
+  __IO uint32_t ISR;          /*!< SDADC interrupt and status register,             Address offset: 0x08 */
+  __IO uint32_t CLRISR;       /*!< SDADC clear interrupt and status register,       Address offset: 0x0C */
+  __IO uint32_t RESERVED0;    /*!< Reserved, 0x10                                                        */
+  __IO uint32_t JCHGR;        /*!< SDADC injected channel group selection register, Address offset: 0x14 */
+  __IO uint32_t RESERVED1;    /*!< Reserved, 0x18                                                        */
+  __IO uint32_t RESERVED2;    /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t CONF0R;       /*!< SDADC configuration 0 register,                  Address offset: 0x20 */
+  __IO uint32_t CONF1R;       /*!< SDADC configuration 1 register,                  Address offset: 0x24 */
+  __IO uint32_t CONF2R;       /*!< SDADC configuration 2 register,                  Address offset: 0x28 */
+  __IO uint32_t RESERVED3[5]; /*!< Reserved, 0x2C - 0x3C                                                 */
+  __IO uint32_t CONFCHR1;     /*!< SDADC channel configuration register 1,          Address offset: 0x40 */
+  __IO uint32_t CONFCHR2;     /*!< SDADC channel configuration register 2,          Address offset: 0x44 */
+  __IO uint32_t RESERVED4[6]; /*!< Reserved, 0x48 - 0x5C                                                 */
+  __IO uint32_t JDATAR;       /*!< SDADC data register for injected group,          Address offset: 0x60 */
+  __IO uint32_t RDATAR;       /*!< SDADC data register for the regular channel,     Address offset: 0x64 */
+  __IO uint32_t RESERVED5[2]; /*!< Reserved, 0x68 - 0x6C                                                 */
+  __IO uint32_t JDATA12R;     /*!< SDADC1 and SDADC2 injected data register,        Address offset: 0x70 */
+  __IO uint32_t RDATA12R;     /*!< SDADC1 and SDADC2 regular data register,         Address offset: 0x74 */
+  __IO uint32_t JDATA13R;     /*!< SDADC1 and SDADC3 injected data register,        Address offset: 0x78 */
+  __IO uint32_t RDATA13R;     /*!< SDADC1 and SDADC3 regular data register,         Address offset: 0x7C */
+} SDADC_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef; 
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
+#define DAC2_BASE             (APB1PERIPH_BASE + 0x9800)
+#define TIM18_BASE            (APB1PERIPH_BASE + 0x9C00)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
+#define COMP_BASE             (APB2PERIPH_BASE + 0x001C)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM19_BASE            (APB2PERIPH_BASE + 0x5C00)
+#define SDADC1_BASE           (APB2PERIPH_BASE + 0x6000)
+#define SDADC2_BASE           (APB2PERIPH_BASE + 0x6400)
+#define SDADC3_BASE           (APB2PERIPH_BASE + 0x6800)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHB1PERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHB1PERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHB1PERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHB1PERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHB1PERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHB1PERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHB1PERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHB1PERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHB1PERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHB1PERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHB1PERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHB1PERIPH_BASE + 0x0458)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)     /*!< Flash Option Bytes base address */
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400)
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define TIM18               ((TIM_TypeDef *) TIM18_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM19               ((TIM_TypeDef *) TIM19_BASE)
+#define SDADC1              ((SDADC_TypeDef *) SDADC1_BASE)
+#define SDADC2              ((SDADC_TypeDef *) SDADC2_BASE)
+#define SDADC3              ((SDADC_TypeDef *) SDADC3_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter SAR (ADC)               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)  /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)  /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)  /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)  /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)  /*!< Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)  /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)  /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)  /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)  /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)  /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)  /*!< Bit 4 */
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)  /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)  /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)  /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)  /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)  /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)  /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)  /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)  /*!< Discontinuous mode on injected channels */
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)  /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)  /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)  /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)  /*!< Bit 2 */
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)  /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)  /*!< Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)  /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)  /*!< Continuous Conversion */
+#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)  /*!< A/D Calibration */
+#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)  /*!< Reset Calibration */
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)  /*!< Direct Memory access mode */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)  /*!< Data Alignment */
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)  /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
+#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)  /*!< External Trigger Conversion mode for injected channels */
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)  /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)  /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)  /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)  /*!< Bit 2 */
+#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)  /*!< External Trigger Conversion mode for regular channels */
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)  /*!< Start Conversion of injected channels */
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)  /*!< Start Conversion of regular channels */
+#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)  /*!< Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)  /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)  /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)  /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)  /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)  /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)  /*!< Bit 0 */
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)  /*!< Bit 1 */
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)  /*!< Bit 2 */
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)  /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Controller Area Network (CAN )                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */
+
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */
+
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */
+
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */
+
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     CRC calculation unit (CRC)                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_POLSIZE                      ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define  CRC_CR_POLSIZE_0                    ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define  CRC_CR_POLSIZE_1                    ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define  CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital to Analog Converter (DAC)                          */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU (DBGMCU)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP        ((uint32_t)0x00000004)
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP        ((uint32_t)0x00000008)
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP       ((uint32_t)0x00000040)
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP       ((uint32_t)0x00000080)
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)
+#define  DBGMCU_APB1_FZ_DBG_TIM18_STOP       ((uint32_t)0x00000200)
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00000004)
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00000008)
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00000010)
+#define  DBGMCU_APB2_FZ_DBG_TIM19_STOP       ((uint32_t)0x00000020)
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller (DMA)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller (EXTI)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+#define  EXTI_IMR_MR28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+#define  EXTI_EMR_MR28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+#define  EXTI_RTSR_TR24                      ((uint32_t)0x01000000)        /*!< Rising trigger event configuration bit of line 24 */
+#define  EXTI_RTSR_TR25                      ((uint32_t)0x02000000)        /*!< Rising trigger event configuration bit of line 25 */
+#define  EXTI_RTSR_TR26                      ((uint32_t)0x04000000)        /*!< Rising trigger event configuration bit of line 26 */
+#define  EXTI_RTSR_TR27                      ((uint32_t)0x08000000)        /*!< Rising trigger event configuration bit of line 27 */
+#define  EXTI_RTSR_TR28                      ((uint32_t)0x10000000)        /*!< Rising trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+#define  EXTI_FTSR_TR24                      ((uint32_t)0x01000000)        /*!< Falling trigger event configuration bit of line 24 */
+#define  EXTI_FTSR_TR25                      ((uint32_t)0x02000000)        /*!< Falling trigger event configuration bit of line 25 */
+#define  EXTI_FTSR_TR26                      ((uint32_t)0x04000000)        /*!< Falling trigger event configuration bit of line 26 */
+#define  EXTI_FTSR_TR27                      ((uint32_t)0x08000000)        /*!< Falling trigger event configuration bit of line 27 */
+#define  EXTI_FTSR_TR28                      ((uint32_t)0x10000000)        /*!< Falling trigger event configuration bit of line 28 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+#define  EXTI_SWIER_SWIER24                  ((uint32_t)0x01000000)        /*!< Software Interrupt on line 24 */
+#define  EXTI_SWIER_SWIER25                  ((uint32_t)0x02000000)        /*!< Software Interrupt on line 25 */
+#define  EXTI_SWIER_SWIER26                  ((uint32_t)0x04000000)        /*!< Software Interrupt on line 26 */
+#define  EXTI_SWIER_SWIER27                  ((uint32_t)0x08000000)        /*!< Software Interrupt on line 27 */
+#define  EXTI_SWIER_SWIER28                  ((uint32_t)0x10000000)        /*!< Software Interrupt on line 28 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit for line 23 */
+#define  EXTI_PR_PR24                        ((uint32_t)0x01000000)        /*!< Pending bit for line 24 */
+#define  EXTI_PR_PR25                        ((uint32_t)0x02000000)        /*!< Pending bit for line 25 */
+#define  EXTI_PR_PR26                        ((uint32_t)0x04000000)        /*!< Pending bit for line 26 */
+#define  EXTI_PR_PR27                        ((uint32_t)0x08000000)        /*!< Pending bit for line 27 */
+#define  EXTI_PR_PR28                        ((uint32_t)0x10000000)        /*!< Pending bit for line 28 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!< Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!< Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< OptionBytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for FLASH_WRP0 register  ******************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP1 register  ******************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP2 register  ******************/
+#define  OB_WRP2_WRP2                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP2_nWRP2                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRP3 register  ******************/
+#define  OB_WRP3_WRP3                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP3_nWRP3                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O (GPIO)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)        /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG (IWDG)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                       ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                              */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message                 */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message                   */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time                    */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                           */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                             */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation         */
+#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation        */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional           */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast No error generation       */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                         */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                         */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                              */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                              */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                      */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                      */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                            */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                   */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error             */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error              */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge                */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                      */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                       */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                   */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                    */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                              */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable            */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable            */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable                  */
+#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable         */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable   */
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable    */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable            */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable            */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable         */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                    */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+#define  PWR_CR_SDADC1EN                     ((uint16_t)0x0200)     /*!< Enable Analog part of the SDADC1 */
+#define  PWR_CR_SDADC2EN                     ((uint16_t)0x0400)     /*!< Enable Analog part of the SDADC2 */
+#define  PWR_CR_SDADC3EN                     ((uint16_t)0x0800)     /*!< Enable Analog part of the SDADC3 */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)
+
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< ADCPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)
+#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)
+#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< ADC CLK divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< ADC CLK divided by 4 */
+#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< ADC CLK divided by 6 */
+#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< ADC CLK divided by 8 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00400000)        /*!< USB prescaler */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!< SDADCPRE configuration */
+#define  RCC_CFGR_SDADCPRE                   ((uint32_t)0xF8000000)        /*!< SDADCPRE[4:0] bits (Sigma Delta ADC prescaler) */
+#define  RCC_CFGR_SDADCPRE_0                 ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  RCC_CFGR_SDADCPRE_1                 ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  RCC_CFGR_SDADCPRE_2                 ((uint32_t)0x20000000)        /*!< Bit 2 */
+#define  RCC_CFGR_SDADCPRE_3                 ((uint32_t)0x40000000)        /*!< Bit 3 */
+#define  RCC_CFGR_SDADCPRE_4                 ((uint32_t)0x80000000)        /*!< Bit 4 */
+
+#define  RCC_CFGR_SDADCPRE_DIV1              ((uint32_t)0x00000000)        /*!< SDADC CLK not divided */
+#define  RCC_CFGR_SDADCPRE_DIV2              ((uint32_t)0x80000000)        /*!< SDADC CLK divided by 2 */
+#define  RCC_CFGR_SDADCPRE_DIV4              ((uint32_t)0x88000000)        /*!< SDADC CLK divided by 4 */
+#define  RCC_CFGR_SDADCPRE_DIV6              ((uint32_t)0x90000000)        /*!< SDADC CLK divided by 6 */
+#define  RCC_CFGR_SDADCPRE_DIV8              ((uint32_t)0x98000000)        /*!< SDADC CLK divided by 8 */
+#define  RCC_CFGR_SDADCPRE_DIV10             ((uint32_t)0xA0000000)        /*!< SDADC CLK divided by 10 */
+#define  RCC_CFGR_SDADCPRE_DIV12             ((uint32_t)0xA8000000)        /*!< SDADC CLK divided by 12 */
+#define  RCC_CFGR_SDADCPRE_DIV14             ((uint32_t)0xB0000000)        /*!< SDADC CLK divided by 14 */
+#define  RCC_CFGR_SDADCPRE_DIV16             ((uint32_t)0xB8000000)        /*!< SDADC CLK divided by 16 */
+#define  RCC_CFGR_SDADCPRE_DIV20             ((uint32_t)0xC0000000)        /*!< SDADC CLK divided by 20 */
+#define  RCC_CFGR_SDADCPRE_DIV24             ((uint32_t)0xC8000000)        /*!< SDADC CLK divided by 24 */
+#define  RCC_CFGR_SDADCPRE_DIV28             ((uint32_t)0xD0000000)        /*!< SDADC CLK divided by 28 */
+#define  RCC_CFGR_SDADCPRE_DIV32             ((uint32_t)0xD8000000)        /*!< SDADC CLK divided by 32 */
+#define  RCC_CFGR_SDADCPRE_DIV36             ((uint32_t)0xE0000000)        /*!< SDADC CLK divided by 36 */
+#define  RCC_CFGR_SDADCPRE_DIV40             ((uint32_t)0xE8000000)        /*!< SDADC CLK divided by 40 */
+#define  RCC_CFGR_SDADCPRE_DIV44             ((uint32_t)0xF0000000)        /*!< SDADC CLK divided by 44 */
+#define  RCC_CFGR_SDADCPRE_DIV48             ((uint32_t)0xF8000000)        /*!< SDADC CLK divided by 48 */
+
+/*********************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/******************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 reset */
+#define  RCC_APB2RSTR_TIM19RST               ((uint32_t)0x00080000)        /*!< TIM19 reset */
+#define  RCC_APB2RSTR_SDADC1RST              ((uint32_t)0x01000000)        /*!< SDADC1 reset */
+#define  RCC_APB2RSTR_SDADC2RST              ((uint32_t)0x02000000)        /*!< SDADC2 reset */
+#define  RCC_APB2RSTR_SDADC3RST              ((uint32_t)0x04000000)        /*!< SDADC3 reset */
+
+/******************  Bit definition for RCC_APB1RSTR register  ******************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< Timer 12 reset */
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< Timer 13 reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 reset */
+#define  RCC_APB1RSTR_TIM18RST               ((uint32_t)0x00000200)        /*!< Timer 18 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 reset */
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI3 reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN reset */
+#define  RCC_APB1RSTR_DAC2RST                ((uint32_t)0x04000000)        /*!< DAC 2 reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR reset */
+#define  RCC_APB1RSTR_DAC1RST                ((uint32_t)0x20000000)        /*!< DAC 1 reset */
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x00000002)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00200000)        /*!< GPIOE clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+
+#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_TIM19EN                 ((uint32_t)0x00080000)        /*!< TIM19 clock enable */
+#define  RCC_APB2ENR_SDADC1EN                ((uint32_t)0x01000000)        /*!< SDADC1 clock enable */
+#define  RCC_APB2ENR_SDADC2EN                ((uint32_t)0x02000000)        /*!< SDADC2 clock enable */
+#define  RCC_APB2ENR_SDADC3EN                ((uint32_t)0x04000000)        /*!< SDADC3 clock enable */
+
+/******************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)        /*!< Timer 12 clock enable */
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)        /*!< Timer 13 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_TIM18EN                 ((uint32_t)0x00000200)        /*!< Timer 18 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI3 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN clock enable */
+#define  RCC_APB1ENR_DAC2EN                  ((uint32_t)0x04000000)        /*!< DAC 2 clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DAC1EN                  ((uint32_t)0x20000000)        /*!< DAC 1 clock enable */
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                  ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF reset */
+#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_I2CSW                     ((uint32_t)0x00000030)        /*!< I2CSW bits */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
+#define  RCC_CFGR3_I2C2SW                    ((uint32_t)0x00000020)        /*!< I2C2SW bits */
+#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
+
+#define  RCC_CFGR3_USART2SW                  ((uint32_t)0x00030000)        /*!< USART2SW[1:0] bits */
+#define  RCC_CFGR3_USART2SW_0                ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART2SW_1                ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  RCC_CFGR3_USART3SW                  ((uint32_t)0x000C0000)        /*!< USART3SW[1:0] bits */
+#define  RCC_CFGR3_USART3SW_0                ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART3SW_1                ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*             Sigma-Delta Analog to Digital Converter (SDADC)                */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SDADC_CR1 register  ********************/
+#define  SDADC_CR1_EOCALIE                       ((uint32_t)0x00000001)        /*!< End of calibration interrupt enable */
+#define  SDADC_CR1_JEOCIE                        ((uint32_t)0x00000002)        /*!< Injected end of conversion interrupt enable */
+#define  SDADC_CR1_JOVRIE                        ((uint32_t)0x00000004)        /*!< Injected data overrun interrupt enable */
+#define  SDADC_CR1_REOCIE                        ((uint32_t)0x00000008)        /*!< Regular end of conversion interrupt enable */
+#define  SDADC_CR1_ROVRIE                        ((uint32_t)0x00000010)        /*!< Regular data overrun interrupt enable */
+#define  SDADC_CR1_REFV                          ((uint32_t)0x00000300)        /*!< Reference voltage selection */
+#define  SDADC_CR1_REFV_0                        ((uint32_t)0x00000100)        /*!< Reference voltage selection bit 0 */
+#define  SDADC_CR1_REFV_1                        ((uint32_t)0x00000200)        /*!< Reference voltage selection bit 1 */
+#define  SDADC_CR1_SLOWCK                        ((uint32_t)0x00000400)        /*!< Slow clock mode enable */
+#define  SDADC_CR1_SBI                           ((uint32_t)0x00000800)        /*!< Enter standby mode when idle */
+#define  SDADC_CR1_PDI                           ((uint32_t)0x00001000)        /*!< Enter power down mode when idle */
+#define  SDADC_CR1_JSYNC                         ((uint32_t)0x00004000)        /*!< Launch a injected conversion synchronously with SDADC1 */
+#define  SDADC_CR1_RSYNC                         ((uint32_t)0x00008000)        /*!< Launch regular conversion synchronously with SDADC1 */
+#define  SDADC_CR1_JDMAEN                        ((uint32_t)0x00010000)        /*!< DMA channel enabled to read data for the injected channel group */
+#define  SDADC_CR1_RDMAEN                        ((uint32_t)0x00020000)        /*!< DMA channel enabled to read data for the regular channel */
+#define  SDADC_CR1_INIT                          ((uint32_t)0x80000000)        /*!< Initialization mode request */
+
+/*****************  Bit definition for SDADC_CR2 register  ********************/
+#define  SDADC_CR2_ADON                          ((uint32_t)0x00000001)        /*!< SDADC enable */
+#define  SDADC_CR2_CALIBCNT                      ((uint32_t)0x00000006)        /*!< Number of calibration sequences to be performed */
+#define  SDADC_CR2_CALIBCNT_0                    ((uint32_t)0x00000002)        /*!< Number of calibration sequences to be performed bit 0 */
+#define  SDADC_CR2_CALIBCNT_1                    ((uint32_t)0x00000004)        /*!< Number of calibration sequences to be performed bit 1 */
+#define  SDADC_CR2_STARTCALIB                    ((uint32_t)0x00000010)        /*!< Start calibration */
+#define  SDADC_CR2_JCONT                         ((uint32_t)0x00000020)        /*!< Continuous mode selection for injected conversions */
+#define  SDADC_CR2_JDS                           ((uint32_t)0x00000040)        /*!< Delay start of injected conversions */
+#define  SDADC_CR2_JEXTSEL                       ((uint32_t)0x00000F00)        /*!< Trigger signal selection for launching injected conversions */
+#define  SDADC_CR2_JEXTSEL_0                     ((uint32_t)0x00000100)        /*!< Trigger signal selection for launching injected conversions bit 0 */
+#define  SDADC_CR2_JEXTSEL_1                     ((uint32_t)0x00000200)        /*!< Trigger signal selection for launching injected conversions bit 1 */
+#define  SDADC_CR2_JEXTSEL_2                     ((uint32_t)0x00000400)        /*!< Trigger signal selection for launching injected conversions bit 2 */
+#define  SDADC_CR2_JEXTSEL_3                     ((uint32_t)0x00000800)        /*!< Trigger signal selection for launching injected conversions bit 3 */
+#define  SDADC_CR2_JEXTEN                        ((uint32_t)0x00006000)        /*!< Trigger enable and trigger edge selection for injected conversions */
+#define  SDADC_CR2_JEXTEN_0                      ((uint32_t)0x00002000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 0 */
+#define  SDADC_CR2_JEXTEN_1                      ((uint32_t)0x00004000)        /*!< Trigger enable and trigger edge selection for injected conversions bit 1 */
+#define  SDADC_CR2_JSWSTART                      ((uint32_t)0x00008000)        /*!< Start a conversion of the injected group of channels */
+#define  SDADC_CR2_RCH                           ((uint32_t)0x000F0000)        /*!< Regular channel selection */
+#define  SDADC_CR2_RCH_0                         ((uint32_t)0x00010000)        /*!< Regular channel selection bit 0 */
+#define  SDADC_CR2_RCH_1                         ((uint32_t)0x00020000)        /*!< Regular channel selection bit 1 */
+#define  SDADC_CR2_RCH_2                         ((uint32_t)0x00040000)        /*!< Regular channel selection bit 2 */
+#define  SDADC_CR2_RCH_3                         ((uint32_t)0x00080000)        /*!< Regular channel selection bit 3 */
+#define  SDADC_CR2_RCONT                         ((uint32_t)0x00400000)        /*!< Continuous mode selection for regular conversions */
+#define  SDADC_CR2_RSWSTART                      ((uint32_t)0x00800000)        /*!< Software start of a conversion on the regular channel */
+#define  SDADC_CR2_FAST                          ((uint32_t)0x01000000)        /*!< Fast conversion mode selection */
+
+/********************  Bit definition for SDADC_ISR register  *****************/
+#define  SDADC_ISR_EOCALF                        ((uint32_t)0x00000001)        /*!< End of calibration flag */
+#define  SDADC_ISR_JEOCF                         ((uint32_t)0x00000002)        /*!< End of injected conversion flag */
+#define  SDADC_ISR_JOVRF                         ((uint32_t)0x00000004)        /*!< Injected conversion overrun flag */
+#define  SDADC_ISR_REOCF                         ((uint32_t)0x00000010)        /*!< End of regular conversion flag */
+#define  SDADC_ISR_ROVRF                         ((uint32_t)0x00000020)        /*!< Regular conversion overrun flag */
+#define  SDADC_ISR_CALIBIP                       ((uint32_t)0x00001000)        /*!< Calibration in progress status */
+#define  SDADC_ISR_JCIP                          ((uint32_t)0x00002000)        /*!< Injected conversion in progress status */
+#define  SDADC_ISR_RCIP                          ((uint32_t)0x00004000)        /*!< Regular conversion in progress status */
+#define  SDADC_ISR_STABIP                        ((uint32_t)0x00008000)        /*!< Stabilization in progress status */
+#define  SDADC_ISR_INITRDY                       ((uint32_t)0x80000000)        /*!< Initialization mode is ready */
+
+/******************  Bit definition for SDADC_CLRISR register  ****************/
+#define  SDADC_ISR_CLREOCALF                     ((uint32_t)0x00000001)       /*!< Clear the end of calibration flag */
+#define  SDADC_ISR_CLRJOVRF                      ((uint32_t)0x00000004)       /*!< Clear the injected conversion overrun flag */
+#define  SDADC_ISR_CLRROVRF                      ((uint32_t)0x00000010)       /*!< Clear the regular conversion overrun flag */
+
+/******************  Bit definition for SDADC_JCHGR register  *****************/
+#define  SDADC_JCHGR_JCHG                        ((uint32_t)0x000001FF)       /*!< Injected channel group selection */
+#define  SDADC_JCHGR_JCHG_0                      ((uint32_t)0x00000001)       /*!< Injected channel 0 selection */
+#define  SDADC_JCHGR_JCHG_1                      ((uint32_t)0x00000002)       /*!< Injected channel 1 selection */
+#define  SDADC_JCHGR_JCHG_2                      ((uint32_t)0x00000004)       /*!< Injected channel 2 selection */
+#define  SDADC_JCHGR_JCHG_3                      ((uint32_t)0x00000008)       /*!< Injected channel 3 selection */
+#define  SDADC_JCHGR_JCHG_4                      ((uint32_t)0x00000010)       /*!< Injected channel 4 selection */
+#define  SDADC_JCHGR_JCHG_5                      ((uint32_t)0x00000020)       /*!< Injected channel 5 selection */
+#define  SDADC_JCHGR_JCHG_6                      ((uint32_t)0x00000040)       /*!< Injected channel 6 selection */
+#define  SDADC_JCHGR_JCHG_7                      ((uint32_t)0x00000080)       /*!< Injected channel 7 selection */
+#define  SDADC_JCHGR_JCHG_8                      ((uint32_t)0x00000100)       /*!< Injected channel 8 selection */
+
+/******************  Bit definition for SDADC_CONF0R register  ****************/
+#define  SDADC_CONF0R_OFFSET0                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 0 */
+#define  SDADC_CONF0R_GAIN0                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 0 */
+#define  SDADC_CONF0R_GAIN0_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 0 Bit 0*/
+#define  SDADC_CONF0R_GAIN0_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 0 Bit 1 */
+#define  SDADC_CONF0R_GAIN0_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 0 Bit 2 */
+#define  SDADC_CONF0R_SE0                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 0 */
+#define  SDADC_CONF0R_SE0_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 0 Bit 0 */
+#define  SDADC_CONF0R_SE0_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 0 Bit 1 */
+#define  SDADC_CONF0R_COMMON0                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 0 */
+#define  SDADC_CONF0R_COMMON0_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 0 Bit 0 */
+#define  SDADC_CONF0R_COMMON0_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 0 Bit 1 */
+
+/******************  Bit definition for SDADC_CONF1R register  ****************/
+#define  SDADC_CONF1R_OFFSET1                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 1 */
+#define  SDADC_CONF1R_GAIN1                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 1 */
+#define  SDADC_CONF1R_GAIN1_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_GAIN1_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 1 Bit 1 */
+#define  SDADC_CONF1R_GAIN1_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 1 Bit 2 */
+#define  SDADC_CONF1R_SE1                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 1 */
+#define  SDADC_CONF1R_SE1_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_SE1_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 1 Bit 1 */
+#define  SDADC_CONF1R_COMMON1                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 1 */
+#define  SDADC_CONF1R_COMMON1_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 0 */
+#define  SDADC_CONF1R_COMMON1_1                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 1 Bit 1 */
+
+/******************  Bit definition for SDADC_CONF2R register  ****************/
+#define  SDADC_CONF2R_OFFSET2                    ((uint32_t)0x00000FFF)       /*!< 12-bit calibration offset for configuration 2 */
+#define  SDADC_CONF2R_GAIN2                      ((uint32_t)0x00700000)       /*!< Gain setting for configuration 2 */
+#define  SDADC_CONF2R_GAIN2_0                    ((uint32_t)0x00100000)       /*!< Gain setting for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_GAIN2_1                    ((uint32_t)0x00200000)       /*!< Gain setting for configuration 2 Bit 1 */
+#define  SDADC_CONF2R_GAIN2_2                    ((uint32_t)0x00400000)       /*!< Gain setting for configuration 2 Bit 2 */
+#define  SDADC_CONF2R_SE2                        ((uint32_t)0x0C000000)       /*!< Single ended mode for configuration 2 */
+#define  SDADC_CONF2R_SE2_0                      ((uint32_t)0x04000000)       /*!< Single ended mode for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_SE2_1                      ((uint32_t)0x08000000)       /*!< Single ended mode for configuration 2 Bit 1 */
+#define  SDADC_CONF2R_COMMON2                    ((uint32_t)0xC0000000)       /*!< Common mode for configuration 2 */
+#define  SDADC_CONF2R_COMMON2_0                  ((uint32_t)0x40000000)       /*!< Common mode for configuration 2 Bit 0 */
+#define  SDADC_CONF2R_COMMON2_1                  ((uint32_t)0x80000000)       /*!< Common mode for configuration 2 Bit 1 */
+
+/*****************  Bit definition for SDADC_CONFCHR1 register  ***************/
+#define  SDADC_CONFCHR1_CONFCH0                  ((uint32_t)0x00000003)      /*!< Channel 0 configuration */
+#define  SDADC_CONFCHR1_CONFCH1                  ((uint32_t)0x00000030)      /*!< Channel 1 configuration */
+#define  SDADC_CONFCHR1_CONFCH2                  ((uint32_t)0x00000300)      /*!< Channel 2 configuration */
+#define  SDADC_CONFCHR1_CONFCH3                  ((uint32_t)0x00003000)      /*!< Channel 3 configuration */
+#define  SDADC_CONFCHR1_CONFCH4                  ((uint32_t)0x00030000)      /*!< Channel 4 configuration */
+#define  SDADC_CONFCHR1_CONFCH5                  ((uint32_t)0x00300000)      /*!< Channel 5 configuration */
+#define  SDADC_CONFCHR1_CONFCH6                  ((uint32_t)0x03000000)      /*!< Channel 6 configuration */
+#define  SDADC_CONFCHR1_CONFCH7                  ((uint32_t)0x30000000)      /*!< Channel 7 configuration */
+
+/*****************  Bit definition for SDADC_CONFCHR2 register  ***************/
+#define  SDADC_CONFCHR2_CONFCH8                  ((uint32_t)0x00000003)      /*!< Channel 8 configuration */
+
+/*****************  Bit definition for SDADC_JDATAR register  ***************/
+#define  SDADC_JDATAR_JDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
+#define  SDADC_JDATAR_JDATACH                    ((uint32_t)0x0F000000)      /*!< Injected channel most recently converted */
+#define  SDADC_JDATAR_JDATACH_0                  ((uint32_t)0x01000000)      /*!< Injected channel most recently converted bit 0 */
+#define  SDADC_JDATAR_JDATACH_1                  ((uint32_t)0x02000000)      /*!< Injected channel most recently converted bit 1 */
+#define  SDADC_JDATAR_JDATACH_2                  ((uint32_t)0x04000000)      /*!< Injected channel most recently converted bit 2 */
+#define  SDADC_JDATAR_JDATACH_3                  ((uint32_t)0x08000000)      /*!< Injected channel most recently converted bit 3 */
+
+/*****************  Bit definition for SDADC_RDATAR register  ***************/
+#define  SDADC_RDATAR_RDATA                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data */
+
+/*****************  Bit definition for SDADC_JDATA12R register  ***************/
+#define  SDADC_JDATA12R_JDATA2                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC2 */
+#define  SDADC_JDATA12R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_RDATA12R register  ***************/
+#define  SDADC_RDATA12R_RDATA2                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC2 */
+#define  SDADC_RDATA12R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_JDATA13R register  ***************/
+#define  SDADC_JDATA13R_JDATA3                      ((uint32_t)0xFFFF0000)      /*!< Injected group conversion data for SDADC3 */
+#define  SDADC_JDATA13R_JDATA1                      ((uint32_t)0x0000FFFF)      /*!< Injected group conversion data for SDADC1 */
+
+/*****************  Bit definition for SDADC_RDATA13R register  ***************/
+#define  SDADC_RDATA13R_RDATA3                      ((uint32_t)0xFFFF0000)      /*!< Regular conversion data for SDADC3 */
+#define  SDADC_RDATA13R_RDATA1                      ((uint32_t)0x0000FFFF)      /*!< Regular conversion data for SDADC1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        System Configuration(SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP    ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP    ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
+#define SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP   ((uint32_t)0x00008000) /*!< Timer 18 / DAC2 Ch1 DMA remap */
+#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1           ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C2           ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_VBAT                   ((uint32_t)0x01000000) /*!< VBAT monitoring */
+#define SYSCFG_CFGR1_FPU_IE                 ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0               ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1               ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2               ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3               ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4               ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5               ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!< PF[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!< PF[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!< PF[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x00C0)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                     ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                     ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                      ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                     ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                     ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f37x_conf.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F37x_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html
new file mode 100644
index 0000000..b07de37
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Release_Notes.html
@@ -0,0 +1,133 @@
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+
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+
+
+
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
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+<style>
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+<td style="padding: 0cm;" valign="top">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+          <tr>
+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>
+          </tr>
+<tr style="">
+<td style="padding: 1.5pt;">
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32F37x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr>
+<td style="padding: 0cm;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+<ol style="margin-top: 0cm;" start="1" type="1">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F37x&nbsp;CMSIS
+update History</a><o:p></o:p></span></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
+</ol>
+<span style="font-family: &quot;Times New Roman&quot;;"></span>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F37x CMSIS
+update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 /20-September-2012<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">First official release for 
+<span style="font-style: italic; font-weight: bold;">STM32F37x devices</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
+
+<ul style="margin-top: 0in;" type="disc">
+</ul>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+    complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
+    Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32f3" target="_blank">www.st.com/stm32f3</a></span></u></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s
new file mode 100644
index 0000000..30da828
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s
@@ -0,0 +1,463 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f37x.s
+  * @author    MCD Application Team
+  * @version   V1.0.0
+  * @date      20-September-2012
+  * @brief     stm32f37x vector table for Atollic TrueSTUDIO toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+    
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_IRQHandler
+	.word	TAMPER_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_TS_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	TIM18_DAC2_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	CEC_IRQHandler
+	.word	TIM12_IRQHandler
+	.word	TIM13_IRQHandler
+	.word	TIM14_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	TIM5_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	0
+	.word	0
+	.word	TIM6_DAC1_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	SDADC1_IRQHandler
+	.word	SDADC2_IRQHandler
+	.word	SDADC3_IRQHandler
+	.word	COMP_IRQHandler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	USB_HP_IRQHandler
+	.word	USB_LP_IRQHandler
+	.word	USBWakeUp_IRQHandler
+	.word	0
+	.word	TIM19_IRQHandler
+	.word	0
+	.word	0
+	.word	FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_IRQHandler
+	.thumb_set PVD_IRQHandler,Default_Handler
+
+	.weak	TAMPER_STAMP_IRQHandler
+	.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_TS_IRQHandler
+	.thumb_set EXTI2_TS_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_IRQHandler
+	.thumb_set ADC1_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM18_DAC2_IRQHandler
+	.thumb_set TIM18_DAC2_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	CEC_IRQHandler
+	.thumb_set CEC_IRQHandler,Default_Handler
+
+	.weak	TIM12_IRQHandler
+	.thumb_set TIM12_IRQHandler,Default_Handler
+
+	.weak	TIM13_IRQHandler
+	.thumb_set TIM13_IRQHandler,Default_Handler
+
+	.weak	TIM14_IRQHandler
+	.thumb_set TIM14_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+	
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC1_IRQHandler
+	.thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	SDADC1_IRQHandler
+	.thumb_set SDADC1_IRQHandler,Default_Handler	
+
+	.weak	SDADC2_IRQHandler
+	.thumb_set SDADC2_IRQHandler,Default_Handler	
+
+	.weak	SDADC3_IRQHandler
+	.thumb_set SDADC3_IRQHandler,Default_Handler	
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler	
+		
+	.weak	USB_HP_IRQHandler
+	.thumb_set USB_HP_IRQHandler,Default_Handler
+	
+	.weak	USB_LP_IRQHandler
+	.thumb_set USB_LP_IRQHandler,Default_Handler
+	
+	.weak	USBWakeUp_IRQHandler
+	.thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+	.weak	TIM19_IRQHandler
+	.thumb_set TIM19_IRQHandler,Default_Handler
+  	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s
new file mode 100644
index 0000000..6ca14f8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/arm/startup_stm32f37x.s
@@ -0,0 +1,396 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f37x.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 20-September-2012
+;* Description        : STM32F37x devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+;  @attention
+; 
+;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;  You may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at:
+; 
+;         http://www.st.com/software_license_agreement_liberty_v2
+; 
+;  Unless required by applicable law or agreed to in writing, software 
+;  distributed under the License is distributed on an "AS IS" BASIS, 
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+; 
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMPER_STAMP_IRQHandler           ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_TS_IRQHandler               ; EXTI Line2 and Touch Sense                                              
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1                                   
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2                                  
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3                                   
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4                                   
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5                                   
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6                                   
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7                                   
+                DCD     ADC1_IRQHandler                   ; ADC1                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM15_IRQHandler                  ; TIM15                   
+                DCD     TIM16_IRQHandler                  ; TIM16                 
+                DCD     TIM17_IRQHandler                  ; TIM17
+                DCD     TIM18_DAC2_IRQHandler             ; TIM18 and DAC2                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     CEC_IRQHandler                    ; CEC                       
+                DCD     TIM12_IRQHandler                  ; TIM12                  
+                DCD     TIM13_IRQHandler                  ; TIM13                 
+                DCD     TIM14_IRQHandler                  ; TIM14
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM5_IRQHandler                   ; TIM5                                    
+                DCD     SPI3_IRQHandler                   ; SPI3    
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved                                       
+                DCD     TIM6_DAC1_IRQHandler              ; TIM6 and DAC1 Channel1 & channel2                                           
+                DCD     TIM7_IRQHandler                   ; TIM7                                              
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1                                           
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2  
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3  
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4  
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5  
+                DCD     SDADC1_IRQHandler                 ; SDADC1                                            
+                DCD     SDADC2_IRQHandler                 ; SDADC2                                           
+                DCD     SDADC3_IRQHandler                 ; SDADC3                                          
+                DCD     COMP_IRQHandler                   ; COMP   
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved                
+                DCD     USB_HP_IRQHandler                 ; USB High Priority                    
+                DCD     USB_LP_IRQHandler                 ; USB Low Priority                                    
+                DCD     USBWakeUp_IRQHandler               ; USB Wakeup   
+                DCD     0                                 ; Reserved                                
+                DCD     TIM19_IRQHandler                  ; TIM19   
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FPU_IRQHandler                    ; FPU                                  
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMPER_STAMP_IRQHandler           [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_TS_IRQHandler               [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]                                
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]                                   
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]                                   
+                EXPORT  ADC1_IRQHandler                   [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM15_IRQHandler                  [WEAK]                  
+                EXPORT  TIM16_IRQHandler                  [WEAK]                
+                EXPORT  TIM17_IRQHandler                  [WEAK] 
+                EXPORT  TIM18_DAC2_IRQHandler             [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  CEC_IRQHandler                    [WEAK]                        
+                EXPORT  TIM12_IRQHandler                  [WEAK]                 
+                EXPORT  TIM13_IRQHandler                  [WEAK]                 
+                EXPORT  TIM14_IRQHandler                  [WEAK] 
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                   
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                          
+                EXPORT  TIM6_DAC1_IRQHandler              [WEAK]                                             
+                EXPORT  TIM7_IRQHandler                   [WEAK]                                             
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]                                  
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]                                   
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]                                    
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]                                    
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]                                 
+                EXPORT  SDADC1_IRQHandler                 [WEAK]                                         
+                EXPORT  SDADC2_IRQHandler                 [WEAK]                     
+                EXPORT  SDADC3_IRQHandler                 [WEAK]                                               
+                EXPORT  COMP_IRQHandler                   [WEAK]                                               
+                EXPORT  USB_HP_IRQHandler                 [WEAK]                                               
+                EXPORT  USB_LP_IRQHandler                 [WEAK]                                               
+                EXPORT  USBWakeUp_IRQHandler              [WEAK]                                       
+                EXPORT  TIM19_IRQHandler                  [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]                                   
+
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMPER_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_TS_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Channel1_IRQHandler                                       
+DMA1_Channel2_IRQHandler                                          
+DMA1_Channel3_IRQHandler                                          
+DMA1_Channel4_IRQHandler                                          
+DMA1_Channel5_IRQHandler                                          
+DMA1_Channel6_IRQHandler                                          
+DMA1_Channel7_IRQHandler                                          
+ADC1_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM15_IRQHandler                        
+TIM16_IRQHandler                      
+TIM17_IRQHandler  
+TIM18_DAC2_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+CEC_IRQHandler                                
+TIM12_IRQHandler                      
+TIM13_IRQHandler                       
+TIM14_IRQHandler  
+TIM5_IRQHandler                                               
+SPI3_IRQHandler                                                            
+TIM6_DAC1_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Channel1_IRQHandler                                         
+DMA2_Channel2_IRQHandler                                          
+DMA2_Channel3_IRQHandler                                           
+DMA2_Channel4_IRQHandler                                           
+DMA2_Channel5_IRQHandler                                        
+SDADC1_IRQHandler                                                         
+SDADC2_IRQHandler                                
+SDADC3_IRQHandler                                                           
+COMP_IRQHandler                                                          
+USB_HP_IRQHandler                           
+USB_LP_IRQHandler                            
+USBWakeUp_IRQHandler                                
+TIM19_IRQHandler
+FPU_IRQHandler                                                    
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s
new file mode 100644
index 0000000..211862e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/iar/startup_stm32f37x.s
@@ -0,0 +1,542 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32f37x.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 20-September-2012
+;* Description        : STM32F37x Devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;  @attention
+; 
+;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;  You may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at:
+; 
+;         http://www.st.com/software_license_agreement_liberty_v2
+; 
+;  Unless required by applicable law or agreed to in writing, software 
+;  distributed under the License is distributed on an "AS IS" BASIS, 
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+; 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+       ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+        DCD     TAMPER_STAMP_IRQHandler           ; Tamper and TimeStamps through the EXTI line            
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+        DCD     FLASH_IRQHandler                  ; FLASH                                           
+        DCD     RCC_IRQHandler                    ; RCC                                             
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+        DCD     EXTI2_TS_IRQHandler               ; EXTI Line2 and Touch Sense controller                                             
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1                                   
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2                                  
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3                                   
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4                                   
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5                                   
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6                                   
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7                                   
+        DCD     ADC1_IRQHandler                   ; ADC1                            
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+        DCD     TIM15_IRQHandler                  ; TIM15                   
+        DCD     TIM16_IRQHandler                  ; TIM16                 
+        DCD     TIM17_IRQHandler                  ; TIM17
+        DCD     TIM18_DAC2_IRQHandler             ; TIM18 and DAC2                                   
+        DCD     TIM2_IRQHandler                   ; TIM2                                            
+        DCD     TIM3_IRQHandler                   ; TIM3                                            
+        DCD     TIM4_IRQHandler                   ; TIM4                                            
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+        DCD     SPI1_IRQHandler                   ; SPI1                                            
+        DCD     SPI2_IRQHandler                   ; SPI2                                            
+        DCD     USART1_IRQHandler                 ; USART1                                          
+        DCD     USART2_IRQHandler                 ; USART2                                          
+        DCD     USART3_IRQHandler                 ; USART3                                          
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+        DCD     CEC_IRQHandler                    ; CEC                       
+        DCD     TIM12_IRQHandler                  ; TIM12                  
+        DCD     TIM13_IRQHandler                  ; TIM13                 
+        DCD     TIM14_IRQHandler                  ; TIM14
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     TIM5_IRQHandler                   ; TIM5                                    
+        DCD     SPI3_IRQHandler                   ; SPI3    
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved                                       
+        DCD     TIM6_DAC1_IRQHandler              ; TIM6 and DAC1 Channel1 & channel2                                           
+        DCD     TIM7_IRQHandler                   ; TIM7                                              
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1                                           
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2  
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3  
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4  
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5  
+        DCD     SDADC1_IRQHandler                 ; SDADC1                                            
+        DCD     SDADC2_IRQHandler                 ; SDADC2                                           
+        DCD     SDADC3_IRQHandler                 ; SDADC3                                          
+        DCD     COMP_IRQHandler                   ; COMP   
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved                
+        DCD     USB_HP_IRQHandler                 ; USB High Priority                    
+        DCD     USB_LP_IRQHandler                 ; USB Low Priority                                    
+        DCD     USBWakeUp_IRQHandler               ; USB Wakeup   
+        DCD     0                                 ; Reserved                                
+        DCD     TIM19_IRQHandler                  ; TIM19
+        DCD     0                                 ; Reserved     
+        DCD     0                                 ; Reserved
+        DCD     FPU_IRQHandler                    ; FPU     
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TAMPER_STAMP_IRQHandler  
+        B TAMPER_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_TS_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_TS_IRQHandler  
+        B EXTI2_TS_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel1_IRQHandler  
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel2_IRQHandler  
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel3_IRQHandler  
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel4_IRQHandler  
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel5_IRQHandler  
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel6_IRQHandler  
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Channel7_IRQHandler  
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler  
+        B ADC1_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM15_IRQHandler  
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM16_IRQHandler  
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM17_IRQHandler  
+        B TIM17_IRQHandler
+        
+        PUBWEAK TIM18_DAC2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM18_DAC2_IRQHandler  
+        B TIM18_DAC2_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+CEC_IRQHandler  
+        B CEC_IRQHandler
+      
+        PUBWEAK TIM12_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM12_IRQHandler  
+        B TIM12_IRQHandler
+
+        PUBWEAK TIM13_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM13_IRQHandler  
+        B TIM13_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM14_IRQHandler  
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK TIM6_DAC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM6_DAC1_IRQHandler  
+        B TIM6_DAC1_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel1_IRQHandler  
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel2_IRQHandler  
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel3_IRQHandler  
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel4_IRQHandler  
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Channel5_IRQHandler  
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK SDADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SDADC1_IRQHandler  
+        B SDADC1_IRQHandler
+
+        PUBWEAK SDADC2_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+SDADC2_IRQHandler  
+        B SDADC2_IRQHandler
+
+        PUBWEAK SDADC3_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+SDADC3_IRQHandler  
+        B SDADC3_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+COMP_IRQHandler  
+        B COMP_IRQHandler
+
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler  
+        B USB_HP_IRQHandler
+
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler  
+        B USB_LP_IRQHandler
+
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler  
+        B USBWakeUp_IRQHandler
+
+        PUBWEAK TIM19_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+TIM19_IRQHandler  
+        B TIM19_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+        
+        END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c
new file mode 100644
index 0000000..f7add14
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | DISABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
new file mode 100644
index 0000000..df5adaa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
@@ -0,0 +1,6351 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    09-March-2012
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32L1xx High-, Medium-density
+  *          and Medium-density Plus devices.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx
+  * @{
+  */
+    
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+  /* #define STM32L1XX_MD  */   /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
+  /* #define STM32L1XX_MDP */   /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */
+  #define STM32L1XX_HD    /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 
+   STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
+ - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 
+   microcontrollers where the Flash memory density is 384 Kbytes.
+  */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE  ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  ((uint32_t)37000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
+/**
+ * @brief STM32L1xx Standard Peripheral Library version number V1.1.1
+   */
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L1XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32L1XX_STDPERIPH_VERSION       ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32L1XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
+#define __MPU_PRESENT             1 /*!< STM32L provides MPU                          */
+#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+ 
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
+
+/******  STM32L specific Interrupt Numbers ***********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and Time Stamp through EXTI Line Interrupts      */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
+  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
+  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
+  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
+  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
+  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
+  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
+  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
+  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
+  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
+  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
+#ifdef STM32L1XX_MD
+  TIM7_IRQn                   = 44      /*!< TIM7 global Interrupt                                   */
+#endif
+
+#ifdef STM32L1XX_MDP
+  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
+  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
+  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
+  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
+  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
+  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
+  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
+  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
+  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
+  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
+#endif
+
+#ifdef STM32L1XX_HD
+  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
+  SDIO_IRQn                   = 45,     /*!< SDIO global Interrupt                                   */
+  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
+  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
+  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
+  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
+  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
+  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
+  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
+  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
+  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
+  AES_IRQn                    = 55,     /*!< AES global Interrupt                                    */
+  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
+#endif
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source 
+   module. Using the 'Options for File' dialog you can simply change the 
+   'Code / Const' area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 
+   'Options for Target' dialog. 
+*/
+ #define __RAM_FUNC FLASH_Status 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+ #define __RAM_FUNC __ramfunc FLASH_Status
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+   RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".data")))". 
+*/
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
+
+#elif defined   (  __TASKING__  )
+/* TASKING Compiler
+   ----------------
+   RAM functions are defined using a specific toolchain pragma. This pragma is 
+   defined in the stm32l1xx_flash_ramfunc.c 
+*/
+ #define __RAM_FUNC  FLASH_Status
+
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
+  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
+  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
+  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
+  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
+  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
+  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
+  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
+  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
+  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
+  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
+  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
+  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
+  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
+  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
+  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief AES hardware accelerator
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< AES control register,                        Address offset: 0x00 */
+  __IO uint32_t SR;           /*!< AES status register,                         Address offset: 0x04 */
+  __IO uint32_t DINR;         /*!< AES data input register,                     Address offset: 0x08 */
+  __IO uint32_t DOUTR;        /*!< AES data output register,                    Address offset: 0x0C */
+  __IO uint32_t KEYR0;        /*!< AES key register 0,                          Address offset: 0x10 */
+  __IO uint32_t KEYR1;        /*!< AES key register 1,                          Address offset: 0x14 */
+  __IO uint32_t KEYR2;        /*!< AES key register 2,                          Address offset: 0x18 */
+  __IO uint32_t KEYR3;        /*!< AES key register 3,                          Address offset: 0x1C */
+  __IO uint32_t IVR0;         /*!< AES initialization vector register 0,        Address offset: 0x20 */
+  __IO uint32_t IVR1;         /*!< AES initialization vector register 1,        Address offset: 0x24 */
+  __IO uint32_t IVR2;         /*!< AES initialization vector register 2,        Address offset: 0x28 */
+  __IO uint32_t IVR3;         /*!< AES initialization vector register 3,        Address offset: 0x2C */
+} AES_TypeDef;
+
+/** 
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/** 
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t   RESERVED0;        /*!< Reserved,                                    0x05                 */
+  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
+  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
+  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
+  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
+  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
+  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
+  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
+  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
+  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
+  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
+  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
+  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
+  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
+  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!< EXTI interrupt mask register,                 Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!< EXTI event mask register,                     Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!< EXTI rising edge trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!< EXTI software interrupt event register,       Address offset: 0x10 */
+  __IO uint32_t PR;           /*!< EXTI pending register,                        Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
+  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
+  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
+  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
+  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
+  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
+  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
+  __IO uint32_t WRPR;         /*!< Write protection register,                   Address offset: 0x20 */
+  uint32_t   RESERVED[23];    /*!< Reserved,                                    0x24                 */
+  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x28 */
+  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x2C */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Option Bytes Registers
+  */
+  
+typedef struct
+{
+  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
+  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
+  __IO uint32_t WRP01;             /*!< write protection register 0 1,          Address offset: 0x08 */
+  __IO uint32_t WRP23;             /*!< write protection register 2 3,          Address offset: 0x0C */
+  __IO uint32_t WRP45;             /*!< write protection register 4 5,          Address offset: 0x10 */
+  __IO uint32_t WRP67;             /*!< write protection register 6 7,          Address offset: 0x14 */
+  __IO uint32_t WRP89;             /*!< write protection register 8 9,          Address offset: 0x18 */
+  __IO uint32_t WRP1011;           /*!< write protection register 10 11,        Address offset: 0x1C */
+} OB_TypeDef;
+
+/** 
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
+  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];      /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];      /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;        
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
+  uint16_t RESERVED0;         /*!< Reserved,                                    0x06                      */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
+  uint16_t RESERVED1;         /*!< Reserved,                                    0x12                      */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
+  uint16_t RESERVED2;         /*!< Reserved,                                    0x16                      */
+  __IO uint16_t BSRRL;        /*!< GPIO port bit set/reset low registerBSRR,    Address offset: 0x18      */
+  __IO uint16_t BSRRH;        /*!< GPIO port bit set/reset high registerBSRR,   Address offset: 0x1A      */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,        Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
+  uint16_t RESERVED3;         /*!< Reserved,                                    0x2A                      */
+} GPIO_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
+  uint16_t  RESERVED0;        /*!< Reserved,                                    0x02                 */
+  __IO uint16_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
+  uint16_t  RESERVED1;        /*!< Reserved,                                    0x06                 */
+  __IO uint16_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
+  uint16_t  RESERVED2;        /*!< Reserved,                                    0x0A                 */
+  __IO uint16_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
+  uint16_t  RESERVED3;        /*!< Reserved,                                    0x0E                 */
+  __IO uint16_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
+  uint16_t  RESERVED4;        /*!< Reserved,                                    0x12                 */
+  __IO uint16_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
+  uint16_t  RESERVED5;        /*!< Reserved,                                    0x16                 */
+  __IO uint16_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
+  uint16_t  RESERVED6;        /*!< Reserved,                                    0x1A                 */
+  __IO uint16_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
+  uint16_t  RESERVED7;        /*!< Reserved,                                    0x1E                 */
+  __IO uint16_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;        /*!< Reserved,                                    0x22                 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
+  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
+  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
+  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
+  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
+  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
+  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
+  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Routing Interface 
+  */
+
+typedef struct
+{
+  __IO uint32_t ICR;       /*!< RI input capture register,             Address offset: 0x00 */
+  __IO uint32_t ASCR1;     /*!< RI analog switches control register,   Address offset: 0x04 */
+  __IO uint32_t ASCR2;     /*!< RI analog switch control register 2,   Address offset: 0x08 */
+  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,       Address offset: 0x0C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,       Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,       Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,       Address offset: 0x18 */
+} RI_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;    /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;    /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;         /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;    /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;    /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;    /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;    /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;    /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;    /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;    /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;          /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED10;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
+  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
+  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
+  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
+  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
+  __IO uint16_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED18;   /*!< Reserved, 0x4A                                            */ 
+  __IO uint16_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED19;   /*!< Reserved, 0x4E                                            */ 
+  __IO uint16_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED20;   /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define COMP_BASE             (APB1PERIPH_BASE + 0x7C00)
+#define RI_BASE               (APB1PERIPH_BASE + 0x7C04)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7C5C)
+
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x0800)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x1000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2700)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+
+#define GPIOA_BASE            (AHBPERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHBPERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHBPERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHBPERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHBPERIPH_BASE + 0x1000)
+#define GPIOH_BASE            (AHBPERIPH_BASE + 0x1400)
+#define GPIOF_BASE            (AHBPERIPH_BASE + 0x1800)
+#define GPIOG_BASE            (AHBPERIPH_BASE + 0x1C00)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x3800)
+
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x6000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080)
+
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x6400)
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001C)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058)
+
+#define AES_BASE              ((uint32_t)0x50060000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+
+#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define RI                  ((RI_TypeDef *) RI_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+
+#define AES                 ((AES_TypeDef *) AES_BASE)
+
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
+#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
+#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
+#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
+#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
+#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
+#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
+#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
+#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
+
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
+
+#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
+#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
+
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
+
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
+#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
+
+#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
+#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
+
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
+
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
+
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
+#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
+#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
+#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
+#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
+#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
+#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
+#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
+#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
+#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
+#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
+#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_SMPR3 register  *******************/
+#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+ 
+#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
+#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
+#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
+#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
+#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
+#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
+#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
+#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
+#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
+#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
+#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
+#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
+#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR4 register  *******************/
+#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+/*******************  Bit definition for ADC_SQR5 register  *******************/
+#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
+
+#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
+#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
+#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
+#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
+
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
+
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/******************  Bit definition for ADC_SMPR0 register  *******************/
+#define  ADC_SMPR3_SMP30                     ((uint32_t)0x00000007)        /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
+#define  ADC_SMPR3_SMP30_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP30_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP30_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
+ 
+#define  ADC_SMPR3_SMP31                     ((uint32_t)0x00000038)        /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
+#define  ADC_SMPR3_SMP31_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  ADC_SMPR3_SMP31_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+#define  ADC_SMPR3_SMP31_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
+#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
+#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Advanced Encryption Standard (AES)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for AES_CR register  *********************/
+#define  AES_CR_EN                           ((uint32_t)0x00000001)        /*!< AES Enable */
+#define  AES_CR_DATATYPE                     ((uint32_t)0x00000006)        /*!< Data type selection */
+#define  AES_CR_DATATYPE_0                   ((uint32_t)0x00000002)        /*!< Bit 0 */
+#define  AES_CR_DATATYPE_1                   ((uint32_t)0x00000004)        /*!< Bit 1 */
+
+#define  AES_CR_MODE                         ((uint32_t)0x00000018)        /*!< AES Mode Of Operation */
+#define  AES_CR_MODE_0                       ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  AES_CR_MODE_1                       ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+#define  AES_CR_CHMOD                        ((uint32_t)0x00000060)        /*!< AES Chaining Mode */
+#define  AES_CR_CHMOD_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
+#define  AES_CR_CHMOD_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
+
+#define  AES_CR_CCFC                         ((uint32_t)0x00000080)        /*!< Computation Complete Flag Clear */
+#define  AES_CR_ERRC                         ((uint32_t)0x00000100)        /*!< Error Clear */
+#define  AES_CR_CCIE                         ((uint32_t)0x00000200)        /*!< Computation Complete Interrupt Enable */
+#define  AES_CR_ERRIE                        ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  AES_CR_DMAINEN                      ((uint32_t)0x00000800)        /*!< DMA ENable managing the data input phase */
+#define  AES_CR_DMAOUTEN                     ((uint32_t)0x00001000)        /*!< DMA Enable managing the data output phase */
+
+/*******************  Bit definition for AES_SR register  *********************/
+#define  AES_SR_CCF                          ((uint32_t)0x00000001)        /*!< Computation Complete Flag */
+#define  AES_SR_RDERR                        ((uint32_t)0x00000002)        /*!< Read Error Flag */
+#define  AES_SR_WRERR                        ((uint32_t)0x00000004)        /*!< Write Error Flag */
+
+/*******************  Bit definition for AES_DINR register  *******************/
+#define  AES_DINR                            ((uint32_t)0x0000FFFF)        /*!< AES Data Input Register */
+
+/*******************  Bit definition for AES_DOUTR register  ******************/
+#define  AES_DOUTR                           ((uint32_t)0x0000FFFF)        /*!< AES Data Output Register */
+
+/*******************  Bit definition for AES_KEYR0 register  ******************/
+#define  AES_KEYR0                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 0 */
+
+/*******************  Bit definition for AES_KEYR1 register  ******************/
+#define  AES_KEYR1                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 1 */
+
+/*******************  Bit definition for AES_KEYR2 register  ******************/
+#define  AES_KEYR2                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 2 */
+
+/*******************  Bit definition for AES_KEYR3 register  ******************/
+#define  AES_KEYR3                           ((uint32_t)0x0000FFFF)        /*!< AES Key Register 3 */
+
+/*******************  Bit definition for AES_IVR0 register  *******************/
+#define  AES_IVR0                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 0 */
+
+/*******************  Bit definition for AES_IVR1 register  *******************/
+#define  AES_IVR1                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 1 */
+
+/*******************  Bit definition for AES_IVR2 register  *******************/
+#define  AES_IVR2                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 2 */
+
+/*******************  Bit definition for AES_IVR3 register  *******************/
+#define  AES_IVR3                            ((uint32_t)0x0000FFFF)        /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for COMP_CSR register  ********************/
+#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
+#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
+#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
+#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
+
+#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
+#define  COMP_CSR_SW1                        ((uint32_t)0x00000020)        /*!< SW1 analog switch enable */
+#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
+
+#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
+#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
+
+#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
+#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
+
+#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
+#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
+
+#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
+#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
+#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
+#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
+
+#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
+#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
+#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
+
+#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
+#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
+#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for OPAMP_CSR register  ******************/
+#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
+#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
+#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
+#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
+#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
+#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
+#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
+#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
+#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
+#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
+#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
+#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
+#define OPAMP_CSR_OPA3PD                     ((uint32_t)0x00010000)        /*!< OPAMP3 disable */
+#define OPAMP_CSR_S3SEL3                     ((uint32_t)0x00020000)        /*!< Switch 3 for OPAMP3 Enable */
+#define OPAMP_CSR_S4SEL3                     ((uint32_t)0x00040000)        /*!< Switch 4 for OPAMP3 Enable */
+#define OPAMP_CSR_S5SEL3                     ((uint32_t)0x00080000)        /*!< Switch 5 for OPAMP3 Enable */
+#define OPAMP_CSR_S6SEL3                     ((uint32_t)0x00100000)        /*!< Switch 6 for OPAMP3 Enable */
+#define OPAMP_CSR_OPA3CAL_L                  ((uint32_t)0x00200000)        /*!< OPAMP3 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA3CAL_H                  ((uint32_t)0x00400000)        /*!< OPAMP3 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA3LPM                    ((uint32_t)0x00800000)        /*!< OPAMP3 Low power enable */
+#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
+#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
+#define OPAMP_CSR_ANAWSEL3                   ((uint32_t)0x04000000)        /*!< Switch ANA Enable for OPAMP3 */
+#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
+#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
+#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
+#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
+#define OPAMP_CSR_OPA3CALOUT                 ((uint32_t)0x80000000)        /*!< OPAMP3 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM        ((uint32_t)0x000003FF)        /*!< Offset trim for OPAMP1 */
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM        ((uint32_t)0x000FFC00)        /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM        ((uint32_t)0x3FF00000)        /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000003FF)        /*!< Offset trim in low power for OPAMP1 */
+#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP  ((uint32_t)0x000FFC00)        /*!< Offset trim in low power for OPAMP2 */
+#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP  ((uint32_t)0x3FF00000)        /*!< Offset trim in low power for OPAMP3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital to Analog Converter (DAC)                       */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun interrupt enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
+
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+
+#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  External Interrupt/Event Controller (EXTI)                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
+#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
+#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
+#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
+#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                FLASH, DATA EEPROM and Option Bytes Registers               */
+/*                        (FLASH, DATA_EEPROM, OB)                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
+#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
+#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
+#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
+
+/*******************  Bit definition for FLASH_PECR register  ******************/
+#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
+#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
+#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
+#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
+#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
+#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
+
+/******************  Bit definition for FLASH_PDKEYR register  ******************/
+#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PEKEYR register  ******************/
+#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PRGKEYR register  ******************/
+#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
+
+/******************  Bit definition for FLASH_OPTKEYR register  ******************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
+#define  FLASH_SR_ENHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
+#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
+
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
+#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
+#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
+#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
+#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x000000AA)        /*!< Read Protection */
+#define  FLASH_OBR_BOR_LEV                   ((uint16_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
+#define  FLASH_OBR_nRST_BFB2                 ((uint32_t)0x00800000)        /*!< BFB2 */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/******************  Bit definition for FLASH_WRPR1 register  *****************/
+#define  FLASH_WRPR1_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+
+/******************  Bit definition for FLASH_WRPR2 register  *****************/
+#define  FLASH_WRPR2_WRP                     ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
+/******************************************************************************/
+/*                                                                            */
+/*                       Flexible Static Memory Controller                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */
+
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */
+
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      General Purpose IOs (GPIO)                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/  
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_OTYPER register  ****************/   
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/*******************  Bit definition for GPIO_OSPEEDR register  ***************/  
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register  *****************/  
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15
+
+/*******************  Bit definition for GPIO_BSRR register  ******************/  
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_LCKR register  ******************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/*******************  Bit definition for GPIO_AFRL register  ******************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/*******************  Bit definition for GPIO_AFRH register  ******************/
+#define GPIO_AFRH_AFRH8            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH9            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH10           ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH11           ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH12           ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH13           ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH14           ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH15           ((uint32_t)0xF0000000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */
+
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */
+
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */
+
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
+#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
+#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
+#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
+
+#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
+#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
+#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
+
+#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
+#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
+#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
+
+#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
+#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
+
+#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
+#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
+#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+#define  PWR_CR_ULP                          ((uint16_t)0x0200)     /*!< Ultra Low Power mode */
+#define  PWR_CR_FWU                          ((uint16_t)0x0400)     /*!< Fast wakeup */
+
+#define  PWR_CR_VOS                          ((uint16_t)0x1800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define  PWR_CR_VOS_0                        ((uint16_t)0x0800)     /*!< Bit 0 */
+#define  PWR_CR_VOS_1                        ((uint16_t)0x1000)     /*!< Bit 1 */
+#define  PWR_CR_LPRUN                        ((uint16_t)0x4000)     /*!< Low power run mode */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+#define  PWR_CSR_VOSF                        ((uint16_t)0x0010)     /*!< Voltage Scaling select flag */
+#define  PWR_CSR_REGLPF                      ((uint16_t)0x0020)     /*!< Regulator LP flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+#define  PWR_CSR_EWUP3                       ((uint16_t)0x0400)     /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Reset and Clock Control (RCC)                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+
+#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
+#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
+
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
+
+#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
+#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
+#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
+
+/********************  Bit definition for RCC_ICSCR register  *****************/
+#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
+#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
+
+#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
+#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
+#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+/*!< SW configuration */
+#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+/*!< PLL entry clock source*/
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
+
+
+#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
+#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
+#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
+#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
+#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
+#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
+#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
+#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
+#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
+#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
+
+
+/*!< PLLDIV configuration */
+#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
+#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
+#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
+#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
+
+
+#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
+#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
+
+#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
+#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
+
+/*!< MCO Prescaler configuration */
+#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
+#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
+#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
+#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
+#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
+#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
+#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
+
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
+#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+
+/*****************  Bit definition for RCC_AHBRSTR register  ******************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
+#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
+#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00000040)        /*!< GPIO port F reset */
+#define  RCC_AHBRSTR_GPIOGRST                ((uint32_t)0x00000080)        /*!< GPIO port G reset */
+#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
+#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
+#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
+#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
+#define  RCC_AHBRSTR_AESRST                  ((uint32_t)0x08000000)        /*!< AES reset */
+#define  RCC_AHBRSTR_FSMCRST                 ((uint32_t)0x40000000)        /*!< FSMC reset */
+ 
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)        /*!< SDIO reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
+#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
+#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
+#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00000040)        /*!< GPIO port F clock enable */
+#define  RCC_AHBENR_GPIOGEN                  ((uint32_t)0x00000080)        /*!< GPIO port G clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
+                                                                                the Flash memory is in power down mode) */
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
+#define  RCC_AHBENR_AESEN                    ((uint32_t)0x08000000)        /*!< AES clock enable */
+#define  RCC_AHBENR_FSMCEN                   ((uint32_t)0x40000000)        /*!< FSMC clock enable */
+
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)         /*!< SDIO clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
+
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
+#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
+
+/******************  Bit definition for RCC_AHBLPENR register  ****************/
+#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOFLPEN              ((uint32_t)0x00000040)        /*!< GPIO port F clock enabled in sleep mode */
+#define  RCC_AHBLPENR_GPIOGLPEN              ((uint32_t)0x00000080)        /*!< GPIO port G clock enabled in sleep mode */
+#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
+#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
+                                                                                (has effect only when the Flash memory is
+                                                                                 in power down mode) */
+#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
+#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
+#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
+#define  RCC_AHBLPENR_AESLPEN                ((uint32_t)0x08000000)        /*!< AES clock enabled in sleep mode */
+#define  RCC_AHBLPENR_FSMCLPEN               ((uint32_t)0x40000000)        /*!< FSMC clock enabled in sleep mode */
+
+/******************  Bit definition for RCC_APB2LPENR register  ***************/
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)         /*!< SDIO clock enabled in sleep mode */
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_APB1LPENR register  ****************/
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)        /*!< UART 4 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)        /*!< UART 5 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
+#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
+#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+
+#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
+#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
+#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
+#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
+#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
+
+#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
+
+#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
+#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
+ 
+#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
+#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */
+
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */
+
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */
+
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */
+
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */
+
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */
+
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Serial Peripheral Interface (SPI)                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */
+#define  SPI_CR2_FRF                         ((uint8_t)0x08)               /*!< Frame format */
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
+#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*****************  Bit definition for SYSCFG_PMC register  *******************/
+#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0006) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0007) /*!< PG[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0060) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0070) /*!< PG[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0500) /*!< PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0600) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0700) /*!< PG[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x3000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x4000) /*!< PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0006) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0007) /*!< PG[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0060) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0070) /*!< PG[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0600) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0700) /*!< PG[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */ 
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x6000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x7000) /*!< PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0006) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0007) /*!< PG[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0060) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0070) /*!< PG[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0600) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0700) /*!< PG[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */ 
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x6000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x7000) /*!< PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0006) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0007) /*!< PG[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0060) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0070) /*!< PG[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0600) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0700) /*!< PG[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */ 
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x6000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x7000) /*!< PG[15] pin */
+ 
+/******************************************************************************/
+/*                                                                            */
+/*                       Routing Interface (RI)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RI_ICR register  ********************/
+#define  RI_ICR_IC1Z                    ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
+#define  RI_ICR_IC1Z_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_ICR_IC1Z_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_ICR_IC1Z_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_ICR_IC1Z_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define  RI_ICR_IC2Z                    ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
+#define  RI_ICR_IC2Z_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
+#define  RI_ICR_IC2Z_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
+#define  RI_ICR_IC2Z_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
+#define  RI_ICR_IC2Z_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define  RI_ICR_IC3Z                    ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
+#define  RI_ICR_IC3Z_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
+#define  RI_ICR_IC3Z_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
+#define  RI_ICR_IC3Z_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
+#define  RI_ICR_IC3Z_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define  RI_ICR_IC4Z                    ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
+#define  RI_ICR_IC4Z_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
+#define  RI_ICR_IC4Z_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
+#define  RI_ICR_IC4Z_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
+#define  RI_ICR_IC4Z_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
+
+#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
+#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
+#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
+#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
+#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
+
+/********************  Bit definition for RI_ASCR1 register  ********************/
+#define  RI_ASCR1_CH                    ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
+#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
+#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
+#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
+#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
+#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
+#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
+#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
+#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
+#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
+#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
+#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
+#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
+#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
+#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
+#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
+#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
+
+/********************  Bit definition for RI_ASCR2 register  ********************/
+#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
+#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
+#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
+#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
+#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
+#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
+#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
+#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
+#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
+#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
+#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
+#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
+#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
+#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
+#define  RI_ASCR2_CH1b                  ((uint32_t)0x00020000) /*!< CH1b selection bit */
+#define  RI_ASCR2_CH2b                  ((uint32_t)0x00040000) /*!< CH2b selection bit */
+#define  RI_ASCR2_CH3b                  ((uint32_t)0x00080000) /*!< CH3b selection bit */
+#define  RI_ASCR2_CH6b                  ((uint32_t)0x00100000) /*!< CH6b selection bit */
+#define  RI_ASCR2_CH7b                  ((uint32_t)0x00200000) /*!< CH7b selection bit */
+#define  RI_ASCR2_CH8b                  ((uint32_t)0x00400000) /*!< CH8b selection bit */
+#define  RI_ASCR2_CH9b                  ((uint32_t)0x00800000) /*!< CH9b selection bit */
+#define  RI_ASCR2_CH10b                 ((uint32_t)0x01000000) /*!< CH10b selection bit */
+#define  RI_ASCR2_CH11b                 ((uint32_t)0x02000000) /*!< CH11b selection bit */
+#define  RI_ASCR2_CH12b                 ((uint32_t)0x04000000) /*!< CH12b selection bit */
+#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
+#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
+#define  RI_ASCR2_GR5_4                 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
+
+/********************  Bit definition for RI_HYSCR1 register  ********************/
+#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
+#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
+#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR2 register  ********************/
+#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
+#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
+#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR3 register  ********************/
+#define  RI_HYSCR2_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
+#define  RI_HYSCR2_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR2_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR2_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR2_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR2_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR2_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR2_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR2_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR2_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR2_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR2_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR2_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR2_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR2_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR2_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR2_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define  RI_HYSCR3_PF                   ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
+#define  RI_HYSCR3_PF_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define  RI_HYSCR3_PF_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define  RI_HYSCR3_PF_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define  RI_HYSCR3_PF_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define  RI_HYSCR3_PF_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define  RI_HYSCR3_PF_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define  RI_HYSCR3_PF_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define  RI_HYSCR3_PF_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define  RI_HYSCR3_PF_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define  RI_HYSCR3_PF_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define  RI_HYSCR3_PF_10                ((uint32_t)0x04000000) /*!< Bit 10 */
+#define  RI_HYSCR3_PF_11                ((uint32_t)0x08000000) /*!< Bit 11 */
+#define  RI_HYSCR3_PF_12                ((uint32_t)0x10000000) /*!< Bit 12 */
+#define  RI_HYSCR3_PF_13                ((uint32_t)0x20000000) /*!< Bit 13 */
+#define  RI_HYSCR3_PF_14                ((uint32_t)0x40000000) /*!< Bit 14 */
+#define  RI_HYSCR3_PF_15                ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define  RI_HYSCR4_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
+#define  RI_HYSCR4_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define  RI_HYSCR4_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define  RI_HYSCR4_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define  RI_HYSCR4_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define  RI_HYSCR4_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define  RI_HYSCR4_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define  RI_HYSCR4_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define  RI_HYSCR4_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define  RI_HYSCR4_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define  RI_HYSCR4_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define  RI_HYSCR4_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
+#define  RI_HYSCR4_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
+#define  RI_HYSCR4_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
+#define  RI_HYSCR4_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
+#define  RI_HYSCR4_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
+#define  RI_HYSCR4_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!<OCCS bits (OCref Clear Selection) */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+                   
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+           
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define  TIM_OR_TI1RMP                       ((uint16_t)0x0003)            /*!<Option register for TI1 Remapping */
+#define  TIM_OR_TI1RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_OR_TI1RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< Oversampling by 8-bit mode */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */
+
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One sample bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */
+
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Universal Serial Bus (USB)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!<Endpoint Address */
+
+#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!<Bit 1 */
+
+#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!<Data Toggle, for transmission transfers */
+#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!<Correct Transfer for transmission */
+#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!<Endpoint Kind */
+
+#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!<Bit 0 */
+#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!<Bit 1 */
+
+#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!<Setup transaction completed */
+
+#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!<Data Toggle, for reception transfers */
+#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!<Force USB Reset */
+#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!<Power down */
+#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!<Low-power mode */
+#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!<Force suspend */
+#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!<Resume request */
+#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!<Expected Start Of Frame Interrupt Mask */
+#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!<Start Of Frame Interrupt Mask */
+#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!<RESET Interrupt Mask */
+#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!<Suspend mode Interrupt Mask */
+#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!<Wakeup Interrupt Mask */
+#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!<Error Interrupt Mask */
+#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!<Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!<Endpoint Identifier */
+#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!<Direction of transaction */
+#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!<Expected Start Of Frame */
+#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!<Start Of Frame */
+#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!<USB RESET request */
+#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!<Suspend mode request */
+#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!<Wake up */
+#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!<Error */
+#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!<Packet Memory Area Over / Underrun */
+#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!<Correct Transfer */
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!<Frame Number */
+#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!<Lost SOF */
+#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!<Locked */
+#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!<Receive Data - Line Status */
+#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!<Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!<ADD[6:0] bits (Device Address) */
+#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!<Bit 0 */
+#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!<Bit 1 */
+#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!<Bit 2 */
+#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!<Bit 3 */
+#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!<Bit 4 */
+#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!<Bit 5 */
+#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!<Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/    
+#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!<Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */
+
+#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */
+#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */
+#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */
+#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
+
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
+
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
+#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
+
+#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        SystemTick (SysTick)                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Nested Vectored Interrupt Controller (NVIC)                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32l1xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1XX_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
new file mode 100644
index 0000000..e392277
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
@@ -0,0 +1,104 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    09-March-2012
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm
new file mode 100644
index 0000000..85626cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TASKING/cstart_thumb2.asm
@@ -0,0 +1,140 @@
+
+
+;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;;        we will only use 16-bit Thumb intructions.
+
+        .extern _lc_ub_stack            ; usr/sys mode stack pointer
+        .extern _lc_ue_stack            ; symbol required by debugger
+        .extern _lc_ub_table            ; ROM to RAM copy table
+        .extern main
+        .extern _Exit
+        .extern exit
+        .weak   exit
+        .global __get_argcv
+        .weak   __get_argcv
+        .extern __argcvbuf
+        .weak   __argcvbuf
+        ;;.extern __init_hardware
+        .extern  SystemInit
+        
+    .if @defined('__PROF_ENABLE__')
+        .extern __prof_init
+    .endif
+    .if @defined('__POSIX__')
+        .extern posix_main
+        .extern _posix_boot_stack_top
+    .endif
+
+        .global _START
+
+        .section .text.cstart
+
+        .thumb
+_START:
+        ;; anticipate possible ROM/RAM remapping
+        ;; by loading the 'real' program address
+        ldr     r1,=_Next
+        bx      r1
+_Next:
+        ;; initialize the stack pointer
+        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
+        mov     sp,r1
+
+        ;; call a user function which initializes function.
+        bl  SystemInit
+
+        ;; copy initialized sections from ROM to RAM
+        ;; and clear uninitialized data sections in RAM
+
+        ldr     r3,=_lc_ub_table
+        movs    r0,#0
+cploop:
+        ldr     r4,[r3,#0]      ; load type
+        ldr     r5,[r3,#4]      ; dst address
+        ldr     r6,[r3,#8]      ; src address
+        ldr     r7,[r3,#12]     ; size
+
+        cmp     r4,#1
+        beq     copy
+        cmp     r4,#2
+        beq     clear
+        b       done
+
+copy:
+        subs    r7,r7,#1
+        ldrb    r1,[r6,r7]
+        strb    r1,[r5,r7]
+        bne     copy
+
+        adds    r3,r3,#16
+        b       cploop
+
+clear:
+        subs    r7,r7,#1
+        strb    r0,[r5,r7]
+        bne     clear
+        
+        adds    r3,r3,#16
+        b       cploop
+        
+done:   
+
+      .if @defined('__POSIX__')
+        
+        ;; posix stack buffer for system upbringing
+        ldr     r0,=_posix_boot_stack_top
+        ldr     r0, [r0]
+        mov     sp,r0
+     
+     .else
+        
+        ;; load r10 with end of USR/SYS stack, which is
+        ;; needed in case stack overflow checking is on
+        ;; NOTE: use 16-bit instructions only, for ARMv6M
+        ldr     r0,=_lc_ue_stack
+        mov     r10,r0
+     
+     .endif
+
+    .if @defined('__PROF_ENABLE__')
+        bl      __prof_init
+    .endif
+
+    .if @defined('__POSIX__')
+        ;; call posix_main with no arguments
+        bl      posix_main
+    .else
+        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+        bl      __get_argcv
+        ldr     r1,=__argcvbuf
+        ;; call main
+        bl       main
+    .endif
+
+        ;; call exit using the return value from main()
+        ;; Note. Calling exit will also run all functions
+        ;; that were supplied through atexit().
+        bl      exit
+        
+__get_argcv:                    ; weak definition
+        movs     r0,#0
+        bx      lr
+
+        .ltorg
+        .endsec
+
+        .calls  '_START', '  '
+        .calls  '_START','__init_vector_table'
+    .if @defined('__PROF_ENABLE__')
+        .calls  '_START','__prof_init'
+    .endif
+    .if @defined('__POSIX__')
+        .calls  '_START','posix_main'
+    .else
+        .calls  '_START','__get_argcv'
+        .calls  '_START','main'
+    .endif
+        .calls  '_START','exit'
+        .calls  '_START','',0
+
+        .end
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s
new file mode 100644
index 0000000..45aefde
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_hd.s
@@ -0,0 +1,424 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l1xx_hd.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      09-March-2012
+  * @brief     STM32L1xx Ultra Low Power High-density Devices vector table for 
+  *            Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler  
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word SDIO_IRQHandler
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word AES_IRQHandler
+  .word COMP_ACQ_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L15x ULtra Low Power High-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler  
+
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+  
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+  
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak COMP_ACQ_IRQHandler
+   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..cc8d06c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_mdp.s
@@ -0,0 +1,415 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l1xx_mdp.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      09-March-2012
+  * @brief     STM32L1xx Ultra Low Power Medium-density Plus Devices vector table
+  *            for Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler  
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word 0
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word 0
+  .word 0
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word AES_IRQHandler
+  .word COMP_ACQ_IRQHandler  
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L15x ULtra Low Power Medium-density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler  
+
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+  
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak COMP_ACQ_IRQHandler
+   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..4fc8d5f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_md.s
@@ -0,0 +1,319 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32l1xx_md.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 09-March-2012
+;* Description        : STM32L1xx Ultra Low Power Medium-density Devices vector 
+;*                      table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     LCD_IRQHandler            ; LCD
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0              
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler             [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+LCD_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..8ea1e39
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/arm/startup_stm32l1xx_mdp.s
@@ -0,0 +1,350 @@
+;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32l1xx_mdp.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 09-March-2012
+;* Description        : STM32L1xx Ultra Low Power Medium-density Plus Devices vector 
+;*                      table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; 
+; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+; You may not use this file except in compliance with the License.
+; You may obtain a copy of the License at:
+; 
+;        http://www.st.com/software_license_agreement_liberty_v2
+; 
+; Unless required by applicable law or agreed to in writing, software 
+; distributed under the License is distributed on an "AS IS" BASIS, 
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+; 
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     LCD_IRQHandler            ; LCD
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     0                         ; Reserved
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     AES_IRQHandler            ; AES
+                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0              
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler             [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+                EXPORT  TIM5_IRQHandler            [WEAK]
+                EXPORT  SPI3_IRQHandler            [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
+                EXPORT  AES_IRQHandler             [WEAK]
+                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+LCD_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+AES_IRQHandler
+COMP_ACQ_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s
new file mode 100644
index 0000000..d1e0458
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_hd.s
@@ -0,0 +1,419 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l1xx_hd.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      09-March-2012
+  * @brief     STM32L1xx Ultra Low Power High-density Devices vector table for 
+  *            RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */  
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None     
+ * @retval None       
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/    
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word SDIO_IRQHandler
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word UART4_IRQHandler
+  .word UART5_IRQHandler
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word AES_IRQHandler
+  .word COMP_ACQ_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L15x ULtra Low Power High-density devices. */
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler
+  
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Default_Handler
+
+  .weak TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+  
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak UART5_IRQHandler
+  .thumb_set UART5_IRQHandler,Default_Handler
+  
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak COMP_ACQ_IRQHandler
+   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+  
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..bd72ed0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_md.s
@@ -0,0 +1,371 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l1xx_md.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      09-March-2012
+  * @brief     STM32L1xx Ultra Low Power Medium-density Devices vector table for 
+  *            RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */  
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None     
+ * @retval None       
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/    
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L15x ULtra Low Power Medium-density devices. */
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler
+  
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..d9f3587
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/gcc_ride7/startup_stm32l1xx_mdp.s
@@ -0,0 +1,410 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l1xx_mdp.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      09-March-2012
+  * @brief     STM32L1xx Ultra Low Power Medium-density Plus Devices vector table
+  *            for RIDE7 toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */  
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call the application's entry point.*/
+  bl main
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None     
+ * @retval None       
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/    
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word LCD_IRQHandler
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word 0
+  .word TIM5_IRQHandler
+  .word SPI3_IRQHandler
+  .word 0
+  .word 0
+  .word DMA2_Channel1_IRQHandler
+  .word DMA2_Channel2_IRQHandler
+  .word DMA2_Channel3_IRQHandler
+  .word DMA2_Channel4_IRQHandler
+  .word DMA2_Channel5_IRQHandler
+  .word AES_IRQHandler
+  .word COMP_ACQ_IRQHandler  
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
+                            STM32L15x ULtra Low Power Medium-density Plus devices. */
+   
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+*
+*******************************************************************************/
+    
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Default_Handler
+  
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak TIM5_IRQHandler
+  .thumb_set TIM5_IRQHandler,Default_Handler
+  
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel1_IRQHandler
+  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel2_IRQHandler
+  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel3_IRQHandler
+  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel4_IRQHandler
+  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA2_Channel5_IRQHandler
+  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak COMP_ACQ_IRQHandler
+   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+  
+/************************* (C) COPYRIGHT STMicroelectronics *****END OF FILE***/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s
new file mode 100644
index 0000000..552b42d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_md.s
@@ -0,0 +1,463 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32l1xx_md.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 09-March-2012
+;* Description        : STM32L1xx Ultra Low Power Medium-density Devices vector 
+;*                      table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+        DCD     FLASH_IRQHandler          ; FLASH
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler           ; ADC1
+        DCD     USB_HP_IRQHandler         ; USB High Priority
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority
+        DCD     DAC_IRQHandler            ; DAC
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     LCD_IRQHandler            ; LCD
+        DCD     TIM9_IRQHandler           ; TIM9
+        DCD     TIM10_IRQHandler          ; TIM10
+        DCD     TIM11_IRQHandler          ; TIM11
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+        
+        
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+        
+                
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+        
+        
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        
+        
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+        
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+        
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+        B TAMPER_STAMP_IRQHandler
+        
+        
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+        
+        
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+        
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        
+        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        
+        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        
+        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        
+        
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        
+        
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        
+        
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+        
+        
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+        
+        
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+        
+        
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+        
+        
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+        
+        
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        
+        
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+        
+        
+        PUBWEAK TIM9_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM9_IRQHandler
+        B TIM9_IRQHandler
+        
+        
+        PUBWEAK TIM10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM10_IRQHandler
+        B TIM10_IRQHandler
+        
+        
+        PUBWEAK TIM11_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM11_IRQHandler
+        B TIM11_IRQHandler
+        
+        
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+        
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+        
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+        
+        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        
+        
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        
+        
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        
+        
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        
+        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+        
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+        
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+        
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+        
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+        
+        
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+        
+        
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+        
+        
+        PUBWEAK USB_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_FS_WKUP_IRQHandler
+        B USB_FS_WKUP_IRQHandler
+        
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+        
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler                
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s
new file mode 100644
index 0000000..cba4f98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/iar/startup_stm32l1xx_mdp.s
@@ -0,0 +1,520 @@
+;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
+;* File Name          : startup_stm32l1xx_mdp.s
+;* Author             : MCD Application Team
+;* Version            : V1.1.1
+;* Date               : 09-March-2012
+;* Description        : STM32L1xx Ultra Low Power Medium-density Plus Devices vector 
+;*                      table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+;* You may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at:
+;* 
+;*        http://www.st.com/software_license_agreement_liberty_v2
+;* 
+;* Unless required by applicable law or agreed to in writing, software 
+;* distributed under the License is distributed on an "AS IS" BASIS, 
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;* 
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+        DCD     FLASH_IRQHandler          ; FLASH
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler           ; ADC1
+        DCD     USB_HP_IRQHandler         ; USB High Priority
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority
+        DCD     DAC_IRQHandler            ; DAC
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     LCD_IRQHandler            ; LCD
+        DCD     TIM9_IRQHandler           ; TIM9
+        DCD     TIM10_IRQHandler          ; TIM10
+        DCD     TIM11_IRQHandler          ; TIM11
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+        DCD     0                         ; Reserved
+        DCD     TIM5_IRQHandler           ; TIM5
+        DCD     SPI3_IRQHandler           ; SPI3
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+        DCD     AES_IRQHandler            ; AES
+        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+        
+        
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+        
+                
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+        
+        
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        
+        
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+        
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+        
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TAMPER_STAMP_IRQHandler
+        B TAMPER_STAMP_IRQHandler
+        
+        
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+        
+        
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+        
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        
+        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        
+        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        
+        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        
+        
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        
+        
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        
+        
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+        
+        
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+        
+        
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+        
+        
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+        
+        
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+        
+        
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        
+        
+        PUBWEAK LCD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+LCD_IRQHandler
+        B LCD_IRQHandler
+        
+        
+        PUBWEAK TIM9_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM9_IRQHandler
+        B TIM9_IRQHandler
+        
+        
+        PUBWEAK TIM10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM10_IRQHandler
+        B TIM10_IRQHandler
+        
+        
+        PUBWEAK TIM11_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM11_IRQHandler
+        B TIM11_IRQHandler
+        
+        
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+        
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+        
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+        
+        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        
+        
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        
+        
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        
+        
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        
+        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+        
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+        
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+        
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+        
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+        
+        
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+        
+        
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+        
+        
+        PUBWEAK USB_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_FS_WKUP_IRQHandler
+        B USB_FS_WKUP_IRQHandler
+        
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+        
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK COMP_ACQ_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+COMP_ACQ_IRQHandler
+        B COMP_ACQ_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
new file mode 100644
index 0000000..06528af
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    09-March-2012
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png
new file mode 100644
index 0000000..a542159
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png
new file mode 100644
index 0000000..1cacaf2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_CORE_Files_user.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000..2056b7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/CMSIS_Logo_Final.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html
new file mode 100644
index 0000000..be8279b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html
@@ -0,0 +1,144 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>MISRA-C:2004 Compliance Exceptions</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('_c_o_r_e__m_i_s_r_a__exceptions_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">MISRA-C:2004 Compliance Exceptions </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>CMSIS-CORE uses the common coding rules for CMSIS components that are documented under <a href="../../General/html/index.html"><b>Introduction</b> </a>.</p>
+<p>CMSIS-CORE violates the following MISRA-C:2004 rules:</p>
+<ul>
+<li>Required Rule 8.5, object/function definition in header file.<br/>
+ Violated since function definitions in header files are used to allow 'inlining'.</li>
+</ul>
+<ul>
+<li>Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br/>
+ Violated since unions are used for effective representation of core registers.</li>
+</ul>
+<ul>
+<li>Advisory Rule 19.7, Function-like macro defined.<br/>
+ Violated since function-like macros are used to allow more efficient code. </li>
+</ul>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html
new file mode 100644
index 0000000..bdf0347
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html
@@ -0,0 +1,305 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Register Mapping</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('_reg_map_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Register Mapping </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.</p>
+<table  class="cmtable" summary="Register Mapping">
+<tr>
+<th>CMSIS Register Name </th><th>Cortex-M3 and Cortex-M4 </th><th>Cortex-M0 and Cortex-M0+ </th><th>Register Name  </th></tr>
+<tr>
+<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access  </th></tr>
+<tr>
+<td>NVIC-&gt;ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers  </td></tr>
+<tr>
+<td>NVIC-&gt;ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers  </td></tr>
+<tr>
+<td>NVIC-&gt;ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers  </td></tr>
+<tr>
+<td>NVIC-&gt;ICPR[] </td><td>NVIC_ICPR0..7 </td><td>ICPR </td><td>Interrupt Clear-Pending Registers  </td></tr>
+<tr>
+<td>NVIC-&gt;IABR[] </td><td>NVIC_IABR0..7 </td><td>- </td><td>Interrupt Active Bit Register  </td></tr>
+<tr>
+<td>NVIC-&gt;IP[] </td><td>NVIC_IPR0..59 </td><td>IPR0..7 </td><td>Interrupt Priority Register  </td></tr>
+<tr>
+<td>NVIC-&gt;STIR </td><td>STIR </td><td>- </td><td>Software Triggered Interrupt Register  </td></tr>
+<tr>
+<th colspan="4">System Control Block (SCB) Register Access  </th></tr>
+<tr>
+<td>SCB-&gt;CPUID </td><td>CPUID </td><td>CPUID </td><td>CPUID Base Register  </td></tr>
+<tr>
+<td>SCB-&gt;ICSR </td><td>ICSR </td><td>ICSR </td><td>Interrupt Control and State Register  </td></tr>
+<tr>
+<td>SCB-&gt;VTOR </td><td>VTOR </td><td>- </td><td>Vector Table Offset Register  </td></tr>
+<tr>
+<td>SCB-&gt;AIRCR </td><td>AIRCR </td><td>AIRCR </td><td>Application Interrupt and Reset Control Register  </td></tr>
+<tr>
+<td>SCB-&gt;SCR </td><td>SCR </td><td>SCR </td><td>System Control Register  </td></tr>
+<tr>
+<td>SCB-&gt;CCR </td><td>CCR </td><td>CCR </td><td>Configuration and Control Register  </td></tr>
+<tr>
+<td>SCB-&gt;SHP[] </td><td>SHPR1..3 </td><td>SHPR2..3 </td><td>System Handler Priority Registers  </td></tr>
+<tr>
+<td>SCB-&gt;SHCSR </td><td>SHCSR </td><td>SHCSR </td><td>System Handler Control and State Register  </td></tr>
+<tr>
+<td>SCB-&gt;CFSR </td><td>CFSR </td><td>- </td><td>Configurable Fault Status Registers  </td></tr>
+<tr>
+<td>SCB-&gt;HFSR </td><td>HFSR </td><td>- </td><td>HardFault Status Register  </td></tr>
+<tr>
+<td>SCB-&gt;DFSR </td><td>DFSR </td><td>- </td><td>Debug Fault Status Register  </td></tr>
+<tr>
+<td>SCB-&gt;MMFAR </td><td>MMFAR </td><td>- </td><td>MemManage Fault Address Register  </td></tr>
+<tr>
+<td>SCB-&gt;BFAR </td><td>BFAR </td><td>- </td><td>BusFault Address Register  </td></tr>
+<tr>
+<td>SCB-&gt;AFSR </td><td>AFSR </td><td>- </td><td>Auxiliary Fault Status Register  </td></tr>
+<tr>
+<td>SCB-&gt;PFR[] </td><td>ID_PFR0..1 </td><td>- </td><td>Processor Feature Registers  </td></tr>
+<tr>
+<td>SCB-&gt;DFR </td><td>ID_DFR0 </td><td>- </td><td>Debug Feature Register  </td></tr>
+<tr>
+<td>SCB-&gt;ADR </td><td>ID_AFR0 </td><td>- </td><td>Auxiliary Feature Register  </td></tr>
+<tr>
+<td>SCB-&gt;MMFR[] </td><td>ID_MMFR0..3 </td><td>- </td><td>Memory Model Feature Registers  </td></tr>
+<tr>
+<td>SCB-&gt;ISAR[] </td><td>ID_ISAR0..4 </td><td>- </td><td>Instruction Set Attributes Registers  </td></tr>
+<tr>
+<td>SCB-&gt;CPACR </td><td>CPACR </td><td>- </td><td>Coprocessor Access Control Register  </td></tr>
+<tr>
+<th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access  </th></tr>
+<tr>
+<td>SCnSCB-&gt;ICTR </td><td>ICTR </td><td>- </td><td>Interrupt Controller Type Register  </td></tr>
+<tr>
+<td>SCnSCB-&gt;ACTLR </td><td>ACTLR </td><td>- </td><td>Auxiliary Control Register  </td></tr>
+<tr>
+<th colspan="4">System Timer (SysTick) Control and Status Register Access  </th></tr>
+<tr>
+<td>SysTick-&gt;CTRL </td><td>STCSR </td><td>SYST_CSR </td><td>SysTick Control and Status Register  </td></tr>
+<tr>
+<td>SysTick-&gt;LOAD </td><td>STRVR </td><td>SYST_RVR </td><td>SysTick Reload Value Register  </td></tr>
+<tr>
+<td>SysTick-&gt;VAL </td><td>STCVR </td><td>SYST_CVR </td><td>SysTick Current Value Register  </td></tr>
+<tr>
+<td>SysTick-&gt;CALIB </td><td>STCR </td><td>SYST_CALIB </td><td>SysTick Calibaration Value Register  </td></tr>
+<tr>
+<th colspan="4">Data Watchpoint and Trace (DWT) Register Access  </th></tr>
+<tr>
+<td>DWT-&gt;CTRL </td><td>DWT_CTRL </td><td>- </td><td>Control Register  </td></tr>
+<tr>
+<td>DWT-&gt;CYCCNT </td><td>DWT_CYCCNT </td><td>- </td><td>Cycle Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;CPICNT </td><td>DWT_CPICNT </td><td>- </td><td>CPI Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;EXCCNT </td><td>DWT_EXCCNT </td><td>- </td><td>Exception Overhead Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;SLEEPCNT </td><td>DWT_SLEEPCNT </td><td>- </td><td>Sleep Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;LSUCNT </td><td>DWT_LSUCNT </td><td>- </td><td>LSU Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;FOLDCNT </td><td>DWT_FOLDCNT </td><td>- </td><td>Folded-instruction Count Register  </td></tr>
+<tr>
+<td>DWT-&gt;PCSR </td><td>DWT_PCSR </td><td>- </td><td>Program Counter Sample Register  </td></tr>
+<tr>
+<td>DWT-&gt;COMP0..3 </td><td>DWT_COMP0..3 </td><td>- </td><td>Comparator Register 0..3  </td></tr>
+<tr>
+<td>DWT-&gt;MASK0..3 </td><td>DWT_MASK0..3 </td><td>- </td><td>Mask Register 0..3  </td></tr>
+<tr>
+<td>DWT-&gt;FUNCTION0..3 </td><td>DWT_FUNCTION0..3 </td><td>- </td><td>Function Register 0..3  </td></tr>
+<tr>
+<th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access  </th></tr>
+<tr>
+<td>ITM-&gt;PORT[] </td><td>ITM_STIM0..31 </td><td>- </td><td>Stimulus Port Registers  </td></tr>
+<tr>
+<td>ITM-&gt;TER </td><td>ITM_TER </td><td>- </td><td>Trace Enable Register  </td></tr>
+<tr>
+<td>ITM-&gt;TPR </td><td>ITM_TPR </td><td>- </td><td>ITM Trace Privilege Register  </td></tr>
+<tr>
+<td>ITM-&gt;TCR </td><td>ITM_TCR </td><td>- </td><td>Trace Control Register  </td></tr>
+<tr>
+<th colspan="4">Trace Port Interface (TPIU) Register Access  </th></tr>
+<tr>
+<td>TPI-&gt;SSPSR </td><td>TPIU_SSPR </td><td>- </td><td>Supported Parallel Port Size Register  </td></tr>
+<tr>
+<td>TPI-&gt;CSPSR </td><td>TPIU_CSPSR </td><td>- </td><td>Current Parallel Port Size Register  </td></tr>
+<tr>
+<td>TPI-&gt;ACPR </td><td>TPIU_ACPR </td><td>- </td><td>Asynchronous Clock Prescaler Register  </td></tr>
+<tr>
+<td>TPI-&gt;SPPR </td><td>TPIU_SPPR </td><td>- </td><td>Selected Pin Protocol Register  </td></tr>
+<tr>
+<td>TPI-&gt;FFSR </td><td>TPIU_FFSR </td><td>- </td><td>Formatter and Flush Status Register  </td></tr>
+<tr>
+<td>TPI-&gt;FFCR </td><td>TPIU_FFCR </td><td>- </td><td>Formatter and Flush Control Register  </td></tr>
+<tr>
+<td>TPI-&gt;FSCR </td><td>TPIU_FSCR </td><td>- </td><td>Formatter Synchronization Counter Register  </td></tr>
+<tr>
+<td>TPI-&gt;TRIGGER </td><td>TRIGGER </td><td>- </td><td>TRIGGER  </td></tr>
+<tr>
+<td>TPI-&gt;FIFO0 </td><td>FIFO data 0 </td><td>- </td><td>Integration ETM Data  </td></tr>
+<tr>
+<td>TPI-&gt;ITATBCTR2 </td><td>ITATBCTR2 </td><td>- </td><td>ITATBCTR2  </td></tr>
+<tr>
+<td>TPI-&gt;ITATBCTR0 </td><td>ITATBCTR0 </td><td>- </td><td>ITATBCTR0  </td></tr>
+<tr>
+<td>TPI-&gt;FIFO1 </td><td>FIFO data 1 </td><td>- </td><td>Integration ITM Data  </td></tr>
+<tr>
+<td>TPI-&gt;ITCTRL </td><td>TPIU_ITCTRL </td><td>- </td><td>Integration Mode Control  </td></tr>
+<tr>
+<td>TPI-&gt;CLAIMSET </td><td>CLAIMSET </td><td>- </td><td>Claim tag set  </td></tr>
+<tr>
+<td>TPI-&gt;CLAIMCLR </td><td>CLAIMCLR </td><td>- </td><td>Claim tag clear  </td></tr>
+<tr>
+<td>TPI-&gt;DEVID </td><td>TPIU_DEVID </td><td>- </td><td>TPIU_DEVID  </td></tr>
+<tr>
+<td>TPI-&gt;DEVTYPE </td><td>TPIU_DEVTYPE </td><td>- </td><td>TPIU_DEVTYPE  </td></tr>
+<tr>
+<th colspan="4">Memory Protection Unit (MPU) Register Access  </th></tr>
+<tr>
+<td>MPU-&gt;TYPE </td><td>MPU_TYPE </td><td>- </td><td>MPU Type Register  </td></tr>
+<tr>
+<td>MPU-&gt;CTRL </td><td>MPU_CTRL </td><td>- </td><td>MPU Control Register  </td></tr>
+<tr>
+<td>MPU-&gt;RNR </td><td>MPU_RNR </td><td>- </td><td>MPU Region Number Register  </td></tr>
+<tr>
+<td>MPU-&gt;RBAR </td><td>MPU_RBAR </td><td>- </td><td>MPU Region Base Address Register  </td></tr>
+<tr>
+<td>MPU-&gt;RASR </td><td>MPU_RASR </td><td>- </td><td>MPU Region Attribute and Size Register  </td></tr>
+<tr>
+<td>MPU-&gt;RBAR_A1..3 </td><td>MPU_RBAR_A1..3 </td><td>- </td><td>MPU alias Register  </td></tr>
+<tr>
+<td>MPU-&gt;RSAR_A1..3 </td><td>MPU_RSAR_A1..3 </td><td>- </td><td>MPU alias Register  </td></tr>
+<tr>
+<th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]  </th></tr>
+<tr>
+<td>FPU-&gt;FPCCR </td><td>FPCCR </td><td>- </td><td>FP Context Control Register  </td></tr>
+<tr>
+<td>FPU-&gt;FPCAR </td><td>FPCAR </td><td>- </td><td>FP Context Address Register  </td></tr>
+<tr>
+<td>FPU-&gt;FPDSCR </td><td>FPDSCR </td><td>- </td><td>FP Default Status Control Register  </td></tr>
+<tr>
+<td>FPU-&gt;MVFR0..1 </td><td>MVFR0..1 </td><td>- </td><td>Media and VFP Feature Registers  </td></tr>
+</table>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
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+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html
new file mode 100644
index 0000000..fbaf463
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_templates_pg.html
@@ -0,0 +1,215 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Template Files</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+          <input type="text" id="MSearchField" value="Search" accesskey="S"
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
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+  initNavTree('_templates_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Template Files </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of <a class="el" href="index.html#tested_tools_sec">Tested and Verified Toolchains</a> for compliancy. These template files include the following:</p>
+<ul>
+<li>Register names of the Core Peripherals and names of the Core Exception Vectors.</li>
+<li>Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4)</li>
+<li>Generic startup code and system configuration code.</li>
+</ul>
+<p>The detailed file structure of the CMSIS-CORE is shown in the following picture.</p>
+<div class="image">
+<img src="CMSIS_CORE_Files.png" alt="CMSIS_CORE_Files.png"/>
+<div class="caption">
+CMSIS-CORE File Structure</div></div>
+ <h2><a class="anchor" id="template_files_sec"></a>
+Template Files</h2>
+<p>The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:</p>
+<ul>
+<li><b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.</li>
+<li><b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.</li>
+<li><b>Interrupt vectors</b> in the startup file that are device specific.</li>
+</ul>
+<table  class="cmtable">
+<tr>
+<th>Template File </th><th>Description  </th></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s" </td><td>Startup file template for ARM C/C++ Compiler.  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s" </td><td>Startup file template for GNU GCC ARM Embedded Compiler.  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Source\G++\startup_Device.s" </td><td>Startup file template for GNU Sourcery G++ Compiler.  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s" </td><td>Startup file template for IAR C/C++ Compiler.  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c" </td><td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Include\Device.h" </td><td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.  </td></tr>
+<tr>
+<td>".\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h" </td><td>Generic system device configuration include file.  </td></tr>
+</table>
+<p>In addition ARM provides the following core header files that do not need any modifications.</p>
+<table  class="cmtable">
+<tr>
+<th>Core Header Files </th><th>Description  </th></tr>
+<tr>
+<td><b>core_&lt;cpu&gt;.h</b> </td><td>Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:<ul>
+<li>core_cm0.h: for the Cortex-M0 processor</li>
+<li>core_cm0plus.h: for the Cortex-M0+ processor</li>
+<li>core_cm3.h: for the Cortex-M0 processor</li>
+<li>core_cm4.h: for the Cortex-M0 processor</li>
+<li>core_sc000.h: for the SecurCore SC000 processor</li>
+<li>core_sc300.h: for the SecurCore SC300 processor   </li>
+</ul>
+</td></tr>
+<tr>
+<td><b>core_cmInstr.h</b> </td><td>Defines intrinsic functions to access special Cortex-M instructions.  </td></tr>
+<tr>
+<td><b>core_cmFunc.h</b> </td><td>Defines functions to access the Cortex-M core peripherals.  </td></tr>
+<tr>
+<td><b>core_cm4_simd.h</b> </td><td>Defines intrinsic functions to access the Cortex-M4 SIMD instructions.  </td></tr>
+</table>
+<h2><a class="anchor" id="adapt_template_files_sec"></a>
+Adaption of Template Files to Devices</h2>
+<p>Copy the complete folder including files and replace:</p>
+<ul>
+<li>folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.</li>
+<li>folder name 'Device' with the specific device name e.g.: LPC17xx.</li>
+<li>in the filenames 'Device' with the specific device name e.g.: LPC17xx.</li>
+</ul>
+<p>Each template file contains comments that start with <b>ToDo:</b> that describe a required modification. The template files contain placeholders:</p>
+<table  class="cmtable">
+<tr>
+<th>Placeholder </th><th>Replaced with  </th></tr>
+<tr>
+<td>&lt;Device&gt; </td><td>the specific device name or device family name; i.e. LPC17xx.  </td></tr>
+<tr>
+<td>&lt;DeviceInterrupt&gt; </td><td>a specific interrupt name of the device; i.e. TIM1 for Timer 1. </td></tr>
+<tr>
+<td>&lt;DeviceAbbreviation&gt; </td><td>short name or abbreviation of the device family; i.e. LPC.  </td></tr>
+<tr>
+<td>Cortex-M# </td><td>the specific Cortex-M processor name; i.e. Cortex-M3.  </td></tr>
+</table>
+<p>The adaption of the template files is described in detail on the following pages:</p>
+<ul>
+<li><a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a></li>
+<li><a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a></li>
+<li><a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> </li>
+</ul>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
new file mode 100644
index 0000000..a69504c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html
@@ -0,0 +1,167 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Using CMSIS with generic ARM Processors</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+<div class="header">
+  <div class="headertitle">
+<div class="title">Using CMSIS with generic ARM Processors </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.</p>
+<table  class="cmtable">
+<tr>
+<th>Folder </th><th>Processor </th><th>Description  </th></tr>
+<tr>
+<td>".\Device\ARM\ARMCM0" </td><td>Cortex-M0 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMCM0.h&gt;.   </td></tr>
+<tr>
+<td>".\Device\ARM\ARMCM0plus" </td><td>Cortex-M0+ </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMCM0plus.h&gt;.   </td></tr>
+<tr>
+<td>".\Device\ARM\ARMCM3" </td><td>Cortex-M3 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMCM3.h&gt;.   </td></tr>
+<tr>
+<td>".\Device\ARM\ARMCM4" </td><td>Cortex-M4 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMCM4.h&gt;.   </td></tr>
+<tr>
+<td>".\Device\ARM\ARMSC000" </td><td>SecurCore SC000 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMSC000.h&gt;.   </td></tr>
+<tr>
+<td>".\Device\ARM\ARMSC300" </td><td>SecurCore SC300 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is &lt;ARMSC300.h&gt;.   </td></tr>
+</table>
+<h2><a class="anchor" id="Using_ARM_Lib_sec"></a>
+Create generic Libraries with CMSIS</h2>
+<p>The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The <a href="../../DSP/html/index.html"><b>CMSIS-DSP</b> </a> Libraries are an example for such a generic library.</p>
+<p>To build a generic Library set the define <b>__CMSIS_GENERIC</b> and include the relevant <b>core_&lt;cpu&gt;.h</b> CMSIS CPU &amp; Core Access header file for the processor. The define <b>__CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>. Refer to <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> for a list of the available <b>core_&lt;cpu&gt;.h</b> header files.</p>
+<p><b>Example:</b> </p>
+<p>The following code section shows the usage of the <b>core_&lt;cpu&gt;.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define <b>CORTEX_M4</b>, <b>CORTEX_M3</b>, or <b>CORTEX_M0</b>. By using this header file, the source code can access the functions for <a class="el" href="group___core___register__gr.html">Core Register Access</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html">Intrinsic Functions for CPU Instructions</a>, <a class="el" href="group__intrinsic___s_i_m_d__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4]</a>, and <a class="el" href="group___i_t_m___debug__gr.html">Debug Access</a>.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#define __CMSIS_GENERIC              </span><span class="comment">/* disable NVIC and Systick functions */</span>
+
+<span class="preprocessor">#if defined (CORTEX_M4)</span>
+<span class="preprocessor"></span><span class="preprocessor">  #include &quot;core_cm4.h&quot;</span>
+<span class="preprocessor">#elif defined (CORTEX_M3)</span>
+<span class="preprocessor"></span><span class="preprocessor">  #include &quot;core_cm3.h&quot;</span>
+<span class="preprocessor">#elif defined (CORTEX_M0)</span>
+<span class="preprocessor"></span><span class="preprocessor">  #include &quot;core_cm0.h&quot;</span>
+<span class="preprocessor">#elif defined (CORTEX_M0PLUS)</span>
+<span class="preprocessor"></span><span class="preprocessor">  #include &quot;core_cm0plus.h&quot;</span>
+<span class="preprocessor">#else</span>
+<span class="preprocessor"></span><span class="preprocessor">  #error &quot;Processor not specified or unsupported.&quot;</span>
+<span class="preprocessor">#endif</span>
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using_pg.html
new file mode 100644
index 0000000..4e6a54b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/_using_pg.html
@@ -0,0 +1,216 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Using CMSIS in Embedded Applications</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+<div id="doc-content">
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+  <div class="headertitle">
+<div class="title">Using CMSIS in Embedded Applications </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>To use the CMSIS-CORE the following files are added to the embedded application:</p>
+<ul>
+<li><a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> with reset handler and exception vectors.</li>
+<li><a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a> with general device configuration (i.e. for clock and BUS setup).</li>
+<li><a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> gives access to processor core and all peripherals.</li>
+</ul>
+<dl class="note"><dt><b>Note:</b></dt><dd>The files <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> and <a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a> may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.</dd></dl>
+<p>The <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> is executed after reset and calls <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the <b>main</b> function in the user code. In addition the <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.</p>
+<p>The <a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a> performs the setup for the processor clock. The variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> indicates the CPU clock speed. <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a> describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.</p>
+<p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> is the central include file that the application programmer is using in the C source code. It provides the following features:</p>
+<ul>
+<li><a class="el" href="group__peripheral__gr.html">Peripheral Access</a> provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.</li>
+<li><a class="el" href="group___n_v_i_c__gr.html">Interrupts and Exceptions (NVIC)</a> can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.</li>
+<li><a class="el" href="group__intrinsic___c_p_u__gr.html">Intrinsic Functions for CPU Instructions</a> allow to access special instructions, for example for activating sleep mode or the NOP instruction.</li>
+<li><a class="el" href="group__intrinsic___s_i_m_d__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4]</a> provide access to the DSP-oriented instructions.</li>
+<li><a class="el" href="group___sys_tick__gr.html">Systick Timer (SYSTICK)</a> function to configure and start a periodic timer interrupt.</li>
+<li><a class="el" href="group___i_t_m___debug__gr.html">Debug Access</a> are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.</li>
+</ul>
+<div class="image">
+<img src="CMSIS_CORE_Files_user.png" alt="CMSIS_CORE_Files_user.png"/>
+<div class="caption">
+CMSIS-CORE User Files</div></div>
+<p> The CMSIS-CORE are device specific. In addition, the <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. <a class="el" href="_using__a_r_m_pg.html">Using CMSIS with generic ARM Processors</a> explains how to use CMSIS-CORE for ARM processors.</p>
+<p>For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:</p>
+<table  class="cmtable">
+<tr>
+<th>File </th><th>Description  </th></tr>
+<tr>
+<td>".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" </td><td><a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> for the STM32F10x Connectivity Line device variants.  </td></tr>
+<tr>
+<td>".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" </td><td><a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a> for the STM32F10x device families.  </td></tr>
+<tr>
+<td>".\ARM\INC\ST\STM32F10x\stm32f10x.h" </td><td><a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> for the STM32F10x device families.  </td></tr>
+<tr>
+<td>".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" </td><td><a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> for the STM32F10x device families.  </td></tr>
+</table>
+<dl class="note"><dt><b>Note:</b></dt><dd>The silicon vendors create these device-specific CMSIS-CORE files based on <a class="el" href="_templates_pg.html">Template Files</a> provide by ARM.</dd></dl>
+<p>Thereafter, the functions described under <a href="Modules.html"><b>Reference</b> </a> can be used in the application.</p>
+<p>A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &lt;stm32f10x.h&gt;</span>                           <span class="comment">// File name depends on device used</span>
+
+uint32_t <span class="keyword">volatile</span> msTicks;                       <span class="comment">// Counter for millisecond Interval</span>
+
+<span class="keywordtype">void</span> SysTick_Handler (<span class="keywordtype">void</span>) {                    <span class="comment">// SysTick Interrupt Handler</span>
+  msTicks++;                                     <span class="comment">// Increment Counter</span>
+}
+
+<span class="keywordtype">void</span> WaitForTick (<span class="keywordtype">void</span>)  {
+  uint32_t curTicks;
+
+  curTicks = msTicks;                            <span class="comment">// Save Current SysTick Value</span>
+  <span class="keywordflow">while</span> (msTicks == curTicks)  {                 <span class="comment">// Wait for next SysTick Interrupt</span>
+    <a class="code" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563" title="Wait For Event.">__WFE</a> ();                                    <span class="comment">// Power-Down until next Event/Interrupt</span>
+  }
+}
+
+<span class="keywordtype">void</span> TIM1_UP_IRQHandler (<span class="keywordtype">void</span>) {                 <span class="comment">// Timer Interrupt Handler</span>
+  ;                                              <span class="comment">// Add user code here</span>
+}
+
+<span class="keywordtype">void</span> timer1_init(<span class="keywordtype">int</span> frequency) {                <span class="comment">// Set up Timer (device specific)</span>
+  <a class="code" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority</a> (TIM1_UP_IRQn, 1);            <span class="comment">// Set Timer priority</span>
+  <a class="code" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" title="Enable an external interrupt.">NVIC_EnableIRQ</a> (TIM1_UP_IRQn);                 <span class="comment">// Enable Timer Interrupt</span>
+}
+
+
+<span class="keywordtype">void</span> Device_Initialization (<span class="keywordtype">void</span>)  {             <span class="comment">// Configure &amp; Initialize MCU</span>
+  <span class="keywordflow">if</span> (<a class="code" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config</a> (<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000)) { <span class="comment">// SysTick 1mSec</span>
+       : <span class="comment">// Handle Error </span>
+  }
+  timer1_init ();                                <span class="comment">// setup device-specific timer</span>
+}
+
+
+<span class="comment">// The processor clock is initialized by CMSIS startup + system file</span>
+<span class="keywordtype">void</span> main (<span class="keywordtype">void</span>) {                                   <span class="comment">// user application starts here</span>
+  Device_Initialization ();                      <span class="comment">// Configure &amp; Initialize MCU</span>
+  <span class="keywordflow">while</span> (1)  {                                   <span class="comment">// Endless Loop (the Super-Loop)</span>
+    <a class="code" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013" title="Globally disables interrupts and configurable fault handlers.">__disable_irq</a> ();                            <span class="comment">// Disable all interrupts</span>
+    Get_InputValues ();                          <span class="comment">// Read Values</span>
+    <a class="code" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27" title="Globally enables interrupts and configurable fault handlers.">__enable_irq</a> ();                             <span class="comment">// Enable all interrupts </span>
+    Calculation_Response ();                     <span class="comment">// Calculate Results</span>
+    Output_Response ();                          <span class="comment">// Output Results</span>
+    WaitForTick ();                              <span class="comment">// Synchronize to SysTick Timer</span>
+  }
+}
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/bc_s.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/bc_s.png
new file mode 100644
index 0000000..43f6f23
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/bc_s.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/check.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/check.png
new file mode 100644
index 0000000..094e59c
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/check.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/classes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/classes.html
new file mode 100644
index 0000000..e60173d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/classes.html
@@ -0,0 +1,160 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Data Structure Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
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+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
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+          </span><span class="right">
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+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Data Structure Index</div>  </div>
+</div>
+<div class="contents">
+<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
+<table style="margin: 10px;" align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
+<tr><td rowspan="2" valign="bottom"><a name="letter_A"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;A&#160;&#160;</div></td></tr></table>
+</td><td rowspan="2" valign="bottom"><a name="letter_D"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;D&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_i_t_m___type.html">ITM_Type</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_S"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;S&#160;&#160;</div></td></tr></table>
+</td><td rowspan="2" valign="bottom"><a name="letter_X"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;X&#160;&#160;</div></td></tr></table>
+</td></tr>
+<tr><td rowspan="2" valign="bottom"><a name="letter_M"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;M&#160;&#160;</div></td></tr></table>
+</td></tr>
+<tr><td valign="top"><a class="el" href="union_a_p_s_r___type.html">APSR_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="struct_d_w_t___type.html">DWT_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="struct_s_c_b___type.html">SCB_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="unionx_p_s_r___type.html">xPSR_Type</a>&#160;&#160;&#160;</td></tr>
+<tr><td rowspan="2" valign="bottom"><a name="letter_C"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;C&#160;&#160;</div></td></tr></table>
+</td><td rowspan="2" valign="bottom"><a name="letter_F"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;F&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_m_p_u___type.html">MPU_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td rowspan="2" valign="bottom"><a name="letter_N"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;N&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_sys_tick___type.html">SysTick_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td valign="top"><a class="el" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="struct_f_p_u___type.html">FPU_Type</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_T"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;T&#160;&#160;</div></td></tr></table>
+</td><td></td></tr>
+<tr><td valign="top"><a class="el" href="struct_core_debug___type.html">CoreDebug_Type</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_I"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;I&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_n_v_i_c___type.html">NVIC_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td></td><td></td><td valign="top"><a class="el" href="struct_t_p_i___type.html">TPI_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td></td><td valign="top"><a class="el" href="union_i_p_s_r___type.html">IPSR_Type</a>&#160;&#160;&#160;</td><td></td><td></td><td></td></tr>
+<tr><td></td><td></td><td></td><td></td><td></td></tr>
+</table>
+<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
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+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
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new file mode 100644
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new file mode 100644
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
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+}
+.group1
+{
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+}
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+ul ul {
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+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
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+	color:Maroon;
+	z-index:20;
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+.title {
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+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/doxygen.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/doxygen.png
new file mode 100644
index 0000000..b9ed6a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/doxygen.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png
new file mode 100644
index 0000000..e4a4a81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2doc.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png
new file mode 100644
index 0000000..ad69f0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderclosed.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png
new file mode 100644
index 0000000..a12e307
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2folderopen.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png
new file mode 100644
index 0000000..3b7a29c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2lastnode.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2link.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2link.png
new file mode 100644
index 0000000..e4a4a81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2link.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png
new file mode 100644
index 0000000..37dba19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2mnode.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2node.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2node.png
new file mode 100644
index 0000000..3b7a29c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2node.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png
new file mode 100644
index 0000000..0f94c47
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2pnode.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png
new file mode 100644
index 0000000..3b7a29c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/ftv2vertline.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions.html
new file mode 100644
index 0000000..00189ad
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions.html
@@ -0,0 +1,629 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Data Fields</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
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+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="functions.html"><span>All</span></a></li>
+      <li><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li><a href="#index__"><span>_</span></a></li>
+      <li><a href="#index_a"><span>a</span></a></li>
+      <li><a href="#index_b"><span>b</span></a></li>
+      <li><a href="#index_c"><span>c</span></a></li>
+      <li><a href="#index_d"><span>d</span></a></li>
+      <li><a href="#index_e"><span>e</span></a></li>
+      <li><a href="#index_f"><span>f</span></a></li>
+      <li><a href="#index_h"><span>h</span></a></li>
+      <li><a href="#index_i"><span>i</span></a></li>
+      <li><a href="#index_l"><span>l</span></a></li>
+      <li><a href="#index_m"><span>m</span></a></li>
+      <li><a href="#index_n"><span>n</span></a></li>
+      <li><a href="#index_p"><span>p</span></a></li>
+      <li><a href="#index_q"><span>q</span></a></li>
+      <li><a href="#index_r"><span>r</span></a></li>
+      <li><a href="#index_s"><span>s</span></a></li>
+      <li><a href="#index_t"><span>t</span></a></li>
+      <li><a href="#index_u"><span>u</span></a></li>
+      <li><a href="#index_v"><span>v</span></a></li>
+      <li><a href="#index_w"><span>w</span></a></li>
+      <li><a href="#index_z"><span>z</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('functions.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div>
+
+<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
+<li>_reserved0
+: <a class="el" href="union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
+<li>ACPR
+: <a class="el" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">TPI_Type</a>
+</li>
+<li>ACTLR
+: <a class="el" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">SCnSCB_Type</a>
+</li>
+<li>ADR
+: <a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">SCB_Type</a>
+</li>
+<li>AFSR
+: <a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">SCB_Type</a>
+</li>
+<li>AIRCR
+: <a class="el" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
+<li>b
+: <a class="el" href="union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a>
+</li>
+<li>BFAR
+: <a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>C
+: <a class="el" href="union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a>
+</li>
+<li>CALIB
+: <a class="el" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">SysTick_Type</a>
+</li>
+<li>CCR
+: <a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">SCB_Type</a>
+</li>
+<li>CFSR
+: <a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">SCB_Type</a>
+</li>
+<li>CLAIMCLR
+: <a class="el" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">TPI_Type</a>
+</li>
+<li>CLAIMSET
+: <a class="el" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">TPI_Type</a>
+</li>
+<li>COMP0
+: <a class="el" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">DWT_Type</a>
+</li>
+<li>COMP1
+: <a class="el" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">DWT_Type</a>
+</li>
+<li>COMP2
+: <a class="el" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">DWT_Type</a>
+</li>
+<li>COMP3
+: <a class="el" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">DWT_Type</a>
+</li>
+<li>CPACR
+: <a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">SCB_Type</a>
+</li>
+<li>CPICNT
+: <a class="el" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">DWT_Type</a>
+</li>
+<li>CPUID
+: <a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">SCB_Type</a>
+</li>
+<li>CSPSR
+: <a class="el" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">TPI_Type</a>
+</li>
+<li>CTRL
+: <a class="el" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">DWT_Type</a>
+, <a class="el" href="struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328">MPU_Type</a>
+, <a class="el" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">SysTick_Type</a>
+</li>
+<li>CYCCNT
+: <a class="el" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>DCRDR
+: <a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">CoreDebug_Type</a>
+</li>
+<li>DCRSR
+: <a class="el" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">CoreDebug_Type</a>
+</li>
+<li>DEMCR
+: <a class="el" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">CoreDebug_Type</a>
+</li>
+<li>DEVID
+: <a class="el" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">TPI_Type</a>
+</li>
+<li>DEVTYPE
+: <a class="el" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">TPI_Type</a>
+</li>
+<li>DFR
+: <a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">SCB_Type</a>
+</li>
+<li>DFSR
+: <a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">SCB_Type</a>
+</li>
+<li>DHCSR
+: <a class="el" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">CoreDebug_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>EXCCNT
+: <a class="el" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>FFCR
+: <a class="el" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">TPI_Type</a>
+</li>
+<li>FFSR
+: <a class="el" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">TPI_Type</a>
+</li>
+<li>FIFO0
+: <a class="el" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">TPI_Type</a>
+</li>
+<li>FIFO1
+: <a class="el" href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e">TPI_Type</a>
+</li>
+<li>FOLDCNT
+: <a class="el" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">DWT_Type</a>
+</li>
+<li>FPCA
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type</a>
+</li>
+<li>FPCAR
+: <a class="el" href="struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b">FPU_Type</a>
+</li>
+<li>FPCCR
+: <a class="el" href="struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8">FPU_Type</a>
+</li>
+<li>FPDSCR
+: <a class="el" href="struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6">FPU_Type</a>
+</li>
+<li>FSCR
+: <a class="el" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">TPI_Type</a>
+</li>
+<li>FUNCTION0
+: <a class="el" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">DWT_Type</a>
+</li>
+<li>FUNCTION1
+: <a class="el" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">DWT_Type</a>
+</li>
+<li>FUNCTION2
+: <a class="el" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">DWT_Type</a>
+</li>
+<li>FUNCTION3
+: <a class="el" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
+<li>HFSR
+: <a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>IABR
+: <a class="el" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">NVIC_Type</a>
+</li>
+<li>ICER
+: <a class="el" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">NVIC_Type</a>
+</li>
+<li>ICPR
+: <a class="el" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">NVIC_Type</a>
+</li>
+<li>ICSR
+: <a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">SCB_Type</a>
+</li>
+<li>ICTR
+: <a class="el" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">SCnSCB_Type</a>
+</li>
+<li>IP
+: <a class="el" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">NVIC_Type</a>
+</li>
+<li>ISAR
+: <a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">SCB_Type</a>
+</li>
+<li>ISER
+: <a class="el" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">NVIC_Type</a>
+</li>
+<li>ISPR
+: <a class="el" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">NVIC_Type</a>
+</li>
+<li>ISR
+: <a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a>
+</li>
+<li>IT
+: <a class="el" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a>
+</li>
+<li>ITATBCTR0
+: <a class="el" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">TPI_Type</a>
+</li>
+<li>ITATBCTR2
+: <a class="el" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">TPI_Type</a>
+</li>
+<li>ITCTRL
+: <a class="el" href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198">TPI_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
+<li>LOAD
+: <a class="el" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">SysTick_Type</a>
+</li>
+<li>LSUCNT
+: <a class="el" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
+<li>MASK0
+: <a class="el" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">DWT_Type</a>
+</li>
+<li>MASK1
+: <a class="el" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">DWT_Type</a>
+</li>
+<li>MASK2
+: <a class="el" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">DWT_Type</a>
+</li>
+<li>MASK3
+: <a class="el" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">DWT_Type</a>
+</li>
+<li>MMFAR
+: <a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">SCB_Type</a>
+</li>
+<li>MMFR
+: <a class="el" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976">SCB_Type</a>
+</li>
+<li>MVFR0
+: <a class="el" href="struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1">FPU_Type</a>
+</li>
+<li>MVFR1
+: <a class="el" href="struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d">FPU_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
+<li>N
+: <a class="el" href="union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a>
+</li>
+<li>nPRIV
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
+<li>PCSR
+: <a class="el" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">DWT_Type</a>
+</li>
+<li>PFR
+: <a class="el" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">SCB_Type</a>
+</li>
+<li>PORT
+: <a class="el" href="struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46">ITM_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
+<li>Q
+: <a class="el" href="union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c">xPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
+<li>RASR
+: <a class="el" href="struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03">MPU_Type</a>
+</li>
+<li>RASR_A1
+: <a class="el" href="struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185">MPU_Type</a>
+</li>
+<li>RASR_A2
+: <a class="el" href="struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014">MPU_Type</a>
+</li>
+<li>RASR_A3
+: <a class="el" href="struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d">MPU_Type</a>
+</li>
+<li>RBAR
+: <a class="el" href="struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9">MPU_Type</a>
+</li>
+<li>RBAR_A1
+: <a class="el" href="struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639">MPU_Type</a>
+</li>
+<li>RBAR_A2
+: <a class="el" href="struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395">MPU_Type</a>
+</li>
+<li>RBAR_A3
+: <a class="el" href="struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804">MPU_Type</a>
+</li>
+<li>RESERVED0
+: <a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">NVIC_Type</a>
+, <a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type</a>
+, <a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type</a>
+, <a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">ITM_Type</a>
+, <a class="el" href="struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36">FPU_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">TPI_Type</a>
+</li>
+<li>RESERVED1
+: <a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">ITM_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">TPI_Type</a>
+</li>
+<li>RESERVED2
+: <a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">ITM_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">NVIC_Type</a>
+</li>
+<li>RESERVED3
+: <a class="el" href="struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">NVIC_Type</a>
+</li>
+<li>RESERVED4
+: <a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">NVIC_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type</a>
+</li>
+<li>RESERVED5
+: <a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type</a>
+</li>
+<li>RESERVED7
+: <a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type</a>
+</li>
+<li>RNR
+: <a class="el" href="struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833">MPU_Type</a>
+</li>
+<li>RSERVED1
+: <a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
+<li>SCR
+: <a class="el" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCB_Type</a>
+</li>
+<li>SHCSR
+: <a class="el" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SCB_Type</a>
+</li>
+<li>SHP
+: <a class="el" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">SCB_Type</a>
+</li>
+<li>SLEEPCNT
+: <a class="el" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">DWT_Type</a>
+</li>
+<li>SPPR
+: <a class="el" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">TPI_Type</a>
+</li>
+<li>SPSEL
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a>
+</li>
+<li>SSPSR
+: <a class="el" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">TPI_Type</a>
+</li>
+<li>STIR
+: <a class="el" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">NVIC_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
+<li>T
+: <a class="el" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type</a>
+</li>
+<li>TCR
+: <a class="el" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">ITM_Type</a>
+</li>
+<li>TER
+: <a class="el" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">ITM_Type</a>
+</li>
+<li>TPR
+: <a class="el" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">ITM_Type</a>
+</li>
+<li>TRIGGER
+: <a class="el" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TPI_Type</a>
+</li>
+<li>TYPE
+: <a class="el" href="struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7">MPU_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
+<li>u16
+: <a class="el" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">ITM_Type</a>
+</li>
+<li>u32
+: <a class="el" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">ITM_Type</a>
+</li>
+<li>u8
+: <a class="el" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">ITM_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
+<li>V
+: <a class="el" href="union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a>
+</li>
+<li>VAL
+: <a class="el" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">SysTick_Type</a>
+</li>
+<li>VTOR
+: <a class="el" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
+<li>w
+: <a class="el" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_z"></a>- z -</h3><ul>
+<li>Z
+: <a class="el" href="union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions_vars.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions_vars.html
new file mode 100644
index 0000000..91623ed
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/functions_vars.html
@@ -0,0 +1,629 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Data Fields - Variables</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li class="current"><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="functions.html"><span>All</span></a></li>
+      <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li><a href="#index__"><span>_</span></a></li>
+      <li><a href="#index_a"><span>a</span></a></li>
+      <li><a href="#index_b"><span>b</span></a></li>
+      <li><a href="#index_c"><span>c</span></a></li>
+      <li><a href="#index_d"><span>d</span></a></li>
+      <li><a href="#index_e"><span>e</span></a></li>
+      <li><a href="#index_f"><span>f</span></a></li>
+      <li><a href="#index_h"><span>h</span></a></li>
+      <li><a href="#index_i"><span>i</span></a></li>
+      <li><a href="#index_l"><span>l</span></a></li>
+      <li><a href="#index_m"><span>m</span></a></li>
+      <li><a href="#index_n"><span>n</span></a></li>
+      <li><a href="#index_p"><span>p</span></a></li>
+      <li><a href="#index_q"><span>q</span></a></li>
+      <li><a href="#index_r"><span>r</span></a></li>
+      <li><a href="#index_s"><span>s</span></a></li>
+      <li><a href="#index_t"><span>t</span></a></li>
+      <li><a href="#index_u"><span>u</span></a></li>
+      <li><a href="#index_v"><span>v</span></a></li>
+      <li><a href="#index_w"><span>w</span></a></li>
+      <li><a href="#index_z"><span>z</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('functions.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
+<li>_reserved0
+: <a class="el" href="union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
+<li>ACPR
+: <a class="el" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">TPI_Type</a>
+</li>
+<li>ACTLR
+: <a class="el" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">SCnSCB_Type</a>
+</li>
+<li>ADR
+: <a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">SCB_Type</a>
+</li>
+<li>AFSR
+: <a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">SCB_Type</a>
+</li>
+<li>AIRCR
+: <a class="el" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
+<li>b
+: <a class="el" href="union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a>
+</li>
+<li>BFAR
+: <a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>C
+: <a class="el" href="union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a>
+</li>
+<li>CALIB
+: <a class="el" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">SysTick_Type</a>
+</li>
+<li>CCR
+: <a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">SCB_Type</a>
+</li>
+<li>CFSR
+: <a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">SCB_Type</a>
+</li>
+<li>CLAIMCLR
+: <a class="el" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">TPI_Type</a>
+</li>
+<li>CLAIMSET
+: <a class="el" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">TPI_Type</a>
+</li>
+<li>COMP0
+: <a class="el" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">DWT_Type</a>
+</li>
+<li>COMP1
+: <a class="el" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">DWT_Type</a>
+</li>
+<li>COMP2
+: <a class="el" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">DWT_Type</a>
+</li>
+<li>COMP3
+: <a class="el" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">DWT_Type</a>
+</li>
+<li>CPACR
+: <a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">SCB_Type</a>
+</li>
+<li>CPICNT
+: <a class="el" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">DWT_Type</a>
+</li>
+<li>CPUID
+: <a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">SCB_Type</a>
+</li>
+<li>CSPSR
+: <a class="el" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">TPI_Type</a>
+</li>
+<li>CTRL
+: <a class="el" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">DWT_Type</a>
+, <a class="el" href="struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328">MPU_Type</a>
+, <a class="el" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">SysTick_Type</a>
+</li>
+<li>CYCCNT
+: <a class="el" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>DCRDR
+: <a class="el" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">CoreDebug_Type</a>
+</li>
+<li>DCRSR
+: <a class="el" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">CoreDebug_Type</a>
+</li>
+<li>DEMCR
+: <a class="el" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">CoreDebug_Type</a>
+</li>
+<li>DEVID
+: <a class="el" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">TPI_Type</a>
+</li>
+<li>DEVTYPE
+: <a class="el" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">TPI_Type</a>
+</li>
+<li>DFR
+: <a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">SCB_Type</a>
+</li>
+<li>DFSR
+: <a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">SCB_Type</a>
+</li>
+<li>DHCSR
+: <a class="el" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">CoreDebug_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>EXCCNT
+: <a class="el" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>FFCR
+: <a class="el" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">TPI_Type</a>
+</li>
+<li>FFSR
+: <a class="el" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">TPI_Type</a>
+</li>
+<li>FIFO0
+: <a class="el" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">TPI_Type</a>
+</li>
+<li>FIFO1
+: <a class="el" href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e">TPI_Type</a>
+</li>
+<li>FOLDCNT
+: <a class="el" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">DWT_Type</a>
+</li>
+<li>FPCA
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type</a>
+</li>
+<li>FPCAR
+: <a class="el" href="struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b">FPU_Type</a>
+</li>
+<li>FPCCR
+: <a class="el" href="struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8">FPU_Type</a>
+</li>
+<li>FPDSCR
+: <a class="el" href="struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6">FPU_Type</a>
+</li>
+<li>FSCR
+: <a class="el" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">TPI_Type</a>
+</li>
+<li>FUNCTION0
+: <a class="el" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">DWT_Type</a>
+</li>
+<li>FUNCTION1
+: <a class="el" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">DWT_Type</a>
+</li>
+<li>FUNCTION2
+: <a class="el" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">DWT_Type</a>
+</li>
+<li>FUNCTION3
+: <a class="el" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
+<li>HFSR
+: <a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">SCB_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>IABR
+: <a class="el" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">NVIC_Type</a>
+</li>
+<li>ICER
+: <a class="el" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">NVIC_Type</a>
+</li>
+<li>ICPR
+: <a class="el" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">NVIC_Type</a>
+</li>
+<li>ICSR
+: <a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">SCB_Type</a>
+</li>
+<li>ICTR
+: <a class="el" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">SCnSCB_Type</a>
+</li>
+<li>IP
+: <a class="el" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">NVIC_Type</a>
+</li>
+<li>ISAR
+: <a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">SCB_Type</a>
+</li>
+<li>ISER
+: <a class="el" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">NVIC_Type</a>
+</li>
+<li>ISPR
+: <a class="el" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">NVIC_Type</a>
+</li>
+<li>ISR
+: <a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a>
+</li>
+<li>IT
+: <a class="el" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a>
+</li>
+<li>ITATBCTR0
+: <a class="el" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">TPI_Type</a>
+</li>
+<li>ITATBCTR2
+: <a class="el" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">TPI_Type</a>
+</li>
+<li>ITCTRL
+: <a class="el" href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198">TPI_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
+<li>LOAD
+: <a class="el" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">SysTick_Type</a>
+</li>
+<li>LSUCNT
+: <a class="el" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">DWT_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
+<li>MASK0
+: <a class="el" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">DWT_Type</a>
+</li>
+<li>MASK1
+: <a class="el" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">DWT_Type</a>
+</li>
+<li>MASK2
+: <a class="el" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">DWT_Type</a>
+</li>
+<li>MASK3
+: <a class="el" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">DWT_Type</a>
+</li>
+<li>MMFAR
+: <a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">SCB_Type</a>
+</li>
+<li>MMFR
+: <a class="el" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976">SCB_Type</a>
+</li>
+<li>MVFR0
+: <a class="el" href="struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1">FPU_Type</a>
+</li>
+<li>MVFR1
+: <a class="el" href="struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d">FPU_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
+<li>N
+: <a class="el" href="union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a>
+</li>
+<li>nPRIV
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
+<li>PCSR
+: <a class="el" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">DWT_Type</a>
+</li>
+<li>PFR
+: <a class="el" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">SCB_Type</a>
+</li>
+<li>PORT
+: <a class="el" href="struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46">ITM_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
+<li>Q
+: <a class="el" href="union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c">xPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
+<li>RASR
+: <a class="el" href="struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03">MPU_Type</a>
+</li>
+<li>RASR_A1
+: <a class="el" href="struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185">MPU_Type</a>
+</li>
+<li>RASR_A2
+: <a class="el" href="struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014">MPU_Type</a>
+</li>
+<li>RASR_A3
+: <a class="el" href="struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d">MPU_Type</a>
+</li>
+<li>RBAR
+: <a class="el" href="struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9">MPU_Type</a>
+</li>
+<li>RBAR_A1
+: <a class="el" href="struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639">MPU_Type</a>
+</li>
+<li>RBAR_A2
+: <a class="el" href="struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395">MPU_Type</a>
+</li>
+<li>RBAR_A3
+: <a class="el" href="struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804">MPU_Type</a>
+</li>
+<li>RESERVED0
+: <a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">NVIC_Type</a>
+, <a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type</a>
+, <a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type</a>
+, <a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">ITM_Type</a>
+, <a class="el" href="struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36">FPU_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">TPI_Type</a>
+</li>
+<li>RESERVED1
+: <a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">ITM_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">TPI_Type</a>
+</li>
+<li>RESERVED2
+: <a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">ITM_Type</a>
+, <a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">DWT_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">NVIC_Type</a>
+</li>
+<li>RESERVED3
+: <a class="el" href="struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">NVIC_Type</a>
+</li>
+<li>RESERVED4
+: <a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">NVIC_Type</a>
+, <a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type</a>
+</li>
+<li>RESERVED5
+: <a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type</a>
+, <a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type</a>
+</li>
+<li>RESERVED7
+: <a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type</a>
+</li>
+<li>RNR
+: <a class="el" href="struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833">MPU_Type</a>
+</li>
+<li>RSERVED1
+: <a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
+<li>SCR
+: <a class="el" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCB_Type</a>
+</li>
+<li>SHCSR
+: <a class="el" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SCB_Type</a>
+</li>
+<li>SHP
+: <a class="el" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">SCB_Type</a>
+</li>
+<li>SLEEPCNT
+: <a class="el" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">DWT_Type</a>
+</li>
+<li>SPPR
+: <a class="el" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">TPI_Type</a>
+</li>
+<li>SPSEL
+: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a>
+</li>
+<li>SSPSR
+: <a class="el" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">TPI_Type</a>
+</li>
+<li>STIR
+: <a class="el" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">NVIC_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
+<li>T
+: <a class="el" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type</a>
+</li>
+<li>TCR
+: <a class="el" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">ITM_Type</a>
+</li>
+<li>TER
+: <a class="el" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">ITM_Type</a>
+</li>
+<li>TPR
+: <a class="el" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">ITM_Type</a>
+</li>
+<li>TRIGGER
+: <a class="el" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TPI_Type</a>
+</li>
+<li>TYPE
+: <a class="el" href="struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7">MPU_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
+<li>u16
+: <a class="el" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">ITM_Type</a>
+</li>
+<li>u32
+: <a class="el" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">ITM_Type</a>
+</li>
+<li>u8
+: <a class="el" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">ITM_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
+<li>V
+: <a class="el" href="union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a>
+</li>
+<li>VAL
+: <a class="el" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">SysTick_Type</a>
+</li>
+<li>VTOR
+: <a class="el" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">SCB_Type</a>
+</li>
+</ul>
+
+
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+<li>w
+: <a class="el" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a>
+, <a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a>
+, <a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_z"></a>- z -</h3><ul>
+<li>Z
+: <a class="el" href="union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a>
+, <a class="el" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a>
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+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_enum.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_enum.html
new file mode 100644
index 0000000..1db4027
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_enum.html
@@ -0,0 +1,140 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li class="current"><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
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+</div>
+<script type="text/javascript">
+  initNavTree('globals.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+&#160;<ul>
+<li>IRQn_Type
+: <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">Ref_NVIC.txt</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_eval.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_eval.html
new file mode 100644
index 0000000..5260e40
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_eval.html
@@ -0,0 +1,170 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+      </li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li class="current"><a href="globals_eval.html"><span>Enumerator</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('globals.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+&#160;<ul>
+<li>BusFault_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">Ref_NVIC.txt</a>
+</li>
+<li>DebugMonitor_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">Ref_NVIC.txt</a>
+</li>
+<li>HardFault_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">Ref_NVIC.txt</a>
+</li>
+<li>MemoryManagement_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">Ref_NVIC.txt</a>
+</li>
+<li>NonMaskableInt_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">Ref_NVIC.txt</a>
+</li>
+<li>PendSV_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">Ref_NVIC.txt</a>
+</li>
+<li>PVD_STM_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">Ref_NVIC.txt</a>
+</li>
+<li>SVCall_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">Ref_NVIC.txt</a>
+</li>
+<li>SysTick_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">Ref_NVIC.txt</a>
+</li>
+<li>UsageFault_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">Ref_NVIC.txt</a>
+</li>
+<li>WWDG_STM_IRQn
+: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">Ref_NVIC.txt</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
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+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_func.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_func.html
new file mode 100644
index 0000000..2046327
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/globals_func.html
@@ -0,0 +1,528 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
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+&#160;
+
+<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
+<li>__CLREX()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">Ref_cmInstr.txt</a>
+</li>
+<li>__CLZ()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a>
+</li>
+<li>__disable_fault_irq()
+: <a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a>
+</li>
+<li>__disable_irq()
+: <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">Ref_CoreReg.txt</a>
+</li>
+<li>__DMB()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">Ref_cmInstr.txt</a>
+</li>
+<li>__DSB()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a>
+</li>
+<li>__enable_fault_irq()
+: <a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a>
+</li>
+<li>__enable_irq()
+: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a>
+</li>
+<li>__get_APSR()
+: <a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a>
+</li>
+<li>__get_BASEPRI()
+: <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">Ref_CoreReg.txt</a>
+</li>
+<li>__get_CONTROL()
+: <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">Ref_CoreReg.txt</a>
+</li>
+<li>__get_FAULTMASK()
+: <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">Ref_CoreReg.txt</a>
+</li>
+<li>__get_FPSCR()
+: <a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">Ref_CoreReg.txt</a>
+</li>
+<li>__get_IPSR()
+: <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">Ref_CoreReg.txt</a>
+</li>
+<li>__get_MSP()
+: <a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">Ref_CoreReg.txt</a>
+</li>
+<li>__get_PRIMASK()
+: <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">Ref_CoreReg.txt</a>
+</li>
+<li>__get_PSP()
+: <a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">Ref_CoreReg.txt</a>
+</li>
+<li>__get_xPSR()
+: <a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">Ref_CoreReg.txt</a>
+</li>
+<li>__ISB()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">Ref_cmInstr.txt</a>
+</li>
+<li>__LDREXB()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">Ref_cmInstr.txt</a>
+</li>
+<li>__LDREXH()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">Ref_cmInstr.txt</a>
+</li>
+<li>__LDREXW()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">Ref_cmInstr.txt</a>
+</li>
+<li>__NOP()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">Ref_cmInstr.txt</a>
+</li>
+<li>__PKHBT()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">Ref_cm4_simd.txt</a>
+</li>
+<li>__PKHTB()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">Ref_cm4_simd.txt</a>
+</li>
+<li>__QADD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">Ref_cm4_simd.txt</a>
+</li>
+<li>__QADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">Ref_cm4_simd.txt</a>
+</li>
+<li>__QADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">Ref_cm4_simd.txt</a>
+</li>
+<li>__QASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">Ref_cm4_simd.txt</a>
+</li>
+<li>__QSAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">Ref_cm4_simd.txt</a>
+</li>
+<li>__QSUB()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">Ref_cm4_simd.txt</a>
+</li>
+<li>__QSUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5">Ref_cm4_simd.txt</a>
+</li>
+<li>__QSUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61">Ref_cm4_simd.txt</a>
+</li>
+<li>__RBIT()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">Ref_cmInstr.txt</a>
+</li>
+<li>__REV()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">Ref_cmInstr.txt</a>
+</li>
+<li>__REV16()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">Ref_cmInstr.txt</a>
+</li>
+<li>__REVSH()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">Ref_cmInstr.txt</a>
+</li>
+<li>__ROR()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">Ref_cmInstr.txt</a>
+</li>
+<li>__SADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984">Ref_cm4_simd.txt</a>
+</li>
+<li>__SADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac20aa0f741d0a1494d58c531e38d5785">Ref_cm4_simd.txt</a>
+</li>
+<li>__SASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a">Ref_cm4_simd.txt</a>
+</li>
+<li>__SEL()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe">Ref_cm4_simd.txt</a>
+</li>
+<li>__set_BASEPRI()
+: <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">Ref_CoreReg.txt</a>
+</li>
+<li>__set_CONTROL()
+: <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">Ref_CoreReg.txt</a>
+</li>
+<li>__set_FAULTMASK()
+: <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">Ref_CoreReg.txt</a>
+</li>
+<li>__set_FPSCR()
+: <a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">Ref_CoreReg.txt</a>
+</li>
+<li>__set_MSP()
+: <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">Ref_CoreReg.txt</a>
+</li>
+<li>__set_PRIMASK()
+: <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">Ref_CoreReg.txt</a>
+</li>
+<li>__set_PSP()
+: <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">Ref_CoreReg.txt</a>
+</li>
+<li>__SEV()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">Ref_cmInstr.txt</a>
+</li>
+<li>__SHADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">Ref_cm4_simd.txt</a>
+</li>
+<li>__SHADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea">Ref_cm4_simd.txt</a>
+</li>
+<li>__SHASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">Ref_cm4_simd.txt</a>
+</li>
+<li>__SHSAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">Ref_cm4_simd.txt</a>
+</li>
+<li>__SHSUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">Ref_cm4_simd.txt</a>
+</li>
+<li>__SHSUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLAD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLADX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLALD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLALDX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLSD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLSDX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLSLD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMLSLDX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga83e69ef81057d3cbd06863d729385187">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMUAD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMUADX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaee6390f86965cb662500f690b0012092">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMUSD()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga039142a5368840683cf329cb55b73f84">Ref_cm4_simd.txt</a>
+</li>
+<li>__SMUSDX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">Ref_cm4_simd.txt</a>
+</li>
+<li>__SSAT()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">Ref_cmInstr.txt</a>
+</li>
+<li>__SSAT16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga95e666b82216066bf6064d1244e6883c">Ref_cm4_simd.txt</a>
+</li>
+<li>__SSAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">Ref_cm4_simd.txt</a>
+</li>
+<li>__SSUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">Ref_cm4_simd.txt</a>
+</li>
+<li>__SSUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">Ref_cm4_simd.txt</a>
+</li>
+<li>__STREXB()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">Ref_cmInstr.txt</a>
+</li>
+<li>__STREXH()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">Ref_cmInstr.txt</a>
+</li>
+<li>__STREXW()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">Ref_cmInstr.txt</a>
+</li>
+<li>__SXTAB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac540b4fc41d30778ba102d2a65db5589">Ref_cm4_simd.txt</a>
+</li>
+<li>__SXTB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a>
+</li>
+<li>__UADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">Ref_cm4_simd.txt</a>
+</li>
+<li>__UADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab3d7fd00d113b20fb3741a17394da762">Ref_cm4_simd.txt</a>
+</li>
+<li>__UASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga980353d2c72ebb879282e49f592fddc0">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabd0b0e2da2e6364e176d051687702b86">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga028f0732b961fb6e5209326fb3855261">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHSAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga09e129e6613329aab87c89f1108b7ed7">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHSUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">Ref_cm4_simd.txt</a>
+</li>
+<li>__UHSUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga48a55df1c3e73923b73819d7c19b392d">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQADD16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9e2cc5117e79578a08b25f1e89022966">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQADD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafa9af218db3934a692fb06fa728d8031">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQASX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQSAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gadecfdfabc328d8939d49d996f2fd4482">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQSUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5ec4e2e231d15e5c692233feb3806187">Ref_cm4_simd.txt</a>
+</li>
+<li>__UQSUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9736fe816aec74fe886e7fb949734eab">Ref_cm4_simd.txt</a>
+</li>
+<li>__USAD8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac8855c07044239ea775c8128013204f0">Ref_cm4_simd.txt</a>
+</li>
+<li>__USADA8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">Ref_cm4_simd.txt</a>
+</li>
+<li>__USAT()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">Ref_cmInstr.txt</a>
+</li>
+<li>__USAT16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga967f516afff5900cf30f1a81907cdd89">Ref_cm4_simd.txt</a>
+</li>
+<li>__USAX()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e">Ref_cm4_simd.txt</a>
+</li>
+<li>__USUB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">Ref_cm4_simd.txt</a>
+</li>
+<li>__USUB8()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">Ref_cm4_simd.txt</a>
+</li>
+<li>__UXTAB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09">Ref_cm4_simd.txt</a>
+</li>
+<li>__UXTB16()
+: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228">Ref_cm4_simd.txt</a>
+</li>
+<li>__WFE()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">Ref_cmInstr.txt</a>
+</li>
+<li>__WFI()
+: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">Ref_cmInstr.txt</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>ITM_CheckChar()
+: <a class="el" href="group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">Ref_Debug.txt</a>
+</li>
+<li>ITM_ReceiveChar()
+: <a class="el" href="group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">Ref_Debug.txt</a>
+</li>
+<li>ITM_SendChar()
+: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">Ref_Debug.txt</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
+<li>NVIC_ClearPendingIRQ()
+: <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_DecodePriority()
+: <a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_DisableIRQ()
+: <a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_EnableIRQ()
+: <a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_EncodePriority()
+: <a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_GetActive()
+: <a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_GetPendingIRQ()
+: <a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_GetPriority()
+: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_GetPriorityGrouping()
+: <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_SetPendingIRQ()
+: <a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_SetPriority()
+: <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_SetPriorityGrouping()
+: <a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354">Ref_NVIC.txt</a>
+</li>
+<li>NVIC_SystemReset()
+: <a class="el" href="group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">Ref_NVIC.txt</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
+<li>SystemCoreClockUpdate()
+: <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">Ref_SystemAndClock.txt</a>
+</li>
+<li>SystemInit()
+: <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">Ref_SystemAndClock.txt</a>
+</li>
+<li>SysTick_Config()
+: <a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">Ref_Systick.txt</a>
+</li>
+</ul>
+</div>
+</div>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html
new file mode 100644
index 0000000..1974899
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___core___register__gr.html
@@ -0,0 +1,1148 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
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+<!-- Generated by Doxygen 1.7.5.1 -->
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+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Core Register Access</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the CONTROL register.  <a href="#ga963cf236b73219ce78e965deb01b81a7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a> (uint32_t control)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the CONTROL Register.  <a href="#gac64d37e7ff9de06437f9fb94bbab8b6c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">__get_IPSR</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the IPSR register.  <a href="#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the APSR register.  <a href="#ga811c0012221ee918a75111ca84c4d5e7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the xPSR register.  <a href="#ga732e08184154f44a617963cc65ff95bd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the PSP register.  <a href="#ga914dfa8eff7ca53380dd54cf1d8bebd9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a> (uint32_t topOfProcStack)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the PSP register.  <a href="#ga48e5853f417e17a8a65080f6a605b743"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the MSP register.  <a href="#gab898559392ba027814e5bbb5a98b38d2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a> (uint32_t topOfMainStack)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the MSP register.  <a href="#ga0bf9564ebc1613a8faba014275dac2a4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the PRIMASK register bit.  <a href="#ga799b5d9a2ae75e459264c8512c7c0e02"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a> (uint32_t priMask)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Priority Mask bit.  <a href="#ga70b4e1a6c1c86eb913fb9d6e8400156f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the BASEPRI register [not for Cortex-M0 variants].  <a href="#ga32da759f46e52c95bcfbde5012260667"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a> (uint32_t basePri)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the BASEPRI register [not for Cortex-M0 variants].  <a href="#ga360c73eb7ffb16088556f9278953b882"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the FAULTMASK register [not for Cortex-M0 variants].  <a href="#gaa78e4e6bf619a65e9f01b4af13fed3a8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a> (uint32_t faultMask)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the FAULTMASK register [not for Cortex-M0 variants].  <a href="#gaa5587cc09031053a40a35c14ec36078a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">__get_FPSCR</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the FPSCR register [only for Cortex-M4].  <a href="#gad6d7eca9ddd1d9072dd7b020cfe64905"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">__set_FPSCR</a> (uint32_t fpscr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the FPSC register [only for Cortex-M4].  <a href="#ga6f26bd75ca7e3247f27b272acc10536b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Globally enables interrupts and configurable fault handlers.  <a href="#ga0f98dfbd252b89d12564472dbeba9c27"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Globally disables interrupts and configurable fault handlers.  <a href="#gaeb8e5f7564a8ea23678fe3c987b04013"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">__enable_fault_irq</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables interrupts and all fault handlers [not for Cortex-M0 variants].  <a href="#ga6575d37863cec5d334864f93b5b783bf"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">__disable_fault_irq</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables interrupts and all fault handlers [not for Cortex-M0 variants].  <a href="#ga9d174f979b2f76fdb3228a9b338fd939"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The following functions provide access to Cortex-M core registers. </p>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga9d174f979b2f76fdb3228a9b338fd939"></a><!-- doxytag: member="Ref_CoreReg.txt::__disable_fault_irq" ref="ga9d174f979b2f76fdb3228a9b338fd939" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __disable_fault_irq </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function disables interrupts and all fault handlers by setting the F-bit in the CPSR. The function uses the instruction <b>CPSID f</b>.</p>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Can be executed in privileged mode only.</li>
+<li>An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">__enable_fault_irq</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a>; <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0 variants].">__set_FAULTMASK</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaeb8e5f7564a8ea23678fe3c987b04013"></a><!-- doxytag: member="Ref_CoreReg.txt::__disable_irq" ref="gaeb8e5f7564a8ea23678fe3c987b04013" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __disable_irq </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function disables interrupts and all configurable fault handlers by setting the I-bit in the CPSR. The function uses the instruction <b>CPSID i</b>.</p>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Can be executed in privileged mode only.</li>
+<li>Basically, it sets PRIMASK.</li>
+<li>An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a>; <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit.">__set_PRIMASK</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6575d37863cec5d334864f93b5b783bf"></a><!-- doxytag: member="Ref_CoreReg.txt::__enable_fault_irq" ref="ga6575d37863cec5d334864f93b5b783bf" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __enable_fault_irq </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function enables interrupts and all fault handlers by clearing the F-bit in the CPSR. The function uses the instruction <b>CPSIE f</b>.</p>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Can be executed in privileged mode only.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">__disable_fault_irq</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a>; <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0 variants].">__set_FAULTMASK</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0f98dfbd252b89d12564472dbeba9c27"></a><!-- doxytag: member="Ref_CoreReg.txt::__enable_irq" ref="ga0f98dfbd252b89d12564472dbeba9c27" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __enable_irq </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function enables interrupts and all configurable fault handlers by clearing the I-bit in the CPSR. The function uses the instruction <b>CPSIE i</b>.</p>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Can be executed in privileged mode only.</li>
+<li>Basically, it clears PRIMASK.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a>; <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit.">__set_PRIMASK</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga811c0012221ee918a75111ca84c4d5e7"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_APSR" ref="ga811c0012221ee918a75111ca84c4d5e7" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_APSR </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Application Program Status Register (APSR) using the instruction <b>MRS</b>. <br/>
+<br/>
+ The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:</p>
+<ul>
+<li><b>N</b> (APSR[31]) (Negative flag)<ul>
+<li>=1 The instruction result has a negative value (when interpreted as signed integer).</li>
+<li>=0 The instruction result has a positive value or equal zero. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>Z</b> (APSR[30]) (Zero flag)<ul>
+<li>=1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>C</b> (APSR[29]) (Carry or borrow flag)<ul>
+<li>=1 For unsigned additions, if an unsigned overflow occurred.</li>
+<li>=<em>inverse of borrow output status</em> For unsigned subtract operations. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>V</b> (APSR[28]) (Overflow flag)<ul>
+<li>=1 A signed overflow occurred (for signed additions or subtractions). <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>Q</b> (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]<ul>
+<li>This flag is a <em>sticky</em> flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.</li>
+<li>=1 When saturation or an overflow occurred. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>GE</b> (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]<ul>
+<li>Can be set by the parallel add and subtract instructions.</li>
+<li>Are used by the <code>SEL</code> instruction to perform byte-based selection from two registers.</li>
+</ul>
+</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>APSR register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Some instructions update all flags; some instructions update a subset of the flags.</li>
+<li>If a flag is not updated, the original value is preserved.</li>
+<li>Conditional instructions that are not executed have no effect on the flags.</li>
+<li>The CMSIS does not provide a function to update this register.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a>; <a class="el" href="union_a_p_s_r___type.html" title="Union type to access the Application Program Status Register (APSR).">APSR_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga32da759f46e52c95bcfbde5012260667"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_BASEPRI" ref="ga32da759f46e52c95bcfbde5012260667" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_BASEPRI </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function returns the Base Priority Mask register (BASEPRI) using the instruction <b>MRS</b>. <br/>
+<br/>
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>BASEPRI register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8" title="Read the FAULTMASK register [not for Cortex-M0 variants].">__get_FAULTMASK</a>; <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02" title="Read the PRIMASK register bit.">__get_PRIMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga963cf236b73219ce78e965deb01b81a7"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_CONTROL" ref="ga963cf236b73219ce78e965deb01b81a7" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_CONTROL </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the CONTROL register value using the instruction <b>MRS</b>. <br/>
+<br/>
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/>
+</p>
+<ul>
+<li><b>CONTROL</b>[2] [only Cortex-M4]<ul>
+<li>=0 FPU not active</li>
+<li>=1 FPU active <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>CONTROL</b>[1]<ul>
+<li>=0 In handler mode - MSP is selected. No alternate stack possible for handler mode.</li>
+<li>=0 In thread mode - Default stack pointer MSP is used.</li>
+<li>=1 In thread mode - Alternate stack pointer PSP is used. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>CONTROL</b>[0] [not Cortex-M0]<ul>
+<li>=0 In thread mode and privileged state.</li>
+<li>=1 In thread mode and user state.</li>
+</ul>
+</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>CONTROL register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The processor can be in user state or privileged state when running in thread mode.</li>
+<li>Exception handlers always run in privileged state.</li>
+<li>On reset, the processor is in thread mode with privileged access rights.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a>; <a class="el" href="union_c_o_n_t_r_o_l___type.html" title="Union type to access the Control Registers (CONTROL).">CONTROL_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa78e4e6bf619a65e9f01b4af13fed3a8"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_FAULTMASK" ref="gaa78e4e6bf619a65e9f01b4af13fed3a8" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_FAULTMASK </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Fault Mask register (FAULTMASK) value using the instruction <b>MRS</b>. <br/>
+<br/>
+ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>FAULTMASK register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a>; <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0 variants].">__get_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02" title="Read the PRIMASK register bit.">__get_PRIMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad6d7eca9ddd1d9072dd7b020cfe64905"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_FPSCR" ref="gad6d7eca9ddd1d9072dd7b020cfe64905" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_FPSCR </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Floating-Point Status Control Register (FPSCR) value. <br/>
+<br/>
+ FPSCR provides all necessary User level controls of the floating-point system.</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
+<li>FPSCR register value, when __FPU_PRESENT=1</li>
+<li>=0, when __FPU_PRESENT=0</li>
+</ul>
+</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only for Cortex-M4.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">__set_FPSCR</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_IPSR" ref="ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_IPSR </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Interrupt Program Status Register (IPSR) using the instruction <b>MRS</b>. <br/>
+<br/>
+ The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:</p>
+<ul>
+<li><b>ISR_NUMBER</b> (IPSR[8:0])<ul>
+<li>=0 Thread mode</li>
+<li>=1 Reserved</li>
+<li>=2 NMI</li>
+<li>=3 HardFault</li>
+<li>=4 MemManage</li>
+<li>=5 BusFault</li>
+<li>=6 UsageFault</li>
+<li>=7-10 Reserved</li>
+<li>=11 SVCall</li>
+<li>=12 Reserved for Debug</li>
+<li>=13 Reserved</li>
+<li>=14 PendSV</li>
+<li>=15 SysTick</li>
+<li>=16 IRQ0</li>
+<li>...</li>
+<li>=n+15 IRQ(n-1)</li>
+</ul>
+</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>ISPR register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>This register is read-only.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a>; <a class="el" href="union_i_p_s_r___type.html" title="Union type to access the Interrupt Program Status Register (IPSR).">IPSR_Type</a></li>
+<li><a class="el" href="group___n_v_i_c__gr.html">Interrupts and Exceptions (NVIC)</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab898559392ba027814e5bbb5a98b38d2"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_MSP" ref="gab898559392ba027814e5bbb5a98b38d2" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_MSP </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Main Status Pointer (MSP) value using the instruction <b>MRS</b>. <br/>
+<br/>
+ Physically two different stack pointers (SP) exist:</p>
+<ul>
+<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li>
+<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li>
+</ul>
+<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p>
+<ul>
+<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li>
+<li>=1 PSP is the current stack pointer. The initial value is undefined.</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>MSP Register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only one of the two SPs is visible at a time.</li>
+<li>For many applications, the system can completely rely on the MSP.</li>
+<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a>; <a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9" title="Read the PSP register.">__get_PSP</a>; <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7" title="Read the CONTROL register.">__get_CONTROL</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga799b5d9a2ae75e459264c8512c7c0e02"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_PRIMASK" ref="ga799b5d9a2ae75e459264c8512c7c0e02" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_PRIMASK </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Priority Mask register (PRIMASK) value using the instruction <b>MRS</b>. <br/>
+<br/>
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>PRIMASK register value<ul>
+<li>=0 no effect</li>
+<li>=1 prevents the activation of all exceptions with configurable priority</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a>; <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0 variants].">__get_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8" title="Read the FAULTMASK register [not for Cortex-M0 variants].">__get_FAULTMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga914dfa8eff7ca53380dd54cf1d8bebd9"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_PSP" ref="ga914dfa8eff7ca53380dd54cf1d8bebd9" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_PSP </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the Program Status Pointer (PSP) value using the instruction <b>MRS</b>. <br/>
+<br/>
+ Physically two different stack pointers (SP) exist:</p>
+<ul>
+<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li>
+<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li>
+</ul>
+<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p>
+<ul>
+<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li>
+<li>=1 PSP is the current stack pointer. The initial value is undefined.</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>PSP register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only one of the two SPs is visible at a time.</li>
+<li>For many applications, the system can completely rely on the MSP.</li>
+<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a>; <a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2" title="Read the MSP register.">__get_MSP</a>; <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7" title="Read the CONTROL register.">__get_CONTROL</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga732e08184154f44a617963cc65ff95bd"></a><!-- doxytag: member="Ref_CoreReg.txt::__get_xPSR" ref="ga732e08184154f44a617963cc65ff95bd" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __get_xPSR </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function reads the combined Program Status Register (xPSR) using the instruction <b>MRS</b>. <br/>
+<br/>
+ xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: </p>
+<ul>
+<li>Application Program Status Register (APSR) </li>
+<li>Interrupt Program Status Register (IPSR) </li>
+<li>Execution Program Status Register (EPSR)</li>
+</ul>
+<p>In addition to the flags described in <a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a> and <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">__get_IPSR</a>, the register provides the following flags:</p>
+<ul>
+<li><b>IT</b> (xPSR[26:25]) (If-Then condition instruction)<ul>
+<li>Contains up to four instructions following an IT instruction.</li>
+<li>Each instruction in the block is conditional.</li>
+<li>The conditions for the instructions are either all the same, or some can be the inverse of others. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>T</b> (xPSR[24]) (Thumb bit)<ul>
+<li>=1 Indicates that that the processor is in Thumb state.</li>
+<li>=0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.</li>
+<li>The conditions for the instructions are either all the same, or some can be the inverse of others.</li>
+</ul>
+</li>
+</ul>
+<dl class="return"><dt><b>Returns:</b></dt><dd>xPSR register value</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The CMSIS does not provide functions that access EPSR.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a>; <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8" title="Read the IPSR register.">__get_IPSR</a>; <a class="el" href="unionx_p_s_r___type.html" title="Union type to access the Special-Purpose Program Status Registers (xPSR).">xPSR_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga360c73eb7ffb16088556f9278953b882"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_BASEPRI" ref="ga360c73eb7ffb16088556f9278953b882" args="(uint32_t basePri)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_BASEPRI </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>basePri</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Base Priority Mask register (BASEPRI) value using the instruction <b>MSR</b>. <br/>
+<br/>
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">basePri</td><td>BASEPRI value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Cannot be set in user state.</li>
+<li>Useful for changing the masking level or disabling the masking.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0 variants].">__set_FAULTMASK</a>; <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit.">__set_PRIMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac64d37e7ff9de06437f9fb94bbab8b6c"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_CONTROL" ref="gac64d37e7ff9de06437f9fb94bbab8b6c" args="(uint32_t control)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_CONTROL </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>control</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the CONTROL register value using the instruction <b>MSR</b>. <br/>
+<br/>
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/>
+</p>
+<ul>
+<li><b>CONTROL</b>[2] [only Cortex-M4]<ul>
+<li>=0 FPU not active</li>
+<li>=1 FPU active <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>CONTROL</b>[1]<ul>
+<li>Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).</li>
+<li>=0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.</li>
+<li>=0 In thread mode - Default stack pointer MSP is used.</li>
+<li>=1 In thread mode - Alternate stack pointer PSP is used. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>CONTROL</b>[0] [not writeable for Cortex-M0]<ul>
+<li>Writeable only when the processor is in privileged state.</li>
+<li>Can be used to switch the processor to user state (thread mode).</li>
+<li>Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).</li>
+<li>=0 In thread mode and privileged state.</li>
+<li>=1 In thread mode and user state.</li>
+</ul>
+</li>
+</ul>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">control</td><td>CONTROL register value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The processor can be in user state or privileged state when running in thread mode.</li>
+<li>Exception handlers always run in privileged state.</li>
+<li>On reset, the processor is in thread mode with privileged access rights.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a>; <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743" title="Set the PSP register.">__set_PSP</a>; <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4" title="Set the MSP register.">__set_MSP</a>; <a class="el" href="union_c_o_n_t_r_o_l___type.html" title="Union type to access the Control Registers (CONTROL).">CONTROL_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa5587cc09031053a40a35c14ec36078a"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_FAULTMASK" ref="gaa5587cc09031053a40a35c14ec36078a" args="(uint32_t faultMask)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_FAULTMASK </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>faultMask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Fault Mask register (FAULTMASK) value using the instruction <b>MSR</b>. <br/>
+<br/>
+ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:</p>
+<ol type="1">
+<li><b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.</li>
+<li><b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.</li>
+</ol>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">faultMask</td><td>FAULTMASK register value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.</li>
+<li>When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.</li>
+<li>Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).</li>
+<li>When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit.">__set_PRIMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6f26bd75ca7e3247f27b272acc10536b"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_FPSCR" ref="ga6f26bd75ca7e3247f27b272acc10536b" args="(uint32_t fpscr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_FPSCR </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>fpscr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Floating-Point Status Control Register (FPSCR) value. <br/>
+<br/>
+ FPSCR provides all necessary User level control of the floating-point system. <br/>
+</p>
+<ul>
+<li><b>N</b> (FPSC[31]) (Negative flag)<ul>
+<li>=1 The instruction result has a negative value (when interpreted as signed integer).</li>
+<li>=0 The instruction result has a positive value or equal zero. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>Z</b> (FPSC[30]) (Zero flag)<ul>
+<li>=1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>C</b> (FPSC[29]) (Carry or borrow flag)<ul>
+<li>=1 For unsigned additions, if an unsigned overflow occurred.</li>
+<li>=<em>inverse of borrow output status</em> For unsigned subtract operations. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>V</b> (FPSC[28]) (Overflow flag)<ul>
+<li>=1 A signed overflow occurred (for signed additions or subtractions). <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>AHP</b> (FPSC[26]) (Alternative half-precision flag)<ul>
+<li>=1 Alternative half-precision format selected.</li>
+<li>=0 IEEE half-precision format selected. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>DN</b> (FPSC[25]) (Default NaN mode control flag)<ul>
+<li>=1 Any operation involving one or more NaNs returns the Default NaN.</li>
+<li>=0 NaN operands propagate through to the output of a floating-point operation. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>FZ</b> (FPSC[24]) (Flush-to-zero mode control flag)<ul>
+<li>=1 Flush-to-zero mode enabled.</li>
+<li>=0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>RMode</b> (FPSC[23:22]) (Rounding Mode control flags)<ul>
+<li>=0b00 Round to Nearest (RN) mode.</li>
+<li>=0b01 Round towards Plus Infinity (RP) mode.</li>
+<li>=0b10 Round towards Minus Infinity (RM) mode.</li>
+<li>=0b11 Round towards Zero (RZ) mode.</li>
+<li>The specified rounding mode is used by almost all floating-point instructions. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>IDC</b> (FPSC[7]) (Input Denormal cumulative exception flags)<ul>
+<li>See Cumulative exception bits (FPSC[4:0]). <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>IXC</b> (FPSC[4]) (Inexact cumulative exception flag)<ul>
+<li>=1 Exception occurred.</li>
+<li>=0 Value has to be set explicitly.</li>
+<li>Flag is not cleared automatically. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>UFC</b> (FPSC[3]) (Underflow cumulative exception flag)<ul>
+<li>=1 Exception occurred.</li>
+<li>=0 Value has to be set explicitly.</li>
+<li>Flag is not cleared automatically. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>OFC</b> (FPSC[2]) (Overflow cumulative exception flag)<ul>
+<li>=1 Exception occurred.</li>
+<li>=0 Value has to be set explicitly.</li>
+<li>Flag is not cleared automatically. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>DZC</b> (FPSC[1]) (Division by Zero cumulative exception flag)<ul>
+<li>=1 Exception occurred.</li>
+<li>=0 Value has to be set explicitly.</li>
+<li>Flag is not cleared automatically. <br/>
+<br/>
+</li>
+</ul>
+</li>
+<li><b>IOC</b> (FPSC[0]) (Invalid Operation cumulative exception flag)<ul>
+<li>=1 Exception occurred.</li>
+<li>=0 Value has to be set explicitly.</li>
+<li>Flag is not cleared automatically.</li>
+</ul>
+</li>
+</ul>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">fpscr</td><td>FPSCR value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only for Cortex-M4.</li>
+<li>The variable <b>__FPU_PRESENT</b> has to be set to 1.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">__get_FPSCR</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0bf9564ebc1613a8faba014275dac2a4"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_MSP" ref="ga0bf9564ebc1613a8faba014275dac2a4" args="(uint32_t topOfMainStack)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_MSP </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>topOfMainStack</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Main Status Pointer (MSP) value using the instruction <b>MSR</b>. <br/>
+<br/>
+ Physically two different stack pointers (SP) exist:</p>
+<ul>
+<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li>
+<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li>
+</ul>
+<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p>
+<ul>
+<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li>
+<li>=1 PSP is the current stack pointer. The initial value is undefined.</li>
+</ul>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">topOfMainStack</td><td>MSP value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only one of the two SPs is visible at a time.</li>
+<li>For many applications, the system can completely rely on the MSP.</li>
+<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a>; <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743" title="Set the PSP register.">__set_PSP</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga70b4e1a6c1c86eb913fb9d6e8400156f"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_PRIMASK" ref="ga70b4e1a6c1c86eb913fb9d6e8400156f" args="(uint32_t priMask)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_PRIMASK </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>priMask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Priority Mask register (PRIMASK) value using the instruction <b>MSR</b>. <br/>
+<br/>
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">priMask</td><td>Priority Mask<ul>
+<li>=0 no effect</li>
+<li>=1 prevents the activation of all exceptions with configurable priority</li>
+</ul>
+</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.</li>
+<li>When set and a fault occurs, the hard fault handler will be executed.</li>
+<li>Useful for temprorarily disabling all interrupts for timing critical tasks.</li>
+<li>Does not have the ability to mask BusFault or bypass MPU.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>; <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0 variants].">__set_FAULTMASK</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga48e5853f417e17a8a65080f6a605b743"></a><!-- doxytag: member="Ref_CoreReg.txt::__set_PSP" ref="ga48e5853f417e17a8a65080f6a605b743" args="(uint32_t topOfProcStack)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __set_PSP </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>topOfProcStack</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the Program Status Pointer (PSP) value using the instruction <b>MSR</b>. <br/>
+<br/>
+ Physically two different stack pointers (SP) exist:</p>
+<ul>
+<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li>
+<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li>
+</ul>
+<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p>
+<ul>
+<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li>
+<li>=1 PSP is the current stack pointer. The initial value is undefined.</li>
+</ul>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">topOfProcStack</td><td>PSP value to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Only one of the two SPs is visible at a time.</li>
+<li>For many applications, the system can completely rely on the MSP.</li>
+<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a>; <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4" title="Set the MSP register.">__set_MSP</a>; <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register.">__set_CONTROL</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
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+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
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+  <div class="summary">
+<a href="#enum-members">Enumerations</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Interrupts and Exceptions (NVIC)</div>  </div>
+</div>
+<div class="contents">
+
+<p>Describes programming of interrupts and exception functions.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> =  -14, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a> =  -13, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> =  -12, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> =  -11, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> =  -10, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> =  -5, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> =  -4, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> =  -2, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> =  -1, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">WWDG_STM_IRQn</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">PVD_STM_IRQn</a> =  1
+<br/>
+ }</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Definition of IRQn numbers.  <a href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">More...</a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a> (uint32_t PriorityGroup)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set priority grouping [not for Cortex-M0 variants].  <a href="#gad78f447e891789b4d8f2e5b21eeda354"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the priority grouping [not for Cortex-M0 variants].  <a href="#gaa81b19849367d3cdb95ac108c500fa78"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable an external interrupt.  <a href="#ga530ad9fda2ed1c8b70e439ecfe80591f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable an external interrupt.  <a href="#ga736ba13a76eb37ef6e2c253be8b0331c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the pending interrupt.  <a href="#ga95a8329a680b051ecf3ee8f516acc662"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set an interrupt to pending.  <a href="#ga3b885147ef9965ecede49614de8df9d2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear an interrupt from pending.  <a href="#ga382ad6bedd6eecfdabd1b94dd128a01a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt active status [not for Cortex-M0 variants].  <a href="#gadf4252e600661fd762cfc0d1a9f5b892"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the priority for an interrupt.  <a href="#ga5bb7f43ad92937c039dee3d36c3c2798"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> (<a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the priority of an interrupt.  <a href="#gab18fb9f6c5f4c70fdd73047f0f7c8395"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Encodes Priority [not for Cortex-M0 variants].  <a href="#ga0688c59605b119c53c71b2505ab23eb5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Decode the interrupt priority [not for Cortex-M0 variants].  <a href="#gad3cbca1be7a4726afa9448a9acd89377"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset the system.  <a href="#ga1b47d17e90b6a03e7bd1ec6a0d549b46"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>ARM provides a template file <b>startup_<em>device</em></b> for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a <b><em>weak</em></b> function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.</p>
+<p>The table below describes the core exception names and their availability in various Cortex-M cores.</p>
+<table  class="cmtable" summary="Core Exception Name">
+<tr>
+<th>Core Exception Name </th><th>IRQn Value </th><th>M0 </th><th>M0p </th><th>M3 </th><th>M4 </th><th>SC000 </th><th>SC300 </th><th>Description  </th></tr>
+<tr>
+<td><b>NonMaskableInt_IRQn</b> </td><td>-14 </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Non Maskable Interrupt  </td></tr>
+<tr>
+<td><b>HardFault_IRQn</b> </td><td>-13 </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Hard Fault Interrupt  </td></tr>
+<tr>
+<td><b>MemoryManagement_IRQn</b> </td><td>-12 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Memory Management Interrupt  </td></tr>
+<tr>
+<td><b>BusFault_IRQn</b> </td><td>-11 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Bus Fault Interrupt  </td></tr>
+<tr>
+<td><b>UsageFault_IRQn</b> </td><td>-10 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Usage Fault Interrupt  </td></tr>
+<tr>
+<td><b>SVCall_IRQn</b> </td><td>-5 </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>SV Call Interrupt   </td></tr>
+<tr>
+<td><b>DebugMonitor_IRQn</b> </td><td>-4 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>&#160; </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Debug Monitor Interrupt  </td></tr>
+<tr>
+<td><b>PendSV_IRQn</b> </td><td>-2 </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>Pend SV Interrupt  </td></tr>
+<tr>
+<td><b>SysTick_IRQn</b> </td><td>-1 </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td><div class="image">
+<img src="check.png" alt="check.png" alt="available"/>
+</div>
+ </td><td>System Tick Interrupt  </td></tr>
+</table>
+<h2><a class="anchor" id="cmsis_vectortable_M0_sec"></a>
+For Cortex-M0 and Cortex-M0+</h2>
+<p>The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:</p>
+<div class="fragment"><pre class="fragment">__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+</pre></div><h2><a class="anchor" id="cmsis_vectortable_M3_sec"></a>
+For Cortex-M3</h2>
+<p>The following exception names are fixed and define the start of the vector table for a Cortex-M3:</p>
+<div class="fragment"><pre class="fragment">__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+</pre></div><h2><a class="anchor" id="cmsis_vectortable_ex_sec"></a>
+Example</h2>
+<p>The following is an examples for device-specific interrupts:</p>
+<div class="fragment"><pre class="fragment">; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+</pre></div><p>Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.</p>
+<div class="fragment"><pre class="fragment">Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+</pre></div><p>The user application may simply define an interrupt handler function by using the handler name as shown below.</p>
+<div class="fragment"><pre class="fragment"><span class="keywordtype">void</span> WWDG_IRQHandler(<span class="keywordtype">void</span>)
+{
+  ...
+}
+</pre></div><h2><a class="anchor" id="cmsis_vectortable_code_ex1_sec"></a>
+Code Example 1</h2>
+<p>The code below shows the usage of the CMSIS NVIC functions <a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354" title="Set priority grouping [not for Cortex-M0 variants].">NVIC_SetPriorityGrouping()</a>, <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0 variants].">NVIC_GetPriorityGrouping()</a>, <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority()</a>, <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt.">NVIC_GetPriority()</a>, <a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5" title="Encodes Priority [not for Cortex-M0 variants].">NVIC_EncodePriority()</a>, and <a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377" title="Decode the interrupt priority [not for Cortex-M0 variants].">NVIC_DecodePriority()</a> with an LPC1700.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span>
+
+uint32_t priorityGroup;                                     <span class="comment">/* Variables to store priority group and priority */</span>
+uint32_t priority;
+uint32_t preemptPriority;
+uint32_t subPriority;
+
+
+<span class="keywordtype">int</span> main (<span class="keywordtype">void</span>)  {
+
+  <a class="code" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354" title="Set priority grouping [not for Cortex-M0 variants].">NVIC_SetPriorityGrouping</a>(5);                              <span class="comment">/* Set priority group to 5:</span>
+<span class="comment">                                                               Bit[7..6] preempt priority Bits, </span>
+<span class="comment">                                                               Bit[5..3] subpriority Bits </span>
+<span class="comment">                                                               (valid for five priority bits) */</span>
+     
+  priorityGroup =  <a class="code" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0 variants].">NVIC_GetPriorityGrouping</a>();              <span class="comment">/* Get used priority grouping */</span>
+
+  priority = <a class="code" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5" title="Encodes Priority [not for Cortex-M0 variants].">NVIC_EncodePriority</a>(priorityGroup, 1, 6);      <span class="comment">/* Encode priority with 6 for subpriority and 1 for preempt priority</span>
+<span class="comment">                                                               Note: priority depends on the used priority grouping */</span>
+                                                               
+  <a class="code" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority</a>(UART0_IRQn, priority);                   <span class="comment">/* Set new priority */</span>
+
+  priority =  <a class="code" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt.">NVIC_GetPriority</a>(UART0_IRQn);                 <span class="comment">/* Retrieve priority again */</span>    
+
+  <a class="code" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377" title="Decode the interrupt priority [not for Cortex-M0 variants].">NVIC_DecodePriority</a>(priority, priorityGroup, &amp;preemptPriority, &amp;subPriority);
+
+  <span class="keywordflow">while</span>(1);
+}
+</pre></div><h2><a class="anchor" id="cmsis_vectortable_code_ex2_sec"></a>
+Code Example 2</h2>
+<p>The code below shows the usage of the CMSIS NVIC functions <a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" title="Enable an external interrupt.">NVIC_EnableIRQ()</a>, <a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892" title="Get the interrupt active status [not for Cortex-M0 variants].">NVIC_GetActive()</a> with an LPC1700.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span>
+
+uint32_t active;                                            <span class="comment">/* Variable to store interrupt active state */</span>
+
+
+<span class="keywordtype">void</span> TIMER0_IRQHandler(<span class="keywordtype">void</span>)  {                             <span class="comment">/* Timer 0 interrupt handler  */</span>
+
+  <span class="keywordflow">if</span> (LPC_TIM0-&gt;IR &amp; (1 &lt;&lt; 0))  {                           <span class="comment">/* Check if interrupt for match channel 0 occured */</span> 
+    LPC_TIM0-&gt;IR |= (1 &lt;&lt; 0);                               <span class="comment">/* Acknowledge interrupt for match channel 0 occured */</span>
+  }
+  active = <a class="code" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892" title="Get the interrupt active status [not for Cortex-M0 variants].">NVIC_GetActive</a>(TIMER0_IRQn);                     <span class="comment">/* Get interrupt active state of timer 0 */</span>
+}
+
+
+<span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {
+                                                            <span class="comment">/* Set match channel register MR0 to 1 millisecond */</span>
+  LPC_TIM0-&gt;MR0 = (((<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000) / 4) - 1);     <span class="comment">/* 1 ms? */</span>
+  
+  LPC_TIM0-&gt;MCR = (3 &lt;&lt; 0);                                 <span class="comment">/* Enable interrupt and reset for match channel MR0 */</span>
+
+  <a class="code" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" title="Enable an external interrupt.">NVIC_EnableIRQ</a>(TIMER0_IRQn);                              <span class="comment">/* Enable NVIC interrupt for timer 0 */</span>
+  
+  LPC_TIM0-&gt;TCR = (1 &lt;&lt; 0);                                 <span class="comment">/* Enable timer 0 */</span>
+
+  <span class="keywordflow">while</span>(1);
+}
+</pre></div> <hr/><h2>Enumeration Type Documentation</h2>
+<a class="anchor" id="ga7e1129cd8a196f4284d41db3e82ad5c8"></a><!-- doxytag: member="Ref_NVIC.txt::IRQn_Type" ref="ga7e1129cd8a196f4284d41db3e82ad5c8" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">enum <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The core exception enumeration names for IRQn values are defined in the file <b>device.h</b>.</p>
+<p>Negative IRQn values represent processor core exceptions (internal interrupts). Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.</p>
+<p>The table below describes the core exception names and their availability in various Cortex-M cores. </p>
+<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"></a><!-- doxytag: member="NonMaskableInt_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30" args="" -->NonMaskableInt_IRQn</em>&nbsp;</td><td>
+<p>Exception 2: Non Maskable Interrupt. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85"></a><!-- doxytag: member="HardFault_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85" args="" -->HardFault_IRQn</em>&nbsp;</td><td>
+<p>Exception 3: Hard Fault Interrupt. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa"></a><!-- doxytag: member="MemoryManagement_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa" args="" -->MemoryManagement_IRQn</em>&nbsp;</td><td>
+<p>Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af"></a><!-- doxytag: member="BusFault_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af" args="" -->BusFault_IRQn</em>&nbsp;</td><td>
+<p>Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf"></a><!-- doxytag: member="UsageFault_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf" args="" -->UsageFault_IRQn</em>&nbsp;</td><td>
+<p>Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"></a><!-- doxytag: member="SVCall_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237" args="" -->SVCall_IRQn</em>&nbsp;</td><td>
+<p>Exception 11: SV Call Interrupt. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c"></a><!-- doxytag: member="DebugMonitor_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c" args="" -->DebugMonitor_IRQn</em>&nbsp;</td><td>
+<p>Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"></a><!-- doxytag: member="PendSV_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2" args="" -->PendSV_IRQn</em>&nbsp;</td><td>
+<p>Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"></a><!-- doxytag: member="SysTick_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7" args="" -->SysTick_IRQn</em>&nbsp;</td><td>
+<p>Exception 15: System Tick Interrupt. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2"></a><!-- doxytag: member="WWDG_STM_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2" args="" -->WWDG_STM_IRQn</em>&nbsp;</td><td>
+<p>Device Interrupt 0: Window WatchDog Interrupt. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86"></a><!-- doxytag: member="PVD_STM_IRQn" ref="gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86" args="" -->PVD_STM_IRQn</em>&nbsp;</td><td>
+<p>Device Interrupt 1: PVD through EXTI Line detection Interrupt. </p>
+</td></tr>
+</table>
+</dd>
+</dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga382ad6bedd6eecfdabd1b94dd128a01a"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_ClearPendingIRQ" ref="ga382ad6bedd6eecfdabd1b94dd128a01a" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_ClearPendingIRQ </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function removes the pending state of the specified interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative number.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
+<li>An interrupt can have the status pending though it is not active.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662" title="Get the pending interrupt.">NVIC_GetPendingIRQ</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad3cbca1be7a4726afa9448a9acd89377"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_DecodePriority" ref="gad3cbca1be7a4726afa9448a9acd89377" args="(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_DecodePriority </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>Priority</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>PriorityGroup</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t *&#160;</td>
+          <td class="paramname"><em>pPreemptPriority</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t *&#160;</td>
+          <td class="paramname"><em>pSubPriority</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function decodes an interrupt priority value with the priority group <em>PriorityGroup</em> to preemptive priority value <em>pPreemptPriority</em> and subpriority value <em>pSubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">Priority</td><td>Priority </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr>
+    <tr><td class="paramdir">[out]</td><td class="paramname">*pPreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr>
+    <tr><td class="paramdir">[out]</td><td class="paramname">*pSubPriority</td><td>Subpriority value (starting from 0)</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a>; <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt.">NVIC_GetPriority</a>; <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0 variants].">NVIC_GetPriorityGrouping</a>;</li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga736ba13a76eb37ef6e2c253be8b0331c"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_DisableIRQ" ref="ga736ba13a76eb37ef6e2c253be8b0331c" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_DisableIRQ </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function disables the specified device-specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Number of the external interrupt to disable</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga530ad9fda2ed1c8b70e439ecfe80591f"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_EnableIRQ" ref="ga530ad9fda2ed1c8b70e439ecfe80591f" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_EnableIRQ </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function enables the specified device-specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li>
+<li>The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: <br/>
+ ICTR[4:0]<ul>
+<li>=0 - 32 interrupts supported</li>
+<li>=1 - 64 interrupts supported</li>
+<li>...</li>
+</ul>
+</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a>; <a class="el" href="struct_s_cn_s_c_b___type.html" title="Structure type to access the System Control and ID Register not in the SCB.">SCnSCB_Type</a>;</li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0688c59605b119c53c71b2505ab23eb5"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_EncodePriority" ref="ga0688c59605b119c53c71b2505ab23eb5" args="(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t NVIC_EncodePriority </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>PriorityGroup</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>PreemptPriority</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>SubPriority</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function encodes the priority for an interrupt with the priority group <em>PriorityGroup</em>, preemptive priority value <em>PreemptPriority</em>, and subpriority value <em>SubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">PreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">SubPriority</td><td>Subpriority value (starting from 0)</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Encoded priority for the interrupt</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a>; <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority</a>;</li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadf4252e600661fd762cfc0d1a9f5b892"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_GetActive" ref="gadf4252e600661fd762cfc0d1a9f5b892" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t NVIC_GetActive </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt <em>IRQn</em>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
+<li>=0 Interrupt is not active</li>
+<li>=1 Interrupt is active, or active and pending</li>
+</ul>
+</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.</li>
+<li>When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga95a8329a680b051ecf3ee8f516acc662"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_GetPendingIRQ" ref="ga95a8329a680b051ecf3ee8f516acc662" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t NVIC_GetPendingIRQ </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function returns the pending status of the specified interrupt <em>IRQn</em>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd><ul>
+<li>=0 Interrupt is not pending</li>
+<li>=1 Interrupt is pending</li>
+</ul>
+</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear an interrupt from pending.">NVIC_ClearPendingIRQ</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab18fb9f6c5f4c70fdd73047f0f7c8395"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_GetPriority" ref="gab18fb9f6c5f4c70fdd73047f0f7c8395" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t NVIC_GetPriority </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reads the priority for the specified interrupt <em>IRQn</em>. <em>IRQn</em> can can specify any device-specific (external) interrupt, or core (internal) interrupt.</p>
+<p>The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Interrupt priority</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>Each external interrupt has an associated priority-level register.</li>
+<li>Unimplemented bits are read as zero.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a>; <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0 variants].">NVIC_GetPriorityGrouping</a>; <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0 variants].">__get_BASEPRI</a>;</li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa81b19849367d3cdb95ac108c500fa78"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_GetPriorityGrouping" ref="gaa81b19849367d3cdb95ac108c500fa78" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t NVIC_GetPriorityGrouping </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).</p>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Priority grouping field</dd></dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>By default, priority group setting is zero.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a>; <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt.">NVIC_GetPriority</a>; <a class="el" href="struct_s_c_b___type.html" title="Structure type to access the System Control Block (SCB).">SCB_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga3b885147ef9965ecede49614de8df9d2"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_SetPendingIRQ" ref="ga3b885147ef9965ecede49614de8df9d2" args="(IRQn_Type IRQn)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_SetPendingIRQ </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function sets the pending bit for the specified interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a>; <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear an interrupt from pending.">NVIC_ClearPendingIRQ</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5bb7f43ad92937c039dee3d36c3c2798"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_SetPriority" ref="ga5bb7f43ad92937c039dee3d36c3c2798" args="(IRQn_Type IRQn, uint32_t priority)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_SetPriority </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
+          <td class="paramname"><em>IRQn</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>priority</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Sets the priority for the interrupt specified by <em>IRQn</em>.<em>IRQn</em> can can specify any device-specific (external) interrupt, or core (internal) interrupt. The <em>priority</em> specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.</p>
+<p>The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt Number </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority to set</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write <em>0xFF</em> to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is <em>0xE0</em>.</li>
+<li>Writes to unimplemented bits are ignored.</li>
+<li><b>For Cortex-M0</b>:<ul>
+<li>Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.</li>
+<li>Supports 0 to 192 priority levels.</li>
+<li>Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.</li>
+</ul>
+</li>
+<li><b>For Cortex-M3 and Cortex-M4</b>:<ul>
+<li>Dynamic switching of interrupt priority levels is supported.</li>
+<li>Supports 0 to 255 priority levels.</li>
+<li>Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.</li>
+</ul>
+</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a>; <a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354" title="Set priority grouping [not for Cortex-M0 variants].">NVIC_SetPriorityGrouping</a>; <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0 variants].">__set_BASEPRI</a>;</li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad78f447e891789b4d8f2e5b21eeda354"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_SetPriorityGrouping" ref="gad78f447e891789b4d8f2e5b21eeda354" args="(uint32_t PriorityGroup)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_SetPriorityGrouping </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>PriorityGroup</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The function sets the priority grouping <em>PriorityGroup</em> using the required unlock sequence. <em>PriorityGroup</em> is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>not for Cortex-M0 variants.</li>
+<li>By default, priority group setting is zero.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a>; <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority</a>; <a class="el" href="struct_s_c_b___type.html" title="Structure type to access the System Control Block (SCB).">SCB_Type</a></li>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1b47d17e90b6a03e7bd1ec6a0d549b46"></a><!-- doxytag: member="Ref_NVIC.txt::NVIC_SystemReset" ref="ga1b47d17e90b6a03e7bd1ec6a0d549b46" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void NVIC_SystemReset </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.</p>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd><ul>
+<li>In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.</li>
+</ul>
+</dd></dl>
+<dl class="see"><dt><b>See also:</b></dt><dd><ul>
+<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+</div>
+</div>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
new file mode 100644
index 0000000..0c55ae9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html
@@ -0,0 +1,196 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Systick Timer (SYSTICK)</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+var searchBox = new SearchBox("searchBox", "search",false,'Search');
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+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Systick Timer (SYSTICK)</div>  </div>
+</div>
+<div class="contents">
+
+<p>Initialize and start the SysTick timer.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> (uint32_t ticks)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">System Tick Timer Configuration.  <a href="#gabe47de40e9b0ad465b752297a9d9f427"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.</p>
+<h2><a class="anchor" id="SysTick_code_ex_sec"></a>
+Code Example</h2>
+<p>The code below shows the usage of the function <a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config()</a> with an LPC1700.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span>
+
+uint32_t msTicks = 0;                                       <span class="comment">/* Variable to store millisecond ticks */</span>
+
+                                            
+<span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>)  {                               <span class="comment">/* SysTick interrupt Handler.</span>
+<span class="comment">  msTicks++;                                                   See startup file startup_LPC17xx.s for SysTick vector */</span> 
+}
+
+
+<span class="keywordtype">int</span> main (<span class="keywordtype">void</span>)  {
+  uint32_t returnCode;
+
+  returnCode = <a class="code" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000);      <span class="comment">/* Configure SysTick to generate an interrupt every millisecond */</span>
+
+  <span class="keywordflow">if</span> (returnCode != 0)  {                                   <span class="comment">/* Check return code for errors */</span>
+    <span class="comment">// Error Handling </span>
+  }
+
+  <span class="keywordflow">while</span>(1);
+}
+</pre></div> <hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gabe47de40e9b0ad465b752297a9d9f427"></a><!-- doxytag: member="Ref_Systick.txt::SysTick_Config" ref="gabe47de40e9b0ad465b752297a9d9f427" args="(uint32_t ticks)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t SysTick_Config </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>ticks</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">ticks</td><td>Number of ticks between two interrupts</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>0 - success </dd>
+<dd>
+1 - failure</dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>When <b>#define __Vendor_SysTickConfig</b> is set to 1, the standard function <b>SysTick_Config</b> is excluded. In this case, the file <b><em>device</em>.h</b> must contain a vendor specific implementation of this function. </dd></dl>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
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+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Intrinsic Functions for CPU Instructions</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#gac71fad9f0a91980fecafcb450ee0a63e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gad3efec76c3bfa2b8528ded530386c563"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#ga3c34da7eb16496ae2668a5b95fa441e7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#ga93c09b4709394d81977300d5f84950e5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#gacb2a8ca6eae1ba4b31161578b720c199"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#gab1c9b393641dc2d397b3408fdbe72b96"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#ga4717abc17af5ba29b1e4c055e0a0d9b8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a> (uint32_t value)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gaeef6f853b6df3a365c838ee5b49a7a26"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">__REVSH</a> (int32_t value)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order in signed short value.  <a href="#ga1ec006e6d79063363cb0c2a2e0b3adbe"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value [not for Cortex-M0 variants].  <a href="#gad6f9f297f6b91a995ee199fbc796b863"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a> (uint32_t value, uint32_t shift)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate a value right by a number of bits.  <a href="#gaf66beb577bb9d90424c3d1d7f684c024"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a> (volatile uint8_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (8 bit) [not for Cortex-M0 variants].  <a href="#ga9e3ac13d8dcf4331176b624cf6234a7e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a> (volatile uint16_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (16 bit) [not for Cortex-M0 variants].  <a href="#ga9feffc093d6f68b120d592a7a0d45a15"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a> (volatile uint32_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (32 bit) [not for Cortex-M0 variants].  <a href="#gabd78840a0f2464905b7cec791ebc6a4c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a> (uint8_t value, volatile uint8_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (8 bit) [not for Cortex-M0 variants].  <a href="#gaab6482d1f59f59e2b6b7efc1af391c99"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a> (uint16_t value, volatile uint16_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (16 bit) [not for Cortex-M0 variants].  <a href="#ga0a354bdf71caa52f081a4a54e84c8d2a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> (uint32_t value, volatile uint32_t *addr)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (32 bit) [not for Cortex-M0 variants].  <a href="#ga335deaaa7991490e1450cb7d1e4c5197"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Remove the exclusive lock [not for Cortex-M0 variants].  <a href="#ga354c5ac8870cc3dfb823367af9c4b412"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">__SSAT</a> (unint32_t value, uint32_t sat)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Signed Saturate [not for Cortex-M0 variants].  <a href="#ga7d9dddda18805abbf51ac21c639845e1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">__USAT</a> (uint32_t value, uint32_t sat)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsigned Saturate [not for Cortex-M0 variants].  <a href="#ga76bbe4374a5912362866cdc1ded4064a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros [not for Cortex-M0 variants].  <a href="#ga90884c591ac5d73d6069334eba9d6c02"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. </p>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga354c5ac8870cc3dfb823367af9c4b412"></a><!-- doxytag: member="Ref_cmInstr.txt::__CLREX" ref="ga354c5ac8870cc3dfb823367af9c4b412" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __CLREX </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants]. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga90884c591ac5d73d6069334eba9d6c02"></a><!-- doxytag: member="Ref_cmInstr.txt::__CLZ" ref="ga90884c591ac5d73d6069334eba9d6c02" args="(uint32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t __CLZ </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>number of leading zeros in value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab1c9b393641dc2d397b3408fdbe72b96"></a><!-- doxytag: member="Ref_cmInstr.txt::__DMB" ref="gab1c9b393641dc2d397b3408fdbe72b96" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DMB </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>
+
+</div>
+</div>
+<a class="anchor" id="gacb2a8ca6eae1ba4b31161578b720c199"></a><!-- doxytag: member="Ref_cmInstr.txt::__DSB" ref="gacb2a8ca6eae1ba4b31161578b720c199" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __DSB </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga93c09b4709394d81977300d5f84950e5"></a><!-- doxytag: member="Ref_cmInstr.txt::__ISB" ref="ga93c09b4709394d81977300d5f84950e5" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __ISB </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9e3ac13d8dcf4331176b624cf6234a7e"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXB" ref="ga9e3ac13d8dcf4331176b624cf6234a7e" args="(volatile uint8_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint8_t __LDREXB </td>
+          <td>(</td>
+          <td class="paramtype">volatile uint8_t *&#160;</td>
+          <td class="paramname"><em>addr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint8_t at (*addr) </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9feffc093d6f68b120d592a7a0d45a15"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXH" ref="ga9feffc093d6f68b120d592a7a0d45a15" args="(volatile uint16_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint16_t __LDREXH </td>
+          <td>(</td>
+          <td class="paramtype">volatile uint16_t *&#160;</td>
+          <td class="paramname"><em>addr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint16_t at (*addr) </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gabd78840a0f2464905b7cec791ebc6a4c"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXW" ref="gabd78840a0f2464905b7cec791ebc6a4c" args="(volatile uint32_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __LDREXW </td>
+          <td>(</td>
+          <td class="paramtype">volatile uint32_t *&#160;</td>
+          <td class="paramname"><em>addr</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint32_t at (*addr) </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac71fad9f0a91980fecafcb450ee0a63e"></a><!-- doxytag: member="Ref_cmInstr.txt::__NOP" ref="gac71fad9f0a91980fecafcb450ee0a63e" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __NOP </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function does nothing. This instruction can be used for code alignment purposes. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad6f9f297f6b91a995ee199fbc796b863"></a><!-- doxytag: member="Ref_cmInstr.txt::__RBIT" ref="gad6f9f297f6b91a995ee199fbc796b863" args="(uint32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __RBIT </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reverses the bit order of the given value [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga4717abc17af5ba29b1e4c055e0a0d9b8"></a><!-- doxytag: member="Ref_cmInstr.txt::__REV" ref="ga4717abc17af5ba29b1e4c055e0a0d9b8" args="(uint32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __REV </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reverses the byte order in integer value.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaeef6f853b6df3a365c838ee5b49a7a26"></a><!-- doxytag: member="Ref_cmInstr.txt::__REV16" ref="gaeef6f853b6df3a365c838ee5b49a7a26" args="(uint32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __REV16 </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reverses the byte order in two unsigned short values.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1ec006e6d79063363cb0c2a2e0b3adbe"></a><!-- doxytag: member="Ref_cmInstr.txt::__REVSH" ref="ga1ec006e6d79063363cb0c2a2e0b3adbe" args="(int32_t value)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t __REVSH </td>
+          <td>(</td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>value</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function reverses the byte order in a signed short value with sign extension to integer.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf66beb577bb9d90424c3d1d7f684c024"></a><!-- doxytag: member="Ref_cmInstr.txt::__ROR" ref="gaf66beb577bb9d90424c3d1d7f684c024" args="(uint32_t value, uint32_t shift)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __ROR </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>shift</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function rotates a value right by a specified number of bits.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be shifted right </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">shift</td><td>Number of bits in the range [1..31] </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Rotated value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga3c34da7eb16496ae2668a5b95fa441e7"></a><!-- doxytag: member="Ref_cmInstr.txt::__SEV" ref="ga3c34da7eb16496ae2668a5b95fa441e7" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __SEV </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7d9dddda18805abbf51ac21c639845e1"></a><!-- doxytag: member="Ref_cmInstr.txt::__SSAT" ref="ga7d9dddda18805abbf51ac21c639845e1" args="(unint32_t value, uint32_t sat)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __SSAT </td>
+          <td>(</td>
+          <td class="paramtype">unint32_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>sat</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function saturates a signed value [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [1..32] </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Saturated value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaab6482d1f59f59e2b6b7efc1af391c99"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXB" ref="gaab6482d1f59f59e2b6b7efc1af391c99" args="(uint8_t value, volatile uint8_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __STREXB </td>
+          <td>(</td>
+          <td class="paramtype">uint8_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">volatile uint8_t *&#160;</td>
+          <td class="paramname"><em>addr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
+<dd>
+1 Function failed </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0a354bdf71caa52f081a4a54e84c8d2a"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXH" ref="ga0a354bdf71caa52f081a4a54e84c8d2a" args="(uint16_t value, volatile uint16_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __STREXH </td>
+          <td>(</td>
+          <td class="paramtype">uint16_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">volatile uint16_t *&#160;</td>
+          <td class="paramname"><em>addr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
+<dd>
+1 Function failed </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga335deaaa7991490e1450cb7d1e4c5197"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXW" ref="ga335deaaa7991490e1450cb7d1e4c5197" args="(uint32_t value, volatile uint32_t *addr)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __STREXW </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">volatile uint32_t *&#160;</td>
+          <td class="paramname"><em>addr</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
+<dd>
+1 Function failed </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga76bbe4374a5912362866cdc1ded4064a"></a><!-- doxytag: member="Ref_cmInstr.txt::__USAT" ref="ga76bbe4374a5912362866cdc1ded4064a" args="(uint32_t value, uint32_t sat)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __USAT </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>value</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>sat</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>This function saturates an unsigned value [not for Cortex-M0 variants].</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [0..31] </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>Saturated value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad3efec76c3bfa2b8528ded530386c563"></a><!-- doxytag: member="Ref_cmInstr.txt::__WFE" ref="gad3efec76c3bfa2b8528ded530386c563" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __WFE </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p>
+<ul>
+<li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul>
+<li>An exception, unless masked by the exception mask registers or the current priority level.</li>
+<li>An exception enters the Pending state, if SEVONPEND in the System Control Register is set.</li>
+<li>A Debug Entry request, if Debug is enabled.</li>
+<li>An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.</li>
+</ul>
+</li>
+</ul>
+<ul>
+<li>If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a><!-- doxytag: member="Ref_cmInstr.txt::__WFI" ref="gaed91dfbf3d7d7b7fba8d912fcbeaad88" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void __WFI </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p>
+<ul>
+<li>A non-masked interrupt occurs and is taken.</li>
+<li>An interrupt masked by PRIMASK becomes pending.</li>
+<li>A Debug Entry request. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
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+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+   </ul>
+ </div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html
new file mode 100644
index 0000000..c2fa9b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html
@@ -0,0 +1,228 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>System and Clock Configuration</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
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+<!-- Generated by Doxygen 1.7.5.1 -->
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+<a href="#var-members">Variables</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">System and Clock Configuration</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="var-members"></a>
+Variables</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Variable to hold the system core clock value.  <a href="#gaa3cd3e43291e81e795d642b79b6088e6"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Function to Initialize the system.  <a href="#ga93f514700ccf00d08dbdcff7f1224eb2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Function to update the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>.  <a href="#gae0c36a9591fe6e9c45ecb21a794f0f0f"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>ARM provides a template file <b>system_<em>device</em>.c</b> that must be adapted by the silicon vendor to match their actual device. As a <b>minimum requirement</b>, this file must provide:</p>
+<ul>
+<li>A device-specific system configuration function, <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit()</a>.</li>
+<li>A global variable that contains the system frequency, <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>.</li>
+</ul>
+<p>The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.</p>
+<h2><a class="anchor" id="system_init_code_ex_sec"></a>
+Code Example</h2>
+<p>The code below shows the usage of the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and the functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> and <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock.">SystemCoreClockUpdate()</a> with an LPC1700.</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;LPC17xx.h&quot;</span>
+
+uint32_t coreClock_1 = 0;                       <span class="comment">/* Variables to store core clock values */</span>
+uint32_t coreClock_2 = 0;
+
+
+<span class="keywordtype">int</span> main (<span class="keywordtype">void</span>)  {
+
+  coreClock_1 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a>;                <span class="comment">/* Store value of predefined SystemCoreClock */</span>
+
+  <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock.">SystemCoreClockUpdate</a>();                      <span class="comment">/* Update SystemCoreClock according to register settings */</span>
+
+  coreClock_2 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a>;                <span class="comment">/* Store value of calculated SystemCoreClock */</span>
+
+  <span class="keywordflow">if</span> (coreClock_2 != coreClock_1)  {            <span class="comment">/* Without changing the clock setting both core clock values should be the same */</span> 
+    <span class="comment">// Error Handling</span>
+  }
+
+  <span class="keywordflow">while</span>(1);
+}
+</pre></div> <hr/><h2>Variable Documentation</h2>
+<a class="anchor" id="gaa3cd3e43291e81e795d642b79b6088e6"></a><!-- doxytag: member="Ref_SystemAndClock.txt::SystemCoreClock" ref="gaa3cd3e43291e81e795d642b79b6088e6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.</p>
+<dl class="attention"><dt><b>Attention:</b></dt><dd>Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gae0c36a9591fe6e9c45ecb21a794f0f0f"></a><!-- doxytag: member="Ref_SystemAndClock.txt::SystemCoreClockUpdate" ref="gae0c36a9591fe6e9c45ecb21a794f0f0f" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void SystemCoreClockUpdate </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga93f514700ccf00d08dbdcff7f1224eb2"></a><!-- doxytag: member="Ref_SystemAndClock.txt::SystemInit" ref="ga93f514700ccf00d08dbdcff7f1224eb2" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void SystemInit </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. SystemInit is called from the file <b>startup<em>_device</em></b>. </p>
+
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/index.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/index.html
new file mode 100644
index 0000000..0b4beec
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/index.html
@@ -0,0 +1,205 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+  <div class="headertitle">
+<div class="title">Overview </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
+<ul>
+<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
+<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
+<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
+<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
+<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
+<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
+</ul>
+<hr/>
+<p>This chapter provides details about the CMSIS-CORE and contains the following sections:</p>
+<ul>
+<li><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
+<li><a class="el" href="_templates_pg.html">Template Files</a> describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices.</li>
+<li><a class="el" href="_c_o_r_e__m_i_s_r_a__exceptions_pg.html">MISRA-C:2004 Compliance Exceptions</a> describes the violations to the MISRA standard.</li>
+<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
+</ul>
+<hr/>
+<h2><a class="anchor" id="ref_man_sec"></a>
+Cortex-M Reference Manuals</h2>
+<p>The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.</p>
+<ul>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a></li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a></li>
+<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a></li>
+</ul>
+<hr/>
+<h2><a class="anchor" id="tested_tools_sec"></a>
+Tested and Verified Toolchains</h2>
+<p>The CMSIS-CORE <a class="el" href="_templates_pg.html">Template Files</a> supplied by ARM have been tested and verified with the following toolchains:</p>
+<ul>
+<li>ARM: MDK-ARM Version 4.13a (or greater)</li>
+<li>GNU: GCC ARM Embedded 2011-q4-major (or greater)</li>
+<li>GNU: Sourcery G++ Lite Edition for ARM 2010.09-51 (or greater)</li>
+<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater)</li>
+</ul>
+<hr/>
+<p>Revision History of CMSIS-CORE</p>
+<table  class="cmtable" summary="Core Exception Name">
+<tr>
+<th>Version </th><th>Description  </th></tr>
+<tr>
+<td>V3.01 </td><td>Added support for Cortex-M0+ processor. <br/>
+ Integration of CMSIS DSP Library version 1.1.0 <br/>
+   </td></tr>
+<tr>
+<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/>
+ Added function <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/>
+ Added <a class="el" href="_reg_map_pg.html">Register Mapping</a> for TPIU, DWT. <br/>
+ Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/>
+ Corrected <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/>
+ Corrected the functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/>
+ Documentation restructured.   </td></tr>
+<tr>
+<td>V2.10 </td><td>Updated documentation.<br/>
+ Updated CMSIS core include files.<br/>
+ Changed CMSIS/Device folder structure.<br/>
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/>
+ Reworked CMSIS DSP library examples.   </td></tr>
+<tr>
+<td>V2.00 </td><td>Added support for Cortex-M4 processor.  </td></tr>
+<tr>
+<td>V1.30 </td><td>Reworked Startup Concept.<br/>
+ Added additional Debug Functionality.<br/>
+ Changed folder structure.<br/>
+ Added doxygen comments.<br/>
+ Added definitions for bit.   </td></tr>
+<tr>
+<td>V1.01 </td><td>Added support for Cortex-M0 processor.  </td></tr>
+<tr>
+<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a>  </td></tr>
+<tr>
+<td>V1.00 </td><td>Initial Release for Cortex-M3 processor.  </td></tr>
+</table>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
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+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/jquery.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/jquery.js
new file mode 100644
index 0000000..c052173
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return 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+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m<n.length;m++){if(j.options[n[m][0]]){n[m][1].apply(j.element,k)}}}},contains:function(k,j){return document.compareDocumentPosition?k.compareDocumentPosition(j)&16:k!==j&&k.contains(j)},hasScroll:function(m,k){if(c(m).css("overflow")=="hidden"){return false}var j=(k&&k=="left")?"scrollLeft":"scrollTop",l=false;if(m[j]>0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f<k.length;f++){var h=c.trim(k[f]),d="ui-resizable-"+h;var g=c('<div class="ui-resizable-handle '+d+'"></div>');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var m={width:(l.size.width-j),height:(l.size.height-e)},i=(parseInt(l.element.css("left"),10)+(l.position.left-l.originalPosition.left))||null,k=(parseInt(l.element.css("top"),10)+(l.position.top-l.originalPosition.top))||null;if(!h.animate){this.element.css(c.extend(m,{top:k,left:i}))}l.helper.height(l.size.height);l.helper.width(l.size.width);if(this._helper&&!h.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",g);if(this._helper){this.helper.remove()}return false},_updateCache:function(d){var e=this.options;this.offset=this.helper.offset();if(a(d.left)){this.position.left=d.left}if(a(d.top)){this.position.top=d.top}if(a(d.height)){this.size.height=d.height}if(a(d.width)){this.size.width=d.width}},_updateRatio:function(g,f){var h=this.options,i=this.position,e=this.size,d=this.axis;if(g.height){g.width=(e.height*this.aspectRatio)}else{if(g.width){g.height=(e.width/this.aspectRatio)}}if(d=="sw"){g.left=i.left+(e.width-g.width);g.top=null}if(d=="nw"){g.top=i.top+(e.height-g.height);g.left=i.left+(e.width-g.width)}return g},_respectSize:function(k,f){var i=this.helper,h=this.options,q=this._aspectRatio||f.shiftKey,p=this.axis,s=a(k.width)&&h.maxWidth&&(h.maxWidth<k.width),l=a(k.height)&&h.maxHeight&&(h.maxHeight<k.height),g=a(k.width)&&h.minWidth&&(h.minWidth>k.width),r=a(k.height)&&h.minHeight&&(h.minHeight>k.height);if(g){k.width=h.minWidth}if(r){k.height=h.minHeight}if(s){k.width=h.maxWidth}if(l){k.height=h.maxHeight}var e=this.originalPosition.left+this.originalSize.width,n=this.position.top+this.size.height;var j=/sw|nw|w/.test(p),d=/nw|ne|n/.test(p);if(g&&j){k.left=e-h.minWidth}if(s&&j){k.left=e-h.maxWidth}if(r&&d){k.top=n-h.minHeight}if(l&&d){k.top=n-h.maxHeight}var m=!k.width&&!k.height;if(m&&!k.left&&k.top){k.top=null}else{if(m&&!k.top&&k.left){k.left=null}}return k},_proportionallyResize:function(){var j=this.options;if(!this._proportionallyResizeElements.length){return}var f=this.helper||this.element;for(var e=0;e<this._proportionallyResizeElements.length;e++){var g=this._proportionallyResizeElements[e];if(!this.borderDif){var d=[g.css("borderTopWidth"),g.css("borderRightWidth"),g.css("borderBottomWidth"),g.css("borderLeftWidth")],h=[g.css("paddingTop"),g.css("paddingRight"),g.css("paddingBottom"),g.css("paddingLeft")];this.borderDif=c.map(d,function(k,m){var l=parseInt(k,10)||0,n=parseInt(h[m],10)||0;return l+n})}if(c.browser.msie&&!(!(c(f).is(":hidden")||c(f).parents(":hidden").length))){continue}g.css({height:(f.height()-this.borderDif[0]-this.borderDif[2])||0,width:(f.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var e=this.element,h=this.options;this.elementOffset=e.offset();if(this._helper){this.helper=this.helper||c('<div style="overflow:hidden;"></div>');var d=c.browser.msie&&c.browser.version<7,f=(d?1:0),g=(d?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+g,height:this.element.outerHeight()+g,position:"absolute",left:this.elementOffset.left-f+"px",top:this.elementOffset.top-f+"px",zIndex:++h.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(f,e,d){return{width:this.originalSize.width+e}},w:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{left:h.left+e,width:f.width-e}},n:function(g,e,d){var i=this.options,f=this.originalSize,h=this.originalPosition;return{top:h.top+d,height:f.height-d}},s:function(f,e,d){return{height:this.originalSize.height+d}},se:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},sw:function(f,e,d){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[f,e,d]))},ne:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[f,e,d]))},nw:function(f,e,d){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[f,e,d]))}},_propagate:function(e,d){c.ui.plugin.call(this,e,[d,this.ui()]);(e!="resize"&&this._trigger(e,d,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}));c.extend(c.ui.resizable,{version:"1.7.2",eventPrefix:"resize",defaults:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,cancel:":input,option",containment:false,delay:0,distance:1,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000}});c.ui.plugin.add("resizable","alsoResize",{start:function(e,f){var d=c(this).data("resizable"),g=d.options;_store=function(h){c(h).each(function(){c(this).data("resizable-alsoresize",{width:parseInt(c(this).width(),10),height:parseInt(c(this).height(),10),left:parseInt(c(this).css("left"),10),top:parseInt(c(this).css("top"),10)})})};if(typeof(g.alsoResize)=="object"&&!g.alsoResize.parentNode){if(g.alsoResize.length){g.alsoResize=g.alsoResize[0];_store(g.alsoResize)}else{c.each(g.alsoResize,function(h,i){_store(h)})}}else{_store(g.alsoResize)}},resize:function(f,h){var e=c(this).data("resizable"),i=e.options,g=e.originalSize,k=e.originalPosition;var j={height:(e.size.height-g.height)||0,width:(e.size.width-g.width)||0,top:(e.position.top-k.top)||0,left:(e.position.left-k.left)||0},d=function(l,m){c(l).each(function(){var p=c(this),q=c(this).data("resizable-alsoresize"),o={},n=m&&m.length?m:["width","height","top","left"];c.each(n||["width","height","top","left"],function(r,t){var s=(q[t]||0)+(j[t]||0);if(s&&s>=0){o[t]=s||null}});if(/relative/.test(p.css("position"))&&c.browser.opera){e._revertToRelativePosition=true;p.css({position:"absolute",top:"auto",left:"auto"})}p.css(o)})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.nodeType){c.each(i.alsoResize,function(l,m){d(l,m)})}else{d(i.alsoResize)}},stop:function(e,f){var d=c(this).data("resizable");if(d._revertToRelativePosition&&c.browser.opera){d._revertToRelativePosition=false;el.css({position:"relative"})}c(this).removeData("resizable-alsoresize-start")}});c.ui.plugin.add("resizable","animate",{stop:function(h,m){var n=c(this).data("resizable"),i=n.options;var g=n._proportionallyResizeElements,d=g.length&&(/textarea/i).test(g[0].nodeName),e=d&&c.ui.hasScroll(g[0],"left")?0:n.sizeDiff.height,k=d?0:n.sizeDiff.width;var f={width:(n.size.width-k),height:(n.size.height-e)},j=(parseInt(n.element.css("left"),10)+(n.position.left-n.originalPosition.left))||null,l=(parseInt(n.element.css("top"),10)+(n.position.top-n.originalPosition.top))||null;n.element.animate(c.extend(f,l&&j?{top:l,left:j}:{}),{duration:i.animateDuration,easing:i.animateEasing,step:function(){var o={width:parseInt(n.element.css("width"),10),height:parseInt(n.element.css("height"),10),top:parseInt(n.element.css("top"),10),left:parseInt(n.element.css("left"),10)};if(g&&g.length){c(g[0]).css({width:o.width,height:o.height})}n._updateCache(o);n._propagate("resize",h)}})}});c.ui.plugin.add("resizable","containment",{start:function(e,q){var s=c(this).data("resizable"),i=s.options,k=s.element;var f=i.containment,j=(f instanceof c)?f.get(0):(/parent/.test(f))?k.parent().get(0):f;if(!j){return}s.containerElement=c(j);if(/document/.test(f)||f==document){s.containerOffset={left:0,top:0};s.containerPosition={left:0,top:0};s.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var m=c(j),h=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){h[p]=b(m.css("padding"+o))});s.containerOffset=m.offset();s.containerPosition=m.position();s.containerSize={height:(m.innerHeight()-h[3]),width:(m.innerWidth()-h[1])};var n=s.containerOffset,d=s.containerSize.height,l=s.containerSize.width,g=(c.ui.hasScroll(j,"left")?j.scrollWidth:l),r=(c.ui.hasScroll(j)?j.scrollHeight:d);s.parentData={element:j,left:n.left,top:n.top,width:g,height:r}}},resize:function(f,p){var s=c(this).data("resizable"),h=s.options,e=s.containerSize,n=s.containerOffset,l=s.size,m=s.position,q=s._aspectRatio||f.shiftKey,d={top:0,left:0},g=s.containerElement;if(g[0]!=document&&(/static/).test(g.css("position"))){d=n}if(m.left<(s._helper?n.left:0)){s.size.width=s.size.width+(s._helper?(s.position.left-n.left):(s.position.left-d.left));if(q){s.size.height=s.size.width/h.aspectRatio}s.position.left=h.helper?n.left:0}if(m.top<(s._helper?n.top:0))
+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/modules.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/modules.html
new file mode 100644
index 0000000..62f1bce
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/modules.html
@@ -0,0 +1,140 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
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+<div class="textblock">Here is a list of all modules:</div><ul>
+<li><a class="el" href="group__peripheral__gr.html">Peripheral Access</a></li>
+<li><a class="el" href="group__system__init__gr.html">System and Clock Configuration</a></li>
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+<li><a class="el" href="group___sys_tick__gr.html">Systick Timer (SYSTICK)</a></li>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+      [ "System and Clock Configuration", "group__system__init__gr.html", null ],
+      [ "Interrupts and Exceptions (NVIC)", "group___n_v_i_c__gr.html", null ],
+      [ "Core Register Access", "group___core___register__gr.html", null ],
+      [ "Intrinsic Functions for CPU Instructions", "group__intrinsic___c_p_u__gr.html", null ],
+      [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4]", "group__intrinsic___s_i_m_d__gr.html", null ],
+      [ "Systick Timer (SYSTICK)", "group___sys_tick__gr.html", null ],
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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+  
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+  
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+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('pages.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Usage and Description</div>  </div>
+</div>
+<div class="contents">
+<div class="textblock">Here is a list of all related documentation pages:</div><ul>
+<li><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a>
+</li>
+<li><a class="el" href="_templates_pg.html">Template Files</a>
+</li>
+<li><a class="el" href="_c_o_r_e__m_i_s_r_a__exceptions_pg.html">MISRA-C:2004 Compliance Exceptions</a>
+</li>
+<li><a class="el" href="_reg_map_pg.html">Register Mapping</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search.css
new file mode 100644
index 0000000..1746d13
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_61.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_61.html
new file mode 100644
index 0000000..e4f1a97
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_61.html
@@ -0,0 +1,55 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_acpr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab" target="_parent">ACPR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_actlr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d" target="_parent">ACTLR</a>
+  <span class="SRScope">SCnSCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_adr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2" target="_parent">ADR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_afsr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef" target="_parent">AFSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_aircr">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d" target="_parent">AIRCR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_apsr_5ftype">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../union_a_p_s_r___type.html" target="_parent">APSR_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_62.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_62.html
new file mode 100644
index 0000000..aa9d4dc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_62.html
@@ -0,0 +1,43 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_b">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_b')">b</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14" target="_parent">APSR_Type::b()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50" target="_parent">IPSR_Type::b()</a>
+    <a id="Item0_c2" onkeydown="return searchResults.NavChild(event,0,2)" onkeypress="return searchResults.NavChild(event,0,2)" onkeyup="return searchResults.NavChild(event,0,2)" class="SRScope" href="../unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70" target="_parent">xPSR_Type::b()</a>
+    <a id="Item0_c3" onkeydown="return searchResults.NavChild(event,0,3)" onkeypress="return searchResults.NavChild(event,0,3)" onkeyup="return searchResults.NavChild(event,0,3)" class="SRScope" href="../union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9" target="_parent">CONTROL_Type::b()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_bfar">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a" target="_parent">BFAR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_busfault_5firqn">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af" target="_parent">BusFault_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_64.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_64.html
new file mode 100644
index 0000000..7f145c7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_64.html
@@ -0,0 +1,79 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_dcrdr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9" target="_parent">DCRDR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dcrsr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983" target="_parent">DCRSR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_debugmonitor_5firqn">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c" target="_parent">DebugMonitor_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_demcr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d" target="_parent">DEMCR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_devid">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d" target="_parent">DEVID</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_devtype">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35" target="_parent">DEVTYPE</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dfr">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86" target="_parent">DFR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dfsr">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d" target="_parent">DFSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dhcsr">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d" target="_parent">DHCSR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dwt_5ftype">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_d_w_t___type.html" target="_parent">DWT_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_65.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_65.html
new file mode 100644
index 0000000..b3db09d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_65.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_exccnt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82" target="_parent">EXCCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_66.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_66.html
new file mode 100644
index 0000000..74554be
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_66.html
@@ -0,0 +1,109 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_ffcr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880" target="_parent">FFCR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ffsr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd" target="_parent">FFSR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fifo0">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10" target="_parent">FIFO0</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fifo1">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e" target="_parent">FIFO1</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_foldcnt">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab" target="_parent">FOLDCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpca">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd" target="_parent">FPCA</a>
+  <span class="SRScope">CONTROL_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpcar">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b" target="_parent">FPCAR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpccr">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8" target="_parent">FPCCR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpdscr">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6" target="_parent">FPDSCR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpu_5ftype">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_f_p_u___type.html" target="_parent">FPU_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_fscr">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef" target="_parent">FSCR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function0">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729" target="_parent">FUNCTION0</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function1">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747" target="_parent">FUNCTION1</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function2">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b" target="_parent">FUNCTION2</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function3">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890" target="_parent">FUNCTION3</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_69.html
new file mode 100644
index 0000000..704a08c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_69.html
@@ -0,0 +1,147 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_iabr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11" target="_parent">IABR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icer">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5" target="_parent">ICER</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icpr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5" target="_parent">ICPR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icsr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a" target="_parent">ICSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ictr">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98" target="_parent">ICTR</a>
+  <span class="SRScope">SCnSCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ip">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c" target="_parent">IP</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ipsr_5ftype">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../union_i_p_s_r___type.html" target="_parent">IPSR_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_irqn_5ftype">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8" target="_parent">IRQn_Type</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_isar">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f" target="_parent">ISAR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_iser">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f" target="_parent">ISER</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ispr">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90" target="_parent">ISPR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_isr">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_isr')">ISR</a>
+  <div class="SRChildren">
+    <a id="Item11_c0" onkeydown="return searchResults.NavChild(event,11,0)" onkeypress="return searchResults.NavChild(event,11,0)" onkeyup="return searchResults.NavChild(event,11,0)" class="SRScope" href="../union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5" target="_parent">IPSR_Type::ISR()</a>
+    <a id="Item11_c1" onkeydown="return searchResults.NavChild(event,11,1)" onkeypress="return searchResults.NavChild(event,11,1)" onkeyup="return searchResults.NavChild(event,11,1)" class="SRScope" href="../unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970" target="_parent">xPSR_Type::ISR()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_it">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328" target="_parent">IT</a>
+  <span class="SRScope">xPSR_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itatbctr0">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0" target="_parent">ITATBCTR0</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itatbctr2">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d" target="_parent">ITATBCTR2</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itctrl">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198" target="_parent">ITCTRL</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5fcheckchar">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535" target="_parent">ITM_CheckChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5freceivechar">
+ <div class="SREntry">
+  <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c" target="_parent">ITM_ReceiveChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5frxbuffer">
+ <div class="SREntry">
+  <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8" target="_parent">ITM_RxBuffer</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5fsendchar">
+ <div class="SREntry">
+  <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1" target="_parent">ITM_SendChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5ftype">
+ <div class="SREntry">
+  <a id="Item20" onkeydown="return searchResults.Nav(event,20)" onkeypress="return searchResults.Nav(event,20)" onkeyup="return searchResults.Nav(event,20)" class="SRSymbol" href="../struct_i_t_m___type.html" target="_parent">ITM_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html
new file mode 100644
index 0000000..337c839
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6c.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_load">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f" target="_parent">LOAD</a>
+  <span class="SRScope">SysTick_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_lsucnt">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35" target="_parent">LSUCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html
new file mode 100644
index 0000000..540c1dd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_6d.html
@@ -0,0 +1,84 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_mask0">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f" target="_parent">MASK0</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mask1">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef" target="_parent">MASK1</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mask2">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e" target="_parent">MASK2</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mask3">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba" target="_parent">MASK3</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_memorymanagement_5firqn">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa" target="_parent">MemoryManagement_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_misra_2etxt">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../_m_i_s_r_a_8txt.html" target="_parent">MISRA.txt</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_mmfar">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd" target="_parent">MMFAR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mmfr">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976" target="_parent">MMFR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mpu_5ftype">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_m_p_u___type.html" target="_parent">MPU_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_mvfr0">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1" target="_parent">MVFR0</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_mvfr1">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d" target="_parent">MVFR1</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_70.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_70.html
new file mode 100644
index 0000000..90cb2f2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_70.html
@@ -0,0 +1,50 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_pcsr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5" target="_parent">PCSR</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pendsv_5firqn">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2" target="_parent">PendSV_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pfr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7" target="_parent">PFR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_port">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46" target="_parent">PORT</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pvd_5fstm_5firqn">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86" target="_parent">PVD_STM_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_71.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_71.html
new file mode 100644
index 0000000..0c1e07b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_71.html
@@ -0,0 +1,29 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_q">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_q')">Q</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de" target="_parent">APSR_Type::Q()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c" target="_parent">xPSR_Type::Q()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_74.html
new file mode 100644
index 0000000..47364a0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_74.html
@@ -0,0 +1,66 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_t">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658" target="_parent">T</a>
+  <span class="SRScope">xPSR_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_tcr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45" target="_parent">TCR</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_template_2etxt">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../_template_8txt.html" target="_parent">Template.txt</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ter">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589" target="_parent">TER</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_tpi_5ftype">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html" target="_parent">TPI_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_tpr">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa" target="_parent">TPR</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_trigger">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe" target="_parent">TRIGGER</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_type">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7" target="_parent">TYPE</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_75.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_75.html
new file mode 100644
index 0000000..67c5a01
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_75.html
@@ -0,0 +1,49 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_u16">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4" target="_parent">u16</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_u32">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df" target="_parent">u32</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_u8">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433" target="_parent">u8</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_usagefault_5firqn">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf" target="_parent">UsageFault_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_using_2etxt">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../_using_8txt.html" target="_parent">Using.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_76.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_76.html
new file mode 100644
index 0000000..4d6ec2c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/all_76.html
@@ -0,0 +1,41 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_v">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_v')">V</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e" target="_parent">APSR_Type::V()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a" target="_parent">xPSR_Type::V()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_val">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4" target="_parent">VAL</a>
+  <span class="SRScope">SysTick_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_vtor">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f" target="_parent">VTOR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_61.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_61.html
new file mode 100644
index 0000000..1f2ce6b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_61.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_apsr_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../union_a_p_s_r___type.html" target="_parent">APSR_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_63.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_63.html
new file mode 100644
index 0000000..6f38777
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_63.html
@@ -0,0 +1,30 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_control_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../union_c_o_n_t_r_o_l___type.html" target="_parent">CONTROL_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_coredebug_5ftype">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_core_debug___type.html" target="_parent">CoreDebug_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_66.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_66.html
new file mode 100644
index 0000000..b7d4603
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_66.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_fpu_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_f_p_u___type.html" target="_parent">FPU_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_69.html
new file mode 100644
index 0000000..52ad50f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_69.html
@@ -0,0 +1,30 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_ipsr_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../union_i_p_s_r___type.html" target="_parent">IPSR_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5ftype">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_i_t_m___type.html" target="_parent">ITM_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6d.html
new file mode 100644
index 0000000..bf46580
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6d.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_mpu_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_m_p_u___type.html" target="_parent">MPU_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6e.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6e.html
new file mode 100644
index 0000000..3065a7a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_6e.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_nvic_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_n_v_i_c___type.html" target="_parent">NVIC_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_73.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_73.html
new file mode 100644
index 0000000..39c24f7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_73.html
@@ -0,0 +1,35 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_scb_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_s_c_b___type.html" target="_parent">SCB_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_scnscb_5ftype">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_cn_s_c_b___type.html" target="_parent">SCnSCB_Type</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_systick_5ftype">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_sys_tick___type.html" target="_parent">SysTick_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_74.html
new file mode 100644
index 0000000..e88762b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_74.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_tpi_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_t_p_i___type.html" target="_parent">TPI_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_78.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_78.html
new file mode 100644
index 0000000..b0a0751
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/classes_78.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_xpsr_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../unionx_p_s_r___type.html" target="_parent">xPSR_Type</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/close.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/close.png
new file mode 100644
index 0000000..9342d3d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/close.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enums_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enums_69.html
new file mode 100644
index 0000000..e7e2f67
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enums_69.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_irqn_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8" target="_parent">IRQn_Type</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_62.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_62.html
new file mode 100644
index 0000000..356e936
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_62.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_busfault_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af" target="_parent">BusFault_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_68.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_68.html
new file mode 100644
index 0000000..34bd281
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_68.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_hardfault_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85" target="_parent">HardFault_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6d.html
new file mode 100644
index 0000000..5332353
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6d.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_memorymanagement_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa" target="_parent">MemoryManagement_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6e.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6e.html
new file mode 100644
index 0000000..db14a2d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_6e.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_nonmaskableint_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30" target="_parent">NonMaskableInt_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_70.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_70.html
new file mode 100644
index 0000000..77dc556
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_70.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_pendsv_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2" target="_parent">PendSV_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pvd_5fstm_5firqn">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86" target="_parent">PVD_STM_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html
new file mode 100644
index 0000000..8c4b0e1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/enumvalues_75.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_usagefault_5firqn">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf" target="_parent">UsageFault_IRQn</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6d.html
new file mode 100644
index 0000000..8ecfaa0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6d.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_misra_2etxt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../_m_i_s_r_a_8txt.html" target="_parent">MISRA.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6f.html
new file mode 100644
index 0000000..e8d54e7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_6f.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_overview_2etxt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../_overview_8txt.html" target="_parent">Overview.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_74.html
new file mode 100644
index 0000000..be1c1f1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_74.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_template_2etxt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../_template_8txt.html" target="_parent">Template.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_75.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_75.html
new file mode 100644
index 0000000..0fcb29d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/files_75.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_using_2etxt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../_using_8txt.html" target="_parent">Using.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html
new file mode 100644
index 0000000..b4c96cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_5f.html
@@ -0,0 +1,644 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR__5f_5fclrex">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412" target="_parent">__CLREX</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fclz">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02" target="_parent">__CLZ</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fdisable_5ffault_5firq">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939" target="_parent">__disable_fault_irq</a>
+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fdisable_5firq">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013" target="_parent">__disable_irq</a>
+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fdmb">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96" target="_parent">__DMB</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fdsb">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199" target="_parent">__DSB</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fenable_5ffault_5firq">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_CoreReg.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fget_5fmsp">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fget_5fprimask">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02" target="_parent">__get_PRIMASK</a>
+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fget_5fpsp">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9" target="_parent">__get_PSP</a>
+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fget_5fxpsr">
+ <div class="SREntry">
+  <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd" target="_parent">__get_xPSR</a>
+  <span class="SRScope">Ref_CoreReg.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fisb">
+ <div class="SREntry">
+  <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5" target="_parent">__ISB</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fldrexb">
+ <div class="SREntry">
+  <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e" target="_parent">__LDREXB</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fldrexh">
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+<div class="SRResult" id="SR__5f_5fldrexw">
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fpkhbt">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+<div class="SRResult" id="SR__5f_5fpkhtb">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+<div class="SRResult" id="SR__5f_5fqadd16">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fqadd8">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fqasx">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fqsax">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fqsub">
+ <div class="SREntry">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+</div>
+<div class="SRResult" id="SR__5f_5fqsub16">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+<div class="SRResult" id="SR__5f_5fqsub8">
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+<div class="SRResult" id="SR__5f_5frbit">
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+<div class="SRResult" id="SR__5f_5frev">
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+  <span class="SRScope">Ref_cmInstr.txt</span>
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+  <span class="SRScope">Ref_cm4_simd.txt</span>
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+<div class="SRResult" id="SR__5f_5fset_5fbasepri">
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+<div class="SRResult" id="SR__5f_5fset_5fcontrol">
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+  <span class="SRScope">Ref_CoreReg.txt</span>
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+<div class="SRResult" id="SR__5f_5fset_5ffaultmask">
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+<div class="SRResult" id="SR__5f_5fset_5ffpscr">
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+<div class="SRResult" id="SR__5f_5fset_5fmsp">
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+<div class="SRResult" id="SR__5f_5fset_5fprimask">
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+<div class="SRResult" id="SR__5f_5fusax">
+ <div class="SREntry">
+  <a id="Item97" onkeydown="return searchResults.Nav(event,97)" onkeypress="return searchResults.Nav(event,97)" onkeyup="return searchResults.Nav(event,97)" class="SRSymbol" href="../group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e" target="_parent">__USAX</a>
+  <span class="SRScope">Ref_cm4_simd.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fusub16">
+ <div class="SREntry">
+  <a id="Item98" onkeydown="return searchResults.Nav(event,98)" onkeypress="return searchResults.Nav(event,98)" onkeyup="return searchResults.Nav(event,98)" class="SRSymbol" href="../group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e" target="_parent">__USUB16</a>
+  <span class="SRScope">Ref_cm4_simd.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fusub8">
+ <div class="SREntry">
+  <a id="Item99" onkeydown="return searchResults.Nav(event,99)" onkeypress="return searchResults.Nav(event,99)" onkeyup="return searchResults.Nav(event,99)" class="SRSymbol" href="../group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8" target="_parent">__USUB8</a>
+  <span class="SRScope">Ref_cm4_simd.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fuxtab16">
+ <div class="SREntry">
+  <a id="Item100" onkeydown="return searchResults.Nav(event,100)" onkeypress="return searchResults.Nav(event,100)" onkeyup="return searchResults.Nav(event,100)" class="SRSymbol" href="../group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09" target="_parent">__UXTAB16</a>
+  <span class="SRScope">Ref_cm4_simd.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fuxtb16">
+ <div class="SREntry">
+  <a id="Item101" onkeydown="return searchResults.Nav(event,101)" onkeypress="return searchResults.Nav(event,101)" onkeyup="return searchResults.Nav(event,101)" class="SRSymbol" href="../group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228" target="_parent">__UXTB16</a>
+  <span class="SRScope">Ref_cm4_simd.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fwfe">
+ <div class="SREntry">
+  <a id="Item102" onkeydown="return searchResults.Nav(event,102)" onkeypress="return searchResults.Nav(event,102)" onkeyup="return searchResults.Nav(event,102)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563" target="_parent">__WFE</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR__5f_5fwfi">
+ <div class="SREntry">
+  <a id="Item103" onkeydown="return searchResults.Nav(event,103)" onkeypress="return searchResults.Nav(event,103)" onkeyup="return searchResults.Nav(event,103)" class="SRSymbol" href="../group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88" target="_parent">__WFI</a>
+  <span class="SRScope">Ref_cmInstr.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html
new file mode 100644
index 0000000..073a792
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_69.html
@@ -0,0 +1,38 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_itm_5fcheckchar">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535" target="_parent">ITM_CheckChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5freceivechar">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c" target="_parent">ITM_ReceiveChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5fsendchar">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1" target="_parent">ITM_SendChar</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html
new file mode 100644
index 0000000..f85ddec
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_6e.html
@@ -0,0 +1,98 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_nvic_5fclearpendingirq">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" target="_parent">NVIC_ClearPendingIRQ</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fdecodepriority">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377" target="_parent">NVIC_DecodePriority</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fdisableirq">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" target="_parent">NVIC_DisableIRQ</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fenableirq">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" target="_parent">NVIC_EnableIRQ</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fencodepriority">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5" target="_parent">NVIC_EncodePriority</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fgetactive">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892" target="_parent">NVIC_GetActive</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fgetpendingirq">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662" target="_parent">NVIC_GetPendingIRQ</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fgetpriority">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" target="_parent">NVIC_GetPriority</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fgetprioritygrouping">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78" target="_parent">NVIC_GetPriorityGrouping</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fsetpendingirq">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2" target="_parent">NVIC_SetPendingIRQ</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fsetpriority">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" target="_parent">NVIC_SetPriority</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fsetprioritygrouping">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354" target="_parent">NVIC_SetPriorityGrouping</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_nvic_5fsystemreset">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46" target="_parent">NVIC_SystemReset</a>
+  <span class="SRScope">Ref_NVIC.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html
new file mode 100644
index 0000000..add7be0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/functions_73.html
@@ -0,0 +1,38 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_systemcoreclockupdate">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" target="_parent">SystemCoreClockUpdate</a>
+  <span class="SRScope">Ref_SystemAndClock.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_systeminit">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" target="_parent">SystemInit</a>
+  <span class="SRScope">Ref_SystemAndClock.txt</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_systick_5fconfig">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" target="_parent">SysTick_Config</a>
+  <span class="SRScope">Ref_Systick.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/mag_sel.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/mag_sel.png
new file mode 100644
index 0000000..81f6040
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/mag_sel.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html
new file mode 100644
index 0000000..b1ded27
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/nomatches.html
@@ -0,0 +1,12 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="NoMatches">No Matches</div>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.css
new file mode 100644
index 0000000..1746d13
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.js
new file mode 100644
index 0000000..6b45bd0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search.js
@@ -0,0 +1,738 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "enums",
+  6: "enumvalues"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i<search.length;i++)
+  {
+    var c = search.charAt(i);
+    var cn = c.charCodeAt(0);
+    if (c.match(/[a-z0-9]/))
+    {
+      result+=c;
+    }
+    else if (cn<16) 
+    {
+      result+="_0"+cn.toString(16);
+    }
+    else 
+    {
+      result+="_"+cn.toString(16);
+    }
+  }
+  return result;
+}
+
+function getXPos(item)
+{
+  var x = 0;
+  if (item.offsetWidth)
+  {
+    while (item && item!=document.body)
+    {
+      x   += item.offsetLeft;
+      item = item.offsetParent;
+    }
+  }
+  return x;
+}
+
+function getYPos(item)
+{
+  var y = 0;
+  if (item.offsetWidth)
+  {
+     while (item && item!=document.body)
+     {
+       y   += item.offsetTop;
+       item = item.offsetParent;
+     }
+  }
+  return y;
+}
+
+/* A class handling everything associated with the search panel.
+
+   Parameters:
+   name - The name of the global variable that will be 
+          storing this instance.  Is needed to be able to set timeouts.
+   resultPath - path to use for external files
+*/
+function SearchBox(name, resultsPath, inFrame, label)
+{
+  if (!name || !resultsPath) {  alert("Missing parameters to SearchBox."); }
+   
+  // ---------- Instance variables
+  this.name                  = name;
+  this.resultsPath           = resultsPath;
+  this.keyTimeout            = 0;
+  this.keyTimeoutLength      = 500;
+  this.closeSelectionTimeout = 300;
+  this.lastSearchValue       = "";
+  this.lastResultsPage       = "";
+  this.hideTimeout           = 0;
+  this.searchIndex           = 0;
+  this.searchActive          = false;
+  this.insideFrame           = inFrame;
+  this.searchLabel           = label;
+
+  // ----------- DOM Elements
+
+  this.DOMSearchField = function()
+  {  return document.getElementById("MSearchField");  }
+
+  this.DOMSearchSelect = function()
+  {  return document.getElementById("MSearchSelect");  }
+
+  this.DOMSearchSelectWindow = function()
+  {  return document.getElementById("MSearchSelectWindow");  }
+
+  this.DOMPopupSearchResults = function()
+  {  return document.getElementById("MSearchResults");  }
+
+  this.DOMPopupSearchResultsWindow = function()
+  {  return document.getElementById("MSearchResultsWindow");  }
+
+  this.DOMSearchClose = function()
+  {  return document.getElementById("MSearchClose"); }
+
+  this.DOMSearchBox = function()
+  {  return document.getElementById("MSearchBox");  }
+
+  // ------------ Event Handlers
+
+  // Called when focus is added or removed from the search field.
+  this.OnSearchFieldFocus = function(isActive)
+  {
+    this.Activate(isActive);
+  }
+
+  this.OnSearchSelectShow = function()
+  {
+    var searchSelectWindow = this.DOMSearchSelectWindow();
+    var searchField        = this.DOMSearchSelect();
+
+    if (this.insideFrame)
+    {
+      var left = getXPos(searchField);
+      var top  = getYPos(searchField);
+      left += searchField.offsetWidth + 6;
+      top += searchField.offsetHeight;
+
+      // show search selection popup
+      searchSelectWindow.style.display='block';
+      left -= searchSelectWindow.offsetWidth;
+      searchSelectWindow.style.left =  left + 'px';
+      searchSelectWindow.style.top  =  top  + 'px';
+    }
+    else
+    {
+      var left = getXPos(searchField);
+      var top  = getYPos(searchField);
+      top += searchField.offsetHeight;
+
+      // show search selection popup
+      searchSelectWindow.style.display='block';
+      searchSelectWindow.style.left =  left + 'px';
+      searchSelectWindow.style.top  =  top  + 'px';
+    }
+
+    // stop selection hide timer
+    if (this.hideTimeout) 
+    {
+      clearTimeout(this.hideTimeout);
+      this.hideTimeout=0;
+    }
+    return false; // to avoid "image drag" default event
+  }
+
+  this.OnSearchSelectHide = function()
+  {
+    this.hideTimeout = setTimeout(this.name +".CloseSelectionWindow()",
+                                  this.closeSelectionTimeout);
+  }
+
+  // Called when the content of the search field is changed.
+  this.OnSearchFieldChange = function(evt)
+  {
+    if (this.keyTimeout) // kill running timer
+    {
+      clearTimeout(this.keyTimeout);
+      this.keyTimeout = 0;
+    }
+
+    var e  = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 || e.keyCode==13)
+    {
+      if (e.shiftKey==1)
+      {
+        this.OnSearchSelectShow();
+        var win=this.DOMSearchSelectWindow(); 
+        for (i=0;i<win.childNodes.length;i++)
+        {
+          var child = win.childNodes[i]; // get span within a
+          if (child.className=='SelectItem')
+          {
+            child.focus();
+            return;
+          }
+        }
+        return;
+      }
+      else if (window.frames.MSearchResults.searchResults)
+      {
+        var elem = window.frames.MSearchResults.searchResults.NavNext(0);
+        if (elem) elem.focus();
+      }
+    }
+    else if (e.keyCode==27) // Escape out of the search field
+    {
+      this.DOMSearchField().blur();
+      this.DOMPopupSearchResultsWindow().style.display = 'none';
+      this.DOMSearchClose().style.display = 'none';
+      this.lastSearchValue = '';
+      this.Activate(false);
+      return;
+    }
+
+    // strip whitespaces
+    var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+
+    if (searchValue != this.lastSearchValue) // search value has changed
+    {
+      if (searchValue != "") // non-empty search
+      {
+        // set timer for search update
+        this.keyTimeout = setTimeout(this.name + '.Search()',
+                                     this.keyTimeoutLength);
+      }
+      else // empty search field
+      {
+        this.DOMPopupSearchResultsWindow().style.display = 'none';
+        this.DOMSearchClose().style.display = 'none';
+        this.lastSearchValue = '';
+      }
+    }
+  }
+
+  this.SelectItemCount = function(id)
+  {
+    var count=0;
+    var win=this.DOMSearchSelectWindow(); 
+    for (i=0;i<win.childNodes.length;i++)
+    {
+      var child = win.childNodes[i]; // get span within a
+      if (child.className=='SelectItem')
+      {
+        count++;
+      }
+    }
+    return count;
+  }
+
+  this.SelectItemSet = function(id)
+  {
+    var i,j=0;
+    var win=this.DOMSearchSelectWindow(); 
+    for (i=0;i<win.childNodes.length;i++)
+    {
+      var child = win.childNodes[i]; // get span within a
+      if (child.className=='SelectItem')
+      {
+        var node = child.firstChild;
+        if (j==id)
+        {
+          node.innerHTML='&#8226;';
+        }
+        else
+        {
+          node.innerHTML='&#160;';
+        }
+        j++;
+      }
+    }
+  }
+
+  // Called when an search filter selection is made.
+  // set item with index id as the active item
+  this.OnSelectItem = function(id)
+  {
+    this.searchIndex = id;
+    this.SelectItemSet(id);
+    var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+    if (searchValue!="" && this.searchActive) // something was found -> do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down
+    {
+      this.searchIndex++;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==38 && this.searchIndex>0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of <Search()>.
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_l.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_l.png
new file mode 100644
index 0000000..c872f4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_l.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_r.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_r.png
new file mode 100644
index 0000000..97ee8b4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/search_r.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html
new file mode 100644
index 0000000..45a0ac5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_61.html
@@ -0,0 +1,50 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_acpr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab" target="_parent">ACPR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_actlr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d" target="_parent">ACTLR</a>
+  <span class="SRScope">SCnSCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_adr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2" target="_parent">ADR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_afsr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef" target="_parent">AFSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_aircr">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d" target="_parent">AIRCR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html
new file mode 100644
index 0000000..5f65963
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_62.html
@@ -0,0 +1,37 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_b">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_b')">b</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14" target="_parent">APSR_Type::b()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50" target="_parent">IPSR_Type::b()</a>
+    <a id="Item0_c2" onkeydown="return searchResults.NavChild(event,0,2)" onkeypress="return searchResults.NavChild(event,0,2)" onkeyup="return searchResults.NavChild(event,0,2)" class="SRScope" href="../unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70" target="_parent">xPSR_Type::b()</a>
+    <a id="Item0_c3" onkeydown="return searchResults.NavChild(event,0,3)" onkeypress="return searchResults.NavChild(event,0,3)" onkeyup="return searchResults.NavChild(event,0,3)" class="SRScope" href="../union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9" target="_parent">CONTROL_Type::b()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_bfar">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a" target="_parent">BFAR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html
new file mode 100644
index 0000000..2a678b6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_64.html
@@ -0,0 +1,68 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_dcrdr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9" target="_parent">DCRDR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dcrsr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983" target="_parent">DCRSR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_demcr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d" target="_parent">DEMCR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_devid">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d" target="_parent">DEVID</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_devtype">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35" target="_parent">DEVTYPE</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dfr">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86" target="_parent">DFR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dfsr">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d" target="_parent">DFSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dhcsr">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d" target="_parent">DHCSR</a>
+  <span class="SRScope">CoreDebug_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html
new file mode 100644
index 0000000..b3db09d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_65.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_exccnt">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82" target="_parent">EXCCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html
new file mode 100644
index 0000000..709a9e9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_66.html
@@ -0,0 +1,104 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_ffcr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880" target="_parent">FFCR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ffsr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd" target="_parent">FFSR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fifo0">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10" target="_parent">FIFO0</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fifo1">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e" target="_parent">FIFO1</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_foldcnt">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab" target="_parent">FOLDCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpca">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd" target="_parent">FPCA</a>
+  <span class="SRScope">CONTROL_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpcar">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b" target="_parent">FPCAR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpccr">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8" target="_parent">FPCCR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fpdscr">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6" target="_parent">FPDSCR</a>
+  <span class="SRScope">FPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_fscr">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef" target="_parent">FSCR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function0">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729" target="_parent">FUNCTION0</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function1">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747" target="_parent">FUNCTION1</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function2">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b" target="_parent">FUNCTION2</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_function3">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890" target="_parent">FUNCTION3</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html
new file mode 100644
index 0000000..5b9971c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_68.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_hfsr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d" target="_parent">HFSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html
new file mode 100644
index 0000000..75edc19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_69.html
@@ -0,0 +1,113 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_iabr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11" target="_parent">IABR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icer">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5" target="_parent">ICER</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icpr">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5" target="_parent">ICPR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_icsr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a" target="_parent">ICSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ictr">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98" target="_parent">ICTR</a>
+  <span class="SRScope">SCnSCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ip">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c" target="_parent">IP</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_isar">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f" target="_parent">ISAR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_iser">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f" target="_parent">ISER</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ispr">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90" target="_parent">ISPR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_isr">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_isr')">ISR</a>
+  <div class="SRChildren">
+    <a id="Item9_c0" onkeydown="return searchResults.NavChild(event,9,0)" onkeypress="return searchResults.NavChild(event,9,0)" onkeyup="return searchResults.NavChild(event,9,0)" class="SRScope" href="../union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5" target="_parent">IPSR_Type::ISR()</a>
+    <a id="Item9_c1" onkeydown="return searchResults.NavChild(event,9,1)" onkeypress="return searchResults.NavChild(event,9,1)" onkeyup="return searchResults.NavChild(event,9,1)" class="SRScope" href="../unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970" target="_parent">xPSR_Type::ISR()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_it">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328" target="_parent">IT</a>
+  <span class="SRScope">xPSR_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itatbctr0">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0" target="_parent">ITATBCTR0</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itatbctr2">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d" target="_parent">ITATBCTR2</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itctrl">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198" target="_parent">ITCTRL</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_itm_5frxbuffer">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8" target="_parent">ITM_RxBuffer</a>
+  <span class="SRScope">Ref_Debug.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html
new file mode 100644
index 0000000..337c839
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_6c.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_load">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f" target="_parent">LOAD</a>
+  <span class="SRScope">SysTick_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_lsucnt">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35" target="_parent">LSUCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html
new file mode 100644
index 0000000..a017e22
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_70.html
@@ -0,0 +1,38 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_pcsr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5" target="_parent">PCSR</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pfr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7" target="_parent">PFR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_port">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46" target="_parent">PORT</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html
new file mode 100644
index 0000000..ea9fc46
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_72.html
@@ -0,0 +1,148 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_rasr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03" target="_parent">RASR</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rasr_5fa1">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185" target="_parent">RASR_A1</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rasr_5fa2">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014" target="_parent">RASR_A2</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rasr_5fa3">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d" target="_parent">RASR_A3</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rbar">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9" target="_parent">RBAR</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rbar_5fa1">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639" target="_parent">RBAR_A1</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rbar_5fa2">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395" target="_parent">RBAR_A2</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rbar_5fa3">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804" target="_parent">RBAR_A3</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved0">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved0')">RESERVED0</a>
+  <div class="SRChildren">
+    <a id="Item8_c0" onkeydown="return searchResults.NavChild(event,8,0)" onkeypress="return searchResults.NavChild(event,8,0)" onkeyup="return searchResults.NavChild(event,8,0)" class="SRScope" href="../struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80" target="_parent">NVIC_Type::RESERVED0()</a>
+    <a id="Item8_c1" onkeydown="return searchResults.NavChild(event,8,1)" onkeypress="return searchResults.NavChild(event,8,1)" onkeyup="return searchResults.NavChild(event,8,1)" class="SRScope" href="../struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6" target="_parent">SCB_Type::RESERVED0()</a>
+    <a id="Item8_c2" onkeydown="return searchResults.NavChild(event,8,2)" onkeypress="return searchResults.NavChild(event,8,2)" onkeyup="return searchResults.NavChild(event,8,2)" class="SRScope" href="../struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1" target="_parent">SCnSCB_Type::RESERVED0()</a>
+    <a id="Item8_c3" onkeydown="return searchResults.NavChild(event,8,3)" onkeypress="return searchResults.NavChild(event,8,3)" onkeyup="return searchResults.NavChild(event,8,3)" class="SRScope" href="../struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e" target="_parent">ITM_Type::RESERVED0()</a>
+    <a id="Item8_c4" onkeydown="return searchResults.NavChild(event,8,4)" onkeypress="return searchResults.NavChild(event,8,4)" onkeyup="return searchResults.NavChild(event,8,4)" class="SRScope" href="../struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36" target="_parent">FPU_Type::RESERVED0()</a>
+    <a id="Item8_c5" onkeydown="return searchResults.NavChild(event,8,5)" onkeypress="return searchResults.NavChild(event,8,5)" onkeyup="return searchResults.NavChild(event,8,5)" class="SRScope" href="../struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59" target="_parent">DWT_Type::RESERVED0()</a>
+    <a id="Item8_c6" onkeydown="return searchResults.NavChild(event,8,6)" onkeypress="return searchResults.NavChild(event,8,6)" onkeyup="return searchResults.NavChild(event,8,6)" class="SRScope" href="../struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9" target="_parent">TPI_Type::RESERVED0()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved1">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved1')">RESERVED1</a>
+  <div class="SRChildren">
+    <a id="Item9_c0" onkeydown="return searchResults.NavChild(event,9,0)" onkeypress="return searchResults.NavChild(event,9,0)" onkeyup="return searchResults.NavChild(event,9,0)" class="SRScope" href="../struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce" target="_parent">ITM_Type::RESERVED1()</a>
+    <a id="Item9_c1" onkeydown="return searchResults.NavChild(event,9,1)" onkeypress="return searchResults.NavChild(event,9,1)" onkeyup="return searchResults.NavChild(event,9,1)" class="SRScope" href="../struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4" target="_parent">DWT_Type::RESERVED1()</a>
+    <a id="Item9_c2" onkeydown="return searchResults.NavChild(event,9,2)" onkeypress="return searchResults.NavChild(event,9,2)" onkeyup="return searchResults.NavChild(event,9,2)" class="SRScope" href="../struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12" target="_parent">TPI_Type::RESERVED1()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved2">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved2')">RESERVED2</a>
+  <div class="SRChildren">
+    <a id="Item10_c0" onkeydown="return searchResults.NavChild(event,10,0)" onkeypress="return searchResults.NavChild(event,10,0)" onkeyup="return searchResults.NavChild(event,10,0)" class="SRScope" href="../struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72" target="_parent">NVIC_Type::RESERVED2()</a>
+    <a id="Item10_c1" onkeydown="return searchResults.NavChild(event,10,1)" onkeypress="return searchResults.NavChild(event,10,1)" onkeyup="return searchResults.NavChild(event,10,1)" class="SRScope" href="../struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b" target="_parent">ITM_Type::RESERVED2()</a>
+    <a id="Item10_c2" onkeydown="return searchResults.NavChild(event,10,2)" onkeypress="return searchResults.NavChild(event,10,2)" onkeyup="return searchResults.NavChild(event,10,2)" class="SRScope" href="../struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738" target="_parent">DWT_Type::RESERVED2()</a>
+    <a id="Item10_c3" onkeydown="return searchResults.NavChild(event,10,3)" onkeypress="return searchResults.NavChild(event,10,3)" onkeyup="return searchResults.NavChild(event,10,3)" class="SRScope" href="../struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096" target="_parent">TPI_Type::RESERVED2()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved3">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved3')">RESERVED3</a>
+  <div class="SRChildren">
+    <a id="Item11_c0" onkeydown="return searchResults.NavChild(event,11,0)" onkeypress="return searchResults.NavChild(event,11,0)" onkeyup="return searchResults.NavChild(event,11,0)" class="SRScope" href="../struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab" target="_parent">NVIC_Type::RESERVED3()</a>
+    <a id="Item11_c1" onkeydown="return searchResults.NavChild(event,11,1)" onkeypress="return searchResults.NavChild(event,11,1)" onkeyup="return searchResults.NavChild(event,11,1)" class="SRScope" href="../struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c" target="_parent">TPI_Type::RESERVED3()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved4">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved4')">RESERVED4</a>
+  <div class="SRChildren">
+    <a id="Item12_c0" onkeydown="return searchResults.NavChild(event,12,0)" onkeypress="return searchResults.NavChild(event,12,0)" onkeyup="return searchResults.NavChild(event,12,0)" class="SRScope" href="../struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790" target="_parent">NVIC_Type::RESERVED4()</a>
+    <a id="Item12_c1" onkeydown="return searchResults.NavChild(event,12,1)" onkeypress="return searchResults.NavChild(event,12,1)" onkeyup="return searchResults.NavChild(event,12,1)" class="SRScope" href="../struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46" target="_parent">TPI_Type::RESERVED4()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved5">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_reserved5')">RESERVED5</a>
+  <div class="SRChildren">
+    <a id="Item13_c0" onkeydown="return searchResults.NavChild(event,13,0)" onkeypress="return searchResults.NavChild(event,13,0)" onkeyup="return searchResults.NavChild(event,13,0)" class="SRScope" href="../struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8" target="_parent">NVIC_Type::RESERVED5()</a>
+    <a id="Item13_c1" onkeydown="return searchResults.NavChild(event,13,1)" onkeypress="return searchResults.NavChild(event,13,1)" onkeyup="return searchResults.NavChild(event,13,1)" class="SRScope" href="../struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30" target="_parent">TPI_Type::RESERVED5()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_reserved7">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550" target="_parent">RESERVED7</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rnr">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833" target="_parent">RNR</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_rserved1">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe" target="_parent">RSERVED1</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html
new file mode 100644
index 0000000..d4b45ae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_73.html
@@ -0,0 +1,74 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_scr">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16" target="_parent">SCR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_shcsr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f" target="_parent">SHCSR</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_shp">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4" target="_parent">SHP</a>
+  <span class="SRScope">SCB_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_sleepcnt">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d" target="_parent">SLEEPCNT</a>
+  <span class="SRScope">DWT_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_sppr">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e" target="_parent">SPPR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_spsel">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2" target="_parent">SPSEL</a>
+  <span class="SRScope">CONTROL_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_sspsr">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912" target="_parent">SSPSR</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_stir">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749" target="_parent">STIR</a>
+  <span class="SRScope">NVIC_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_systemcoreclock">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" target="_parent">SystemCoreClock</a>
+  <span class="SRScope">Ref_SystemAndClock.txt</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html
new file mode 100644
index 0000000..66d0dbb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_74.html
@@ -0,0 +1,56 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_t">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658" target="_parent">T</a>
+  <span class="SRScope">xPSR_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_tcr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45" target="_parent">TCR</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ter">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589" target="_parent">TER</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_tpr">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa" target="_parent">TPR</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_trigger">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe" target="_parent">TRIGGER</a>
+  <span class="SRScope">TPI_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_type">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7" target="_parent">TYPE</a>
+  <span class="SRScope">MPU_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html
new file mode 100644
index 0000000..dded075
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_75.html
@@ -0,0 +1,38 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_u16">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4" target="_parent">u16</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_u32">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df" target="_parent">u32</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_u8">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433" target="_parent">u8</a>
+  <span class="SRScope">ITM_Type</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html
new file mode 100644
index 0000000..fdc60a2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_77.html
@@ -0,0 +1,31 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_w">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_w')">w</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94" target="_parent">APSR_Type::w()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879" target="_parent">IPSR_Type::w()</a>
+    <a id="Item0_c2" onkeydown="return searchResults.NavChild(event,0,2)" onkeypress="return searchResults.NavChild(event,0,2)" onkeyup="return searchResults.NavChild(event,0,2)" class="SRScope" href="../unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2" target="_parent">xPSR_Type::w()</a>
+    <a id="Item0_c3" onkeydown="return searchResults.NavChild(event,0,3)" onkeypress="return searchResults.NavChild(event,0,3)" onkeyup="return searchResults.NavChild(event,0,3)" class="SRScope" href="../union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f" target="_parent">CONTROL_Type::w()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html
new file mode 100644
index 0000000..1c0da89
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/search/variables_7a.html
@@ -0,0 +1,29 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_z">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_z')">Z</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5" target="_parent">APSR_Type::Z()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562" target="_parent">xPSR_Type::Z()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html
new file mode 100644
index 0000000..e16b33c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html
@@ -0,0 +1,359 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Startup File startup_&lt;device&gt;.s</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
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+<script type="text/javascript" src="search/search.js"></script>
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+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
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+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
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+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
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+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
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+      <li><a href="modules.html"><span>Reference</span></a></li>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+    </div>
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
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+<script type="text/javascript">
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+  <div class="headertitle">
+<div class="title">Startup File startup_&lt;device&gt;.s </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The <a class="el" href="startup_s_pg.html">Startup File startup_&lt;device&gt;.s</a> contains:</p>
+<ul>
+<li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li>
+<li>The setup values for the Main Stack Pointer (MSP).</li>
+<li>Exception vectors of the Cortex-M Processor with weak functions that implement default routines.</li>
+<li>Interrupt vectors that are device specific with weak functions that implement default routines.</li>
+</ul>
+<p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p>
+<p>To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are &lt;interrupt_name&gt;_IRQHandler. This table needs to be consistent with <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all the IRQ numbers for each interrupt.</p>
+<p><b>Example:</b> </p>
+<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
+<div class="fragment"><pre class="fragment">                ; External Interrupts
+                DCD     WAKEUP0_IRQHandler       ; 16+ 0: Wakeup PIO0.0
+                DCD     WAKEUP1_IRQHandler       ; 16+ 1: Wakeup PIO0.1
+                DCD     WAKEUP2_IRQHandler       ; 16+ 2: Wakeup PIO0.2
+                 :       :
+                 :       :
+                DCD     EINT1_IRQHandler         ; 16+30: PIO INT1
+                DCD     EINT0_IRQHandler         ; 16+31: PIO INT0
+         :  
+         :
+                EXPORT  WAKEUP0_IRQHandler       [WEAK]
+                EXPORT  WAKEUP1_IRQHandler       [WEAK]
+                EXPORT  WAKEUP2_IRQHandler       [WEAK]
+                 :       :
+                 :       :                                               
+                EXPORT  EINT1_IRQHandler         [WEAK]
+                EXPORT  EINT0_IRQHandler         [WEAK]
+
+WAKEUP0_IRQHandler
+WAKEUP1_IRQHandler
+WAKEUP1_IRQHandler
+      :
+      :
+EINT1_IRQHandler
+EINT0_IRQHandler
+                B       .
+</pre></div><h2><a class="anchor" id="startup_s_sec"></a>
+startup_Device.s Template File</h2>
+<p>The <a class="el" href="startup_s_pg.html#startup_s_sec">startup_Device.s Template File</a> for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p>
+<div class="fragment"><pre class="fragment">;/**************************************************************************//**
+; * @file     startup_&lt;Device&gt;.s
+; * @brief    CMSIS Cortex-M# Core Device Startup File for
+; *           Device &lt;Device&gt;
+; * @version  V3.01
+; * @date     06. March 2012
+; *
+; * @note
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- &lt;&lt;&lt; Use Configuration Wizard in Context Menu &gt;&gt;&gt; ------------------
+;*/
+
+
+; &lt;h&gt; Stack Configuration
+;   &lt;o&gt; Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
+; &lt;/h&gt;
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; &lt;h&gt; Heap Configuration
+;   &lt;o&gt;  Heap Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
+; &lt;/h&gt;
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     &lt;DeviceInterrupt&gt;_IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT  &lt;DeviceInterrupt&gt;_IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+&lt;DeviceInterrupt&gt;_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack &amp; Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="_templates_pg.html">Template Files</a>      </li>
+<!-- window showing the filter options -->
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+     onmouseover="return searchBox.OnSearchSelectShow()"
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html
new file mode 100644
index 0000000..eb5fb16
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html
@@ -0,0 +1,492 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>DWT_Type Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
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+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+    </ul>
+  </div>
+</div>
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+       class="ui-resizable-handle">
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+  initNavTree('struct_d_w_t___type.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">DWT_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="DWT_Type" -->
+<p>Structure type to access the Data Watchpoint and Trace Register (DWT).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">CTRL</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Control Register.  <a href="#a37964d64a58551b69ce4c8097210d37d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">CYCCNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Cycle Count Register.  <a href="#a71680298e85e96e57002f87e7ab78fd4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">CPICNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) CPI Count Register.  <a href="#a88cca2ab8eb1b5b507817656ceed89fc"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">EXCCNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Exception Overhead Count Register.  <a href="#ac0801a2328f3431e4706fed91c828f82"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">SLEEPCNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Sleep Count Register.  <a href="#a8afd5a4bf994011748bc012fa442c74d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">LSUCNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) LSU Count Register.  <a href="#aeba92e6c7fd3de4ba06bfd94f47f5b35"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">FOLDCNT</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) Folded-instruction Count Register.  <a href="#a35f2315f870a574e3e6958face6584ab"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">PCSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/ ) Program Counter Sample Register.  <a href="#abc5ae11d98da0ad5531a5e979a3c2ab5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">COMP0</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) Comparator Register 0.  <a href="#a7cf71ff4b30a8362690fddd520763904"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">MASK0</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) Mask Register 0.  <a href="#a5bb1c17fc754180cc197b874d3d8673f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">FUNCTION0</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) Function Register 0.  <a href="#a5fbd9947d110cc168941f6acadc4a729"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">RESERVED0</a> [1]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#addd893d655ed90d40705b20170daac59"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">COMP1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x030 (R/W) Comparator Register 1.  <a href="#a4a5bb70a5ce3752bd628d5ce5658cb0c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">MASK1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x034 (R/W) Mask Register 1.  <a href="#a0c684438a24f8c927e6e01c0e0a605ef"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">FUNCTION1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x038 (R/W) Function Register 1.  <a href="#a3345a33476ee58e165447a3212e6d747"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">RESERVED1</a> [1]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a069871233a8c1df03521e6d7094f1de4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">COMP2</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 (R/W) Comparator Register 2.  <a href="#a8927aedbe9fd6bdae8983088efc83332"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">MASK2</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x044 (R/W) Mask Register 2.  <a href="#a8ecdc8f0d917dac86b0373532a1c0e2e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">FUNCTION2</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 (R/W) Function Register 2.  <a href="#acba1654190641a3617fcc558b5e3f87b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">RESERVED2</a> [1]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a8556ca1c32590517602d92fe0cd55738"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">COMP3</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 (R/W) Comparator Register 3.  <a href="#a3df15697eec279dbbb4b4e9d9ae8b62f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">MASK3</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x054 (R/W) Mask Register 3.  <a href="#ae3f01137a8d28c905ddefe7333547fba"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">FUNCTION3</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x058 (R/W) Function Register 3.  <a href="#a80bd242fc05ca80f9db681ce4d82e890"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a7cf71ff4b30a8362690fddd520763904"></a><!-- doxytag: member="DWT_Type::COMP0" ref="a7cf71ff4b30a8362690fddd520763904" args="" -->
+<div class="memitem">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">DWT_Type::COMP0</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a4a5bb70a5ce3752bd628d5ce5658cb0c"></a><!-- doxytag: member="DWT_Type::COMP1" ref="a4a5bb70a5ce3752bd628d5ce5658cb0c" args="" -->
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+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
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+</div>
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+<div class="memdoc">
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+<a class="anchor" id="a3df15697eec279dbbb4b4e9d9ae8b62f"></a><!-- doxytag: member="DWT_Type::COMP3" ref="a3df15697eec279dbbb4b4e9d9ae8b62f" args="" -->
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+        </tr>
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+</div>
+<div class="memdoc">
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+</div>
+<a class="anchor" id="a88cca2ab8eb1b5b507817656ceed89fc"></a><!-- doxytag: member="DWT_Type::CPICNT" ref="a88cca2ab8eb1b5b507817656ceed89fc" args="" -->
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">DWT_Type::CPICNT</a></td>
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+<a class="anchor" id="a37964d64a58551b69ce4c8097210d37d"></a><!-- doxytag: member="DWT_Type::CTRL" ref="a37964d64a58551b69ce4c8097210d37d" args="" -->
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+
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+</div>
+<a class="anchor" id="a71680298e85e96e57002f87e7ab78fd4"></a><!-- doxytag: member="DWT_Type::CYCCNT" ref="a71680298e85e96e57002f87e7ab78fd4" args="" -->
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">DWT_Type::CYCCNT</a></td>
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+</div>
+<a class="anchor" id="a35f2315f870a574e3e6958face6584ab"></a><!-- doxytag: member="DWT_Type::FOLDCNT" ref="a35f2315f870a574e3e6958face6584ab" args="" -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html
new file mode 100644
index 0000000..5ac444b
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+<div id="top"><!-- do not remove this div! -->
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+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
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+</div>
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+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
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+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">FPU_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="FPU_Type" -->
+<p>Structure type to access the Floating Point Unit (FPU).  
+</p>
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+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a7b2967b069046c8544adbbc1db143a36"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8">FPCCR</a></td></tr>
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+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Floating-Point Default Status Control Register.  <a href="#a4d58ef3ebea69a5ec5acd8c90a9941b6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1">MVFR0</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/ ) Media and FP Feature Register 0.  <a href="#a135577b0a76bd3164be2a02f29ca46f1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d">MVFR1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/ ) Media and FP Feature Register 1.  <a href="#a776e8625853e1413c4e8330ec85c256d"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="aa48253f088dc524de80c42fbc995f66b"></a><!-- doxytag: member="FPU_Type::FPCAR" ref="aa48253f088dc524de80c42fbc995f66b" args="" -->
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+        </tr>
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+<div class="memdoc">
+
+</div>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html
new file mode 100644
index 0000000..6abb25b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html
@@ -0,0 +1,312 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
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+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
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+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">MPU_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="MPU_Type" -->
+<p>Structure type to access the Memory Protection Unit (MPU).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7">TYPE</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register.  <a href="#a6ae8a8c3a4909ae41447168d793608f7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328">CTRL</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register.  <a href="#aab33593671948b93b1c0908d78779328"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833">RNR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register.  <a href="#afd8de96a5d574c3953e2106e782f9833"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9">RBAR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register.  <a href="#a3f2e2448a77aadacd9f394f6c4c708d9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03">RASR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register.  <a href="#adc65d266d15ce9ba57b3d127e8267f03"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639">RBAR_A1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.  <a href="#a4dbcffa0a71c31e521b645b34b40e639"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185">RASR_A1</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.  <a href="#a94222f9a8637b5329016e18f08af7185"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395">RBAR_A2</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.  <a href="#a8703a00626dba046b841c0db6c78c395"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014">RASR_A2</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.  <a href="#a0aac7727a6225c6aa00627c36d51d014"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804">RBAR_A3</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.  <a href="#a9fda17c37b85ef317c7c8688ff8c5804"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d">RASR_A3</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.  <a href="#aced0b908173b9a4bae4f59452f0cdb0d"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="aab33593671948b93b1c0908d78779328"></a><!-- doxytag: member="MPU_Type::CTRL" ref="aab33593671948b93b1c0908d78779328" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328">MPU_Type::CTRL</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="adc65d266d15ce9ba57b3d127e8267f03"></a><!-- doxytag: member="MPU_Type::RASR" ref="adc65d266d15ce9ba57b3d127e8267f03" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03">MPU_Type::RASR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a94222f9a8637b5329016e18f08af7185"></a><!-- doxytag: member="MPU_Type::RASR_A1" ref="a94222f9a8637b5329016e18f08af7185" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185">MPU_Type::RASR_A1</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a0aac7727a6225c6aa00627c36d51d014"></a><!-- doxytag: member="MPU_Type::RASR_A2" ref="a0aac7727a6225c6aa00627c36d51d014" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014">MPU_Type::RASR_A2</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aced0b908173b9a4bae4f59452f0cdb0d"></a><!-- doxytag: member="MPU_Type::RASR_A3" ref="aced0b908173b9a4bae4f59452f0cdb0d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d">MPU_Type::RASR_A3</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a3f2e2448a77aadacd9f394f6c4c708d9"></a><!-- doxytag: member="MPU_Type::RBAR" ref="a3f2e2448a77aadacd9f394f6c4c708d9" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9">MPU_Type::RBAR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a4dbcffa0a71c31e521b645b34b40e639"></a><!-- doxytag: member="MPU_Type::RBAR_A1" ref="a4dbcffa0a71c31e521b645b34b40e639" args="" -->
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+        </tr>
+      </table>
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+<div class="memdoc">
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+<a class="anchor" id="a8703a00626dba046b841c0db6c78c395"></a><!-- doxytag: member="MPU_Type::RBAR_A2" ref="a8703a00626dba046b841c0db6c78c395" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395">MPU_Type::RBAR_A2</a></td>
+        </tr>
+      </table>
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+<div class="memdoc">
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+<a class="anchor" id="a9fda17c37b85ef317c7c8688ff8c5804"></a><!-- doxytag: member="MPU_Type::RBAR_A3" ref="a9fda17c37b85ef317c7c8688ff8c5804" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804">MPU_Type::RBAR_A3</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
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+</div>
+<a class="anchor" id="afd8de96a5d574c3953e2106e782f9833"></a><!-- doxytag: member="MPU_Type::RNR" ref="afd8de96a5d574c3953e2106e782f9833" args="" -->
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+<div class="memproto">
+      <table class="memname">
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+        </tr>
+      </table>
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+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a6ae8a8c3a4909ae41447168d793608f7"></a><!-- doxytag: member="MPU_Type::TYPE" ref="a6ae8a8c3a4909ae41447168d793608f7" args="" -->
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+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7">MPU_Type::TYPE</a></td>
+        </tr>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html
new file mode 100644
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@@ -0,0 +1,342 @@
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+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
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+</div>
+
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+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">NVIC_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="NVIC_Type" -->
+<p>Structure type to access the Nested Vectored Interrupt Controller (NVIC).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">ISER</a> [8]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Interrupt Set Enable Register.  <a href="#af90c80b7c2b48e248780b3781e0df80f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">RESERVED0</a> [24]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a2de17698945ea49abd58a2d45bdc9c80"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">ICER</a> [8]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Clear Enable Register.  <a href="#a1965a2e68b61d2e2009621f6949211a5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">RSERVED1</a> [24]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a6d1daf7ab6f2ba83f57ff67ae6f571fe"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">ISPR</a> [8]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set Pending Register.  <a href="#acf8e38fc2e97316242ddeb7ea959ab90"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">RESERVED2</a> [24]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a0953af43af8ec7fd5869a1d826ce5b72"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">ICPR</a> [8]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear Pending Register.  <a href="#a46241be64208436d35c9a4f8552575c5"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">RESERVED3</a> [24]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a9dd330835dbf21471e7b5be8692d77ab"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">IABR</a> [8]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Active bit Register.  <a href="#a33e917b381e08dabe4aa5eb2881a7c11"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">RESERVED4</a> [56]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a5c0e5d507ac3c1bd5cdaaf9bbd177790"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">IP</a> [240]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)  <a href="#a6524789fedb94623822c3e0a47f3d06c"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">RESERVED5</a> [644]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a4f753b4f824270175af045ac99bc12e8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__O uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">STIR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xE00 ( /W) Software Trigger Interrupt Register.  <a href="#a0b0d7f3131da89c659a2580249432749"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a33e917b381e08dabe4aa5eb2881a7c11"></a><!-- doxytag: member="NVIC_Type::IABR" ref="a33e917b381e08dabe4aa5eb2881a7c11" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">NVIC_Type::IABR</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a1965a2e68b61d2e2009621f6949211a5"></a><!-- doxytag: member="NVIC_Type::ICER" ref="a1965a2e68b61d2e2009621f6949211a5" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">NVIC_Type::ICER</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a46241be64208436d35c9a4f8552575c5"></a><!-- doxytag: member="NVIC_Type::ICPR" ref="a46241be64208436d35c9a4f8552575c5" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">NVIC_Type::ICPR</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a6524789fedb94623822c3e0a47f3d06c"></a><!-- doxytag: member="NVIC_Type::IP" ref="a6524789fedb94623822c3e0a47f3d06c" args="[240]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint8_t <a class="el" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">NVIC_Type::IP</a>[240]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af90c80b7c2b48e248780b3781e0df80f"></a><!-- doxytag: member="NVIC_Type::ISER" ref="af90c80b7c2b48e248780b3781e0df80f" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">NVIC_Type::ISER</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="acf8e38fc2e97316242ddeb7ea959ab90"></a><!-- doxytag: member="NVIC_Type::ISPR" ref="acf8e38fc2e97316242ddeb7ea959ab90" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">NVIC_Type::ISPR</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a2de17698945ea49abd58a2d45bdc9c80"></a><!-- doxytag: member="NVIC_Type::RESERVED0" ref="a2de17698945ea49abd58a2d45bdc9c80" args="[24]" -->
+<div class="memitem">
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+        </tr>
+      </table>
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+<div class="memdoc">
+
+</div>
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+<a class="anchor" id="a0953af43af8ec7fd5869a1d826ce5b72"></a><!-- doxytag: member="NVIC_Type::RESERVED2" ref="a0953af43af8ec7fd5869a1d826ce5b72" args="[24]" -->
+<div class="memitem">
+<div class="memproto">
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+
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+<div class="memitem">
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+      <table class="memname">
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+        </tr>
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+
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+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">uint32_t <a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type::RESERVED5</a>[644]</td>
+        </tr>
+      </table>
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+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a6d1daf7ab6f2ba83f57ff67ae6f571fe"></a><!-- doxytag: member="NVIC_Type::RSERVED1" ref="a6d1daf7ab6f2ba83f57ff67ae6f571fe" args="[24]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">uint32_t <a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type::RSERVED1</a>[24]</td>
+        </tr>
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+
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+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__O uint32_t <a class="el" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">NVIC_Type::STIR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="struct_n_v_i_c___type.html">NVIC_Type</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html
new file mode 100644
index 0000000..de2783a
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+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SCB_Type Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
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+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
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+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+<script type="text/javascript">
+  initNavTree('struct_s_c_b___type.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">SCB_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="SCB_Type" -->
+<p>Structure type to access the System Control Block (SCB).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">CPUID</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register.  <a href="#afa7a9ee34dfa1da0b60b4525da285032"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">ICSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register.  <a href="#a3e66570ab689d28aebefa7e84e85dc4a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">VTOR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register.  <a href="#a0faf96f964931cadfb71cfa54e051f6f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">AIRCR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.  <a href="#a6ed3c9064013343ea9fd0a73a734f29d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register.  <a href="#abfad14e7b4534d73d329819625d77a16"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">CCR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register.  <a href="#a6d273c6b90bad15c91dfbbad0f6e92d8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">SHP</a> [12]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)  <a href="#af6336103f8be0cab29de51daed5a65f4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SHCSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register.  <a href="#ae9891a59abbe51b0b2067ca507ca212f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">CFSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register.  <a href="#a2f94bf549b16fdeb172352e22309e3c4"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">HFSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register.  <a href="#a7bed53391da4f66d8a2a236a839d4c3d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">DFSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register.  <a href="#ad7d61d9525fa9162579c3da0b87bff8d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">MMFAR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register.  <a href="#ac49b24b3f222508464f111772f2c44dd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">BFAR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register.  <a href="#a31f79afe86c949c9862e7d5fce077c3a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">AFSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register.  <a href="#aeb77053c84f49c261ab5b8374e8958ef"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">PFR</a> [2]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register.  <a href="#a3f51c43f952f3799951d0c54e76b0cb7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">DFR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register.  <a href="#a586a5225467262b378c0f231ccc77f86"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">ADR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register.  <a href="#aaedf846e435ed05c68784b40d3db2bf2"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976">MMFR</a> [4]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register.  <a href="#aec2f8283d2737c6897188568a4214976"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">ISAR</a> [5]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register.  <a href="#acee8e458f054aac964268f4fe647ea4f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#ac89a5d9901e3748d22a7090bfca2bee6"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">CPACR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register.  <a href="#af460b56ce524a8e3534173f0aee78e85"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="aaedf846e435ed05c68784b40d3db2bf2"></a><!-- doxytag: member="SCB_Type::ADR" ref="aaedf846e435ed05c68784b40d3db2bf2" args="" -->
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+          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">SCB_Type::ADR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aeb77053c84f49c261ab5b8374e8958ef"></a><!-- doxytag: member="SCB_Type::AFSR" ref="aeb77053c84f49c261ab5b8374e8958ef" args="" -->
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">SCB_Type::AFSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a6ed3c9064013343ea9fd0a73a734f29d"></a><!-- doxytag: member="SCB_Type::AIRCR" ref="a6ed3c9064013343ea9fd0a73a734f29d" args="" -->
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+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a31f79afe86c949c9862e7d5fce077c3a"></a><!-- doxytag: member="SCB_Type::BFAR" ref="a31f79afe86c949c9862e7d5fce077c3a" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">SCB_Type::BFAR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a6d273c6b90bad15c91dfbbad0f6e92d8"></a><!-- doxytag: member="SCB_Type::CCR" ref="a6d273c6b90bad15c91dfbbad0f6e92d8" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">SCB_Type::CCR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a2f94bf549b16fdeb172352e22309e3c4"></a><!-- doxytag: member="SCB_Type::CFSR" ref="a2f94bf549b16fdeb172352e22309e3c4" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">SCB_Type::CFSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af460b56ce524a8e3534173f0aee78e85"></a><!-- doxytag: member="SCB_Type::CPACR" ref="af460b56ce524a8e3534173f0aee78e85" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">SCB_Type::CPACR</a></td>
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+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="afa7a9ee34dfa1da0b60b4525da285032"></a><!-- doxytag: member="SCB_Type::CPUID" ref="afa7a9ee34dfa1da0b60b4525da285032" args="" -->
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+<div class="memproto">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">SCB_Type::CPUID</a></td>
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+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a586a5225467262b378c0f231ccc77f86"></a><!-- doxytag: member="SCB_Type::DFR" ref="a586a5225467262b378c0f231ccc77f86" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">SCB_Type::DFR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ad7d61d9525fa9162579c3da0b87bff8d"></a><!-- doxytag: member="SCB_Type::DFSR" ref="ad7d61d9525fa9162579c3da0b87bff8d" args="" -->
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+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">SCB_Type::DFSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a7bed53391da4f66d8a2a236a839d4c3d"></a><!-- doxytag: member="SCB_Type::HFSR" ref="a7bed53391da4f66d8a2a236a839d4c3d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">SCB_Type::HFSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a3e66570ab689d28aebefa7e84e85dc4a"></a><!-- doxytag: member="SCB_Type::ICSR" ref="a3e66570ab689d28aebefa7e84e85dc4a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">SCB_Type::ICSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="acee8e458f054aac964268f4fe647ea4f"></a><!-- doxytag: member="SCB_Type::ISAR" ref="acee8e458f054aac964268f4fe647ea4f" args="[5]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">SCB_Type::ISAR</a>[5]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ac49b24b3f222508464f111772f2c44dd"></a><!-- doxytag: member="SCB_Type::MMFAR" ref="ac49b24b3f222508464f111772f2c44dd" args="" -->
+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">SCB_Type::MMFAR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aec2f8283d2737c6897188568a4214976"></a><!-- doxytag: member="SCB_Type::MMFR" ref="aec2f8283d2737c6897188568a4214976" args="[4]" -->
+<div class="memitem">
+<div class="memproto">
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+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a3f51c43f952f3799951d0c54e76b0cb7"></a><!-- doxytag: member="SCB_Type::PFR" ref="a3f51c43f952f3799951d0c54e76b0cb7" args="[2]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">SCB_Type::PFR</a>[2]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ac89a5d9901e3748d22a7090bfca2bee6"></a><!-- doxytag: member="SCB_Type::RESERVED0" ref="ac89a5d9901e3748d22a7090bfca2bee6" args="[5]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type::RESERVED0</a>[5]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="abfad14e7b4534d73d329819625d77a16"></a><!-- doxytag: member="SCB_Type::SCR" ref="abfad14e7b4534d73d329819625d77a16" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCB_Type::SCR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ae9891a59abbe51b0b2067ca507ca212f"></a><!-- doxytag: member="SCB_Type::SHCSR" ref="ae9891a59abbe51b0b2067ca507ca212f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SCB_Type::SHCSR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af6336103f8be0cab29de51daed5a65f4"></a><!-- doxytag: member="SCB_Type::SHP" ref="af6336103f8be0cab29de51daed5a65f4" args="[12]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint8_t <a class="el" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">SCB_Type::SHP</a>[12]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a0faf96f964931cadfb71cfa54e051f6f"></a><!-- doxytag: member="SCB_Type::VTOR" ref="a0faf96f964931cadfb71cfa54e051f6f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">SCB_Type::VTOR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="struct_s_c_b___type.html">SCB_Type</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
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+</div>
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+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html
new file mode 100644
index 0000000..4c307fe
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html
@@ -0,0 +1,192 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SCnSCB_Type Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
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+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
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+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+        <div id="MSearchBox" class="MSearchBoxInactive">
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+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
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+  initNavTree('struct_s_cn_s_c_b___type.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">SCnSCB_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="SCnSCB_Type" -->
+<p>Structure type to access the System Control and ID Register not in the SCB.  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">RESERVED0</a> [1]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#afe1d5fd2966d5062716613b05c8d0ae1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">ICTR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register.  <a href="#ad99a25f5d4c163d9005ca607c24f6a98"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">ACTLR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Auxiliary Control Register.  <a href="#aacadedade30422fed705e8dfc8e6cd8d"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="aacadedade30422fed705e8dfc8e6cd8d"></a><!-- doxytag: member="SCnSCB_Type::ACTLR" ref="aacadedade30422fed705e8dfc8e6cd8d" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">SCnSCB_Type::ACTLR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ad99a25f5d4c163d9005ca607c24f6a98"></a><!-- doxytag: member="SCnSCB_Type::ICTR" ref="ad99a25f5d4c163d9005ca607c24f6a98" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__I uint32_t <a class="el" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">SCnSCB_Type::ICTR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="afe1d5fd2966d5062716613b05c8d0ae1"></a><!-- doxytag: member="SCnSCB_Type::RESERVED0" ref="afe1d5fd2966d5062716613b05c8d0ae1" args="[1]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type::RESERVED0</a>[1]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
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+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
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+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html
new file mode 100644
index 0000000..cadd4e0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html
@@ -0,0 +1,507 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>TPI_Type Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
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+    </ul>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+    <div id="nav-tree-contents">
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('struct_t_p_i___type.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">TPI_Type Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="TPI_Type" -->
+<p>Structure type to access the Trace Port Interface Register (TPI).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">SSPSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) Supported Parallel Port Size Register.  <a href="#a158e9d784f6ee6398f4bdcb2e4ca0912"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">CSPSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Current Parallel Port Size Register.  <a href="#aa723ef3d38237aa2465779b3cc73a94a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">RESERVED0</a> [2]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#af143c5e8fc9a3b2be2878e9c1f331aa9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">ACPR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.  <a href="#ad75832a669eb121f6fce3c28d36b7fab"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">RESERVED1</a> [55]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#ac3956fe93987b725d89d3be32738da12"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">SPPR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0F0 (R/W) Selected Pin Protocol Register.  <a href="#a3eb655f2e45d7af358775025c1a50c8e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">RESERVED2</a> [131]</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#ac7bbb92e6231b9b38ac483f7d161a096"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">FFSR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/ ) Formatter and Flush Status Register.  <a href="#ae67849b2c1016fe6ef9095827d16cddd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">FFCR</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x304 (R/W) Formatter and Flush Control Register.  <a href="#a3eb42d69922e340037692424a69da880"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">FSCR</a></td></tr>
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+</table>
+<hr/><h2>Field Documentation</h2>
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+<div class="memitem">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">TPI_Type::FIFO0</a></td>
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+<div class="memitem">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">TPI_Type::ITATBCTR0</a></td>
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+<div class="memitem">
+<div class="memproto">
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+          <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">TPI_Type::ITATBCTR2</a></td>
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+<div class="memproto">
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+<div class="memitem">
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+<div class="memproto">
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+        </tr>
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+<div class="memitem">
+<div class="memproto">
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+        </tr>
+      </table>
+</div>
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+
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+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">uint32_t <a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type::RESERVED4</a>[1]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
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+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type::RESERVED5</a>[39]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a476ca23fbc9480f1697fbec871130550"></a><!-- doxytag: member="TPI_Type::RESERVED7" ref="a476ca23fbc9480f1697fbec871130550" args="[8]" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type::RESERVED7</a>[8]</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
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+<div class="memitem">
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+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">TPI_Type::SPPR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a158e9d784f6ee6398f4bdcb2e4ca0912"></a><!-- doxytag: member="TPI_Type::SSPSR" ref="a158e9d784f6ee6398f4bdcb2e4ca0912" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__IO uint32_t <a class="el" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">TPI_Type::SSPSR</a></td>
+        </tr>
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aa4b603c71768dbda553da571eccba1fe"></a><!-- doxytag: member="TPI_Type::TRIGGER" ref="aa4b603c71768dbda553da571eccba1fe" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">__I uint32_t <a class="el" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TPI_Type::TRIGGER</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="struct_t_p_i___type.html">TPI_Type</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html
new file mode 100644
index 0000000..04920b0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/system_c_pg.html
@@ -0,0 +1,286 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
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+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+<script type="text/javascript">
+  initNavTree('system_c_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The <a class="el" href="system_c_pg.html">System Configuration Files system_&lt;device&gt;.c and system_&lt;device&gt;.h</a> provides as a minimum the functions described under <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a>. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.</p>
+<p>For devices with external memory BUS the system_&lt;device&gt;.c also configures the BUS system.</p>
+<p>The silicon vendor might expose other functions (i.e. for power configuration) in the system_&lt;device&gt;.c file. In case of additional features the function prototypes need to be added to the system_&lt;device&gt;.h header file.</p>
+<h2><a class="anchor" id="system_Device_sec"></a>
+system_Device.c Template File</h2>
+<p>The <a class="el" href="system_c_pg.html#system_Device_sec">system_Device.c Template File</a> for the Cortex-M3 is shown below.</p>
+<div class="fragment"><pre class="fragment">/**************************************************************************//**
+ * @file     system_&lt;Device&gt;.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device &lt;Device&gt;
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include &lt;stdint.h&gt;
+#include "&lt;Device&gt;.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization     
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!&lt; System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+</pre></div><h2><a class="anchor" id="system_Device_h_sec"></a>
+system_Device.h Template File</h2>
+<p>The system_&lt;device&gt;.h header file contains prototypes to access the public functions in the system_&lt;device&gt;.c file. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> is shown below.</p>
+<div class="fragment"><pre class="fragment">/**************************************************************************//**
+ * @file     system_&lt;Device&gt;.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device &lt;Device&gt;
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_&lt;Device&gt;_H   /* ToDo: replace '&lt;Device&gt;' with your device name */
+#define SYSTEM_&lt;Device&gt;_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include &lt;stdint.h&gt;
+
+extern uint32_t SystemCoreClock;     /*!&lt; System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_&lt;Device&gt;_H */
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="_templates_pg.html">Template Files</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
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+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/tab_a.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/tab_a.png
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@@ -0,0 +1,71 @@
+.tabs, .tabs1, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 10px;
+}
+
+.tabs1 {
+    background-image: url('tab_topnav.png');
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+}
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+    font-size: 9px;
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+    line-height: 24px;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    list-style: none;
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+
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+    float: left;
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+    display: block;
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html
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@@ -0,0 +1,268 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>APSR_Type Union Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
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+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('union_a_p_s_r___type.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">APSR_Type Union Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="APSR_Type" -->
+<p>Union type to access the Application Program Status Register (APSR).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" >struct {</td></tr>
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+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 31 Negative condition code flag  <a href="#a77dede9507ca1f554043f49035299f2e"></a><br/></td></tr>
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+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <a href="#ae4c2ef8c9430d7b7bef5cbfbbaed3a94"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="afbce95646fd514c10aa85ec0a33db728"></a><!-- doxytag: member="APSR_Type::_reserved0" ref="afbce95646fd514c10aa85ec0a33db728" args="" -->
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+        </tr>
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+        </tr>
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+<div class="memdoc">
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+</div>
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+<a class="anchor" id="ae4c2ef8c9430d7b7bef5cbfbbaed3a94"></a><!-- doxytag: member="APSR_Type::w" ref="ae4c2ef8c9430d7b7bef5cbfbbaed3a94" args="" -->
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+        </tr>
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+</div>
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+  <div id="nav-path" class="navpath">
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+
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+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html
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+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>IPSR_Type Union Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">IPSR_Type Union Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="IPSR_Type" -->
+<p>Union type to access the Interrupt Program Status Register (IPSR).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" >struct {</td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">ISR</a>:9</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0.. 8 Exception number  <a href="#afaf0827367274b557f0d28e0a2398229"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">_reserved0</a>:23</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 9..31 Reserved  <a href="#aa0449af1acf460572a66b57e2d07a931"></a><br/></td></tr>
+<tr><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">b</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access.  <a href="#add0d6497bd50c25569ea22b48a03ec50"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">w</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <a href="#a4adca999d3a0bc1ae682d73ea7cfa879"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="ad2eb0a06de4f03f58874a727716aa9aa"></a><!-- doxytag: member="IPSR_Type::_reserved0" ref="ad2eb0a06de4f03f58874a727716aa9aa" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">uint32_t <a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type::_reserved0</a></td>
+        </tr>
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+<div class="memdoc">
+
+</div>
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+<a class="anchor" id="add0d6497bd50c25569ea22b48a03ec50"></a><!-- doxytag: member="IPSR_Type::b" ref="add0d6497bd50c25569ea22b48a03ec50" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">struct { ... }   <a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type::b</a></td>
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+<div class="memdoc">
+
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+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
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+          <td class="memname">uint32_t <a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type::ISR</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a4adca999d3a0bc1ae682d73ea7cfa879"></a><!-- doxytag: member="IPSR_Type::w" ref="a4adca999d3a0bc1ae682d73ea7cfa879" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type::w</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="union_i_p_s_r___type.html">IPSR_Type</a>      </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html
new file mode 100644
index 0000000..1816f20
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+<title>xPSR_Type Union Reference</title>
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+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-CORE
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li class="current"><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
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+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">xPSR_Type Union Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="xPSR_Type" -->
+<p>Union type to access the Special-Purpose Program Status Registers (xPSR).  
+</p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" >struct {</td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970">ISR</a>:9</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0.. 8 Exception number  <a href="#a14aa41f658bf70c2d44435d24761a760"></a><br/></td></tr>
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+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 9..23 Reserved  <a href="#a7af0067da9805e481890c297bf4ed70f"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658">T</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 24 Thumb bit (read 0)  <a href="#a5224815d0f90fb7d26c7007bfb8e38d5"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328">IT</a>:2</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 25..26 saved IT state (read 0)  <a href="#a0c9d4cef85e4cc7d6dc701d7d3377af0"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c">Q</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 27 Saturation condition flag  <a href="#a0713a6888c5b556e9050aa82d2c1b0e1"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a">V</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 Overflow condition code flag  <a href="#a6dd30396c78f8bc53d30ca13b058cbb2"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d">C</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 29 Carry condition code flag  <a href="#ae33d83822b56cd849b9fa9affddd59b2"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562">Z</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 30 Zero condition code flag  <a href="#ac1f7475b01a46aef06d9f53d3a2a69ef"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5">N</a>:1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 31 Negative condition code flag  <a href="#a38ba57343e56c653939fd792c19af047"></a><br/></td></tr>
+<tr><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70">b</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access.  <a href="#a3b1063bb5cdad67e037cba993b693b70"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">w</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <a href="#a1a47176768f45f79076c4f5b1b534bc2"></a><br/></td></tr>
+</table>
+<hr/><h2>Field Documentation</h2>
+<a class="anchor" id="af438e0f407357e914a70b5bd4d6a97c5"></a><!-- doxytag: member="xPSR_Type::_reserved0" ref="af438e0f407357e914a70b5bd4d6a97c5" args="" -->
+<div class="memitem">
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+<div class="memdoc">
+
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+<div class="memitem">
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+        </tr>
+      </table>
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+
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+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="unionx_p_s_r___type.html">xPSR_Type</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:37:44 for CMSIS-CORE by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Introduction</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
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+
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS
+   &#160;<span id="projectnumber">Version 3.01</span>
+   </div>
+   <div id="projectbrief">Cortex Microcontroller Software Interface Standard</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li class="current"><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
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+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Introduction </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The <b>Cortex Microcontroller Software Interface Standard</b> (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.</p>
+<p>The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.</p>
+<p>The CMSIS components are:</p>
+<ul>
+<li><a href="../../Core/html/index.html"><b>CMSIS-CORE</b></a>: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300. Included are also SIMD intrinsic functions for Cortex-M4 SIMD instructions.</li>
+</ul>
+<ul>
+<li><a href="../../DSP/html/index.html"><b>CMSIS-DSP</b></a>: DSP Library Collection with over 60 Functions for various data types: fix-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for Cortex-M0, Cortex-M3, and Cortex-M4. The Cortex-M4 implementation is optimized for the SIMD instruction set.</li>
+</ul>
+<ul>
+<li><a href="../../RTOS/html/index.html"><b>CMSIS-RTOS API</b></a>: Common API for Real-Time operating systems. It provides a standardized programming interface that is portable to many RTOS and enables therefore software templates, middleware, libraries, and other components that can work acrosss supported the RTOS systems.</li>
+</ul>
+<ul>
+<li><a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a>: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.</li>
+</ul>
+<div class="image">
+<img src="CMSIS_V3_small.png" alt="CMSIS_V3_small.png"/>
+<div class="caption">
+CMSIS Structure</div></div>
+ <h2><a class="anchor" id="Motivation"></a>
+Motivation</h2>
+<p>CMSIS has been created to help the industry in standardization. It is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard. In detail the benefits of the CMSIS are:</p>
+<ul>
+<li>Consistent software interfaces improve the software portability and re-usability. Generic software libraries can interface with device libraries from various silicon vendors.</li>
+<li>Reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through an easy to use and standardized software interface.</li>
+<li>Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR, and GNU).</li>
+<li>Enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output and RTOS kernel awareness.</li>
+</ul>
+<h2><a class="anchor" id="CodingRules"></a>
+Coding Rules</h2>
+<p>The CMSIS uses the following essential coding rules and conventions:</p>
+<ul>
+<li>Compliant with ANSI C and C++.</li>
+<li>Uses ANSI C standard data types defined in <b>&lt;stdint.h&gt;</b>.</li>
+<li>Variables and parameters have a complete data type.</li>
+<li>Expressions for <em>#define</em> constants are enclosed in parenthesis.</li>
+<li>Conforms to MISRA 2004. MIRSA rule violations are documented.</li>
+</ul>
+<p>In addition, the CMSIS recommends the following conventions for identifiers:</p>
+<ul>
+<li><b>CAPITAL</b> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
+<li><b>CamelCase</b> names to identify function names and interrupt functions.</li>
+<li><b>Namespace_</b> prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).</li>
+</ul>
+<p>The CMSIS is documented within the source files with: </p>
+<ul>
+<li>Comments that use the C or C++ style. </li>
+<li>Doxygen compliant <b>function comments</b> that provide:<ul>
+<li>brief function overview.</li>
+<li>detailed description of the function.</li>
+<li>detailed parameter explanation.</li>
+<li>detailed information about return values.</li>
+</ul>
+</li>
+</ul>
+<p>Doxygen comment example: </p>
+<div class="fragment"><pre class="fragment">
+/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
+</pre></div><h2><a class="anchor" id="License"></a>
+Licence</h2>
+<p>The CMSIS is provided free of charge by ARM and can be used for all Cortex-M based devices. View the <a href="..\..\..\CMSIS END USER LICENCE AGREEMENT.pdf">LICENCE AGREEMENT for CMSIS</a> in detail. </p>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS by ARM Ltd. All rights reserved.
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/Timer.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html
new file mode 100644
index 0000000..89bffb7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html
@@ -0,0 +1,164 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Using a CMSIS RTOS Implementation</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('_using_o_s.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Using a CMSIS RTOS Implementation </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>A CMSIS RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based application the RTOS library (and typically a configuration file) needs to be added. The available functionality of the RTOS library is defined in the file <b><a class="el" href="cmsis__os_8h.html">cmsis_os.h</a></b> that is specific for each RTOS implementation.</p>
+<div class="image">
+<img src="CMSIS_RTOS_Files.png" alt="CMSIS_RTOS_Files.png"/>
+<div class="caption">
+CMSIS-RTOS File Structure</div></div>
+<p> Depending on the CMSIS-RTOS implementation, execution may start with the <b>main</b> function as the first thread. This has the benefit that an application programmer may use other middleware libraries that create threads internally, but the remaining part of the user application just uses the <b>main</b> thread. Therefore, the usage of the RTOS can be invisible to the application programmer, but libraries can use CMSIS-RTOS features.</p>
+<p>Once the files are added to a project, the user can start using the CMSIS-RTOS functions. A code example is provided below:</p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;<a class="code" href="cmsis__os_8h.html">cmsis_os.h</a>&quot;</span>                           <span class="comment">// CMSIS RTOS header file</span>
+
+<span class="keywordtype">void</span> job1 (<span class="keywordtype">void</span> <span class="keyword">const</span> *argument)  {             <span class="comment">// thread function &#39;job1&#39;</span>
+  <span class="keywordflow">while</span> (1)  {
+     :                                          <span class="comment">// execute some code</span>
+    <a class="code" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255" title="Wait for Timeout (Time Delay)">osDelay</a> (10);                               <span class="comment">// delay execution for 10 milli seconds</span>
+  }
+}
+<span class="comment">// define job1 as thread function</span>
+<a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f" title="Create a Thread Definition with function, priority, and stack requirements.">osThreadDef</a>(job1, <a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b" title="priority: above normal">osPriorityAboveNormal</a>, 1, 0); <span class="comment">// define job1 as thread function</span>
+
+
+<span class="keywordtype">void</span> job2 (<span class="keywordtype">void</span> <span class="keyword">const</span> *argument)  {             <span class="comment">// thread function &#39;job2&#39;</span>
+  <a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db" title="Create a thread and add it to Active Threads and set it to state READY.">osThreadCreate</a>(<a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453" title="Access a Thread defintion.">osThread</a>(job1),NULL);          <span class="comment">// create job1 thread</span>
+  <span class="keywordflow">while</span> (1)   {
+    :                                           <span class="comment">// execute some code</span>
+  }
+}
+
+<a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f" title="Create a Thread Definition with function, priority, and stack requirements.">osThreadDef</a>(job2, <a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1" title="priority: normal (default)">osPriorityNormal</a>, 1, 0);      <span class="comment">// define job2 as thread function</span>
+
+
+<span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {                               <span class="comment">// program execution starts here</span>
+    :                                           <span class="comment">// setup and initialize</span>
+  <a class="code" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8" title="Start the RTOS Kernel with executing the specified thread.">osKernelStart</a> (<a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453" title="Access a Thread defintion.">osThread</a>(job2), NULL);         <span class="comment">// start kernel with job2 execution</span>
+  <span class="keywordflow">while</span> (1);                                    <span class="comment">// program will never reach this point</span>
+}
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/annotated.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/annotated.html
new file mode 100644
index 0000000..2c03c28
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/annotated.html
@@ -0,0 +1,148 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Data Structures</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li class="current"><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="classes.html"><span>Data&#160;Structure&#160;Index</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('annotated.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Data Structures</div>  </div>
+</div>
+<div class="contents">
+<div class="textblock">Here are the data structures with brief descriptions:</div><table>
+  <tr><td class="indexkey"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q">os_mailQ</a></td><td class="indexvalue"></td></tr>
+  <tr><td class="indexkey"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a></td><td class="indexvalue">Event structure contains detailed information about an event </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_mail_q_def__t.html">osMailQDef_t</a></td><td class="indexvalue">Definition structure for mail queue </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_message_q_def__t.html">osMessageQDef_t</a></td><td class="indexvalue">Definition structure for message queue </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a></td><td class="indexvalue">Mutex Definition structure contains setup information for a mutex </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_pool_def__t.html">osPoolDef_t</a></td><td class="indexvalue">Definition structure for memory block allocation </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a></td><td class="indexvalue">Semaphore Definition structure contains setup information for a semaphore </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_thread_def__t.html">osThreadDef_t</a></td><td class="indexvalue">Thread Definition structure contains startup information of a thread </td></tr>
+  <tr><td class="indexkey"><a class="el" href="structos_timer_def__t.html">osTimerDef_t</a></td><td class="indexvalue">Timer Definition structure contains timer parameters </td></tr>
+</table>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/bc_s.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/bc_s.png
new file mode 100644
index 0000000..51ba006
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/bc_s.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/closed.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/closed.png
new file mode 100644
index 0000000..b7d4bd9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/closed.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css
new file mode 100644
index 0000000..a5c4b8d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 200% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: center;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html
new file mode 100644
index 0000000..7dceb42
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html
@@ -0,0 +1,193 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>cmsis_os.txt File Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('cmsis__os_8txt.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#enum-members">Enumerations</a>  </div>
+  <div class="headertitle">
+<div class="title">cmsis_os.txt File Reference</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> { <br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81">osPriorityIdle</a> =  -3, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4">osPriorityLow</a> =  -2, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6">osPriorityBelowNormal</a> =  -1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1">osPriorityNormal</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b">osPriorityAboveNormal</a> =  +1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2">osPriorityHigh</a> =  +2, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af">osPriorityRealtime</a> =  +3, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4">osPriorityError</a> =  0x84
+<br/>
+ }</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9">os_timer_type</a> { <br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951">osTimerOnce</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788">osTimerPeriodic</a> =  1
+<br/>
+ }</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> { <br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f">osOK</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518">osEventSignal</a> =  0x08, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342">osEventMessage</a> =  0x10, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926">osEventMail</a> =  0x20, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177">osEventTimeout</a> =  0x40, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109">osErrorParameter</a> =  0x80, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d">osErrorResource</a> =  0x81, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467">osErrorTimeoutResource</a> =  0xC1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f">osErrorISR</a> =  0x82, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65">osErrorISRRecursive</a> =  0x83, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f">osErrorPriority</a> =  0x84, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81">osErrorNoMemory</a> =  0x85, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee">osErrorValue</a> =  0x86, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc">osErrorOS</a> =  0xFF, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1">os_status_reserved</a> =  0x7FFFFFFF
+<br/>
+ }</td></tr>
+</table>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="cmsis__os_8txt.html">cmsis_os.txt</a>      </li>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html
new file mode 100644
index 0000000..05bb698
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html
@@ -0,0 +1,169 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Header File Template: cmsis_os.h</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+               onfocus="searchBox.OnSearchFieldFocus(true)" 
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+<script type="text/javascript">
+  initNavTree('cmsis_os_h.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Header File Template: <a class="el" href="cmsis__os_8h.html">cmsis_os.h</a> </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The file <b><a class="el" href="cmsis__os_8h.html">cmsis_os.h</a></b> is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). Each RTOS that is compliant with CMSIS-RTOS shall provide a specific <b><a class="el" href="cmsis__os_8h.html">cmsis_os.h</a></b> header file that represents its implementation.</p>
+<p>The file <a class="el" href="cmsis__os_8h.html">cmsis_os.h</a> contains:</p>
+<ul>
+<li>CMSIS-RTOS API function definitions</li>
+<li>struct definitions for parameters and return types</li>
+<li>status and priority values used by CMSIS-RTOS API functions</li>
+<li>macros for defining threads and other kernel objects</li>
+</ul>
+<p><b>Name conventions and header file modifications</b></p>
+<p>All definitions are prefixed with <b>os</b> to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed <b>os_</b> are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. <b>osThread</b>.</p>
+<p>Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel.</p>
+<p>Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.</p>
+<p><b>Function calls from interrupt service routines</b></p>
+<p>The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):</p>
+<ul>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">osSignalSet</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">osSemaphoreRelease</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">osPoolAlloc</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">osPoolCAlloc</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">osPoolFree</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">osMessagePut</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">osMessageGet</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">osMailAlloc</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">osMailCAlloc</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">osMailGet</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">osMailPut</a>, <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">osMailFree</a></li>
+</ul>
+<p>Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code <b>osErrorISR</b>. In some implementations this condition might be caught using the HARD FAULT vector.</p>
+<p>Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code <b>osErrorISRRecursive</b>.</p>
+<p><b>Define and reference object definitions</b></p>
+<p>With <b>#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file that is used troughtout a project as shown below:</p>
+<p><em>Header File</em> </p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &lt;<a class="code" href="cmsis__os_8h.html">cmsis_os.h</a>&gt;</span>                                         <span class="comment">// CMSIS RTOS header file</span>
+
+<span class="comment">// Thread definition</span>
+<span class="keyword">extern</span> <span class="keywordtype">void</span> thread_sample (<span class="keywordtype">void</span> <span class="keyword">const</span> *argument);             <span class="comment">// function prototype</span>
+<a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f" title="Create a Thread Definition with function, priority, and stack requirements.">osThreadDef</a> (thread_sample, <a class="code" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6" title="priority: below normal">osPriorityBelowNormal</a>, 1, 100);
+
+<span class="comment">// Pool definition</span>
+<a class="code" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b" title="Define a Memory Pool.">osPoolDef</a>(MyPool, 10, <span class="keywordtype">long</span>);                      
+</pre></div><p>This header file defines all objects when included in a C/C++ source file. When <b>#define osObjectsExternal</b> is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project.</p>
+<p><em>Example</em> </p>
+<div class="fragment"><pre class="fragment"><span class="preprocessor">#include &quot;osObjects.h&quot;</span>     <span class="comment">// Definition of the CMSIS-RTOS objects</span>
+</pre></div><div class="fragment"><pre class="fragment"><span class="preprocessor">#define osObjectExternal   // Objects will be defined as external symbols</span>
+<span class="preprocessor">#include &quot;osObjects.h&quot;     // Reference to the CMSIS-RTOS objects</span>
+</pre></div> </div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
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+<title>Data Fields - Variables</title>
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+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+   <div id="projectname">CMSIS-RTOS
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+  
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+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+, <a class="el" href="structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">osMailQDef_t</a>
+, <a class="el" href="structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">osMessageQDef_t</a>
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+: <a class="el" href="structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47">osTimerDef_t</a>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
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+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
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+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
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+  
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+</div>
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+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
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+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
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+    <div id="nav-tree-contents">
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+       class="ui-resizable-handle">
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+<script type="text/javascript">
+  initNavTree('globals.html','');
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+<div id="doc-content">
+<div class="contents">
+&#160;<ul>
+<li>osCMSIS
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1">cmsis_os.h</a>
+</li>
+<li>osCMSIS_KERNEL
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de">cmsis_os.h</a>
+</li>
+<li>osFeature_MailQ
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">cmsis_os.h</a>
+</li>
+<li>osFeature_MainThread
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">cmsis_os.h</a>
+</li>
+<li>osFeature_MessageQ
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203">cmsis_os.h</a>
+</li>
+<li>osFeature_Pool
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">cmsis_os.h</a>
+</li>
+<li>osFeature_Semaphore
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a">cmsis_os.h</a>
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+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
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+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
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+      </li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+      <li><a href="globals_defs.html"><span>Defines</span></a></li>
+    </ul>
+  </div>
+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li><a href="#index_o"><span>o</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('globals.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_o"></a>- o -</h3><ul>
+<li>osDelay()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">cmsis_os.h</a>
+</li>
+<li>osKernelRunning()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5">cmsis_os.h</a>
+</li>
+<li>osKernelStart()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">cmsis_os.h</a>
+</li>
+<li>osMailAlloc()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">cmsis_os.h</a>
+</li>
+<li>osMailCAlloc()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">cmsis_os.h</a>
+</li>
+<li>osMailCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">cmsis_os.h</a>
+</li>
+<li>osMailFree()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">cmsis_os.h</a>
+</li>
+<li>osMailGet()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">cmsis_os.h</a>
+</li>
+<li>osMailPut()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">cmsis_os.h</a>
+</li>
+<li>osMessageCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">cmsis_os.h</a>
+</li>
+<li>osMessageGet()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">cmsis_os.h</a>
+</li>
+<li>osMessagePut()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">cmsis_os.h</a>
+</li>
+<li>osMutexCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">cmsis_os.h</a>
+</li>
+<li>osMutexRelease()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">cmsis_os.h</a>
+</li>
+<li>osMutexWait()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">cmsis_os.h</a>
+</li>
+<li>osPoolAlloc()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">cmsis_os.h</a>
+</li>
+<li>osPoolCAlloc()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">cmsis_os.h</a>
+</li>
+<li>osPoolCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">cmsis_os.h</a>
+</li>
+<li>osPoolFree()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">cmsis_os.h</a>
+</li>
+<li>osSemaphoreCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">cmsis_os.h</a>
+</li>
+<li>osSemaphoreRelease()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">cmsis_os.h</a>
+</li>
+<li>osSemaphoreWait()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">cmsis_os.h</a>
+</li>
+<li>osSignalClear()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8">cmsis_os.h</a>
+</li>
+<li>osSignalGet()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1">cmsis_os.h</a>
+</li>
+<li>osSignalSet()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">cmsis_os.h</a>
+</li>
+<li>osSignalWait()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">cmsis_os.h</a>
+</li>
+<li>osThreadCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">cmsis_os.h</a>
+</li>
+<li>osThreadGetId()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">cmsis_os.h</a>
+</li>
+<li>osThreadGetPriority()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9">cmsis_os.h</a>
+</li>
+<li>osThreadSetPriority()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">cmsis_os.h</a>
+</li>
+<li>osThreadTerminate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">cmsis_os.h</a>
+</li>
+<li>osThreadYield()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">cmsis_os.h</a>
+</li>
+<li>osTimerCreate()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">cmsis_os.h</a>
+</li>
+<li>osTimerStart()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">cmsis_os.h</a>
+</li>
+<li>osTimerStop()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091">cmsis_os.h</a>
+</li>
+<li>osWait()
+: <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">cmsis_os.h</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html
new file mode 100644
index 0000000..ad6be33
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/globals_type.html
@@ -0,0 +1,165 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Index</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
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+  </div>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('globals.html','');
+</script>
+<div id="doc-content">
+<div class="contents">
+&#160;<ul>
+<li>os_pthread
+: <a class="el" href="cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7">cmsis_os.h</a>
+</li>
+<li>os_ptimer
+: <a class="el" href="cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065">cmsis_os.h</a>
+</li>
+<li>osMailQId
+: <a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">cmsis_os.h</a>
+</li>
+<li>osMessageQId
+: <a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">cmsis_os.h</a>
+</li>
+<li>osMutexId
+: <a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">cmsis_os.h</a>
+</li>
+<li>osPoolId
+: <a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">cmsis_os.h</a>
+</li>
+<li>osSemaphoreId
+: <a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">cmsis_os.h</a>
+</li>
+<li>osThreadId
+: <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">cmsis_os.h</a>
+</li>
+<li>osTimerId
+: <a class="el" href="cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7">cmsis_os.h</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html
new file mode 100644
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>CMSIS-RTOS API</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
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+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
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+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+  initNavTree('group___c_m_s_i_s___r_t_o_s.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#groups">Modules</a>  </div>
+  <div class="headertitle">
+<div class="title">CMSIS-RTOS API</div>  </div>
+</div>
+<div class="contents">
+
+<p>This section describes the CMSIS-RTOS API.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="groups"></a>
+Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html">Kernel Information and Control</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Provide version/system information and start the RTOS Kernel. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html">Thread Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Define, create, and control thread functions. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html">Generic Wait Functions</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Wait for a time period or unspecified events. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html">Timer Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Create and control timer and timer callback functions. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html">Signal Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Control or wait for signal flags. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html">Mutex Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Synchronize thread execution with a Mutex. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html">Semaphore Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Control access to shared resources. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html">Memory Pool Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Define and manage fixed-size memory pools. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html">Message Queue Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Control, send, receive, or wait for messages. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html">Mail Queue Management</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Control, send, receive, or wait for mail. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html">Generic Data Types and Definitions</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Data Type Definitions used by the CMSIS-RTOS API functions. </p>
+<br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight"><p>Status and Error Codes returned by CMSIS-RTOS API functions. </p>
+<br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel. It provides the following functional modules: </p>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html
new file mode 100644
index 0000000..81dd20d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html
@@ -0,0 +1,300 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Generic Data Types and Definitions</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group___c_m_s_i_s___r_t_o_s___definitions.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#nested-classes">Data Structures</a>  </div>
+  <div class="headertitle">
+<div class="title">Generic Data Types and Definitions</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Data Type Definitions used by the CMSIS-RTOS API functions.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Event structure contains detailed information about an event.  <a href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">More...</a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q">os_mailQ</a></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions. </p>
+<hr/><h2>Data Structure Documentation</h2>
+<a name="structos_event" id="structos_event"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct osEvent</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>os_event</b> shall be consistent in every CMSIS-RTOS. However the struct may be extended at the end.</dd></dl>
+<p>The <b><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event" title="Event structure contains detailed information about an event.">osEvent</a></b> structure describes the events returned by CMSIS-RTOS functions. </p>
+</div><table class="memberdecls">
+<tr><td colspan="2"><h3>Data Fields</h3></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3">status</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">status code: event or error information  <a href="#ad477a289f1f03ac45407b64268d707d3"></a><br/></td></tr>
+<tr><td class="memItemLeft" >union {</td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc">v</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">message as 32-bit value  <a href="#a9e0a00edabf3b8a5dafff624fff7bbfc"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;void *&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709">p</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">message or mail as void pointer  <a href="#a117104b82864d3b23ec174af6d392709"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;int32_t&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6">signals</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">signal flags  <a href="#ad0dda1bf7e74f1576261d493fba232b6"></a><br/></td></tr>
+<tr><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f">value</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">event value  <a href="#a0b9f8fd3645f01d8cb09cae82add2d7f"></a><br/></td></tr>
+<tr><td class="memItemLeft" >union {</td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e">mail_id</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">mail id obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>  <a href="#ac86175a4b1706bee596f3018322df26e"></a><br/></td></tr>
+<tr><td class="memItemLeft" >&#160;&#160;&#160;<a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a>&#160;&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0">message_id</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">message id obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a>  <a href="#af394cbe21dde7377974e63af38cd87b0"></a><br/></td></tr>
+<tr><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6">def</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">event definition  <a href="#a596b6d55c3321db19239256bbe403df6"></a><br/></td></tr>
+</table>
+<hr/><h4>Field Documentation</h4>
+<a class="anchor" id="a596b6d55c3321db19239256bbe403df6"></a><!-- doxytag: member="osEvent::def" ref="a596b6d55c3321db19239256bbe403df6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">union { ... }   <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6">def</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ac86175a4b1706bee596f3018322df26e"></a><!-- doxytag: member="osEvent::mail_id" ref="ac86175a4b1706bee596f3018322df26e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e">mail_id</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af394cbe21dde7377974e63af38cd87b0"></a><!-- doxytag: member="osEvent::message_id" ref="af394cbe21dde7377974e63af38cd87b0" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0">message_id</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a117104b82864d3b23ec174af6d392709"></a><!-- doxytag: member="osEvent::p" ref="a117104b82864d3b23ec174af6d392709" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void* <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709">p</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ad0dda1bf7e74f1576261d493fba232b6"></a><!-- doxytag: member="osEvent::signals" ref="ad0dda1bf7e74f1576261d493fba232b6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6">signals</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ad477a289f1f03ac45407b64268d707d3"></a><!-- doxytag: member="osEvent::status" ref="ad477a289f1f03ac45407b64268d707d3" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3">status</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a9e0a00edabf3b8a5dafff624fff7bbfc"></a><!-- doxytag: member="osEvent::v" ref="a9e0a00edabf3b8a5dafff624fff7bbfc" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc">v</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a0b9f8fd3645f01d8cb09cae82add2d7f"></a><!-- doxytag: member="osEvent::value" ref="a0b9f8fd3645f01d8cb09cae82add2d7f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">union { ... }   <a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f">value</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+
+</div>
+</div>
+<!-- doxytag: class="osEvent" --><a name="structos__mail_q" id="structos__mail_q"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">struct os_mailQ</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<div class="textblock"><p>The <b><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event" title="Event structure contains detailed information about an event.">osEvent</a></b> structure describes the events returned by CMSIS-RTOS functions. </p>
+</div>
+</div>
+</div>
+<!-- doxytag: class="os_mailQ" --></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html
new file mode 100644
index 0000000..cd2f1e9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html
@@ -0,0 +1,284 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Kernel Information and Control</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
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+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Kernel Information and Control</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Provide version/system information and start the RTOS Kernel.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">osFeature_MainThread</a>&#160;&#160;&#160;1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">main thread 1=main can be thread, 0=not available  <a href="#ga22f7d235bc9f783933bd5a981fd79696"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1">osCMSIS</a>&#160;&#160;&#160;0x00003</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">API version (main [31:16] .sub [15:0])  <a href="#ga702196bacccbb978620c736b209387f1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de">osCMSIS_KERNEL</a>&#160;&#160;&#160;0x10000</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">RTOS identification and version (main [31:16] .sub [15:0])  <a href="#gab78dce646fabec479c5f34bc5175b7de"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289">osKernelSystemId</a>&#160;&#160;&#160;&quot;KERNEL V1.00&quot;</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">RTOS identification string.  <a href="#ga47cf03658f01cdffca688e9096b58289"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a> (<a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *thread_def, void *argument)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Start the RTOS Kernel with executing the specified thread.  <a href="#ga2865f10e5030a67d93424e32134881c8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5">osKernelRunning</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if the RTOS kernel is already started.  <a href="#ga3b571de44cd3094c643247a7397f86b5"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Kernel Information and Control function group allow to:</p>
+<ul>
+<li>obtain information about the system and the underlaying kernel.</li>
+<li>obtain version information about the CMSIS RTOS API.</li>
+<li>the start of the RTOS kernel.</li>
+<li>checking the execution status of the RTOS kernel.</li>
+</ul>
+<p>The function <b>main</b> is a special thread function that may be started at system initialization. In this case it has the initial priority <em>osPriorityNormal</em>. </p>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga702196bacccbb978620c736b209387f1"></a><!-- doxytag: member="cmsis_os.h::osCMSIS" ref="ga702196bacccbb978620c736b209387f1" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osCMSIS&#160;&#160;&#160;0x00003</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Version information of the CMSIS RTOS API whereby major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osCMSIS</b> identifies the CMSIS-RTOS API version </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab78dce646fabec479c5f34bc5175b7de"></a><!-- doxytag: member="cmsis_os.h::osCMSIS_KERNEL" ref="gab78dce646fabec479c5f34bc5175b7de" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osCMSIS_KERNEL&#160;&#160;&#160;0x10000</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Identifies the underlaying RTOS kernel and version number. The actual name of that define depends on the RTOS Kernel used in the implementation. For example, <b>osCMSIS_FreeRTOS</b> identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major verison is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>osCMSIS_KERNEL</b> identifies the underlaying RTOS kernel and version number. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga22f7d235bc9f783933bd5a981fd79696"></a><!-- doxytag: member="cmsis_os.h::osFeature_MainThread" ref="ga22f7d235bc9f783933bd5a981fd79696" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_MainThread&#160;&#160;&#160;1</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>A CMSIS-RTOS implementation may support to start thread execution with the function 'main'. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">osFeature_MainThread</a> is 1 the RTOS offers to start with 'main'. The RTOS kernel is in this case already started. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696">osFeature_MainThread</a> is 0 the RTOS requries explicit start with <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a>.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osFeature_xxx</b> shall be consistent in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga47cf03658f01cdffca688e9096b58289"></a><!-- doxytag: member="cmsis_os.h::osKernelSystemId" ref="ga47cf03658f01cdffca688e9096b58289" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osKernelSystemId&#160;&#160;&#160;&quot;KERNEL V1.00&quot;</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Defines a string that identifies the underlaying RTOS Kernel and provides version information. The lenght of that string is limited to 21 bytes. A valid indenification string is for example, <b>"FreeRTOS V1.00"</b>.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osKernelSystemId</b> shall be consistent in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga3b571de44cd3094c643247a7397f86b5"></a><!-- doxytag: member="cmsis_os.h::osKernelRunning" ref="ga3b571de44cd3094c643247a7397f86b5" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t osKernelRunning </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osKernelRunning</b> shall be consistent in every CMSIS-RTOS. </dd></dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>0 RTOS is not started, 1 RTOS is started.</dd></dl>
+<p>Identifies if the RTOS kernel is started. For systems with the option to start the 'main' function as a thread this allows to identify that the RTOS kernel is already running. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2865f10e5030a67d93424e32134881c8"></a><!-- doxytag: member="cmsis_os.h::osKernelStart" ref="ga2865f10e5030a67d93424e32134881c8" args="(osThreadDef_t *thread_def, void *argument)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void osKernelStart </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *&#160;</td>
+          <td class="paramname"><em>thread_def</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>argument</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_def</td><td>thread definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">osThread</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">argument</td><td>pointer that is passed to the thread function as start argument. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osKernelStart</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Start the RTOS Kernel and begin execution of the thread function specified by <em>thread_def</em>. The <em>argument</em> is passed to the thread function.</p>
+<p>When the CMSIS-RTOS starts thread execution with 'main', the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a> terminates this 'main; thread and starts execution with the specified thread function. This ensures that the code is portable regardless weather the function 'main' is started as thread or executed without control of the RTOS kernel.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The thread ID of the started thread can be obtained with the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </dd></dl>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
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+<!-- iframe showing the search results (closed by default) -->
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+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
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+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html
new file mode 100644
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--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html
@@ -0,0 +1,499 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Mail Queue Management</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+<script type="text/javascript">
+  initNavTree('group___c_m_s_i_s___r_t_o_s___mail.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Mail Queue Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Control, send, receive, or wait for mail.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a>&#160;&#160;&#160;1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Mail Queues: 1=available, 0=not available.  <a href="#gaceb2e0071ce160d153047f2eac1aca8e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b">osMailQDef</a>(name, queue_sz, type)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create a Mail Queue Definition.  <a href="#ga58d712b16c0c6668059f509386d1e55b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2">osMailQ</a>(name)&#160;&#160;&#160;&amp;os_mailQ_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Mail Queue Definition.  <a href="#gad2deeb66d51ade54e63d8f87ff2ec9d2"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a> (<a class="el" href="structos_mail_q_def__t.html">osMailQDef_t</a> *queue_def, <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create and Initialize mail queue.  <a href="#gae5313fdeb9b8a0791e2affb602a182f0"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">osMailAlloc</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Allocate a memory block from a mail.  <a href="#gadf5ce811bd6a56e617e902a1db6c2194"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">osMailCAlloc</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Allocate a memory block from a mail and set memory block to zero.  <a href="#ga8fde74f6fe5b9e88f75cc5eb8f2124fd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02">osMailPut</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, void *mail)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Put a mail to a queue.  <a href="#ga485ef6f81854ebda8ffbce4832181e02"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">osMailGet</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get a mail from a queue.  <a href="#gac6ad7e6e7d6c4a80e60da22c57a42ccd"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc">osMailFree</a> (<a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> queue_id, void *mail)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Free a memory block from a mail.  <a href="#ga27c1060cf21393f96b4fd1ed1c0167cc"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Mail Queue Management function group allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine.</p>
+<div class="image">
+<img src="MailQueue.png" alt="MailQueue.png"/>
+<div class="caption">
+CMSIS-RTOS Mail Queue</div></div>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="gaceb2e0071ce160d153047f2eac1aca8e"></a><!-- doxytag: member="cmsis_os.h::osFeature_MailQ" ref="gaceb2e0071ce160d153047f2eac1aca8e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_MailQ&#160;&#160;&#160;1</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>A CMSIS-RTOS implementation may support mail queues. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a> is 1 mail queues are supported. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a> is 0 no mail queues are supported. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad2deeb66d51ade54e63d8f87ff2ec9d2"></a><!-- doxytag: member="cmsis_os.h::osMailQ" ref="gad2deeb66d51ade54e63d8f87ff2ec9d2" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMailQ</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_mailQ_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access to the mail queue definition for the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the queue </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMailQ</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga58d712b16c0c6668059f509386d1e55b"></a><!-- doxytag: member="cmsis_os.h::osMailQDef" ref="ga58d712b16c0c6668059f509386d1e55b" args="(name, queue_sz, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMailQDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">queue_sz, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">type&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define the attributes of a mail queue that can by the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a> using <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2">osMailQ</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the queue </td></tr>
+    <tr><td class="paramname">queue_sz</td><td>maximum number of messages in queue </td></tr>
+    <tr><td class="paramname">type</td><td>data type of a single message element </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMailQDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gadf5ce811bd6a56e617e902a1db6c2194"></a><!-- doxytag: member="cmsis_os.h::osMailAlloc" ref="gadf5ce811bd6a56e617e902a1db6c2194" args="(osMailQId queue_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void * osMailAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>mail queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>pointer to memory block that can be filled with mail or NULL in case error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailAlloc</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Allocate a memory block from the mail queue that is filled with the mail information. When no memory block slot is available, the tread is put into the state <b>WAITING</b> for the time specified with <em>millisec</em>. When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an infinite time until a mail queue slot becomes available.</p>
+<p>A NULL pointer is returned when no memory slot can be obtained or <em>queue</em> specifies an illegal parameter.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The parameter <em>millisec</em> must be 0 for using this function in an ISR. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga8fde74f6fe5b9e88f75cc5eb8f2124fd"></a><!-- doxytag: member="cmsis_os.h::osMailCAlloc" ref="ga8fde74f6fe5b9e88f75cc5eb8f2124fd" args="(osMailQId queue_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void * osMailCAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>mail queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>pointer to memory block that can shall filled with mail or NULL in case error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailCAlloc</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Allocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared. When no memory block is available, the tread is put into the state <b>WAITING</b> for the time specified with <em>millisec</em>. When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an infinite time until a mail queue slot becomes available.</p>
+<p>A NULL pointer is returned when no memory block can be obtained or <em>queue</em> specifies an illegal parameter.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The parameter <em>millisec</em> must be 0 for using this function in an ISR. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae5313fdeb9b8a0791e2affb602a182f0"></a><!-- doxytag: member="cmsis_os.h::osMailCreate" ref="gae5313fdeb9b8a0791e2affb602a182f0" args="(osMailQDef_t *queue_def, osThreadId thread_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a> osMailCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_mail_q_def__t.html">osMailQDef_t</a> *&#160;</td>
+          <td class="paramname"><em>queue_def</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_def</td><td>reference to the mail queue definition obtain with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2">osMailQ</a> </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID (obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>) or NULL. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>mail queue ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Initialize and create a mail queue. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga27c1060cf21393f96b4fd1ed1c0167cc"></a><!-- doxytag: member="cmsis_os.h::osMailFree" ref="ga27c1060cf21393f96b4fd1ed1c0167cc" args="(osMailQId queue_id, void *mail)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osMailFree </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>mail</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>mail queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">mail</td><td>pointer to the memory block that was obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd">osMailGet</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailFree</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Free the memory block specified by <em>mail</em> and return it to the mail queue.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the <em>mail</em> block is released.</li>
+<li><em>osErrorValue:</em> <em>mail</em> block does not belong to the mail queue pool.</li>
+<li><em>osErrorParameter:</em> the value to the parameter <em>queue</em> is incorrect. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gac6ad7e6e7d6c4a80e60da22c57a42ccd"></a><!-- doxytag: member="cmsis_os.h::osMailGet" ref="gac6ad7e6e7d6c4a80e60da22c57a42ccd" args="(osMailQId queue_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> osMailGet </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>mail queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>event that contains mail information or error code. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailGet</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Suspend the execution of the current <b>RUNNING</b> thread until a mail arrives. When a mail is already in the queue, the function returns instantly with the mail information. When <em>millisec</em> is 0, the function returns instantly with status <b>osOK</b>. Otherwise the thread is put into the state <b>WAITING</b>. When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an infinite time until a mail arrives.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The parameter <em>millisec</em> must be 0 for using this function in an ISR.</dd></dl>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> no mail is available in the queue and no timeout was specified</li>
+<li><em>osEventTimeout:</em> no mail has arrived during the given timeout period.</li>
+<li><em>osEventMail:</em> mail received, <em>value.p</em> contains the pointer to mail content.</li>
+<li><em>osErrorParameter:</em> a parameter is invalid or outside of a permitted range. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="ga485ef6f81854ebda8ffbce4832181e02"></a><!-- doxytag: member="cmsis_os.h::osMailPut" ref="ga485ef6f81854ebda8ffbce4832181e02" args="(osMailQId queue_id, void *mail)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osMailPut </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5">osMailQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>mail</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>mail queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0">osMailCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">mail</td><td>memory block previously allocated with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194">osMailAlloc</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd">osMailCAlloc</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMailPut</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Put the memory block specified with <em>mail</em> into the mail queue specified by <em>queue</em>.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the message is put into the queue.</li>
+<li><em>osErrorValue:</em> <em>mail</em> was previously not allocated as memory slot.</li>
+<li><em>osErrorParameter:</em> a parameter is invalid or outside of a permitted range. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+ </div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html
new file mode 100644
index 0000000..7e383fa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html
@@ -0,0 +1,380 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Message Queue Management</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
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+<link href="navtree.css" rel="stylesheet" type="text/css"/>
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+</script>
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+<div id="top"><!-- do not remove this div! -->
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+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
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+          <img id="MSearchSelect" src="search/mag_sel.png"
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+               onfocus="searchBox.OnSearchFieldFocus(true)" 
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Message Queue Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Control, send, receive, or wait for messages.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203">osFeature_MessageQ</a>&#160;&#160;&#160;1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Message Queues: 1=available, 0=not available.  <a href="#ga479a6561f859e3d4818e25708593d203"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326">osMessageQDef</a>(name, queue_sz, type)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create a Message Queue Definition.  <a href="#gac9a6a6276c12609793e7701afcc82326"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97">osMessageQ</a>(name)&#160;&#160;&#160;&amp;os_messageQ_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Message Queue Definition.  <a href="#ga2d446a0b4bb90bf05d6f92eedeaabc97"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a> (<a class="el" href="structos_message_q_def__t.html">osMessageQDef_t</a> *queue_def, <a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create and Initialize a Message Queue.  <a href="#gad2d08f3d9250d19b045c83762b7b599f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d">osMessagePut</a> (<a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> queue_id, uint32_t info, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Put a Message to a Queue.  <a href="#gac0dcf462fc92de8ffaba6cc004514a6d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae">osMessageGet</a> (<a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> queue_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get a Message or Wait for a Message from a Queue.  <a href="#ga6c6892b8f2296cca6becd57ca2d7e1ae"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>Message Queue Management functions allow to control, send, receive, or wait for messages. A message can be an integer or pointer value that is send to a thread or interrupt service routine.</p>
+<div class="image">
+<img src="MessageQueue.png" alt="MessageQueue.png"/>
+<div class="caption">
+CMSIS-RTOS Message Queue</div></div>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga479a6561f859e3d4818e25708593d203"></a><!-- doxytag: member="cmsis_os.h::osFeature_MessageQ" ref="ga479a6561f859e3d4818e25708593d203" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_MessageQ&#160;&#160;&#160;1</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>A CMSIS-RTOS implementation may support message queues. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a> is 1 message queues are supported. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e">osFeature_MailQ</a> is 0 no message queues are supported. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2d446a0b4bb90bf05d6f92eedeaabc97"></a><!-- doxytag: member="cmsis_os.h::osMessageQ" ref="ga2d446a0b4bb90bf05d6f92eedeaabc97" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMessageQ</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_messageQ_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access to the message queue definition for the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the queue </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMessageQ</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac9a6a6276c12609793e7701afcc82326"></a><!-- doxytag: member="cmsis_os.h::osMessageQDef" ref="gac9a6a6276c12609793e7701afcc82326" args="(name, queue_sz, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMessageQDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">queue_sz, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">type&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define the attributes of a message queue created by the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a> using <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97">osMessageQ</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the queue. </td></tr>
+    <tr><td class="paramname">queue_sz</td><td>maximum number of messages in the queue. </td></tr>
+    <tr><td class="paramname">type</td><td>data type of a single message element (for debugger). </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMessageQDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gad2d08f3d9250d19b045c83762b7b599f"></a><!-- doxytag: member="cmsis_os.h::osMessageCreate" ref="gad2d08f3d9250d19b045c83762b7b599f" args="(osMessageQDef_t *queue_def, osThreadId thread_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a> osMessageCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_message_q_def__t.html">osMessageQDef_t</a> *&#160;</td>
+          <td class="paramname"><em>queue_def</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_def</td><td>queue definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97">osMessageQ</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID (obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>) or NULL. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>message queue ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMessageCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Create and initialize a message queue. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6c6892b8f2296cca6becd57ca2d7e1ae"></a><!-- doxytag: member="cmsis_os.h::osMessageGet" ref="ga6c6892b8f2296cca6becd57ca2d7e1ae" args="(osMessageQId queue_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> osMessageGet </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>message queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>event information that includes status code. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMessageGet</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Suspend the execution of the current <b>RUNNING</b> thread until a message arrives. When a message is already in the queue, the function returns instantly with the message information. When <em>millisec</em> is 0, the function returns instantly with status <b>osOK</b>. Otherwise the thread is put into the state <b>WAITING</b>. When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an infinite time until a message arrives.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The parameter <em>millisec</em> must be 0 for using this function in an ISR.</dd></dl>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> no message is available in the queue and no timeout was specified.</li>
+<li><em>osEventTimeout:</em> no message has arrived during the given timeout period.</li>
+<li><em>osEventMessage:</em> message received, <em>value.p</em> contains the pointer to message.</li>
+<li><em>osErrorParameter:</em> a parameter is invalid or outside of a permitted range. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gac0dcf462fc92de8ffaba6cc004514a6d"></a><!-- doxytag: member="cmsis_os.h::osMessagePut" ref="gac0dcf462fc92de8ffaba6cc004514a6d" args="(osMessageQId queue_id, uint32_t info, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osMessagePut </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f">osMessageQId</a>&#160;</td>
+          <td class="paramname"><em>queue_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>info</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">queue_id</td><td>message queue ID obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f">osMessageCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">info</td><td>message information. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMessagePut</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Put the message <em>info</em> in a message queue specified by <em>queue_id</em>. When the message queue is full, the system retry for a specified time with <em>millisec</em>. In this case, the tread is put into the state <b>WAITING</b>. When <em>millisec</em> is set to <b>osWaitForever</b>, the function will wait for an infinite time until a message queue slot becomes available.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>The parameter <em>millisec</em> must be 0 for using this function in an ISR.</dd></dl>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the message is put into the queue.</li>
+<li><em>osErrorResource:</em> no memory in the queue was available.</li>
+<li><em>osErrorTimeoutResource:</em> no memory in the queue was available during the given time limit.</li>
+<li><em>osErrorParameter:</em> a parameter is invalid or outside of a permitted range. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html
new file mode 100644
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--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html
@@ -0,0 +1,317 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Mutex Management</title>
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+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
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+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Mutex Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Synchronize thread execution with a Mutex.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3">osMutexDef</a>(name)&#160;&#160;&#160;<a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> os_mutex_def_##name = { 0 }</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Define a Mutex.  <a href="#ga9b522438489d7c402c95332b58bc94f3"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934">osMutex</a>(name)&#160;&#160;&#160;&amp;os_mutex_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Mutex defintion.  <a href="#ga1122a86faa64b4a0880c76cf68d0c934"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a> (<a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> *mutex_def)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create and Initialize a Mutex object.  <a href="#ga6356ddcf2e34ada892c57f13b284105e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a> (<a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> mutex_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait until a Mutex becomes available.  <a href="#ga5e1752b73f573ee015dbd9ef1edaba13"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">osMutexRelease</a> (<a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> mutex_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Release a Mutex that was obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a>.  <a href="#ga006e4744d741e8e132c3d5bbc295afe1"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Mutex Management function group is used to synchronize the execution of threads. This is for example used to protect access to a shared resource, for example a shared memory image.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>Mutex Management functions cannot be called from interrupt service routines (ISR).</dd></dl>
+<div class="image">
+<img src="Mutex.png" alt="Mutex.png"/>
+<div class="caption">
+CMSIS-RTOS Mutex</div></div>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga1122a86faa64b4a0880c76cf68d0c934"></a><!-- doxytag: member="cmsis_os.h::osMutex" ref="ga1122a86faa64b4a0880c76cf68d0c934" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMutex</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_mutex_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access to mutex object for the functions <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the mutex object. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMutex</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9b522438489d7c402c95332b58bc94f3"></a><!-- doxytag: member="cmsis_os.h::osMutexDef" ref="ga9b522438489d7c402c95332b58bc94f3" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osMutexDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;<a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> os_mutex_def_##name = { 0 }</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define a mutex object that is referenced by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934">osMutex</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the mutex object. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osMutexDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga6356ddcf2e34ada892c57f13b284105e"></a><!-- doxytag: member="cmsis_os.h::osMutexCreate" ref="ga6356ddcf2e34ada892c57f13b284105e" args="(osMutexDef_t *mutex_def)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a> osMutexCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_mutex_def__t.html">osMutexDef_t</a> *&#160;</td>
+          <td class="paramname"><em>mutex_def</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mutex_def</td><td>mutex definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934">osMutex</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>mutex ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMutexCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Create and initialize a Mutex object. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga006e4744d741e8e132c3d5bbc295afe1"></a><!-- doxytag: member="cmsis_os.h::osMutexRelease" ref="ga006e4744d741e8e132c3d5bbc295afe1" args="(osMutexId mutex_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osMutexRelease </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a>&#160;</td>
+          <td class="paramname"><em>mutex_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mutex_id</td><td>mutex ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMutexRelease</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Release a Mutex that was obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a>. Other threads that currently wait for the same mutex will be now put into the state <b>READY</b>.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the mutex has been correctly released.</li>
+<li><em>osErrorResource:</em> the mutex was not obtained before.</li>
+<li><em>osErrorParameter:</em> the parameter <em>mutex_id</em> is incorrect.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1">osMutexRelease</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="ga5e1752b73f573ee015dbd9ef1edaba13"></a><!-- doxytag: member="cmsis_os.h::osMutexWait" ref="ga5e1752b73f573ee015dbd9ef1edaba13" args="(osMutexId mutex_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osMutexWait </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2">osMutexId</a>&#160;</td>
+          <td class="paramname"><em>mutex_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mutex_id</td><td>mutex ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga6356ddcf2e34ada892c57f13b284105e">osMutexCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osMutexWait</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Wait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the mutex has been obtain.</li>
+<li><em>osErrorTimeoutResource:</em> the mutex could not be obtained in the given time.</li>
+<li><em>osErrorResource:</em> the mutex could not be obtained when no timeout was specified.</li>
+<li><em>osErrorParameter:</em> the parameter <em>mutex_id</em> is incorrect.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13">osMutexWait</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+</div>
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+  <div id="nav-path" class="navpath">
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+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group___c_m_s_i_s___r_t_o_s___pool_mgmt.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Memory Pool Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Define and manage fixed-size memory pools.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">osFeature_Pool</a>&#160;&#160;&#160;1</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory Pools: 1=available, 0=not available.  <a href="#gadd84b683001de327894851b428587caa"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b">osPoolDef</a>(name, no, type)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Define a Memory Pool.  <a href="#ga87b471d4fe2d5dbd0040708edd52771b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697">osPool</a>(name)&#160;&#160;&#160;&amp;os_pool_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Memory Pool definition.  <a href="#ga5f0b204a82327533d420210125c90697"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a> (<a class="el" href="structos_pool_def__t.html">osPoolDef_t</a> *pool_def)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create and Initialize a memory pool.  <a href="#ga2e265bdc4fcd4f001e34c9321be16d6f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543">osPoolAlloc</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Allocate a memory block from a memory pool.  <a href="#gaa0b2994f1a866c19e0d11e6e0d44f543"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a">osPoolCAlloc</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Allocate a memory block from a memory pool and set memory block to zero.  <a href="#ga9f129fcad4730fbd1048ad4fa262f36a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54">osPoolFree</a> (<a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> pool_id, void *block)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Return an allocated memory block back to a specific memory pool.  <a href="#ga4a861e9c469c9d0daf5721bf174f8e54"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Memory Pool Management function group is used to define and manage fixed-sized memory pools. </p>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="gadd84b683001de327894851b428587caa"></a><!-- doxytag: member="cmsis_os.h::osFeature_Pool" ref="gadd84b683001de327894851b428587caa" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_Pool&#160;&#160;&#160;1</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>A CMSIS-RTOS implementation may support fixed-size memory pools. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">osFeature_Pool</a> is 1 memory pools are supported. When the value <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa">osFeature_Pool</a> is 0 no memory pools are supported. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5f0b204a82327533d420210125c90697"></a><!-- doxytag: member="cmsis_os.h::osPool" ref="ga5f0b204a82327533d420210125c90697" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osPool</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_pool_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access a memory pool for the functions <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the memory pool </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osPool</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga87b471d4fe2d5dbd0040708edd52771b"></a><!-- doxytag: member="cmsis_os.h::osPoolDef" ref="ga87b471d4fe2d5dbd0040708edd52771b" args="(name, no, type)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osPoolDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">no, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">type&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define a memory pool that is referenced by <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697">osPool</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the memory pool. </td></tr>
+    <tr><td class="paramname">no</td><td>maximum number of objects (elements) in the memory pool. </td></tr>
+    <tr><td class="paramname">type</td><td>data type of a single object (element). </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osPoolDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gaa0b2994f1a866c19e0d11e6e0d44f543"></a><!-- doxytag: member="cmsis_os.h::osPoolAlloc" ref="gaa0b2994f1a866c19e0d11e6e0d44f543" args="(osPoolId pool_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void * osPoolAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a>&#160;</td>
+          <td class="paramname"><em>pool_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">pool_id</td><td>memory pool ID obtain referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>address of the allocated memory block or NULL in case of no memory available. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPoolAlloc</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Allocate a memory block from the memory pool. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9f129fcad4730fbd1048ad4fa262f36a"></a><!-- doxytag: member="cmsis_os.h::osPoolCAlloc" ref="ga9f129fcad4730fbd1048ad4fa262f36a" args="(osPoolId pool_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">void * osPoolCAlloc </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a>&#160;</td>
+          <td class="paramname"><em>pool_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">pool_id</td><td>memory pool ID obtain referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>address of the allocated memory block or NULL in case of no memory available. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPoolCAlloc</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Allocate a memory block from the memory pool. The block is initialized to zero. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2e265bdc4fcd4f001e34c9321be16d6f"></a><!-- doxytag: member="cmsis_os.h::osPoolCreate" ref="ga2e265bdc4fcd4f001e34c9321be16d6f" args="(osPoolDef_t *pool_def)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a> osPoolCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_pool_def__t.html">osPoolDef_t</a> *&#160;</td>
+          <td class="paramname"><em>pool_def</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">pool_def</td><td>memory pool definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697">osPool</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>memory pool ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPoolCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Create and initialize a memory pool. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4a861e9c469c9d0daf5721bf174f8e54"></a><!-- doxytag: member="cmsis_os.h::osPoolFree" ref="ga4a861e9c469c9d0daf5721bf174f8e54" args="(osPoolId pool_id, void *block)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osPoolFree </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686">osPoolId</a>&#160;</td>
+          <td class="paramname"><em>pool_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>block</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">pool_id</td><td>memory pool ID obtain referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f">osPoolCreate</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">block</td><td>address of the allocated memory block that is returned to the memory pool. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPoolFree</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Return a memory block to a memory pool.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the memory block is released.</li>
+<li><em>osErrorValue:</em> <em>block</em> does not belong to the memory pool.</li>
+<li><em>osErrorParameter:</em> a parameter is invalid or outside of a permitted range. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
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+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html
new file mode 100644
index 0000000..4a46700
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html
@@ -0,0 +1,335 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Semaphore Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Control access to shared resources.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a">osFeature_Semaphore</a>&#160;&#160;&#160;30</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">maximum count for SemaphoreInit function  <a href="#ga7da4c7bfb340779c9fc7b321f5ab3e3a"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b">osSemaphoreDef</a>(name)&#160;&#160;&#160;<a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> os_semaphore_def_##name = { 0 }</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Define a Semaphore object.  <a href="#ga9e66fe361749071e5ab87826c43c2f1b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>(name)&#160;&#160;&#160;&amp;os_semaphore_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Semaphore definition.  <a href="#ga03761ee8d2c3cd4544e18364ab301dac"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">osSemaphoreCreate</a> (<a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> *semaphore_def, int32_t count)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create and Initialize a Semaphore object used for managing resources.  <a href="#ga5ede9e5c5c3747cae928ff4f9d13e76d"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">osSemaphoreWait</a> (<a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> semaphore_id, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait until a Semaphore token becomes available.  <a href="#gacc15b0fc8ce1167fe43da33042e62098"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">osSemaphoreRelease</a> (<a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> semaphore_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Release a Semaphore token.  <a href="#gab108914997c49e14d8ff1ae0d1988ca0"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Semaphore Management function group is used to manage and protect access to shared resources. For example, with a Semaphore the access to a group of identical peripherals can be managed. The number of available resources is specified as parameter of the <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">osSemaphoreCreate</a> function.</p>
+<p>Each time a Semaphore token is obtained with <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098">osSemaphoreWait</a> the semaphore count is decremented. When the semaphore count is 0, no Semaphore token can be obtained. Semaphores are released with <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0">osSemaphoreRelease</a>; this function increments the semaphore count.</p>
+<div class="image">
+<img src="Semaphore.png" alt="Semaphore.png"/>
+<div class="caption">
+CMSIS-RTOS Semaphore</div></div>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga7da4c7bfb340779c9fc7b321f5ab3e3a"></a><!-- doxytag: member="cmsis_os.h::osFeature_Semaphore" ref="ga7da4c7bfb340779c9fc7b321f5ab3e3a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_Semaphore&#160;&#160;&#160;30</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>A CMSIS-RTOS implementation may support semaphores. The value <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a">osFeature_Semaphore</a> indicates the maximum index count for a semaphore. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga03761ee8d2c3cd4544e18364ab301dac"></a><!-- doxytag: member="cmsis_os.h::osSemaphore" ref="ga03761ee8d2c3cd4544e18364ab301dac" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osSemaphore</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_semaphore_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access to semaphore object for the functions <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d">osSemaphoreCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the semaphore object. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osSemaphore</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9e66fe361749071e5ab87826c43c2f1b"></a><!-- doxytag: member="cmsis_os.h::osSemaphoreDef" ref="ga9e66fe361749071e5ab87826c43c2f1b" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osSemaphoreDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;<a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> os_semaphore_def_##name = { 0 }</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define a semaphore object that is referenced by <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the semaphore object. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osSemaphoreDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga5ede9e5c5c3747cae928ff4f9d13e76d"></a><!-- doxytag: member="cmsis_os.h::osSemaphoreCreate" ref="ga5ede9e5c5c3747cae928ff4f9d13e76d" args="(osSemaphoreDef_t *semaphore_def, int32_t count)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a> osSemaphoreCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_semaphore_def__t.html">osSemaphoreDef_t</a> *&#160;</td>
+          <td class="paramname"><em>semaphore_def</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>count</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">semaphore_def</td><td>semaphore definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">count</td><td>number of available resources. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>semaphore ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSemaphoreCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Create and initialize a Semaphore object that is used to manage access to shared resources. The parameter <em>count</em> specifies the number of available resources. The <em>count</em> value 1 creates a binary semaphore. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab108914997c49e14d8ff1ae0d1988ca0"></a><!-- doxytag: member="cmsis_os.h::osSemaphoreRelease" ref="gab108914997c49e14d8ff1ae0d1988ca0" args="(osSemaphoreId semaphore_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osSemaphoreRelease </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a>&#160;</td>
+          <td class="paramname"><em>semaphore_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">semaphore_id</td><td>semaphore object referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSemaphoreRelease</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Release a Semaphore token. This increments the count of avaiable semaphore tokens.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>osSemaphoreRelease can be called also from interrupt service routines.</dd></dl>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the semaphore has been released.</li>
+<li><em>osErrorResource:</em> all tokens have already been released.</li>
+<li><em>osErrorParameter:</em> the parameter <em>semaphore_id</em> is incorrect. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gacc15b0fc8ce1167fe43da33042e62098"></a><!-- doxytag: member="cmsis_os.h::osSemaphoreWait" ref="gacc15b0fc8ce1167fe43da33042e62098" args="(osSemaphoreId semaphore_id, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t osSemaphoreWait </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84">osSemaphoreId</a>&#160;</td>
+          <td class="paramname"><em>semaphore_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">semaphore_id</td><td>semaphore object referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac">osSemaphore</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>number of available tokens, or -1 in case of incorrect parameters. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSemaphoreWait</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Wait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter <em>millisec</em>. When <em>millisec</em> is set to <b>osWaitForever</b>, the function will wait for an infinite time until a Semaphore token becomes available. The return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available. </p>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html
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+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
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+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Signal Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Control or wait for signal flags.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6">osFeature_Signals</a>&#160;&#160;&#160;8</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">maximum number of Signal Flags available per thread  <a href="#ga01edde265710d883b6e237d34a6ef4a6"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e">osSignalSet</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, int32_t signal)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the specified Signal Flags of an active thread.  <a href="#ga029340f7007656c06fdb8eeeae7b056e"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8">osSignalClear</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, int32_t signal)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the specified Signal Flags of an active thread.  <a href="#gafcb3a9bd9a3c4c99f2f86d5d33faffd8"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1">osSignalGet</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Signal Flags status of an active thread.  <a href="#ga071c0d1c3bdcac9e75fad0b25a5cd8f1"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">osSignalWait</a> (int32_t signals, uint32_t millisec)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait for one or more Signal Flags to become signaled for the current <b>RUNNING</b> thread.  <a href="#ga38860acda96df47da6923348d96fc4c9"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Signal Management function group allows to control or wait signal flags. Each thread has assigned signal flags. </p>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ga01edde265710d883b6e237d34a6ef4a6"></a><!-- doxytag: member="cmsis_os.h::osFeature_Signals" ref="ga01edde265710d883b6e237d34a6ef4a6" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osFeature_Signals&#160;&#160;&#160;8</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>The CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available per thread. The maximum value is 31 signal flags per thread. </p>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="gafcb3a9bd9a3c4c99f2f86d5d33faffd8"></a><!-- doxytag: member="cmsis_os.h::osSignalClear" ref="gafcb3a9bd9a3c4c99f2f86d5d33faffd8" args="(osThreadId thread_id, int32_t signal)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t osSignalClear </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>signals</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">signals</td><td>specifies the signal flags of the thread that shall be cleared. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSignalClear</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Clear the signal flags of an active thread. This function may be used also within interrupt service routines. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga071c0d1c3bdcac9e75fad0b25a5cd8f1"></a><!-- doxytag: member="cmsis_os.h::osSignalGet" ref="ga071c0d1c3bdcac9e75fad0b25a5cd8f1" args="(osThreadId thread_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t osSignalGet </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSignalGet</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Return the event flags of an active thread. This function may be used also within interrupt service routines. Signal flags that are returned are automatically cleared. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga029340f7007656c06fdb8eeeae7b056e"></a><!-- doxytag: member="cmsis_os.h::osSignalSet" ref="ga029340f7007656c06fdb8eeeae7b056e" args="(osThreadId thread_id, int32_t signal)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int32_t osSignalSet </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>signals</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">signals</td><td>specifies the signal flags of the thread that should be set. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSignalSet</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Set the signal flags of an active thread. This function may be used also within interrupt service routines. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga38860acda96df47da6923348d96fc4c9"></a><!-- doxytag: member="cmsis_os.h::osSignalWait" ref="ga38860acda96df47da6923348d96fc4c9" args="(int32_t signals, uint32_t millisec)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event">osEvent</a> osSignalWait </td>
+          <td>(</td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>signals</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>millisec</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">signals</td><td>wait until all specified signal flags set or 0 for any single signal flag. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">millisec</td><td>timeout value or 0 in case of no time-out. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>event flag information or error code. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osSignalWait</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Suspend the execution of the current <b>RUNNING</b> thread until all specified signal flags with the parameter <em>signals</em> are set. When this signal flags are already set, the function returns instantly. Otherwise the thread is put into the state <b>WAITING</b>. Signal flags that are reported as event are automatically cleared.</p>
+<p>When <em>millisec</em> is set to <b>osWaitForever</b> the function will wait for an inifinite time until a message queue slot becomes available.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> no signal received when the timeout value <em>millisec</em> was zero.</li>
+<li><em>osEventTimeout:</em> signal not occurred within timeout</li>
+<li><em>osEventSignal:</em> signal occurred, <em>value.signals</em> contains the signal flags; these signal flags are cleared.</li>
+<li><em>osErrorValue:</em> the value <em>signals</em> is outside of the permitted range.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9">osSignalWait</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
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new file mode 100644
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--- /dev/null
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+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
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+  initNavTree('group___c_m_s_i_s___r_t_o_s___status.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#enum-members">Enumerations</a>  </div>
+  <div class="headertitle">
+<div class="title">Status and Error Codes</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Status and Error Codes returned by CMSIS-RTOS API functions.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> { <br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f">osOK</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518">osEventSignal</a> =  0x08, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342">osEventMessage</a> =  0x10, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926">osEventMail</a> =  0x20, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177">osEventTimeout</a> =  0x40, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109">osErrorParameter</a> =  0x80, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d">osErrorResource</a> =  0x81, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467">osErrorTimeoutResource</a> =  0xC1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f">osErrorISR</a> =  0x82, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65">osErrorISRRecursive</a> =  0x83, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f">osErrorPriority</a> =  0x84, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81">osErrorNoMemory</a> =  0x85, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee">osErrorValue</a> =  0x86, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc">osErrorOS</a> =  0xFF, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1">os_status_reserved</a> =  0x7FFFFFFF
+<br/>
+ }</td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return. </p>
+<hr/><h2>Enumeration Type Documentation</h2>
+<a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99e"></a><!-- doxytag: member="cmsis_os.txt::osStatus" ref="gae2e091fefc4c767117727bd5aba4d99e" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osStatus</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>The <a class="el" href="cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e">osStatus</a> enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions. </p>
+<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f"></a><!-- doxytag: member="osOK" ref="gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f" args="" -->osOK</em>&nbsp;</td><td>
+<p>function completed; no event occurred. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518"></a><!-- doxytag: member="osEventSignal" ref="gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518" args="" -->osEventSignal</em>&nbsp;</td><td>
+<p>function completed; signal event occurred. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342"></a><!-- doxytag: member="osEventMessage" ref="gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342" args="" -->osEventMessage</em>&nbsp;</td><td>
+<p>function completed; message event occurred. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926"></a><!-- doxytag: member="osEventMail" ref="gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926" args="" -->osEventMail</em>&nbsp;</td><td>
+<p>function completed; mail event occurred. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177"></a><!-- doxytag: member="osEventTimeout" ref="gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177" args="" -->osEventTimeout</em>&nbsp;</td><td>
+<p>function completed; timeout occurred. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109"></a><!-- doxytag: member="osErrorParameter" ref="gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109" args="" -->osErrorParameter</em>&nbsp;</td><td>
+<p>parameter error: a mandatory parameter was missing or specified an incorrect object. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d"></a><!-- doxytag: member="osErrorResource" ref="gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d" args="" -->osErrorResource</em>&nbsp;</td><td>
+<p>resource not available: a specified resource was not available. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467"></a><!-- doxytag: member="osErrorTimeoutResource" ref="gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467" args="" -->osErrorTimeoutResource</em>&nbsp;</td><td>
+<p>resource not available within given time: a specified resource was not available within the timeout period. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f"></a><!-- doxytag: member="osErrorISR" ref="gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f" args="" -->osErrorISR</em>&nbsp;</td><td>
+<p>not allowed in ISR context: the function cannot be called from interrupt service routines. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65"></a><!-- doxytag: member="osErrorISRRecursive" ref="gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65" args="" -->osErrorISRRecursive</em>&nbsp;</td><td>
+<p>function called multiple times from ISR with same object. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f"></a><!-- doxytag: member="osErrorPriority" ref="gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f" args="" -->osErrorPriority</em>&nbsp;</td><td>
+<p>system cannot determine priority or thread has illegal priority. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81"></a><!-- doxytag: member="osErrorNoMemory" ref="gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81" args="" -->osErrorNoMemory</em>&nbsp;</td><td>
+<p>system is out of memory: it was impossible to allocate or reserve memory for the operation. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee"></a><!-- doxytag: member="osErrorValue" ref="gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee" args="" -->osErrorValue</em>&nbsp;</td><td>
+<p>value of a parameter is out of range. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc"></a><!-- doxytag: member="osErrorOS" ref="gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc" args="" -->osErrorOS</em>&nbsp;</td><td>
+<p>unspecified RTOS error: run-time error but no other error message fits. </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1"></a><!-- doxytag: member="os_status_reserved" ref="gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1" args="" -->os_status_reserved</em>&nbsp;</td><td>
+<p>prevent from enum down-size compiler optimization. </p>
+</td></tr>
+</table>
+</dd>
+</dl>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html
new file mode 100644
index 0000000..205640f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html
@@ -0,0 +1,511 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Thread Management</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
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+<link href="search/search.css" rel="stylesheet" type="text/css"/>
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+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
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+          <img id="MSearchSelect" src="search/mag_sel.png"
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+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
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+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+<div id="side-nav" class="ui-resizable side-nav-resizable">
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+       class="ui-resizable-handle">
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+<script type="text/javascript">
+  initNavTree('group___c_m_s_i_s___r_t_o_s___thread_mgmt.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Defines</a> &#124;
+<a href="#enum-members">Enumerations</a> &#124;
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">Thread Management</div>  </div>
+<div class="ingroups"><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a></div></div>
+<div class="contents">
+
+<p>Define, create, and control thread functions.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f">osThreadDef</a>(name, priority, instances, stacksz)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create a Thread Definition with function, priority, and stack requirements.  <a href="#gaee93d929beb350f16e5cc7fa602e229f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">osThread</a>(name)&#160;&#160;&#160;&amp;os_thread_def_##name</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Access a Thread defintion.  <a href="#gaf0c7c6b5e09f8be198312144b5c9e453"></a><br/></td></tr>
+<tr><td colspan="2"><h2><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> { <br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81">osPriorityIdle</a> =  -3, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4">osPriorityLow</a> =  -2, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6">osPriorityBelowNormal</a> =  -1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1">osPriorityNormal</a> =  0, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b">osPriorityAboveNormal</a> =  +1, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2">osPriorityHigh</a> =  +2, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af">osPriorityRealtime</a> =  +3, 
+<br/>
+&#160;&#160;<a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4">osPriorityError</a> =  0x84
+<br/>
+ }</td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> (<a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *thread_def, void *argument)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Create a thread and add it to Active Threads and set it to state READY.  <a href="#ga9e8ce62ab5f8c169d025af8c52e715db"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the thread ID of the current running thread.  <a href="#gab1df2a28925862ef8f9cf4e1c995c5a7"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Terminate execution of a thread and remove it from Active Threads.  <a href="#gaea135bb90eb853eff39e0800b91bbeab"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">osThreadSetPriority</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id, <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> priority)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Change priority of an active thread.  <a href="#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9">osThreadGetPriority</a> (<a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> thread_id)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Get current priority of an active thread.  <a href="#ga4299d838978bc2aae5e4350754e6a4e9"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> (void)</td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Pass control to next thread that is in state <b>READY</b>.  <a href="#gaf13a667493c5d629a90c13e113b99233"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>The Thread Management function group allow defining, creating, and controlling thread functions in the system. The function <b>main</b> is a special thread function that is started at system initialization and has the initial priority <em>osPriorityNormal</em>.</p>
+<p>Threads can be in the following states:</p>
+<ul>
+<li><b>RUNNING:</b> The thread that is currently running is in the <b>RUNNING</b> state. Only one thread at a time can be in this state.</li>
+<li><b>READY:</b> Threads which are ready to run are in the READY state. Once the <b>RUNNING</b> thread has terminated or is <b>WAITING</b> the next READY thread with the highest priority becomes the RUNNING thread.</li>
+<li><b>WAITING:</b> Threads that are waiting for an event to occur are in the <b>WAITING</b> state.</li>
+<li><b>INACTIVE:</b> Threads that are not created or terminated are in the <b>INACTIVE</b> state. These threads typically consume no system resources.</li>
+</ul>
+<div class="image">
+<img src="ThreadStatus.png" alt="ThreadStatus.png"/>
+<div class="caption">
+Thread State and State Transitions</div></div>
+<p> The CMSIS-RTOS assumes that threads are scheduled as shown in the figure <b>Thread State and State Transitions</b>. The thread states change as described below:</p>
+<ul>
+<li>A thread is created using the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a>. This puts the thread into the <b>READY</b> or <b>RUNNING</b> state (depending on the thread priority).</li>
+<li>CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the <b>RUNNING</b> thread provided it does not wait for any event. The initial priority of a thread is defined with the <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f">osThreadDef</a> but may be changed during execution using the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">osThreadSetPriority</a>.</li>
+<li>The <b>RUNNING</b> thread transfers into the <b>WAITING</b> state when it is waiting for an event.</li>
+<li>Active threads can be terminated any time using the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a>. Threads can terminate also by just returning from the thread function. Threads that are terminated are in the <b>INACTIVE</b> state and typically do not consume any dynamic memory resources. </li>
+</ul>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="gaf0c7c6b5e09f8be198312144b5c9e453"></a><!-- doxytag: member="cmsis_os.h::osThread" ref="gaf0c7c6b5e09f8be198312144b5c9e453" args="(name)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osThread</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name</td><td>)</td>
+          <td>&#160;&#160;&#160;&amp;os_thread_def_##name</td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Access to the thread definition for the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the thread definition object. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameter to <b>osThread</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaee93d929beb350f16e5cc7fa602e229f"></a><!-- doxytag: member="cmsis_os.h::osThreadDef" ref="gaee93d929beb350f16e5cc7fa602e229f" args="(name, priority, instances, stacksz)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define osThreadDef</td>
+          <td>(</td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">name, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">priority, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">instances, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">&#160;</td>
+          <td class="paramname">stacksz&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<p>Define the attributes of a thread functions that can be created by the function <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> using <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">osThread</a>.</p>
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramname">name</td><td>name of the thread function. </td></tr>
+    <tr><td class="paramname">priority</td><td>initial priority of the thread function. </td></tr>
+    <tr><td class="paramname">instances</td><td>number of possible thread instances. </td></tr>
+    <tr><td class="paramname">stacksz</td><td>stack size (in bytes) requirements for the thread function. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: The parameters to <b>osThreadDef</b> shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. </dd></dl>
+
+</div>
+</div>
+<hr/><h2>Enumeration Type Documentation</h2>
+<a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849a"></a><!-- doxytag: member="cmsis_os.txt::osPriority" ref="ga7f2b42f1983b9107775ec2a1c69a849a" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">enum <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osPriority</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>The <a class="el" href="cmsis__os_8h.html#a7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> value specifies the priority for a thread. The default thread priority should be <em>osPriorityNormal</em>. If a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately to execute the new task.</p>
+<p>To prevent from a priority inversion, a CMSIS-RTOS complained OS may optionally implement a <b>priority inheritance</b> method. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread with a lower priority. </p>
+<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81"></a><!-- doxytag: member="osPriorityIdle" ref="ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81" args="" -->osPriorityIdle</em>&nbsp;</td><td>
+<p>priority: idle (lowest) </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4"></a><!-- doxytag: member="osPriorityLow" ref="ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4" args="" -->osPriorityLow</em>&nbsp;</td><td>
+<p>priority: low </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6"></a><!-- doxytag: member="osPriorityBelowNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6" args="" -->osPriorityBelowNormal</em>&nbsp;</td><td>
+<p>priority: below normal </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1"></a><!-- doxytag: member="osPriorityNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1" args="" -->osPriorityNormal</em>&nbsp;</td><td>
+<p>priority: normal (default) </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b"></a><!-- doxytag: member="osPriorityAboveNormal" ref="ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b" args="" -->osPriorityAboveNormal</em>&nbsp;</td><td>
+<p>priority: above normal </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2"></a><!-- doxytag: member="osPriorityHigh" ref="ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2" args="" -->osPriorityHigh</em>&nbsp;</td><td>
+<p>priority: high </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af"></a><!-- doxytag: member="osPriorityRealtime" ref="ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af" args="" -->osPriorityRealtime</em>&nbsp;</td><td>
+<p>priority: realtime (highest) </p>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4"></a><!-- doxytag: member="osPriorityError" ref="ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4" args="" -->osPriorityError</em>&nbsp;</td><td>
+<p>system cannot determine priority or thread has illegal priority </p>
+</td></tr>
+</table>
+</dd>
+</dl>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ga9e8ce62ab5f8c169d025af8c52e715db"></a><!-- doxytag: member="cmsis_os.h::osThreadCreate" ref="ga9e8ce62ab5f8c169d025af8c52e715db" args="(osThreadDef_t *thread_def, void *argument)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> osThreadCreate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="structos_thread_def__t.html">osThreadDef_t</a> *&#160;</td>
+          <td class="paramname"><em>thread_def</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>argument</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_def</td><td>thread definition referenced with <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453">osThread</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">argument</td><td>pointer that is passed to the thread function as start argument. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>thread ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadCreate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Start a thread function by adding it to the Active Threads list and set it to state <b>READY</b>. The thread function receives the <em>argument</em> pointer as function argument when the function is started. When the priority of the created thread function is higher than the current <b>RUNNING</b> thread, the created thread function starts instantly and becomes the new <b>RUNNING</b> thread. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab1df2a28925862ef8f9cf4e1c995c5a7"></a><!-- doxytag: member="cmsis_os.h::osThreadGetId" ref="gab1df2a28925862ef8f9cf4e1c995c5a7" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a> osThreadGetId </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl class="return"><dt><b>Returns:</b></dt><dd>thread ID for reference by other functions or NULL in case of error. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadGetId</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Get the thread ID of the current running thread. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4299d838978bc2aae5e4350754e6a4e9"></a><!-- doxytag: member="cmsis_os.h::osThreadGetPriority" ref="ga4299d838978bc2aae5e4350754e6a4e9" args="(osThreadId thread_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a> osThreadGetPriority </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>current priority value of the thread function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadGetPriority</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Get the priority of an active thread. In case of a failure the value <b>osPriorityError</b> is returned. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga0dfb90ccf1f6e4b54b9251b12d1cbc8b"></a><!-- doxytag: member="cmsis_os.h::osThreadSetPriority" ref="ga0dfb90ccf1f6e4b54b9251b12d1cbc8b" args="(osThreadId thread_id, osPriority priority)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osThreadSetPriority </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype"><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a">osPriority</a>&#160;</td>
+          <td class="paramname"><em>priority</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>new priority value for the thread function. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadSetPriority</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Change the priority of an active thread.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the prioirty of the specified thread has been successfully changed.</li>
+<li><em>osErrorParameter:</em> thread_id is incorrect.</li>
+<li><em>osErrorValue:</em> incorrect priority value.</li>
+<li><em>osErrorResource:</em> thread_id refers to a thread that is not an active thread.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b">osThreadSetPriority</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gaea135bb90eb853eff39e0800b91bbeab"></a><!-- doxytag: member="cmsis_os.h::osThreadTerminate" ref="gaea135bb90eb853eff39e0800b91bbeab" args="(osThreadId thread_id)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osThreadTerminate </td>
+          <td>(</td>
+          <td class="paramtype"><a class="el" href="cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f">osThreadId</a>&#160;</td>
+          <td class="paramname"><em>thread_id</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Parameters:</b></dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">thread_id</td><td>thread ID obtained by <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db">osThreadCreate</a> or <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7">osThreadGetId</a>. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadTerminate</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Remove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.</p>
+<dl class="note"><dt><b>Note:</b></dt><dd>In case that <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a> terminates the currently running task, the function never returns and other threads that are in the READY state are started.</dd></dl>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the specified thread has been successfully terminated.</li>
+<li><em>osErrorParameter:</em> thread_id is incorrect.</li>
+<li><em>osErrorResource:</em> thread_id refers to a thread that is not an active thread.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab">osThreadTerminate</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+<a class="anchor" id="gaf13a667493c5d629a90c13e113b99233"></a><!-- doxytag: member="cmsis_os.h::osThreadYield" ref="gaf13a667493c5d629a90c13e113b99233" args="(void)" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e">osStatus</a> osThreadYield </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div>
+<div class="memdoc">
+<dl class="return"><dt><b>Returns:</b></dt><dd>status code that indicates the execution status of the function. </dd></dl>
+<dl class="note"><dt><b>Note:</b></dt><dd>MUST REMAIN UNCHANGED: <b>osThreadYield</b> shall be consistent in every CMSIS-RTOS.</dd></dl>
+<p>Pass control to next thread that is in state <b>READY</b>. If there is no other thread in the state <b>READY</b>, the current thread continues execution and no thread switching occurs.</p>
+<p><b><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></b><br/>
+</p>
+<ul>
+<li><em>osOK:</em> the function has been correctly executed.</li>
+<li><em>osErrorISR:</em> <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> cannot be called from interrupt service routines. </li>
+</ul>
+
+</div>
+</div>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+ </div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/index.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/index.html
new file mode 100644
index 0000000..8225cd5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/index.html
@@ -0,0 +1,199 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Overview</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
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+<script type="text/javascript">
+  initNavTree('index.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Overview </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The CMSIS-RTOS API is a generic RTOS interface for Cortex-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.</p>
+<ul>
+<li>CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).</li>
+<li>The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.</li>
+<li>Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.</li>
+<li>Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.</li>
+</ul>
+<dl class="note"><dt><b>Note:</b></dt><dd>The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.</dd></dl>
+<div class="image">
+<img src="API_Structure.png" alt="API_Structure.png"/>
+<div class="caption">
+CMSIS-RTOS API Structure</div></div>
+<p> A typical CMSIS-RTOS API implementation interfaces to an existing Real-Time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:</p>
+<ul>
+<li>Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.</li>
+</ul>
+<ul>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html">Thread Management</a> allows to define, create, and control threads.</li>
+</ul>
+<ul>
+<li>Interrupt Service Routines (ISR) can call many CMSIS-RTOS functions. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.</li>
+</ul>
+<ul>
+<li>Three different thread event types support communication between multiple threads and/or ISR:<ul>
+<li><b>Signals:</b> are flags that may be used to signal specific conditions to a thread. Signals can be modified in an ISR or set from other threads.</li>
+<li><b>Message:</b> is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.</li>
+<li><b>Mail:</b> is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.</li>
+</ul>
+</li>
+</ul>
+<ul>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html">Mutex Management</a> and <a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html">Semaphore Management</a> are incorporated.</li>
+</ul>
+<ul>
+<li>CPU time can be schedule with the following functionalities:<ul>
+<li>A <em>timeout</em> parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.</li>
+<li>The <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255">osDelay</a> function puts a thread into the state <b>WAITING</b> for a specified period of time.</li>
+<li>The generic <a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70">osWait</a> function waits for events that are assigned to a thread.</li>
+<li>The <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a> provides co-operative thread switching and passes execution to another thread of the same priority.</li>
+</ul>
+</li>
+</ul>
+<p>The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).</p>
+<p>In some RTOS implementations threads may execute on different processors and <b>Mail</b> and <b>Message</b> queues can therefore reside in shard memory resources.</p>
+<p>The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for example:</p>
+<ul>
+<li>Generic Wait function; i.e. with support of time intervals.</li>
+<li>Support of the Cortex-M Memory Protection Unit (MPU).</li>
+<li>Zero-copy mail queue.</li>
+<li>Support of multi-processor systems.</li>
+<li>Support of a DMA controller.</li>
+<li>Deterministic context switching.</li>
+<li>Round-robin context switching.</li>
+<li>Deadlock avoidance, for example with priority inversion.</li>
+<li>Zero interrupt latency by using the Cortex-M3/M4 instructions LDEX and STEX.</li>
+</ul>
+<hr/>
+<p>Revision History of CMSIS-RTOS API</p>
+<table  class="cmtable" summary="Core Exeption Name">
+<tr>
+<th>Version </th><th>Description  </th></tr>
+<tr>
+<td>V0.02 </td><td>Preview Release.  </td></tr>
+<tr>
+<td>V0.03 </td><td>Added: <a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8">osKernelStart</a>; starting 'main' as a thread is now an optional feature.<br/>
+ Semaphores have now the standard behavior.<br/>
+ <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89">osTimerCreate</a> does no longer start the timer. Added: <a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca">osTimerStart</a> (replaces osTimerRestart).<br/>
+ Changed: osThreadPass is renamed to <a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233">osThreadYield</a>.   </td></tr>
+</table>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Defines</a></div>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
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+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+   </ul>
+ </div>
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+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/jquery.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/jquery.js
new file mode 100644
index 0000000..c052173
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/jquery.js
@@ -0,0 +1,54 @@
+/*
+ * jQuery JavaScript Library v1.3.2
+ * http://jquery.com/
+ *
+ * Copyright (c) 2009 John Resig
+ * Dual licensed under the MIT and GPL licenses.
+ * http://docs.jquery.com/License
+ *
+ * Date: 2009-02-19 17:34:21 -0500 (Thu, 19 Feb 2009)
+ * Revision: 6246
+ */
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J=this[0],G=J.offsetParent,F=J,O=J.ownerDocument,M,H=O.documentElement,K=O.body,L=O.defaultView,E=L.getComputedStyle(J,null),N=J.offsetTop,I=J.offsetLeft;while((J=J.parentNode)&&J!==K&&J!==H){M=L.getComputedStyle(J,null);N-=J.scrollTop,I-=J.scrollLeft;if(J===G){N+=J.offsetTop,I+=J.offsetLeft;if(o.offset.doesNotAddBorder&&!(o.offset.doesAddBorderForTableAndCells&&/^t(able|d|h)$/i.test(J.tagName))){N+=parseInt(M.borderTopWidth,10)||0,I+=parseInt(M.borderLeftWidth,10)||0}F=G,G=J.offsetParent}if(o.offset.subtractsBorderForOverflowNotVisible&&M.overflow!=="visible"){N+=parseInt(M.borderTopWidth,10)||0,I+=parseInt(M.borderLeftWidth,10)||0}E=M}if(E.position==="relative"||E.position==="static"){N+=K.offsetTop,I+=K.offsetLeft}if(E.position==="fixed"){N+=Math.max(H.scrollTop,K.scrollTop),I+=Math.max(H.scrollLeft,K.scrollLeft)}return{top:N,left:I}}}o.offset={initialize:function(){if(this.initialized){return}var L=document.body,F=document.createElement("div"),H,G,N,I,M,E,J=L.style.marginTop,K='<div style="position:absolute;top:0;left:0;margin:0;border:5px solid #000;padding:0;width:1px;height:1px;"><div></div></div><table style="position:absolute;top:0;left:0;margin:0;border:5px solid #000;padding:0;width:1px;height:1px;" cellpadding="0" cellspacing="0"><tr><td></td></tr></table>';M={position:"absolute",top:0,left:0,margin:0,border:0,width:"1px",height:"1px",visibility:"hidden"};for(E in M){F.style[E]=M[E]}F.innerHTML=K;L.insertBefore(F,L.firstChild);H=F.firstChild,G=H.firstChild,I=H.nextSibling.firstChild.firstChild;this.doesNotAddBorder=(G.offsetTop!==5);this.doesAddBorderForTableAndCells=(I.offsetTop===5);H.style.overflow="hidden",H.style.position="relative";this.subtractsBorderForOverflowNotVisible=(G.offsetTop===-5);L.style.marginTop="1px";this.doesNotIncludeMarginInBodyOffset=(L.offsetTop===0);L.style.marginTop=J;L.removeChild(F);this.initialized=true},bodyOffset:function(E){o.offset.initialized||o.offset.initialize();var G=E.offsetTop,F=E.offsetLeft;if(o.offset.doesNotIncludeMarginInBodyOffset){G+=parseInt(o.curCSS(E,"marginTop",true),10)||0,F+=parseInt(o.curCSS(E,"marginLeft",true),10)||0}return{top:G,left:F}}};o.fn.extend({position:function(){var I=0,H=0,F;if(this[0]){var G=this.offsetParent(),J=this.offset(),E=/^body|html$/i.test(G[0].tagName)?{top:0,left:0}:G.offset();J.top-=j(this,"marginTop");J.left-=j(this,"marginLeft");E.top+=j(G,"borderTopWidth");E.left+=j(G,"borderLeftWidth");F={top:J.top-E.top,left:J.left-E.left}}return F},offsetParent:function(){var E=this[0].offsetParent||document.body;while(E&&(!/^body|html$/i.test(E.tagName)&&o.css(E,"position")=="static")){E=E.offsetParent}return o(E)}});o.each(["Left","Top"],function(F,E){var G="scroll"+E;o.fn[G]=function(H){if(!this[0]){return null}return H!==g?this.each(function(){this==l||this==document?l.scrollTo(!F?H:o(l).scrollLeft(),F?H:o(l).scrollTop()):this[G]=H}):this[0]==l||this[0]==document?self[F?"pageYOffset":"pageXOffset"]||o.boxModel&&document.documentElement[G]||document.body[G]:this[0][G]}});o.each(["Height","Width"],function(I,G){var E=I?"Left":"Top",H=I?"Right":"Bottom",F=G.toLowerCase();o.fn["inner"+G]=function(){return this[0]?o.css(this[0],F,false,"padding"):null};o.fn["outer"+G]=function(K){return this[0]?o.css(this[0],F,false,K?"margin":"border"):null};var J=G.toLowerCase();o.fn[J]=function(K){return this[0]==l?document.compatMode=="CSS1Compat"&&document.documentElement["client"+G]||document.body["client"+G]:this[0]==document?Math.max(document.documentElement["client"+G],document.body["scroll"+G],document.documentElement["scroll"+G],document.body["offset"+G],document.documentElement["offset"+G]):K===g?(this.length?o.css(this[0],J):null):this.css(J,typeof K==="string"?K:K+"px")}})})();
+/*
+ * jQuery UI 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI
+ */
+jQuery.ui||(function(c){var i=c.fn.remove,d=c.browser.mozilla&&(parseFloat(c.browser.version)<1.9);c.ui={version:"1.7.2",plugin:{add:function(k,l,n){var m=c.ui[k].prototype;for(var j in n){m.plugins[j]=m.plugins[j]||[];m.plugins[j].push([l,n[j]])}},call:function(j,l,k){var n=j.plugins[l];if(!n||!j.element[0].parentNode){return}for(var m=0;m<n.length;m++){if(j.options[n[m][0]]){n[m][1].apply(j.element,k)}}}},contains:function(k,j){return document.compareDocumentPosition?k.compareDocumentPosition(j)&16:k!==j&&k.contains(j)},hasScroll:function(m,k){if(c(m).css("overflow")=="hidden"){return false}var j=(k&&k=="left")?"scrollLeft":"scrollTop",l=false;if(m[j]>0){return true}m[j]=1;l=(m[j]>0);m[j]=0;return l},isOverAxis:function(k,j,l){return(k>j)&&(k<(j+l))},isOver:function(o,k,n,m,j,l){return c.ui.isOverAxis(o,n,j)&&c.ui.isOverAxis(k,m,l)},keyCode:{BACKSPACE:8,CAPS_LOCK:20,COMMA:188,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38}};if(d){var f=c.attr,e=c.fn.removeAttr,h="http://www.w3.org/2005/07/aaa",a=/^aria-/,b=/^wairole:/;c.attr=function(k,j,l){var m=l!==undefined;return(j=="role"?(m?f.call(this,k,j,"wairole:"+l):(f.apply(this,arguments)||"").replace(b,"")):(a.test(j)?(m?k.setAttributeNS(h,j.replace(a,"aaa:"),l):f.call(this,k,j.replace(a,"aaa:"))):f.apply(this,arguments)))};c.fn.removeAttr=function(j){return(a.test(j)?this.each(function(){this.removeAttributeNS(h,j.replace(a,""))}):e.call(this,j))}}c.fn.extend({remove:function(){c("*",this).add(this).each(function(){c(this).triggerHandler("remove")});return i.apply(this,arguments)},enableSelection:function(){return this.attr("unselectable","off").css("MozUserSelect","").unbind("selectstart.ui")},disableSelection:function(){return this.attr("unselectable","on").css("MozUserSelect","none").bind("selectstart.ui",function(){return false})},scrollParent:function(){var j;if((c.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){j=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(c.curCSS(this,"position",1))&&(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}else{j=this.parents().filter(function(){return(/(auto|scroll)/).test(c.curCSS(this,"overflow",1)+c.curCSS(this,"overflow-y",1)+c.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!j.length?c(document):j}});c.extend(c.expr[":"],{data:function(l,k,j){return !!c.data(l,j[3])},focusable:function(k){var l=k.nodeName.toLowerCase(),j=c.attr(k,"tabindex");return(/input|select|textarea|button|object/.test(l)?!k.disabled:"a"==l||"area"==l?k.href||!isNaN(j):!isNaN(j))&&!c(k)["area"==l?"parents":"closest"](":hidden").length},tabbable:function(k){var j=c.attr(k,"tabindex");return(isNaN(j)||j>=0)&&c(k).is(":focusable")}});function g(m,n,o,l){function k(q){var p=c[m][n][q]||[];return(typeof p=="string"?p.split(/,?\s+/):p)}var j=k("getter");if(l.length==1&&typeof l[0]=="string"){j=j.concat(k("getterSetter"))}return(c.inArray(o,j)!=-1)}c.widget=function(k,j){var l=k.split(".")[0];k=k.split(".")[1];c.fn[k]=function(p){var n=(typeof p=="string"),o=Array.prototype.slice.call(arguments,1);if(n&&p.substring(0,1)=="_"){return this}if(n&&g(l,k,p,o)){var m=c.data(this[0],k);return(m?m[p].apply(m,o):undefined)}return this.each(function(){var q=c.data(this,k);(!q&&!n&&c.data(this,k,new c[l][k](this,p))._init());(q&&n&&c.isFunction(q[p])&&q[p].apply(q,o))})};c[l]=c[l]||{};c[l][k]=function(o,n){var m=this;this.namespace=l;this.widgetName=k;this.widgetEventPrefix=c[l][k].eventPrefix||k;this.widgetBaseClass=l+"-"+k;this.options=c.extend({},c.widget.defaults,c[l][k].defaults,c.metadata&&c.metadata.get(o)[k],n);this.element=c(o).bind("setData."+k,function(q,p,r){if(q.target==o){return m._setData(p,r)}}).bind("getData."+k,function(q,p){if(q.target==o){return m._getData(p)}}).bind("remove",function(){return m.destroy()})};c[l][k].prototype=c.extend({},c.widget.prototype,j);c[l][k].getterSetter="option"};c.widget.prototype={_init:function(){},destroy:function(){this.element.removeData(this.widgetName).removeClass(this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").removeAttr("aria-disabled")},option:function(l,m){var k=l,j=this;if(typeof l=="string"){if(m===undefined){return this._getData(l)}k={};k[l]=m}c.each(k,function(n,o){j._setData(n,o)})},_getData:function(j){return this.options[j]},_setData:function(j,k){this.options[j]=k;if(j=="disabled"){this.element[k?"addClass":"removeClass"](this.widgetBaseClass+"-disabled "+this.namespace+"-state-disabled").attr("aria-disabled",k)}},enable:function(){this._setData("disabled",false)},disable:function(){this._setData("disabled",true)},_trigger:function(l,m,n){var p=this.options[l],j=(l==this.widgetEventPrefix?l:this.widgetEventPrefix+l);m=c.Event(m);m.type=j;if(m.originalEvent){for(var k=c.event.props.length,o;k;){o=c.event.props[--k];m[o]=m.originalEvent[o]}}this.element.trigger(m,n);return !(c.isFunction(p)&&p.call(this.element[0],m,n)===false||m.isDefaultPrevented())}};c.widget.defaults={disabled:false};c.ui.mouse={_mouseInit:function(){var j=this;this.element.bind("mousedown."+this.widgetName,function(k){return j._mouseDown(k)}).bind("click."+this.widgetName,function(k){if(j._preventClickEvent){j._preventClickEvent=false;k.stopImmediatePropagation();return false}});if(c.browser.msie){this._mouseUnselectable=this.element.attr("unselectable");this.element.attr("unselectable","on")}this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName);(c.browser.msie&&this.element.attr("unselectable",this._mouseUnselectable))},_mouseDown:function(l){l.originalEvent=l.originalEvent||{};if(l.originalEvent.mouseHandled){return}(this._mouseStarted&&this._mouseUp(l));this._mouseDownEvent=l;var k=this,m=(l.which==1),j=(typeof this.options.cancel=="string"?c(l.target).parents().add(l.target).filter(this.options.cancel).length:false);if(!m||j||!this._mouseCapture(l)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){k.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(l)&&this._mouseDelayMet(l)){this._mouseStarted=(this._mouseStart(l)!==false);if(!this._mouseStarted){l.preventDefault();return true}}this._mouseMoveDelegate=function(n){return k._mouseMove(n)};this._mouseUpDelegate=function(n){return k._mouseUp(n)};c(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);(c.browser.safari||l.preventDefault());l.originalEvent.mouseHandled=true;return true},_mouseMove:function(j){if(c.browser.msie&&!j.button){return this._mouseUp(j)}if(this._mouseStarted){this._mouseDrag(j);return j.preventDefault()}if(this._mouseDistanceMet(j)&&this._mouseDelayMet(j)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,j)!==false);(this._mouseStarted?this._mouseDrag(j):this._mouseUp(j))}return !this._mouseStarted},_mouseUp:function(j){c(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;this._preventClickEvent=(j.target==this._mouseDownEvent.target);this._mouseStop(j)}return false},_mouseDistanceMet:function(j){return(Math.max(Math.abs(this._mouseDownEvent.pageX-j.pageX),Math.abs(this._mouseDownEvent.pageY-j.pageY))>=this.options.distance)},_mouseDelayMet:function(j){return this.mouseDelayMet},_mouseStart:function(j){},_mouseDrag:function(j){},_mouseStop:function(j){},_mouseCapture:function(j){return true}};c.ui.mouse.defaults={cancel:null,distance:1,delay:0}})(jQuery);;/* * jQuery UI Resizable 1.7.2
+ *
+ * Copyright (c) 2009 AUTHORS.txt (http://jqueryui.com/about)
+ * Dual licensed under the MIT (MIT-LICENSE.txt)
+ * and GPL (GPL-LICENSE.txt) licenses.
+ *
+ * http://docs.jquery.com/UI/Resizables
+ *
+ * Depends:
+ *	ui.core.js
+ */
+(function(c){c.widget("ui.resizable",c.extend({},c.ui.mouse,{_init:function(){var e=this,j=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(j.aspectRatio),aspectRatio:j.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:j.helper||j.ghost||j.animate?j.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){if(/relative/.test(this.element.css("position"))&&c.browser.opera){this.element.css({position:"relative",top:"auto",left:"auto"})}this.element.wrap(c('<div class="ui-wrapper" style="overflow: hidden;"></div>').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=j.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var k=this.handles.split(",");this.handles={};for(var f=0;f<k.length;f++){var h=c.trim(k[f]),d="ui-resizable-"+h;var g=c('<div class="ui-resizable-handle '+d+'"></div>');if(/sw|se|ne|nw/.test(h)){g.css({zIndex:++j.zIndex})}if("se"==h){g.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[h]=".ui-resizable-"+h;this.element.append(g)}}this._renderAxis=function(p){p=p||this.element;for(var m in this.handles){if(this.handles[m].constructor==String){this.handles[m]=c(this.handles[m],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var n=c(this.handles[m],this.element),o=0;o=/sw|ne|nw|se|n|s/.test(m)?n.outerHeight():n.outerWidth();var l=["padding",/ne|nw|n/.test(m)?"Top":/se|sw|s/.test(m)?"Bottom":/^e$/.test(m)?"Right":"Left"].join("");p.css(l,o);this._proportionallyResize()}if(!c(this.handles[m]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!e.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}e.axis=i&&i[1]?i[1]:"se"}});if(j.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){c(this).removeClass("ui-resizable-autohide");e._handles.show()},function(){if(!e.resizing){c(this).addClass("ui-resizable-autohide");e._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var d=function(f){c(f).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){d(this.element);var e=this.element;e.parent().append(this.originalElement.css({position:e.css("position"),width:e.outerWidth(),height:e.outerHeight(),top:e.css("top"),left:e.css("left")})).end().remove()}this.originalElement.css("resize",this.originalResizeStyle);d(this.originalElement)},_mouseCapture:function(e){var f=false;for(var d in this.handles){if(c(this.handles[d])[0]==e.target){f=true}}return this.options.disabled||!!f},_mouseStart:function(f){var i=this.options,e=this.element.position(),d=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(d.is(".ui-draggable")||(/absolute/).test(d.css("position"))){d.css({position:"absolute",top:e.top,left:e.left})}if(c.browser.opera&&(/relative/).test(d.css("position"))){d.css({position:"relative",top:"auto",left:"auto"})}this._renderProxy();var j=b(this.helper.css("left")),g=b(this.helper.css("top"));if(i.containment){j+=c(i.containment).scrollLeft()||0;g+=c(i.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:j,top:g};this.size=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalSize=this._helper?{width:d.outerWidth(),height:d.outerHeight()}:{width:d.width(),height:d.height()};this.originalPosition={left:j,top:g};this.sizeDiff={width:d.outerWidth()-d.width(),height:d.outerHeight()-d.height()};this.originalMousePosition={left:f.pageX,top:f.pageY};this.aspectRatio=(typeof i.aspectRatio=="number")?i.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var h=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",h=="auto"?this.axis+"-resize":h);d.addClass("ui-resizable-resizing");this._propagate("start",f);return true},_mouseDrag:function(d){var g=this.helper,f=this.options,l={},p=this,i=this.originalMousePosition,m=this.axis;var q=(d.pageX-i.left)||0,n=(d.pageY-i.top)||0;var h=this._change[m];if(!h){return false}var k=h.apply(this,[d,q,n]),j=c.browser.msie&&c.browser.version<7,e=this.sizeDiff;if(this._aspectRatio||d.shiftKey){k=this._updateRatio(k,d)}k=this._respectSize(k,d);this._propagate("resize",d);g.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(k);this._trigger("resize",d,this.ui());return false},_mouseStop:function(g){this.resizing=false;var h=this.options,l=this;if(this._helper){var f=this._proportionallyResizeElements,d=f.length&&(/textarea/i).test(f[0].nodeName),e=d&&c.ui.hasScroll(f[0],"left")?0:l.sizeDiff.height,j=d?0:l.sizeDiff.width;var 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+{s.size.height=s.size.height+(s._helper?(s.position.top-n.top):s.position.top);if(q){s.size.width=s.size.height*h.aspectRatio}s.position.top=s._helper?n.top:0}s.offset.left=s.parentData.left+s.position.left;s.offset.top=s.parentData.top+s.position.top;var k=Math.abs((s._helper?s.offset.left-d.left:(s.offset.left-d.left))+s.sizeDiff.width),r=Math.abs((s._helper?s.offset.top-d.top:(s.offset.top-n.top))+s.sizeDiff.height);var j=s.containerElement.get(0)==s.element.parent().get(0),i=/relative|absolute/.test(s.containerElement.css("position"));if(j&&i){k-=s.parentData.left}if(k+s.size.width>=s.parentData.width){s.size.width=s.parentData.width-k;if(q){s.size.height=s.size.width/s.aspectRatio}}if(r+s.size.height>=s.parentData.height){s.size.height=s.parentData.height-r;if(q){s.size.width=s.size.height*s.aspectRatio}}},stop:function(e,m){var p=c(this).data("resizable"),f=p.options,k=p.position,l=p.containerOffset,d=p.containerPosition,g=p.containerElement;var i=c(p.helper),q=i.offset(),n=i.outerWidth()-p.sizeDiff.width,j=i.outerHeight()-p.sizeDiff.height;if(p._helper&&!f.animate&&(/relative/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}if(p._helper&&!f.animate&&(/static/).test(g.css("position"))){c(this).css({left:q.left-d.left-l.left,width:n,height:j})}}});c.ui.plugin.add("resizable","ghost",{start:function(f,g){var d=c(this).data("resizable"),h=d.options,e=d.size;d.ghost=d.originalElement.clone();d.ghost.css({opacity:0.25,display:"block",position:"relative",height:e.height,width:e.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof h.ghost=="string"?h.ghost:"");d.ghost.appendTo(d.helper)},resize:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost){d.ghost.css({position:"relative",height:d.size.height,width:d.size.width})}},stop:function(e,f){var d=c(this).data("resizable"),g=d.options;if(d.ghost&&d.helper){d.helper.get(0).removeChild(d.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(d,l){var n=c(this).data("resizable"),g=n.options,j=n.size,h=n.originalSize,i=n.originalPosition,m=n.axis,k=g._aspectRatio||d.shiftKey;g.grid=typeof g.grid=="number"?[g.grid,g.grid]:g.grid;var f=Math.round((j.width-h.width)/(g.grid[0]||1))*(g.grid[0]||1),e=Math.round((j.height-h.height)/(g.grid[1]||1))*(g.grid[1]||1);if(/^(se|s|e)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e}else{if(/^(ne)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e}else{if(/^(sw)$/.test(m)){n.size.width=h.width+f;n.size.height=h.height+e;n.position.left=i.left-f}else{n.size.width=h.width+f;n.size.height=h.height+e;n.position.top=i.top-e;n.position.left=i.left-f}}}}});var b=function(d){return parseInt(d,10)||0};var a=function(d){return !isNaN(parseInt(d,10))}})(jQuery);;
+/**
+ * jQuery.ScrollTo - Easy element scrolling using jQuery.
+ * Copyright (c) 2008 Ariel Flesler - aflesler(at)gmail(dot)com
+ * Licensed under GPL license (http://www.opensource.org/licenses/gpl-license.php).
+ * Date: 2/8/2008
+ * @author Ariel Flesler
+ * @version 1.3.2
+ */
+;(function($){var o=$.scrollTo=function(a,b,c){o.window().scrollTo(a,b,c)};o.defaults={axis:'y',duration:1};o.window=function(){return $($.browser.safari?'body':'html')};$.fn.scrollTo=function(l,m,n){if(typeof m=='object'){n=m;m=0}n=$.extend({},o.defaults,n);m=m||n.speed||n.duration;n.queue=n.queue&&n.axis.length>1;if(n.queue)m/=2;n.offset=j(n.offset);n.over=j(n.over);return this.each(function(){var a=this,b=$(a),t=l,c,d={},w=b.is('html,body');switch(typeof t){case'number':case'string':if(/^([+-]=)?\d+(px)?$/.test(t)){t=j(t);break}t=$(t,this);case'object':if(t.is||t.style)c=(t=$(t)).offset()}$.each(n.axis.split(''),function(i,f){var P=f=='x'?'Left':'Top',p=P.toLowerCase(),k='scroll'+P,e=a[k],D=f=='x'?'Width':'Height';if(c){d[k]=c[p]+(w?0:e-b.offset()[p]);if(n.margin){d[k]-=parseInt(t.css('margin'+P))||0;d[k]-=parseInt(t.css('border'+P+'Width'))||0}d[k]+=n.offset[p]||0;if(n.over[p])d[k]+=t[D.toLowerCase()]()*n.over[p]}else d[k]=t[p];if(/^\d+$/.test(d[k]))d[k]=d[k]<=0?0:Math.min(d[k],h(D));if(!i&&n.queue){if(e!=d[k])g(n.onAfterFirst);delete d[k]}});g(n.onAfter);function g(a){b.animate(d,m,n.easing,a&&function(){a.call(this,l)})};function h(D){var b=w?$.browser.opera?document.body:document.documentElement:a;return b['scroll'+D]-b['client'+D]}})};function j(a){return typeof a=='object'?a:{top:a,left:a}}})(jQuery);
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/modules.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/modules.html
new file mode 100644
index 0000000..d50acf2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/modules.html
@@ -0,0 +1,147 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li class="current"><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('modules.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Reference</div>  </div>
+</div>
+<div class="contents">
+<div class="textblock">Here is a list of all modules:</div><ul>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s.html">CMSIS-RTOS API</a><ul>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html">Kernel Information and Control</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___thread_mgmt.html">Thread Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___wait.html">Generic Wait Functions</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___timer_mgmt.html">Timer Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___signal_mgmt.html">Signal Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html">Mutex Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html">Semaphore Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___pool_mgmt.html">Memory Pool Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___message.html">Message Queue Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___mail.html">Mail Queue Management</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___definitions.html">Generic Data Types and Definitions</a></li>
+<li><a class="el" href="group___c_m_s_i_s___r_t_o_s___status.html">Status and Error Codes</a></li>
+</ul>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
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+        name="MSearchResults" id="MSearchResults">
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+</div>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/navtree.css
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+#nav-tree .children_ul {
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+}
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+}
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+  border:0px;
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+}
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+}
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+}
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+}
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+}
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+}
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+#nav-tree .item {
+  margin:0px;
+  padding:0px;
+}
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+#nav-tree {
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+  background-color: #FAFAFF; 
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+  overflow:auto;
+}
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+}
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+  margin: 6px 0px 0px 0px;
+}
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+#nav-tree {
+  background-image:url('nav_h.png');
+  background-repeat:repeat-x;
+  background-color: #F9FAFC;
+}
+
+
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/navtree.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/navtree.js
new file mode 100644
index 0000000..90d2882
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/navtree.js
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+var NAVTREE =
+[
+  [ "CMSIS-RTOS", "index.html", [
+    [ "Overview", "index.html", null ],
+    [ "Usage and Description", "pages.html", [
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+      [ "Function Overview", "_function_overview.html", null ],
+      [ "Header File Template: cmsis_os.h", "cmsis_os_h.html", null ]
+    ] ],
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+        [ "Generic Wait Functions", "group___c_m_s_i_s___r_t_o_s___wait.html", null ],
+        [ "Timer Management", "group___c_m_s_i_s___r_t_o_s___timer_mgmt.html", null ],
+        [ "Signal Management", "group___c_m_s_i_s___r_t_o_s___signal_mgmt.html", null ],
+        [ "Mutex Management", "group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html", null ],
+        [ "Semaphore Management", "group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html", null ],
+        [ "Memory Pool Management", "group___c_m_s_i_s___r_t_o_s___pool_mgmt.html", null ],
+        [ "Message Queue Management", "group___c_m_s_i_s___r_t_o_s___message.html", null ],
+        [ "Mail Queue Management", "group___c_m_s_i_s___r_t_o_s___mail.html", null ],
+        [ "Generic Data Types and Definitions", "group___c_m_s_i_s___r_t_o_s___definitions.html", null ],
+        [ "Status and Error Codes", "group___c_m_s_i_s___r_t_o_s___status.html", null ]
+      ] ]
+    ] ],
+    [ "Data Structures", "annotated.html", [
+      [ "os_mailQ", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q", null ],
+      [ "osEvent", "group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event", null ],
+      [ "osMailQDef_t", "structos_mail_q_def__t.html", null ],
+      [ "osMessageQDef_t", "structos_message_q_def__t.html", null ],
+      [ "osMutexDef_t", "structos_mutex_def__t.html", null ],
+      [ "osPoolDef_t", "structos_pool_def__t.html", null ],
+      [ "osSemaphoreDef_t", "structos_semaphore_def__t.html", null ],
+      [ "osThreadDef_t", "structos_thread_def__t.html", null ],
+      [ "osTimerDef_t", "structos_timer_def__t.html", null ]
+    ] ],
+    [ "Data Structure Index", "classes.html", null ],
+    [ "Data Fields", "functions.html", null ],
+    [ "Files", "files.html", [
+      [ "cmsis_os.h", "cmsis__os_8h.html", null ]
+    ] ],
+    [ "Index", "globals.html", null ]
+  ] ]
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+}
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+  node.relpath = po.relpath;
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+
+  node.li = document.createElement("li");
+  po.getChildrenUL().appendChild(node.li);
+  node.parentNode = po;
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+  node.itemDiv = document.createElement("div");
+  node.itemDiv.className = "item";
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+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
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+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
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+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
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+  } 
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+      a.onclick = node.expandToggle.onclick;
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+  node.childrenUL = null;
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+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
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+  return node;
+}
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+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
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+    {
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+    }
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+    node.expanded = true;
+  }
+}
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+function getNode(o, po)
+{
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+  var l = po.childrenData.length-1;
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+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
+      }
+    }
+  }
+  return null;
+}
+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
+  o.node.depth = 0;
+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
+
+  o.breadcrumbs = findNavTreePage(toroot, NAVTREE);
+  if (o.breadcrumbs == null)
+  {
+    o.breadcrumbs = findNavTreePage("index.html",NAVTREE);
+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
+    var p = o.node;
+    for (var i in o.breadcrumbs) 
+    {
+      var j = o.breadcrumbs[i];
+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/pages.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/pages.html
new file mode 100644
index 0000000..90c9d2c
--- /dev/null
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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Usage and Description</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
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+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
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+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
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+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
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+<div class="header">
+  <div class="headertitle">
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+<div class="textblock">Here is a list of all related documentation pages:</div><ul>
+<li><a class="el" href="_using_o_s.html">Using a CMSIS RTOS Implementation</a>
+</li>
+<li><a class="el" href="_function_overview.html">Function Overview</a>
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+<li><a class="el" href="cmsis_os_h.html">Header File Template: cmsis_os.h</a>
+</li>
+</ul>
+</div>
+</div>
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+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
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+   </ul>
+ </div>
+
+
+</body>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html
new file mode 100644
index 0000000..b71fac6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_63.html
@@ -0,0 +1,30 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_cmsis_5fos_2eh">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../cmsis__os_8h.html" target="_parent">cmsis_os.h</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_cmsis_5fos_2etxt">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../cmsis__os_8txt.html" target="_parent">cmsis_os.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html
new file mode 100644
index 0000000..17ea606
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_64.html
@@ -0,0 +1,35 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_def">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6" target="_parent">def</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_dummy">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_dummy')">dummy</a>
+  <div class="SRChildren">
+    <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca" target="_parent">osMutexDef_t::dummy()</a>
+    <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca" target="_parent">osSemaphoreDef_t::dummy()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html
new file mode 100644
index 0000000..a924b79
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_69.html
@@ -0,0 +1,36 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_instances">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603" target="_parent">instances</a>
+  <span class="SRScope">osThreadDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_item_5fsz">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_item_5fsz')">item_sz</a>
+  <div class="SRChildren">
+    <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osPoolDef_t::item_sz()</a>
+    <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osMessageQDef_t::item_sz()</a>
+    <a id="Item1_c2" onkeydown="return searchResults.NavChild(event,1,2)" onkeypress="return searchResults.NavChild(event,1,2)" onkeyup="return searchResults.NavChild(event,1,2)" class="SRScope" href="../structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f" target="_parent">osMailQDef_t::item_sz()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html
new file mode 100644
index 0000000..6a09242
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_6f.html
@@ -0,0 +1,662 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_os_5fmailq">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html" target="_parent">os_mailQ</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_os_5fpthread">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7" target="_parent">os_pthread</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_os_5fptimer">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065" target="_parent">os_ptimer</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_os_5fstatus_5freserved">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1" target="_parent">os_status_reserved</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_os_5ftimer_5ftype">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_os_5ftimer_5ftype')">os_timer_type</a>
+  <div class="SRChildren">
+    <a id="Item4_c0" onkeydown="return searchResults.NavChild(event,4,0)" onkeypress="return searchResults.NavChild(event,4,0)" onkeyup="return searchResults.NavChild(event,4,0)" class="SRScope" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9" target="_parent">os_timer_type():&#160;cmsis_os.txt</a>
+    <a id="Item4_c1" onkeydown="return searchResults.NavChild(event,4,1)" onkeypress="return searchResults.NavChild(event,4,1)" onkeyup="return searchResults.NavChild(event,4,1)" class="SRScope" href="../cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9" target="_parent">os_timer_type():&#160;cmsis_os.h</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_oscmsis">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1" target="_parent">osCMSIS</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oscmsis_5fkernel">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de" target="_parent">osCMSIS_KERNEL</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osdelay">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255" target="_parent">osDelay</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorisr">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f" target="_parent">osErrorISR</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorisrrecursive">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65" target="_parent">osErrorISRRecursive</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrornomemory">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81" target="_parent">osErrorNoMemory</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserroros">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc" target="_parent">osErrorOS</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorparameter">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109" target="_parent">osErrorParameter</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorpriority">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f" target="_parent">osErrorPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorresource">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d" target="_parent">osErrorResource</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrortimeoutresource">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467" target="_parent">osErrorTimeoutResource</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorvalue">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee" target="_parent">osErrorValue</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osevent">
+ <div class="SREntry">
+  <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html" target="_parent">osEvent</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventmail">
+ <div class="SREntry">
+  <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926" target="_parent">osEventMail</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventmessage">
+ <div class="SREntry">
+  <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342" target="_parent">osEventMessage</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventsignal">
+ <div class="SREntry">
+  <a id="Item20" onkeydown="return searchResults.Nav(event,20)" onkeypress="return searchResults.Nav(event,20)" onkeyup="return searchResults.Nav(event,20)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518" target="_parent">osEventSignal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventtimeout">
+ <div class="SREntry">
+  <a id="Item21" onkeydown="return searchResults.Nav(event,21)" onkeypress="return searchResults.Nav(event,21)" onkeyup="return searchResults.Nav(event,21)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177" target="_parent">osEventTimeout</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osfeature_5fmailq">
+ <div class="SREntry">
+  <a id="Item22" onkeydown="return searchResults.Nav(event,22)" onkeypress="return searchResults.Nav(event,22)" onkeyup="return searchResults.Nav(event,22)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e" target="_parent">osFeature_MailQ</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osfeature_5fmainthread">
+ <div class="SREntry">
+  <a id="Item23" onkeydown="return searchResults.Nav(event,23)" onkeypress="return searchResults.Nav(event,23)" onkeyup="return searchResults.Nav(event,23)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696" target="_parent">osFeature_MainThread</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osfeature_5fmessageq">
+ <div class="SREntry">
+  <a id="Item24" onkeydown="return searchResults.Nav(event,24)" onkeypress="return searchResults.Nav(event,24)" onkeyup="return searchResults.Nav(event,24)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203" target="_parent">osFeature_MessageQ</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
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+<div class="SRResult" id="SR_ospriorityhigh">
+ <div class="SREntry">
+  <a id="Item69" onkeydown="return searchResults.Nav(event,69)" onkeypress="return searchResults.Nav(event,69)" onkeyup="return searchResults.Nav(event,69)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2" target="_parent">osPriorityHigh</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityidle">
+ <div class="SREntry">
+  <a id="Item70" onkeydown="return searchResults.Nav(event,70)" onkeypress="return searchResults.Nav(event,70)" onkeyup="return searchResults.Nav(event,70)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81" target="_parent">osPriorityIdle</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osprioritylow">
+ <div class="SREntry">
+  <a id="Item71" onkeydown="return searchResults.Nav(event,71)" onkeypress="return searchResults.Nav(event,71)" onkeyup="return searchResults.Nav(event,71)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4" target="_parent">osPriorityLow</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osprioritynormal">
+ <div class="SREntry">
+  <a id="Item72" onkeydown="return searchResults.Nav(event,72)" onkeypress="return searchResults.Nav(event,72)" onkeyup="return searchResults.Nav(event,72)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1" target="_parent">osPriorityNormal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityrealtime">
+ <div class="SREntry">
+  <a id="Item73" onkeydown="return searchResults.Nav(event,73)" onkeypress="return searchResults.Nav(event,73)" onkeyup="return searchResults.Nav(event,73)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af" target="_parent">osPriorityRealtime</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphore">
+ <div class="SREntry">
+  <a id="Item74" onkeydown="return searchResults.Nav(event,74)" onkeypress="return searchResults.Nav(event,74)" onkeyup="return searchResults.Nav(event,74)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac" target="_parent">osSemaphore</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorecreate">
+ <div class="SREntry">
+  <a id="Item75" onkeydown="return searchResults.Nav(event,75)" onkeypress="return searchResults.Nav(event,75)" onkeyup="return searchResults.Nav(event,75)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d" target="_parent">osSemaphoreCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphoredef">
+ <div class="SREntry">
+  <a id="Item76" onkeydown="return searchResults.Nav(event,76)" onkeypress="return searchResults.Nav(event,76)" onkeyup="return searchResults.Nav(event,76)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b" target="_parent">osSemaphoreDef</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphoredef_5ft">
+ <div class="SREntry">
+  <a id="Item77" onkeydown="return searchResults.Nav(event,77)" onkeypress="return searchResults.Nav(event,77)" onkeyup="return searchResults.Nav(event,77)" class="SRSymbol" href="../structos_semaphore_def__t.html" target="_parent">osSemaphoreDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphoreid">
+ <div class="SREntry">
+  <a id="Item78" onkeydown="return searchResults.Nav(event,78)" onkeypress="return searchResults.Nav(event,78)" onkeyup="return searchResults.Nav(event,78)" class="SRSymbol" href="../cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84" target="_parent">osSemaphoreId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorerelease">
+ <div class="SREntry">
+  <a id="Item79" onkeydown="return searchResults.Nav(event,79)" onkeypress="return searchResults.Nav(event,79)" onkeyup="return searchResults.Nav(event,79)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0" target="_parent">osSemaphoreRelease</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorewait">
+ <div class="SREntry">
+  <a id="Item80" onkeydown="return searchResults.Nav(event,80)" onkeypress="return searchResults.Nav(event,80)" onkeyup="return searchResults.Nav(event,80)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098" target="_parent">osSemaphoreWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalclear">
+ <div class="SREntry">
+  <a id="Item81" onkeydown="return searchResults.Nav(event,81)" onkeypress="return searchResults.Nav(event,81)" onkeyup="return searchResults.Nav(event,81)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8" target="_parent">osSignalClear</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalget">
+ <div class="SREntry">
+  <a id="Item82" onkeydown="return searchResults.Nav(event,82)" onkeypress="return searchResults.Nav(event,82)" onkeyup="return searchResults.Nav(event,82)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1" target="_parent">osSignalGet</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalset">
+ <div class="SREntry">
+  <a id="Item83" onkeydown="return searchResults.Nav(event,83)" onkeypress="return searchResults.Nav(event,83)" onkeyup="return searchResults.Nav(event,83)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e" target="_parent">osSignalSet</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalwait">
+ <div class="SREntry">
+  <a id="Item84" onkeydown="return searchResults.Nav(event,84)" onkeypress="return searchResults.Nav(event,84)" onkeyup="return searchResults.Nav(event,84)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9" target="_parent">osSignalWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osstatus">
+ <div class="SREntry">
+  <a id="Item85" onkeydown="return searchResults.Nav(event,85)" onkeypress="return searchResults.Nav(event,85)" onkeyup="return searchResults.Nav(event,85)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_osstatus')">osStatus</a>
+  <div class="SRChildren">
+    <a id="Item85_c0" onkeydown="return searchResults.NavChild(event,85,0)" onkeypress="return searchResults.NavChild(event,85,0)" onkeyup="return searchResults.NavChild(event,85,0)" class="SRScope" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e" target="_parent">osStatus():&#160;cmsis_os.txt</a>
+    <a id="Item85_c1" onkeydown="return searchResults.NavChild(event,85,1)" onkeypress="return searchResults.NavChild(event,85,1)" onkeyup="return searchResults.NavChild(event,85,1)" class="SRScope" href="../cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e" target="_parent">osStatus():&#160;cmsis_os.h</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthread">
+ <div class="SREntry">
+  <a id="Item86" onkeydown="return searchResults.Nav(event,86)" onkeypress="return searchResults.Nav(event,86)" onkeyup="return searchResults.Nav(event,86)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453" target="_parent">osThread</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadcreate">
+ <div class="SREntry">
+  <a id="Item87" onkeydown="return searchResults.Nav(event,87)" onkeypress="return searchResults.Nav(event,87)" onkeyup="return searchResults.Nav(event,87)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db" target="_parent">osThreadCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreaddef">
+ <div class="SREntry">
+  <a id="Item88" onkeydown="return searchResults.Nav(event,88)" onkeypress="return searchResults.Nav(event,88)" onkeyup="return searchResults.Nav(event,88)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f" target="_parent">osThreadDef</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreaddef_5ft">
+ <div class="SREntry">
+  <a id="Item89" onkeydown="return searchResults.Nav(event,89)" onkeypress="return searchResults.Nav(event,89)" onkeyup="return searchResults.Nav(event,89)" class="SRSymbol" href="../structos_thread_def__t.html" target="_parent">osThreadDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadgetid">
+ <div class="SREntry">
+  <a id="Item90" onkeydown="return searchResults.Nav(event,90)" onkeypress="return searchResults.Nav(event,90)" onkeyup="return searchResults.Nav(event,90)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7" target="_parent">osThreadGetId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadgetpriority">
+ <div class="SREntry">
+  <a id="Item91" onkeydown="return searchResults.Nav(event,91)" onkeypress="return searchResults.Nav(event,91)" onkeyup="return searchResults.Nav(event,91)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9" target="_parent">osThreadGetPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadid">
+ <div class="SREntry">
+  <a id="Item92" onkeydown="return searchResults.Nav(event,92)" onkeypress="return searchResults.Nav(event,92)" onkeyup="return searchResults.Nav(event,92)" class="SRSymbol" href="../cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f" target="_parent">osThreadId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadsetpriority">
+ <div class="SREntry">
+  <a id="Item93" onkeydown="return searchResults.Nav(event,93)" onkeypress="return searchResults.Nav(event,93)" onkeyup="return searchResults.Nav(event,93)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b" target="_parent">osThreadSetPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadterminate">
+ <div class="SREntry">
+  <a id="Item94" onkeydown="return searchResults.Nav(event,94)" onkeypress="return searchResults.Nav(event,94)" onkeyup="return searchResults.Nav(event,94)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab" target="_parent">osThreadTerminate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadyield">
+ <div class="SREntry">
+  <a id="Item95" onkeydown="return searchResults.Nav(event,95)" onkeypress="return searchResults.Nav(event,95)" onkeyup="return searchResults.Nav(event,95)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233" target="_parent">osThreadYield</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimer">
+ <div class="SREntry">
+  <a id="Item96" onkeydown="return searchResults.Nav(event,96)" onkeypress="return searchResults.Nav(event,96)" onkeyup="return searchResults.Nav(event,96)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678" target="_parent">osTimer</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimercreate">
+ <div class="SREntry">
+  <a id="Item97" onkeydown="return searchResults.Nav(event,97)" onkeypress="return searchResults.Nav(event,97)" onkeyup="return searchResults.Nav(event,97)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89" target="_parent">osTimerCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerdef">
+ <div class="SREntry">
+  <a id="Item98" onkeydown="return searchResults.Nav(event,98)" onkeypress="return searchResults.Nav(event,98)" onkeyup="return searchResults.Nav(event,98)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492" target="_parent">osTimerDef</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerdef_5ft">
+ <div class="SREntry">
+  <a id="Item99" onkeydown="return searchResults.Nav(event,99)" onkeypress="return searchResults.Nav(event,99)" onkeyup="return searchResults.Nav(event,99)" class="SRSymbol" href="../structos_timer_def__t.html" target="_parent">osTimerDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerid">
+ <div class="SREntry">
+  <a id="Item100" onkeydown="return searchResults.Nav(event,100)" onkeypress="return searchResults.Nav(event,100)" onkeyup="return searchResults.Nav(event,100)" class="SRSymbol" href="../cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7" target="_parent">osTimerId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimeronce">
+ <div class="SREntry">
+  <a id="Item101" onkeydown="return searchResults.Nav(event,101)" onkeypress="return searchResults.Nav(event,101)" onkeyup="return searchResults.Nav(event,101)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951" target="_parent">osTimerOnce</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerperiodic">
+ <div class="SREntry">
+  <a id="Item102" onkeydown="return searchResults.Nav(event,102)" onkeypress="return searchResults.Nav(event,102)" onkeyup="return searchResults.Nav(event,102)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788" target="_parent">osTimerPeriodic</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerstart">
+ <div class="SREntry">
+  <a id="Item103" onkeydown="return searchResults.Nav(event,103)" onkeypress="return searchResults.Nav(event,103)" onkeyup="return searchResults.Nav(event,103)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca" target="_parent">osTimerStart</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerstop">
+ <div class="SREntry">
+  <a id="Item104" onkeydown="return searchResults.Nav(event,104)" onkeypress="return searchResults.Nav(event,104)" onkeyup="return searchResults.Nav(event,104)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091" target="_parent">osTimerStop</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oswait">
+ <div class="SREntry">
+  <a id="Item105" onkeydown="return searchResults.Nav(event,105)" onkeypress="return searchResults.Nav(event,105)" onkeyup="return searchResults.Nav(event,105)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70" target="_parent">osWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oswaitforever">
+ <div class="SREntry">
+  <a id="Item106" onkeydown="return searchResults.Nav(event,106)" onkeypress="return searchResults.Nav(event,106)" onkeyup="return searchResults.Nav(event,106)" class="SRSymbol" href="../cmsis__os_8h.html#a9eb9a7a797a42e4b55eb171ecc609ddb" target="_parent">osWaitForever</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html
new file mode 100644
index 0000000..760f336
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_70.html
@@ -0,0 +1,54 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_p">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709" target="_parent">p</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pool">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_pool')">pool</a>
+  <div class="SRChildren">
+    <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osPoolDef_t::pool()</a>
+    <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osMessageQDef_t::pool()</a>
+    <a id="Item1_c2" onkeydown="return searchResults.NavChild(event,1,2)" onkeypress="return searchResults.NavChild(event,1,2)" onkeyup="return searchResults.NavChild(event,1,2)" class="SRScope" href="../structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osMailQDef_t::pool()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_pool_5fsz">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763" target="_parent">pool_sz</a>
+  <span class="SRScope">osPoolDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pthread">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e" target="_parent">pthread</a>
+  <span class="SRScope">osThreadDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ptimer">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47" target="_parent">ptimer</a>
+  <span class="SRScope">osTimerDef_t</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html
new file mode 100644
index 0000000..9923f9a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_71.html
@@ -0,0 +1,29 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_queue_5fsz">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_queue_5fsz')">queue_sz</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0" target="_parent">osMessageQDef_t::queue_sz()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0" target="_parent">osMailQDef_t::queue_sz()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html
new file mode 100644
index 0000000..bcddb85
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_73.html
@@ -0,0 +1,38 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_signals">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6" target="_parent">signals</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_stacksize">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1" target="_parent">stacksize</a>
+  <span class="SRScope">osThreadDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_status">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3" target="_parent">status</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html
new file mode 100644
index 0000000..bd1c905
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_74.html
@@ -0,0 +1,26 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_tpriority">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7" target="_parent">tpriority</a>
+  <span class="SRScope">osThreadDef_t</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html
new file mode 100644
index 0000000..f0a5ee2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/all_76.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_v">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc" target="_parent">v</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_value">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f" target="_parent">value</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html
new file mode 100644
index 0000000..e5e385c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/classes_6f.html
@@ -0,0 +1,65 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_os_5fmailq">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html" target="_parent">os_mailQ</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osevent">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html" target="_parent">osEvent</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailqdef_5ft">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../structos_mail_q_def__t.html" target="_parent">osMailQDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmessageqdef_5ft">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../structos_message_q_def__t.html" target="_parent">osMessageQDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmutexdef_5ft">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../structos_mutex_def__t.html" target="_parent">osMutexDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospooldef_5ft">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../structos_pool_def__t.html" target="_parent">osPoolDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphoredef_5ft">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../structos_semaphore_def__t.html" target="_parent">osSemaphoreDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreaddef_5ft">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../structos_thread_def__t.html" target="_parent">osThreadDef_t</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerdef_5ft">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../structos_timer_def__t.html" target="_parent">osTimerDef_t</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/close.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/close.png
new file mode 100644
index 0000000..9342d3d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/close.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html
new file mode 100644
index 0000000..806ec82
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enums_6f.html
@@ -0,0 +1,47 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_os_5ftimer_5ftype">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_os_5ftimer_5ftype')">os_timer_type</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9" target="_parent">os_timer_type():&#160;cmsis_os.txt</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../cmsis__os_8h.html#adac860eb9e1b4b0619271e6595ed83d9" target="_parent">os_timer_type():&#160;cmsis_os.h</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriority">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_ospriority')">osPriority</a>
+  <div class="SRChildren">
+    <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a" target="_parent">osPriority():&#160;cmsis_os.txt</a>
+    <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../cmsis__os_8h.html#a7f2b42f1983b9107775ec2a1c69a849a" target="_parent">osPriority():&#160;cmsis_os.h</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_osstatus">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_osstatus')">osStatus</a>
+  <div class="SRChildren">
+    <a id="Item2_c0" onkeydown="return searchResults.NavChild(event,2,0)" onkeypress="return searchResults.NavChild(event,2,0)" onkeyup="return searchResults.NavChild(event,2,0)" class="SRScope" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e" target="_parent">osStatus():&#160;cmsis_os.txt</a>
+    <a id="Item2_c1" onkeydown="return searchResults.NavChild(event,2,1)" onkeypress="return searchResults.NavChild(event,2,1)" onkeyup="return searchResults.NavChild(event,2,1)" class="SRScope" href="../cmsis__os_8h.html#ae2e091fefc4c767117727bd5aba4d99e" target="_parent">osStatus():&#160;cmsis_os.h</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html
new file mode 100644
index 0000000..3929b4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/enumvalues_6f.html
@@ -0,0 +1,170 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_os_5fstatus_5freserved">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1" target="_parent">os_status_reserved</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorisr">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f" target="_parent">osErrorISR</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorisrrecursive">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65" target="_parent">osErrorISRRecursive</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrornomemory">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81" target="_parent">osErrorNoMemory</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserroros">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc" target="_parent">osErrorOS</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorparameter">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109" target="_parent">osErrorParameter</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorpriority">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f" target="_parent">osErrorPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorresource">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d" target="_parent">osErrorResource</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrortimeoutresource">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467" target="_parent">osErrorTimeoutResource</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oserrorvalue">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee" target="_parent">osErrorValue</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventmail">
+ <div class="SREntry">
+  <a id="Item10" onkeydown="return searchResults.Nav(event,10)" onkeypress="return searchResults.Nav(event,10)" onkeyup="return searchResults.Nav(event,10)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926" target="_parent">osEventMail</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventmessage">
+ <div class="SREntry">
+  <a id="Item11" onkeydown="return searchResults.Nav(event,11)" onkeypress="return searchResults.Nav(event,11)" onkeyup="return searchResults.Nav(event,11)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342" target="_parent">osEventMessage</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventsignal">
+ <div class="SREntry">
+  <a id="Item12" onkeydown="return searchResults.Nav(event,12)" onkeypress="return searchResults.Nav(event,12)" onkeyup="return searchResults.Nav(event,12)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518" target="_parent">osEventSignal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oseventtimeout">
+ <div class="SREntry">
+  <a id="Item13" onkeydown="return searchResults.Nav(event,13)" onkeypress="return searchResults.Nav(event,13)" onkeyup="return searchResults.Nav(event,13)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177" target="_parent">osEventTimeout</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osok">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f" target="_parent">osOK</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityabovenormal">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b" target="_parent">osPriorityAboveNormal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osprioritybelownormal">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6" target="_parent">osPriorityBelowNormal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityerror">
+ <div class="SREntry">
+  <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4" target="_parent">osPriorityError</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityhigh">
+ <div class="SREntry">
+  <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2" target="_parent">osPriorityHigh</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityidle">
+ <div class="SREntry">
+  <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81" target="_parent">osPriorityIdle</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osprioritylow">
+ <div class="SREntry">
+  <a id="Item20" onkeydown="return searchResults.Nav(event,20)" onkeypress="return searchResults.Nav(event,20)" onkeyup="return searchResults.Nav(event,20)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4" target="_parent">osPriorityLow</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osprioritynormal">
+ <div class="SREntry">
+  <a id="Item21" onkeydown="return searchResults.Nav(event,21)" onkeypress="return searchResults.Nav(event,21)" onkeyup="return searchResults.Nav(event,21)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1" target="_parent">osPriorityNormal</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospriorityrealtime">
+ <div class="SREntry">
+  <a id="Item22" onkeydown="return searchResults.Nav(event,22)" onkeypress="return searchResults.Nav(event,22)" onkeyup="return searchResults.Nav(event,22)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af" target="_parent">osPriorityRealtime</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimeronce">
+ <div class="SREntry">
+  <a id="Item23" onkeydown="return searchResults.Nav(event,23)" onkeypress="return searchResults.Nav(event,23)" onkeyup="return searchResults.Nav(event,23)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951" target="_parent">osTimerOnce</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerperiodic">
+ <div class="SREntry">
+  <a id="Item24" onkeydown="return searchResults.Nav(event,24)" onkeypress="return searchResults.Nav(event,24)" onkeyup="return searchResults.Nav(event,24)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788" target="_parent">osTimerPeriodic</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html
new file mode 100644
index 0000000..b71fac6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/files_63.html
@@ -0,0 +1,30 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_cmsis_5fos_2eh">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../cmsis__os_8h.html" target="_parent">cmsis_os.h</a>
+ </div>
+</div>
+<div class="SRResult" id="SR_cmsis_5fos_2etxt">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../cmsis__os_8txt.html" target="_parent">cmsis_os.txt</a>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html
new file mode 100644
index 0000000..59c72e0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/functions_6f.html
@@ -0,0 +1,236 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_osdelay">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255" target="_parent">osDelay</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oskernelrunning">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5" target="_parent">osKernelRunning</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oskernelstart">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga2865f10e5030a67d93424e32134881c8" target="_parent">osKernelStart</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailalloc">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194" target="_parent">osMailAlloc</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailcalloc">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd" target="_parent">osMailCAlloc</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailcreate">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#gae5313fdeb9b8a0791e2affb602a182f0" target="_parent">osMailCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailfree">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc" target="_parent">osMailFree</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailget">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd" target="_parent">osMailGet</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailput">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02" target="_parent">osMailPut</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmessagecreate">
+ <div class="SREntry">
+  <a id="Item9" onkeydown="return searchResults.Nav(event,9)" onkeypress="return searchResults.Nav(event,9)" onkeyup="return searchResults.Nav(event,9)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___message.html#gad2d08f3d9250d19b045c83762b7b599f" target="_parent">osMessageCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmessageget">
+ <div class="SREntry">
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+ </div>
+</div>
+<div class="SRResult" id="SR_osmessageput">
+ <div class="SREntry">
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+ </div>
+</div>
+<div class="SRResult" id="SR_osmutexcreate">
+ <div class="SREntry">
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+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmutexrelease">
+ <div class="SREntry">
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+</div>
+<div class="SRResult" id="SR_osmutexwait">
+ <div class="SREntry">
+  <a id="Item14" onkeydown="return searchResults.Nav(event,14)" onkeypress="return searchResults.Nav(event,14)" onkeyup="return searchResults.Nav(event,14)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13" target="_parent">osMutexWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospoolalloc">
+ <div class="SREntry">
+  <a id="Item15" onkeydown="return searchResults.Nav(event,15)" onkeypress="return searchResults.Nav(event,15)" onkeyup="return searchResults.Nav(event,15)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543" target="_parent">osPoolAlloc</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospoolcalloc">
+ <div class="SREntry">
+  <a id="Item16" onkeydown="return searchResults.Nav(event,16)" onkeypress="return searchResults.Nav(event,16)" onkeyup="return searchResults.Nav(event,16)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a" target="_parent">osPoolCAlloc</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospoolcreate">
+ <div class="SREntry">
+  <a id="Item17" onkeydown="return searchResults.Nav(event,17)" onkeypress="return searchResults.Nav(event,17)" onkeyup="return searchResults.Nav(event,17)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga2e265bdc4fcd4f001e34c9321be16d6f" target="_parent">osPoolCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospoolfree">
+ <div class="SREntry">
+  <a id="Item18" onkeydown="return searchResults.Nav(event,18)" onkeypress="return searchResults.Nav(event,18)" onkeyup="return searchResults.Nav(event,18)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54" target="_parent">osPoolFree</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorecreate">
+ <div class="SREntry">
+  <a id="Item19" onkeydown="return searchResults.Nav(event,19)" onkeypress="return searchResults.Nav(event,19)" onkeyup="return searchResults.Nav(event,19)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga5ede9e5c5c3747cae928ff4f9d13e76d" target="_parent">osSemaphoreCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorerelease">
+ <div class="SREntry">
+  <a id="Item20" onkeydown="return searchResults.Nav(event,20)" onkeypress="return searchResults.Nav(event,20)" onkeyup="return searchResults.Nav(event,20)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0" target="_parent">osSemaphoreRelease</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphorewait">
+ <div class="SREntry">
+  <a id="Item21" onkeydown="return searchResults.Nav(event,21)" onkeypress="return searchResults.Nav(event,21)" onkeyup="return searchResults.Nav(event,21)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098" target="_parent">osSemaphoreWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalclear">
+ <div class="SREntry">
+  <a id="Item22" onkeydown="return searchResults.Nav(event,22)" onkeypress="return searchResults.Nav(event,22)" onkeyup="return searchResults.Nav(event,22)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#gafcb3a9bd9a3c4c99f2f86d5d33faffd8" target="_parent">osSignalClear</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalget">
+ <div class="SREntry">
+  <a id="Item23" onkeydown="return searchResults.Nav(event,23)" onkeypress="return searchResults.Nav(event,23)" onkeyup="return searchResults.Nav(event,23)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga071c0d1c3bdcac9e75fad0b25a5cd8f1" target="_parent">osSignalGet</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalset">
+ <div class="SREntry">
+  <a id="Item24" onkeydown="return searchResults.Nav(event,24)" onkeypress="return searchResults.Nav(event,24)" onkeyup="return searchResults.Nav(event,24)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga029340f7007656c06fdb8eeeae7b056e" target="_parent">osSignalSet</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossignalwait">
+ <div class="SREntry">
+  <a id="Item25" onkeydown="return searchResults.Nav(event,25)" onkeypress="return searchResults.Nav(event,25)" onkeyup="return searchResults.Nav(event,25)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9" target="_parent">osSignalWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadcreate">
+ <div class="SREntry">
+  <a id="Item26" onkeydown="return searchResults.Nav(event,26)" onkeypress="return searchResults.Nav(event,26)" onkeyup="return searchResults.Nav(event,26)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga9e8ce62ab5f8c169d025af8c52e715db" target="_parent">osThreadCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadgetid">
+ <div class="SREntry">
+  <a id="Item27" onkeydown="return searchResults.Nav(event,27)" onkeypress="return searchResults.Nav(event,27)" onkeyup="return searchResults.Nav(event,27)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7" target="_parent">osThreadGetId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadgetpriority">
+ <div class="SREntry">
+  <a id="Item28" onkeydown="return searchResults.Nav(event,28)" onkeypress="return searchResults.Nav(event,28)" onkeyup="return searchResults.Nav(event,28)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9" target="_parent">osThreadGetPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadsetpriority">
+ <div class="SREntry">
+  <a id="Item29" onkeydown="return searchResults.Nav(event,29)" onkeypress="return searchResults.Nav(event,29)" onkeyup="return searchResults.Nav(event,29)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b" target="_parent">osThreadSetPriority</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadterminate">
+ <div class="SREntry">
+  <a id="Item30" onkeydown="return searchResults.Nav(event,30)" onkeypress="return searchResults.Nav(event,30)" onkeyup="return searchResults.Nav(event,30)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab" target="_parent">osThreadTerminate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadyield">
+ <div class="SREntry">
+  <a id="Item31" onkeydown="return searchResults.Nav(event,31)" onkeypress="return searchResults.Nav(event,31)" onkeyup="return searchResults.Nav(event,31)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233" target="_parent">osThreadYield</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimercreate">
+ <div class="SREntry">
+  <a id="Item32" onkeydown="return searchResults.Nav(event,32)" onkeypress="return searchResults.Nav(event,32)" onkeyup="return searchResults.Nav(event,32)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga12cbe501cd7f1aec940cfeb4d8c73c89" target="_parent">osTimerCreate</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerstart">
+ <div class="SREntry">
+  <a id="Item33" onkeydown="return searchResults.Nav(event,33)" onkeypress="return searchResults.Nav(event,33)" onkeyup="return searchResults.Nav(event,33)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca" target="_parent">osTimerStart</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerstop">
+ <div class="SREntry">
+  <a id="Item34" onkeydown="return searchResults.Nav(event,34)" onkeypress="return searchResults.Nav(event,34)" onkeyup="return searchResults.Nav(event,34)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091" target="_parent">osTimerStop</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_oswait">
+ <div class="SREntry">
+  <a id="Item35" onkeydown="return searchResults.Nav(event,35)" onkeypress="return searchResults.Nav(event,35)" onkeyup="return searchResults.Nav(event,35)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___wait.html#gaad5030efe48c1ae9902502e73873bc70" target="_parent">osWait</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/mag_sel.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/mag_sel.png
new file mode 100644
index 0000000..81f6040
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/mag_sel.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html
new file mode 100644
index 0000000..b1ded27
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/nomatches.html
@@ -0,0 +1,12 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="NoMatches">No Matches</div>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.css
new file mode 100644
index 0000000..1746d13
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 24px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 3px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
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+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.js
new file mode 100644
index 0000000..32e7118
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search.js
@@ -0,0 +1,742 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
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+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "typedefs",
+  6: "enums",
+  7: "enumvalues",
+  8: "defines"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i<search.length;i++)
+  {
+    var c = search.charAt(i);
+    var cn = c.charCodeAt(0);
+    if (c.match(/[a-z0-9]/))
+    {
+      result+=c;
+    }
+    else if (cn<16) 
+    {
+      result+="_0"+cn.toString(16);
+    }
+    else 
+    {
+      result+="_"+cn.toString(16);
+    }
+  }
+  return result;
+}
+
+function getXPos(item)
+{
+  var x = 0;
+  if (item.offsetWidth)
+  {
+    while (item && item!=document.body)
+    {
+      x   += item.offsetLeft;
+      item = item.offsetParent;
+    }
+  }
+  return x;
+}
+
+function getYPos(item)
+{
+  var y = 0;
+  if (item.offsetWidth)
+  {
+     while (item && item!=document.body)
+     {
+       y   += item.offsetTop;
+       item = item.offsetParent;
+     }
+  }
+  return y;
+}
+
+/* A class handling everything associated with the search panel.
+
+   Parameters:
+   name - The name of the global variable that will be 
+          storing this instance.  Is needed to be able to set timeouts.
+   resultPath - path to use for external files
+*/
+function SearchBox(name, resultsPath, inFrame, label)
+{
+  if (!name || !resultsPath) {  alert("Missing parameters to SearchBox."); }
+   
+  // ---------- Instance variables
+  this.name                  = name;
+  this.resultsPath           = resultsPath;
+  this.keyTimeout            = 0;
+  this.keyTimeoutLength      = 500;
+  this.closeSelectionTimeout = 300;
+  this.lastSearchValue       = "";
+  this.lastResultsPage       = "";
+  this.hideTimeout           = 0;
+  this.searchIndex           = 0;
+  this.searchActive          = false;
+  this.insideFrame           = inFrame;
+  this.searchLabel           = label;
+
+  // ----------- DOM Elements
+
+  this.DOMSearchField = function()
+  {  return document.getElementById("MSearchField");  }
+
+  this.DOMSearchSelect = function()
+  {  return document.getElementById("MSearchSelect");  }
+
+  this.DOMSearchSelectWindow = function()
+  {  return document.getElementById("MSearchSelectWindow");  }
+
+  this.DOMPopupSearchResults = function()
+  {  return document.getElementById("MSearchResults");  }
+
+  this.DOMPopupSearchResultsWindow = function()
+  {  return document.getElementById("MSearchResultsWindow");  }
+
+  this.DOMSearchClose = function()
+  {  return document.getElementById("MSearchClose"); }
+
+  this.DOMSearchBox = function()
+  {  return document.getElementById("MSearchBox");  }
+
+  // ------------ Event Handlers
+
+  // Called when focus is added or removed from the search field.
+  this.OnSearchFieldFocus = function(isActive)
+  {
+    this.Activate(isActive);
+  }
+
+  this.OnSearchSelectShow = function()
+  {
+    var searchSelectWindow = this.DOMSearchSelectWindow();
+    var searchField        = this.DOMSearchSelect();
+
+    if (this.insideFrame)
+    {
+      var left = getXPos(searchField);
+      var top  = getYPos(searchField);
+      left += searchField.offsetWidth + 6;
+      top += searchField.offsetHeight;
+
+      // show search selection popup
+      searchSelectWindow.style.display='block';
+      left -= searchSelectWindow.offsetWidth;
+      searchSelectWindow.style.left =  left + 'px';
+      searchSelectWindow.style.top  =  top  + 'px';
+    }
+    else
+    {
+      var left = getXPos(searchField);
+      var top  = getYPos(searchField);
+      top += searchField.offsetHeight;
+
+      // show search selection popup
+      searchSelectWindow.style.display='block';
+      searchSelectWindow.style.left =  left + 'px';
+      searchSelectWindow.style.top  =  top  + 'px';
+    }
+
+    // stop selection hide timer
+    if (this.hideTimeout) 
+    {
+      clearTimeout(this.hideTimeout);
+      this.hideTimeout=0;
+    }
+    return false; // to avoid "image drag" default event
+  }
+
+  this.OnSearchSelectHide = function()
+  {
+    this.hideTimeout = setTimeout(this.name +".CloseSelectionWindow()",
+                                  this.closeSelectionTimeout);
+  }
+
+  // Called when the content of the search field is changed.
+  this.OnSearchFieldChange = function(evt)
+  {
+    if (this.keyTimeout) // kill running timer
+    {
+      clearTimeout(this.keyTimeout);
+      this.keyTimeout = 0;
+    }
+
+    var e  = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 || e.keyCode==13)
+    {
+      if (e.shiftKey==1)
+      {
+        this.OnSearchSelectShow();
+        var win=this.DOMSearchSelectWindow(); 
+        for (i=0;i<win.childNodes.length;i++)
+        {
+          var child = win.childNodes[i]; // get span within a
+          if (child.className=='SelectItem')
+          {
+            child.focus();
+            return;
+          }
+        }
+        return;
+      }
+      else if (window.frames.MSearchResults.searchResults)
+      {
+        var elem = window.frames.MSearchResults.searchResults.NavNext(0);
+        if (elem) elem.focus();
+      }
+    }
+    else if (e.keyCode==27) // Escape out of the search field
+    {
+      this.DOMSearchField().blur();
+      this.DOMPopupSearchResultsWindow().style.display = 'none';
+      this.DOMSearchClose().style.display = 'none';
+      this.lastSearchValue = '';
+      this.Activate(false);
+      return;
+    }
+
+    // strip whitespaces
+    var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+
+    if (searchValue != this.lastSearchValue) // search value has changed
+    {
+      if (searchValue != "") // non-empty search
+      {
+        // set timer for search update
+        this.keyTimeout = setTimeout(this.name + '.Search()',
+                                     this.keyTimeoutLength);
+      }
+      else // empty search field
+      {
+        this.DOMPopupSearchResultsWindow().style.display = 'none';
+        this.DOMSearchClose().style.display = 'none';
+        this.lastSearchValue = '';
+      }
+    }
+  }
+
+  this.SelectItemCount = function(id)
+  {
+    var count=0;
+    var win=this.DOMSearchSelectWindow(); 
+    for (i=0;i<win.childNodes.length;i++)
+    {
+      var child = win.childNodes[i]; // get span within a
+      if (child.className=='SelectItem')
+      {
+        count++;
+      }
+    }
+    return count;
+  }
+
+  this.SelectItemSet = function(id)
+  {
+    var i,j=0;
+    var win=this.DOMSearchSelectWindow(); 
+    for (i=0;i<win.childNodes.length;i++)
+    {
+      var child = win.childNodes[i]; // get span within a
+      if (child.className=='SelectItem')
+      {
+        var node = child.firstChild;
+        if (j==id)
+        {
+          node.innerHTML='&#8226;';
+        }
+        else
+        {
+          node.innerHTML='&#160;';
+        }
+        j++;
+      }
+    }
+  }
+
+  // Called when an search filter selection is made.
+  // set item with index id as the active item
+  this.OnSelectItem = function(id)
+  {
+    this.searchIndex = id;
+    this.SelectItemSet(id);
+    var searchValue = this.DOMSearchField().value.replace(/ +/g, "");
+    if (searchValue!="" && this.searchActive) // something was found -> do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down
+    {
+      this.searchIndex++;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==38 && this.searchIndex>0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of <Search()>.
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_l.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_l.png
new file mode 100644
index 0000000..c872f4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_l.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_m.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_m.png
new file mode 100644
index 0000000..b429a16
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/search_m.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html
new file mode 100644
index 0000000..b1372ca
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/typedefs_6f.html
@@ -0,0 +1,74 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_os_5fpthread">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../cmsis__os_8h.html#aee631e5ea1b700fc35695cc7bc574cf7" target="_parent">os_pthread</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_os_5fptimer">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065" target="_parent">os_ptimer</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmailqid">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../cmsis__os_8h.html#a1dac049fb7725a8af8b26c71cbb373b5" target="_parent">osMailQId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmessageqid">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../cmsis__os_8h.html#ad9ec70c32c6c521970636b521e12d17f" target="_parent">osMessageQId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osmutexid">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../cmsis__os_8h.html#a3263c1ad9fd79b84f908d65e8da44ac2" target="_parent">osMutexId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ospoolid">
+ <div class="SREntry">
+  <a id="Item5" onkeydown="return searchResults.Nav(event,5)" onkeypress="return searchResults.Nav(event,5)" onkeyup="return searchResults.Nav(event,5)" class="SRSymbol" href="../cmsis__os_8h.html#a08d2e20fd9bbd96220fe068d420f3686" target="_parent">osPoolId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ossemaphoreid">
+ <div class="SREntry">
+  <a id="Item6" onkeydown="return searchResults.Nav(event,6)" onkeypress="return searchResults.Nav(event,6)" onkeyup="return searchResults.Nav(event,6)" class="SRSymbol" href="../cmsis__os_8h.html#aa8968896c84094aa973683c84fa06f84" target="_parent">osSemaphoreId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_osthreadid">
+ <div class="SREntry">
+  <a id="Item7" onkeydown="return searchResults.Nav(event,7)" onkeypress="return searchResults.Nav(event,7)" onkeyup="return searchResults.Nav(event,7)" class="SRSymbol" href="../cmsis__os_8h.html#adfeb153a84a81309e2d958268197617f" target="_parent">osThreadId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ostimerid">
+ <div class="SREntry">
+  <a id="Item8" onkeydown="return searchResults.Nav(event,8)" onkeypress="return searchResults.Nav(event,8)" onkeyup="return searchResults.Nav(event,8)" class="SRSymbol" href="../cmsis__os_8h.html#ab8530dd4273f1f5382187732e14fcaa7" target="_parent">osTimerId</a>
+  <span class="SRScope">cmsis_os.h</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html
new file mode 100644
index 0000000..68f4268
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_6d.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_mail_5fid">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e" target="_parent">mail_id</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_message_5fid">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0" target="_parent">message_id</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html
new file mode 100644
index 0000000..760f336
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_70.html
@@ -0,0 +1,54 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_p">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709" target="_parent">p</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pool">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_pool')">pool</a>
+  <div class="SRChildren">
+    <a id="Item1_c0" onkeydown="return searchResults.NavChild(event,1,0)" onkeypress="return searchResults.NavChild(event,1,0)" onkeyup="return searchResults.NavChild(event,1,0)" class="SRScope" href="../structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osPoolDef_t::pool()</a>
+    <a id="Item1_c1" onkeydown="return searchResults.NavChild(event,1,1)" onkeypress="return searchResults.NavChild(event,1,1)" onkeyup="return searchResults.NavChild(event,1,1)" class="SRScope" href="../structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osMessageQDef_t::pool()</a>
+    <a id="Item1_c2" onkeydown="return searchResults.NavChild(event,1,2)" onkeypress="return searchResults.NavChild(event,1,2)" onkeyup="return searchResults.NavChild(event,1,2)" class="SRScope" href="../structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c" target="_parent">osMailQDef_t::pool()</a>
+  </div>
+ </div>
+</div>
+<div class="SRResult" id="SR_pool_5fsz">
+ <div class="SREntry">
+  <a id="Item2" onkeydown="return searchResults.Nav(event,2)" onkeypress="return searchResults.Nav(event,2)" onkeyup="return searchResults.Nav(event,2)" class="SRSymbol" href="../structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763" target="_parent">pool_sz</a>
+  <span class="SRScope">osPoolDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_pthread">
+ <div class="SREntry">
+  <a id="Item3" onkeydown="return searchResults.Nav(event,3)" onkeypress="return searchResults.Nav(event,3)" onkeyup="return searchResults.Nav(event,3)" class="SRSymbol" href="../structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e" target="_parent">pthread</a>
+  <span class="SRScope">osThreadDef_t</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_ptimer">
+ <div class="SREntry">
+  <a id="Item4" onkeydown="return searchResults.Nav(event,4)" onkeypress="return searchResults.Nav(event,4)" onkeyup="return searchResults.Nav(event,4)" class="SRSymbol" href="../structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47" target="_parent">ptimer</a>
+  <span class="SRScope">osTimerDef_t</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html
new file mode 100644
index 0000000..9923f9a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_71.html
@@ -0,0 +1,29 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_queue_5fsz">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="javascript:searchResults.Toggle('SR_queue_5fsz')">queue_sz</a>
+  <div class="SRChildren">
+    <a id="Item0_c0" onkeydown="return searchResults.NavChild(event,0,0)" onkeypress="return searchResults.NavChild(event,0,0)" onkeyup="return searchResults.NavChild(event,0,0)" class="SRScope" href="../structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0" target="_parent">osMessageQDef_t::queue_sz()</a>
+    <a id="Item0_c1" onkeydown="return searchResults.NavChild(event,0,1)" onkeypress="return searchResults.NavChild(event,0,1)" onkeyup="return searchResults.NavChild(event,0,1)" class="SRScope" href="../structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0" target="_parent">osMailQDef_t::queue_sz()</a>
+  </div>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html
new file mode 100644
index 0000000..f0a5ee2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/search/variables_76.html
@@ -0,0 +1,32 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html><head><title></title>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<link rel="stylesheet" type="text/css" href="search.css"/>
+<script type="text/javascript" src="search.js"></script>
+</head>
+<body class="SRPage">
+<div id="SRIndex">
+<div class="SRStatus" id="Loading">Loading...</div>
+<div class="SRResult" id="SR_v">
+ <div class="SREntry">
+  <a id="Item0" onkeydown="return searchResults.Nav(event,0)" onkeypress="return searchResults.Nav(event,0)" onkeyup="return searchResults.Nav(event,0)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc" target="_parent">v</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRResult" id="SR_value">
+ <div class="SREntry">
+  <a id="Item1" onkeydown="return searchResults.Nav(event,1)" onkeypress="return searchResults.Nav(event,1)" onkeyup="return searchResults.Nav(event,1)" class="SRSymbol" href="../group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f" target="_parent">value</a>
+  <span class="SRScope">osEvent</span>
+ </div>
+</div>
+<div class="SRStatus" id="Searching">Searching...</div>
+<div class="SRStatus" id="NoMatches">No Matches</div>
+<script type="text/javascript"><!--
+document.getElementById("Loading").style.display="none";
+document.getElementById("NoMatches").style.display="none";
+var searchResults = new SearchResults("searchResults");
+searchResults.Search();
+--></script>
+</div>
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html
new file mode 100644
index 0000000..9e8b627
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html
@@ -0,0 +1,195 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>osMailQDef_t Struct Reference</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
+   </div>
+   <div id="projectbrief">CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+  <div id="navrow2" class="tabs2">
+    <ul class="tablist">
+      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
+      <li><a href="classes.html"><span>Data&#160;Structure&#160;Index</span></a></li>
+      <li><a href="functions.html"><span>Data&#160;Fields</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('structos_mail_q_def__t.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">osMailQDef_t Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="osMailQDef_t" -->
+<p>Definition structure for mail queue.  
+ <a href="structos_mail_q_def__t.html#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0">queue_sz</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">number of elements in the queue  <a href="#a8a83a3a8c0aa8057b13807d2a54077e0"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">item_sz</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">size of an item  <a href="#a4c2a0c691de3365c00ecd22d8102811f"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c">pool</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">memory array for mail  <a href="#a269c3935f8bc66db70bccdd02cb05e3c"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_mailQ_def</b> is implementation specific in every CMSIS-RTOS. </dd></dl>
+</div><hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a4c2a0c691de3365c00ecd22d8102811f"></a><!-- doxytag: member="osMailQDef_t::item_sz" ref="a4c2a0c691de3365c00ecd22d8102811f" args="" -->
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t <a class="el" href="structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f">item_sz</a></td>
+        </tr>
+      </table>
+</div>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html
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+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">osMessageQDef_t Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="osMessageQDef_t" -->
+<p>Definition structure for message queue.  
+ <a href="structos_message_q_def__t.html#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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+<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_messageQ_def</b> is implementation specific in every CMSIS-RTOS. </dd></dl>
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+<a class="anchor" id="a4c2a0c691de3365c00ecd22d8102811f"></a><!-- doxytag: member="osMessageQDef_t::item_sz" ref="a4c2a0c691de3365c00ecd22d8102811f" args="" -->
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html
new file mode 100644
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+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
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+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">osMutexDef_t Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="osMutexDef_t" -->
+<p>Mutex Definition structure contains setup information for a mutex.  
+ <a href="structos_mutex_def__t.html#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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+<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca">dummy</a></td></tr>
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+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_mutex_def</b> is implementation specific in every CMSIS-RTOS. </dd></dl>
+</div><hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a44b7a3baf02bac7ad707e8f2f5eca1ca"></a><!-- doxytag: member="osMutexDef_t::dummy" ref="a44b7a3baf02bac7ad707e8f2f5eca1ca" args="" -->
+<div class="memitem">
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+<div class="title">osSemaphoreDef_t Struct Reference</div>  </div>
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+<p>Semaphore Definition structure contains setup information for a semaphore.  
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html
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+   &#160;<span id="projectnumber">Version 1.00</span>
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+<a href="#pub-attribs">Data Fields</a>  </div>
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+<div class="title">osThreadDef_t Struct Reference</div>  </div>
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+<!-- doxytag: class="osThreadDef_t" -->
+<p>Thread Definition structure contains startup information of a thread.  
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+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
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+</table>
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+<title>osTimerDef_t Struct Reference</title>
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+   <div id="projectname">CMSIS-RTOS
+   &#160;<span id="projectnumber">Version 1.00</span>
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+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li class="current"><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#pub-attribs">Data Fields</a>  </div>
+  <div class="headertitle">
+<div class="title">osTimerDef_t Struct Reference</div>  </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="osTimerDef_t" -->
+<p>Timer Definition structure contains timer parameters.  
+ <a href="structos_timer_def__t.html#details">More...</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__os_8h.html#aa2d85e49bde9f6951ff3545cd323f065">os_ptimer</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47">ptimer</a></td></tr>
+<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">start address of a timer function  <a href="#a15773df83aba93f8e61f3737af5fae47"></a><br/></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<div class="textblock"><dl class="note"><dt><b>Note:</b></dt><dd>CAN BE CHANGED: <b>os_timer_def</b> is implementation specific in every CMSIS-RTOS. </dd></dl>
+</div><hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a15773df83aba93f8e61f3737af5fae47"></a><!-- doxytag: member="osTimerDef_t::ptimer" ref="a15773df83aba93f8e61f3737af5fae47" args="" -->
+<div class="memitem">
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+      <table class="memname">
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+        </tr>
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+
+</div>
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+    <ul>
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+    <li class="footer">Generated on Wed Mar 28 2012 15:38:10 for CMSIS-RTOS by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
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+<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @date: 07.12.2011
+  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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+ -->
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+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
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+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
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+  <xs:simpleType name="dimIndexType">
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+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
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+  <xs:simpleType name="scaledNonNegativeInteger">
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+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
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+  <xs:complexType name="writeConstraintType">
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+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
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+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
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+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
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+      <xs:element name="name" type="xs:string"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
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+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
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+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
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+  <xs:group name="bitRangeOffsetWidthStyle">
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+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
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+  <xs:element name="device" nillable="true">
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+        <xs:element name="name" type="xs:string"/>
+        <xs:element name="version" type="xs:string"/>
+        <xs:element name="description" type="xs:string"/>
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+        <xs:element name="peripherals">
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+              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+                <xs:complexType>
+                  <xs:sequence>
+                    <xs:element name="name" type="xs:Name"/>
+                    <xs:element name="version" type="xs:string" minOccurs="0"/>
+                    <xs:element name="description" type="xs:string" minOccurs="0"/>
+                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
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+                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
+                      <xs:complexType>
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+                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+                            <xs:complexType>
+                              <xs:sequence>
+                                <xs:group ref="dimElementGroup" minOccurs="0"/>
+                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+                                <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
+                                  <xs:complexType>
+                                    <xs:sequence>
+                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+                                      <xs:complexType>
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+                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
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+                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+                                          </xs:choice>
+                                          <xs:element name="access" type="accessType" minOccurs="0"/>
+                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+                                            <xs:complexType>
+                                              <xs:sequence>
+                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
+                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+                                                  <xs:complexType>
+                                                    <xs:sequence>
+                                                      <xs:element name="name" type="xs:string"/>
+                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                                      <xs:choice>
+                                                        <xs:element name="value" type="enumeratedValueDataType"/>
+                                                        <xs:element name="isDefault" type="xs:boolean"/>
+                                                      </xs:choice>
+                                                    </xs:sequence>
+                                                  </xs:complexType>
+                                                </xs:element>
+                                              </xs:sequence>
+                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                            </xs:complexType>
+                                          </xs:element>
+                                        </xs:sequence>
+                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                      </xs:complexType>
+                                    </xs:element>
+                                    </xs:sequence>
+                                  </xs:complexType>
+                                </xs:element>
+                              </xs:sequence>
+                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                            </xs:complexType>
+                          </xs:element>
+                        </xs:sequence>
+                      </xs:complexType>
+                    </xs:element>
+                  </xs:sequence>
+                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                </xs:complexType>
+              </xs:element>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png
new file mode 100644
index 0000000..2056b7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_Logo_Final.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png
new file mode 100644
index 0000000..d62f75b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_Vendor_DD.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png
new file mode 100644
index 0000000..1354448
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/CMSIS_SVD_WEB_DATABASE.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png
new file mode 100644
index 0000000..f14f62c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/Manage_SVD_DD.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/bc_s.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/bc_s.png
new file mode 100644
index 0000000..51ba006
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/bc_s.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/closed.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/closed.png
new file mode 100644
index 0000000..b7d4bd9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/closed.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/cmsis.css b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/cmsis.css
new file mode 100644
index 0000000..a5c4b8d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/cmsis.css
@@ -0,0 +1,957 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* CMSIS styles */
+
+.style1 {
+		text-align: center;
+}
+.style2 {
+		color: #0000FF;
+		font-weight: normal;
+}
+.style3 {
+		text-align: left;
+}
+.style4 {
+		color: #008000;
+}
+.style5 {
+		color: #0000FF;
+}
+.style6 {
+		color: #000000;
+		font-style:italic;
+}
+.mand {
+		color: #0000FF;
+}
+.opt {
+		color: #008000;
+}
+.cond {
+		color: #990000;
+}
+
+.choice 
+{
+	background-color:#F7F9D0;
+}
+.seq 
+{
+	background-color:#C9DECB;
+}
+.group1
+{
+	background-color:#F8F1F1;
+}
+.group2
+{
+	background-color:#DCEDEA;
+}
+
+
+ul ul {
+		list-style-type: disc;
+}
+
+ul ul ul {
+		list-style-type: disc;
+}
+
+ul.hierarchy {
+		color: green;
+}
+
+em {
+		color: #000000;
+		font-style:italic;
+}
+
+
+
+/*  CMSIS Tables */
+table.cmtab1 {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+	text-align: justify;
+	width:70%;
+}
+
+th.cmtab1 {
+	background: #EBEFF6;
+	font-weight: bold;
+	height: 28px;
+}
+
+td.cmtab1 {
+	padding:1px;
+	text-align: left;
+}
+
+table.cmtable {
+	border-collapse:collapse;
+	text-align: justify;
+}
+
+table.cmtable td, table.cmtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.cmtable th {
+	background-color: #EBEFF6;
+	border: 1px solid #2D4068;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+	height: 28px;
+}
+
+td.MonoTxt {
+	font-family:"Arial monospaced for SAP";
+}
+
+span.XML-Token 
+{
+	azimuth: 180;
+	font-style:italic;
+	color:Maroon;
+	z-index:20;
+	
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
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+        font-size: 8pt;
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+        background-repeat:repeat-x;
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/dynsections.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/dynsections.js
new file mode 100644
index 0000000..bf14807
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/dynsections.js
@@ -0,0 +1,42 @@
+var showTriggers = new Array();
+
+function registerShow(sectId,showFunc) {
+  showTriggers[sectId] = showFunc;
+}
+
+function hasClass(ele,cls) {
+  return ele.className.match(new RegExp('(\\s|^)'+cls+'(\\s|$)'));
+}
+
+function addClass(ele,cls) {
+  if (!this.hasClass(ele,cls)) ele.className += " "+cls;
+}
+
+function removeClass(ele,cls) {
+  if (hasClass(ele,cls)) {
+    var reg = new RegExp('(\\s|^)'+cls+'(\\s|$)');
+    ele.className=ele.className.replace(reg,' ');
+  }
+}
+
+function toggleVisibility(linkObj) {
+ var base = linkObj.getAttribute('id');
+ var summary = document.getElementById(base + '-summary');
+ var content = document.getElementById(base + '-content');
+ var trigger = document.getElementById(base + '-trigger');
+ if ( hasClass(linkObj,'closed') ) {
+   summary.style.display = 'none';
+   content.style.display = 'block';
+   trigger.src = trigger.src.substring(0,trigger.src.length-10)+'open.png';
+   removeClass(linkObj,'closed');
+   addClass(linkObj,'opened');
+   if (showTriggers[base]) { showTriggers[base](); }
+ } else if ( hasClass(linkObj,'opened') ) {
+   summary.style.display = 'block';
+   content.style.display = 'none';
+   trigger.src = trigger.src.substring(0,trigger.src.length-8)+'closed.png';
+   removeClass(linkObj,'opened');
+   addClass(linkObj,'closed');
+ }
+ return false;
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2blank.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2blank.png
new file mode 100644
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--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2blank.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2folderclosed.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2folderclosed.png
new file mode 100644
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2folderclosed.png
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new file mode 100644
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/ftv2mnode.png
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new file mode 100644
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new file mode 100644
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html
new file mode 100644
index 0000000..aee5b81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__cluster_level__gr.html
@@ -0,0 +1,182 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Cluster Level (New)</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__cluster_level__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Cluster Level (New)</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div>
+<div class="contents">
+<p><b>Cluster</b> adds a new and optional sub-level to the CMSIS SVD <em>registers</em> level. A cluster describes a sequence of registers within a peripheral. A cluster has an base offset relative to the base address of the peripheral. All registers within a cluster specify their address offset relative to the cluster base address. <em>Register</em> and <em>cluster</em> sections can occur in an arbitrary order. This feature, targeted at the generation of device header files, is useful to create a C data structure within the peripheral structure type, rather than describing all registers of a peripheral in a flat structure.</p>
+<hr/>
+<pre>
+<span class="mand"><b>&lt;registers&gt;</b> </span></pre><pre><span class="mand">    <b>&lt;cluster <span class="opt">derivedFrom=<em>identifierType</em></span>&gt;</b>
+    <span class="opt">
+        <em>&lt;!-- dimElementGroup --&gt; </em>
+        &lt;dim&gt;<em>scaledNonNegativeInteger</em>&lt;/dim&gt;
+        &lt;dimIncrement&gt;<em>scaledNonNegativeInteger</em>&lt;/dimIncrement&gt;
+        &lt;dimIndex&gt;<em>dimIndexType</em>&lt;/dimIndex&gt;
+        <em>&lt;!-- end of dimElementGroup --&gt; </em>
+    </span>
+        &lt;name&gt;<em>identifierType</em>&lt;/name&gt;
+        &lt;description&gt;<em>xs:string</em>&lt;/description&gt;
+    <span class="opt">
+        &lt;headerStructName&gt;<em>identifierType</em>&lt;/headerStructName&gt;
+        &lt;alternateCluster&gt;<em>identifierType</em>&lt;/alternateCluster&gt;
+    </span>
+        &lt;addressOffset&gt;<em>scaledNonNegativeInteger</em>&lt;/addressOffset&gt;</span></pre><pre><span class="mand">        &lt;register&gt;
+            ...
+        &lt;/register&gt;
+    <b>&lt;/cluster&gt;</b>
+    <span class="opt">...
+    &lt;register&gt;
+        ...
+    &lt;/register&gt;
+    &lt;cluster&gt;
+        ...
+    &lt;/cluster&gt;
+     </span>
+<b>&lt;registers&gt;</b> </span>
+</pre><table  class="cmtable" summary="Cluster Level Schema">
+<tr>
+<th>Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>derivedFrom </td><td>Specifies the name of the cluster from which to inherit the data. Elements being specified underneath will override the inherited values. <br/>
+<b>Remarks:</b> When deriving a cluster, it is mandatory to specify at least the name, the description, and the addressOffset. </td><td>registerType </td><td>0..1  </td></tr>
+<tr>
+<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr class="group1">
+<td colspan="4">See <a class="el" href="group__dim_element_group__gr.html">dimElementGroup</a> for details.  </td></tr>
+<tr class="group1">
+<td align="left">dimIncrement </td><td>The value defines the number of elements in an array of clusters.  </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr class="group1">
+<td align="left">dimIncrement </td><td>If <em>dim</em> is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring clusters of the cluster array in the address map. </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr class="group1">
+<td align="left">dimIndex </td><td>Specifies the substrings that replaces the <em>[%s]</em> placeholder within the cluster name. By default, the index is a decimal value starting with 0 for the first cluster element.  </td><td>dimIndexType  </td><td>0..1   </td></tr>
+<tr>
+<td>name </td><td>String that identifies the cluster. Register names are required to be unique within the scope of a peripheral. Specify <em>[%s]</em> for generating an array in the device header file. </td><td>identifierType  </td><td>1..1   </td></tr>
+<tr>
+<td>description </td><td>String describing the details of the register. </td><td>xs:string  </td><td>0..1   </td></tr>
+<tr>
+<td>alternateCluster  </td><td>This tag needs to specify the name of the original description of the register sequence if this cluster provides an alternative description. Otherwise the SVDConv will issue errors. </td><td>identifierType </td><td>0..1   </td></tr>
+<tr>
+<td>headerStructName  </td><td>This tag specifies the struct type name in the device header file. If not specified, then the name of the cluster will be used. </td><td>identifierType </td><td>0..1   </td></tr>
+<tr>
+<td>addressOffset </td><td>Value defining the cluster address relative to the <em>baseAddress</em> defined by the peripheral of the register. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+</table>
+<h2><a class="anchor" id="clusterSection_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">&lt;cluster&gt;
+    &lt;dim&gt;4&lt;/dim&gt;
+        &lt;dimIncrement&gt;8&lt;/dimIncrement&gt;
+        &lt;dimIndex&gt;0-3&lt;/dimIndex&gt;
+    &lt;name&gt;TX[%s]&lt;/name&gt;
+    &lt;description&gt;Grouping of Transfer data and address&lt;/description&gt;
+    &lt;addressOffset&gt;0x40&lt;/addressOffset&gt;
+    &lt;<span class="keyword">register</span>&gt;
+            &lt;name&gt;TX_DATA&lt;/name&gt;
+        ...
+            &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+        ...
+    &lt;/<span class="keyword">register</span>&gt;
+    &lt;<span class="keyword">register</span>&gt;
+            &lt;name&gt;TX_ADDR&lt;/name&gt;
+        ...
+            &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+        ...
+    &lt;/<span class="keyword">register</span>&gt;
+&lt;/cluster&gt;
+</pre></div><p>The example above describes an array of type TX with 4 elements. TX is a cluster of two consecutive registers with 4 elements. The device header file looks like this:</p>
+<div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct </span>{
+    ...
+    <span class="keyword">struct </span>{
+       __IO uint32_t  TX_DATA;
+       __IO uint32_t  TX_ADDR;
+    } TX[4];
+    ...
+} ..._Type;
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html
new file mode 100644
index 0000000..db637ac
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html
@@ -0,0 +1,125 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>dimElementGroup</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__dim_element_group__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">dimElementGroup</div>  </div>
+<div class="ingroups"><a class="el" href="group__elem__type__gr.html">Element Groups</a></div></div>
+<div class="contents">
+<p>The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the &lt;dim&gt; element. The register names can be composed by the register name and an index-specific substring defined in &lt;dimIndex&gt;. The &lt;dimIncrement&gt; specifies the address offset between two registers. The elements below can be used to generate an array of registers.</p>
+<table  class="cmtable" summary="dimElementGroup Description">
+<tr>
+<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>dim </td><td>The value defines the number of elements in an array of registers. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+<tr>
+<td>dimIncrement </td><td>If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+<tr>
+<td>dimIndex </td><td>Specifies the substrings that replaces the <em>s</em> placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. </td><td>dimIndexType </td><td>0..1   </td></tr>
+</table>
+<h2><a class="anchor" id="dimElementGroup_ex"></a>
+Examples:</h2>
+<div class="fragment"><pre class="fragment">...
+&lt;<span class="keyword">register</span>&gt;
+    &lt;dim&gt;6&lt;/dim&gt; 
+    &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; 
+    &lt;dimIndex&gt;A,B,C,D,E,Z&lt;/dimIndex&gt; 
+    &lt;name&gt;GPIO_%s_CTRL&lt;/name&gt; 
+...
+&lt;/<span class="keyword">register</span>&gt;
+</pre></div><p>The code above generates: =&gt; GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL</p>
+<div class="fragment"><pre class="fragment">...
+&lt;<span class="keyword">register</span>&gt;
+    &lt;dim&gt;4&lt;/dim&gt; 
+    &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; 
+    &lt;dimIndex&gt;3-6&lt;/dimIndex&gt; 
+    &lt;name&gt;IRQ%s&lt;/name&gt; 
+...
+&lt;/<span class="keyword">register</span>&gt;
+</pre></div><p>The example above generates: =&gt; IRQ3, IRQ4, IRQ5, IRQ6 </p>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html
new file mode 100644
index 0000000..94dc75e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html
@@ -0,0 +1,121 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Extensions to the Peripheral Section</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__peripheral_section_extensions__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Extensions to the Peripheral Section</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div>
+<div class="contents">
+<p>The following elements have been added to the peripheral section. All new elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.</p>
+<table  class="cmtable" summary="Peripheral Section Extension Elements">
+<tr>
+<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>alternatePeripheral </td><td>All address blocks in the memory space of a device are assigned to a unique peripheral by default. If there are multiple peripherals describing the same address blocks, this needs to be specified explicitly. A peripheral redefining an address block needs to specify the name of the peripheral that is listed first in the description. If no alternate peripheral is specified, then the <em>SVDConv</em> utility will generate errors. </td><td>identifierType  </td><td>0..1   </td></tr>
+<tr>
+<td>headerStructName </td><td>The header file generator uses the name of a peripheral as the base name for the C structure type. If this element is specfied, then this string is used instead of the peripheral name. This is particularly useful when multiple peripherals get derived from a peripheral description and a generic type name shall be used. </td><td>identifierType  </td><td>0..1   </td></tr>
+</table>
+<h2><a class="anchor" id="periperalSectionExtensions_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">&lt;peripheral&gt;
+  &lt;name&gt;Timer1&lt;/name&gt;
+  &lt;version&gt;1.0&lt;/version&gt;
+  &lt;description&gt;Timer 1 is a standard timer ... &lt;/description&gt;
+  &lt;baseAddress&gt;0x40002000&lt;/baseAddress&gt;
+  ...
+&lt;/peripheral&gt;
+&lt;peripheral&gt;
+  &lt;name&gt;Timer1_Alt&lt;/name&gt;
+  &lt;version&gt;1.0&lt;/version&gt;
+  &lt;description&gt;Alternate Timer 1 is a special timer execution mode ... &lt;/description&gt;
+  &lt;baseAddress&gt;0x40002000&lt;/baseAddress&gt;
+  &lt;alternatePeripheral&gt;Timer1&lt;/alternatePeripheral&gt;
+  ...
+&lt;/peripheral&gt;
+</pre></div><p>Two timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals. </p>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html
new file mode 100644
index 0000000..e1b2272
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html
@@ -0,0 +1,116 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>registerPropertiesGroup</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__register_properties_group__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">registerPropertiesGroup</div>  </div>
+<div class="ingroups"><a class="el" href="group__elem__type__gr.html">Element Groups</a></div></div>
+<div class="contents">
+<p>Register properties can be set on device, peripheral, and register level. Element values defined on a lower level overwrite element values defined on a more general level. For example, the <em>register-level.&lt;size&gt;</em> will overwrite <em>peripheral-level.&lt;size&gt;</em>. Elements that have not been defined on a more general level, must be defined at register level at the latest.</p>
+<table  class="cmtable" summary="Register Properties Group Elements">
+<tr>
+<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>size </td><td>Defines the default bit-width of any register contained in the device (implicit inheritance). This element can be redefined on any lower level of the description using the size element there.  </td><td>scaledNonNegativeInteger  </td><td>0..1   </td></tr>
+<tr>
+<td>access  </td><td>Defines the default access rights for all registers. Access rights can be redefined on any lower level of the description using the <em>access</em> element there. <br/>
+ <br/>
+ The predefined tokens are:<ul>
+<li><span class="XML-Token">read-only</span>: read access is permitted. Write operations have an undefined result.</li>
+<li><span class="XML-Token">write-only</span>: write access is permitted. Read operations have an undefined result.</li>
+<li><span class="XML-Token">read-write</span>: both read and write accesses are permitted. Writes affect the state of the register and reads return a value related to the register.</li>
+<li><span class="XML-Token">writeOnce</span>: only the first write after reset has an effect on the register. Read operations deliver undefined results.</li>
+<li><span class="XML-Token">read-writeOnce</span>: Read operations deliver a result related to the register content. Only the first write access to this register after a reset will have an effect on the register content.  </li>
+</ul>
+</td><td>accessType </td><td>0..1   </td></tr>
+<tr>
+<td>resetValue  </td><td>Defines the default value for all registers at RESET. The default register value can be redefined on any lower level using the <em>resetValue</em> element there. The actual reset value is calculated from the <em>resetValue</em> and the <em>resetMask</em>. The mask is used to specify bits with an undefined reset value. </td><td>scaledNonNegativeInteger  </td><td>0..1   </td></tr>
+<tr>
+<td>resetMask </td><td>Identifies which register bits have a defined reset value. These bit positions are set to one. Bit positions with an undefined reset value are set to zero. </td><td>scaledNonNegativeInteger </td><td>0..1   </td></tr>
+</table>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html
new file mode 100644
index 0000000..65a0520
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html
@@ -0,0 +1,151 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Extensions to the Register Section</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__register_section_extensions__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Extensions to the Register Section</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div>
+<div class="contents">
+<p>The following elements have been added to the register section. All new elements are optional.</p>
+<table  class="cmtable" summary="Register Section Extension Elements">
+<tr>
+<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>alternateRegister </td><td>This tag can reference a register that has been defined above to current location in the description and that describes the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is intentional. The register name needs to be unique within the scope of the current peripheral. A register description is defined either for a unique address location or could be a redefinition of an already described address. In the latter case, the register can be either marked <em>alternateRegister</em> and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through the tag <em>alternateGroup</em> (specified in version 1.0). </td><td>identifierType  </td><td>0..1   </td></tr>
+<tr>
+<td>dataType </td><td>It can be useful to assign a specific native C datatype to a register. This helps avoiding type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then <em>dataType</em> can be set to "uint32_t *". The following simple data types are predefined:<ul>
+<li><span class="XML-Token">uint8_t</span>: unsigned byte</li>
+<li><span class="XML-Token">uint16_t</span>: unsigned half word</li>
+<li><span class="XML-Token">uint32_t</span>: unsigned word</li>
+<li><span class="XML-Token">uint64_t</span>: unsigned double word</li>
+<li><span class="XML-Token">int8_t</span>: signed byte</li>
+<li><span class="XML-Token">int16_t</span>: signed half word</li>
+<li><span class="XML-Token">int32_t</span>: signed world</li>
+<li><span class="XML-Token">int64_t</span>: signed double word</li>
+<li><span class="XML-Token">uint8_t *</span>: pointer to unsigned byte</li>
+<li><span class="XML-Token">uint16_t *</span>: pointer to unsigned half word</li>
+<li><span class="XML-Token">uint32_t *</span>: pointer to unsigned word</li>
+<li><span class="XML-Token">uint64_t *</span>: pointer to unsigned double word</li>
+<li><span class="XML-Token">int8_t *</span>: pointer to signed byte</li>
+<li><span class="XML-Token">int16_t *</span>: pointer to signed half word</li>
+<li><span class="XML-Token">int32_t *</span>: pointer to signed world</li>
+<li><span class="XML-Token">int64_t *</span>: pointer to signed double word </li>
+</ul>
+</td><td>dataTypeType  </td><td>0..1   </td></tr>
+</table>
+<h2><a class="anchor" id="registerSection_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">...
+&lt;<span class="keyword">register</span>&gt;
+    &lt;name&gt;TIM_MODEA&lt;/name&gt;
+    &lt;description&gt;In mode A <span class="keyword">this</span> <span class="keyword">register</span> acts as a reload value&lt;/description&gt;
+    &lt;addressOffset&gt;0xC&lt;/addressOffset&gt;
+&lt;/<span class="keyword">register</span>&gt;
+&lt;<span class="keyword">register</span>&gt;
+    &lt;name&gt;TIM_MODEB&lt;/name&gt;
+    &lt;description&gt;In mode B <span class="keyword">this</span> <span class="keyword">register</span> acts as the compare value&lt;/description&gt;
+    &lt;alternateRegister&gt;TIM_MODEA&lt;/alternateRegister&gt;
+    &lt;addressOffset&gt;0xC&lt;/addressOffset&gt;
+&lt;/<span class="keyword">register</span>&gt;     
+&lt;<span class="keyword">register</span>&gt;
+    &lt;name&gt;DMA_DATA&lt;/name&gt;
+    &lt;description&gt;This <span class="keyword">register</span> contains the address of the data being transferred&lt;/description&gt;
+    &lt;dataType&gt;uint32_t *&lt;/dataType&gt;
+    &lt;addressOffset&gt;0xf0&lt;/addressOffset&gt;
+&lt;/<span class="keyword">register</span>&gt;     
+...
+</pre></div><p>This example describes two registers, TIM_MODEA and TIM_MODEB. Both have the same address offset. Based on the configured operation model being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. The code generated for the device header file is:</p>
+<div class="fragment"><pre class="fragment"><span class="keyword">typedef</span> <span class="keyword">struct </span>{
+  <span class="keyword">union </span>{
+    __IO   uint32_t TIM_MODEA;
+    __IO   uint32_t TIM_MODEB;
+        };
+  __IO uint32_t * DMA_DATA; 
+  ...
+} &lt;peripheral:name&gt;_Type;
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html
new file mode 100644
index 0000000..e47cb52
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html
@@ -0,0 +1,603 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>CMSIS-SVD Schema File Ver. 1.1 (draft)</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__schema__1__1__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">CMSIS-SVD Schema File Ver. 1.1 (draft)</div>  </div>
+</div>
+<div class="contents">
+<div class="fragment"><pre class="fragment">&lt;?xml version="1.0" encoding="UTF-8"?&gt;
+&lt;!-- 
+  @note    Copyright (C) 2011-2012 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @date: 12.03.2012
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+  This is a draft for CMSIS-SVD version 1.1
+  For backward compatibility all additional tags have been made optional.
+  Extensions may be mandatory for successful device header file generation
+  Other changes are related to some restructuring of the schema.
+  
+  Note that the memory section has been removed since this would limit the
+  reuse of descriptions for a series of devices.
+ --&gt;
+
+&lt;xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.1"&gt;
+  &lt;!-- stringType requires a none empty string of a least one character length --&gt;
+  &lt;xs:simpleType name="stringType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:minLength value="1"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released --&gt;
+  &lt;xs:simpleType name="cpuNameType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="CM0"/&gt;
+      &lt;xs:enumeration value="CM0PLUS"/&gt;
+      &lt;xs:enumeration value="CM0+"/&gt;
+      &lt;xs:enumeration value="SC000"/&gt;
+      &lt;xs:enumeration value="CM3"/&gt;
+      &lt;xs:enumeration value="SC300"/&gt;
+      &lt;xs:enumeration value="CM4"/&gt;
+      &lt;xs:enumeration value="other"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) --&gt;
+  &lt;xs:simpleType name="revisionType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="r[0-9]p[0-9]"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- EndianType pre-defines the tokens for specifying the endianess of the device --&gt;
+  &lt;xs:simpleType name="endianType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="little"/&gt;
+      &lt;xs:enumeration value="big"/&gt;
+      &lt;xs:enumeration value="selectable"/&gt;
+      &lt;xs:enumeration value="other"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- dataType pre-defines the tokens in line with CMSIS data type definitions --&gt;
+  &lt;xs:simpleType name="dataTypeType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="uint8_t"/&gt;
+      &lt;xs:enumeration value="uint16_t"/&gt;
+      &lt;xs:enumeration value="uint32_t"/&gt;
+      &lt;xs:enumeration value="uint64_t"/&gt;
+      &lt;xs:enumeration value="int8_t"/&gt;
+      &lt;xs:enumeration value="int16_t"/&gt;
+      &lt;xs:enumeration value="int32_t"/&gt;
+      &lt;xs:enumeration value="int64_t"/&gt;
+      &lt;xs:enumeration value="uint8_t *"/&gt;
+      &lt;xs:enumeration value="uint16_t *"/&gt;
+      &lt;xs:enumeration value="uint32_t *"/&gt;
+      &lt;xs:enumeration value="uint64_t *"/&gt;
+      &lt;xs:enumeration value="int8_t *"/&gt;
+      &lt;xs:enumeration value="int16_t *"/&gt;
+      &lt;xs:enumeration value="int32_t *"/&gt;
+      &lt;xs:enumeration value="int64_t *"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels --&gt;
+  &lt;xs:simpleType name="nvicPrioBitsType"&gt;
+    &lt;xs:restriction base="xs:integer"&gt;
+      &lt;xs:minInclusive value="2"/&gt;
+      &lt;xs:maxInclusive value="8"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. --&gt;
+  &lt;!-- this is particularly important as these are used in ANSI C Structures during the device header file generation --&gt;
+  &lt;xs:simpleType name="identifierType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. --&gt;
+  &lt;!-- this is particularly important as these are used in ANSI C Structures during the device header file generation --&gt;
+  &lt;xs:simpleType name="enumerationNameType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[_A-Za-z0-9]*"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays --&gt;
+  &lt;xs:simpleType name="dimIndexType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format --&gt;
+  &lt;xs:simpleType name="scaledNonNegativeInteger"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues --&gt;
+  &lt;xs:simpleType name="enumeratedValueDataType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- accessType specfies the pre-defined tokens for the available accesses --&gt;
+  &lt;xs:simpleType name="accessType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="read-only"/&gt;
+      &lt;xs:enumeration value="write-only"/&gt;
+      &lt;xs:enumeration value="read-write"/&gt;
+      &lt;xs:enumeration value="writeOnce"/&gt;
+      &lt;xs:enumeration value="read-writeOnce"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects --&gt;
+  &lt;xs:simpleType name="modifiedWriteValuesType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="oneToClear"/&gt;
+      &lt;xs:enumeration value="oneToSet"/&gt;
+      &lt;xs:enumeration value="oneToToggle"/&gt;
+      &lt;xs:enumeration value="zeroToClear"/&gt;
+      &lt;xs:enumeration value="zeroToSet"/&gt;
+      &lt;xs:enumeration value="zeroToToggle"/&gt;
+      &lt;xs:enumeration value="clear"/&gt;
+      &lt;xs:enumeration value="set"/&gt;
+      &lt;xs:enumeration value="modify"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- readAction type specifies the pre-defined tokens for read side effects --&gt;
+  &lt;xs:simpleType name="readActionType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="clear"/&gt;
+      &lt;xs:enumeration value="set"/&gt;
+      &lt;xs:enumeration value="modify"/&gt;
+      &lt;xs:enumeration value="modifyExternal"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with --&gt;
+  &lt;xs:simpleType name="enumUsageType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="read"/&gt;
+      &lt;xs:enumeration value="write"/&gt;
+      &lt;xs:enumeration value="read-write"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 --&gt;
+  &lt;xs:simpleType name="bitRangeType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+  &lt;!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource --&gt;
+  &lt;xs:complexType name="writeConstraintType"&gt;
+    &lt;xs:choice&gt;
+      &lt;xs:element name="writeAsRead" type="xs:boolean"/&gt;
+      &lt;xs:element name="useEnumeratedValues" type="xs:boolean"/&gt;
+      &lt;xs:element name="range"&gt;
+        &lt;xs:complexType&gt;
+          &lt;xs:sequence&gt;
+            &lt;xs:element name="minimum" type="scaledNonNegativeInteger"/&gt;
+            &lt;xs:element name="maximum" type="scaledNonNegativeInteger"/&gt;
+          &lt;/xs:sequence&gt;
+        &lt;/xs:complexType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:choice&gt;
+  &lt;/xs:complexType&gt;
+  &lt;!-- addressBlockType specifies the elements to describe an address block --&gt;
+  &lt;xs:complexType name="addressBlockType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="offset" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="size" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="usage"&gt;
+        &lt;xs:simpleType&gt;
+          &lt;xs:restriction base="xs:token"&gt;
+            &lt;xs:enumeration value="registers"/&gt;
+            &lt;xs:enumeration value="buffer"/&gt;
+            &lt;xs:enumeration value="reserved"/&gt;
+          &lt;/xs:restriction&gt;
+        &lt;/xs:simpleType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+  &lt;!-- interruptType specifies how to describe an interrupt associated with a peripheral --&gt;
+  &lt;xs:complexType name="interruptType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="name" type="stringType"/&gt;
+      &lt;xs:element name="description" type="xs:string" minOccurs="0"/&gt;
+      &lt;xs:element name="value" type="xs:integer"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+  &lt;!-- register properties group specifies register size, access permission and reset value 
+       this is used in multiple locations. Settings are inherited downstream. --&gt;  
+  &lt;xs:group name="registerPropertiesGroup"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+      &lt;xs:element name="access" type="accessType" minOccurs="0"/&gt;
+      &lt;xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+      &lt;xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+  &lt;!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+       by specifying the least significant and the most significant bit position --&gt;
+  &lt;xs:group name="bitRangeLsbMsbStyle"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="lsb"  type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="msb"  type="scaledNonNegativeInteger"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+  &lt;!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
+       by specifying the least significant bit position and the bitWidth of the field --&gt;
+  &lt;xs:group name="bitRangeOffsetWidthStyle"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="bitOffset" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/&gt;   
+    &lt;/xs:sequence&gt; 
+  &lt;/xs:group&gt;
+  &lt;!-- dimElementGroup specifies the number of array elements (dim), the address offset
+       between to consecutive array elements and an a comma seperated list of strings 
+       being used for identifying each element in the array --&gt;
+  &lt;xs:group name="dimElementGroup"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="dim" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="dimIncrement" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+
+  &lt;xs:complexType name="cpuType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;!-- V1.1: ARM processor name: Cortex-Mx / SCxxx --&gt;
+      &lt;xs:element name="name" type="cpuNameType"/&gt;
+      &lt;!-- V1.1: ARM defined revision of the cpu --&gt;
+      &lt;xs:element name="revision" type="revisionType"/&gt;
+      &lt;!-- V1.1: Endian specifies the endianess of the processor/device --&gt;
+      &lt;xs:element name="endian" type="endianType"/&gt;
+      &lt;!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present --&gt;
+      &lt;xs:element name="mpuPresent" type="xs:boolean"/&gt;
+      &lt;!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present --&gt;
+      &lt;xs:element name="fpuPresent" type="xs:boolean"/&gt;
+      &lt;!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller
+                   for defining the priority level = # priority levels --&gt;
+      &lt;xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/&gt;
+      &lt;!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device 
+                   instead of the ARM specified SysTickTimer --&gt;
+      &lt;xs:element name="vendorSystickConfig" type="xs:boolean"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="enumeratedValuesType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;!-- name specfies a reference to this enumeratedValues section for reuse purposes
+           this name does not appear in the System Viewer nor the Header File. --&gt;
+      &lt;xs:element name="name" type="enumerationNameType" minOccurs="0"/&gt;
+      &lt;!-- usage specifies whether this enumeration is to be used for read or write or 
+                                                       (read and write) accesses --&gt;
+      &lt;xs:element name="usage" type="enumUsageType" minOccurs="0"/&gt;
+      &lt;!-- enumeratedValue derivedFrom=&lt;identifierType&gt; --&gt;
+      &lt;xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded"&gt;
+        &lt;xs:complexType&gt;
+          &lt;xs:sequence&gt;
+            &lt;!-- name is a ANSI C indentifier representing the value (C Enumeration) --&gt;
+            &lt;xs:element name="name" type="enumerationNameType"/&gt;
+            &lt;!-- description contains the details about the semantics/behavior specified by this value --&gt;
+            &lt;xs:element name="description" type="stringType" minOccurs="0"/&gt;
+            &lt;xs:choice&gt;
+              &lt;xs:element name="value" type="enumeratedValueDataType"/&gt;
+              &lt;!-- isDefault specifies the name and description for all values that are not
+                   specifically described individually --&gt;
+              &lt;xs:element name="isDefault" type="xs:boolean"/&gt;
+            &lt;/xs:choice&gt;
+          &lt;/xs:sequence&gt;
+        &lt;/xs:complexType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="derivedFrom" type="identifierType" use="optional"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="fieldType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;!-- name specifies a field's name. The System Viewer and the device header file will
+           use the name of the field as identifier --&gt;
+      &lt;xs:element name="name" type="identifierType"/&gt;
+      &lt;!-- description contains reference manual level information about the function and 
+           options of a field --&gt;
+      &lt;xs:element name="description" type="stringType" minOccurs="0"/&gt;
+      &lt;!-- alternative specifications of the bit position of the field within the register --&gt;
+      &lt;xs:choice minOccurs="1" maxOccurs="1"&gt;
+        &lt;!-- bit field described by lsb followed by msb tag --&gt;
+        &lt;xs:group ref="bitRangeLsbMsbStyle"/&gt;
+        &lt;!-- bit field described by bit offset relative to Bit0 + bit width of field --&gt;
+        &lt;xs:group ref="bitRangeOffsetWidthStyle"/&gt;
+        &lt;!-- bit field described by [&lt;msb&gt;:&lt;lsb&gt;] --&gt;
+        &lt;xs:element name="bitRange" type="bitRangeType"/&gt;
+      &lt;/xs:choice&gt;
+      &lt;!-- access describes the predefined permissions for the field. --&gt;
+      &lt;xs:element name="access" type="accessType" minOccurs="0"/&gt;
+      &lt;!-- predefined description of write side effects --&gt;
+      &lt;xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/&gt;
+      &lt;!-- writeContstraint specifies the subrange of allowed values --&gt;
+      &lt;xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/&gt;
+      &lt;!-- readAction specifies the read side effects. --&gt;
+      &lt;xs:element name="readAction" type="readActionType" minOccurs="0"/&gt;
+      &lt;!-- enumeratedValues derivedFrom=&lt;identifierType&gt; --&gt;
+      &lt;xs:element name="enumeratedValues" type="enumeratedValuesType" minOccurs="0" maxOccurs="2"&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="derivedFrom" type="identifierType" use="optional"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="fieldsType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;!-- field derivedFrom=&lt;identifierType&gt; --&gt;
+      &lt;xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="registerType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:group    ref="dimElementGroup" minOccurs="0"/&gt;
+      &lt;!-- name specifies the name of the register. The register name is used by System Viewer and
+                                     device header file generator to represent a register --&gt;
+      &lt;xs:element name="name" type="identifierType"/&gt;
+      &lt;!-- display name specifies a register name without the restritions of an ANSIS C identifier.
+                                     The use of this tag is discouraged because it does not allow consistency between
+                                     the System View and the device header file. --&gt;
+      &lt;xs:element name="displayName" type="stringType" minOccurs="0"/&gt;
+      &lt;!-- description contains a reference manual level description about the register and it's purpose --&gt;
+      &lt;xs:element name="description" type="stringType" minOccurs="0"/&gt;
+      &lt;xs:choice&gt;
+        &lt;!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
+                                       This is useful if a register has a different description per mode but a single name --&gt;
+        &lt;xs:element name="alternateGroup" type="identifierType" minOccurs="0"/&gt;
+        &lt;!-- V1.1: alternateRegister specifies an alternate register description for an address that is
+                                       already fully described. In this case the register name must be unique within the peripheral --&gt;
+        &lt;xs:element name="alternateRegister" type="identifierType" minOccurs="0"/&gt;
+      &lt;/xs:choice&gt;
+      &lt;!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral --&gt;
+      &lt;xs:element name="addressOffset" type="scaledNonNegativeInteger"/&gt;
+      &lt;!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                                     reset value. These default values are inherited to all fields contained in this register --&gt;
+      &lt;xs:group    ref="registerPropertiesGroup" minOccurs="0"/&gt;
+      &lt;!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) --&gt;
+      &lt;xs:element name="dataType" type="dataTypeType" minOccurs="0"/&gt;
+      &lt;!-- modifiedWriteValues specifies the write side effects --&gt;
+      &lt;xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/&gt;
+      &lt;!-- writeConstraint specifies the subset of allowed write values --&gt;
+      &lt;xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/&gt;
+      &lt;!-- readAcction specifies the read side effects --&gt;
+      &lt;xs:element name="readAction" type="readActionType" minOccurs="0"/&gt;
+      &lt;!-- fields section contains all fields that belong to this register --&gt;
+      &lt;xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="derivedFrom" type="identifierType" use="optional"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file --&gt;
+  &lt;xs:complexType name="clusterType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:group   ref="dimElementGroup" minOccurs="0"/&gt;
+      &lt;xs:element name="name" type="identifierType"/&gt;
+      &lt;xs:element name="description" type="xs:string"/&gt;
+      &lt;!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
+                 already fully described. In this case the cluster name must be unique within the peripheral --&gt;
+      &lt;xs:element name="alternateCluster" type="identifierType" minOccurs="0"/&gt;
+      &lt;!-- V1.1: headerStructName specifies the name for the cluster structure typedef
+                 used in the device header generation instead of the cluster name --&gt;
+      &lt;xs:element name="headerStructName" type="identifierType" minOccurs="0"/&gt;
+      &lt;xs:element name="addressOffset" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="register" type="registerType" minOccurs="1" maxOccurs="unbounded"/&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="derivedFrom" type="identifierType" use="optional"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- the registers section can have an arbitrary list of cluster and register sections --&gt;
+  &lt;xs:complexType name="registersType"&gt;
+    &lt;xs:choice minOccurs="1" maxOccurs="unbounded"&gt;
+      &lt;xs:element name="cluster" type="clusterType"/&gt;
+      &lt;xs:element name="register" type="registerType"/&gt;
+    &lt;/xs:choice&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="peripheralType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;!-- name specifies the name of a peripheral. This name is used for the System View and device header file --&gt;
+      &lt;xs:element name="name" type="xs:Name"/&gt;
+      &lt;!-- version specifies the version of the peripheral descriptions --&gt;
+      &lt;xs:element name="version" type="stringType" minOccurs="0"/&gt;
+      &lt;!-- description provides a high level functional description of the peripheral --&gt;
+      &lt;xs:element name="description" type="stringType" minOccurs="0"/&gt;
+      &lt;!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
+           already fully by a peripheral described. In this case the peripheral name must be unique within the device description --&gt;
+      &lt;xs:element name="alternatePeripheral" type="identifierType" minOccurs="0"/&gt;
+      &lt;!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View --&gt;
+      &lt;xs:element name="groupName" type="xs:Name" minOccurs="0"/&gt;
+      &lt;!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. --&gt;
+      &lt;xs:element name="prependToName" type="identifierType" minOccurs="0"/&gt;
+      &lt;!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+                         file will sho the registers in a C-Struct of the peripheral without the postfix --&gt;
+      &lt;xs:element name="appendToName" type="identifierType" minOccurs="0"/&gt;
+      &lt;!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
+                         used in the device header generation instead of the peripheral name --&gt;
+      &lt;xs:element name="headerStructName" type="identifierType" minOccurs="0"/&gt;
+      &lt;!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+                         if the condition is evaluated to true, the peripheral display will be disabled --&gt;
+      &lt;xs:element name="disableCondition" type="stringType" minOccurs="0"/&gt;
+      &lt;!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
+                         to specify a baseAddress. --&gt;
+      &lt;xs:element name="baseAddress" type="scaledNonNegativeInteger"/&gt;
+      &lt;!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                         reset value. These default values are inherited to all registers contained in this peripheral --&gt;
+      &lt;xs:group ref="registerPropertiesGroup" minOccurs="0"/&gt;
+      &lt;!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
+                         at least one address block --&gt;
+      &lt;xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/&gt;
+      &lt;!-- interrupt specifies can specify one or more interrtupts by name, description and value --&gt;
+      &lt;xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/&gt;
+      &lt;!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
+                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        registers section is not allowed --&gt;
+      &lt;xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1"&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="derivedFrom" type="identifierType" use="optional"/&gt;
+  &lt;/xs:complexType&gt;
+  
+  &lt;!-- ==================================================== --&gt;
+  &lt;!-- The top level element of a description is the device --&gt;
+  &lt;!-- ==================================================== --&gt;
+  &lt;xs:element name="device" nillable="true"&gt;
+    &lt;xs:complexType&gt;
+      &lt;xs:sequence&gt;
+        &lt;!-- V1.1: Vendor Name --&gt;
+        &lt;xs:element name="vendor" type="stringType" minOccurs="0"/&gt;
+        &lt;!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) --&gt;
+        &lt;xs:element name="vendorID" type="identifierType" minOccurs="0"/&gt;
+        &lt;!-- name specifies the device name being described --&gt;
+        &lt;xs:element name="name" type="identifierType"/&gt;
+        &lt;!-- V1.1: series specifies the device series or family name --&gt;
+        &lt;xs:element name="series" type="stringType" minOccurs="0"/&gt;
+        &lt;!-- version specifies the version of the device description --&gt;
+        &lt;xs:element name="version" type="stringType"/&gt;
+        &lt;!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) --&gt;
+        &lt;xs:element name="description" type="stringType"/&gt;
+        &lt;!-- V1.1: licenseText specifies the file header section to be included in any derived file --&gt;
+        &lt;xs:element name="licenseText" type="stringType" minOccurs="0"/&gt;
+        &lt;!-- V1.1: cpu specifies the details of the processor included in the device --&gt;
+        &lt;xs:element name="cpu" type="cpuType" minOccurs="0"/&gt;
+        &lt;!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
+             This tag is used by the header file generator for customizing the include statement referencing the
+             CMSIS system file within the CMSIS device header file. By default the filename is "system_&lt;device.name&gt;"
+             In cases a device series shares a single system header file, the name of the series shall be used 
+             instead of the individual device name. --&gt;
+        &lt;xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/&gt;
+        &lt;!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
+             generated device header file --&gt;
+        &lt;xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/&gt;
+        &lt;!-- addressUnitBits specifies the size of the minimal addressable unit in bits --&gt;
+        &lt;xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/&gt;
+        &lt;!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
+             This sets the maximum size of a single register that can be defined for an address space --&gt;
+        &lt;xs:element name="width" type="scaledNonNegativeInteger"/&gt;
+        &lt;!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+             reset value --&gt;
+        &lt;xs:group ref="registerPropertiesGroup" minOccurs="0"/&gt;
+
+        &lt;!-- peripherals is containing all peripherals --&gt;
+        &lt;xs:element name="peripherals"&gt;
+          &lt;xs:complexType&gt;
+            &lt;xs:sequence&gt;
+              &lt;xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/&gt;
+            &lt;/xs:sequence&gt;
+          &lt;/xs:complexType&gt;
+        &lt;/xs:element&gt;
+
+        &lt;!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default --&gt;
+        &lt;xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1"&gt;
+          &lt;xs:complexType&gt;
+            &lt;xs:sequence&gt;
+              &lt;xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded"&gt;
+              &lt;/xs:any&gt;
+            &lt;/xs:sequence&gt;
+          &lt;/xs:complexType&gt;
+        &lt;/xs:element&gt;
+      &lt;/xs:sequence&gt;
+      &lt;xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.1"/&gt;
+    &lt;/xs:complexType&gt;
+  &lt;/xs:element&gt;
+&lt;/xs:schema&gt;
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html
new file mode 100644
index 0000000..5715fe0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html
@@ -0,0 +1,368 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>CMSIS-SVD Schema File Ver. 1.0</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__schema__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">CMSIS-SVD Schema File Ver. 1.0</div>  </div>
+</div>
+<div class="contents">
+<div class="fragment"><pre class="fragment">&lt;?xml version="1.0" encoding="UTF-8"?&gt;
+&lt;!-- 
+  @date: 07.12.2011
+  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ --&gt;
+
+&lt;xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0"&gt;
+  
+  &lt;xs:simpleType name="registerNameType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="dimIndexType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="scaledNonNegativeInteger"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="enumeratedValueDataType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="accessType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="read-only"/&gt;
+      &lt;xs:enumeration value="write-only"/&gt;
+      &lt;xs:enumeration value="read-write"/&gt;
+      &lt;xs:enumeration value="writeOnce"/&gt;
+      &lt;xs:enumeration value="read-writeOnce"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="modifiedWriteValuesType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="oneToClear"/&gt;
+      &lt;xs:enumeration value="oneToSet"/&gt;
+      &lt;xs:enumeration value="oneToToggle"/&gt;
+      &lt;xs:enumeration value="zeroToClear"/&gt;
+      &lt;xs:enumeration value="zeroToSet"/&gt;
+      &lt;xs:enumeration value="zeroToToggle"/&gt;
+      &lt;xs:enumeration value="clear"/&gt;
+      &lt;xs:enumeration value="set"/&gt;
+      &lt;xs:enumeration value="modify"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="readActionType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="clear"/&gt;
+      &lt;xs:enumeration value="set"/&gt;
+      &lt;xs:enumeration value="modify"/&gt;
+      &lt;xs:enumeration value="modifyExternal"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="enumUsageType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="read"/&gt;
+      &lt;xs:enumeration value="write"/&gt;
+      &lt;xs:enumeration value="read-write"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="bitRangeType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:complexType name="writeConstraintType"&gt;
+    &lt;xs:choice&gt;
+      &lt;xs:element name="writeAsRead" type="xs:boolean"/&gt;
+      &lt;xs:element name="useEnumeratedValues" type="xs:boolean"/&gt;
+      &lt;xs:element name="range"&gt;
+        &lt;xs:complexType&gt;
+          &lt;xs:sequence&gt;
+            &lt;xs:element name="minimum" type="scaledNonNegativeInteger"/&gt;
+            &lt;xs:element name="maximum" type="scaledNonNegativeInteger"/&gt;
+          &lt;/xs:sequence&gt;
+        &lt;/xs:complexType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:choice&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="addressBlockType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="offset" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="size" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="usage"&gt;
+        &lt;xs:simpleType&gt;
+          &lt;xs:restriction base="xs:token"&gt;
+            &lt;xs:enumeration value="registers"/&gt;
+            &lt;xs:enumeration value="buffer"/&gt;
+            &lt;xs:enumeration value="reserved"/&gt;
+          &lt;/xs:restriction&gt;
+        &lt;/xs:simpleType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="interruptType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="name" type="xs:string"/&gt;
+      &lt;xs:element name="value" type="xs:integer"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:group name="registerPropertiesGroup"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+      &lt;xs:element name="access" type="accessType" minOccurs="0"/&gt;
+      &lt;xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+      &lt;xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+
+  &lt;xs:group name="bitRangeLsbMsbStyle"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="lsb"  type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="msb"  type="scaledNonNegativeInteger"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+
+  &lt;xs:group name="bitRangeOffsetWidthStyle"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="bitOffset" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/&gt;   
+    &lt;/xs:sequence&gt; 
+  &lt;/xs:group&gt;
+
+  &lt;xs:group name="dimElementGroup"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="dim" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="dimIncrement" type="scaledNonNegativeInteger"/&gt;
+      &lt;xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:group&gt;
+
+  &lt;xs:element name="device" nillable="true"&gt;
+    &lt;xs:complexType&gt;
+      &lt;xs:sequence&gt;
+        &lt;xs:element name="name" type="xs:string"/&gt;
+        &lt;xs:element name="version" type="xs:string"/&gt;
+        &lt;xs:element name="description" type="xs:string"/&gt;
+        &lt;xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/&gt;
+        &lt;xs:element name="width" type="scaledNonNegativeInteger"/&gt;
+        &lt;xs:group ref="registerPropertiesGroup" minOccurs="0"/&gt;
+        &lt;xs:element name="peripherals"&gt;
+          &lt;xs:complexType&gt;
+            &lt;xs:sequence&gt;
+              &lt;xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded"&gt;
+                &lt;xs:complexType&gt;
+                  &lt;xs:sequence&gt;
+                    &lt;xs:element name="name" type="xs:Name"/&gt;
+                    &lt;xs:element name="version" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="description" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="groupName" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="prependToName" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="appendToName" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="disableCondition" type="xs:string" minOccurs="0"/&gt;
+                    &lt;xs:element name="baseAddress" type="scaledNonNegativeInteger"/&gt;
+                    &lt;xs:group ref="registerPropertiesGroup" minOccurs="0"/&gt;
+                    &lt;xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/&gt;
+                    &lt;xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/&gt;
+                    &lt;xs:element name="registers" minOccurs="0" maxOccurs="1"&gt;
+                      &lt;xs:complexType&gt;
+                        &lt;xs:sequence&gt;
+                          &lt;xs:element name="register" minOccurs="1" maxOccurs="unbounded"&gt;
+                            &lt;xs:complexType&gt;
+                              &lt;xs:sequence&gt;
+                                &lt;xs:group ref="dimElementGroup" minOccurs="0"/&gt;
+                                &lt;xs:element name="name" type="registerNameType"/&gt; &lt;!-- was xs:Name --&gt;
+                                &lt;xs:element name="displayName" type="xs:string" minOccurs="0"/&gt;
+                                &lt;xs:element name="description" type="xs:string" minOccurs="0"/&gt;
+                                &lt;xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/&gt;
+                                &lt;xs:element name="addressOffset" type="scaledNonNegativeInteger"/&gt;
+                                &lt;xs:group ref="registerPropertiesGroup" minOccurs="0"/&gt;
+                                &lt;xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/&gt;
+                                &lt;xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/&gt;
+                                &lt;xs:element name="readAction" type="readActionType" minOccurs="0"/&gt;
+                                &lt;xs:element name="fields" minOccurs="0" maxOccurs="1"&gt;
+                                  &lt;xs:complexType&gt;
+                                    &lt;xs:sequence&gt;
+                                      &lt;xs:element name="field" minOccurs="1" maxOccurs="unbounded"&gt;
+                                      &lt;xs:complexType&gt;
+                                        &lt;xs:sequence&gt;
+                                          &lt;xs:element name="name" type="xs:string"/&gt;
+                                          &lt;xs:element name="description" type="xs:string" minOccurs="0"/&gt;
+                                          &lt;xs:choice&gt;
+                                            &lt;xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/&gt;
+                                            &lt;xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/&gt;
+                                            &lt;xs:element name="bitRange" type="bitRangeType" minOccurs="0"/&gt;
+                                          &lt;/xs:choice&gt;
+                                          &lt;xs:element name="access" type="accessType" minOccurs="0"/&gt;
+                                          &lt;xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/&gt;
+                                          &lt;xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/&gt;
+                                          &lt;xs:element name="readAction" type="readActionType" minOccurs="0"/&gt;
+                                          &lt;xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2"&gt;
+                                            &lt;xs:complexType&gt;
+                                              &lt;xs:sequence&gt;
+                                                &lt;xs:element name="name" type="xs:Name" minOccurs="0"/&gt;
+                                                &lt;xs:element name="usage" type="enumUsageType" minOccurs="0"/&gt;
+                                                &lt;xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded"&gt;
+                                                  &lt;xs:complexType&gt;
+                                                    &lt;xs:sequence&gt;
+                                                      &lt;xs:element name="name" type="xs:string"/&gt;
+                                                      &lt;xs:element name="description" type="xs:string" minOccurs="0"/&gt;
+                                                      &lt;xs:choice&gt;
+                                                        &lt;xs:element name="value" type="enumeratedValueDataType"/&gt;
+                                                        &lt;xs:element name="isDefault" type="xs:boolean"/&gt;
+                                                      &lt;/xs:choice&gt;
+                                                    &lt;/xs:sequence&gt;
+                                                  &lt;/xs:complexType&gt;
+                                                &lt;/xs:element&gt;
+                                              &lt;/xs:sequence&gt;
+                                              &lt;xs:attribute name="derivedFrom" type="xs:Name" use="optional"/&gt;
+                                            &lt;/xs:complexType&gt;
+                                          &lt;/xs:element&gt;
+                                        &lt;/xs:sequence&gt;
+                                        &lt;xs:attribute name="derivedFrom" type="xs:Name" use="optional"/&gt;
+                                      &lt;/xs:complexType&gt;
+                                    &lt;/xs:element&gt;
+                                    &lt;/xs:sequence&gt;
+                                  &lt;/xs:complexType&gt;
+                                &lt;/xs:element&gt;
+                              &lt;/xs:sequence&gt;
+                              &lt;xs:attribute name="derivedFrom" type="xs:Name" use="optional"/&gt;
+                            &lt;/xs:complexType&gt;
+                          &lt;/xs:element&gt;
+                        &lt;/xs:sequence&gt;
+                      &lt;/xs:complexType&gt;
+                    &lt;/xs:element&gt;
+                  &lt;/xs:sequence&gt;
+                  &lt;xs:attribute name="derivedFrom" type="xs:Name" use="optional"/&gt;
+                &lt;/xs:complexType&gt;
+              &lt;/xs:element&gt;
+            &lt;/xs:sequence&gt;
+          &lt;/xs:complexType&gt;
+        &lt;/xs:element&gt;
+        &lt;xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1"&gt;
+          &lt;xs:complexType&gt;
+            &lt;xs:sequence&gt;
+              &lt;xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded"&gt;
+              &lt;/xs:any&gt;
+            &lt;/xs:sequence&gt;
+          &lt;/xs:complexType&gt;
+        &lt;/xs:element&gt;
+      &lt;/xs:sequence&gt;
+      &lt;xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/&gt;
+    &lt;/xs:complexType&gt;
+  &lt;/xs:element&gt;
+&lt;/xs:schema&gt;
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html
new file mode 100644
index 0000000..0c91e2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html
@@ -0,0 +1,107 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SVD Extension in Version 1.1</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__svd___format__1__1__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#groups">Modules</a>  </div>
+  <div class="headertitle">
+<div class="title">SVD Extension in Version 1.1</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="groups"></a>
+Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device_section_extensions__gr.html">Extensions to the Device Section</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cpu_section__gr.html">CPU Section (New)</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral_section_extensions__gr.html">Extensions to the Peripheral Section</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cluster_level__gr.html">Cluster Level (New)</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__register_section_extensions__gr.html">Extensions to the Register Section</a></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>From a schema perspective, CMSIS-SVD Version 1.1 is fully backward compatible to version 1.0. Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. It is expected that over time all CMSIS-SVD descriptions will comply with version 1.1. Version 1.1 has not been finalized yet and is therefore currently marked <b>draft</b>. </p>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html
new file mode 100644
index 0000000..f1a0714
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html
@@ -0,0 +1,139 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SVD File Schema Levels</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__svd___format__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#groups">Modules</a>  </div>
+  <div class="headertitle">
+<div class="title">SVD File Schema Levels</div>  </div>
+</div>
+<div class="contents">
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="groups"></a>
+Modules</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__svd__xml__device__gr.html">Device Level</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__svd__xml__peripherals__gr.html">Peripherals Level</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__svd__xml__registers__gr.html">Registers Level</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__svd__xml__fields__gr.html">Fields Level</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__svd__xml__enum__gr.html">Enumerated Values Level</a></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Description</h2>
+<p>This section specifies the <b>SVD file format</b> Version 1.0. Each subsection defines one level of hierarchy and lists all mandatory and optional language elements as well as their type. A brief example description snippet demonstrates the usage of the elements. </p>
+<dl class="note"><dt><b>Note:</b></dt><dd><ul>
+<li>The sequence of elements in CMSIS-SVD is mandatory.</li>
+<li><span class="opt">Optional elements</span> are highlighted in green.</li>
+<li><span class="mand">Mandatory elements</span> are highlighted in blue. Optional sections can contain mandatory elements, which must be specified when the optional section is used. In this case the mandatory elements are also highlighted in blue.</li>
+</ul>
+</dd></dl>
+<h2><a class="anchor" id="Names"></a>
+Names</h2>
+<p>All <b>name</b> tags must comply with the ANSI C identifier naming restrictions (identifierType). In particular they must not contain any spaces or special characters. This is necessary to support the generation of device header files thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS compliant target software.</p>
+<h2><a class="anchor" id="Constants"></a>
+Constants</h2>
+<p>Number constants shall be entered in hexadecimal, decimal, or binary format. </p>
+<ul>
+<li>The Hexadecimal format is indicated by a leading <b>"0x"</b>. </li>
+<li>The Binary format is indicated by a leading <b>"#"</b>. </li>
+<li>All other formats are interpreted as decimal numbers. </li>
+<li>The value tag in <em>enumeratedValue</em> accepts do not care bits represented by <b>"x"</b>.</li>
+</ul>
+<h2><a class="anchor" id="Comments"></a>
+Comments</h2>
+<p>Comments have the standard XML format. </p>
+<ul>
+<li>Start a comment with <b>"&lt;!--"</b>. </li>
+<li>End a comment with <b>"--&gt;"</b>.</li>
+</ul>
+<h2><a class="anchor" id="_"></a>
+Empty Tags</h2>
+<ul>
+<li>Single tags are not supported (for example, &lt;name&gt;).</li>
+<li>The tag content must not consist of an empty string (instead, omit optional tags).</li>
+</ul>
+<dl class="remark"><dt><b>Remarks:</b></dt><dd>The <a class="el" href="group__schema__gr.html">CMSIS-SVD Schema File Ver. 1.0</a> and schema_1_1_gr are provided alongside this document. </dd></dl>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html
new file mode 100644
index 0000000..4542279
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html
@@ -0,0 +1,177 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Device Level</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__svd__xml__device__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Device Level</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></div></div>
+<div class="contents">
+<p>The element <b>device</b> provides the outermost frame of the description.</p>
+<ul>
+<li>Only one device section is allowed per file. All other elements like peripherals, registers, fields, enumerated values, and vendor extensions are described within this scope.</li>
+<li>A device contains one or more peripherals.</li>
+<li>Optional elements like size, access, resetValue, and resetMask defined on this level are used as default values throughout the device description, unless they get redefined at a lower level. </li>
+</ul>
+<hr/>
+<pre>
+<span class="mand"><b>&lt;device schemaVersion=<em>"xs:decimal"</em> xmlns:xs=<em>"http://www.w3.org/2001/XMLSchema-instance"</em> xs:noNamespaceSchemaLocation=<em>"CMSIS-SVD_Schema_1_0.xsd"</em>&gt;</b></span></pre><pre><span class="mand">    &lt;name&gt;<em>identifierType</em>&lt;/name&gt;
+    &lt;version&gt;<em>xs:string</em>&lt;/version&gt;
+    &lt;description&gt;<em>xs:string</em>&lt;/description&gt;
+    &lt;addressUnitBits&gt;<em>scaledNonNegativeInteger</em>&lt;/addressUnitBits&gt;
+    &lt;width&gt;<em>scaledNonNegativeInteger</em>&lt;/width&gt;
+<span class="opt">
+    <em>&lt;!-- registerPropertiesGroup --&gt;</em>
+    &lt;size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;
+    &lt;access&gt;<em>accessType</em>&lt;/access&gt;
+    &lt;resetValue&gt;<em>scaledNonNegativeInteger</em>&lt;/resetValue&gt;
+    &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;
+    <em>&lt;!-- end of registerPropertiesGroup --&gt;</em>
+</span>
+    &lt;peripherals&gt;
+        ...
+    &lt;/peripherals&gt;
+<span class="opt">
+    &lt;vendorExtensions&gt;
+        ...
+    &lt;/vendorExtensions&gt;</span></span></pre><pre><span class="mand"><b>&lt;/device&gt;</b>
+</span>
+</pre><table  class="cmtable" summary="Device Level Schema">
+<tr>
+<th>Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>xmlns:xs </td><td>Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: <span class="XML-Token">"http://www.w3.org/2001/XMLSchema-instance"</span>. </td><td>xs:decimal </td><td>1..1  </td></tr>
+<tr>
+<td>xmlns:xs </td><td>Specifies the file path and file name of the CMSIS-SVD Schema. For example, <span class="XML-Token">CMSIS-SVD_Schema_1_0.xsd</span>. </td><td>xs:string </td><td>1..1  </td></tr>
+<tr>
+<td>schemaVersion </td><td>Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.0).  </td><td>xs:decimal </td><td>1..1  </td></tr>
+<tr>
+<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>name </td><td>The name string is used to identify the device or device series. Device names are required to be unique. </td><td>xs:string  </td><td>1..1   </td></tr>
+<tr>
+<td>version  </td><td>The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version.   </td><td>xs:string  </td><td>1..1  </td></tr>
+<tr>
+<td>description  </td><td>String for describing main features of a device (for example CPU, clock frequency, peripheral overview). </td><td>xs:string  </td><td>1..1   </td></tr>
+<tr>
+<td>addressUnitBits  </td><td>Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable).  </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr>
+<td>width  </td><td>Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr class="group1">
+<td colspan="4">See <a class="el" href="group__register_properties_group__gr.html">registerPropertiesGroup</a> for details.  </td></tr>
+<tr class="group1">
+<td align="right">size </td><td>Defines the default bit-width of any register contained in the device (implicit inheritance).  </td><td>scaledNonNegativeInteger </td><td>0..1  </td></tr>
+<tr class="group1">
+<td align="right">access </td><td>Defines the default access rights for all registers. </td><td>accessType </td><td>0..1   </td></tr>
+<tr class="group1">
+<td align="right">resetValue  </td><td>Defines the default value for all registers at RESET. </td><td>scaledNonNegativeInteger  </td><td>0..1   </td></tr>
+<tr class="group1">
+<td align="right">resetMask </td><td>Identifies which register bits have a defined reset value. </td><td>scaledNonNegativeInteger </td><td>0..1  </td></tr>
+<tr>
+<td>peripherals  </td><td>Next level of description. see <a class="el" href="group__svd__xml__peripherals__gr.html">Peripherals Level</a> for details. </td><td>&#160; </td><td>1..1   </td></tr>
+<tr>
+<td>vendorExtensions  </td><td>The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section.  </td><td>xs:anyType (restriction)  </td><td>0..1   </td></tr>
+</table>
+<h2><a class="anchor" id="dev_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">&lt;device schemaVersion=<span class="stringliteral">&quot;1.0&quot;</span> xmlns:xs=<span class="stringliteral">&quot;http://www.w3.org/2001/XMLSchema-instance&quot;</span> xs:noNamespaceSchemaLocation=<span class="stringliteral">&quot;CMSIS-SVD_Schema_1_0.xsd&quot;</span>&gt;
+  &lt;name&gt;ARM_Cortex_M3&lt;/name&gt;
+  &lt;version&gt;0.1&lt;/version&gt;
+  &lt;description&gt;ARM Cortex-M3 based Microcontroller demonstration device&lt;/description&gt;
+  &lt;addressUnitBits&gt;8&lt;/addressUnitBits&gt;
+  &lt;width&gt;32&lt;/width&gt;
+  &lt;size&gt;32&lt;/size&gt;
+  &lt;access&gt;read-write&lt;/access&gt;
+  &lt;resetValue&gt;0&lt;/resetValue&gt;
+  &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;
+
+  &lt;peripherals&gt;
+    ...
+  &lt;/peripherals&gt;
+&lt;/device&gt;
+</pre></div><p>The device description above is at version 0.1 and uniquely identifies the device by the name "ARM_Cortex_M3". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level. </p>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html
new file mode 100644
index 0000000..342960d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__fields__gr.html
@@ -0,0 +1,215 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Fields Level</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__svd__xml__fields__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Fields Level</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></div></div>
+<div class="contents">
+<p>All fields of a register are enclosed between the &lt;fields&gt; opening and closing tags</p>
+<p>A bit-field has a name that is unique within the register. The position and size within the register is either described by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or the lsb and the bit-width of the field. A field may define an <em>enumeratedValue</em> in order to make the display more intuitive to read. <hr/>
+ <pre><span class="mand">
+<b>&lt;fields&gt;</b></span></pre><pre><span class="mand"><b>    &lt;field <span class="opt">derivedFrom=<em>"xs:Name"</em></span>&gt;</b></span></pre><pre><span class="mand">        &lt;name&gt;<em>xs:Name</em>&lt;/name&gt;
+        &lt;description&gt;<em>xs:string</em>&lt;/description&gt;</span></pre><pre><span class="mand">        &lt;choice&gt;
+            <em> &lt;!-- bitRangeLsbMsbStyle --&gt; </em>
+            &lt;bitOffset&gt;<em>scaledNonNegativeInteger</em>&lt;bitOffset&gt;
+            &lt;bitWidth&gt;<em>scaledNonNegativeInteger</em>&lt;/bitWidth&gt;
+            <em>or</em>
+            <em> &lt;!-- bitRangeOffsetWidthStyle --&gt; </em>
+            &lt;lsb&gt;<em>scaledNonNegativeInteger</em>&lt;/lsb&gt; 
+            &lt;msb&gt;<em>scaledNonNegativeInteger</em>&lt;/msb&gt;
+            <em>or</em>
+            <em> &lt;!-- bitRangePattern --&gt; </em>
+            &lt;bitRange&gt;<em>pattern</em>&lt;/bitRange&gt;
+        &lt;/choice&gt;
+        <span class="opt">
+        &lt;access&gt;<em>accessType</em>&lt;/access&gt;
+        &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;
+        &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;
+        &lt;readAction&gt;<em>readActionType</em>&lt;/readAction&gt;</span></span></pre><pre><span class="mand"><span class="opt">        &lt;enumeratedValues&gt;
+            ...
+        &lt;/enumeratedValues&gt;</span></span></pre><pre><span class="mand">    <b>&lt;/field&gt;
+    <span class="opt">...
+    &lt;field&gt;
+       ...
+    &lt;/field&gt;
+    </span>
+&lt;fields&gt;
+</b></span>
+</pre><table  class="cmtable" summary="Field Level Schema">
+<tr>
+<th>Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>derivedFrom </td><td>The field is cloned from a previously defined field with a unique name. </td><td>xs:Name </td><td>0..1  </td></tr>
+<tr>
+<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>name </td><td>Name string used to identify the field. Field names must be unique within a register. </td><td>xs:string  </td><td>1..1   </td></tr>
+<tr>
+<td>description </td><td>String describing the details of the register.  </td><td>xs:string  </td><td>0..1   </td></tr>
+<tr class="choice">
+<td><em>Choice of</em> </td><td colspan="2">Three options exist to describe the field's bit-range. The options are to be used mutually exclusive: </td><td>1..1  </td></tr>
+<tr class="choice">
+<td colspan="4"><em>1. bitRangeLsbMsbStyle</em>   </td></tr>
+<tr class="choice">
+<td align="right">bitOffset </td><td>Value defining the position of the least significant bit of the field within the register it belongs to. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+<tr class="choice">
+<td align="right">bitWidth  </td><td>Value defining the bit-width of the bitfield within the register it belongs to.  </td><td>scaledNonNegativeInteger </td><td>0..1   </td></tr>
+<tr class="choice">
+<td colspan="4"><em>2. bitRangeOffsetWidthStyle</em>  </td></tr>
+<tr class="choice">
+<td align="right">lsb  </td><td>Value defining the bit position of the least significant bit within the register it belongs to. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+<tr class="choice">
+<td align="right">msb  </td><td>Value defining the bit position of the most significant bit within the register it belongs to.  </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
+<tr class="choice">
+<td colspan="4"><em>3. bitRangePattern</em>  </td></tr>
+<tr class="choice">
+<td align="right">bitRange  </td><td>A string in the format: "[&lt;msb&gt;:&lt;lsb&gt;]" </td><td>bitRangeType  </td><td>0..1   </td></tr>
+<tr>
+<td>access </td><td>Predefined strings can be used to define the allowed access types for this field: <span class="XML-Token">read-only<em>,</em> write-only<em>,</em> read-write<em>, </em> writeOnce<em>, and</em> read-writeOnce</span>. Can be omitted if it matches the access permission set for the parent register.  </td><td>accessType </td><td>0..1   </td></tr>
+<tr>
+<td>modifiedWriteValues </td><td>Describe the manipulation of data written to a field. If not specified, the value written to the field is the value stored in the field. The other options are bitwise operations: <ul>
+<li><span class="XML-Token">oneToClear</span>: write data bit of one shall clear (set to zero) the corresponding bit in the field. </li>
+<li><span class="XML-Token">oneToSet</span>: write data bit of one shall set (set to one) the corresponding bit in the field. </li>
+<li><span class="XML-Token">oneToToggle</span>: write data bit of one shall toggle (invert) the corresponding bit in the field. </li>
+<li><span class="XML-Token">zeroToClear</span>: write data bit of zero shall clear (set to zero) the corresponding bit in the field. </li>
+<li><span class="XML-Token">zeroToSet</span>: write data bit of zero shall set (set to one) the corresponding bit in the field. </li>
+<li><span class="XML-Token">zeroToToggle</span>: write data bit of zero shall toggle (invert) the corresponding bit in the field. </li>
+<li><span class="XML-Token">clear</span>: after a write operation all bits in the field are cleared (set to zero). </li>
+<li><span class="XML-Token">set</span>: after a write operation all bits in the field are set (set to one). </li>
+<li><span class="XML-Token">modify</span>: after a write operation all bit in the field may be modified (default).  </li>
+</ul>
+</td><td>modifiedWriteValuesType </td><td>0..1   </td></tr>
+<tr class="choice">
+<td><em>writeConstraint</em> </td><td colspan="2">Three options exist to set write-constraints: </td><td>0..1  </td></tr>
+<tr class="choice">
+<td><em>1. writeAsRead</em> </td><td>If TRUE, only the last read value can be written. </td><td>xs:boolean </td><td>0..1  </td></tr>
+<tr class="choice">
+<td nowrap="nowrap"><em>2. useEnumeratedValues</em> </td><td>If TRUE, only the values listed in the <em>enumeratedValues</em> list are considered valid write values. </td><td>xs:boolean </td><td>0..1  </td></tr>
+<tr class="choice">
+<td><em>3. range</em> </td><td>Consists of the following two elements: </td><td>&#160; </td><td>0..1  </td></tr>
+<tr class="choice">
+<td align="right">minimum </td><td>Specifies the smallest number to be written to the field. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
+<tr class="choice">
+<td align="right">maximum </td><td>Specifies the largest number to be written to the field. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
+<tr>
+<td>readAction </td><td>If set, it specifies the side effect following a read operation. If not set, the field is not modified after a read. The defined side effects are: <ul>
+<li><span class="XML-Token">clear</span>: The field is cleared (set to zero) following a read operation. </li>
+<li><span class="XML-Token">set</span>: The field is set (set to ones) following a read operation. </li>
+<li><span class="XML-Token">modify</span>: The field is modified in some way after a read operation. </li>
+<li><span class="XML-Token">modifyExternal</span>: One or more dependent resources other than the current field are immediately affected by a read operation (it is recommended that the field description specifies these dependencies). Debuggers are not expected to read this field location unless explicitly instructed by the user. </li>
+</ul>
+</td><td>readActionType </td><td>0..1 register  </td></tr>
+<tr>
+<td>enumeratedValues </td><td>Next lower level of description. See section <a class="el" href="group__svd__xml__enum__gr.html">Enumerated Values Level</a> for details. </td><td>&#160; </td><td>0..2  </td></tr>
+</table>
+<h2><a class="anchor" id="field_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">...
+&lt;field&gt;
+  &lt;name&gt;TimerCtrl0_IntSel&lt;/name&gt;
+  &lt;description&gt;Select interrupt line that is triggered by timer overflow.&lt;/description&gt;
+  &lt;bitOffset&gt;1&lt;/bitOffset&gt;
+  &lt;bitWidth&gt;3&lt;/bitWidth&gt;
+  &lt;access&gt;read-write&lt;/access&gt;
+  &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+  &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
+  &lt;writeConstraint&gt;
+    &lt;range&gt;
+      &lt;minimum&gt;0&lt;/minimum&gt;
+      &lt;maximum&gt;5&lt;/maximum&gt;
+    &lt;/range&gt;
+  &lt;/writeConstraint&gt;
+  &lt;readAction&gt;clear&lt;/readAction&gt;
+ 
+  &lt;enumeratedValues&gt;
+    ...
+  &lt;/enumeratedValues&gt;
+&lt;/field&gt;
+...
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html
new file mode 100644
index 0000000..4a26175
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html
@@ -0,0 +1,234 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Registers Level</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('group__svd__xml__registers__gr.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Registers Level</div>  </div>
+<div class="ingroups"><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></div></div>
+<div class="contents">
+<p>All registers of a peripheral are enclosed between the <b>&lt;registers&gt;</b> opening and closing tags.</p>
+<p>The description of registers is the most essential part of the SVD description. The register's name, detailed description, and the address-offset relative to the peripheral base address are the mandatory elements. If the size, access, reset value, and reset mask have not been specified on the device or peripheral level, or if the default values need to be redefined locally, these fields become mandatory.</p>
+<p>A register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics. In schema-terms the <em>fields</em> section is optional, however, from a specification perspective, fields are mandatory when they are described in the device documentation.</p>
+<p>The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the &lt;dim&gt; element. The register names can be composed by the register name and an index specific substring define in &lt;dimIndex&gt;. The &lt;dimIncrement&gt; specifies the address offset between two registers.</p>
+<hr/>
+<pre>
+<span class="mand"><b>&lt;registers&gt;</b> </span></pre><pre><span class="mand">    <b>&lt;register <span class="opt">derivedFrom=<em>registerNameType</em></span>&gt;</b>
+    <span class="opt">
+        <em>&lt;!-- dimElementGroup --&gt; </em>
+        &lt;dim&gt;<em>scaledNonNegativeInteger</em>&lt;/dim&gt;
+        &lt;dimIncrement&gt;<em>scaledNonNegativeInteger</em>&lt;/dimIncrement&gt;
+        &lt;dimIndex&gt;<em>xs:string</em>&lt;/dimIndex&gt;
+        <em>&lt;!-- end of dimElementGroup --&gt; </em>
+   </span>
+        &lt;name&gt;<em>identifierType</em>&lt;/name&gt;
+    <span class="opt">
+        &lt;displayName&gt;<em>xs:string</em>&lt;/displayName&gt;
+    </span>
+        &lt;description&gt;<em>xs:string</em>&lt;/description&gt;
+    <span class="opt">
+        &lt;alternateGroup&gt;<em>xs:Name</em>&lt;/alternateGroup&gt;
+    </span>
+        &lt;addressOffset&gt;<em>scaledNonNegativeInteger</em>&lt;/addressOffset&gt;
+    <span class="opt">
+        <em>&lt;!-- registerPropertiesGroup --&gt; </em>
+        &lt;size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;
+        &lt;access&gt;<em>accessType</em>&lt;/access&gt;
+        &lt;resetValue&gt;<em>scaledNonNegativeInteger</em>&lt;/resetValue&gt;
+        &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;
+        <em>&lt;!-- end of registerPropertiesGroup --&gt; </em>
+    </span><span class="opt">
+        &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;
+        &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;
+        &lt;readAction&gt;<em>readActionType</em>&lt;/readAction&gt;</span></span></pre><pre><span class="mand"><span class="opt">        &lt;fields&gt;
+            ...
+        &lt;/fields&gt;
+    </span>
+    <b>&lt;/register&gt;</b>
+    <span class="opt">...
+    &lt;register&gt;
+        ...
+    &lt;/register&gt;
+    </span>
+<b>&lt;registers&gt;</b> </span>
+</pre><table  class="cmtable" summary="Register Level Schema">
+<tr>
+<th>Attribute Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr>
+<td>derivedFrom </td><td>Specifies the name of the register from which to inherit the data. Elements being specified underneath will override the inherited values. <br/>
+<b>Remarks:</b> When deriving a register, it is mandatory to specify at least the name, the description, and the addressOffset. </td><td>xs:Name </td><td>0..1  </td></tr>
+<tr>
+<th>Element Name </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
+<tr class="group1">
+<td colspan="4">See <a class="el" href="group__dim_element_group__gr.html">dimElementGroup</a> for details.  </td></tr>
+<tr class="group1">
+<td align="right">dimIncrement </td><td>The value defines the number of elements in an array of registers.  </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr class="group1">
+<td align="right">dimIncrement </td><td>If <em>dim</em> is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
+<tr class="group1">
+<td align="right">dimIndex </td><td>Specifies the substrings that replaces the s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register.  </td><td>dimIndexType  </td><td>0..1   </td></tr>
+<tr>
+<td>name </td><td>Name string used to identify the register. Register names are required to be unique within the scope of a peripheral.  </td><td>registerNameType  </td><td>1..1   </td></tr>
+<tr>
+<td>displayName </td><td>When specified, the string is being used by a graphical frontend to visualize the register. Otherwise the name element is displayed. The <em>displayName</em> may contain special characters and white spaces. The place holder <b>s</b> can be used and is replaced by the <em>dimIndex</em> substring.  </td><td>xs:string  </td><td>0..1   </td></tr>
+<tr>
+<td>description </td><td>String describing the details of the register. </td><td>xs:string  </td><td>0..1   </td></tr>
+<tr>
+<td>alternateGroup  </td><td>Specifies a group name associated with all alternate register that have the same name. At the same time, it indicates that there is a register definition allocating the same absolute address in the address space. </td><td>xs:Name  </td><td>0..1   </td></tr>
+<tr>
+<td>addressOffset </td><td>Value defining the address of the register relative to the <em>baseAddress</em> defined by the peripheral of the register. </td><td>scaledNonNegativeInteger </td><td>1..1   </td></tr>
+<tr class="group1">
+<td colspan="4">See <a class="el" href="group__register_properties_group__gr.html">registerPropertiesGroup</a> for details.  </td></tr>
+<tr class="group1">
+<td align="right">size </td><td>Defines the default bit-width of any register contained in the device (implicit inheritance).  </td><td>scaledNonNegativeInteger </td><td>0..1  </td></tr>
+<tr class="group1">
+<td align="right">access </td><td>Defines the default access rights for all registers. </td><td>accessType </td><td>0..1   </td></tr>
+<tr class="group1">
+<td align="right">resetValue  </td><td>Defines the default value for all registers at RESET. </td><td>scaledNonNegativeInteger  </td><td>0..1   </td></tr>
+<tr class="group1">
+<td align="right">resetMask </td><td>Identifies which register bits have a defined reset value. </td><td>scaledNonNegativeInteger </td><td>0..1  </td></tr>
+<tr>
+<td>modifiedWriteValues </td><td>Element to describe the manipulation of data written to a register. If not specified, the value written to the field is the value stored in the field. The other options define bitwise operations: <ul>
+<li><span class="XML-Token">oneToClear</span>: write data bits of one shall clear (set to zero) the corresponding bit in the register. </li>
+<li><span class="XML-Token">oneToSet</span>: write data bits of one shall set (set to one) the corresponding bit in the register. </li>
+<li><span class="XML-Token">oneToToggle</span>: write data bits of one shall toggle (invert) the corresponding bit in the register. </li>
+<li><span class="XML-Token">zeroToClear</span>: write data bits of zero shall clear (set to zero) the corresponding bit in the register. </li>
+<li><span class="XML-Token">zeroToSet</span>: write data bits of zero shall set (set to one) the corresponding bit in the register. </li>
+<li><span class="XML-Token">zeroToToggle</span>: write data bits of zero shall toggle (invert) the corresponding bit in the register. </li>
+<li><span class="XML-Token">clear</span>: after a write operation all bits in the field are cleared (set to zero). </li>
+<li><span class="XML-Token">set</span>: after a write operation all bits in the field are set (set to one). </li>
+<li><span class="XML-Token">modify</span>: after a write operation all bit in the field may be modified (default).  </li>
+</ul>
+</td><td>modifiedWriteValuesType </td><td>0..1   </td></tr>
+<tr class="choice">
+<td><em>writeConstraint</em> </td><td colspan="2">Three options exist to set write-constraints: </td><td>0..1  </td></tr>
+<tr class="choice">
+<td><em>1. writeAsRead</em> </td><td>If TRUE, only the last read value can be written. </td><td>xs:boolean </td><td>0..1  </td></tr>
+<tr class="choice">
+<td nowrap="nowrap"><em>2. useEnumeratedValues</em> </td><td>If TRUE, only the values listed in the <em>enumeratedValues</em> list are considered valid write values. </td><td>xs:boolean </td><td>0..1  </td></tr>
+<tr class="choice">
+<td><em>3. range</em> </td><td>Consists of the following two elements: </td><td>&#160; </td><td>0..1  </td></tr>
+<tr class="choice">
+<td align="right">minimum </td><td>Specifies the smallest number to be written to the field. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
+<tr class="choice">
+<td align="right">maximum </td><td>Specifies the largest number to be written to the field. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
+<tr>
+<td>readAction  </td><td>If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are: <ul>
+<li><span class="XML-Token">clear</span>: The register is cleared (set to zero) following a read operation. </li>
+<li><span class="XML-Token">set</span>: The register is set (set to ones) following a read operation. </li>
+<li><span class="XML-Token">modify</span>: The register is modified in some way after a read operation. </li>
+<li><span class="XML-Token">modifyExternal</span>: One or more dependent resources other than the current register are immediately affected by a read operation (it is recommended that the register description specifies these dependencies). Debuggers are not expected to read this register location unless explicitly instructed by the user. </li>
+</ul>
+</td><td>readActionType </td><td><p class="starttd">0..1  </p>
+<p class="endtd"></p>
+</td></tr>
+<tr>
+<td>fields  </td><td>Next lower level of description (see <a class="el" href="group__svd__xml__fields__gr.html">Fields Level</a> for details). Not all registers are further divided into fields, therefore, this level is optional. In case a register is subdivided into bit fields, it should be reflected in the description. The device header file can only contain bit access macros and bit-field structures if this information is contained in the description. </td><td>&#160; </td><td>0..1   </td></tr>
+</table>
+<h2><a class="anchor" id="reg_ex"></a>
+Example:</h2>
+<div class="fragment"><pre class="fragment">...
+&lt;<span class="keyword">register</span>&gt;
+  &lt;name&gt;TimerCtrl0&lt;/name&gt;
+  &lt;description&gt;Timer Control Register&lt;/description&gt;
+  &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+  &lt;access&gt;read-write&lt;/access&gt;
+  &lt;resetValue&gt;0x00008001&lt;/resetValue&gt;
+  &lt;resetMask&gt;0x0000ffff&lt;/resetMask&gt;
+  &lt;size&gt;32&lt;/size&gt;
+  &lt;fields&gt;
+    ...
+  &lt;/fields&gt;
+&lt;/<span class="keyword">register</span>&gt;
+
+&lt;<span class="keyword">register</span> derivedFrom=<span class="stringliteral">&quot;TimerCtrl0&quot;</span>&gt;
+  &lt;name&gt;TimerCtrl1&lt;/name&gt;
+  &lt;description&gt;Derived Timer&lt;/description&gt;
+  &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+&lt;/<span class="keyword">register</span>&gt;
+...
+</pre></div> </div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/index.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/index.html
new file mode 100644
index 0000000..813b480
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/index.html
@@ -0,0 +1,153 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>System View Description</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li class="current"><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('index.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">System View Description </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>This chapter contains the introduction and specification of the CMSIS System View Description format (CMSIS-SVD). The introduction section outlines the objectives and benefits CMSIS-SVD.</p>
+<p><b>Introduction</b></p>
+<p>CMSIS-SVD formalizes the description of the programmer's view for the system contained in ARM Cortex-M processor-based microcontrollers, in particular the memory mapped registers of the peripherals. The detail contained in system view descriptions is comparable to what is found in device reference manuals published by silicon vendors. The information ranges from a high level functional description of a peripheral all the way down to the definition and purpose of an individual bit field in a memory mapped register. CMSIS-SVD files are developed and maintained by the silicon vendors. Silicon vendors manage their descriptions in a central, web-based Device Database and the CMSIS-SVD files are downloadable via a public web interface once they have been released by the silicon vendor. Tool vendors use these descriptions for providing device-specific debug views of peripherals in their debugger. Last but not least CMSIS compliant device header files are generated from CMSIS-SVD files.</p>
+<p><b>CMSIS-SVD Benefits</b></p>
+<ul>
+<li>The benefits for the Software Developer:<ul>
+<li>Consistency between device header file and what is being displayed by the debugger.</li>
+<li>Detailed information about peripherals, registers, fields, and bit values from within the debugger, without the need to reference device documentation.</li>
+<li>Public access via a web interface to new and updated descriptions as they become available from silicon vendors.</li>
+<li>Improved software development efficiency.</li>
+</ul>
+</li>
+</ul>
+<ul>
+<li>The benefits for the Silicon Vendor:<ul>
+<li>A tool vendor independent file format enables early device support by a wide range of toolchains with limited effort.</li>
+<li>The XML-based format helps ease the integration into in-house design flows.</li>
+<li>Automated generation of CMSIS compliant device header files.</li>
+<li>Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance via the web-based Device Database.</li>
+</ul>
+</li>
+</ul>
+<ul>
+<li>The benefits for the Tool Vendor:<ul>
+<li>Unified file format across silicon vendors helps the efficiency of supporting a wide range of new devices in a timely manner.</li>
+<li>Silicon vendors provide early review access to individuals ahead of the publishing date.</li>
+<li>Updated descriptions are available over the web simplifying the maintenance of device support.</li>
+</ul>
+</li>
+</ul>
+<p><b>The Web Infrastructure</b></p>
+<div class="image">
+<img src="CMSIS_SVD_WEB_DATABASE.png" alt="CMSIS_SVD_WEB_DATABASE.png"/>
+<div class="caption">
+CMSIS-SVD Management Processes</div></div>
+<p> The diagram illustrates the management process steps for uploading, validating, reviewing, publishing, and downloading CMSIS-SVD files.</p>
+<ul>
+<li><b>Managing Files:</b> A CMSIS-SVD file is uploaded by a silicon vendor via the web interface (<a href="https://cmsis.arm.com/user/index.php" target="_blank"><b>Device Database</b></a>). The system performs a check against the CMSIS-SVD Schema and runs the SVDConv consistency checker. Only if both checks have been successful the file will be stored in the SVD Storage. Files can be added, replaced and deleted.</li>
+</ul>
+<ul>
+<li><b>Managing Devices:</b> The silicon vendor creates an entry for each of his devices in the database by defining a name and associating it with a CMSIS-SVD file from the SVD Storage. The publishing date set forth for a device is used by the system to determine when this device becomes visible in the public device database. Prior to the publishing date, the silicon vendor can grant review access to individuals for an individual device. Reviewers get notified by e-mail about a device being made available for review.</li>
+</ul>
+<ul>
+<li><b>Public Download:</b> Public access to the silicon vendor specific CMSIS-SVD download pages is provided from <a href="http://cmsis.arm.com" target="_blank">cmsis.arm.com</a> or <a href="http://www.arm.com/cmsis" target="_blank">www.arm.com/cmsis</a>. Select the CMSIS-SVD tab and select the Silicon Vendor of interest from the list. For the public download of the CMSIS-SVD files of published devices it is mandatory to:<ul>
+<li>Be logged in on the ARM web site.</li>
+<li>Have accepted a silicon vendor specific End Users License Agreement (EULA).</li>
+</ul>
+</li>
+</ul>
+<p>More information about the web infrastructure can be found in the <a class="el" href="svd_web_pg.html">CMSIS-SVD Web Interface User Guide</a></p>
+<p><b>Language Outline</b></p>
+<ul>
+<li><a class="el" href="svd__outline_pg.html">SVD File Description</a></li>
+</ul>
+<p><b>Language Specification</b></p>
+<ul>
+<li><a class="el" href="group__svd___format__gr.html">SVD File Schema Levels</a></li>
+<li><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a> </li>
+</ul>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_f.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_f.png
new file mode 100644
index 0000000..1b07a16
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_f.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_h.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_h.png
new file mode 100644
index 0000000..01f5fa6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/nav_h.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/navtree.js b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/navtree.js
new file mode 100644
index 0000000..18ba992
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/navtree.js
@@ -0,0 +1,285 @@
+var NAVTREE =
+[
+  [ "CMSIS-SVD", "index.html", [
+    [ "System View Description", "index.html", [
+      [ "CMSIS-SVD Web Interface User Guide", "svd_web_pg.html", [
+        [ "Public Download Area", "svd_web_public_pg.html", null ],
+        [ "Restricted Management Area", "svd_web_restricted_pg.html", null ]
+      ] ],
+      [ "SVD File Description", "svd__outline_pg.html", null ]
+    ] ],
+    [ "Usage and Description", "pages.html", [
+      [ "SVD File Validation", "svd_validate_file_pg.html", null ],
+      [ "SVD File Usage", "svd__usage_pg.html", null ],
+      [ "SVD File Example", "svd__example_pg.html", null ]
+    ] ],
+    [ "Reference", "modules.html", [
+      [ "SVD File Schema Levels", "group__svd___format__gr.html", [
+        [ "Device Level", "group__svd__xml__device__gr.html", null ],
+        [ "Peripherals Level", "group__svd__xml__peripherals__gr.html", null ],
+        [ "Registers Level", "group__svd__xml__registers__gr.html", null ],
+        [ "Fields Level", "group__svd__xml__fields__gr.html", null ],
+        [ "Enumerated Values Level", "group__svd__xml__enum__gr.html", null ]
+      ] ],
+      [ "Element Groups", "group__elem__type__gr.html", [
+        [ "dimElementGroup", "group__dim_element_group__gr.html", null ],
+        [ "registerPropertiesGroup", "group__register_properties_group__gr.html", null ]
+      ] ],
+      [ "SVD Extension in Version 1.1", "group__svd___format__1__1__gr.html", [
+        [ "Extensions to the Device Section", "group__device_section_extensions__gr.html", null ],
+        [ "CPU Section (New)", "group__cpu_section__gr.html", null ],
+        [ "Extensions to the Peripheral Section", "group__peripheral_section_extensions__gr.html", null ],
+        [ "Cluster Level (New)", "group__cluster_level__gr.html", null ],
+        [ "Extensions to the Register Section", "group__register_section_extensions__gr.html", null ]
+      ] ],
+      [ "CMSIS-SVD Schema File Ver. 1.0", "group__schema__gr.html", null ],
+      [ "CMSIS-SVD Schema File Ver. 1.1 (draft)", "group__schema__1__1__gr.html", null ]
+    ] ]
+  ] ]
+];
+
+function createIndent(o,domNode,node,level)
+{
+  if (node.parentNode && node.parentNode.parentNode)
+  {
+    createIndent(o,domNode,node.parentNode,level+1);
+  }
+  var imgNode = document.createElement("img");
+  if (level==0 && node.childrenData)
+  {
+    node.plus_img = imgNode;
+    node.expandToggle = document.createElement("a");
+    node.expandToggle.href = "javascript:void(0)";
+    node.expandToggle.onclick = function() 
+    {
+      if (node.expanded) 
+      {
+        $(node.getChildrenUL()).slideUp("fast");
+        if (node.isLast)
+        {
+          node.plus_img.src = node.relpath+"ftv2plastnode.png";
+        }
+        else
+        {
+          node.plus_img.src = node.relpath+"ftv2pnode.png";
+        }
+        node.expanded = false;
+      } 
+      else 
+      {
+        expandNode(o, node, false);
+      }
+    }
+    node.expandToggle.appendChild(imgNode);
+    domNode.appendChild(node.expandToggle);
+  }
+  else
+  {
+    domNode.appendChild(imgNode);
+  }
+  if (level==0)
+  {
+    if (node.isLast)
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2plastnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2lastnode.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+    else
+    {
+      if (node.childrenData)
+      {
+        imgNode.src = node.relpath+"ftv2pnode.png";
+      }
+      else
+      {
+        imgNode.src = node.relpath+"ftv2node.png";
+        domNode.appendChild(imgNode);
+      }
+    }
+  }
+  else
+  {
+    if (node.isLast)
+    {
+      imgNode.src = node.relpath+"ftv2blank.png";
+    }
+    else
+    {
+      imgNode.src = node.relpath+"ftv2vertline.png";
+    }
+  }
+  imgNode.border = "0";
+}
+
+function newNode(o, po, text, link, childrenData, lastNode)
+{
+  var node = new Object();
+  node.children = Array();
+  node.childrenData = childrenData;
+  node.depth = po.depth + 1;
+  node.relpath = po.relpath;
+  node.isLast = lastNode;
+
+  node.li = document.createElement("li");
+  po.getChildrenUL().appendChild(node.li);
+  node.parentNode = po;
+
+  node.itemDiv = document.createElement("div");
+  node.itemDiv.className = "item";
+
+  node.labelSpan = document.createElement("span");
+  node.labelSpan.className = "label";
+
+  createIndent(o,node.itemDiv,node,0);
+  node.itemDiv.appendChild(node.labelSpan);
+  node.li.appendChild(node.itemDiv);
+
+  var a = document.createElement("a");
+  node.labelSpan.appendChild(a);
+  node.label = document.createTextNode(text);
+  a.appendChild(node.label);
+  if (link) 
+  {
+    a.href = node.relpath+link;
+  } 
+  else 
+  {
+    if (childrenData != null) 
+    {
+      a.className = "nolink";
+      a.href = "javascript:void(0)";
+      a.onclick = node.expandToggle.onclick;
+      node.expanded = false;
+    }
+  }
+
+  node.childrenUL = null;
+  node.getChildrenUL = function() 
+  {
+    if (!node.childrenUL) 
+    {
+      node.childrenUL = document.createElement("ul");
+      node.childrenUL.className = "children_ul";
+      node.childrenUL.style.display = "none";
+      node.li.appendChild(node.childrenUL);
+    }
+    return node.childrenUL;
+  };
+
+  return node;
+}
+
+function showRoot()
+{
+  var headerHeight = $("#top").height();
+  var footerHeight = $("#nav-path").height();
+  var windowHeight = $(window).height() - headerHeight - footerHeight;
+  navtree.scrollTo('#selected',0,{offset:-windowHeight/2});
+}
+
+function expandNode(o, node, imm)
+{
+  if (node.childrenData && !node.expanded) 
+  {
+    if (!node.childrenVisited) 
+    {
+      getNode(o, node);
+    }
+    if (imm)
+    {
+      $(node.getChildrenUL()).show();
+    } 
+    else 
+    {
+      $(node.getChildrenUL()).slideDown("fast",showRoot);
+    }
+    if (node.isLast)
+    {
+      node.plus_img.src = node.relpath+"ftv2mlastnode.png";
+    }
+    else
+    {
+      node.plus_img.src = node.relpath+"ftv2mnode.png";
+    }
+    node.expanded = true;
+  }
+}
+
+function getNode(o, po)
+{
+  po.childrenVisited = true;
+  var l = po.childrenData.length-1;
+  for (var i in po.childrenData) 
+  {
+    var nodeData = po.childrenData[i];
+    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
+        i==l);
+  }
+}
+
+function findNavTreePage(url, data)
+{
+  var nodes = data;
+  var result = null;
+  for (var i in nodes) 
+  {
+    var d = nodes[i];
+    if (d[1] == url) 
+    {
+      return new Array(i);
+    }
+    else if (d[2] != null) // array of children
+    {
+      result = findNavTreePage(url, d[2]);
+      if (result != null) 
+      {
+        return (new Array(i).concat(result));
+      }
+    }
+  }
+  return null;
+}
+
+function initNavTree(toroot,relpath)
+{
+  var o = new Object();
+  o.toroot = toroot;
+  o.node = new Object();
+  o.node.li = document.getElementById("nav-tree-contents");
+  o.node.childrenData = NAVTREE;
+  o.node.children = new Array();
+  o.node.childrenUL = document.createElement("ul");
+  o.node.getChildrenUL = function() { return o.node.childrenUL; };
+  o.node.li.appendChild(o.node.childrenUL);
+  o.node.depth = 0;
+  o.node.relpath = relpath;
+
+  getNode(o, o.node);
+
+  o.breadcrumbs = findNavTreePage(toroot, NAVTREE);
+  if (o.breadcrumbs == null)
+  {
+    o.breadcrumbs = findNavTreePage("index.html",NAVTREE);
+  }
+  if (o.breadcrumbs != null && o.breadcrumbs.length>0)
+  {
+    var p = o.node;
+    for (var i in o.breadcrumbs) 
+    {
+      var j = o.breadcrumbs[i];
+      p = p.children[j];
+      expandNode(o,p,true);
+    }
+    p.itemDiv.className = p.itemDiv.className + " selected";
+    p.itemDiv.id = "selected";
+    $(window).load(showRoot);
+  }
+}
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/pages.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/pages.html
new file mode 100644
index 0000000..288b35e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/pages.html
@@ -0,0 +1,102 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>Usage and Description</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('pages.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">Usage and Description</div>  </div>
+</div>
+<div class="contents">
+<div class="textblock">Here is a list of all related documentation pages:</div><ul>
+<li><a class="el" href="svd_validate_file_pg.html">SVD File Validation</a>
+</li>
+<li><a class="el" href="svd__usage_pg.html">SVD File Usage</a>
+</li>
+<li><a class="el" href="svd__example_pg.html">SVD File Example</a>
+</li>
+</ul>
+</div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html
new file mode 100644
index 0000000..31ec9e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__outline_pg.html
@@ -0,0 +1,128 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SVD File Description</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('svd__outline_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">SVD File Description </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The CMSIS-SVD format is based on XML. The specification of the System View Description format was influenced by IP-XACT, a design description format used in, for example, IP stitching and IP reuse. Due to the much wider scope and complexity of IP-XACT it was decided to specify a separate format, which is focused and tailored toward the description of the programmer's view of a device only.</p>
+<p><b>CMSIS-SVD XML Hierarchy</b></p>
+<div class="image">
+<img src="CMSIS_SVD_Schema_Gen.png" alt="CMSIS_SVD_Schema_Gen.png"/>
+<div class="caption">
+CMSIS-SVD Hierarchy Levels</div></div>
+<p> One CMSIS-SVD file contains the description of a single device. A device consists of a processor and at least one peripheral. Each peripheral contains at least one register. A register may consist of one or more fields. The range of values for a field may be further described with enumerated values.</p>
+<ul>
+<li><b>Device Level:</b> The top level of a System View Description is the device. On this level, information is captured that is specific to the device as a whole. For example, the device name, description, or version. The minimal addressable unit as well as the bit-width of the data bus are required by the debugger to perform the correct target accesses.<br/>
+ <br/>
+Default values for register attributes like register size, reset value, and access permissions can be set for the whole device on this level and are implicitly inherited by the lower levels of the description. If however specified on a lower level, the default setting from a higher level will get overruled.</li>
+</ul>
+<ul>
+<li><b>Peripherals Level:</b> A peripheral is a named collection of registers. A peripheral is mapped to a defined <em>base address</em> within the device's address space. A peripheral allocates one or more exclusive address blocks relative to its base address, such that all described registers fit into the allocated address blocks. Allocated addresses without an associated register description are automatically considered reserved. The peripheral can be assigned to a group of peripherals and may be associated with one or more interrupts.</li>
+</ul>
+<ul>
+<li><b>Registers Level:</b> A register is a named, programmable resource that belongs to a peripheral. Registers are mapped to a defined address in the address space of the device. An address is specified relative to the peripheral base address. The description of a register documents the purpose and function of the resource. A debugger requires information about the permitted access to a resource as well as side effects triggered by read and write accesses respectively.</li>
+</ul>
+<ul>
+<li><b>Fields Level:</b> Registers may be partitioned into chunks of bits of distinct functionality. A chunk is referred to as <em>field</em>. The field names within a single register must be unique. Only architecturally defined fields shall be described. Any bits not being explicitly described are treated as reserved. They are not displayed in the System Viewer and are padded in the bit fields of the device header file. The case-insensitive field named <b>"reserved"</b> is treated as a keyword and each field with this name is ignored.</li>
+</ul>
+<ul>
+<li><b>Enumerated Values Level:</b> An enumeration maps an unsigned integer constant to a descriptive identifier and, optionally, to a description string. Enumerations are used in C to enhance the readability of source code. Similarly, it can be used by debuggers to provide more instructive information to the programmer, avoiding a lookup in the device documentation.</li>
+</ul>
+<ul>
+<li><b>Vendor Extensions:</b> The CMSIS-SVD format includes a section named <em>vendorExtensions</em> positioned after the closing tag <em>peripherals</em>. This allows silicon vendors and tool partners to innovate and expand the description beyond the current specification.</li>
+</ul>
+<p><b>Multiple Instantiation</b></p>
+<p>CMSIS-SVD supports the reuse of whole sections of the description. The attribute <em>derivedFrom</em> for the peripheral-, register-, and field-section specifies the source of the section to be copied from. Individual tags can be used to redefine specific elements within a copied section. In case the name of the description source is not unique, the name needs to be qualified hierarchically until the element composite name becomes unique. Hierarchies are separated by a dot. For example, <em>&lt;peripheral name&gt;.&lt;register name&gt;.&lt;field name&gt;</em>.</p>
+<p><b>Peripheral Grouping</b></p>
+<p>Peripherals that provide similar functionality (Simple Timer, Complex Timer) can be grouped with the element <em>groupName</em>. All peripherals associated with the same group name are collectively listed under this group in the order they have been specified in the file. Collecting similar or related peripherals into peripheral groups helps structuring the list of peripherals in the debugger.</p>
+<p><b>Descriptions</b></p>
+<p>On each level, the tag <em>description</em> provides verbose information about the respective element. The description field plays an important part in improving the software development productivity as it gives instant access to information that otherwise would need to be looked up in the device documentation. </p>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+      <li class="navelem"><a class="el" href="index.html">System View Description</a>      </li>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html
new file mode 100644
index 0000000..9c1d7cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd__usage_pg.html
@@ -0,0 +1,110 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SVD File Usage</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('svd__usage_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">SVD File Usage </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p><b>System Views</b> <br/>
+ There are a number of tool vendors who are supporting the CMSIS-SVD format with their products. Refer to the tools documentation to find out how to use CMSIS-SVD descriptions with the debugger of your choice. You can download the latest versions of available CMSIS-SVD files from the <a class="el" href="svd_web_public_pg.html">Public Download Area</a> on the ARM web. <br/>
+</p>
+<p><b>Device Header File Generation (<em>&lt;device_name&gt;</em>.h):</b> <br/>
+ SVDConv generates CMSIS compliant device header files from a CMSIS-SVD description. Note that CMSIS device header files are developed and maintained by the silicon vendors. Therefore the expectation is that this conversion is only of interest to these parties. <br/>
+ In a first step, a consistency check of the description is performed. In a second step, the device header file is generated. The device header file is generated into the current directory and the file name is determined by the tag <em>name</em> on the device level from CMSIS-SVD input file. </p>
+<div class="fragment"><pre class="fragment">  SVDConv.exe myDevice.xml --generate=header 
+</pre></div><p> <br/>
+</p>
+<ul>
+<li><b>Additional options:</b> <br/>
+ This option generates bit fields in the device header file for each field description contained in the CMSIS-SVD input file. <div class="fragment"><pre class="fragment">    --fields=<span class="keyword">struct</span>
+</pre></div> <br/>
+ This option generates position and mask C-Macros for each field description contained in the CMSIS-SVD input file. <div class="fragment"><pre class="fragment">    --fields=macro
+</pre></div> </li>
+</ul>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html
new file mode 100644
index 0000000..077017c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/svd_validate_file_pg.html
@@ -0,0 +1,123 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<title>SVD File Validation</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+</script>
+
+
+</head>
+<body>
+<div id="top"><!-- do not remove this div! -->
+
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="proglogo"><img alt="CMSIS Logo" src="CMSIS_Logo_Final.png"></td>
+  
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-SVD
+   &#160;<span id="projectnumber">Version 1.10</span>
+   </div>
+   <div id="projectbrief">CMSIS System View Description</div>
+  </td>
+  
+  
+  
+ </tr>
+ </tbody>
+</table>
+</div>
+
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
+      <li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
+      <li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
+      <li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
+      <li class="current"><a href="../../SVD/html/index.html"><span>SVD</span></a></li>
+    </ul>
+</div>
+<!-- Generated by Doxygen 1.7.5.1 -->
+<script type="text/javascript" src="dynsections.js"></script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+    </ul>
+  </div>
+</div>
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+  initNavTree('svd_validate_file_pg.html','');
+</script>
+<div id="doc-content">
+<div class="header">
+  <div class="headertitle">
+<div class="title">SVD File Validation </div>  </div>
+</div>
+<div class="contents">
+<div class="textblock"><p>The quality of the available descriptions is key to the success of the CMSIS-SVD format. Aspects of quality are:</p>
+<ul>
+<li>Syntactical and structural compliance with the specified CMSIS-SVD format.</li>
+<li>Consistency and correctness.</li>
+<li>Completeness.</li>
+<li>Level of detail.</li>
+</ul>
+<p>Automated checks are done on two levels:</p>
+<ol type="1">
+<li><b>The CMSIS-SVD Schema File</b>: The schema file specifies the syntax and structure of an XML-based format. XML tools use the schema file for checking the syntactical and structural correctness of an XML file that claims compliance with a certain format. The schema file <em>CMSIS-SVD_Schema_1_0.xsd</em> can be found in the folder <b>SVD</b> of the CMSIS distribution. <br/>
+<br/>
+</li>
+<li><b>SVD Conversion Utility:</b> ARM provides the <b>SVD Utility (SVDConv.exe)</b> tool to check the semantics and consistency of the data contained in a CMSIS-SVD file. SVDConv is a command-line tool included in the CMSIS distribution. It is located in the SVD folder side by side with the CMSIS-SVD schema file. The SVDConv shall be used for checking CMSIS-SVD descriptions as well as for generating CMSIS-compliant device header files. <br/>
+<br/>
+<ul>
+<li><b>Usage Information:</b> <br/>
+ SVDConv provides usage information at the command line when invoked without arguments. <div class="fragment"><pre class="fragment"> SVDConv.exe 
+</pre></div> <br/>
+<br/>
+</li>
+<li><b>Consistency Check:</b> <br/>
+ SVDConv is performing a consistency of the CMSIS-SVD file passed as the first command-line argument. The checks go beyond syntactical tests as they can be performed using the CMSIS-SVD schema file in combination with XML validation tools. Errors and warnings are printed to the command line. <br/>
+ <div class="fragment"><pre class="fragment">  SVDConv.exe myDevice.xml 
+</pre></div> <br/>
+<br/>
+ </li>
+</ul>
+</li>
+</ol>
+</div></div>
+</div>
+  <div id="nav-path" class="navpath">
+    <ul>
+
+    <li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
+    <!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.5.1 </li>
+    -->
+    </li>
+   </ul>
+ </div>
+
+
+</body>
+</html>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_b.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_b.png
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_b.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_s.png b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_s.png
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--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Documentation/SVD/html/tab_s.png
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_math.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..7266c3e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7557 @@
+/* ----------------------------------------------------------------------   
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.   
+ *   
+ * $Date:        15. February 2012  
+ * $Revision: 	V1.1.0  
+ *   
+ * Project: 	    CMSIS DSP Library   
+ * Title:	     	arm_math.h
+ *   
+ * Description:	 Public header file for CMSIS DSP Library
+ *   
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *  
+ * Version 1.1.0 2012/02/15 
+ *    Updated with more optimizations, bug fixes and minor API changes.  
+ *  
+ * Version 1.0.10 2011/7/15 
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.  
+ *   
+ * Version 1.0.3 2010/11/29  
+ *    Re-organized the CMSIS folders and updated documentation.   
+ *    
+ * Version 1.0.2 2010/11/11   
+ *    Documentation updated.    
+ *   
+ * Version 1.0.1 2010/10/05    
+ *    Production release and review comments incorporated.   
+ *   
+ * Version 1.0.0 2010/09/20    
+ *    Production release and review comments incorporated.   
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library, 
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:  
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values. 
+   *
+   * <b>Pre-processor Macros</b> 
+   * 
+   * Each library project have differant pre-processor macros. 
+   * 
+   * - UNALIGNED_SUPPORT_DISABLE: 
+   * 
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access    
+   * 
+   * - ARM_MATH_BIG_ENDIAN: 
+   * 
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. 
+   * 
+   * - ARM_MATH_MATRIX_CHECK: 
+   * 
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices 
+   * 
+   * - ARM_MATH_ROUNDING: 
+   * 
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target.
+   * 
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.23. 
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * ARM_MATH_CM0 depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined  (__GNUC__)
+  #define __SIMD32(addr)         (*( int32_t **) & (addr))
+  #define  _SIMD32_OFFSET(addr)  (*( int32_t * )   (addr))
+#else
+  #define __SIMD32(addr)         (*(__packed                    int32_t **) & (addr))
+  #define  _SIMD32_OFFSET(addr)  (*(__packed                    int32_t * )   (addr))
+#endif 
+
+  #define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
+
+  __STATIC_INLINE  uint32_t __CLZ(q31_t data);
+
+
+  __STATIC_INLINE uint32_t __CLZ(q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+   */
+
+  __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+   */
+  __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0)
+
+  __STATIC_INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  __STATIC_INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  __STATIC_INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  __STATIC_INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Radix-2 Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+
+
+  /*----------------------------------------------------------------------
+   *		Internal functions prototypes FFT function
+   ----------------------------------------------------------------------*/
+
+  /**
+   * @brief  Core function for the floating-point CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the floating-point CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]      onebyfftLen      value of 1/fftLen.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+   * @param[in]      fftSize      length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+   * @param[in]      *pBitRevTab  points to the bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q31 CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the f32 FFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix2_butterfly_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q31 CFFT butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q15 CFFT butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q15 CFFT Inverse butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef       	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_inverse_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pCoef,
+  uint16_t twidCoefModifier);
+
+        /**  
+	 * @brief  Core function for the Radix-2 Q31 CFFT Inverse butterfly process. 
+	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
+	 * @param[in]      fftLen           length of the FFT. 
+	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
+	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
+	 * @return none. 
+	 */
+
+  void arm_radix2_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the f32 IFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]		 onebyfftLen	  1/fftLenfth
+   * @return none.
+   */
+
+  void arm_radix2_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen);
+
+                                                                /**
+   * @brief  Core function for the Q31 CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q15 CFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+
+  /**
+   * @brief  Core function for the Q15 CIFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab);
+
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q15 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q31 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief  Initialization function for the floating-point RFFT/RIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLenReal     length of the FFT.
+   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+   */
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**  
+ * @brief Convolution of floating-point sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+  
+  /**   
+   * @brief Convolution of Q15 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**  
+ * @brief Convolution of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**   
+   * @brief Convolution of Q7 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**   
+   * @brief Partial convolution of Q15 sequences.   
+   * @param[in]       *pSrcA points to the first input sequence.   
+   * @param[in]       srcALen length of the first input sequence.   
+   * @param[in]       *pSrcB points to the second input sequence.   
+   * @param[in]       srcBLen length of the second input sequence.   
+   * @param[out]      *pDst points to the block of output data   
+   * @param[in]       firstIndex is the first output sample to start with.   
+   * @param[in]       numPoints is the number of output points to be computed.   
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**   
+   * @brief Partial convolution of Q7 sequences   
+   * @param[in]       *pSrcA points to the first input sequence.   
+   * @param[in]       srcALen length of the first input sequence.   
+   * @param[in]       *pSrcB points to the second input sequence.   
+   * @param[in]       srcBLen length of the second input sequence.   
+   * @param[out]      *pDst points to the block of output data   
+   * @param[in]       firstIndex is the first output sample to start with.   
+   * @param[in]       numPoints is the number of output points to be computed.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
+   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**   
+   * @brief Correlation of Q15 sequences   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @return none.   
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**   
+   * @brief Correlation of Q7 sequences.   
+   * @param[in] *pSrcA points to the first input sequence.   
+   * @param[in] srcALen length of the first input sequence.   
+   * @param[in] *pSrcB points to the second input sequence.   
+   * @param[in] srcBLen length of the second input sequence.   
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
+   * @return none.   
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cos output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cosine output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   * 
+   * \par 
+   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.  
+   * The proportional value determines the reaction to the current error, 
+   * the integral value determines the reaction based on the sum of recent errors, 
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure 
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
+   * A separate instance structure must be defined for each PID Controller. 
+   * There are separate instance structure declarations for each of the 3 supported data types. 
+   * 
+   * \par Reset Functions 
+   * There is also an associated reset function for each data type which clears the state array. 
+   *
+   * \par Initialization Functions 
+   * There is also an associated initialization function for each data type. 
+   * The initialization function performs the following operations: 
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.   
+   * 
+   * \par 
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   *
+   * \par Fixed-Point Behavior 
+   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
+   * Refer to the function specific documentation below for usage guidelines. 
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b> 
+   * \par 
+   * The function is implemented using an internal 64-bit accumulator. 
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
+   * Thus, if the accumulator result overflows it wraps around rather than clip. 
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   */
+
+  __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b> 
+   * \par 
+   * The function is implemented using a 64-bit internal accumulator. 
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+    /* Implementation of PID controller */
+
+#ifdef ARM_MATH_CM0
+
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+#else
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+#endif
+
+#ifdef ARM_MATH_CM0
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#else
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   * 
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version 
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents 
+   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,  
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version 
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,  
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version 
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par 
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   * 
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
+   * if x is below input range and returns last value of table if x is above range.  
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (x - S->x1) / xSpacing;
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if(i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12. 
+   *
+   */
+
+
+  __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//    #if __FPU_USED
+    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+    #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+        *pOut = __builtin_sqrtf(in);
+    #else
+        *pOut = sqrtf(in);
+    #endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return none. 
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..19bad5e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,667 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     13. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0plus.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..aa20e68
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x01)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0+ system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts   */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm3.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..0173893
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1612 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4_simd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000..3bc7906
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,649 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmFunc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..3c932e0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmInstr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..597e64d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+  return(op1);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc000.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..39ee60c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for SC000 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc300.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..7e56b0f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1583 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.01
+ * @date     22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/README.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/README.txt
new file mode 100644
index 0000000..9b92ccc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/README.txt
@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2012 ARM Limited. All rights reserved.  
+* 
+* Date:        07 March 2012  
+* Revision:    V3.01 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample.svd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample.svd
new file mode 100644
index 0000000..03db1d4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample.svd
@@ -0,0 +1,739 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+  Copyright (C) 2012 ARM Limited. All rights reserved.
+
+  Purpose: System Viewer Description (SVD) Example (Schema Version 1.0)
+           This is a description of a none-existent and incomplete device
+           for demonstration purposes only.
+ -->
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>ARMCM3xxx</name>                                          <!-- name of part or part series -->
+  <version>1.0</version>                                          <!-- version of this description -->
+  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
+  <width>32</width>                                               <!-- bus width is 32 bits -->
+  <!-- default settings implicitly inherited by subsequent sections -->
+  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
+                                                                       and register that do not define "size" themselves -->
+  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
+  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
+  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->
+
+  <peripherals>
+    <!-- Timer 0 -->
+    <peripheral>
+      <name>TIMER0</name>
+      <version>1.0</version>
+      <description>32 Timer / Counter, counting up or down from different sources</description>
+      <groupName>TIMER</groupName>
+      <baseAddress>0x40010000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+
+      <interrupt>
+        <name>TIMER0</name>
+        <value>0</value>
+      </interrupt>
+
+      <registers>
+      <!-- CR: Control Register -->
+        <register>
+          <name>CR</name>
+          <description>Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x1337F7F</resetMask>
+
+          <fields>
+            <!-- EN: Enable -->
+            <field>
+              <name>EN</name>
+              <description>Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Timer is disabled and does not operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer is enabled and can operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Reset -->
+            <field>
+              <name>RST</name>
+              <description>Reset Timer</description>
+              <bitRange>[1:1]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Reserved</name>
+                  <description>Write as ZERO if necessary</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reset_Timer</name>
+                  <description>Reset the Timer</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNT: Counting Direction -->
+            <field>
+              <name>CNT</name>
+              <description>Counting direction</description>
+              <bitRange>[3:2]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Count_UP</name>
+                  <description>Timer Counts UO and wraps, if no STOP condition is set</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Count_DOWN</name>
+                  <description>Timer Counts DOWN and wraps, if no STOP condition is set</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Toggle</name>
+                  <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Operation Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Continous</name>
+                  <description>Timer runs continously</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register and stops</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- PSC: Use Prescaler -->
+            <field>
+              <name>PSC</name>
+              <description>Use Prescaler</description>
+              <bitRange>[7:7]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Prescaler is not used</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Prescaler is used as divider</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNTSRC: Timer / Counter Soruce Divider -->
+            <field>
+              <name>CNTSRC</name>
+              <description>Timer / Counter Source Divider</description>
+              <bitRange>[11:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CAP_SRC</name>
+                  <description>Capture Source is used directly</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div2</name>
+                  <description>Capture Source is divided by 2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div4</name>
+                  <description>Capture Source is divided by 4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div8</name>
+                  <description>Capture Source is divided by 8</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div16</name>
+                  <description>Capture Source is divided by 16</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div32</name>
+                  <description>Capture Source is divided by 32</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div64</name>
+                  <description>Capture Source is divided by 64</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div128</name>
+                  <description>Capture Source is divided by 128</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div256</name>
+                  <description>Capture Source is divided by 256</description>
+                  <value>8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPSRC: Timer / COunter Capture Source -->
+            <field>
+              <name>CAPSRC</name>
+              <description>Timer / Counter Capture Source</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CClk</name>
+                  <description>Core Clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_0</name>
+                  <description>GPIO A, PIN 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_1</name>
+                  <description>GPIO A, PIN 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_2</name>
+                  <description>GPIO A, PIN 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_3</name>
+                  <description>GPIO A, PIN 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_4</name>
+                  <description>GPIO A, PIN 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_5</name>
+                  <description>GPIO A, PIN 5</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_6</name>
+                  <description>GPIO A, PIN 6</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_7</name>
+                  <description>GPIO A, PIN 7</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_0</name>
+                  <description>GPIO B, PIN 0</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_1</name>
+                  <description>GPIO B, PIN 1</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_2</name>
+                  <description>GPIO B, PIN 2</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_3</name>
+                  <description>GPIO B, PIN 3</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_0</name>
+                  <description>GPIO C, PIN 0</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_5</name>
+                  <description>GPIO C, PIN 1</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_6</name>
+                  <description>GPIO C, PIN 2</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPEDGE: Capture Edge -->
+            <field>
+              <name>CAPEDGE</name>
+              <description>Capture Edge, select which Edge should result in a counter increment or decrement</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Only rising edges result in a counter increment or decrement</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Only falling edges  result in a counter increment or decrement</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Rising and falling edges result in a counter increment or decrement</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- TRGEXT: Triggers an other Peripheral -->
+            <field>
+              <name>TRGEXT</name>
+              <description>Triggers an other Peripheral</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No Trigger is emitted</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA1</name>
+                  <description>DMA Controller 1 is triggered, dependant on MODE</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA2</name>
+                  <description>DMA Controller 2 is triggered, dependant on MODE</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UART</name>
+                  <description>UART is triggered, dependant on MODE</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- Reload: Selects Reload Register n -->
+            <field>
+              <name>RELOAD</name>
+              <description>Select RELOAD Register n to reload Timer on condition</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Selects Reload Register number 0</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Selects Reload Register number 1</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Selects Reload Register number 2</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Selects Reload Register number 3</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- IDR: Inc or dec Reload Register Selection -->
+            <field>
+              <name>IDR</name>
+              <description>Selects, if Reload Register number is incremented, decremented or not modified</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>KEEP</name>
+                  <description>Reload Register number does not change automatically</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INCREMENT</name>
+                  <description>Reload Register number is incremented on each match</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DECREMENT</name>
+                  <description>Reload Register number is decremented on each match</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- START: Starts / Stops the Timer/Counter -->
+            <field>
+              <name>S</name>
+              <description>Starts and Stops the Timer / Counter</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Timer / Counter is stopped</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Timer / Counter is started</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- SR: Status Register -->
+        <register>
+          <name>SR</name>
+          <description>Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xD701</resetMask>
+
+          <fields>
+            <!-- RUN: Shows if Timer is running -->
+            <field>
+              <name>RUN</name>
+              <description>Shows if Timer is running or not</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Stopped</name>
+                  <description>Timer is not running</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Running</name>
+                  <description>Timer is running</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MATCH: Shows if a Match was hit -->
+            <field>
+              <name>MATCH</name>
+              <description>Shows if the MATCH was hit</description>
+              <bitRange>[8:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Match</name>
+                  <description>The MATCH condition was not hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Match_Hit</name>
+                  <description>The MATCH condition was hit</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- UN: Shows if an underflow occured -->
+            <field>
+              <name>UN</name>
+              <description>Shows if an underflow occured. This flag is sticky</description>
+              <bitRange>[9:9]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Underflow</name>
+                  <description>No underflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>A minimum of one underflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- OV: Shows if an overflow occured -->
+            <field>
+              <name>OV</name>
+              <description>Shows if an overflow occured. This flag is sticky</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Overflow</name>
+                  <description>No overflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow_occured</name>
+                  <description>A minimum of one overflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Shows if Timer is in RESET state -->
+            <field>
+              <name>RST</name>
+              <description>Shows if Timer is in RESET state</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Ready</name>
+                  <description>Timer is not in RESET state and can operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>In_Reset</name>
+                  <description>Timer is in RESET state and can not operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RELOAD: Shows the currently active Reload Register -->
+            <field>
+              <name>RELOAD</name>
+              <description>Shows the currently active RELOAD Register</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Reload Register number 0 is active</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Reload Register number 1 is active</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Reload Register number 2 is active</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Reload Register number 3 is active</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- INT: Interrupt Register -->
+        <register>
+          <name>INT</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x0771</resetMask>
+
+          <fields>
+            <!-- EN: Interrupt Enable -->
+            <field>
+              <name>EN</name>
+              <description>Interrupt Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Timer does not generate Interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer triggers the TIMERn Interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Interrupt Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Match</name>
+                  <description>Timer generates an Interrupt when the MATCH condition is hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>Timer generates an Interrupt when it underflows</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow</name>
+                  <description>Timer generates an Interrupt when it overflows</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- COUNT: Counter Register -->
+        <register>
+          <name>COUNT</name>
+          <description>The Counter Register reflects the actual Value of the Timer/Counter</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+        <!-- MATCH: Match Register -->
+        <register>
+          <name>MATCH</name>
+          <description>The Match Register stores the compare Value for the MATCH condition</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Read Register -->
+        <register>
+          <name>PRESCALE_RD</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Write Register -->
+        <register>
+          <name>PRESCALE_WR</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+
+        <!-- RELOAD: Array of Reload Register with 4 elements-->
+        <register>
+          <dim>4</dim>
+          <dimIncrement>4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>RELOAD[%s]</name>
+          <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+
+    <!-- Timer 1 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER1</name>
+      <baseAddress>0x40010100</baseAddress>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>4</value>
+      </interrupt>
+    </peripheral>
+
+    <!-- Timer 2 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER2</name>
+      <baseAddress>0x40010200</baseAddress>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>6</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd
new file mode 100644
index 0000000..b71d48b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/ARM_Sample_1_1.svd
@@ -0,0 +1,763 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!-- File naming: <vendor>_<part/series name>.svd -->
+
+<!--
+  Copyright (C) 2012 ARM Limited. All rights reserved.
+
+  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
+           This is a description of a none-existent and incomplete device
+		   for demonstration purposes only.
+ -->
+ 
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
+  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->
+  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->
+  <name>ARMCM3xxx</name>                                          <!-- name of part-->
+  <series>ARMCM3</series>                                         <!-- device series the device belongs to -->
+  <version>1.2</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
+  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>
+  <licenseText>                                                   <!-- this license text will appear in header file. \n force line breaks -->
+    ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+    processor based microcontroller, but can be equally used for other\n
+    suitable  processor architectures. This file can be freely distributed.\n
+    Modifications to this file shall be clearly marked.\n
+    \n
+    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+  </licenseText>
+  <cpu>                                                           <!-- details about the cpu embedded in the device -->
+    <name>CM3</name>
+    <revision>r1p0</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
+  <width>32</width>                                               <!-- bus width is 32 bits -->
+  <!-- default settings implicitly inherited by subsequent sections -->
+  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
+                                                                       and register that do not define "size" themselves -->
+  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
+  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
+  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->
+
+  <peripherals>
+    <!-- Timer 0 -->
+    <peripheral>
+      <name>TIMER0</name>
+      <version>1.0</version>
+      <description>32 Timer / Counter, counting up or down from different sources</description>
+      <groupName>TIMER</groupName>
+      <baseAddress>0x40010000</baseAddress>
+      <size>32</size>
+      <access>read-write</access>
+
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x100</size>
+        <usage>registers</usage>
+      </addressBlock>
+
+      <interrupt>
+        <name>TIMER0</name>
+        <value>0</value>
+      </interrupt>
+
+      <registers>
+      <!-- CR: Control Register -->
+        <register>
+          <name>CR</name>
+          <description>Control Register</description>
+          <addressOffset>0x00</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x1337F7F</resetMask>
+
+          <fields>
+            <!-- EN: Enable -->
+            <field>
+              <name>EN</name>
+              <description>Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disable</name>
+                  <description>Timer is disabled and does not operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer is enabled and can operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Reset -->
+            <field>
+              <name>RST</name>
+              <description>Reset Timer</description>
+              <bitRange>[1:1]</bitRange>
+              <access>write-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Reserved</name>
+                  <description>Write as ZERO if necessary</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reset_Timer</name>
+                  <description>Reset the Timer</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNT: Counting Direction -->
+            <field>
+              <name>CNT</name>
+              <description>Counting direction</description>
+              <bitRange>[3:2]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Count_UP</name>
+                  <description>Timer Counts UO and wraps, if no STOP condition is set</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Count_DOWN</name>
+                  <description>Timer Counts DOWN and wraps, if no STOP condition is set</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Toggle</name>
+                  <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Operation Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Operation Mode</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Continous</name>
+                  <description>Timer runs continously</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Single_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register and stops</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_ZERO_MAX</name>
+                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Reload_MATCH</name>
+                  <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description>
+                  <value>4</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- PSC: Use Prescaler -->
+            <field>
+              <name>PSC</name>
+              <description>Use Prescaler</description>
+              <bitRange>[7:7]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Prescaler is not used</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enabled</name>
+                  <description>Prescaler is used as divider</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CNTSRC: Timer / Counter Soruce Divider -->
+            <field>
+              <name>CNTSRC</name>
+              <description>Timer / Counter Source Divider</description>
+              <bitRange>[11:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CAP_SRC</name>
+                  <description>Capture Source is used directly</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div2</name>
+                  <description>Capture Source is divided by 2</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div4</name>
+                  <description>Capture Source is divided by 4</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div8</name>
+                  <description>Capture Source is divided by 8</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div16</name>
+                  <description>Capture Source is divided by 16</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div32</name>
+                  <description>Capture Source is divided by 32</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div64</name>
+                  <description>Capture Source is divided by 64</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div128</name>
+                  <description>Capture Source is divided by 128</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CAP_SRC_div256</name>
+                  <description>Capture Source is divided by 256</description>
+                  <value>8</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPSRC: Timer / COunter Capture Source -->
+            <field>
+              <name>CAPSRC</name>
+              <description>Timer / Counter Capture Source</description>
+              <bitRange>[15:12]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>CClk</name>
+                  <description>Core Clock</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_0</name>
+                  <description>GPIO A, PIN 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_1</name>
+                  <description>GPIO A, PIN 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_2</name>
+                  <description>GPIO A, PIN 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_3</name>
+                  <description>GPIO A, PIN 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_4</name>
+                  <description>GPIO A, PIN 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_5</name>
+                  <description>GPIO A, PIN 5</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_6</name>
+                  <description>GPIO A, PIN 6</description>
+                  <value>7</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOA_7</name>
+                  <description>GPIO A, PIN 7</description>
+                  <value>8</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_0</name>
+                  <description>GPIO B, PIN 0</description>
+                  <value>9</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_1</name>
+                  <description>GPIO B, PIN 1</description>
+                  <value>10</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_2</name>
+                  <description>GPIO B, PIN 2</description>
+                  <value>11</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOB_3</name>
+                  <description>GPIO B, PIN 3</description>
+                  <value>12</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_0</name>
+                  <description>GPIO C, PIN 0</description>
+                  <value>13</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_5</name>
+                  <description>GPIO C, PIN 1</description>
+                  <value>14</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>GPIOC_6</name>
+                  <description>GPIO C, PIN 2</description>
+                  <value>15</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- CAPEDGE: Capture Edge -->
+            <field>
+              <name>CAPEDGE</name>
+              <description>Capture Edge, select which Edge should result in a counter increment or decrement</description>
+              <bitRange>[17:16]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RISING</name>
+                  <description>Only rising edges result in a counter increment or decrement</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>FALLING</name>
+                  <description>Only falling edges  result in a counter increment or decrement</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>BOTH</name>
+                  <description>Rising and falling edges result in a counter increment or decrement</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- TRGEXT: Triggers an other Peripheral -->
+            <field>
+              <name>TRGEXT</name>
+              <description>Triggers an other Peripheral</description>
+              <bitRange>[21:20]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>NONE</name>
+                  <description>No Trigger is emitted</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA1</name>
+                  <description>DMA Controller 1 is triggered, dependant on MODE</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DMA2</name>
+                  <description>DMA Controller 2 is triggered, dependant on MODE</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>UART</name>
+                  <description>UART is triggered, dependant on MODE</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- Reload: Selects Reload Register n -->
+            <field>
+              <name>RELOAD</name>
+              <description>Select RELOAD Register n to reload Timer on condition</description>
+              <bitRange>[25:24]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Selects Reload Register number 0</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Selects Reload Register number 1</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Selects Reload Register number 2</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Selects Reload Register number 3</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- IDR: Inc or dec Reload Register Selection -->
+            <field>
+              <name>IDR</name>
+              <description>Selects, if Reload Register number is incremented, decremented or not modified</description>
+              <bitRange>[27:26]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>KEEP</name>
+                  <description>Reload Register number does not change automatically</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INCREMENT</name>
+                  <description>Reload Register number is incremented on each match</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DECREMENT</name>
+                  <description>Reload Register number is decremented on each match</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- START: Starts / Stops the Timer/Counter -->
+            <field>
+              <name>S</name>
+              <description>Starts and Stops the Timer / Counter</description>
+              <bitRange>[31:31]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>STOP</name>
+                  <description>Timer / Counter is stopped</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>START</name>
+                  <description>Timer / Counter is started</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- SR: Status Register -->
+        <register>
+          <name>SR</name>
+          <description>Status Register</description>
+          <addressOffset>0x04</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xD701</resetMask>
+
+          <fields>
+            <!-- RUN: Shows if Timer is running -->
+            <field>
+              <name>RUN</name>
+              <description>Shows if Timer is running or not</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Stopped</name>
+                  <description>Timer is not running</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Running</name>
+                  <description>Timer is running</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MATCH: Shows if a Match was hit -->
+            <field>
+              <name>MATCH</name>
+              <description>Shows if the MATCH was hit</description>
+              <bitRange>[8:8]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Match</name>
+                  <description>The MATCH condition was not hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Match_Hit</name>
+                  <description>The MATCH condition was hit</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- UN: Shows if an underflow occured -->
+            <field>
+              <name>UN</name>
+              <description>Shows if an underflow occured. This flag is sticky</description>
+              <bitRange>[9:9]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Underflow</name>
+                  <description>No underflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>A minimum of one underflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- OV: Shows if an overflow occured -->
+            <field>
+              <name>OV</name>
+              <description>Shows if an overflow occured. This flag is sticky</description>
+              <bitRange>[10:10]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>No_Overflow</name>
+                  <description>No overflow occured since last clear</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow_occured</name>
+                  <description>A minimum of one overflow occured since last clear</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RST: Shows if Timer is in RESET state -->
+            <field>
+              <name>RST</name>
+              <description>Shows if Timer is in RESET state</description>
+              <bitRange>[12:12]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Ready</name>
+                  <description>Timer is not in RESET state and can operate</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>In_Reset</name>
+                  <description>Timer is in RESET state and can not operate</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- RELOAD: Shows the currently active Reload Register -->
+            <field>
+              <name>RELOAD</name>
+              <description>Shows the currently active RELOAD Register</description>
+              <bitRange>[15:14]</bitRange>
+              <access>read-only</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>RELOAD0</name>
+                  <description>Reload Register number 0 is active</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD1</name>
+                  <description>Reload Register number 1 is active</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD2</name>
+                  <description>Reload Register number 2 is active</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RELOAD3</name>
+                  <description>Reload Register number 3 is active</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- INT: Interrupt Register -->
+        <register>
+          <name>INT</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>16</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0x0771</resetMask>
+
+          <fields>
+            <!-- EN: Interrupt Enable -->
+            <field>
+              <name>EN</name>
+              <description>Interrupt Enable</description>
+              <bitRange>[0:0]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Disabled</name>
+                  <description>Timer does not generate Interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Enable</name>
+                  <description>Timer triggers the TIMERn Interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+
+            <!-- MODE: Interrupt Mode -->
+            <field>
+              <name>MODE</name>
+              <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description>
+              <bitRange>[6:4]</bitRange>
+              <access>read-write</access>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>Match</name>
+                  <description>Timer generates an Interrupt when the MATCH condition is hit</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Underflow</name>
+                  <description>Timer generates an Interrupt when it underflows</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>Overflow</name>
+                  <description>Timer generates an Interrupt when it overflows</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+
+        <!-- COUNT: Counter Register -->
+        <register>
+          <name>COUNT</name>
+          <description>The Counter Register reflects the actual Value of the Timer/Counter</description>
+          <addressOffset>0x20</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+        <!-- MATCH: Match Register -->
+        <register>
+          <name>MATCH</name>
+          <description>The Match Register stores the compare Value for the MATCH condition</description>
+          <addressOffset>0x24</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Read Register -->
+        <register>
+          <name>PRESCALE_RD</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>read-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+        
+        <!-- PRESCALE: Prescale Write Register -->
+        <register>
+          <name>PRESCALE_WR</name>
+          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>
+          <addressOffset>0x28</addressOffset>
+          <size>32</size>
+          <access>write-only</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+
+
+        <!-- RELOAD: Array of Reload Register with 4 elements-->
+        <register>
+          <dim>4</dim>
+          <dimIncrement>4</dimIncrement>
+          <dimIndex>0,1,2,3</dimIndex>
+          <name>RELOAD[%s]</name>
+          <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>32</size>
+          <access>read-write</access>
+          <resetValue>0x00000000</resetValue>
+          <resetMask>0xFFFFFFFF</resetMask>
+        </register>
+      </registers>
+    </peripheral>
+
+    <!-- Timer 1 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER1</name>
+      <baseAddress>0x40010100</baseAddress>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>4</value>
+      </interrupt>
+    </peripheral>
+
+    <!-- Timer 2 -->
+    <peripheral derivedFrom="TIMER0">
+      <name>TIMER2</name>
+      <baseAddress>0x40010200</baseAddress>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>6</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 0000000..ceabcb0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,274 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @date: 07.12.2011
+  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
+  
+  <xs:simpleType name="registerNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="xs:string"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <xs:element name="name" type="xs:string"/>
+        <xs:element name="version" type="xs:string"/>
+        <xs:element name="description" type="xs:string"/>
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+                <xs:complexType>
+                  <xs:sequence>
+                    <xs:element name="name" type="xs:Name"/>
+                    <xs:element name="version" type="xs:string" minOccurs="0"/>
+                    <xs:element name="description" type="xs:string" minOccurs="0"/>
+                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
+                    <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
+                    <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+                    <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
+                      <xs:complexType>
+                        <xs:sequence>
+                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+                            <xs:complexType>
+                              <xs:sequence>
+                                <xs:group ref="dimElementGroup" minOccurs="0"/>
+                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+                                <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
+                                  <xs:complexType>
+                                    <xs:sequence>
+                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+                                      <xs:complexType>
+                                        <xs:sequence>
+                                          <xs:element name="name" type="xs:string"/>
+                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                          <xs:choice>
+                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+                                          </xs:choice>
+                                          <xs:element name="access" type="accessType" minOccurs="0"/>
+                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+                                            <xs:complexType>
+                                              <xs:sequence>
+                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
+                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+                                                  <xs:complexType>
+                                                    <xs:sequence>
+                                                      <xs:element name="name" type="xs:string"/>
+                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
+                                                      <xs:choice>
+                                                        <xs:element name="value" type="enumeratedValueDataType"/>
+                                                        <xs:element name="isDefault" type="xs:boolean"/>
+                                                      </xs:choice>
+                                                    </xs:sequence>
+                                                  </xs:complexType>
+                                                </xs:element>
+                                              </xs:sequence>
+                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                            </xs:complexType>
+                                          </xs:element>
+                                        </xs:sequence>
+                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                                      </xs:complexType>
+                                    </xs:element>
+                                    </xs:sequence>
+                                  </xs:complexType>
+                                </xs:element>
+                              </xs:sequence>
+                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                            </xs:complexType>
+                          </xs:element>
+                        </xs:sequence>
+                      </xs:complexType>
+                    </xs:element>
+                  </xs:sequence>
+                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+                </xs:complexType>
+              </xs:element>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd
new file mode 100644
index 0000000..b42f73c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/SVD/CMSIS-SVD_Schema_1_1_draft.xsd
@@ -0,0 +1,509 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- 
+  @note    Copyright (C) 2011-2012 ARM Limited. All rights reserved.
+  @par
+   ARM Limited (ARM) is supplying this software for use with Cortex-M
+   processor based microcontroller, but can be equally used for other
+   suitable  processor architectures. This file can be freely distributed.
+   Modifications to this file shall be clearly marked.
+
+  @date: 12.03.2012
+
+  @par
+   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+  This is a draft for CMSIS-SVD version 1.1
+  For backward compatibility all additional tags have been made optional.
+  Extensions may be mandatory for successful device header file generation
+  Other changes are related to some restructuring of the schema.
+  
+  Note that the memory section has been removed since this would limit the
+  reuse of descriptions for a series of devices.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.1">
+  <!-- stringType requires a none empty string of a least one character length -->
+  <xs:simpleType name="stringType">
+    <xs:restriction base="xs:string">
+      <xs:minLength value="1"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
+  <xs:simpleType name="cpuNameType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="CM0"/>
+      <xs:enumeration value="CM0PLUS"/>
+      <xs:enumeration value="CM0+"/>
+      <xs:enumeration value="SC000"/>
+      <xs:enumeration value="CM3"/>
+      <xs:enumeration value="SC300"/>
+      <xs:enumeration value="CM4"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->
+  <xs:simpleType name="revisionType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="r[0-9]p[0-9]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->
+  <xs:simpleType name="endianType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="little"/>
+      <xs:enumeration value="big"/>
+      <xs:enumeration value="selectable"/>
+      <xs:enumeration value="other"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->
+  <xs:simpleType name="dataTypeType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="uint8_t"/>
+      <xs:enumeration value="uint16_t"/>
+      <xs:enumeration value="uint32_t"/>
+      <xs:enumeration value="uint64_t"/>
+      <xs:enumeration value="int8_t"/>
+      <xs:enumeration value="int16_t"/>
+      <xs:enumeration value="int32_t"/>
+      <xs:enumeration value="int64_t"/>
+      <xs:enumeration value="uint8_t *"/>
+      <xs:enumeration value="uint16_t *"/>
+      <xs:enumeration value="uint32_t *"/>
+      <xs:enumeration value="uint64_t *"/>
+      <xs:enumeration value="int8_t *"/>
+      <xs:enumeration value="int16_t *"/>
+      <xs:enumeration value="int32_t *"/>
+      <xs:enumeration value="int64_t *"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels -->
+  <xs:simpleType name="nvicPrioBitsType">
+    <xs:restriction base="xs:integer">
+      <xs:minInclusive value="2"/>
+      <xs:maxInclusive value="8"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="identifierType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. -->
+  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->
+  <xs:simpleType name="enumerationNameType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[_A-Za-z0-9]*"/>
+    </xs:restriction>
+  </xs:simpleType>
+
+  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->
+  <xs:simpleType name="dimIndexType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format -->
+  <xs:simpleType name="scaledNonNegativeInteger">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->
+  <xs:simpleType name="enumeratedValueDataType">
+    <xs:restriction base="xs:string">
+      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- accessType specfies the pre-defined tokens for the available accesses -->
+  <xs:simpleType name="accessType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read-only"/>
+      <xs:enumeration value="write-only"/>
+      <xs:enumeration value="read-write"/>
+      <xs:enumeration value="writeOnce"/>
+      <xs:enumeration value="read-writeOnce"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->
+  <xs:simpleType name="modifiedWriteValuesType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="oneToClear"/>
+      <xs:enumeration value="oneToSet"/>
+      <xs:enumeration value="oneToToggle"/>
+      <xs:enumeration value="zeroToClear"/>
+      <xs:enumeration value="zeroToSet"/>
+      <xs:enumeration value="zeroToToggle"/>
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- readAction type specifies the pre-defined tokens for read side effects -->
+  <xs:simpleType name="readActionType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="clear"/>
+      <xs:enumeration value="set"/>
+      <xs:enumeration value="modify"/>
+      <xs:enumeration value="modifyExternal"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->
+  <xs:simpleType name="enumUsageType">
+    <xs:restriction base="xs:token">
+      <xs:enumeration value="read"/>
+      <xs:enumeration value="write"/>
+      <xs:enumeration value="read-write"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->
+  <xs:simpleType name="bitRangeType">
+    <xs:restriction base="xs:token">
+      <xs:pattern value="\[([0-4])?[0-9]:([0-4])?[0-9]\]"/>
+    </xs:restriction>
+  </xs:simpleType>
+  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->
+  <xs:complexType name="writeConstraintType">
+    <xs:choice>
+      <xs:element name="writeAsRead" type="xs:boolean"/>
+      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+      <xs:element name="range">
+        <xs:complexType>
+          <xs:sequence>
+            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:choice>
+  </xs:complexType>
+  <!-- addressBlockType specifies the elements to describe an address block -->
+  <xs:complexType name="addressBlockType">
+    <xs:sequence>
+      <xs:element name="offset" type="scaledNonNegativeInteger"/>
+      <xs:element name="size" type="scaledNonNegativeInteger"/>
+      <xs:element name="usage">
+        <xs:simpleType>
+          <xs:restriction base="xs:token">
+            <xs:enumeration value="registers"/>
+            <xs:enumeration value="buffer"/>
+            <xs:enumeration value="reserved"/>
+          </xs:restriction>
+        </xs:simpleType>
+      </xs:element>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->
+  <xs:complexType name="interruptType">
+    <xs:sequence>
+      <xs:element name="name" type="stringType"/>
+      <xs:element name="description" type="xs:string" minOccurs="0"/>
+      <xs:element name="value" type="xs:integer"/>
+    </xs:sequence>
+  </xs:complexType>
+  <!-- register properties group specifies register size, access permission and reset value 
+       this is used in multiple locations. Settings are inherited downstream. -->  
+  <xs:group name="registerPropertiesGroup">
+    <xs:sequence>
+      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+       by specifying the least significant and the most significant bit position -->
+  <xs:group name="bitRangeLsbMsbStyle">
+    <xs:sequence>
+      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
+      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
+    </xs:sequence>
+  </xs:group>
+  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register
+       by specifying the least significant bit position and the bitWidth of the field -->
+  <xs:group name="bitRangeOffsetWidthStyle">
+    <xs:sequence>
+      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
+    </xs:sequence> 
+  </xs:group>
+  <!-- dimElementGroup specifies the number of array elements (dim), the address offset
+       between to consecutive array elements and an a comma seperated list of strings 
+       being used for identifying each element in the array -->
+  <xs:group name="dimElementGroup">
+    <xs:sequence>
+      <xs:element name="dim" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+    </xs:sequence>
+  </xs:group>
+
+  <xs:complexType name="cpuType">
+    <xs:sequence>
+      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->
+      <xs:element name="name" type="cpuNameType"/>
+      <!-- V1.1: ARM defined revision of the cpu -->
+      <xs:element name="revision" type="revisionType"/>
+      <!-- V1.1: Endian specifies the endianess of the processor/device -->
+      <xs:element name="endian" type="endianType"/>
+      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->
+      <xs:element name="mpuPresent" type="xs:boolean"/>
+      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->
+      <xs:element name="fpuPresent" type="xs:boolean"/>
+      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller
+                   for defining the priority level = # priority levels -->
+      <xs:element name="nvicPrioBits" type="scaledNonNegativeInteger"/>
+      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device 
+                   instead of the ARM specified SysTickTimer -->
+      <xs:element name="vendorSystickConfig" type="xs:boolean"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="enumeratedValuesType">
+    <xs:sequence>
+      <!-- name specfies a reference to this enumeratedValues section for reuse purposes
+           this name does not appear in the System Viewer nor the Header File. -->
+      <xs:element name="name" type="enumerationNameType" minOccurs="0"/>
+      <!-- usage specifies whether this enumeration is to be used for read or write or 
+                                                       (read and write) accesses -->
+      <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+      <!-- enumeratedValue derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+        <xs:complexType>
+          <xs:sequence>
+            <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->
+            <xs:element name="name" type="enumerationNameType"/>
+            <!-- description contains the details about the semantics/behavior specified by this value -->
+            <xs:element name="description" type="stringType" minOccurs="0"/>
+            <xs:choice>
+              <xs:element name="value" type="enumeratedValueDataType"/>
+              <!-- isDefault specifies the name and description for all values that are not
+                   specifically described individually -->
+              <xs:element name="isDefault" type="xs:boolean"/>
+            </xs:choice>
+          </xs:sequence>
+        </xs:complexType>
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldType">
+    <xs:sequence>
+      <!-- name specifies a field's name. The System Viewer and the device header file will
+           use the name of the field as identifier -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- description contains reference manual level information about the function and 
+           options of a field -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- alternative specifications of the bit position of the field within the register -->
+      <xs:choice minOccurs="1" maxOccurs="1">
+        <!-- bit field described by lsb followed by msb tag -->
+        <xs:group ref="bitRangeLsbMsbStyle"/>
+        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->
+        <xs:group ref="bitRangeOffsetWidthStyle"/>
+        <!-- bit field described by [<msb>:<lsb>] -->
+        <xs:element name="bitRange" type="bitRangeType"/>
+      </xs:choice>
+      <!-- access describes the predefined permissions for the field. -->
+      <xs:element name="access" type="accessType" minOccurs="0"/>
+      <!-- predefined description of write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeContstraint specifies the subrange of allowed values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAction specifies the read side effects. -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- enumeratedValues derivedFrom=<identifierType> -->
+      <xs:element name="enumeratedValues" type="enumeratedValuesType" minOccurs="0" maxOccurs="2">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <xs:complexType name="fieldsType">
+    <xs:sequence>
+      <!-- field derivedFrom=<identifierType> -->
+      <xs:element name="field" type="fieldType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+  </xs:complexType>
+
+  <xs:complexType name="registerType">
+    <xs:sequence>
+      <xs:group    ref="dimElementGroup" minOccurs="0"/>
+      <!-- name specifies the name of the register. The register name is used by System Viewer and
+                                     device header file generator to represent a register -->
+      <xs:element name="name" type="identifierType"/>
+      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.
+                                     The use of this tag is discouraged because it does not allow consistency between
+                                     the System View and the device header file. -->
+      <xs:element name="displayName" type="stringType" minOccurs="0"/>
+      <!-- description contains a reference manual level description about the register and it's purpose -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <xs:choice>
+        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.
+                                       This is useful if a register has a different description per mode but a single name -->
+        <xs:element name="alternateGroup" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is
+                                       already fully described. In this case the register name must be unique within the peripheral -->
+        <xs:element name="alternateRegister" type="identifierType" minOccurs="0"/>
+      </xs:choice>
+      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                                     reset value. These default values are inherited to all fields contained in this register -->
+      <xs:group    ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->
+      <xs:element name="dataType" type="dataTypeType" minOccurs="0"/>
+      <!-- modifiedWriteValues specifies the write side effects -->
+      <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+      <!-- writeConstraint specifies the subset of allowed write values -->
+      <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+      <!-- readAcction specifies the read side effects -->
+      <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+      <!-- fields section contains all fields that belong to this register -->
+      <xs:element name="fields" type="fieldsType" minOccurs="0" maxOccurs="1"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->
+  <xs:complexType name="clusterType">
+    <xs:sequence>
+      <xs:group   ref="dimElementGroup" minOccurs="0"/>
+      <xs:element name="name" type="identifierType"/>
+      <xs:element name="description" type="xs:string"/>
+      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is
+                 already fully described. In this case the cluster name must be unique within the peripheral -->
+      <xs:element name="alternateCluster" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef
+                 used in the device header generation instead of the cluster name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+      <xs:element name="register" type="registerType" minOccurs="1" maxOccurs="unbounded"/>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+
+  <!-- the registers section can have an arbitrary list of cluster and register sections -->
+  <xs:complexType name="registersType">
+    <xs:choice minOccurs="1" maxOccurs="unbounded">
+      <xs:element name="cluster" type="clusterType"/>
+      <xs:element name="register" type="registerType"/>
+    </xs:choice>
+  </xs:complexType>
+
+  <xs:complexType name="peripheralType">
+    <xs:sequence>
+      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->
+      <xs:element name="name" type="xs:Name"/>
+      <!-- version specifies the version of the peripheral descriptions -->
+      <xs:element name="version" type="stringType" minOccurs="0"/>
+      <!-- description provides a high level functional description of the peripheral -->
+      <xs:element name="description" type="stringType" minOccurs="0"/>
+      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is
+           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->
+      <xs:element name="alternatePeripheral" type="identifierType" minOccurs="0"/>
+      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
+      <xs:element name="groupName" type="xs:Name" minOccurs="0"/>
+      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
+      <xs:element name="prependToName" type="identifierType" minOccurs="0"/>
+      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+                         file will sho the registers in a C-Struct of the peripheral without the postfix -->
+      <xs:element name="appendToName" type="identifierType" minOccurs="0"/>
+      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
+                         used in the device header generation instead of the peripheral name -->
+      <xs:element name="headerStructName" type="identifierType" minOccurs="0"/>
+      <!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+                         if the condition is evaluated to true, the peripheral display will be disabled -->
+      <xs:element name="disableCondition" type="stringType" minOccurs="0"/>
+      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
+                         to specify a baseAddress. -->
+      <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+                         reset value. These default values are inherited to all registers contained in this peripheral -->
+      <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
+                         at least one address block -->
+      <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
+      <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
+                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        registers section is not allowed -->
+      <xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
+      </xs:element>
+    </xs:sequence>
+    <xs:attribute name="derivedFrom" type="identifierType" use="optional"/>
+  </xs:complexType>
+  
+  <!-- ==================================================== -->
+  <!-- The top level element of a description is the device -->
+  <!-- ==================================================== -->
+  <xs:element name="device" nillable="true">
+    <xs:complexType>
+      <xs:sequence>
+        <!-- V1.1: Vendor Name -->
+        <xs:element name="vendor" type="stringType" minOccurs="0"/>
+        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->
+        <xs:element name="vendorID" type="identifierType" minOccurs="0"/>
+        <!-- name specifies the device name being described -->
+        <xs:element name="name" type="identifierType"/>
+        <!-- V1.1: series specifies the device series or family name -->
+        <xs:element name="series" type="stringType" minOccurs="0"/>
+        <!-- version specifies the version of the device description -->
+        <xs:element name="version" type="stringType"/>
+        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->
+        <xs:element name="description" type="stringType"/>
+        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->
+        <xs:element name="licenseText" type="stringType" minOccurs="0"/>
+        <!-- V1.1: cpu specifies the details of the processor included in the device -->
+        <xs:element name="cpu" type="cpuType" minOccurs="0"/>
+        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
+             This tag is used by the header file generator for customizing the include statement referencing the
+             CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
+             In cases a device series shares a single system header file, the name of the series shall be used 
+             instead of the individual device name. -->
+        <xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
+        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in
+             generated device header file -->
+        <xs:element name="headerDefinitionsPrefix" type="identifierType" minOccurs="0"/>
+        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->
+        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.
+             This sets the maximum size of a single register that can be defined for an address space -->
+        <xs:element name="width" type="scaledNonNegativeInteger"/>
+        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
+             reset value -->
+        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+
+        <!-- peripherals is containing all peripherals -->
+        <xs:element name="peripherals">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:element name="peripheral" type="peripheralType" minOccurs="1" maxOccurs="unbounded"/>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+
+        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->
+        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+          <xs:complexType>
+            <xs:sequence>
+              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+              </xs:any>
+            </xs:sequence>
+          </xs:complexType>
+        </xs:element>
+      </xs:sequence>
+      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.1"/>
+    </xs:complexType>
+  </xs:element>
+</xs:schema>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/index.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/index.html
new file mode 100644
index 0000000..c6da080
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/CMSIS/index.html
@@ -0,0 +1,14 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>Redirect to the CMSIS main page after 0 seconds</title>
+<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
+<meta name="keywords" content="automatic redirection">
+</head>
+
+<body>
+
+If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
+
+</body>
+</html>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html
index 44dd101..8999a27 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html
@@ -82,9 +82,8 @@ div.Section1
 <tr style="">
 <td style="padding: 1.5pt;">
 <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x Standard Peripherals Library Drivers
-(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+Notes for STM32F10x Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
 <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
 </td>
 </tr>
@@ -104,7 +103,13 @@ Drivers update History</a><o:p></o:p></span></li>
 <span style="font-family: &quot;Times New Roman&quot;;">
 </span>
 <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
-Peripherals Library Drivers&nbsp; update History</span></h2><br>
+Peripherals Library Drivers&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.1 / 05-March-2012<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.0 / 27-January-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the&nbsp;new license agreement</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SDIO_SetPowerState()</span> function: fix POWER register configuration, only one access (for read or write) is allowed</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_usart.h/.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update procedure to check on&nbsp;overrun error interrupt pending bit, defines for the following flag are added:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_RX:</span> this flag is set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and&nbsp;RXNEIE bit is set</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_ER:</span> </span><span style="font-size: 10pt; font-family: Verdana;">this flag is&nbsp;set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and EIE bit is set</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove <span style="font-style: italic;">IS_USART_PERIPH_FLAG</span> macro (not used)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RTC_GetCounter()</span> function to fix issue when reading the RTC counter registers (CNTL &amp; CNTH registers) and the counter rolls over</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Flash keys moved from&nbsp;to stm32f10x.h file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_UpdateRequestConfig():&nbsp;</span>correct function header's comment&nbsp;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_exti.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">EXTI_InitTypeDef</span> structure : for &#8220;EXTI_Trigger&#8220; member, change &#8220;@ref EXTIMode_TypeDef&#8221;&nbsp; by&nbsp; &#8220;@ref EXTITrigger_TypeDef&#8221;&nbsp;</span></li></ul></ul>
             <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
             <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
 Changes<o:p></o:p></span></u></b></p>
@@ -309,19 +314,12 @@ Cortex-M3 System Control register to allow Sleep mode entering.</span></li>
 
 </ul>
 <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span><p class="MsoNormal"><span style="color: black;"><o:p></o:p></span><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="color: black;"><o:p></o:p></span></p>
 <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
 <hr align="center" size="2" width="100%"></span></div>
 <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
index 9a6bd07..0fea5b2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
@@ -2,21 +2,27 @@
   ******************************************************************************
   * @file    misc.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file contains all the functions prototypes for the miscellaneous
   *          firmware library functions (add-on to CMSIS functions).
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -217,4 +223,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..47e8104
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
@@ -0,0 +1,201 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_bkp.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the BKP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup BKP
+  * @{
+  */
+
+/** @defgroup BKP_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Tamper_Pin_active_level 
+  * @{
+  */
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 
+  * @{
+  */
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+                                          ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+  * @}
+  */
+
+/** @defgroup Data_Backup_Register 
+  * @{
+  */
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup BKP_Exported_Functions
+  * @{
+  */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
new file mode 100644
index 0000000..7adc125
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_cec.h
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+  
+
+/** @defgroup CEC_Exported_Types
+  * @{
+  */
+   
+/** 
+  * @brief  CEC Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 
+                               This parameter can be a value of @ref CEC_BitTiming_Mode */
+  uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 
+                               This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup CEC_BitTiming_Mode 
+  * @{
+  */ 
+#define CEC_BitTimingStdMode                    ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode                CEC_CFGR_BTEM   /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+                                            ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitPeriod_Mode 
+  * @{
+  */ 
+#define CEC_BitPeriodStdMode                    ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode                CEC_CFGR_BPEM   /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+                                            ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_interrupts_definition 
+  * @{
+  */ 
+#define CEC_IT_TERR                              CEC_CSR_TERR
+#define CEC_IT_TBTRF                             CEC_CSR_TBTRF
+#define CEC_IT_RERR                              CEC_CSR_RERR
+#define CEC_IT_RBTF                              CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+                           ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Own_Address 
+  * @{
+  */ 
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Prescaler 
+  * @{
+  */ 
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_flags_definition 
+  * @{
+  */
+   
+/** 
+  * @brief  ESR register flags  
+  */ 
+#define CEC_FLAG_BTE                            ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE                            ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE                          ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE                            ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE                           ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE                           ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE                          ((uint32_t)0x10400000)
+
+/** 
+  * @brief  CSR register flags  
+  */ 
+#define CEC_FLAG_TEOM                           ((uint32_t)0x00000002)  
+#define CEC_FLAG_TERR                           ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF                          ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM                           ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM                           ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR                           ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF                           ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+                               
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+                               ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+                               ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+                               ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+                               ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+                               ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+                               ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CEC_Exported_Macros
+  * @{
+  */
+ 
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions
+  * @{
+  */ 
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
new file mode 100644
index 0000000..355fb91
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
@@ -0,0 +1,100 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
index 89ceb9a..ba7ffe2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
@@ -2,21 +2,27 @@
   ******************************************************************************
   * @file    stm32f10x_dbgmcu.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file contains all the functions prototypes for the DBGMCU 
   *          firmware library.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -116,4 +122,4 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
new file mode 100644
index 0000000..d691564
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
@@ -0,0 +1,445 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dma.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode.
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */
+
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+                         ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */
+
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */
+
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */
+
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory 
+  * @{
+  */
+
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition 
+  * @{
+  */
+
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size 
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions
+  * @{
+  */
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DMA_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..2883c1e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_exti.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)  /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+                                                   Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                            ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                            ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                            ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                            ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                            ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                            ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                            ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                            ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                            ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions
+  * @{
+  */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
new file mode 100644
index 0000000..fa6f405
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
@@ -0,0 +1,432 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_flash.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  FLASH Status  
+  */
+
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Flash_Latency 
+  * @{
+  */
+
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2))
+/**
+  * @}
+  */
+
+/** @defgroup Half_Cycle_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+                                               ((STATE) == FLASH_HalfCycleAccess_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable 
+  * @{
+  */
+
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+                                              ((STATE) == FLASH_PrefetchBuffer_Disable)) 
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+                                                                   Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127      ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+#define FLASH_WRProt_Pages62to511      ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
+
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+#ifdef STM32F10X_XL
+/**
+  * @}
+  */
+/** @defgroup FLASH_Boot
+  * @{
+  */
+#define FLASH_BOOT_Bank1  ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_Bank2  ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                  and this parameter is selected the device will boot from Bank 2 or Bank 1,
+                                                  depending on the activation of the bank */
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
+#endif
+/**
+  * @}
+  */
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_IT_BANK2_ERROR                 ((uint32_t)0x80000400)  /*!< FPEC BANK2 error interrupt source */
+#define FLASH_IT_BANK2_EOP                   ((uint32_t)0x80001000)  /*!< End of FLASH BANK2 Operation Interrupt source */
+
+#define FLASH_IT_BANK1_ERROR                 FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP                   FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH BANK1 Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#else
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */
+#ifdef STM32F10X_XL
+#define FLASH_FLAG_BANK2_BSY                 ((uint32_t)0x80000001)  /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BANK2_EOP                 ((uint32_t)0x80000020)  /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BANK2_PGERR               ((uint32_t)0x80000004)  /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BANK2_WRPRTERR            ((uint32_t)0x80000010)  /*!< FLASH BANK2 Write protected error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR)|| \
+                                  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
+#else
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /*!< FLASH BANK1 Write protected error flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+								  ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions
+  * @{
+  */
+
+/*------------ Functions used for all STM32F10x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/*------------ New function used for all STM32F10x devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef STM32F10X_XL
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseAllBank2Pages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
index 6e1769d..1304d74 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
@@ -2,21 +2,27 @@
   ******************************************************************************
   * @file    stm32f10x_fsmc.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file contains all the functions prototypes for the FSMC firmware 
   *          library.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -730,4 +736,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
   * @}
   */ 
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..971ab42
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
@@ -0,0 +1,146 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_iwdg.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions
+  * @{
+  */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..ad7d2fc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
@@ -0,0 +1,162 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_pwr.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+  * @}
+  */
+
+/** @defgroup Regulator_state_is_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions
+  * @{
+  */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
new file mode 100644
index 0000000..ffa9a45
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
@@ -0,0 +1,733 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_rcc.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the RCC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /*!< returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /*!< returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /*!< returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /*!< returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /*!< returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup HSE_configuration 
+  * @{
+  */
+
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PLL_entry_clock_source 
+  * @{
+  */
+
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
+ #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup PLL_multiplication_factor 
+  * @{
+  */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2                    ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3                    ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10                   ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11                   ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12                   ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13                   ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14                   ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15                   ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16                   ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                              ((MUL) == RCC_PLLMul_16))
+
+#else
+ #define RCC_PLLMul_4                    ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5                    ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6                    ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7                    ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8                    ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9                    ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5                  ((uint32_t)0x00340000)
+
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+                              ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */                              
+/**
+  * @}
+  */
+
+/** @defgroup PREDIV1_division_factor
+  * @{
+  */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define  RCC_PREDIV1_Div1               ((uint32_t)0x00000000)
+ #define  RCC_PREDIV1_Div2               ((uint32_t)0x00000001)
+ #define  RCC_PREDIV1_Div3               ((uint32_t)0x00000002)
+ #define  RCC_PREDIV1_Div4               ((uint32_t)0x00000003)
+ #define  RCC_PREDIV1_Div5               ((uint32_t)0x00000004)
+ #define  RCC_PREDIV1_Div6               ((uint32_t)0x00000005)
+ #define  RCC_PREDIV1_Div7               ((uint32_t)0x00000006)
+ #define  RCC_PREDIV1_Div8               ((uint32_t)0x00000007)
+ #define  RCC_PREDIV1_Div9               ((uint32_t)0x00000008)
+ #define  RCC_PREDIV1_Div10              ((uint32_t)0x00000009)
+ #define  RCC_PREDIV1_Div11              ((uint32_t)0x0000000A)
+ #define  RCC_PREDIV1_Div12              ((uint32_t)0x0000000B)
+ #define  RCC_PREDIV1_Div13              ((uint32_t)0x0000000C)
+ #define  RCC_PREDIV1_Div14              ((uint32_t)0x0000000D)
+ #define  RCC_PREDIV1_Div15              ((uint32_t)0x0000000E)
+ #define  RCC_PREDIV1_Div16              ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup PREDIV1_clock_source
+  * @{
+  */
+#ifdef STM32F10X_CL
+/* PREDIV1 clock source (for STM32 connectivity line devices) */
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
+ #define  RCC_PREDIV1_Source_PLL2        ((uint32_t)0x00010000) 
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+                                        ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/* PREDIV1 clock source (for STM32 Value line devices) */
+ #define  RCC_PREDIV1_Source_HSE         ((uint32_t)0x00000000) 
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 
+#endif
+/**
+  * @}
+  */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV2_division_factor
+  * @{
+  */
+  
+ #define  RCC_PREDIV2_Div1               ((uint32_t)0x00000000)
+ #define  RCC_PREDIV2_Div2               ((uint32_t)0x00000010)
+ #define  RCC_PREDIV2_Div3               ((uint32_t)0x00000020)
+ #define  RCC_PREDIV2_Div4               ((uint32_t)0x00000030)
+ #define  RCC_PREDIV2_Div5               ((uint32_t)0x00000040)
+ #define  RCC_PREDIV2_Div6               ((uint32_t)0x00000050)
+ #define  RCC_PREDIV2_Div7               ((uint32_t)0x00000060)
+ #define  RCC_PREDIV2_Div8               ((uint32_t)0x00000070)
+ #define  RCC_PREDIV2_Div9               ((uint32_t)0x00000080)
+ #define  RCC_PREDIV2_Div10              ((uint32_t)0x00000090)
+ #define  RCC_PREDIV2_Div11              ((uint32_t)0x000000A0)
+ #define  RCC_PREDIV2_Div12              ((uint32_t)0x000000B0)
+ #define  RCC_PREDIV2_Div13              ((uint32_t)0x000000C0)
+ #define  RCC_PREDIV2_Div14              ((uint32_t)0x000000D0)
+ #define  RCC_PREDIV2_Div15              ((uint32_t)0x000000E0)
+ #define  RCC_PREDIV2_Div16              ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+                                  ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+  * @}
+  */
+
+
+/** @defgroup PLL2_multiplication_factor
+  * @{
+  */
+  
+ #define  RCC_PLL2Mul_8                  ((uint32_t)0x00000600)
+ #define  RCC_PLL2Mul_9                  ((uint32_t)0x00000700)
+ #define  RCC_PLL2Mul_10                 ((uint32_t)0x00000800)
+ #define  RCC_PLL2Mul_11                 ((uint32_t)0x00000900)
+ #define  RCC_PLL2Mul_12                 ((uint32_t)0x00000A00)
+ #define  RCC_PLL2Mul_13                 ((uint32_t)0x00000B00)
+ #define  RCC_PLL2Mul_14                 ((uint32_t)0x00000C00)
+ #define  RCC_PLL2Mul_16                 ((uint32_t)0x00000E00)
+ #define  RCC_PLL2Mul_20                 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9)  || \
+                               ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+                               ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+                               ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+                               ((MUL) == RCC_PLL2Mul_20))
+/**
+  * @}
+  */
+
+
+/** @defgroup PLL3_multiplication_factor
+  * @{
+  */
+
+ #define  RCC_PLL3Mul_8                  ((uint32_t)0x00006000)
+ #define  RCC_PLL3Mul_9                  ((uint32_t)0x00007000)
+ #define  RCC_PLL3Mul_10                 ((uint32_t)0x00008000)
+ #define  RCC_PLL3Mul_11                 ((uint32_t)0x00009000)
+ #define  RCC_PLL3Mul_12                 ((uint32_t)0x0000A000)
+ #define  RCC_PLL3Mul_13                 ((uint32_t)0x0000B000)
+ #define  RCC_PLL3Mul_14                 ((uint32_t)0x0000C000)
+ #define  RCC_PLL3Mul_16                 ((uint32_t)0x0000E000)
+ #define  RCC_PLL3Mul_20                 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9)  || \
+                               ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+                               ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+                               ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+                               ((MUL) == RCC_PLL3Mul_20))
+/**
+  * @}
+  */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source 
+  * @{
+  */
+
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_clock_source 
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+
+/** @defgroup APB1_APB2_clock_source 
+  * @{
+  */
+
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt_source 
+  * @{
+  */
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY                  ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY                  ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+                            ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */ 
+
+
+/**
+  * @}
+  */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source 
+  * @{
+  */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+  * @}
+  */
+#else
+/** @defgroup USB_OTG_FS_clock_source 
+  * @{
+  */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3    ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2    ((uint8_t)0x01)
+
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+                                         ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+/**
+  * @}
+  */
+#endif /* STM32F10X_CL */ 
+
+
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source 
+  * @{
+  */
+ #define RCC_I2S2CLKSource_SYSCLK        ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO      ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+                                        ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+  * @}
+  */
+
+/** @defgroup I2S3_clock_source 
+  * @{
+  */
+ #define RCC_I2S3CLKSource_SYSCLK        ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO      ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+                                        ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))    
+/**
+  * @}
+  */
+#endif /* STM32F10X_CL */  
+  
+
+/** @defgroup ADC_clock_source 
+  * @{
+  */
+
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+  * @}
+  */
+
+/** @defgroup LSE_configuration 
+  * @{
+  */
+
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_clock_source 
+  * @{
+  */
+
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+  * @}
+  */
+
+/** @defgroup AHB_peripheral 
+  * @{
+  */
+
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC              ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO              ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS            ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC           ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx        ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx        ((uint32_t)0x00010000)
+
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+  * @}
+  */
+
+/** @defgroup APB2_peripheral 
+  * @{
+  */
+
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup APB1_peripheral 
+  * @{
+  */
+
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
+ 
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup Clock_source_to_output_on_MCO_pin 
+  * @{
+  */
+
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
+                          ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK                 ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2            ((uint8_t)0x09)
+ #define RCC_MCO_XT1                     ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK                 ((uint8_t)0x0B)
+
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+                          ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
+                          ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+                          ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+                          ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */ 
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag 
+  * @{
+  */
+
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+                            ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY                ((uint8_t)0x3B) 
+ #define RCC_FLAG_PLL3RDY                ((uint8_t)0x3D) 
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                            ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+                            ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+                            ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+                            ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */ 
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions
+  * @{
+  */
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+#endif
+
+#ifdef  STM32F10X_CL
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */ 
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */ 
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);                                  
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */ 
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */ 
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
new file mode 100644
index 0000000..d0bfe1c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_sdio.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/** @defgroup SDIO_Exported_Types
+  * @{
+  */
+
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                           enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                           disabled when the bus is idle.
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
+                                           This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
+                                This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_sources 
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type 
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State 
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State 
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers 
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Exported_Functions
+  * @{
+  */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
new file mode 100644
index 0000000..aeedaeb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_spi.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the SPI firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */ 
+
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+                                  ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx) || \
+                           ((MODE) == I2S_Mode_MasterRx) )
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                  ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                 ((IT) == SPI_I2S_IT_RXNE) || \
+                                 ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+                               ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Exported_Functions
+  * @{
+  */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_SPI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
index 65bf76a..077832f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
@@ -2,21 +2,27 @@
   ******************************************************************************
   * @file    stm32f10x_tim.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file contains all the functions prototypes for the TIM firmware 
   *          library.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -1161,4 +1167,4 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
new file mode 100644
index 0000000..25137c4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
@@ -0,0 +1,429 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_usart.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/** @defgroup USART_Exported_Types
+  * @{
+  */ 
+
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /*!< Specifies the steady state value of the serial clock.
+                               This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
+                               This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4) || \
+                                     ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                      ((PERIPH) == USART2) || \
+                                      ((PERIPH) == USART3) || \
+                                      ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @{
+  */
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+/** @defgroup USART_Legacy 
+  * @{
+  */
+#define USART_IT_ORE                          USART_IT_ORE_ER               
+/**
+  * @}
+  */
+  
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                               ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                               ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                            ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                            ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                            ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                            ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
+                            ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Exported_Functions
+  * @{
+  */
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_USART_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
new file mode 100644
index 0000000..1ace8b2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_wwdg.h
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+
+/** @defgroup WWDG_Exported_Types
+  * @{
+  */ 
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */ 
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup WWDG_Exported_Functions
+  * @{
+  */ 
+  
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_WWDG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
new file mode 100644
index 0000000..b252f35
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,231 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/** @defgroup MISC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup MISC_Private_Defines
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM
+  *     @arg NVIC_VectTab_FLASH
+  * @param  Offset: Vector Table base offset field. This value must be a multiple 
+  *         of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND
+  *     @arg NVIC_LP_SLEEPDEEP
+  *     @arg NVIC_LP_SLEEPONEXIT
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
new file mode 100644
index 0000000..51952c1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
@@ -0,0 +1,1313 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_adc.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the ADC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset           ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set              ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset            ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set               ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset             ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set             ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset           ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset             ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset           ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask              ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set                ((uint32_t)0x00000001)
+#define CR2_ADON_Reset              ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set                 ((uint32_t)0x00000100)
+#define CR2_DMA_Reset               ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set              ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set                 ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set             ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set             ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset           ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set     ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset   ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset           ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set            ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset          ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set            ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set   ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set             ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset           ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask              ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set                 ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set                 ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask             ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set                ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set                 ((uint32_t)0x00300000)
+#define JSQR_JL_Reset               ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set               ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set               ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset                  ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS                  ((uint32_t)0x4001244C)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  if (ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+  else if (ADCx == ADC2)
+  {
+    /* Enable ADC2 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+    /* Release ADC2 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+  }
+  else
+  {
+    if (ADCx == ADC3)
+    {
+      /* Enable ADC3 reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+      /* Release ADC3 from reset state */
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear DUALMOD and SCAN bits */
+  tmpreg1 &= CR1_CLEAR_Mask;
+  /* Configure ADCx: Dual mode and scan conversion mode */
+  /* Set DUALMOD bits according to ADC_Mode value */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN and EXTSEL bits */
+  tmpreg1 &= CR2_CLEAR_Mask;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= SQR1_CLEAR_Mask;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+  tmpreg1 |= (uint32_t)tmpreg2 << 20;
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= CR2_ADON_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= CR2_ADON_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 or 3 to select the ADC peripheral.
+  *   Note: ADC2 hasn't a DMA capability.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= CR2_DMA_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= CR2_DMA_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @param  NewState: new state of the specified ADC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Resets the selected ADC calibration registers.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Resets the selected ADC calibration registers */  
+  ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC reset calibration registers status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC reset calibration registers (SET or RESET).
+  */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Starts the selected ADC calibration process.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC calibration process */  
+  ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+  * @brief  Gets the selected ADC calibration status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC calibration (SET or RESET).
+  */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of CAL bit */
+  if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC software start conversion .
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event and start the selected
+       ADC conversion */
+    ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event and stop the selected
+       ADC conversion */
+    ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel
+  *         count value. This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_Reset;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on regular group channel.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= CR1_DISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= CR1_DISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADCx conversion through external trigger.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CR2 |= CR2_EXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CR2 &= CR2_EXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @brief  Returns the last ADC1 and ADC2 conversion result data in dual mode.
+  * @retval The Data conversion value.
+  */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+  /* Return the dual mode conversion value */
+  return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= CR1_JAUTO_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= CR1_JAUTO_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= CR1_JDISCEN_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= CR1_JDISCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+  *     @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+  *                                                       capture compare4 event selected (for ADC1 and ADC2)                       
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+  *     @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)                         
+  *     @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)                        
+  *     @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+  *                                          by external trigger (for ADC1, ADC2 and ADC3)
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_Reset;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADCx injected channels conversion through
+  *         external trigger
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of
+  *         injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CR2 |= CR2_JEXTTRIG_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC start of the injected 
+  *         channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start injected conversion.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion for injected group on external event and start the selected
+       ADC injected conversion */
+    ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event for injected group and stop the selected
+       ADC injected conversion */
+    ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *     @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *     @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *     @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *     @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *     @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *     @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *     @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JL_Set)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Length: The sequencer length. 
+  *   This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequnence lenght JL bits */
+  tmpreg1 &= JSQR_JL_Reset;
+  /* Set the injected sequnence lenght JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));  
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDR_Offset;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp);   
+}
+
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+  *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+  *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on  all regular channel
+  *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on  all injected channel
+  *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= CR1_AWDMode_Reset;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *   This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *   This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_Reset;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 |= CR2_TSVREFE_Set;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 &= CR2_TSVREFE_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = ADC_IT >> 8;
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt mask
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
index ec8e049..2b1924b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
@@ -2,20 +2,26 @@
   ******************************************************************************
   * @file    stm32f10x_can.c
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file provides all the CAN firmware functions.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -1412,4 +1418,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
new file mode 100644
index 0000000..ac731dd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_cec.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the CEC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_cec.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CEC 
+  * @brief CEC driver modules
+  * @{
+  */
+
+/** @defgroup CEC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup CEC_Private_Defines
+  * @{
+  */ 
+
+/* ------------ CEC registers bit address in the alias region ----------- */
+#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of PE bit */
+#define CFGR_OFFSET                 (CEC_OFFSET + 0x00)
+#define PE_BitNumber                0x00
+#define CFGR_PE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
+
+/* Alias word address of IE bit */
+#define IE_BitNumber                0x01
+#define CFGR_IE_BB                  (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TSOM bit */
+#define CSR_OFFSET                  (CEC_OFFSET + 0x10)
+#define TSOM_BitNumber              0x00
+#define CSR_TSOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
+
+/* Alias word address of TEOM bit */
+#define TEOM_BitNumber              0x01
+#define CSR_TEOM_BB                 (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
+  
+#define CFGR_CLEAR_Mask            (uint8_t)(0xF3)        /* CFGR register Mask */
+#define FLAG_Mask                  ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Variables
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_FunctionPrototypes
+  * @{
+  */
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup CEC_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Deinitializes the CEC peripheral registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void CEC_DeInit(void)
+{
+  /* Enable CEC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);  
+  /* Release CEC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 
+}
+
+
+/**
+  * @brief  Initializes the CEC peripheral according to the specified 
+  *         parameters in the CEC_InitStruct.
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
+  *         contains the configuration information for the specified
+  *         CEC peripheral.
+  * @retval None
+  */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+  uint16_t tmpreg = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 
+  assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
+     
+  /*---------------------------- CEC CFGR Configuration -----------------*/
+  /* Get the CEC CFGR value */
+  tmpreg = CEC->CFGR;
+  
+  /* Clear BTEM and BPEM bits */
+  tmpreg &= CFGR_CLEAR_Mask;
+  
+  /* Configure CEC: Bit Timing Error and Bit Period Error */
+  tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
+
+  /* Write to CEC CFGR  register*/
+  CEC->CFGR = tmpreg;
+  
+}
+
+/**
+  * @brief  Enables or disables the specified CEC peripheral.
+  * @param  NewState: new state of the CEC peripheral. 
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
+
+  if(NewState == DISABLE)
+  {
+    /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
+    while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
+    {
+    }  
+  }  
+}
+
+/**
+  * @brief  Enables or disables the CEC interrupt.
+  * @param  NewState: new state of the CEC interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Defines the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address
+  * @retval None
+  */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+
+  /* Set the CEC own address */
+  CEC->OAR = CEC_OwnAddress;
+}
+
+/**
+  * @brief  Sets the CEC prescaler value.
+  * @param  CEC_Prescaler: CEC prescaler new value
+  * @retval None
+  */
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
+
+  /* Set the  Prescaler value*/
+  CEC->PRES = CEC_Prescaler;
+}
+
+/**
+  * @brief  Transmits single data through the CEC peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void CEC_SendDataByte(uint8_t Data)
+{  
+  /* Transmit Data */
+  CEC->TXD = Data ;
+}
+
+
+/**
+  * @brief  Returns the most recent received data by the CEC peripheral.
+  * @param  None
+  * @retval The received data.
+  */
+uint8_t CEC_ReceiveDataByte(void)
+{
+  /* Receive Data */
+  return (uint8_t)(CEC->RXD);
+}
+
+/**
+  * @brief  Starts a new message.
+  * @param  None
+  * @retval None
+  */
+void CEC_StartOfMessage(void)
+{  
+  /* Starts of new message */
+  *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
+}
+
+/**
+  * @brief  Transmits message with or without an EOM bit.
+  * @param  NewState: new state of the CEC Tx End Of Message. 
+  *     This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_EndOfMessageCmd(FunctionalState NewState)
+{   
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* The data byte will be transmitted with or without an EOM bit*/
+  *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Gets the CEC flag status
+  * @param  CEC_FLAG: specifies the CEC flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg CEC_FLAG_BTE: Bit Timing Error
+  *     @arg CEC_FLAG_BPE: Bit Period Error
+  *     @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
+  *     @arg CEC_FLAG_SBE: Start Bit Error
+  *     @arg CEC_FLAG_ACKE: Block Acknowledge Error
+  *     @arg CEC_FLAG_LINE: Line Error
+  *     @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
+  *     @arg CEC_FLAG_TEOM: Tx End Of Message 
+  *     @arg CEC_FLAG_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
+  *     @arg CEC_FLAG_RERR: Rx Error
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+  * @retval The new state of CEC_FLAG (SET or RESET)
+  */
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t cecreg = 0, cecbase = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+ 
+  /* Get the CEC peripheral base address */
+  cecbase = (uint32_t)(CEC_BASE);
+  
+  /* Read flag register index */
+  cecreg = CEC_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  CEC_FLAG &= FLAG_Mask;
+  
+  if(cecreg != 0)
+  {
+    /* Flag in CEC ESR Register */
+    CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
+    
+    /* Get the CEC ESR register address */
+    cecbase += 0xC;
+  }
+  else
+  {
+    /* Get the CEC CSR register address */
+    cecbase += 0x10;
+  }
+  
+  if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
+  {
+    /* CEC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the CEC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's pending flags.
+  * @param  CEC_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg CEC_FLAG_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+  *     @arg CEC_FLAG_RSOM: Rx Start Of Message
+  *     @arg CEC_FLAG_REOM: Rx End Of Message
+  *     @arg CEC_FLAG_RERR: Rx Error
+  *     @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+  * @retval None
+  */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{ 
+  uint32_t tmp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+  tmp = CEC->CSR & 0x2;
+       
+  /* Clear the selected CEC flags */
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg CEC_IT_TERR: Tx Error
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
+  *     @arg CEC_IT_RERR: Rx Error
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
+  * @retval The new state of CEC_IT (SET or RESET).
+  */
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+   assert_param(IS_CEC_GET_IT(CEC_IT));
+   
+  /* Get the CEC IT enable bit status */
+  enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
+  
+  /* Check the status of the specified CEC interrupt */
+  if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* CEC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the CEC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's interrupt pending bits.
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg CEC_IT_TERR: Tx Error
+  *     @arg CEC_IT_TBTF: Tx Block Transfer Finished
+  *     @arg CEC_IT_RERR: Rx Error
+  *     @arg CEC_IT_RBTF: Rx Block Transfer Finished
+  * @retval None
+  */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+  uint32_t tmp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_IT(CEC_IT));
+  
+  tmp = CEC->CSR & 0x2;
+  
+  /* Clear the selected CEC interrupt pending bits */
+  CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
new file mode 100644
index 0000000..70cabd5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_crc.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/** @defgroup CRC_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
new file mode 100644
index 0000000..6278093
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
@@ -0,0 +1,168 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Defines
+  * @{
+  */
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures the specified peripheral and low power mode behavior
+  *   when the MCU under Debug mode.
+  * @param  DBGMCU_Periph: specifies the peripheral and low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode            
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted          
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted          
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted          
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted           
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 
+  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted                
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
index bf072df..cc27774 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
@@ -2,20 +2,26 @@
   ******************************************************************************
   * @file    stm32f10x_dma.c
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file provides all the DMA firmware functions.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -711,4 +717,4 @@ void DMA_ClearITPendingBit(uint32_t DMAy_IT)
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
new file mode 100644
index 0000000..5c14b25
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
@@ -0,0 +1,656 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_gpio.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the GPIO firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */ 
+
+/** @defgroup GPIO_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Defines
+  * @{
+  */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((uint8_t)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* ---  MAPR Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define MAPR_OFFSET                 (AFIO_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber      ((u8)0x17) 
+#define MAPR_MII_RMII_SEL_BB        (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  if (GPIOx == GPIOA)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+  }    
+  else if (GPIOx == GPIOE)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+  } 
+  else if (GPIOx == GPIOF)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+  }
+  else
+  {
+    if (GPIOx == GPIOG)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap, event control
+  *   and EXTI configuration) registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void GPIO_AFIODeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+  *         contains the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+  uint32_t tmpreg = 0x00, pinmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));  
+  
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+  { 
+    /* Check the parameters */
+    assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+    /* Output mode */
+    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+  }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+  /* Configure the eight low port pins */
+  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+  {
+    tmpreg = GPIOx->CRL;
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = ((uint32_t)0x01) << pinpos;
+      /* Get the port pins position */
+      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding low control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+        }
+        else
+        {
+          /* Set the corresponding ODR bit */
+          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+          {
+            GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+          }
+        }
+      }
+    }
+    GPIOx->CRL = tmpreg;
+  }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+  /* Configure the eight high port pins */
+  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+  {
+    tmpreg = GPIOx->CRH;
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = (((uint32_t)0x01) << (pinpos + 0x08));
+      /* Get the port pins position */
+      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        /* Clear the corresponding high control register bits */
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        /* Write the mode configuration in the corresponding bits */
+        tmpreg |= (currentmode << pos);
+        /* Reset the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+        /* Set the corresponding ODR bit */
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+        {
+          GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+      }
+    }
+    GPIOx->CRH = tmpreg;
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin:  specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 
+  
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be one of the BitAction enum values:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal)); 
+  
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @param  GPIOx: where x can be (A..G) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t tmp = 0x00010000;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as Event output.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source
+  *   for Event output.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+  * @param  GPIO_PinSource: specifies the pin for the Event output.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+    
+  tmpreg = AFIO->EVCR;
+  /* Clear the PORT[6:4] and PIN[3:0] bits */
+  tmpreg &= EVCR_PORTPINCONFIG_MASK;
+  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+  tmpreg |= GPIO_PinSource;
+  AFIO->EVCR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Event Output.
+  * @param  NewState: new state of the Event output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIO_Remap: selects the pin to remap.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_Remap_SPI1             : SPI1 Alternate Function mapping
+  *     @arg GPIO_Remap_I2C1             : I2C1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART1           : USART1 Alternate Function mapping
+  *     @arg GPIO_Remap_USART2           : USART2 Alternate Function mapping
+  *     @arg GPIO_PartialRemap_USART3    : USART3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_USART3       : USART3 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TIM1      : TIM1 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM1         : TIM1 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap1_TIM2     : TIM2 Partial1 Alternate Function mapping
+  *     @arg GPIO_PartialRemap2_TIM2     : TIM2 Partial2 Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM2         : TIM2 Full Alternate Function mapping
+  *     @arg GPIO_PartialRemap_TIM3      : TIM3 Partial Alternate Function mapping
+  *     @arg GPIO_FullRemap_TIM3         : TIM3 Full Alternate Function mapping
+  *     @arg GPIO_Remap_TIM4             : TIM4 Alternate Function mapping
+  *     @arg GPIO_Remap1_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap2_CAN1            : CAN1 Alternate Function mapping
+  *     @arg GPIO_Remap_PD01             : PD01 Alternate Function mapping
+  *     @arg GPIO_Remap_TIM5CH4_LSI      : LSI connected to TIM5 Channel4 input capture for calibration
+  *     @arg GPIO_Remap_ADC1_ETRGINJ     : ADC1 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC1_ETRGREG     : ADC1 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_ADC2_ETRGINJ     : ADC2 External Trigger Injected Conversion remapping
+  *     @arg GPIO_Remap_ADC2_ETRGREG     : ADC2 External Trigger Regular Conversion remapping
+  *     @arg GPIO_Remap_ETH              : Ethernet remapping (only for Connectivity line devices)
+  *     @arg GPIO_Remap_CAN2             : CAN2 remapping (only for Connectivity line devices)
+  *     @arg GPIO_Remap_SWJ_NoJTRST      : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+  *     @arg GPIO_Remap_SWJ_JTAGDisable  : JTAG-DP Disabled and SW-DP Enabled
+  *     @arg GPIO_Remap_SWJ_Disable      : Full SWJ Disabled (JTAG-DP + SW-DP)
+  *     @arg GPIO_Remap_SPI3             : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
+  *                                        When the SPI3/I2S3 is remapped using this function, the SWJ is configured
+  *                                        to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.   
+  *     @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+  *                                        to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
+  *                                        If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to 
+  *                                        Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.    
+  *     @arg GPIO_Remap_PTP_PPS          : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
+  *     @arg GPIO_Remap_TIM15            : TIM15 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM16            : TIM16 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM17            : TIM17 Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_CEC              : CEC Alternate Function mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM1_DMA         : TIM1 DMA requests mapping (only for Value line devices)
+  *     @arg GPIO_Remap_TIM9             : TIM9 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM10            : TIM10 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM11            : TIM11 Alternate Function mapping (only for XL-density devices)
+  *     @arg GPIO_Remap_TIM13            : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_TIM14            : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_FSMC_NADV        : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
+  *     @arg GPIO_Remap_TIM67_DAC_DMA    : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
+  *     @arg GPIO_Remap_TIM12            : TIM12 Alternate Function mapping (only for High density Value line devices)
+  *     @arg GPIO_Remap_MISC             : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, 
+  *                                        only for High density Value line devices)     
+  * @param  NewState: new state of the port pin remapping.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_REMAP(GPIO_Remap));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    tmpreg = AFIO->MAPR2;
+  }
+  else
+  {
+    tmpreg = AFIO->MAPR;
+  }
+
+  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+  tmp = GPIO_Remap & LSB_MASK;
+
+  if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+  {
+    tmpreg &= DBGAFR_SWJCFG_MASK;
+    AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+  }
+  else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+  {
+    tmp1 = ((uint32_t)0x03) << tmpmask;
+    tmpreg &= ~tmp1;
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
+  }
+  else
+  {
+    tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+    tmpreg |= ~DBGAFR_SWJCFG_MASK;
+  }
+
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+  }
+
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    AFIO->MAPR2 = tmpreg;
+  }
+  else
+  {
+    AFIO->MAPR = tmpreg;
+  }  
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+  *   This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+  * @param  GPIO_PinSource: specifies the EXTI line to be configured.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmp = 0x00;
+  /* Check the parameters */
+  assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the Ethernet media interface.
+  * @note   This function applies only to STM32 Connectivity line devices.  
+  * @param  GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_ETH_MediaInterface_MII: MII mode
+  *     @arg GPIO_ETH_MediaInterface_RMII: RMII mode    
+  * @retval None
+  */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) 
+{ 
+  assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); 
+
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 
+}
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
new file mode 100644
index 0000000..b28cab3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
@@ -0,0 +1,1337 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_i2c.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the I2C firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */ 
+
+/** @defgroup I2C_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Defines
+  * @{
+  */
+
+/* I2C SPE mask */
+#define CR1_PE_Set              ((uint16_t)0x0001)
+#define CR1_PE_Reset            ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set           ((uint16_t)0x0100)
+#define CR1_START_Reset         ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set            ((uint16_t)0x0200)
+#define CR1_STOP_Reset          ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set             ((uint16_t)0x0400)
+#define CR1_ACK_Reset           ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set            ((uint16_t)0x0040)
+#define CR1_ENGC_Reset          ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set           ((uint16_t)0x8000)
+#define CR1_SWRST_Reset         ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set             ((uint16_t)0x1000)
+#define CR1_PEC_Reset           ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set           ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset         ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set           ((uint16_t)0x0010)
+#define CR1_ENARP_Reset         ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set       ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset     ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask          ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set           ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset         ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set            ((uint16_t)0x1000)
+#define CR2_LAST_Reset          ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset          ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set           ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset         ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set         ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset       ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset         ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set              ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set             ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask               ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask               ((uint32_t)0x07000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified 
+  *   parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *   contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint16_t tmpreg = 0, freqrange = 0;
+  uint16_t result = 0x04;
+  uint32_t pclk1 = 8000000;
+  RCC_ClocksTypeDef  rcc_clocks;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear frequency FREQ[5:0] bits */
+  tmpreg &= CR2_FREQ_Reset;
+  /* Get pclk1 frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  pclk1 = rcc_clocks.PCLK1_Frequency;
+  /* Set frequency bits depending on pclk1 value */
+  freqrange = (uint16_t)(pclk1 / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable the selected I2C peripheral to configure TRISE */
+  I2Cx->CR1 &= CR1_PE_Reset;
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;  
+    }
+    /* Set speed value for standard mode */
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time for standard mode */
+    I2Cx->TRISE = freqrange + 1; 
+  }
+  /* Configure speed in fast mode */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+      /* Set DUTY bit */
+      result |= I2C_DutyCycle_16_9;
+    }
+
+    /* Test if CCR value is under 0x1*/
+    if ((result & CCR_CCR_Set) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (uint16_t)0x0001;  
+    }
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= (uint16_t)(result | CCR_FS_Set);
+    /* Set Maximum Rise Time for fast mode */
+    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
+  }
+
+  /* Write to I2Cx CCR */
+  I2Cx->CCR = tmpreg;
+  /* Enable the selected I2C peripheral */
+  I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= CR1_PE_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= CR1_PE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C DMA requests.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR2 |= CR2_DMAEN_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR2 &= CR2_DMAEN_Reset;
+  }
+}
+
+/**
+  * @brief  Specifies if the next DMA transfer will be the last one.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA last transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Next DMA transfer is the last transfer */
+    I2Cx->CR2 |= CR2_LAST_Set;
+  }
+  else
+  {
+    /* Next DMA transfer is not the last transfer */
+    I2Cx->CR2 &= CR2_LAST_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR1 |= CR1_START_Set;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR1 &= CR1_START_Reset;
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR1 |= CR1_STOP_Set;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR1 &= CR1_STOP_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C Acknowledgement.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR1 |= CR1_ACK_Set;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR1 &= CR1_ACK_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= OAR2_ADD2_Reset;
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C general call feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C General call.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CR1 |= CR1_ENGC_Set;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CR1 &= CR1_ENGC_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_BUF: Buffer interrupt mask
+  *     @arg I2C_IT_EVT: Event interrupt mask
+  *     @arg I2C_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR2 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR2 &= (uint16_t)~I2C_IT;
+  }
+}
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->DR;
+}
+
+/**
+  * @brief  Transmits the address byte to select the slave device.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address which will be transmitted
+  * @param  I2C_Direction: specifies whether the I2C device will be a
+  *   Transmitter or a Receiver. This parameter can be one of the following values
+  *     @arg I2C_Direction_Transmitter: Transmitter mode
+  *     @arg I2C_Direction_Receiver: Receiver mode
+  * @retval None.
+  */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address bit0 for read */
+    Address |= OAR1_ADD0_Set;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= OAR1_ADD0_Reset;
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2C_Register: specifies the register to read.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Register_CR1:  CR1 register.
+  *     @arg I2C_Register_CR2:   CR2 register.
+  *     @arg I2C_Register_OAR1:  OAR1 register.
+  *     @arg I2C_Register_OAR2:  OAR2 register.
+  *     @arg I2C_Register_DR:    DR register.
+  *     @arg I2C_Register_SR1:   SR1 register.
+  *     @arg I2C_Register_SR2:   SR2 register.
+  *     @arg I2C_Register_CCR:   CCR register.
+  *     @arg I2C_Register_TRISE: TRISE register.
+  * @retval The value of the read register.
+  */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C software reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR1 |= CR1_SWRST_Set;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR1 &= CR1_SWRST_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
+  *         This function is useful in I2C Master Receiver mode when the number
+  *         of data to be received is equal to 2. In this case, this function 
+  *         should be called (with parameter I2C_NACKPosition_Next) before data 
+  *         reception starts,as described in the 2-byte reception procedure 
+  *         recommended in Reference Manual in Section: Master receiver.                
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_NACKPosition: specifies the NACK position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+  *          received byte.  
+  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last 
+  *          received byte.
+  *            
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
+  *          is intended to used in SMBUS mode. 
+  *            
+  * @retval None
+  */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+  
+  /* Check the input parameter */
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
+  {
+    /* Next byte in shift register is the last received byte */
+    I2Cx->CR1 |= I2C_NACKPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is the last received byte */
+    I2Cx->CR1 &= I2C_NACKPosition_Current;
+  }
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C PEC transfer.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C PEC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC transmission */
+    I2Cx->CR1 |= CR1_PEC_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC transmission */
+    I2Cx->CR1 &= CR1_PEC_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C PEC position.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_PECPosition: specifies the PEC position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
+  *       
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
+  *          is intended to used in I2C mode.
+  *               
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* Next byte in shift register is PEC */
+    I2Cx->CR1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is PEC */
+    I2Cx->CR1 &= I2C_PECPosition_Current;
+  }
+}
+
+/**
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CR1 |= CR1_ENPEC_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CR1 &= CR1_ENPEC_Reset;
+  }
+}
+
+/**
+  * @brief  Returns the PEC value for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The PEC value.
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the selected I2C PEC value */
+  return ((I2Cx->SR2) >> 8);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C ARP.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx ARP. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CR1 |= CR1_ENARP_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CR1 &= CR1_ENARP_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CCR &= I2C_DutyCycle_2;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
+  }
+}
+
+
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ *                         I2C State Monitoring Functions
+ *                       
+ ****************************************************************************************   
+ * This I2C driver provides three different ways for I2C state monitoring
+ *  depending on the application requirements and constraints:
+ *        
+ *  
+ * 1) Basic state monitoring:
+ *    Using I2C_CheckEvent() function:
+ *    It compares the status registers (SR1 and SR2) content to a given event
+ *    (can be the combination of one or more flags).
+ *    It returns SUCCESS if the current status includes the given flags 
+ *    and returns ERROR if one or more flags are missing in the current status.
+ *    - When to use:
+ *      - This function is suitable for most applications as well as for startup 
+ *      activity since the events are fully described in the product reference manual 
+ *      (RM0008).
+ *      - It is also suitable for users who need to define their own events.
+ *    - Limitations:
+ *      - If an error occurs (ie. error flags are set besides to the monitored flags),
+ *        the I2C_CheckEvent() function may return SUCCESS despite the communication
+ *        hold or corrupted real state. 
+ *        In this case, it is advised to use error interrupts to monitor the error
+ *        events and handle them in the interrupt IRQ handler.
+ *        
+ *        @note 
+ *        For error management, it is advised to use the following functions:
+ *          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ *          - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ *            Where x is the peripheral instance (I2C1, I2C2 ...)
+ *          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() 
+ *            in order to determine which error occured.
+ *          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ *            and/or I2C_GenerateStop() in order to clear the error flag and source,
+ *            and return to correct communication status.
+ *            
+ *
+ *  2) Advanced state monitoring:
+ *     Using the function I2C_GetLastEvent() which returns the image of both status 
+ *     registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+ *     by 16 bits and concatenated to Status Register 1).
+ *     - When to use:
+ *       - This function is suitable for the same applications above but it allows to
+ *         overcome the mentioned limitation of I2C_GetFlagStatus() function.
+ *         The returned value could be compared to events already defined in the 
+ *         library (stm32f10x_i2c.h) or to custom values defined by user.
+ *       - This function is suitable when multiple flags are monitored at the same time.
+ *       - At the opposite of I2C_CheckEvent() function, this function allows user to
+ *         choose when an event is accepted (when all events flags are set and no 
+ *         other flags are set or just when the needed flags are set like 
+ *         I2C_CheckEvent() function).
+ *     - Limitations:
+ *       - User may need to define his own events.
+ *       - Same remark concerning the error management is applicable for this 
+ *         function if user decides to check only regular communication flags (and 
+ *         ignores error flags).
+ *     
+ *
+ *  3) Flag-based state monitoring:
+ *     Using the function I2C_GetFlagStatus() which simply returns the status of 
+ *     one single flag (ie. I2C_FLAG_RXNE ...). 
+ *     - When to use:
+ *        - This function could be used for specific applications or in debug phase.
+ *        - It is suitable when only one flag checking is needed (most I2C events 
+ *          are monitored through multiple flags).
+ *     - Limitations: 
+ *        - When calling this function, the Status register is accessed. Some flags are
+ *          cleared when the status register is accessed. So checking the status
+ *          of one Flag, may clear other ones.
+ *        - Function may need to be called twice or more in order to monitor one 
+ *          single event.
+ *
+ *  For detailed description of Events, please refer to section I2C_Events in 
+ *  stm32f10x_i2c.h file.
+ *  
+ */
+
+/**
+ * 
+ *  1) Basic state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *   as parameter.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED           : EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED              : EV1
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED     : EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED        : EV1
+  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED            : EV1
+  *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED                         : EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)      : EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)    : EV2
+  *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED                      : EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)   : EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
+  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE                           : EV3_2
+  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED                         : EV4
+  *     @arg I2C_EVENT_MASTER_MODE_SELECT                          : EV5
+  *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED            : EV6     
+  *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED               : EV6
+  *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED                        : EV7
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING                    : EV8
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED                     : EV8_2
+  *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10                       : EV9
+  *     
+  * @note: For detailed description of Events, please refer to section 
+  *    I2C_Events in stm32f10x_i2c.h file.
+  *    
+  * @retval An ErrorStatus enumeration value:
+  * - SUCCESS: Last event is equal to the I2C_EVENT
+  * - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Check whether the last event contains the I2C_EVENT */
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+  /* Return status */
+  return status;
+}
+
+/**
+ * 
+ *  2) Advanced state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Returns the last I2Cx Event.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  *     
+  * @note: For detailed description of Events, please refer to section 
+  *    I2C_Events in stm32f10x_i2c.h file.
+  *    
+  * @retval The last event
+  */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_Mask;
+
+  /* Return status */
+  return lastevent;
+}
+
+/**
+ * 
+ *  3) Flag-based state monitoring
+ *******************************************************************************
+ */
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+  *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+  *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+  *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+  *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *     @arg I2C_FLAG_BUSY: Bus busy flag
+  *     @arg I2C_FLAG_MSL: Master/Slave flag
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+  *   Address matched flag (Slave mode)"ENDA"
+  *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the I2Cx peripheral base address */
+  i2cxbase = (uint32_t)I2Cx;
+  
+  /* Read flag register index */
+  i2creg = I2C_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_FLAG &= FLAG_Mask;
+  
+  if(i2creg != 0)
+  {
+    /* Get the I2Cx SR1 register address */
+    i2cxbase += 0x14;
+  }
+  else
+  {
+    /* Flag in I2Cx SR2 Register */
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+    /* Get the I2Cx SR2 register address */
+    i2cxbase += 0x18;
+  }
+  
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *   
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
+  *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
+  *     second byte of the address in DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+  *     register  (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert flag
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_IT_PECERR: PEC error in reception flag
+  *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure flag
+  *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_IT_BERR: Bus error flag
+  *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_IT_BTF: Byte transfer finished flag
+  *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+  *                       Address matched flag (Slave mode)"ENDAD"
+  *     @arg I2C_IT_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_IT &= FLAG_Mask;
+
+  /* Check the status of the specified I2C flag */
+  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx’s interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure interrupt
+  *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+  *     @arg I2C_IT_BERR: Bus error interrupt
+  *   
+  * @note
+  *   - STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *   - ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
+  *     byte of the address in I2C_DR register.
+  *   - BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *   - ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *   - SB (Start Bit) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+  /* Get the I2C flag position */
+  flagpos = I2C_IT & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
new file mode 100644
index 0000000..498d491
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
@@ -0,0 +1,196 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_iwdg.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the IWDG firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/** @defgroup IWDG_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Defines
+  * @{
+  */ 
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload    ((uint16_t)0xAAAA)
+#define KR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup IWDG_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *   This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
new file mode 100644
index 0000000..0987242
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_pwr.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the PWR firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/** @defgroup PWR_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Defines
+  * @{
+  */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the RTC and backup registers.
+  * @param  NewState: new state of the access to the RTC and backup registers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *   This parameter can be one of the following values:
+  *     @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+  *     @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+  *     @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+  *     @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+  *     @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+  *     @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+  *     @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+  *     @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  tmpreg = PWR->CR;
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDS bits */
+  tmpreg &= CR_DS_MASK;
+  /* Set LPDS bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wake-up flag */
+  PWR->CR |= PWR_CR_CWUF;
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag
+  *     @arg PWR_FLAG_SB: StandBy flag
+  *     @arg PWR_FLAG_PVDO: PVD Output
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag
+  *     @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
index a29034b..2e870f6 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
@@ -2,20 +2,26 @@
   ******************************************************************************
   * @file    stm32f10x_rcc.c
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file provides all the RCC firmware functions.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -1467,4 +1473,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT)
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
new file mode 100644
index 0000000..ec5bf10
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
@@ -0,0 +1,804 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_sdio.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the SDIO firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO 
+  * @brief SDIO driver modules
+  * @{
+  */ 
+
+/** @defgroup SDIO_Private_TypesDefinitions
+  * @{
+  */ 
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SDIO_DeInit(void)
+{
+  SDIO->POWER = 0x00000000;
+  SDIO->CLKCR = 0x00000000;
+  SDIO->ARG = 0x00000000;
+  SDIO->CMD = 0x00000000;
+  SDIO->DTIMER = 0x00000000;
+  SDIO->DLEN = 0x00000000;
+  SDIO->DCTRL = 0x00000000;
+  SDIO->ICR = 0x00C007FF;
+  SDIO->MASK = 0x00000000;
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified 
+  *         parameters in the SDIO_InitStruct.
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
+  *         that contains the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
+   
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
+  /* Get the SDIO CLKCR value */
+  tmpreg = SDIO->CLKCR;
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCR_CLEAR_MASK;
+  
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
+  
+  /* Write to SDIO CLKCR */
+  SDIO->CLKCR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
+  *   will be initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param  SDIO_PowerState: new state of the Power state. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_PowerState_OFF
+  *     @arg SDIO_PowerState_ON
+  * @retval None
+  */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+  
+  SDIO->POWER = SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  None
+  * @retval Power status of the controller. The returned value can
+  *   be one of the following:
+  * - 0x00: Power OFF
+  * - 0x02: Power UP
+  * - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(void)
+{
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @param  NewState: new state of the specified SDIO interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None 
+  */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_IT(SDIO_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIO->MASK |= SDIO_IT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIO->MASK &= ~SDIO_IT;
+  } 
+}
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param  NewState: new state of the selected SDIO DMA request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified 
+  *         parameters in the SDIO_CmdInitStruct and send the command.
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
+  *         structure that contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+  
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+  /* Set the SDIO Argument value */
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+  
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
+  /* Get the SDIO CMD value */
+  tmpreg = SDIO->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+  
+  /* Write to SDIO CMD */
+  SDIO->CMD = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response received.
+  * @param  None
+  * @retval Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(void)
+{
+  return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_RESP1: Response Register 1
+  *     @arg SDIO_RESP2: Response Register 2
+  *     @arg SDIO_RESP3: Response Register 3
+  *     @arg SDIO_RESP4: Response Register 4
+  * @retval The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
+  
+  return (*(__IO uint32_t *) tmp); 
+}
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified 
+  *   parameters in the SDIO_DataInitStruct.
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+  *   contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIO Data TimeOut value */
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+  /* Set the SDIO DataLength value */
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
+  /* Get the SDIO DCTRL value */
+  tmpreg = SDIO->DCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIO DCTRL */
+  SDIO->DCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  None
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(void)
+{ 
+  return SDIO->DCOUNT;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  None
+  * @retval Data received
+  */
+uint32_t SDIO_ReadData(void)
+{ 
+  return SDIO->FIFO;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param  Data: 32-bit data word to write.
+  * @retval None
+  */
+void SDIO_WriteData(uint32_t Data)
+{ 
+  SDIO->FIFO = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read from FIFO.	
+  * @param  None
+  * @retval Remaining number of words.
+  */
+uint32_t SDIO_GetFIFOCount(void)
+{ 
+  return SDIO->FIFOCNT;
+}
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Start SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *   This parameter can be:
+  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+  
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param  NewState: new state of SDIO specific operation. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param  NewState: new state of the SD I/O Mode suspend command.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param  NewState: new state of command completion signal. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param  SDIO_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                              bus mode.
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *     @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{ 
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+  
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  SDIO_FLAG: specifies the flag to clear.  
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
+  *                              bus mode
+  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+   
+  SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_IT (SET or RESET).
+  */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{ 
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be one or a combination of the following values:
+  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                            bus mode interrupt
+  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+   
+  SDIO->ICR = SDIO_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
index 4ec65b2..b901d3f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
@@ -2,20 +2,26 @@
   ******************************************************************************
   * @file    stm32f10x_spi.c
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
+  * @version V3.6.1
+  * @date    05-March-2012
   * @brief   This file provides all the SPI firmware functions.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
@@ -905,4 +911,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
   * @}
   */ 
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
new file mode 100644
index 0000000..aa628a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
@@ -0,0 +1,2896 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_tim.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the TIM firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM driver modules
+  * @{
+  */
+
+/** @defgroup TIM_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Defines
+  * @{
+  */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_Mask               ((uint16_t)0x00FF) 
+#define CCMR_Offset                 ((uint16_t)0x0018)
+#define CCER_CCE_Set                ((uint16_t)0x0001)  
+#define	CCER_CCNE_Set               ((uint16_t)0x0004) 
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+  * @{
+  */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval None
+  */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+ 
+  if (TIMx == TIM1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  }     
+  else if (TIMx == TIM2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+  }
+  else if (TIMx == TIM3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+  }
+  else if (TIMx == TIM4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+  } 
+  else if (TIMx == TIM5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+  } 
+  else if (TIMx == TIM6)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+  } 
+  else if (TIMx == TIM7)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+  } 
+  else if (TIMx == TIM8)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+  }
+  else if (TIMx == TIM9)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
+   }  
+  else if (TIMx == TIM10)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
+  }  
+  else if (TIMx == TIM11) 
+  {     
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
+  }  
+  else if (TIMx == TIM12)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
+  }  
+  else if (TIMx == TIM13) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
+  }
+  else if (TIMx == TIM14) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
+  }        
+  else if (TIMx == TIM15)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+  } 
+  else if (TIMx == TIM16)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+  } 
+  else
+  {
+    if (TIMx == TIM17)
+    {
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+    }  
+  }
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+  *         structure that contains the configuration information for the 
+  *         specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+  tmpcr1 = TIMx->CR1;  
+
+  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
+     (TIMx == TIM4) || (TIMx == TIM5)) 
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+  }
+ 
+  if((TIMx != TIM6) && (TIMx != TIM7))
+  {
+    /* Set the clock division */
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+    
+  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler and the Repetition counter
+     values immediately */
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
+}
+
+/**
+  * @brief  Initializes the TIMx Channel1 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+ /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+  
+  /* Set the Output State */
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+    
+  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
+     (TIMx == TIM16)|| (TIMx == TIM17))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
+    /* Set the Output N Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+    
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
+    /* Set the Output N State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
+ 
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel2 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+   /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+    
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+    
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
+    
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel3 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
+    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel4 according to the specified
+  *         parameters in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+  /* Disable the Channel 2: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
+  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+  }
+  else
+  {
+    assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+  {
+    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI3 Configuration */
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+    /* TI4 Configuration */
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM peripheral according to the specified
+  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    icoppositepolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TIM_ICPolarity_Rising;
+  }
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    icoppositeselection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TIM_ICSelection_DirectTI;
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI2 Configuration */
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  { 
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI1 Configuration */
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+  *         the OSSR State and the AOE(automatic output enable).
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval None
+  */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
+  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+  TIM_OCInitStruct->TIM_Pulse = 0x0000;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Main Output */
+    TIMx->BDTR |= TIM_BDTR_MOE;
+  }
+  else
+  {
+    /* Disable the TIM Main Output */
+    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified TIM interrupts.
+  * @param  TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_IT_Update: TIM update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note 
+  *   - TIM6 and TIM7 can only generate an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @param  NewState: new state of the TIM interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (uint16_t)~TIM_IT;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx event to be generate by software.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_EventSource: specifies the event source.
+  *   This parameter can be one or more of the following values:	   
+  *     @arg TIM_EventSource_Update: Timer update Event source
+  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *     @arg TIM_EventSource_COM: Timer COM event source  
+  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *     @arg TIM_EventSource_Break: Timer Break event source
+  * @note 
+  *   - TIM6 and TIM7 can only generate an update event. 
+  *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.      
+  * @retval None
+  */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+  
+  /* Set the event sources */
+  TIMx->EGR = TIM_EventSource;
+}
+
+/**
+  * @brief  Configures the TIMx's DMA interface.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
+  *   the TIM peripheral.
+  * @param  TIM_DMABase: DMA Base address.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+  *          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+  *          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+  *          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+  *          TIM_DMABase_DCR.
+  * @param  TIM_DMABurstLength: DMA Burst length.
+  *   This parameter can be one value between:
+  *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+  /* Set the DMA Base and the DMA Burst Length */
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's DMA Requests.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 
+  *   to select the TIM peripheral. 
+  * @param  TIM_DMASource: specifies the DMA Request sources.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_DMA_Update: TIM update Interrupt source
+  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *     @arg TIM_DMA_COM: TIM Commutation DMA source
+  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIMx->DIER |= TIM_DMASource; 
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx internal Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15
+  *         to select the TIM peripheral.
+  * @retval None
+  */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+}
+
+/**
+  * @brief  Configures the TIMx Internal Trigger as External Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ITRSource: Trigger source.
+  *   This parameter can be one of the following values:
+  * @param  TIM_TS_ITR0: Internal Trigger 0
+  * @param  TIM_TS_ITR1: Internal Trigger 1
+  * @param  TIM_TS_ITR2: Internal Trigger 2
+  * @param  TIM_TS_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TIMx Trigger as External Clock
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  ICFilter : specifies the filter value.
+  *   This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  /* Select the External clock mode1 */
+  tmpsmcr |= TIM_SlaveMode_External1;
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  tmpsmcr |= TIM_TS_ETRF;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= TIM_SMCR_ECE;
+}
+
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *   This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMCR_ETR_Mask;
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TIMx Prescaler.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+  *   This parameter can be one of the following values:
+  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+  * @retval None
+  */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+  /* Set or reset the UG Bit */
+  TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIMx Counter Mode to be used.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
+  *   This parameter can be one of the following values:
+  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
+  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
+  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+  * @retval None
+  */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+  tmpcr1 = TIMx->CR1;
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+  /* Write to TIMx CR1 register */
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_TS_ITR0: Internal Trigger 0
+  *     @arg TIM_TS_ITR1: Internal Trigger 1
+  *     @arg TIM_TS_ITR2: Internal Trigger 2
+  *     @arg TIM_TS_ITR3: Internal Trigger 3
+  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *     @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+  /* Set the Input Trigger source */
+  tmpsmcr |= TIM_InputTriggerSource;
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the TIMx Encoder Interface.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                on the level of the other input.
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+  tmpsmcr |= TIM_EncoderMode;
+  
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+  
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+  
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
+  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
+  * @param  TIMx: where x can be  1 to 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx peripheral Preload register
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TIMx->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM peripheral Commutation event.
+  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TIMx->CR2 |= TIM_CR2_CCUS;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
+  }
+}
+
+/**
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 
+  *         the TIM peripheral.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIMx->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+  * @param  TIMx: where x can be   1, 2, 3, 4, 5, 8 or 15 
+  *         to select the TIMx peripheral
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TIMx->CR2 |= TIM_CR2_CCPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPreload_Enable
+  *     @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 
+  *         the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TIM_OCClear;
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr1 = TIMx->CCMR1;
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TIM_OCClear;
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCClear_Enable: TIM Output clear enable
+  *     @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+  tmpccmr2 = TIMx->CCMR2;
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx channel 1 polarity.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
+  tmpccer |= TIM_OCPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 1N polarity.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+   
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
+  tmpccer |= TIM_OCNPolarity;
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 2 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 2N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+  
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 3 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 3N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCNPolarity_High: Output Compare active high
+  *     @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+    
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 4 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCPolarity_High: Output Compare active high
+  *     @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+  tmpccer = TIMx->CCER;
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  *     @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCX(TIM_CCx));
+
+  tmp = CCER_CCE_Set << TIM_Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t)~ tmp;
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+  *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
+  */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+  tmp = CCER_CCNE_Set << TIM_Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+  * @brief  Selects the TIM Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode.
+  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Channel_1: TIM Channel 1
+  *     @arg TIM_Channel_2: TIM Channel 2
+  *     @arg TIM_Channel_3: TIM Channel 3
+  *     @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCMode_Timing
+  *     @arg TIM_OCMode_Active
+  *     @arg TIM_OCMode_Toggle
+  *     @arg TIM_OCMode_PWM1
+  *     @arg TIM_OCMode_PWM2
+  *     @arg TIM_ForcedAction_Active
+  *     @arg TIM_ForcedAction_InActive
+  * @retval None
+  */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_OCM(TIM_OCMode));
+
+  tmp = (uint32_t) TIMx;
+  tmp += CCMR_Offset;
+
+  tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp1;
+
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+  {
+    tmp += (TIM_Channel>>1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
+   
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
+  }
+  else
+  {
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
+    
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Enables or Disables the TIMx Update event.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx UDIS bit
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TIMx->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_UpdateSource: specifies the Update source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow
+                                       or the setting of UG bit, or an update generation
+                                       through the slave mode controller.
+  *     @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TIMx->CR1 |= TIM_CR1_URS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx Hall sensor interface.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @brief  Selects the TIMx's One Pulse Mode.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OPMode_Single
+  *     @arg TIM_OPMode_Repetitive
+  * @retval None
+  */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+  /* Reset the OPM Bit */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
+  /* Configure the OPM Mode */
+  TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
+  *   This paramter can be one of the following values:
+  *
+  *  - For all TIMx
+  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+  *
+  *  - For all TIMx except TIM6 and TIM7
+  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
+  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TIMx Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+  *                               the counter and triggers an update of the registers.
+  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
+  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
+  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+  * @retval None
+  */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
+  /* Select the Slave Mode */
+  TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                      and its slaves (through TRGO).
+  *     @arg TIM_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+  /* Reset the MSM Bit */
+  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
+  
+  /* Set or Reset the MSM Bit */
+  TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+  * @brief  Sets the TIMx Counter Register value
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Set the Counter Register value */
+  TIMx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TIMx Autoreload Register value
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare1 Register value
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare2 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare3 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare4 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC1PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
+  /* Set the IC1PSC value */
+  TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC2PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
+  /* Set the IC2PSC value */
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC3PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
+  /* Set the IC3PSC value */
+  TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPSC_DIV1: no prescaler
+  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+  /* Reset the IC4PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
+  /* Set the IC4PSC value */
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Clock Division value.
+  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select 
+  *   the TIM peripheral.
+  * @param  TIM_CKD: specifies the clock division value.
+  *   This parameter can be one of the following value:
+  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
+  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+  /* Reset the CKD Bits */
+  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
+  /* Set the CKD value */
+  TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 1 value.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 2 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 3 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 3 Register value.
+  */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 4 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 4 Register value.
+  */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/**
+  * @brief  Gets the TIMx Counter value.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval Counter Register value.
+  */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/**
+  * @brief  Gets the TIMx Prescaler value.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/**
+  * @brief  Checks whether the specified TIM flag is set or not.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_FLAG_Update: TIM update Flag
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *     @arg TIM_FLAG_COM: TIM Commutation Flag
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *     @arg TIM_FLAG_Break: TIM Break Flag
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  * @note
+  *   - TIM6 and TIM7 can have only one update flag. 
+  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @retval The new state of TIM_FLAG (SET or RESET).
+  */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{ 
+  ITStatus bitstatus = RESET;  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+  
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's pending flags.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_FLAG_Update: TIM update Flag
+  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *     @arg TIM_FLAG_COM: TIM Commutation Flag
+  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *     @arg TIM_FLAG_Break: TIM Break Flag
+  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+  * @note
+  *   - TIM6 and TIM7 can have only one update flag. 
+  *   - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+  *      TIM_FLAG_CC2 or TIM_FLAG_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
+  *   - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.   
+  * @retval None
+  */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+   
+  /* Clear the flags */
+  TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TIM interrupt has occurred or not.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_IT_Update: TIM update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note
+  *   - TIM6 and TIM7 can generate only an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.  
+  * @retval The new state of the TIM_IT(SET or RESET).
+  */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_IT(TIM_IT));
+   
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's interrupt pending bits.
+  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg TIM_IT_Update: TIM1 update Interrupt source
+  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *     @arg TIM_IT_Break: TIM Break Interrupt source
+  * @note
+  *   - TIM6 and TIM7 can generate only an update interrupt.
+  *   - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+  *      TIM_IT_CC2 or TIM_IT_Trigger. 
+  *   - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
+  *   - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 
+  *   - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.    
+  * @retval None
+  */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  /* Clear the IT pending Bit */
+  TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+  }
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
+    tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
+  }
+  
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+    
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
+  }
+  
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICPolarity_Rising
+  *     @arg TIM_ICPolarity_Falling
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *   This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+   /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+     (TIMx == TIM4) ||(TIMx == TIM5))
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
+    tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+  }
+  else
+  {
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
+    tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
+  }
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
new file mode 100644
index 0000000..7f01f12
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
@@ -0,0 +1,1065 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_usart.c
+  * @author  MCD Application Team
+  * @version V3.6.1
+  * @date    05-March-2012
+  * @brief   This file provides all the USART firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/** @defgroup USART_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Defines
+  * @{
+  */
+
+#define CR1_UE_Set                ((uint16_t)0x2000)  /*!< USART Enable Mask */
+#define CR1_UE_Reset              ((uint16_t)0xDFFF)  /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask             ((uint16_t)0xF7FF)  /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set               ((uint16_t)0x0002)  /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset             ((uint16_t)0xFFFD)  /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set               ((uint16_t)0x0001)  /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /*!< USART CR1 Mask */
+#define CR2_Address_Mask          ((uint16_t)0xFFF0)  /*!< USART address Mask */
+
+#define CR2_LINEN_Set              ((uint16_t)0x4000)  /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset            ((uint16_t)0xBFFF)  /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask             ((uint16_t)0xFFDF)  /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set              ((uint16_t)0x0020)  /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset            ((uint16_t)0xFFDF)  /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set              ((uint16_t)0x0010)  /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset            ((uint16_t)0xFFEF)  /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set             ((uint16_t)0x0008)  /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask             ((uint16_t)0xFFFB)  /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set              ((uint16_t)0x0002)  /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset            ((uint16_t)0xFFFD)  /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask             ((uint16_t)0x00FF)  /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask             ((uint16_t)0xFF00)  /*!< Guard Time Register MSB Mask */
+#define IT_Mask                   ((uint16_t)0x001F)  /*!< USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CR1_OVER8_Set             ((u16)0x8000)  /* USART OVER8 mode Enable Mask */
+#define CR1_OVER8_Reset           ((u16)0x7FFF)  /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CR3_ONEBITE_Set           ((u16)0x0800)  /* USART ONEBITE mode Enable Mask */
+#define CR3_ONEBITE_Reset         ((u16)0xF7FF)  /* USART ONEBITE mode Disable Mask */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values: 
+  *      USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }    
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }    
+  else
+  {
+    if (USARTx == UART5)
+    { 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART 
+  *         peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  uint32_t usartxbase = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  /* The hardware flow control is available only for USART1, USART2 and USART3 */
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+
+  usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= CR2_STOP_CLEAR_Mask;
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= CR1_CLEAR_Mask;
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+  /* Write to USART CR1 */
+  USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= CR3_CLEAR_Mask;
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  /* Write to USART CR3 */
+  USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  if (usartxbase == USART1_BASE)
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+  {
+    /* Integer part computing in case Oversampling mode is 8 Samples */
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* Integer part computing in case Oversampling mode is 16 Samples */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  tmpreg = (integerdivider / 100) << 4;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  /* Implement the fractional part in the register */
+  if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+  
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *          specified parameters in the USART_ClockInitStruct .
+  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified 
+  *         USART peripheral.  
+  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= CR2_CLOCK_CLEAR_Mask;
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *         This parameter can be one of the following values:
+  *           USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= CR1_UE_Set;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= CR1_UE_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TXE:  Transmit Data Register empty interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *     @arg USART_IT_IDLE: Idle line detection interrupt
+  *     @arg USART_IT_PE:   Parity Error interrupt
+  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_Mask;
+  itmask = (((uint32_t)0x01) << itpos);
+    
+  if (usartreg == 0x01) /* The IT is in CR1 register */
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x10;
+  }
+  else /* The IT is in CR3 register */
+  {
+    usartxbase += 0x14; 
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART’s DMA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_DMAReq_Tx: USART DMA transmit request
+  *     @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note The DMA mode is not available for UART5 except in the STM32
+  *       High density value line devices(STM32F10X_HD_VL).  
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
+  USARTx->CR2 &= CR2_Address_Mask;
+  /* Set the USART address node */
+  USARTx->CR2 |= USART_Address;
+}
+
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *   This parameter can be one of the following values:
+  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+  
+  USARTx->CR1 &= CR1_WAKE_Mask;
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART mute mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+    USARTx->CR1 |= CR1_RWU_Set;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+    USARTx->CR1 &= CR1_RWU_Reset;
+  }
+}
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *   This parameter can be one of the following values:
+  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+  
+  USARTx->CR2 &= CR2_LBDL_Mask;
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART’s LIN mode.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART LIN mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= CR2_LINEN_Set;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= CR2_LINEN_Reset;
+  }
+}
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval None
+  */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Send break characters */
+  USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @note The guard time bits are not available for UART4 and UART5.   
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= GTPR_LSB_Mask;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Prescaler: specifies the prescaler clock.  
+  * @note   The function is used for IrDA mode with UART4 and UART5.
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= GTPR_MSB_Mask;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the USART’s Smart Card mode.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+  *   This parameter can be: ENABLE or DISABLE.     
+  * @note The Smart Card mode is not available for UART4 and UART5. 
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= CR3_SCEN_Set;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= CR3_SCEN_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the USART peripheral. 
+  * @param  NewState: new state of the NACK transmission.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @note The Smart Card mode is not available for UART4 and UART5.
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= CR3_NACK_Set;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= CR3_NACK_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART’s Half Duplex communication.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART Communication.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= CR3_HDSEL_Set;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= CR3_HDSEL_Reset;
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note
+  *     This function has to be called before calling USART_Init()
+  *     function in order to have correct baudrate Divider value.   
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= CR1_OVER8_Set;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= CR1_OVER8_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: Select the USART or the UART peripheral.
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= CR3_ONEBITE_Set;
+  }
+  else
+  {
+    /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= CR3_ONEBITE_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IrDAMode_LowPower
+  *     @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+    
+  USARTx->CR3 &= CR3_IRLP_Mask;
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the IrDA mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= CR3_IREN_Set;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= CR3_IREN_Reset;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag
+  *     @arg USART_FLAG_TXE:  Transmit data register empty flag
+  *     @arg USART_FLAG_TC:   Transmission Complete flag
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag
+  *     @arg USART_FLAG_IDLE: Idle Line detection flag
+  *     @arg USART_FLAG_ORE:  OverRun Error flag
+  *     @arg USART_FLAG_NE:   Noise Error flag
+  *     @arg USART_FLAG_FE:   Framing Error flag
+  *     @arg USART_FLAG_PE:   Parity Error flag
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+  /* The CTS flag is not available for UART4 and UART5 */
+  if (USART_FLAG == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }  
+  
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *     @arg USART_FLAG_TC:   Transmission Complete flag.
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) flags are cleared by software 
+  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
+  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
+  *   - RXNE flag can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - TC flag can be also cleared by software sequence: a read operation to 
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *     to USART_DR register (USART_SendData()).
+  *   - TXE flag is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+  /* The CTS flag is not available for UART4 and UART5 */
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+   
+  USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *     @arg USART_IT_IDLE: Idle line detection interrupt
+  *     @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
+  *     @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set 
+  *     @arg USART_IT_NE:   Noise Error interrupt
+  *     @arg USART_IT_FE:   Framing Error interrupt
+  *     @arg USART_IT_PE:   Parity Error interrupt
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT));
+  /* The CTS interrupt is not available for UART4 and UART5 */ 
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_Mask;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->SR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: Select the USART or the UART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt. 
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+  *   
+  * @note
+  *   - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) pending bits are cleared by 
+  *     software sequence: a read operation to USART_SR register 
+  *     (USART_GetITStatus()) followed by a read operation to USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - RXNE pending bit can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  *   - TC pending bit can be also cleared by software sequence: a read 
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *     operation to USART_DR register (USART_SendData()).
+  *   - TXE pending bit is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT));
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }   
+  
+  bitpos = USART_IT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->SR = (uint16_t)~itmask;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/Release_Notes.html
new file mode 100644
index 0000000..59153a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/Release_Notes.html
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+</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-fareast-font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]-->
+<style type="disc">
+</style><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="45058"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><br>
+</span><span style="font-family: Arial;"><o:p></o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0cm;" valign="top">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 1.5pt;">
+
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32F30x Standard Peripherals Library Drivers (StdPeriph_Drivers)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>
+<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0cm;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+<ol style="margin-top: 0cm;" start="1" type="1">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F30x Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
+</ol>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F30x Standard Peripherals Library Drivers update history<o:p></o:p></span></h2>
+
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 23-October-2012<o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+
+
+
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_adc.c/h<o:p></o:p></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove
+the following functions, the configuration will be done under ADC_Init function :</span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_InjectedSequencerLengthConfig;
+<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_InjectedChannelConfig;<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">ADC_ExternalTriggerInjectedPolarityConfig;<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-style: italic;">ADC_SelectExternalTriggerInjected</span><o:p></o:p></span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update
+&nbsp;comment of <span style="font-style: italic;">uint8_t ADC_TwoSamplingDelay</span> parameter in
+<span style="font-style: italic;">ADC_CommonInitTypeDef</span> structure definition.<o:p></o:p></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>Add
+a function to configure the sampling time for injected channels&nbsp;<o:p></o:p>: <span style="font-style: italic;">void
+ADC_InjectedChannelSampleTimeConfig (ADC_TypeDef* ADCx, uint8_t
+ADC_InjectedChannel, uint8_t ADC_SampleTime);</span></span></p></li></ul></ul>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<p style="margin-left: 40px;" class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>
+<o:p></o:p></span></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">stm32f30x_rtc.c</span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update
+comments : remove all reference to RTC_AF1<o:p></o:p>, reformulate
+the PC13 RTC_AF table to be in line with the description in Reference&nbsp;manual (RM00316)</span></p></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+
+
+
+<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p>stm32f30x_tim.c
+<o:p></o:p></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update local variables declaration (must be uint32_t) to correct&nbsp;Tasking toochain warnings. &nbsp;</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p>stm32f30x_gpio.h
+<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Update <span style="font-style: italic;">GPIOSpeed_TypeDef </span>parameters structure to be in line with description in Reference manual and add GPIO&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">speed</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> legacy defines.</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Remove all references to other products (STM32F37x, STM32F0xx,...) in the comments.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 04-September-2012<o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for <span style="font-style: italic; font-weight: bold;">STM32F30x and STM32F31x devices</span></span></li></ul>
+            <span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
+
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">Licensed 
+under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use 
+this&nbsp;</span><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">package</span><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"> 
+except in compliance with the License. You may obtain a copy of the License 
+at:<br><br></span></p>
+<div style="text-align: center;"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
+<a href="http://www.st.com/software_license_agreement_liberty_v2" target="_blank">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"></span></div><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';"><br>Unless 
+required by applicable law or agreed to in writing, software distributed under 
+the License is distributed on an "AS IS" BASIS, <br>WITHOUT WARRANTIES OR 
+CONDITIONS OF ANY KIND, either express or implied. See the License for the 
+specific language governing permissions and limitations under the 
+License.</span><b><span style="font-size: 10pt; color: black; font-family: Verdana;"></span></b><p class="MsoNormal" style="margin: 4.5pt 0cm;"><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></p>
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; color: black; font-family: 'Verdana','sans-serif';">For 
+complete documentation on </span><span style="font-size: 10pt; font-family: 'Verdana','sans-serif';">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h
new file mode 100644
index 0000000..2a1fd59
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_adc.h
@@ -0,0 +1,820 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_adc.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_ADC_H
+#define __STM32F30x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+typedef struct
+{
+
+  uint32_t ADC_ContinuousConvMode;        /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution.
+                                               This parameter can be a value of @ref ADC_resolution */ 
+  uint32_t ADC_ExternalTrigConvEvent;      /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+  uint32_t ADC_ExternalTrigEventEdge;      /*!< Select the external trigger edge and enable the trigger of a regular group.                                               
+                                               This parameter can be a value of 
+                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+  uint32_t ADC_OverrunMode;               /*!< Specifies the way data overrun are managed.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ADC_AutoInjMode;               /*!< Enable/disable automatic injected group conversion after
+                                               regular group conversion.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint8_t ADC_NbrOfRegChannel;            /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+
+/**
+  * @}
+  */
+/** 
+  * @brief  ADC Init structure definition  
+  */
+typedef struct
+{
+
+   uint32_t ADC_ExternalTrigInjecConvEvent;     /*!< Defines the external trigger used to start the analog
+                                                     to digital conversion of injected channels. This parameter
+                                                     can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
+  uint32_t ADC_ExternalTrigInjecEventEdge;     /*!< Select the external trigger edge and enable the trigger of an injected group. 
+                                                    This parameter can be a value of 
+                                                    @ref ADC_external_trigger_edge_for_Injected_channels_conversion */
+  uint8_t ADC_NbrOfInjecChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                                    using the sequencer for injected channel group.
+                                                    This parameter must range from 1 to 4. */ 
+  uint32_t ADC_InjecSequence1; 
+  uint32_t ADC_InjecSequence2;
+  uint32_t ADC_InjecSequence3;
+  uint32_t ADC_InjecSequence4;                                            
+}ADC_InjectedInitTypeDef;
+
+/**
+  * @}
+  */
+typedef struct 
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
+                                               independent or multi mode. 
+                                               This parameter can be a value of @ref ADC_mode */                                              
+  uint32_t ADC_Clock;                    /*!< Select the clock of the ADC. The clock is common for both master 
+                                              and slave ADCs.
+                                              This parameter can be a value of @ref ADC_Clock */
+  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access mode for multi ADC mode.                                               
+                                               This parameter can be a value of 
+                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
+  uint32_t ADC_DMAMode;                  /*!< Configures the DMA mode for ADC.                                             
+                                              This parameter can be a value of @ref ADC_DMA_Mode_definition */
+  uint8_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
+                                               This parameter can be a value between  0x0 and 0xF  */
+  
+}ADC_CommonInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3) || \
+                                   ((PERIPH) == ADC4))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3) || \
+                                   ((PERIPH) == ADC4))
+
+/** @defgroup ADC_ContinuousConvMode 
+  * @{
+  */
+#define ADC_ContinuousConvMode_Enable	 ((uint32_t)0x00002000)  /*!<  ADC continuous conversion mode enable */
+#define ADC_ContinuousConvMode_Disable	 ((uint32_t)0x00000000)  /*!<  ADC continuous conversion mode disable */
+#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
+                               ((MODE) == ADC_ContinuousConvMode_Disable))
+/**
+  * @}
+  */
+/** @defgroup ADC_OverunMode 
+  * @{
+  */
+#define ADC_OverrunMode_Enable	 ((uint32_t)0x00001000)  /*!<  ADC Overrun Mode enable */
+#define ADC_OverrunMode_Disable	 ((uint32_t)0x00000000)  /*!<  ADC Overrun Mode disable */
+#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
+                                ((MODE) == ADC_OverrunMode_Disable))
+/**
+  * @}
+  */
+/** @defgroup ADC_AutoInjecMode 
+  * @{
+  */
+#define ADC_AutoInjec_Enable	 ((uint32_t)0x02000000)  /*!<  ADC Auto injected Mode enable */
+#define ADC_AutoInjec_Disable	 ((uint32_t)0x00000000)  /*!<  ADC Auto injected Mode disable */
+#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
+                                    ((MODE) == ADC_AutoInjec_Disable))
+/**
+  * @}
+  */
+/** @defgroup ADC_resolution 
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)  /*!<  ADC 12-bit resolution */
+#define ADC_Resolution_10b                         ((uint32_t)0x00000008)  /*!<  ADC 10-bit resolution */
+#define ADC_Resolution_8b                          ((uint32_t)0x00000010)  /*!<  ADC 8-bit resolution */
+#define ADC_Resolution_6b                          ((uint32_t)0x00000018)  /*!<  ADC 6-bit resolution */
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+                                      
+/**
+  * @}
+  */ 
+  
+  
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
+  */
+#define ADC_ExternalTrigEventEdge_None            ((uint16_t)0x0000)     /*!<  ADC No external trigger for regular conversion */
+#define ADC_ExternalTrigEventEdge_RisingEdge      ((uint16_t)0x0400)     /*!<  ADC external trigger rising edge for regular conversion */
+#define ADC_ExternalTrigEventEdge_FallingEdge     ((uint16_t)0x0800)     /*!<  ADC ADC external trigger falling edge for regular conversion */
+#define ADC_ExternalTrigEventEdge_BothEdge        ((uint16_t)0x0C00)     /*!<  ADC ADC external trigger both edges for regular conversion */
+
+#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
+                                    ((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
+                                    ((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
+                                    ((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
+  
+/**
+  * @}
+  */
+   
+/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion 
+  * @{
+  */     
+#define ADC_ExternalTrigInjecEventEdge_None		     ((uint16_t)0x0000)    /*!<  ADC No external trigger for regular conversion */
+#define ADC_ExternalTrigInjecEventEdge_RisingEdge	 ((uint16_t)0x0040)    /*!<  ADC external trigger rising edge for injected conversion */
+#define ADC_ExternalTrigInjecEventEdge_FallingEdge	 ((uint16_t)0x0080)  /*!<  ADC external trigger falling edge for injected conversion */
+#define ADC_ExternalTrigInjecEventEdge_BothEdge	     ((uint16_t)0x00C0)  /*!<  ADC external trigger both edges for injected conversion */
+
+#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
+                                       ((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
+                                       ((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
+                                       ((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
+  
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+#define ADC_ExternalTrigConvEvent_0              ((uint16_t)0x0000)   /*!<  ADC external trigger event 0 */
+#define ADC_ExternalTrigConvEvent_1              ((uint16_t)0x0040)   /*!<  ADC external trigger event 1 */
+#define ADC_ExternalTrigConvEvent_2              ((uint16_t)0x0080)   /*!<  ADC external trigger event 2 */
+#define ADC_ExternalTrigConvEvent_3              ((uint16_t)0x00C0)   /*!<  ADC external trigger event 3 */
+#define ADC_ExternalTrigConvEvent_4              ((uint16_t)0x0100)   /*!<  ADC external trigger event 4 */
+#define ADC_ExternalTrigConvEvent_5              ((uint16_t)0x0140)   /*!<  ADC external trigger event 5 */
+#define ADC_ExternalTrigConvEvent_6              ((uint16_t)0x0180)   /*!<  ADC external trigger event 6 */
+#define ADC_ExternalTrigConvEvent_7              ((uint16_t)0x01C0)   /*!<  ADC external trigger event 7 */
+#define ADC_ExternalTrigConvEvent_8              ((uint16_t)0x0200)   /*!<  ADC external trigger event 8 */
+#define ADC_ExternalTrigConvEvent_9              ((uint16_t)0x0240)   /*!<  ADC external trigger event 9 */
+#define ADC_ExternalTrigConvEvent_10             ((uint16_t)0x0280)   /*!<  ADC external trigger event 10 */
+#define ADC_ExternalTrigConvEvent_11             ((uint16_t)0x02C0)   /*!<  ADC external trigger event 11 */
+#define ADC_ExternalTrigConvEvent_12             ((uint16_t)0x0300)   /*!<  ADC external trigger event 12 */
+#define ADC_ExternalTrigConvEvent_13             ((uint16_t)0x0340)   /*!<  ADC external trigger event 13 */
+#define ADC_ExternalTrigConvEvent_14             ((uint16_t)0x0380)   /*!<  ADC external trigger event 14 */
+#define ADC_ExternalTrigConvEvent_15             ((uint16_t)0x03C0)   /*!<  ADC external trigger event 15 */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConvEvent_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion 
+  * @{
+  */
+        
+#define ADC_ExternalTrigInjecConvEvent_0              ((uint16_t)0x0000)  /*!<  ADC external trigger for injected conversion event 0 */
+#define ADC_ExternalTrigInjecConvEvent_1              ((uint16_t)0x0004)  /*!<  ADC external trigger for injected conversion event 1 */
+#define ADC_ExternalTrigInjecConvEvent_2              ((uint16_t)0x0008)  /*!<  ADC external trigger for injected conversion event 2 */
+#define ADC_ExternalTrigInjecConvEvent_3              ((uint16_t)0x000C)  /*!<  ADC external trigger for injected conversion event 3 */
+#define ADC_ExternalTrigInjecConvEvent_4              ((uint16_t)0x0010)  /*!<  ADC external trigger for injected conversion event 4 */
+#define ADC_ExternalTrigInjecConvEvent_5              ((uint16_t)0x0014)  /*!<  ADC external trigger for injected conversion event 5 */
+#define ADC_ExternalTrigInjecConvEvent_6              ((uint16_t)0x0018)  /*!<  ADC external trigger for injected conversion event 6 */
+#define ADC_ExternalTrigInjecConvEvent_7              ((uint16_t)0x001C)  /*!<  ADC external trigger for injected conversion event 7 */
+#define ADC_ExternalTrigInjecConvEvent_8              ((uint16_t)0x0020)  /*!<  ADC external trigger for injected conversion event 8 */
+#define ADC_ExternalTrigInjecConvEvent_9              ((uint16_t)0x0024)  /*!<  ADC external trigger for injected conversion event 9 */
+#define ADC_ExternalTrigInjecConvEvent_10             ((uint16_t)0x0028)  /*!<  ADC external trigger for injected conversion event 10 */
+#define ADC_ExternalTrigInjecConvEvent_11             ((uint16_t)0x002C)  /*!<  ADC external trigger for injected conversion event 11 */
+#define ADC_ExternalTrigInjecConvEvent_12             ((uint16_t)0x0030)  /*!<  ADC external trigger for injected conversion event 12 */
+#define ADC_ExternalTrigInjecConvEvent_13             ((uint16_t)0x0034)  /*!<  ADC external trigger for injected conversion event 13 */
+#define ADC_ExternalTrigInjecConvEvent_14             ((uint16_t)0x0038)  /*!<  ADC external trigger for injected conversion event 14 */
+#define ADC_ExternalTrigInjecConvEvent_15             ((uint16_t)0x003C)  /*!<  ADC external trigger for injected conversion event 15 */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
+/**
+  * @}
+  */
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)  /*!<  ADC Data alignment right */
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000020)  /*!<  ADC Data alignment left */
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_1                               ((uint8_t)0x01)    /*!<  ADC Channel 1 */
+#define ADC_Channel_2                               ((uint8_t)0x02)    /*!<  ADC Channel 2 */
+#define ADC_Channel_3                               ((uint8_t)0x03)    /*!<  ADC Channel 3 */
+#define ADC_Channel_4                               ((uint8_t)0x04)    /*!<  ADC Channel 4 */
+#define ADC_Channel_5                               ((uint8_t)0x05)    /*!<  ADC Channel 5 */
+#define ADC_Channel_6                               ((uint8_t)0x06)    /*!<  ADC Channel 6 */
+#define ADC_Channel_7                               ((uint8_t)0x07)    /*!<  ADC Channel 7 */
+#define ADC_Channel_8                               ((uint8_t)0x08)    /*!<  ADC Channel 8 */
+#define ADC_Channel_9                               ((uint8_t)0x09)    /*!<  ADC Channel 9 */
+#define ADC_Channel_10                              ((uint8_t)0x0A)    /*!<  ADC Channel 10 */
+#define ADC_Channel_11                              ((uint8_t)0x0B)    /*!<  ADC Channel 11 */
+#define ADC_Channel_12                              ((uint8_t)0x0C)    /*!<  ADC Channel 12 */
+#define ADC_Channel_13                              ((uint8_t)0x0D)    /*!<  ADC Channel 13 */
+#define ADC_Channel_14                              ((uint8_t)0x0E)    /*!<  ADC Channel 14 */
+#define ADC_Channel_15                              ((uint8_t)0x0F)    /*!<  ADC Channel 15 */
+#define ADC_Channel_16                              ((uint8_t)0x10)    /*!<  ADC Channel 16 */
+#define ADC_Channel_17                              ((uint8_t)0x11)    /*!<  ADC Channel 17 */
+#define ADC_Channel_18                              ((uint8_t)0x12)    /*!<  ADC Channel 18 */
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_18)
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1)  || \
+                                 ((CHANNEL) == ADC_Channel_2)  || \
+                                 ((CHANNEL) == ADC_Channel_3)  || \
+                                 ((CHANNEL) == ADC_Channel_4)  || \
+                                 ((CHANNEL) == ADC_Channel_5)  || \
+                                 ((CHANNEL) == ADC_Channel_6)  || \
+                                 ((CHANNEL) == ADC_Channel_7)  || \
+                                 ((CHANNEL) == ADC_Channel_8)  || \
+                                 ((CHANNEL) == ADC_Channel_9)  || \
+                                 ((CHANNEL) == ADC_Channel_10) || \
+                                 ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || \
+                                 ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || \
+                                 ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || \
+                                 ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18))
+#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1)  || \
+                                     ((CHANNEL) == ADC_Channel_2)  || \
+                                     ((CHANNEL) == ADC_Channel_3)  || \
+                                     ((CHANNEL) == ADC_Channel_4)  || \
+                                     ((CHANNEL) == ADC_Channel_5)  || \
+                                     ((CHANNEL) == ADC_Channel_6)  || \
+                                     ((CHANNEL) == ADC_Channel_7)  || \
+                                     ((CHANNEL) == ADC_Channel_8)  || \
+                                     ((CHANNEL) == ADC_Channel_9)  || \
+                                     ((CHANNEL) == ADC_Channel_10) || \
+                                     ((CHANNEL) == ADC_Channel_11) || \
+                                     ((CHANNEL) == ADC_Channel_12) || \
+                                     ((CHANNEL) == ADC_Channel_13) || \
+                                     ((CHANNEL) == ADC_Channel_14))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_mode 
+  * @{
+  */    
+#define ADC_Mode_Independent                  ((uint32_t)0x00000000) /*!<  ADC independent mode */
+#define ADC_Mode_CombRegSimulInjSimul         ((uint32_t)0x00000001) /*!<  ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
+#define ADC_Mode_CombRegSimulAltTrig          ((uint32_t)0x00000002) /*!<  ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
+#define ADC_Mode_InjSimul                     ((uint32_t)0x00000005) /*!<  ADC multi ADC mode: Injected simultaneous mode */
+#define ADC_Mode_RegSimul                     ((uint32_t)0x00000006) /*!<  ADC multi ADC mode: Regular simultaneous mode */
+#define ADC_Mode_Interleave                   ((uint32_t)0x00000007) /*!<  ADC multi ADC mode: Interleave mode */
+#define ADC_Mode_AltTrig                      ((uint32_t)0x00000009) /*!<  ADC multi ADC mode: Alternate Trigger mode */
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
+                           ((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
+                           ((MODE) == ADC_Mode_InjSimul) || \
+                           ((MODE) == ADC_Mode_RegSimul) || \
+                           ((MODE) == ADC_Mode_Interleave) || \
+                           ((MODE) == ADC_Mode_AltTrig))
+                                     
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Clock 
+  * @{
+  */ 
+#define ADC_Clock_AsynClkMode                  ((uint32_t)0x00000000)   /*!< ADC Asynchronous clock mode */
+#define ADC_Clock_SynClkModeDiv1               ((uint32_t)0x00010000)   /*!< Synchronous clock mode divided by 1 */
+#define ADC_Clock_SynClkModeDiv2               ((uint32_t)0x00020000)   /*!<  Synchronous clock mode divided by 2 */
+#define ADC_Clock_SynClkModeDiv4               ((uint32_t)0x00030000)   /*!<  Synchronous clock mode divided by 4 */
+#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
+				((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
+				((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
+				((CLOCK) == ADC_Clock_SynClkModeDiv4))
+/**
+  * @}
+  */
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
+  * @{
+  */ 
+#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /*!<  DMA mode disabled */
+#define ADC_DMAAccessMode_1             ((uint32_t)0x00008000)     /*!<  DMA mode enabled for 12 and 10-bit resolution (6 bit) */
+#define ADC_DMAAccessMode_2             ((uint32_t)0x0000C000)     /*!<  DMA mode enabled for 8 and 6-bit resolution (8bit) */
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+                                      ((MODE) == ADC_DMAAccessMode_1) || \
+                                      ((MODE) == ADC_DMAAccessMode_2))
+                                     
+/**
+  * @}
+  */
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)   /*!<  ADC sampling time 1.5 cycle */
+#define ADC_SampleTime_2Cycles5                    ((uint8_t)0x01)   /*!<  ADC sampling time 2.5 cycles */
+#define ADC_SampleTime_4Cycles5                    ((uint8_t)0x02)   /*!<  ADC sampling time 4.5 cycles */
+#define ADC_SampleTime_7Cycles5                    ((uint8_t)0x03)   /*!<  ADC sampling time 7.5 cycles */
+#define ADC_SampleTime_19Cycles5                   ((uint8_t)0x04)   /*!<  ADC sampling time 19.5 cycles */
+#define ADC_SampleTime_61Cycles5                   ((uint8_t)0x05)   /*!<  ADC sampling time 61.5 cycles */
+#define ADC_SampleTime_181Cycles5                  ((uint8_t)0x06)   /*!<  ADC sampling time 181.5 cycles */
+#define ADC_SampleTime_601Cycles5                  ((uint8_t)0x07)   /*!<  ADC sampling time 601.5 cycles */
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_2Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_4Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_19Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_61Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_181Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_601Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_Channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ADC_Channel_1        /*!<  ADC Injected channel 1 */
+#define ADC_InjectedChannel_2                       ADC_Channel_2        /*!<  ADC Injected channel 2 */
+#define ADC_InjectedChannel_3                       ADC_Channel_3        /*!<  ADC Injected channel 3 */
+#define ADC_InjectedChannel_4                       ADC_Channel_4        /*!<  ADC Injected channel 4 */
+#define ADC_InjectedChannel_5                       ADC_Channel_5        /*!<  ADC Injected channel 5 */
+#define ADC_InjectedChannel_6                       ADC_Channel_6        /*!<  ADC Injected channel 6 */
+#define ADC_InjectedChannel_7                       ADC_Channel_7        /*!<  ADC Injected channel 7 */
+#define ADC_InjectedChannel_8                       ADC_Channel_8        /*!<  ADC Injected channel 8 */
+#define ADC_InjectedChannel_9                       ADC_Channel_9        /*!<  ADC Injected channel 9 */
+#define ADC_InjectedChannel_10                      ADC_Channel_10       /*!<  ADC Injected channel 10 */
+#define ADC_InjectedChannel_11                      ADC_Channel_11       /*!<  ADC Injected channel 11 */
+#define ADC_InjectedChannel_12                      ADC_Channel_12       /*!<  ADC Injected channel 12 */
+#define ADC_InjectedChannel_13                      ADC_Channel_13       /*!<  ADC Injected channel 13 */
+#define ADC_InjectedChannel_14                      ADC_Channel_14       /*!<  ADC Injected channel 14 */
+#define ADC_InjectedChannel_15                      ADC_Channel_15       /*!<  ADC Injected channel 15 */
+#define ADC_InjectedChannel_16                      ADC_Channel_16       /*!<  ADC Injected channel 16 */
+#define ADC_InjectedChannel_17                      ADC_Channel_17       /*!<  ADC Injected channel 17 */
+#define ADC_InjectedChannel_18                      ADC_Channel_18       /*!<  ADC Injected channel 18 */
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_5) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_6) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_7) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_8) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_9) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_10) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_11) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_12) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_13) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_14) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_15) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_16) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_17) ||\
+                                          ((CHANNEL) == ADC_InjectedChannel_18))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_Sequence_selection 
+  * @{
+  */
+
+#define ADC_InjectedSequence_1                       ADC_Channel_1        /*!<  ADC Injected sequence 1 */
+#define ADC_InjectedSequence_2                       ADC_Channel_2        /*!<  ADC Injected sequence 2 */
+#define ADC_InjectedSequence_3                       ADC_Channel_3        /*!<  ADC Injected sequence 3 */
+#define ADC_InjectedSequence_4                       ADC_Channel_4        /*!<  ADC Injected sequence 4 */
+#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
+                                            ((SEQUENCE) == ADC_InjectedSequence_2) || \
+                                            ((SEQUENCE) == ADC_InjectedSequence_3) || \
+                                            ((SEQUENCE) == ADC_InjectedSequence_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00C00000)    /*!<  ADC Analog watchdog single regular mode */
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x01400000)    /*!<  ADC Analog watchdog single injected mode */
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x01C00000)    /*!<  ADC Analog watchdog single regular or injected mode */
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)    /*!<  ADC Analog watchdog all regular mode */
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x01000000)    /*!<  ADC Analog watchdog all injected mode */
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x01800000)    /*!<  ADC Analog watchdog all regular and all injected mode */
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)    /*!<  ADC Analog watchdog off */
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Calibration_Mode_definition 
+  * @{
+  */
+#define ADC_CalibrationMode_Single         ((uint32_t)0x00000000)   /*!<  ADC Calibration for single ended channel */
+#define ADC_CalibrationMode_Differential   ((uint32_t)0x40000000)   /*!<  ADC Calibration for differential channel */
+
+#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_DMA_Mode_definition 
+  * @{
+  */
+#define ADC_DMAMode_OneShot	   ((uint32_t)0x00000000)   /*!<  ADC DMA Oneshot mode */
+#define ADC_DMAMode_Circular   ((uint32_t)0x00000002)   /*!<  ADC DMA circular mode */
+
+#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_RDY           ((uint16_t)0x0001)  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP         ((uint16_t)0x0002)  /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_EOC           ((uint16_t)0x0004)  /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOS           ((uint16_t)0x0008)  /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_OVR           ((uint16_t)0x0010)  /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC          ((uint16_t)0x0020)  /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_JEOS          ((uint16_t)0x0040)  /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IT_AWD1          ((uint16_t)0x0080)  /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IT_AWD2          ((uint16_t)0x0100)  /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IT_AWD3          ((uint16_t)0x0200)  /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IT_JQOVF         ((uint16_t)0x0400)  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
+                           ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
+                           ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
+                           ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
+                           ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
+                           ((IT) == ADC_IT_JQOVF))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+  
+#define ADC_FLAG_RDY           ((uint16_t)0x0001)  /*!< ADC Ready (ADRDY) flag */
+#define ADC_FLAG_EOSMP         ((uint16_t)0x0002)  /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ((uint16_t)0x0004)  /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ((uint16_t)0x0008)  /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ((uint16_t)0x0010)  /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC          ((uint16_t)0x0020)  /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS          ((uint16_t)0x0040)  /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1          ((uint16_t)0x0080)  /*!< ADC Analog watchdog 1 flag */
+#define ADC_FLAG_AWD2          ((uint16_t)0x0100)  /*!< ADC Analog watchdog 2 flag */
+#define ADC_FLAG_AWD3          ((uint16_t)0x0200)  /*!< ADC Analog watchdog 3 flag */
+#define ADC_FLAG_JQOVF         ((uint16_t)0x0400)  /*!< ADC Injected Context Queue Overflow flag */
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
+                               ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
+                               ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
+                               ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
+                               ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
+                               ((FLAG) == ADC_FLAG_JQOVF))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Common_flags_definition 
+  * @{
+  */
+  
+#define ADC_FLAG_MSTRDY           ((uint32_t)0x00000001)  /*!< ADC Master Ready (ADRDY) flag */
+#define ADC_FLAG_MSTEOSMP         ((uint32_t)0x00000002)  /*!< ADC Master End of Sampling flag */
+#define ADC_FLAG_MSTEOC           ((uint32_t)0x00000004)  /*!< ADC Master End of Regular Conversion flag */
+#define ADC_FLAG_MSTEOS           ((uint32_t)0x00000008)  /*!< ADC Master End of Regular sequence of Conversions flag */
+#define ADC_FLAG_MSTOVR           ((uint32_t)0x00000010)  /*!< ADC Master overrun flag */
+#define ADC_FLAG_MSTJEOC          ((uint32_t)0x00000020)  /*!< ADC Master End of Injected Conversion flag */
+#define ADC_FLAG_MSTJEOS          ((uint32_t)0x00000040)  /*!< ADC Master End of Injected sequence of Conversions flag */
+#define ADC_FLAG_MSTAWD1          ((uint32_t)0x00000080)  /*!< ADC Master Analog watchdog 1 flag */
+#define ADC_FLAG_MSTAWD2          ((uint32_t)0x00000100)  /*!< ADC Master Analog watchdog 2 flag */
+#define ADC_FLAG_MSTAWD3          ((uint32_t)0x00000200)  /*!< ADC Master Analog watchdog 3 flag */
+#define ADC_FLAG_MSTJQOVF         ((uint32_t)0x00000400)  /*!< ADC Master Injected Context Queue Overflow flag */
+
+#define ADC_FLAG_SLVRDY           ((uint32_t)0x00010000)  /*!< ADC Slave Ready (ADRDY) flag */
+#define ADC_FLAG_SLVEOSMP         ((uint32_t)0x00020000)  /*!< ADC Slave End of Sampling flag */
+#define ADC_FLAG_SLVEOC           ((uint32_t)0x00040000)  /*!< ADC Slave End of Regular Conversion flag */
+#define ADC_FLAG_SLVEOS           ((uint32_t)0x00080000)  /*!< ADC Slave End of Regular sequence of Conversions flag */
+#define ADC_FLAG_SLVOVR           ((uint32_t)0x00100000)  /*!< ADC Slave overrun flag */
+#define ADC_FLAG_SLVJEOC          ((uint32_t)0x00200000)  /*!< ADC Slave End of Injected Conversion flag */
+#define ADC_FLAG_SLVJEOS          ((uint32_t)0x00400000)  /*!< ADC Slave End of Injected sequence of Conversions flag */
+#define ADC_FLAG_SLVAWD1          ((uint32_t)0x00800000)  /*!< ADC Slave Analog watchdog 1 flag */
+#define ADC_FLAG_SLVAWD2          ((uint32_t)0x01000000)  /*!< ADC Slave Analog watchdog 2 flag */
+#define ADC_FLAG_SLVAWD3          ((uint32_t)0x02000000)  /*!< ADC Slave Analog watchdog 3 flag */
+#define ADC_FLAG_SLVJQOVF         ((uint32_t)0x04000000)  /*!< ADC Slave Injected Context Queue Overflow flag */
+
+#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
+#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
+                                     ((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
+                                     ((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
+                                     ((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
+                                     ((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
+                                     ((FLAG) == ADC_FLAG_MSTJQOVF) || \
+                                     ((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
+                                     ((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
+                                     ((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
+                                     ((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
+                                     ((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
+                                     ((FLAG) == ADC_FLAG_SLVJQOVF))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)  
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)   
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) 
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))  
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_two_sampling_delay_number 
+  * @{
+  */
+#define IS_ADC_TWOSAMPLING_DELAY(DELAY)	(((DELAY) <= 0xF))
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);	
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);	
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); 
+void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct); 
+void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
+void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);    
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+void ADC_StartCalibration(ADC_TypeDef* ADCx); 
+uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
+void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
+void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode); 
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_DisableCmd(ADC_TypeDef* ADCx); 
+FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx); 
+void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);  
+void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
+void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); 
+void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);	
+void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);	
+void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);	
+void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); 
+void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);   
+void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); 
+
+/* Temperature Sensor, Vrefint and Vbat management function */
+void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);  
+void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+
+/* Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength); 
+void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge); 
+ 
+void ADC_StartConversion(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
+void ADC_StopConversion(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);	
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
+
+void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);  
+void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);  
+void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);  
+void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);  
+
+void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);  
+void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);  
+void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);  
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);  
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
+void ADC_StartInjectedConversion(ADC_TypeDef* ADCx); 
+FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx); 
+void ADC_StopInjectedConversion(ADC_TypeDef* ADCx); 
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);  
+
+/* ADC Dual Modes Configuration functions *************************************/
+FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); 
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); 
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); 
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);  
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);  
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h
new file mode 100644
index 0000000..ddb4912
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_comp.h
@@ -0,0 +1,400 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_comp.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the COMP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_COMP_H
+#define __STM32F30x_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+
+  uint32_t COMP_InvertingInput;     /*!< Selects the inverting input of the comparator.
+                                          This parameter can be a value of @ref COMP_InvertingInput */
+
+  uint32_t COMP_NonInvertingInput;  /*!< Selects the non inverting input of the comparator.
+                                         This parameter can be a value of @ref COMP_NonInvertingInput */
+
+  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
+                                          This parameter can be a value of @ref COMP_Output */
+
+  uint32_t COMP_BlankingSrce;      /*!< Selects the output blanking source of the comparator.
+                                          This parameter can be a value of @ref COMP_BlankingSrce */
+
+  uint32_t COMP_OutputPol;           /*!< Selects the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputPoloarity */
+
+  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
+                                          This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
+                                         and allows to adjust the speed/consumption.
+                                          This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP_Selection_COMP1                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP_Selection_COMP2                    ((uint32_t)0x00000004) /*!< COMP2 Selection */
+#define COMP_Selection_COMP3                    ((uint32_t)0x00000008) /*!< COMP3 Selection */
+#define COMP_Selection_COMP4                    ((uint32_t)0x0000000C) /*!< COMP4 Selection */
+#define COMP_Selection_COMP5                    ((uint32_t)0x00000010) /*!< COMP5 Selection */
+#define COMP_Selection_COMP6                    ((uint32_t)0x00000014) /*!< COMP6 Selection */
+#define COMP_Selection_COMP7                    ((uint32_t)0x00000018) /*!< COMP7 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+                                    ((PERIPH) == COMP_Selection_COMP2) || \
+                                    ((PERIPH) == COMP_Selection_COMP3) || \
+                                    ((PERIPH) == COMP_Selection_COMP4) || \
+                                    ((PERIPH) == COMP_Selection_COMP5) || \
+                                    ((PERIPH) == COMP_Selection_COMP6) || \
+                                    ((PERIPH) == COMP_Selection_COMP7))
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_1_2VREFINT          COMP_CSR_COMPxINSEL_0  /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_3_4VREFINT          COMP_CSR_COMPxINSEL_1  /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1                COMP_CSR_COMPxINSEL_2  /*!< DAC1_OUT (PA4) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC2                ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input */
+#define COMP_InvertingInput_IO1                 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3, 
+                                                                            PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
+                                                                            PC0 for COMP7) connected to comparator inverting input */
+
+#define COMP_InvertingInput_IO2                 COMP_CSR_COMPxINSEL    /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
+                                                                            PB15 for COMP6) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_VREFINT)    || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1)       || \
+                                        ((INPUT) == COMP_InvertingInput_DAC2)       || \
+                                        ((INPUT) == COMP_InvertingInput_IO1)        || \
+                                        ((INPUT) == COMP_InvertingInput_IO2))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_NonInvertingInput
+  * @{
+  */
+
+#define COMP_NonInvertingInput_IO1                 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, 
+                                                                               PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+                                                                               PA0 for COMP7) connected to comparator non inverting input */
+
+#define COMP_NonInvertingInput_IO2                 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
+                                                                               PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
+
+#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
+                                           ((INPUT) == COMP_NonInvertingInput_IO2))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Output
+  * @{
+  */
+
+#define COMP_Output_None                  ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
+
+/* Output Redirection common for all comparators COMP1...COMP7 */
+#define COMP_Output_TIM1BKIN              COMP_CSR_COMPxOUTSEL_0   /*!< COMP output connected to TIM1 Break Input (BKIN) */
+#define COMP_Output_TIM1BKIN2             ((uint32_t)0x00000800)   /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_Output_TIM8BKIN              ((uint32_t)0x00000C00)   /*!< COMP output connected to TIM8 Break Input (BKIN) */
+#define COMP_Output_TIM8BKIN2             ((uint32_t)0x00001000)   /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_Output_TIM1BKIN2_TIM8BKIN2   ((uint32_t)0x00001400)   /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+
+/* Output Redirection common for COMP1 and COMP2 */
+#define COMP_Output_TIM1OCREFCLR          ((uint32_t)0x00001800)   /*!< COMP output connected to TIM1 OCREF Clear */
+#define COMP_Output_TIM1IC1               ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM1 Input Capture 1 */
+#define COMP_Output_TIM2IC4               ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TIM2OCREFCLR          ((uint32_t)0x00002400)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM3IC1               ((uint32_t)0x00002800)   /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TIM3OCREFCLR          ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM3 OCREF Clear */
+
+/* Output Redirection specific to COMP3 */
+#define COMP_Output_TIM4IC1               ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM4 Input Capture 1 */
+#define COMP_Output_TIM3IC2               ((uint32_t)0x00002000)   /*!< COMP output connected to TIM3 Input Capture 2 */
+#define COMP_Output_TIM15IC1              ((uint32_t)0x00002800)   /*!< COMP output connected to TIM15 Input Capture 1 */
+#define COMP_Output_TIM15BKIN             ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM15 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP4 */
+#define COMP_Output_TIM3IC3               ((uint32_t)0x00001800)   /*!< COMP output connected to TIM3 Input Capture 3 */
+#define COMP_Output_TIM8OCREFCLR          ((uint32_t)0x00001C00)   /*!< COMP output connected to TIM8 OCREF Clear */
+#define COMP_Output_TIM15IC2              ((uint32_t)0x00002000)   /*!< COMP output connected to TIM15 Input Capture 2 */
+#define COMP_Output_TIM4IC2               ((uint32_t)0x00002400)   /*!< COMP output connected to TIM4 Input Capture 2 */
+#define COMP_Output_TIM15OCREFCLR         ((uint32_t)0x00002800)   /*!< COMP output connected to TIM15 OCREF Clear */
+
+/* Output Redirection specific to COMP5 */
+#define COMP_Output_TIM2IC1               ((uint32_t)0x00001800)   /*!< COMP output connected to TIM2 Input Capture 1 */
+#define COMP_Output_TIM17IC1              ((uint32_t)0x00002000)   /*!< COMP output connected to TIM17 Input Capture 1 */
+#define COMP_Output_TIM4IC3               ((uint32_t)0x00002400)   /*!< COMP output connected to TIM4 Input Capture 3 */
+#define COMP_Output_TIM16BKIN             ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+/* Output Redirection specific to COMP6 */
+#define COMP_Output_TIM2IC2               ((uint32_t)0x00001800)   /*!< COMP output connected to TIM2 Input Capture 2 */
+#define COMP_Output_COMP6TIM2OCREFCLR     ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM16OCREFCLR         ((uint32_t)0x00002400)   /*!< COMP output connected to TIM16 OCREF Clear */
+#define COMP_Output_TIM16IC1              ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 Input Capture 1 */
+#define COMP_Output_TIM4IC4               ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM4 Input Capture 4 */
+
+/* Output Redirection specific to COMP7 */
+#define COMP_Output_TIM2IC3               ((uint32_t)0x00002000)   /*!< COMP output connected to TIM2 Input Capture 3 */
+#define COMP_Output_TIM1IC2               ((uint32_t)0x00002400)   /*!< COMP output connected to TIM1 Input Capture 2 */
+#define COMP_Output_TIM17OCREFCLR         ((uint32_t)0x00002800)   /*!< COMP output connected to TIM16 OCREF Clear */
+#define COMP_Output_TIM17BKIN             ((uint32_t)0x00002C00)   /*!< COMP output connected to TIM16 Break Input (BKIN) */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)                || \
+                                ((OUTPUT) == COMP_Output_TIM1BKIN)            || \
+                                ((OUTPUT) == COMP_Output_TIM1IC1)             || \
+                                ((OUTPUT) == COMP_Output_TIM1OCREFCLR)        || \
+                                ((OUTPUT) == COMP_Output_TIM2IC4)             || \
+                                ((OUTPUT) == COMP_Output_TIM2OCREFCLR)        || \
+                                ((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR)   || \
+                                ((OUTPUT) == COMP_Output_TIM3IC1)             || \
+                                ((OUTPUT) == COMP_Output_TIM3OCREFCLR)        || \
+                                ((OUTPUT) == COMP_Output_TIM8BKIN)            || \
+                                ((OUTPUT) == COMP_Output_TIM1BKIN2)           || \
+                                ((OUTPUT) == COMP_Output_TIM8BKIN2)           || \
+                                ((OUTPUT) == COMP_Output_TIM2OCREFCLR)        || \
+                                ((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
+                                ((OUTPUT) == COMP_Output_TIM3IC2)             || \
+                                ((OUTPUT) == COMP_Output_TIM4IC1)             || \
+                                ((OUTPUT) == COMP_Output_TIM15IC1)            || \
+                                ((OUTPUT) == COMP_Output_TIM15BKIN)           || \
+                                ((OUTPUT) == COMP_Output_TIM8OCREFCLR)        || \
+                                ((OUTPUT) == COMP_Output_TIM3IC3)             || \
+                                ((OUTPUT) == COMP_Output_TIM4IC1)             || \
+                                ((OUTPUT) == COMP_Output_TIM15IC1)            || \
+                                ((OUTPUT) == COMP_Output_TIM2IC1)             || \
+                                ((OUTPUT) == COMP_Output_TIM4IC3)             || \
+                                ((OUTPUT) == COMP_Output_TIM16BKIN)           || \
+                                ((OUTPUT) == COMP_Output_TIM17IC1)            || \
+                                ((OUTPUT) == COMP_Output_TIM2IC2)             || \
+                                ((OUTPUT) == COMP_Output_TIM16IC1)            || \
+                                ((OUTPUT) == COMP_Output_TIM4IC4)             || \
+                                ((OUTPUT) == COMP_Output_TIM16OCREFCLR)       || \
+                                ((OUTPUT) == COMP_Output_TIM2IC3)             || \
+                                ((OUTPUT) == COMP_Output_TIM1IC2)             || \
+                                ((OUTPUT) == COMP_Output_TIM17BKIN)           || \
+                                ((OUTPUT) == COMP_Output_TIM17OCREFCLR))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_BlankingSrce
+  * @{
+  */
+
+/* No blanking source can be selected for all comparators */
+#define COMP_BlankingSrce_None                   ((uint32_t)0x00000000)    /*!< No blanking source */
+
+/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_BlankingSrce_TIM1OC5                COMP_CSR_COMPxBLANKING_0  /*!< TIM1 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BlankingSrce_TIM2OC3                COMP_CSR_COMPxBLANKING_1  /*!< TIM2 OC5 selected as blanking source for compartor */
+
+/* Blanking source common for COMP1, COMP2 and COMP5 */
+#define COMP_BlankingSrce_TIM3OC3                ((uint32_t)0x000C0000)    /*!< TIM2 OC3 selected as blanking source for compartor */
+
+/* Blanking source common for COMP3 and COMP6 */
+#define COMP_BlankingSrce_TIM2OC4                ((uint32_t)0x000C0000)  /*!< TIM2 OC4 selected as blanking source for compartor */
+
+/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_BlankingSrce_TIM8OC5                COMP_CSR_COMPxBLANKING_1  /*!< TIM8 OC5 selected as blanking source for compartor */
+
+/* Blanking source for COMP4 */
+#define COMP_BlankingSrce_TIM3OC4                COMP_CSR_COMPxBLANKING_0  /*!< TIM3 OC4 selected as blanking source for compartor */
+#define COMP_BlankingSrce_TIM15OC1               ((uint32_t)0x000C0000)    /*!< TIM15 OC1 selected as blanking source for compartor */
+
+/* Blanking source common for COMP6 and COMP7 */
+#define COMP_BlankingSrce_TIM15OC2               COMP_CSR_COMPxBLANKING_2    /*!< TIM15 OC2 selected as blanking source for compartor */
+
+#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None)     || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM1OC5)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM2OC3)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM3OC3)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM2OC4)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM8OC5)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM3OC4)  || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
+                                         ((SOURCE) == COMP_BlankingSrce_TIM15OC2))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputPoloarity
+  * @{
+  */
+#define COMP_OutputPol_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutputPol_Inverted             COMP_CSR_COMPxPOL       /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted)  || \
+                                 ((POL) == COMP_OutputPol_Inverted))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Hysteresis
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the hysteresis level */
+#define COMP_Hysteresis_No                         0x00000000           /*!< No hysteresis */
+#define COMP_Hysteresis_Low                        COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium                     COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High                       COMP_CSR_COMPxHYST   /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No)     || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Low)    || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Mode
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the power consumption values */
+#define COMP_Mode_HighSpeed                     0x00000000            /*!< High Speed */
+#define COMP_Mode_MediumSpeed                   COMP_CSR_COMPxMODE_0  /*!< Medium Speed */
+#define COMP_Mode_LowPower                      COMP_CSR_COMPxMODE_1  /*!< Low power mode */
+#define COMP_Mode_UltraLowPower                 COMP_CSR_COMPxMODE    /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_UltraLowPower) || \
+                               ((MODE) == COMP_Mode_LowPower)      || \
+                               ((MODE) == COMP_Mode_MediumSpeed)   || \
+                               ((MODE) == COMP_Mode_HighSpeed))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel
+  * @{
+  */ 
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High                   COMP_CSR_COMPxOUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_WindowMode
+  * @{
+  */
+#define IS_COMP_WINDOW(WINDOW)  (((WINDOW) == COMP_Selection_COMP2) || \
+                                 ((WINDOW) == COMP_Selection_COMP4) || \
+                                 ((WINDOW) == COMP_Selection_COMP6))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(uint32_t COMP_Selection);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h
new file mode 100644
index 0000000..3f317e7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_crc.h
@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_crc.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_CRC_H
+#define __STM32F30x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_ReverseInputData
+  * @{
+  */
+#define CRC_ReverseInputData_No             ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
+#define CRC_ReverseInputData_8bits          CRC_CR_REV_IN_0        /*!< Reverse operation of Input Data on 8 bits */
+#define CRC_ReverseInputData_16bits         CRC_CR_REV_IN_1        /*!< Reverse operation of Input Data on 16 bits */
+#define CRC_ReverseInputData_32bits         CRC_CR_REV_IN          /*!< Reverse operation of Input Data on 32 bits */
+
+#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No)     || \
+                                         ((DATA) == CRC_ReverseInputData_8bits)  || \
+                                         ((DATA) == CRC_ReverseInputData_16bits) || \
+                                         ((DATA) == CRC_ReverseInputData_32bits))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_PolynomialSize
+  * @{
+  */
+#define CRC_PolSize_7                       CRC_CR_POLSIZE        /*!< 7-bit polynomial for CRC calculation */
+#define CRC_PolSize_8                       CRC_CR_POLSIZE_1      /*!< 8-bit polynomial for CRC calculation */
+#define CRC_PolSize_16                      CRC_CR_POLSIZE_0      /*!< 16-bit polynomial for CRC calculation */
+#define CRC_PolSize_32                      ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
+
+#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7)  || \
+                               ((SIZE) == CRC_PolSize_8)  || \
+                               ((SIZE) == CRC_PolSize_16) || \
+                               ((SIZE) == CRC_PolSize_32))
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Configuration of the CRC computation unit **********************************/
+void CRC_DeInit(void);
+void CRC_ResetDR(void);
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); 
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
+void CRC_ReverseOutputDataCmd(FunctionalState NewState);
+void CRC_SetInitRegister(uint32_t CRC_InitValue); 
+void CRC_SetPolynomial(uint32_t CRC_Pol);
+
+/* CRC computation ************************************************************/
+uint32_t CRC_CalcCRC(uint32_t CRC_Data);
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+
+/* Independent register (IDR) access (write/read) *****************************/
+void CRC_SetIDRegister(uint8_t CRC_IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_CRC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h
new file mode 100644
index 0000000..0626be1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dac.h
@@ -0,0 +1,306 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_dac.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DAC_H
+#define __STM32F30x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#define DAC_CR_DMAUDRIE                  ((uint32_t)0x00002000)        /*!< DAC channel DMA underrun interrupt enable */
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None)     || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T3_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO)  || \
+                                 ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9)  || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None)  || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */   
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_DAC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h
new file mode 100644
index 0000000..44a5882
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_dbgmcu.h
@@ -0,0 +1,108 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DBGMCU_H
+#define __STM32F30x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */ 
+#define DBGMCU_SLEEP                          ((uint32_t)0x00000001)
+#define DBGMCU_STOP                           ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY                        ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
+
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM15_STOP            ((uint32_t)0x00000004)
+#define DBGMCU_TIM16_STOP            ((uint32_t)0x00000008)
+#define DBGMCU_TIM17_STOP            ((uint32_t)0x00000010)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_DBGMCU_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h
new file mode 100644
index 0000000..b9a746f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_gpio.h
@@ -0,0 +1,394 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_gpio.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the GPIO 
+  *          firmware library. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_GPIO_H
+#define __STM32F30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+ 
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF))  
+                                    
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                     ((PERIPH) == GPIOB) || \
+                                     ((PERIPH) == GPIOD))  
+/** @defgroup Configuration_Mode_enumeration 
+  * @{
+  */ 
+typedef enum
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+  * @}
+  */
+  
+/** @defgroup Output_type_enumeration
+  * @{
+  */ 
+typedef enum
+{ 
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+  * @}
+  */
+
+/** @defgroup Output_Maximum_frequency_enumeration 
+  * @{
+  */ 
+typedef enum
+{ 
+  GPIO_Speed_Level_1  = 0x01, /*!< Fast Speed     */
+  GPIO_Speed_Level_2  = 0x02, /*!< Meduim Speed   */
+  GPIO_Speed_Level_3  = 0x03  /*!< High Speed     */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+                              ((SPEED) == GPIO_Speed_Level_3))
+/**
+  * @}
+  */  
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration 
+  * @{
+  */ 
+typedef enum
+{
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+/**
+  * @}
+  */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+  * @{
+  */
+typedef enum
+{ 
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+  * @}
+  */
+
+/** 
+  * @brief  GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+                                       
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef   */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef  */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef  */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef   */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected    */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected    */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected    */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected    */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected    */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected    */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected    */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected    */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected    */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected    */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected   */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected   */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected   */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected   */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected   */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected   */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternate_function_selection_define 
+  * @{
+  */
+
+/** 
+  * @brief  AF 0 selection
+  */ 
+#define GPIO_AF_0            ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,  
+                                                MCO, NJTRST, TRACED, TRACECK */
+/** 
+  * @brief  AF 1 selection
+  */ 
+#define GPIO_AF_1            ((uint8_t)0x01) /*  OUT, TIM2, TIM15, TIM16, TIM17 */
+
+/** 
+  * @brief  AF 2 selection
+  */ 
+#define GPIO_AF_2            ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15 */
+
+/** 
+  * @brief  AF 3 selection
+  */ 
+#define GPIO_AF_3            ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch */
+
+/** 
+  * @brief  AF 4 selection
+  */ 
+#define GPIO_AF_4            ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
+
+/** 
+  * @brief  AF 5 selection
+  */ 
+#define GPIO_AF_5            ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
+
+/** 
+  * @brief  AF 6 selection
+  */ 
+#define GPIO_AF_6            ((uint8_t)0x06) /*  IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
+
+/** 
+  * @brief  AF 7 selection
+  */ 
+#define GPIO_AF_7            ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, 
+                                                USART1, USART2, USART3 */
+
+/** 
+  * @brief  AF 8 selection
+  */ 
+#define GPIO_AF_8            ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, 
+                                                COMP5_OUT, COMP6_OUT */
+
+/** 
+  * @brief  AF 9 selection
+  */ 
+#define GPIO_AF_9            ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
+
+/** 
+  * @brief  AF 10 selection
+  */ 
+#define GPIO_AF_10            ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
+
+/** 
+  * @brief  AF 11 selection
+  */ 
+#define GPIO_AF_11            ((uint8_t)0x0B) /* TIM1, TIM8 */
+
+/** 
+   * @brief  AF 12 selection
+   */ 
+#define GPIO_AF_12            ((uint8_t)0x0E) /* TIM1 */
+
+/** 
+  * @brief  AF 14 selection
+  */ 
+#define GPIO_AF_14            ((uint8_t)0x0E) /* USBDM, USBDP */
+
+/** 
+  * @brief  AF 15 selection
+  */ 
+#define GPIO_AF_15            ((uint8_t)0x0F) /* OUT */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
+                          ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
+                          ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
+                          ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
+                          ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
+                          ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
+                          ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Speed_Legacy 
+  * @{
+  */
+
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1   /*!< Fast Speed:10MHz   */
+#define GPIO_Speed_2MHz  GPIO_Speed_Level_2   /*!< Medium Speed:2MHz  */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3   /*!< High Speed:50MHz   */
+
+/**
+  * @}
+  */
+ 
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_GPIO_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h
new file mode 100644
index 0000000..66dffe7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_iwdg.h
@@ -0,0 +1,153 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_IWDG_H
+#define __STM32F30X_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IWDG_FLAG_WVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)  || \
+                            ((FLAG) == IWDG_FLAG_WVU))
+/**
+  * @}
+  */
+  
+/** @defgroup IWDG_Reload_Value
+  * @{
+  */
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_CounterWindow_Value
+  * @{
+  */
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30X_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h
new file mode 100644
index 0000000..ea77dc7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_misc.h
@@ -0,0 +1,204 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_misc.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_MISC_H
+#define __STM32F30x_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type (For 
+                                                   the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f30x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15.
+                                                   A lower priority value indicates a higher priority */
+                                                   
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value 
+                                                   between 0 and 15.
+                                                   A lower priority value indicates a higher priority */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+
+/**  
+  *
+@verbatim   
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endverbatim
+*/
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h
new file mode 100644
index 0000000..e2ab108
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_rtc.h
@@ -0,0 +1,852 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_rtc.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_RTC_H
+#define __STM32F30x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x1FFF */ 
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef; 
+
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition        
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
+#define RTC_Weekday_Saturday           ((uint8_t)0x06)
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions 
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)  
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)  
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)  
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define RTC_Alarm_B                       ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA) || \
+                               ((OUTPUT) == RTC_Output_AlarmB) || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
+#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+                                 ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for 
+                                                      input tamper 1 */
+#define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for 
+                                                      input tamper 2 */
+#define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for 
+                                                      input tamper 3 */
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
+                                           ((BKP) == RTC_BKP_DR1) || \
+                                           ((BKP) == RTC_BKP_DR2) || \
+                                           ((BKP) == RTC_BKP_DR3) || \
+                                           ((BKP) == RTC_BKP_DR4) || \
+                                           ((BKP) == RTC_BKP_DR5) || \
+                                           ((BKP) == RTC_BKP_DR6) || \
+                                           ((BKP) == RTC_BKP_DR7) || \
+                                           ((BKP) == RTC_BKP_DR8) || \
+                                           ((BKP) == RTC_BKP_DR9) || \
+                                           ((BKP) == RTC_BKP_DR10) || \
+                                           ((BKP) == RTC_BKP_DR11) || \
+                                           ((BKP) == RTC_BKP_DR12) || \
+                                           ((BKP) == RTC_BKP_DR13) || \
+                                           ((BKP) == RTC_BKP_DR14) || \
+                                           ((BKP) == RTC_BKP_DR15))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F                   ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
+                                ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                                ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
+
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_WUT) || \
+                           ((IT) == RTC_IT_ALRB)  || ((IT) == RTC_IT_ALRA) || \
+                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
+                           ((IT) == RTC_IT_TAMP3))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the RTC configuration to the default reset state *****/ 
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/ 
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/ 
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/ 
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/ 
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/ 
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/ 
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions ********************************/
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/ 
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/ 
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/ 
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/ 
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/ 
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_RTC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h
new file mode 100644
index 0000000..7607e6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_spi.h
@@ -0,0 +1,606 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_spi.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_SPI_H
+#define __STM32F30x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_mode */
+  
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
+                                       ((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) || \
+                                    ((PERIPH) == I2S3ext))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_DataSize_4b                 ((uint16_t)0x0300)
+#define SPI_DataSize_5b                 ((uint16_t)0x0400)
+#define SPI_DataSize_6b                 ((uint16_t)0x0500)
+#define SPI_DataSize_7b                 ((uint16_t)0x0600)
+#define SPI_DataSize_8b                 ((uint16_t)0x0700)
+#define SPI_DataSize_9b                 ((uint16_t)0x0800)
+#define SPI_DataSize_10b                ((uint16_t)0x0900)
+#define SPI_DataSize_11b                ((uint16_t)0x0A00)
+#define SPI_DataSize_12b                ((uint16_t)0x0B00)
+#define SPI_DataSize_13b                ((uint16_t)0x0C00)
+#define SPI_DataSize_14b                ((uint16_t)0x0D00)
+#define SPI_DataSize_15b                ((uint16_t)0x0E00)
+#define SPI_DataSize_16b                ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+                                ((SIZE) == SPI_DataSize_5b) || \
+                                ((SIZE) == SPI_DataSize_6b) || \
+                                ((SIZE) == SPI_DataSize_7b) || \
+                                ((SIZE) == SPI_DataSize_8b) || \
+                                ((SIZE) == SPI_DataSize_9b) || \
+                                ((SIZE) == SPI_DataSize_10b) || \
+                                ((SIZE) == SPI_DataSize_11b) || \
+                                ((SIZE) == SPI_DataSize_12b) || \
+                                ((SIZE) == SPI_DataSize_13b) || \
+                                ((SIZE) == SPI_DataSize_14b) || \
+                                ((SIZE) == SPI_DataSize_15b) || \
+                                ((SIZE) == SPI_DataSize_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length
+  * @{
+  */
+
+#define SPI_CRCLength_8b                ((uint16_t)0x0000)
+#define SPI_CRCLength_16b               ((uint16_t)0x0800)
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+                                   ((LENGTH) == SPI_CRCLength_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+  
+/** @defgroup I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+
+/** @defgroup I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold 
+  * @{
+  */
+
+#define SPI_RxFIFOThreshold_HF          ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF          ((uint16_t)0x1000)
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+                                             ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_last_DMA_transfers
+  * @{
+  */
+
+#define SPI_LastDMATransfer_TxEvenRxEven   ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven    ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd    ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd     ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+  * @}
+  */
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_transmission_fifo_status_level 
+  * @{
+  */ 
+
+#define SPI_TransmissionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull    ((uint16_t)0x0800) 
+#define SPI_TransmissionFIFOStatus_HalfFull        ((uint16_t)0x1000) 
+#define SPI_TransmissionFIFOStatus_Full            ((uint16_t)0x1800)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_reception_fifo_status_level 
+  * @{
+  */ 
+#define SPI_ReceptionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull    ((uint16_t)0x0200) 
+#define SPI_ReceptionFIFOStatus_HalfFull        ((uint16_t)0x0400) 
+#define SPI_ReceptionFIFOStatus_Full            ((uint16_t)0x0600)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_FRE                ((uint16_t)0x0100)
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+                                   ((FLAG) == I2S_FLAG_UDR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the SPI configuration to the default reset state*******/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h
new file mode 100644
index 0000000..5337a68
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_syscfg.h
@@ -0,0 +1,301 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*!< Define to prevent recursive inclusion -----------------------------------*/
+#ifndef __STM32F30x_SYSCFG_H
+#define __STM32F30x_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ----------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash)        || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DMA_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_DMARemap_TIM17              SYSCFG_CFGR1_TIM17_DMA_RMP        /*!< Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16              SYSCFG_CFGR1_TIM16_DMA_RMP        /*!< Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_TIM6DAC1           SYSCFG_CFGR1_TIM6DAC1_DMA_RMP     /*!< Remap TIM6/DAC1 DMA requests from DMA2 channel3 to DMA1 channel3 */
+#define SYSCFG_DMARemap_TIM7DAC2           SYSCFG_CFGR1_TIM7DAC2_DMA_RMP     /*!< Remap TIM7/DAC2 DMA requests from DMA2 channel4 to DMA1 channel4 */
+#define SYSCFG_DMARemap_ADC2ADC4           SYSCFG_CFGR1_ADC24_DMA_RMP        /*!< Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4 */
+
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17)    || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM16)    || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM6DAC1) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM7DAC2) || \
+                                    ((REMAP) == SYSCFG_DMARemap_ADC2ADC4))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Trigger_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_TriggerRemap_DACTIM3              SYSCFG_CFGR1_DAC_TRIG_RMP     /*!< Remap DAC trigger to TIM3 */
+#define SYSCFG_TriggerRemap_TIM1TIM17            SYSCFG_CFGR1_TIM1_ITR3_RMP    /*!< Remap TIM1 ITR3 to TIM17 OC */
+
+#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3)  || \
+                                        ((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EncoderRemap_Config 
+  * @{
+  */ 
+#define SYSCFG_EncoderRemap_No              ((uint32_t)0x00000000)      /*!< No redirection */
+#define SYSCFG_EncoderRemap_TIM2            SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+#define SYSCFG_EncoderRemap_TIM3            SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+#define SYSCFG_EncoderRemap_TIM4            SYSCFG_CFGR1_ENCODER_MODE   /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
+
+#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No)    || \
+                                        ((REMAP) == SYSCFG_EncoderRemap_TIM2)  || \
+                                        ((REMAP) == SYSCFG_EncoderRemap_TIM3)  || \
+                                        ((REMAP) == SYSCFG_EncoderRemap_TIM4))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config 
+  * @{
+  */ 
+#define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1      SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SYSCFG_I2CFastModePlus_I2C2      SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB7)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB8)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupt_Config 
+  * @{
+  */ 
+#define SYSCFG_IT_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Inexact Interrupt enable (interrupt disabled by default) */
+#define SYSCFG_IT_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Input denormal Interrupt enable */
+#define SYSCFG_IT_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Overflow Interrupt enable */
+#define SYSCFG_IT_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Underflow Interrupt enable */
+#define SYSCFG_IT_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Divide-by-zero Interrupt enable */
+#define SYSCFG_IT_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Invalid operation Interrupt enable */
+
+#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Lock_Config
+  * @{
+  */
+#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK          /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_Break_SRAMParity              SYSCFG_CFGR2_SRAM_PARITY_LOCK  /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
+                                       ((CONFIG) == SYSCFG_Break_SRAMParity) || \
+                                       ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SRAMWRP_Config
+  * @{
+  */
+#define SYSCFG_SRAMWRP_Page0                 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_SRAMWRP_Page1                 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_SRAMWRP_Page2                 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_SRAMWRP_Page3                 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_SRAMWRP_Page4                 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_SRAMWRP_Page5                 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_SRAMWRP_Page6                 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_SRAMWRP_Page7                 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
+
+#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_flags_definition 
+  * @{
+  */
+
+#define SYSCFG_FLAG_PE               SYSCFG_CFGR2_SRAM_PE
+
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/ 
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
+void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
+void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+void SYSCFG_BypassParityCheckDisable(void);
+void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_SYSCFG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h
new file mode 100644
index 0000000..748d54e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_tim.h
@@ -0,0 +1,1334 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_tim.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the TIM firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __stm32f30x_TIM_H
+#define __stm32f30x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup stm32f30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TIM Time Base Init structure definition  
+  * @note   This structure is used with all TIMx except for TIM6 and TIM7.  
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef; 
+
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_State */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/** 
+  * @brief  BDTR structure definition 
+  * @note   This structure is used only with TIM1 and TIM8.    
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_constants 
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM8) || \
+                                   ((PERIPH) == TIM15) || \
+                                   ((PERIPH) == TIM16) || \
+                                   ((PERIPH) == TIM17))
+/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */                                         
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15) || \
+                                     ((PERIPH) == TIM16) || \
+                                     ((PERIPH) == TIM17))
+                                     
+/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */ 
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15))
+/* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */ 
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM8))
+/* LIST4: TIM1 and TIM8 */ 
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
+                                     ((PERIPH) == TIM8))
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM6) || \
+                                     ((PERIPH) == TIM7) || \
+                                     ((PERIPH) == TIM8))
+/* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */                               
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15) || \
+                                     ((PERIPH) == TIM16) || \
+                                     ((PERIPH) == TIM17))
+
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM6) || \
+                                     ((PERIPH) == TIM7) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM15))
+/* LIST8: TIM16 (option register) */                               
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)||  \
+                                     ((PERIPH) == TIM1)||\
+                                     ((PERIPH) == TIM8))
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint32_t)0x00000)
+#define TIM_OCMode_Active                  ((uint32_t)0x00010)
+#define TIM_OCMode_Inactive                ((uint32_t)0x00020)
+#define TIM_OCMode_Toggle                  ((uint32_t)0x00030)
+#define TIM_OCMode_PWM1                    ((uint32_t)0x00060)
+#define TIM_OCMode_PWM2                    ((uint32_t)0x00070)
+
+#define TIM_OCMode_Retrigerrable_OPM1      ((uint32_t)0x10000)
+#define TIM_OCMode_Retrigerrable_OPM2      ((uint32_t)0x10010)
+#define TIM_OCMode_Combined_PWM1           ((uint32_t)0x10040)
+#define TIM_OCMode_Combined_PWM2           ((uint32_t)0x10050)
+#define TIM_OCMode_Asymmetric_PWM1         ((uint32_t)0x10060)
+#define TIM_OCMode_Asymmetric_PWM2         ((uint32_t)0x10070)
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2) || \
+                              ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
+                              ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
+                              ((MODE) == TIM_OCMode_Combined_PWM1) || \
+                              ((MODE) == TIM_OCMode_Combined_PWM2) || \
+                              ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
+                              ((MODE) == TIM_OCMode_Asymmetric_PWM2))
+                              
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive) || \
+                          ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
+                          ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
+                          ((MODE) == TIM_OCMode_Combined_PWM1) || \
+                          ((MODE) == TIM_OCMode_Combined_PWM2) || \
+                          ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
+                          ((MODE) == TIM_OCMode_Asymmetric_PWM2))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+#define TIM_Channel_5                      ((uint16_t)0x0010)
+#define TIM_Channel_6                      ((uint16_t)0x0014)
+                                 
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+                                 
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State 
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_State
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_State
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_N_State
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break1_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break1_Enable                   ((uint32_t)0x00001000)
+#define TIM_Break1_Disable                  ((uint32_t)0x00000000)
+#define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
+                                   ((STATE) == TIM_Break1_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break2_Enable                   ((uint32_t)0x01000000)
+#define TIM_Break2_Disable                  ((uint32_t)0x00000000)
+#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
+                                   ((STATE) == TIM_Break2_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity 
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break1_Polarity 
+  * @{
+  */
+
+#define TIM_Break1Polarity_Low              ((uint32_t)0x00000000)
+#define TIM_Break1Polarity_High             ((uint32_t)0x00002000)
+#define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
+                                         ((POLARITY) == TIM_Break1Polarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break2_Polarity 
+  * @{
+  */
+
+#define TIM_Break2Polarity_Low              ((uint32_t)0x00000000)
+#define TIM_Break2Polarity_High             ((uint32_t)0x02000000)
+#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
+                                         ((POLARITY) == TIM_Break2Polarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break1_Filter 
+  * @{
+  */
+
+#define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break2_Filter 
+  * @{
+  */
+
+#define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Lock_level
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_interrupt_sources 
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
+#define TIM_DMABase_CCMR3                  ((uint16_t)0x0014)
+#define TIM_DMABase_CCR5                   ((uint16_t)0x0015)
+#define TIM_DMABase_CCR6                   ((uint16_t)0x0016)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR) || \
+                               ((BASE) == TIM_DMABase_OR) || \
+                               ((BASE) == TIM_DMABase_CCMR3) || \
+                               ((BASE) == TIM_DMABase_CCR5) || \
+                               ((BASE) == TIM_DMABase_CCR6))                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Forced_Action 
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define TIM_EventSource_Break2             ((uint16_t)0x0100)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))                                          
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Update_Source 
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+
+
+#define TIM_TRGO2Source_Reset                             ((uint32_t)0x00000000)
+#define TIM_TRGO2Source_Enable                            ((uint32_t)0x00100000)
+#define TIM_TRGO2Source_Update                            ((uint32_t)0x00200000)
+#define TIM_TRGO2Source_OC1                               ((uint32_t)0x00300000)
+#define TIM_TRGO2Source_OC1Ref                            ((uint32_t)0x00400000)
+#define TIM_TRGO2Source_OC2Ref                            ((uint32_t)0x00500000)
+#define TIM_TRGO2Source_OC3Ref                            ((uint32_t)0x00600000)
+#define TIM_TRGO2Source_OC4Ref                            ((uint32_t)0x00700000)
+#define TIM_TRGO2Source_OC5Ref                            ((uint32_t)0x00800000)
+#define TIM_TRGO2Source_OC6Ref                            ((uint32_t)0x00900000)
+#define TIM_TRGO2Source_OC4Ref_RisingFalling              ((uint32_t)0x00A00000)
+#define TIM_TRGO2Source_OC6Ref_RisingFalling              ((uint32_t)0x00B00000)
+#define TIM_TRGO2Source_OC4RefRising_OC6RefRising         ((uint32_t)0x00C00000)
+#define TIM_TRGO2Source_OC4RefRising_OC6RefFalling        ((uint32_t)0x00D00000)
+#define TIM_TRGO2Source_OC5RefRising_OC6RefRising         ((uint32_t)0x00E00000)
+#define TIM_TRGO2Source_OC5RefRising_OC6RefFalling        ((uint32_t)0x00F00000)
+#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
+                                     ((SOURCE) == TIM_TRGO2Source_Enable) || \
+                                     ((SOURCE) == TIM_TRGO2Source_Update) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC1) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
+                                     ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                       ((uint32_t)0x00004)
+#define TIM_SlaveMode_Gated                       ((uint32_t)0x00005)
+#define TIM_SlaveMode_Trigger                     ((uint32_t)0x00006)
+#define TIM_SlaveMode_External1                   ((uint32_t)0x00007)
+#define TIM_SlaveMode_Combined_ResetTrigger       ((uint32_t)0x10000)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1) || \
+                                 ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+/** @defgroup TIM_Remap 
+  * @{
+  */
+#define TIM16_GPIO                      ((uint16_t)0x0000)
+#define TIM16_RTC_CLK                   ((uint16_t)0x0001)
+#define TIM16_HSEDiv32                  ((uint16_t)0x0002)
+#define TIM16_MCO                       ((uint16_t)0x0003)
+
+#define TIM1_ADC1_AWDG1                ((uint16_t)0x0001)
+#define TIM1_ADC1_AWDG2                ((uint16_t)0x0002)
+#define TIM1_ADC1_AWDG3                ((uint16_t)0x0003)
+#define TIM1_ADC4_AWDG1                ((uint16_t)0x0004)
+#define TIM1_ADC4_AWDG2                ((uint16_t)0x0008)
+#define TIM1_ADC4_AWDG3                ((uint16_t)0x000C)
+
+#define TIM8_ADC2_AWDG1                ((uint16_t)0x0001)
+#define TIM8_ADC2_AWDG2                ((uint16_t)0x0002)
+#define TIM8_ADC2_AWDG3                ((uint16_t)0x0003)
+#define TIM8_ADC3_AWDG1                ((uint16_t)0x0004)
+#define TIM8_ADC3_AWDG2                ((uint16_t)0x0008)
+#define TIM8_ADC3_AWDG3                ((uint16_t)0x000C)
+
+#define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM16_GPIO)|| \
+                                  ((TIM_REMAP) == TIM16_RTC_CLK) || \
+                                  ((TIM_REMAP) == TIM16_HSEDiv32) || \
+                                  ((TIM_REMAP) == TIM16_MCO) ||\
+                                  ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
+                                  ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
+                                  ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
+                                  ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
+                                  ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
+                                  ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
+                                  ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
+                                  ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
+                                  ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
+                                  ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
+                                  ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
+                                  ((TIM_REMAP) == TIM8_ADC3_AWDG3))                                  
+
+/**
+  * @}
+  */ 
+/** @defgroup TIM_Flags 
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint32_t)0x00001)
+#define TIM_FLAG_CC1                       ((uint32_t)0x00002)
+#define TIM_FLAG_CC2                       ((uint32_t)0x00004)
+#define TIM_FLAG_CC3                       ((uint32_t)0x00008)
+#define TIM_FLAG_CC4                       ((uint32_t)0x00010)
+#define TIM_FLAG_COM                       ((uint32_t)0x00020)
+#define TIM_FLAG_Trigger                   ((uint32_t)0x00040)
+#define TIM_FLAG_Break                     ((uint32_t)0x00080)
+#define TIM_FLAG_Break2                    ((uint32_t)0x00100)
+#define TIM_FLAG_CC1OF                     ((uint32_t)0x00200)
+#define TIM_FLAG_CC2OF                     ((uint32_t)0x00400)
+#define TIM_FLAG_CC3OF                     ((uint32_t)0x00800)
+#define TIM_FLAG_CC4OF                     ((uint32_t)0x01000)
+#define TIM_FLAG_CC5                       ((uint32_t)0x10000)
+#define TIM_FLAG_CC6                       ((uint32_t)0x20000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_Break2) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF) ||\
+                               ((FLAG) == TIM_FLAG_CC5) ||\
+                               ((FLAG) == TIM_FLAG_CC6))
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_OCReferenceClear 
+  * @{
+  */
+#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Legacy 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
+void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);  
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
+void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
+void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/   
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__stm32f30x_TIM_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h
new file mode 100644
index 0000000..3a9ad2c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_usart.h
@@ -0,0 +1,607 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_usart.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_USART_H
+#define __STM32F30x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+   
+   
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+  uint32_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint32_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint32_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition
+  */ 
+
+typedef struct
+{
+  uint32_t USART_Clock;             /*!< Specifies whether the USART clock is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Clock */
+
+  uint32_t USART_CPOL;              /*!< Specifies the steady state of the serial clock.
+                                         This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint32_t USART_CPHA;              /*!< Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint32_t USART_LastBit;           /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                         data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                         This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4) || \
+                                     ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                      ((PERIPH) == USART2) || \
+                                      ((PERIPH) == USART3) || \
+                                      ((PERIPH) == UART4))
+
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+
+#define USART_WordLength_8b                  ((uint32_t)0x00000000)
+#define USART_WordLength_9b                  USART_CR1_M
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+
+#define USART_StopBits_1                     ((uint32_t)0x00000000)
+#define USART_StopBits_2                     USART_CR2_STOP_1
+#define USART_StopBits_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+
+#define USART_Parity_No                      ((uint32_t)0x00000000)
+#define USART_Parity_Even                    USART_CR1_PCE
+#define USART_Parity_Odd                     (USART_CR1_PCE | USART_CR1_PS) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+
+#define USART_Mode_Rx                        USART_CR1_RE
+#define USART_Mode_Tx                        USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+                              ((MODE) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+
+#define USART_HardwareFlowControl_None       ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS        USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS        USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS    (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+  
+#define USART_Clock_Disable                  ((uint32_t)0x00000000)
+#define USART_Clock_Enable                   USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint32_t)0x00000000)
+#define USART_CPOL_High                      USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge                     USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint32_t)0x00000000)
+#define USART_LastBit_Enable                 USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      USART_CR3_DMAT
+#define USART_DMAReq_Rx                      USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+                                  ((DMAREQ) != (uint32_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DMA_Recception_Error
+  * @{
+  */
+
+#define USART_DMAOnError_Enable              ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable             USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+                                       ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark             USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                          ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Address_Detection
+  * @{
+  */ 
+
+#define USART_AddressLength_4b               ((uint32_t)0x00000000)
+#define USART_AddressLength_7b               USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+                                             ((ADDRESS) == USART_AddressLength_7b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_StopMode_WakeUp_methods 
+  * @{
+  */ 
+
+#define USART_WakeUpSource_AddressMatch      ((uint32_t)0x00000000)
+#define USART_WakeUpSource_StartBit          USART_CR3_WUS_1
+#define USART_WakeUpSource_RXNE              (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
+                                                ((SOURCE) == USART_WakeUpSource_StartBit) || \
+                                                ((SOURCE) == USART_WakeUpSource_RXNE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b       ((uint32_t)0x00000000)
+#define USART_LINBreakDetectLength_11b       USART_CR2_LBDL
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              USART_CR3_IRLP
+#define USART_IrDAMode_Normal                ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DE_Polarity 
+  * @{
+  */
+
+#define USART_DEPolarity_High                ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low                 USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+                                        ((POLARITY) == USART_DEPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Inversion_Pins 
+  * @{
+  */
+
+#define USART_InvPin_Tx                      USART_CR2_TXINV
+#define USART_InvPin_Rx                      USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+                                       ((PIN) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_AutoBaudRate_Mode 
+  * @{
+  */
+
+#define USART_AutoBaudRate_StartBit                 ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge              USART_CR2_ABRMODE_0
+#define USART_AutoBaudRate_0x7FFrame                USART_CR2_ABRMODE_1
+#define USART_AutoBaudRate_0x55Frame                (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+                                          ((MODE) == USART_AutoBaudRate_FallingEdge) || \
+                                          ((MODE) == USART_AutoBaudRate_0x7FFrame) || \
+                                          ((MODE) == USART_AutoBaudRate_0x55Frame))
+/**
+  * @}
+  */
+
+/** @defgroup USART_OVR_DETECTION
+  * @{
+  */
+
+#define USART_OVRDetection_Enable            ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable           USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+                                    ((OVR) == USART_OVRDetection_Disable))
+/**
+  * @}
+  */ 
+/** @defgroup USART_Request 
+  * @{
+  */
+
+#define USART_Request_ABRRQ                  USART_RQR_ABRRQ
+#define USART_Request_SBKRQ                  USART_RQR_SBKRQ
+#define USART_Request_MMRQ                   USART_RQR_MMRQ
+#define USART_Request_RXFRQ                  USART_RQR_RXFRQ
+#define USART_Request_TXFRQ                  USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+                                   ((REQUEST) == USART_Request_RXFRQ) || \
+                                   ((REQUEST) == USART_Request_MMRQ) || \
+                                   ((REQUEST) == USART_Request_SBKRQ) || \
+                                   ((REQUEST) == USART_Request_ABRRQ))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+#define USART_FLAG_REACK                     USART_ISR_REACK
+#define USART_FLAG_TEACK                     USART_ISR_TEACK
+#define USART_FLAG_WU                        USART_ISR_WUF
+#define USART_FLAG_RWU                       USART_ISR_RWU
+#define USART_FLAG_SBK                       USART_ISR_SBKF
+#define USART_FLAG_CM                        USART_ISR_CMF
+#define USART_FLAG_BUSY                      USART_ISR_BUSY
+#define USART_FLAG_ABRF                      USART_ISR_ABRF
+#define USART_FLAG_ABRE                      USART_ISR_ABRE
+#define USART_FLAG_EOB                       USART_ISR_EOBF
+#define USART_FLAG_RTO                       USART_ISR_RTOF
+#define USART_FLAG_nCTSS                     USART_ISR_CTS 
+#define USART_FLAG_CTS                       USART_ISR_CTSIF
+#define USART_FLAG_LBD                       USART_ISR_LBD
+#define USART_FLAG_TXE                       USART_ISR_TXE
+#define USART_FLAG_TC                        USART_ISR_TC
+#define USART_FLAG_RXNE                      USART_ISR_RXNE
+#define USART_FLAG_IDLE                      USART_ISR_IDLE
+#define USART_FLAG_ORE                       USART_ISR_ORE
+#define USART_FLAG_NE                        USART_ISR_NE
+#define USART_FLAG_FE                        USART_ISR_FE
+#define USART_FLAG_PE                        USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                             ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+                             ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+                             ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+                             ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+                             ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+                             ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+                                   ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+                                   ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                                   ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+                                   ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+                                   ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @brief USART Interrupt definition
+  * USART_IT possible values
+  * Elements values convention: 0xZZZZYYXX
+  *   XX: Position of the corresponding Interrupt
+  *   YY: Register index
+  *   ZZZZ: Flag position
+  * @{
+  */
+
+#define USART_IT_WU                          ((uint32_t)0x00140316)
+#define USART_IT_CM                          ((uint32_t)0x0011010E)
+#define USART_IT_EOB                         ((uint32_t)0x000C011B)
+#define USART_IT_RTO                         ((uint32_t)0x000B011A)
+#define USART_IT_PE                          ((uint32_t)0x00000108)
+#define USART_IT_TXE                         ((uint32_t)0x00070107)
+#define USART_IT_TC                          ((uint32_t)0x00060106)
+#define USART_IT_RXNE                        ((uint32_t)0x00050105)
+#define USART_IT_IDLE                        ((uint32_t)0x00040104)
+#define USART_IT_LBD                         ((uint32_t)0x00080206)
+#define USART_IT_CTS                         ((uint32_t)0x0009030A) 
+#define USART_IT_ERR                         ((uint32_t)0x00000300)
+#define USART_IT_ORE                         ((uint32_t)0x00030300)
+#define USART_IT_NE                          ((uint32_t)0x00020300)
+#define USART_IT_FE                          ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+                                ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                                ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+                             ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                             ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+                               ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+                               ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+                               ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                               ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Global_definition 
+  * @{
+  */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* STOP Mode functions ********************************************************/
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_USART_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h
new file mode 100644
index 0000000..07cc0b0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc/stm32f30x_wwdg.h
@@ -0,0 +1,109 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the WWDG 
+  *          firmware library.    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_WWDG_H
+#define __STM32F30X_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */ 
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the WWDG configuration to the default reset state ****/  
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation functions **************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30X_WWDG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c
new file mode 100644
index 0000000..b455973
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c
@@ -0,0 +1,503 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_comp.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral: 
+  *           + Comparators configuration
+  *           + Window mode control
+  *
+  @verbatim
+   
+  ==============================================================================
+                        ##### COMP Peripheral features #####
+  ==============================================================================
+  [..]       
+      The device integrates 7 analog comparators COMP1, COMP2...COMP7:
+      (#) The non inverting input and inverting input can be set to GPIO pins
+          as shown in table1. COMP Inputs below.
+  
+      (#) The COMP output is internally is available using COMP_GetOutputLevel()
+          and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
+  
+      (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
+          Refer to table 3. COMP Outputs redirection to embedded timers below.
+  
+      (#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
+          mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
+  
+      (#) The seven comparators have interrupt capability with wake-up
+          from Sleep and Stop modes (through the EXTI controller):
+          (++) COMP1 is internally connected to EXTI Line 21
+          (++) COMP2 is internally connected to EXTI Line 22
+          (++) COMP3 is internally connected to EXTI Line 29
+          (++) COMP4 is internally connected to EXTI Line 30
+          (++) COMP5 is internally connected to EXTI Line 31
+          (++) COMP6 is internally connected to EXTI Line 32
+          (++) COMP7 is internally connected to EXTI Line 33
+
+ [..] Table 1. COMP Inputs
+ +------------------------------------------------------------------------------------------+     
+ |                 |                | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-----------------|----------------|---------------|---------------------------------------|
+ |                 | 1/4 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ |                 | 1/2 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ |                 | 3/4 VREFINT    |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ | Inverting Input | VREFINT        |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ |                 | DAC1 OUT (PA4) |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ |                 | DAC2 OUT (PA5) |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |  OK   |
+ |                 | IO1            |  PA0  |  PA2  |  PD15 |  PE8  |  PD13 |  PD10 |  PC0  |
+ |                 | IO2            |  ---  |  ---  |  PB12 |  PB2  |  PB10 |  PB15 |  ---  |
+ |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
+ |  Non Inverting  | IO1            |  PA1  |  PA7  |  PB14 |  PB0  |  PD12 |  PD11 |  PA0  |
+ |    Input        | IO2            |  ---  |  PA3  |  PD14 |  PE7  |  PB13 |  PB11 |  PC1  |
+ +------------------------------------------------------------------------------------------+  
+
+ [..] Table 2. COMP Outputs
+ +-------------------------------------------------------+     
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-------|-------|-------|-------|-------|-------|-------|
+ |  PA0  |  PA2  |  PB1  |  PC8  |  PC7  |  PA10 |  PC2  |
+ |  PF4  |  PA7  |  ---  |  PA8  |  PA9  |  PC6  |  ---  |
+ |  PA6  |  PA12 |  ---  |  ---  |  ---  |  ---  |  ---  |
+ |  PA11 |  PB9  |  ---  |  ---  |  ---  |  ---  |  ---  |
+ |  PB8  |  ---  |  ---  |  ---  |  ---  |  ---  |  ---  |
+ +-------------------------------------------------------+
+
+ [..] Table 3. COMP Outputs redirection to embedded timers
+ +----------------------------------------------------------------------------------------------------------------------+     
+ |     COMP1      |     COMP2      |     COMP3      |     COMP4      |     COMP5      |     COMP6      |     COMP7      |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |  TIM1 BKIN     |
+ |                |                |                |                |                |                |                |
+ |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
+ |                |                |                |                |                |                |                |
+ |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |  TIM8 BKIN     |
+ |                |                |                |                |                |                |                |
+ |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |  TIM8 BKIN2    |
+ |                |                |                |                |                |                |                |
+ |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |  TIM1 BKIN2    |
+ |     +          |     +          |     +          |     +          |     +          |     +          |     +          |
+ |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |  TIM8BKIN2     |
+ |                |                |                |                |                |                |                |
+ |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM1 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM8 OCREFCLR |  TIM1 OCREFCLR |  
+ |                |                |                |                |                |                |                |
+ |  TIM1 IC1      |  TIM1 IC1      |  TIM2 OCREFCLR |  TIM3 IC3      |  TIM2 IC1      |  TIM2 IC2      |  TIM8 OCREFCLR |
+ |                |                |                |                |                |                |                |
+ |  TIM2 IC4      |  TIM2 IC4      |  TIM3 IC2      |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM2 OCREFCLR |  TIM2 IC3      |
+ |                |                |                |                |                |                |                |
+ |  TIM2 OCREFCLR |  TIM2 OCREFCLR |  TIM4 IC1      |  TIM4 IC2      |  TIM4 IC3      |  TIM16 OCREFCLR|  TIM1 IC2      |
+ |                |                |                |                |                |                |                |
+ |  TIM3 IC1      |  TIM3 IC1      |  TIM15 IC1     |  TIM15 OCREFCLR|  TIM16 BKIN    |  TIM16 IC1     |  TIM17 OCREFCLR|          
+ |                |                |                |                |                |                |                |
+ |  TIM3 OCREFCLR |  TIM3 OCREFCLR |  TIM15 BKIN    |  TIM15 IC2     |  TIM17 IC1     |  TIM4 IC4      |  TIM17 BKIN    |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+ [..] Table 4. COMP Outputs blanking sources
+ +----------------------------------------------------------------------------------------------------------------------+
+ |     COMP1      |     COMP2      |     COMP3      |     COMP4      |     COMP5      |     COMP6      |     COMP7      |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ |  TIM1 OC5      |  TIM1 OC5      |  TIM1 OC5      |  TIM3 OC4      |  TIM3 OC3      |  TIM2 OC4      |  TIM1 OC5      |
+ |                |                |                |                |                |                |                |
+ |  TIM2 OC3      |  TIM2 OC3      |  --------      |  TIM8 OC5      |  TIM8 OC5      |  TIM8 OC5      |  TIM8 OC5      |
+ |                |                |                |                |                |                |                |
+ |  TIM3 OC3      |  TIM3 OC3      |  TIM2 OC4      |  TIM15 OC1     |  TIM8 BKIN     |  TIM15 OC2     |  TIM15 OC2     |
+ |                |                |                |                |                |                |                |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+  
+                         ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  This driver provides functions to configure and program the Comparators 
+  of all STM32F30x devices.
+  
+  To use the comparator, perform the following steps:
+  
+  (#) Enable the SYSCFG APB clock to get write access to comparator
+      register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+  (#) Configure the comparator input in analog mode using GPIO_Init()
+  
+  (#) Configure the comparator output in alternate function mode
+      using GPIO_Init() and use GPIO_PinAFConfig() function to map the
+      comparator output to the GPIO pin
+  
+  (#) Configure the comparator using COMP_Init() function:
+      (++) Select the inverting input
+      (++) Select the non-inverting input
+      (++) Select the output polarity  
+      (++) Select the output redirection
+      (++) Select the hysteresis level
+      (++) Select the power mode
+  
+  (#) Enable the comparator using COMP_Cmd() function
+  
+  (#) If required enable the COMP interrupt by configuring and enabling
+      EXTI line in Interrupt mode and selecting the desired sensitivity
+      level using EXTI_Init() function. After that enable the comparator
+      interrupt vector using NVIC_Init() function.
+
+  @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_comp.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CSR register Mask */
+#define COMP_CSR_CLEAR_MASK              ((uint32_t)0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup COMP_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+  *          to select the COMP peripheral.
+  * @param  None
+  * @retval None
+  */
+void COMP_DeInit(uint32_t COMP_Selection)
+{
+  /*!< Set COMP_CSR register to reset value */
+  *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+  *          to select the COMP peripheral.
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains 
+  *         the configuration information for the specified COMP peripheral.
+  *           - COMP_InvertingInput specifies the inverting input of COMP
+  *           - COMP_NonInvertingInput specifies the non inverting input of COMP
+  *           - COMP_Output connect COMP output to selected timer
+  *             input (Input capture / Output Compare Reference Clear / Break Input)
+  *           - COMP_BlankingSrce specifies the blanking source of COMP
+  *           - COMP_OutputPol select output polarity
+  *           - COMP_Hysteresis configures COMP hysteresis value
+  *           - COMP_Mode configures COMP power mode
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
+  assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
+  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+  assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
+  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
+  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+  /*!< Get the COMPx_CSR register value */
+  tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
+
+  /*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
+  tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
+
+  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+  /*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
+  /*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
+  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
+  tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
+                        COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
+                        COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
+
+  /*!< Write to COMPx_CSR register */
+  *(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
+{
+  COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
+  COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
+  COMP_InitStruct->COMP_Output = COMP_Output_None;
+  COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
+  COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
+  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+  COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+  *          to select the COMP peripheral.
+  * @param  NewState: new state of the COMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  *         When enabled, the comparator compares the non inverting input with 
+  *                       the inverting input and the comparison result is available
+  *                       on comparator output.
+  *         When disabled, the comparator doesn't perform comparison and the 
+  *                        output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected COMPx peripheral */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
+  }
+  else
+  {
+    /* Disable the selected COMP peripheral  */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
+  }
+}
+
+/**
+  * @brief  Close or Open the SW1 switch.
+  * @note   If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
+  *         To unlock the configuration, perform a system reset.  
+  * @note   This switch is solely intended to redirect signals onto high
+  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
+  * @param  NewState: New state of the analog switch.
+  *   This parameter can be 
+  *     ENABLE so the SW1 is closed; PA1 is connected to PA4
+  *     or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
+  * @retval None
+  */
+void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close SW1 switch */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
+  }
+  else
+  {
+    /* Open SW1 switch */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  *         The output level depends on the selected polarity.
+  *         If the polarity is not inverted:
+  *           - Comparator output is low when the non-inverting input is at a lower
+  *             voltage than the inverting input
+  *           - Comparator output is high when the non-inverting input is at a higher
+  *             voltage than the inverting input
+  *         If the polarity is inverted:
+  *           - Comparator output is high when the non-inverting input is at a lower
+  *             voltage than the inverting input
+  *           - Comparator output is low when the non-inverting input is at a higher
+  *             voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+  *          to select the COMP peripheral.
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
+{
+  uint32_t compout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if selected comparator output is high */
+  if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
+  {
+    compout = COMP_OutputLevel_High;
+  }
+  else
+  {
+    compout = COMP_OutputLevel_Low;
+  }
+
+  /* Return the comparator output level */
+  return (uint32_t)(compout);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group2 Window mode control function
+ *  @brief   Window mode control function 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Window mode control function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the window mode.
+  *         Window mode for comparators makes use of two comparators:
+  *         COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
+  *         In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
+  *         non inverting inputs are connected together and only COMPx-1 non
+  *         inverting input can be used.
+  *         e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
+  *             is to be used.
+  * @note   If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
+  *          to select the COMP peripheral.
+  * param   NewState: new state of the window mode.
+  *   This parameter can be ENABLE or DISABLE.
+  *        When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
+  *        When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_COMP_WINDOW(COMP_Selection));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    *(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group3 COMP configuration locking function
+ *  @brief   COMP1, COMP2,...COMP7 configuration locking function
+ *           COMP1, COMP2,...COMP7 configuration can be locked each separately.
+ *           Unlocking is performed by system reset.
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Configuration Lock function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be COMP_Selection_COMPx where x can be 1 to 7
+  *          to select the COMP peripheral.
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Set the lock bit corresponding to selected comparator */
+  *(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c
new file mode 100644
index 0000000..3a47b85
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_crc.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of CRC computation unit peripheral:
+  *            + Configuration of the CRC computation unit
+  *            + CRC computation of one/many 32-bit data
+  *            + CRC Independent register (IDR) access
+  *
+  @verbatim
+    
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..] 
+    (#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
+        function.
+    (#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
+    (#) Set the polynomial coefficients using CRC_SetPolynomial();  
+    (#) If required, select the reverse operation on input data 
+        using CRC_ReverseInputDataSelect();  
+    (#) If required, enable the reverse operation on output data
+        using CRC_ReverseOutputDataCmd(Enable);
+    (#) If required, set the initialization remainder value using
+        CRC_SetInitRegister();
+    (#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
+        or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit 
+        data buffer.
+
+  @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_crc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
+ *  @brief   Configuration of the CRC computation unit functions 
+ *
+@verbatim
+ ===============================================================================
+                  ##### CRC configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes CRC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CRC_DeInit(void)
+{
+  /* Set DR register to reset value */
+  CRC->DR = 0xFFFFFFFF;
+  /* Set the POL register to the reset value: 0x04C11DB7 */
+  CRC->POL = 0x04C11DB7;
+  /* Reset IDR register */
+  CRC->IDR = 0x00;
+  /* Set INIT register to reset value */
+  CRC->INIT = 0xFFFFFFFF;
+  /* Reset the CRC calculation unit */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Resets the CRC calculation unit and sets INIT register content in DR register.
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR |= CRC_CR_RESET;
+}
+
+/**
+  * @brief  Selects the polynomial size.
+  * @param  CRC_PolSize: Specifies the polynomial size.
+  *         This parameter can be:
+  *          @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
+  *          @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
+  * @retval None
+  */
+void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
+{
+  uint32_t tmpcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
+
+  /* Get CR register value */
+  tmpcr = CRC->CR;
+
+  /* Reset POL_SIZE bits */
+  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
+  /* Set the polynomial size */
+  tmpcr |= (uint32_t)CRC_PolSize;
+
+  /* Write to CR register */
+  CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+  * @brief  Selects the reverse operation to be performed on input data.
+  * @param  CRC_ReverseInputData: Specifies the reverse operation on input data.
+  *         This parameter can be:
+  *          @arg CRC_ReverseInputData_No: No reverse operation is performed
+  *          @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
+  *          @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
+  *          @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
+  * @retval None
+  */
+void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
+{
+  uint32_t tmpcr = 0;
+
+  /* Check the parameter */
+  assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
+
+  /* Get CR register value */
+  tmpcr = CRC->CR;
+
+  /* Reset REV_IN bits */
+  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
+  /* Set the reverse operation */
+  tmpcr |= (uint32_t)CRC_ReverseInputData;
+
+  /* Write to CR register */
+  CRC->CR = (uint32_t)tmpcr;
+}
+
+/**
+  * @brief  Enables or disable the reverse operation on output data.
+  *         The reverse operation on output data is performed on 32-bit.
+  * @param  NewState: new state of the reverse operation on output data.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRC_ReverseOutputDataCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable reverse operation on output data */
+    CRC->CR |= CRC_CR_REV_OUT;
+  }
+  else
+  {
+    /* Disable reverse operation on output data */
+    CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
+  }
+}
+
+/**
+  * @brief  Initializes the INIT register.
+  * @note   After resetting CRC calculation unit, CRC_InitValue is stored in DR register
+  * @param  CRC_InitValue: Programmable initial CRC value
+  * @retval None
+  */
+void CRC_SetInitRegister(uint32_t CRC_InitValue)
+{
+  CRC->INIT = CRC_InitValue;
+}
+
+/**
+  * @brief  Initializes the polynomail coefficients.
+  * @param  CRC_Pol: Polynomial to be used for CRC calculation.
+  * @retval None
+  */
+void CRC_SetPolynomial(uint32_t CRC_Pol)
+{
+  CRC->POL = CRC_Pol;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
+ *  @brief   CRC computation of one/many 32-bit data functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### CRC computation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  CRC_Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t CRC_Data)
+{
+  CRC->DR = CRC_Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 16-bit CRC of a given 16-bit data.
+  * @param  CRC_Data: data half-word(16-bit) to compute its CRC
+  * @retval 16-bit CRC
+  */
+uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
+{
+  *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 8-bit CRC of a given 8-bit data.
+  * @param  CRC_Data: 8-bit data to compute its CRC
+  * @retval 8-bit CRC
+  */
+uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
+{
+  *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
+
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
+ *  @brief   CRC Independent Register (IDR) access (write/read) functions
+ *
+@verbatim
+ ===============================================================================
+           ##### CRC Independent Register (IDR) access functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Stores an 8-bit data in the Independent Data(ID) register.
+  * @param  CRC_IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t CRC_IDValue)
+{
+  CRC->IDR = CRC_IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c
new file mode 100644
index 0000000..e93b532
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c
@@ -0,0 +1,213 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Debug MCU (DBGMCU) peripheral:
+  *           + Device and Revision ID management
+  *           + Peripherals Configuration
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dbgmcu.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
+ *  @brief   Device and Revision ID management functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Device and Revision ID management functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief   Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
+ *  @brief   Peripherals Configuration
+ *
+@verbatim
+  ==============================================================================
+               ##### Peripherals Configuration functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode.               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.        
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *   This parameter can be any combination of the following values:        
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
+  *     @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when 
+  *          Core is halted. 
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.        
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when 
+  *          Core is halted.
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when 
+  *          Core is halted.
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.        
+  * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *   This parameter can be any combination of the following values:       
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.   
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted. 
+  *     @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.                
+  *     @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
+  *     @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.   
+  * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c
new file mode 100644
index 0000000..8982b1e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c
@@ -0,0 +1,866 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_dma.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):
+  *           + Initialization and Configuration
+  *           + Data Counter
+  *           + Interrupts and flags management
+  *
+  @verbatim
+    
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    (#) Enable The DMA controller clock using 
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or 
+        using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
+    (#) Enable and configure the peripheral to be connected to the DMA channel
+        (except for internal SRAM / FLASH memories: no initialization is necessary). 
+    (#) For a given Channel, program the Source and Destination addresses,  
+        the transfer Direction, the Buffer Size, the Peripheral and Memory
+        Incrementation mode and Data Size, the Circular or Normal mode, 
+        the channel transfer Priority and the Memory-to-Memory transfer 
+        mode (if needed) using the DMA_Init() function.
+    (#) Enable the NVIC and the corresponding interrupt(s) using the function 
+        DMA_ITConfig() if you need to use DMA interrupts.
+    (#) Enable the DMA channel using the DMA_Cmd() function.
+    (#) Activate the needed channel Request using PPP_DMACmd() function for
+        any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+        The function allowing this operation is provided in each PPP peripheral
+        driver (ie. SPI_DMACmd for SPI peripheral).
+    (#) Optionally, you can configure the number of data to be transferred
+        when the channel is disabled (ie. after each Transfer Complete event
+        or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+        And you can get the number of remaining data to be transferred using 
+        the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
+        enabled and running).
+    (#) To control DMA events you can use one of the following two methods:
+        (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
+        (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+             phase and DMA_GetITStatus() function into interrupt routines in
+             communication phase.
+             After checking on a flag you should clear it using DMA_ClearFlag()
+             function. And after checking on an interrupt event you should 
+             clear it using DMA_ClearITPendingBit() function.
+
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dma.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask        ((uint32_t)0x10000000) /* DMA2 FLAG mask */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions 
+  * @{
+  */
+
+/** @defgroup  DMA_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to initialize the DMA channel 
+         source and destination addresses, incrementation and data sizes, transfer 
+         direction, buffer size, circular/normal mode selection, memory-to-memory 
+         mode selection and channel priority value.
+    [..] The DMA_Init() function follows the DMA configuration procedures as described 
+         in reference manual (RM00316).
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CCR  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->CNDTR = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPAR  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMAR = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
+  }
+  else
+  { 
+    if (DMAy_Channelx == DMA2_Channel5)
+    {
+      /* Reset interrupt pending bits for DMA2 Channel5 */
+      DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified parameters 
+  *         in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CCR;
+
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CCR_CLEAR_MASK;
+
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CCR |= DMA_CCR_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Group2 Data Counter functions
+ *  @brief   Data Counter functions
+ *
+@verbatim  
+ ===============================================================================
+                      ##### Data Counter functions #####
+ ===============================================================================
+    [..] This subsection provides function allowing to configure and read the buffer 
+         size (number of data to be transferred).The DMA data counter can be written 
+         only when the DMA channel is disabled (ie. after transfer complete event).
+    [..] The following function can be used to write the Channel data counter value:
+         (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
+    [..]
+    (@) It is advised to use this function rather than DMA_Init() in situations 
+        where only the Data buffer needs to be reloaded.
+    [..] The DMA data counter can be read to indicate the number of remaining transfers 
+         for the relative DMA channel. This counter is decremented at the end of each 
+         data transfer and when the transfer is complete: 
+         (+) If Normal mode is selected: the counter is set to 0.
+         (+) If Circular mode is selected: the counter is reloaded with the initial 
+         value(configured before enabling the DMA channel).
+    [..] The following function can be used to read the Channel data counter value:
+         (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.   
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None.
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim
+ ===============================================================================
+          ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to configure the DMA Interrupt 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the DMA controller events: Polling mode or Interrupt mode. 
+  
+  *** Polling Mode ***
+  ====================
+    [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller 
+         number, x : DMA channel number):
+         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
+         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
+         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
+         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
+             above occurred.
+    [..]         
+    (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
+        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+         (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] Each DMA channel can be managed through 4 Interrupts:
+    (+) Interrupt Source
+       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
+            event.
+       (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete 
+            event.
+       (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
+       (##) DMA_IT_GL: to indicate that at least one of the interrupts described 
+            above occurred.
+    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
+         the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
+    [..] In this Mode it is advised to use the following functions:
+         (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+         (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+         (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *         or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg DMA_IT_TC: Transfer complete interrupt mask
+  *     @arg DMA_IT_HT: Half transfer interrupt mask
+  *     @arg DMA_IT_TE: Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMAy_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  *     
+  * @note
+  *    The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags 
+  *    relative to the same channel is set (Transfer Complete, Half-transfer 
+  *    Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or 
+  *    DMAy_FLAG_TEx). 
+  *      
+  * @retval The new state of DMAy_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMAy_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  *
+  * @note
+  *    Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+  *    relative to the same channel (Transfer Complete, Half-transfer Complete and
+  *    Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+  *
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->IFCR = DMAy_FLAG;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->IFCR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  *     
+  * @note
+  *    The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other 
+  *    interrupts relative to the same channel is set (Transfer Complete, 
+  *    Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, 
+  *    DMAy_IT_HTx or DMAy_IT_TEx). 
+  *      
+  * @retval The new state of DMAy_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+  {
+    /* DMAy_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMAy_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+  *   This parameter can be any combination (for the same DMA) of the following values:
+  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  *     
+  * @note
+  *    Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other 
+  *    interrupts relative to the same channel (Transfer Complete, Half-transfer 
+  *    Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and 
+  *    DMAy_IT_TEx).  
+  *        
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+  
+  /* Calculate the used DMAy */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->IFCR = DMAy_IT;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->IFCR = DMAy_IT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c
new file mode 100644
index 0000000..885b0f2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c
@@ -0,0 +1,352 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_exti.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:
+  *           + Initialization and Configuration 
+  *           + Interrupts and flags management 
+  *
+  @verbatim
+ ===============================================================================
+                          ##### EXTI features #####
+ ===============================================================================
+    [..] External interrupt/event lines are mapped as following:
+         (#) All available GPIO pins are connected to the 16 external 
+             interrupt/event lines from EXTI0 to EXTI15.
+         (#) EXTI line 16 is connected to the PVD output
+         (#) EXTI line 17 is connected to the RTC Alarm event
+         (#) EXTI line 18 is connected to USB Device wakeup event  
+         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
+         (#) EXTI line 20 is connected to the RTC wakeup event  
+         (#) EXTI line 21 is connected to the Comparator 1 wakeup event 
+         (#) EXTI line 22 is connected to the Comparator 2 wakeup event
+         (#) EXTI line 23 is connected to the I2C1 wakeup event
+         (#) EXTI line 24 is connected to the I2C2 wakeup event  
+         (#) EXTI line 25 is connected to the USART1 wakeup event
+         (#) EXTI line 26 is connected to the USART2 wakeup event  
+         (#) EXTI line 27 is reserved
+         (#) EXTI line 28 is connected to the USART3 wakeup event
+         (#) EXTI line 29 is connected to the Comparator 3 event
+         (#) EXTI line 30 is connected to the Comparator 4 event
+         (#) EXTI line 31 is connected to the Comparator 5 event
+         (#) EXTI line 32 is connected to the Comparator 6 event
+         (#) EXTI line 33 is connected to the Comparator 7 event
+         (#) EXTI line 34 is connected for thr UART4 wakeup event
+         (#) EXTI line 35 is connected for the UART5 wakeup event               
+
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..] In order to use an I/O pin as an external interrupt source, 
+         follow steps below:
+         (#) Configure the I/O in input mode using GPIO_Init().
+         (#) Select the input source pin for the EXTI line using
+             SYSCFG_EXTILineConfig().
+         (#) Select the mode(interrupt, event) and configure the trigger 
+             selection (Rising, falling or both) using EXTI_Init(). For the 
+             internal interrupt, the trigger selection is not needed 
+             (the active edge is always the rising one).
+         (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
+         (#) Optionally, you can generate a software interrupt using the function 
+             EXTI_GenerateSWInterrupt().
+    [..]
+    (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+                
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_exti.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE     ((uint32_t)0x00000)        /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions 
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR    = 0x1F800000;
+  EXTI->EMR    = 0x00000000;
+  EXTI->RTSR   = 0x00000000;
+  EXTI->FTSR   = 0x00000000;
+  EXTI->SWIER  = 0x00000000;
+  EXTI->PR     = 0xE07FFFFF;
+  EXTI->IMR2   = 0x0000000C;
+  EXTI->EMR2   = 0x00000000;
+  EXTI->RTSR2  = 0x00000000;
+  EXTI->FTSR2  = 0x00000000;
+  EXTI->SWIER2 = 0x00000000;
+  EXTI->PR2    = 0x00000003;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  *    EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
+  *    EXTI_Mode specifies which EXTI line is used as interrupt or an event.
+  *    EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
+  *                 pending bit will be set.
+  *    EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 
+  *         contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+  
+
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+      
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */   
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));   
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+     
+    tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+    *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+    
+    tmp = (uint32_t)EXTI_BASE;
+
+    /* Clear Rising Falling edge configuration */
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+    
+      /* Select the trigger for the selected interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+    *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));      
+    }
+    else
+    {
+      tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+      *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+    }
+  }
+      
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+  }
+         
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..20).
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+  *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
+
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief    EXTI Interrupts and flags management functions
+ *
+@verbatim  
+ ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to configure the EXTI Interrupts 
+    sources and check or clear the flags or pending bits status.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..20).
+  * @retval The new state of EXTI_Line (SET or RESET).                  
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+   
+  if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..20).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+  *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));  
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..20).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_Line) >> 5 ) * 0x20) & (uint32_t)(1 << (EXTI_Line & 0x1F));
+ 
+  if ( (((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + (((EXTI_Line) >> 5 ) * 0x20) )) & (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+  
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..20).
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+  
+  *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c
new file mode 100644
index 0000000..3756f79
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c
@@ -0,0 +1,1172 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_flash.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH peripheral:
+  *            + FLASH Interface configuration
+  *            + FLASH Memory Programming
+  *            + Option Bytes Programming
+  *            + Interrupts and flags management
+  *  
+  @verbatim
+  
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..] This driver provides functions to configure and program the FLASH 
+         memory of all STM32F30x devices. These functions are split in 4 groups:
+         (#) FLASH Interface configuration functions: this group includes the
+             management of following features:
+             (++) Set the latency.
+             (++) Enable/Disable the Half Cycle Access.
+             (++) Enable/Disable the prefetch buffer.
+         (#) FLASH Memory Programming functions: this group includes all needed
+             functions to erase and program the main memory:
+             (++) Lock and Unlock the FLASH interface.
+             (++) Erase function: Erase page, erase all pages.
+             (++) Program functions: Half Word and Word write.
+         (#) FLASH Option Bytes Programming functions: this group includes all 
+             needed functions to manage the Option Bytes:
+             (++) Lock and Unlock the Flash Option bytes.
+             (++) Launch the Option Bytes loader
+             (++) Erase the Option Bytes
+             (++) Set/Reset the write protection
+             (++) Set the Read protection Level
+             (++) Program the user option Bytes
+             (++) Set/Reset the BOOT1 bit
+             (++) Enable/Disable the VDDA Analog Monitoring
+             (++) Enable/Disable the SRAM parity
+             (++) Get the user option bytes
+             (++) Get the Write protection
+             (++) Get the read protection status
+         (#) FLASH Interrupts and flags management functions: this group includes 
+             all needed functions to:
+             (++) Enable/Disable the FLASH interrupt sources.
+             (++) Get flags status.
+             (++) Clear flags.
+             (++) Get FLASH operation status.
+             (++) Wait for last FLASH operation.
+ 
+  @endverbatim
+                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_flash.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* FLASH Mask */
+#define RDPRT_MASK                 ((uint32_t)0x00000002)
+#define WRP01_MASK                 ((uint32_t)0x0000FFFF)
+#define WRP23_MASK                 ((uint32_t)0xFFFF0000)
+ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+  *  @brief   FLASH Interface configuration functions 
+ *
+
+@verbatim   
+ ===============================================================================
+            ##### FLASH Interface configuration functions #####
+ ===============================================================================
+    [..] This group includes the following functions:
+         (+) void FLASH_SetLatency(uint32_t FLASH_Latency); 
+         (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);     
+         (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+    [..] The unlock sequence is not needed for these functions.
+ 
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  Sets the code latency value.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  *            @arg FLASH_Latency_1: FLASH One Latency cycle
+  *            @arg FLASH_Latency_2: FLASH Two Latency cycles      
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+   uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+  
+  /* Read the ACR register */
+  tmpreg = FLASH->ACR;  
+  
+  /* Sets the Latency value */
+  tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+  tmpreg |= FLASH_Latency;
+  
+  /* Write the ACR register */
+  FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Half cycle flash access.
+  * @param  FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+  *            @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+  * @retval None
+  */
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_HLFCYA;
+  }
+  else
+  {
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_HLFCYA));
+  }
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param  NewState: new state of the Prefetch Buffer.
+  *          This parameter  can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+  }
+  else
+  {
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ *  @brief   FLASH Memory Programming functions
+ *
+@verbatim   
+ ===============================================================================
+              ##### FLASH Memory Programming functions #####
+ ===============================================================================   
+    [..] This group includes the following functions:
+         (+) void FLASH_Unlock(void);
+         (+) void FLASH_Lock(void);
+         (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+         (+) FLASH_Status FLASH_EraseAllPages(void);
+         (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+         (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+    [..] Any operation of erase or program should follow these steps:
+         (#) Call the FLASH_Unlock() function to enable the FLASH control register 
+             program memory access.
+         (#) Call the desired function to erase page or program data.
+         (#) Call the FLASH_Lock() function to disable the FLASH control register 
+             access (recommended to protect the FLASH memory against possible 
+             unwanted operation).
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH control register access
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+  }  
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+  * @brief  Erases a specified page in program memory.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  * @note   Call the FLASH_Lock() to disable the flash memory access 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)  
+  * @param  Page_Address: The page address in program memory to be erased.
+  * @note   A Page is erased in the Program memory only if the address to load 
+  *         is the start address of a page (multiple of 1024 bytes).  
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+ 
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* If the previous operation is completed, proceed to erase the page */
+    FLASH->CR |= FLASH_CR_PER;
+    FLASH->AR  = Page_Address; 
+    FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    /* Disable the PER Bit */
+    FLASH->CR &= ~FLASH_CR_PER;
+  }
+    
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH pages.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  *         all the FLASH_Lock() to disable the flash memory access 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all pages */
+     FLASH->CR |= FLASH_CR_MER;
+     FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* Disable the MER Bit */
+    FLASH->CR &= ~FLASH_CR_MER;
+  }
+
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_Lock() to disable the flash memory access 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)  
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new first 
+    half word */
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint16_t*)Address = (uint16_t)Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the previous operation is completed, proceed to program the new second 
+      half word */
+      tmp = Address + 2;
+
+      *(__IO uint16_t*) tmp = Data >> 16;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+        
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+    else
+    {
+      /* Disable the PG Bit */
+      FLASH->CR &= ~FLASH_CR_PG;
+    }
+  }
+   
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word at a specified address.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_Lock() to disable the flash memory access 
+  *         (recommended to protect the FLASH memory against possible unwanted operation) 
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new data */
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint16_t*)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    /* Disable the PG Bit */
+    FLASH->CR &= ~FLASH_CR_PG;
+  } 
+  
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ *  @brief   Option Bytes Programming functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Option Bytes Programming functions #####
+ ===============================================================================  
+    [..] This group includes the following functions:
+         (+) void FLASH_OB_Unlock(void);
+         (+) void FLASH_OB_Lock(void);
+         (+) void FLASH_OB_Erase(void);
+         (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+         (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+         (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+         (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+         (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+         (+) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
+         (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);					
+         (+) FLASH_Status FLASH_OB_Launch(void);
+         (+) uint32_t FLASH_OB_GetUser(void);						
+         (+) uint8_t FLASH_OB_GetWRP(void);						
+         (+) uint8_t FLASH_OB_GetRDP(void);							
+    [..] Any operation of erase or program should follow these steps:
+         (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control 
+             register access.
+         (#) Call one or several functions to program the desired Option Bytes:
+             (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); 
+                  => to Enable/Disable the desired sector write protection.
+             (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the 
+                  desired read Protection Level.
+             (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); 
+                  => to configure the user Option Bytes.
+ 	         (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1); 
+                  => to set the boot1 mode
+             (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG); 
+                  => to Enable/Disable the VDDA monotoring.
+             (++) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity); 
+                  => to Enable/Disable the SRAM Parity check.		 
+	         (++) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER); 
+                  => to write all user option bytes: OB_IWDG, OB_STOP, OB_STDBY, 
+                     OB_BOOT1, OB_VDDA_ANALOG and OB_VDD_SD12.  
+         (#) Once all needed Option Bytes to be programmed are correctly written, 
+             call the FLASH_OB_Launch() function to launch the Option Bytes 
+             programming process.
+         (#@) When changing the IWDG mode from HW to SW or from SW to HW, a system 
+              reset is needed to make the change effective.  
+         (#) Call the FLASH_OB_Lock() function to disable the FLASH option control 
+             register access (recommended to protect the Option Bytes against 
+             possible unwanted operations).
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
+  { 
+    /* Unlocking the option bytes block access */
+    FLASH->OPTKEYR = FLASH_OPTKEY1;
+    FLASH->OPTKEYR = FLASH_OPTKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Lock(void)
+{
+  /* Set the OPTWREN Bit to lock the option bytes block access */
+  FLASH->CR &= ~FLASH_CR_OPTWRE;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Launch(void)
+{
+  /* Set the OBL_Launch bit to launch the option byte loading */
+  FLASH->CR |= FLASH_CR_OBL_LAUNCH; 
+}
+
+/**
+  * @brief  Erases the FLASH option bytes.
+  * @note   This functions erases all option bytes except the Read protection (RDP). 
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_Erase(void)
+{
+  uint16_t rdptmp = OB_RDP_Level_0;
+
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Get the actual read protection Option Byte value */ 
+  if(FLASH_OB_GetRDP() != RESET)
+  {
+    rdptmp = 0x00;  
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {   
+    /* If the previous operation is completed, proceed to erase the option bytes */
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+       
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+
+      /* Restore the last read protection Option Byte value */
+      OB->RDP = (uint16_t)rdptmp; 
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else
+    {
+      if (status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }  
+  }
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Write protects the desired pages
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)    
+  * @param  OB_WRP: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  *     @arg  value between OB_WRP_Pages0to35 and OB_WRP_Pages60to63
+  *     @arg OB_WRP_AllPages
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+    
+  OB_WRP = (uint32_t)(~OB_WRP);
+  WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
+  WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTPG;
+
+    if(WRP0_Data != 0xFF)
+    {
+      OB->WRP0 = WRP0_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+    {
+      OB->WRP1 = WRP1_Data;
+      
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+          
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  } 
+  /* Return the write protection operation Status */
+  return status;      
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)   
+  * @param  FLASH_ReadProtection_Level: specifies the read protection level. 
+  *   This parameter can be:
+  *     @arg OB_RDP_Level_0: No protection
+  *     @arg OB_RDP_Level_1: Read protection of the memory                     
+  *     @arg OB_RDP_Level_2: Chip protection
+  *     @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_RDP(OB_RDP));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    FLASH->CR |= FLASH_CR_OPTER;
+    FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status == FLASH_COMPLETE)
+    {
+      /* If the erase operation is completed, disable the OPTER Bit */
+      FLASH->CR &= ~FLASH_CR_OPTER;
+      
+      /* Enable the Option Bytes Programming operation */
+      FLASH->CR |= FLASH_CR_OPTPG;
+       
+      OB->RDP = OB_RDP;
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); 
+    
+      if(status != FLASH_TIMEOUT)
+      {
+        /* if the program operation is completed, disable the OPTPG Bit */
+        FLASH->CR &= ~FLASH_CR_OPTPG;
+      }
+    }
+    else 
+    {
+      if(status != FLASH_TIMEOUT)
+      {
+        /* Disable the OPTER Bit */
+        FLASH->CR &= ~FLASH_CR_OPTER;
+      }
+    }
+  }
+  /* Return the protection operation Status */
+  return status;             
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @param  OB_IWDG: Selects the IWDG mode
+  *   This parameter can be one of the following values:
+  *     @arg OB_IWDG_SW: Software IWDG selected
+  *     @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *     @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, 
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+           
+    OB->USER = (uint8_t)((uint8_t)(OB_IWDG | OB_STOP) | (uint8_t)(OB_STDBY |0xF8));
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the BOOT1. 
+  * @param  OB_BOOT1: Set or Reset the BOOT1.
+  *   This parameter can be one of the following values:
+  *     @arg OB_BOOT1_RESET: BOOT1 Reset
+  *     @arg OB_BOOT1_SET: BOOT1 Set
+  * @retval None
+  */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+           
+	OB->USER = OB_BOOT1|0xEF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the analogue monitoring on VDDA Power source. 
+  * @param  OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+  *   This parameter can be one of the following values:
+  *     @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+  *     @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+  * @retval None
+  */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+           
+	OB->USER = OB_VDDA_ANALOG |0xDF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Sets or resets the SRAM partiy.
+  * @param  OB_SRAM_Parity: Set or Reset the SRAM partiy enable bit.
+  *         This parameter can be one of the following values:
+  *             @arg OB_SRAM_PARITY_SET: Set SRAM partiy.
+  *             @arg OB_SRAM_PARITY_RESET: Reset SRAM partiy.
+  * @retval None
+  */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+
+    OB->USER = OB_SRAM_Parity | 0xBF;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY/ BOOT1 and OB_VDDA_ANALOG.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  * @note   Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)   
+  * @param  OB_USER: Selects all user option bytes
+  *   This parameter is a combination of the following values:
+  *     @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+  *     @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+  *     @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+  *     @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+  *     @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
+  * @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Authorize the small information block programming */
+  FLASH->OPTKEYR = FLASH_KEY1;
+  FLASH->OPTKEYR = FLASH_KEY2;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Enable the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+           
+	  OB->USER = OB_USER | 0x88;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    if(status != FLASH_TIMEOUT)
+    {
+      /* if the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }    
+  /* Return the Option Byte program Status */
+  return status;
+
+}
+
+/**
+  * @brief  Programs a half word at a specified Option Byte Data address.
+  * @note    To correctly run this function, the FLASH_OB_Unlock() function
+  *           must be called before.
+  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *          (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  Address: specifies the address to be programmed.
+  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  /* Check the parameters */
+  assert_param(IS_OB_DATA_ADDRESS(Address));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+  if(status == FLASH_COMPLETE)
+  {
+    /* Enables the Option Bytes Programming operation */
+    FLASH->CR |= FLASH_CR_OPTPG; 
+    *(__IO uint16_t*)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+    if(status != FLASH_TIMEOUT)
+    {
+      /* If the program operation is completed, disable the OPTPG Bit */
+      FLASH->CR &= ~FLASH_CR_OPTPG;
+    }
+  }
+  /* Return the Option Byte Data Program Status */
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval The FLASH User Option Bytes .
+  */
+uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return (uint8_t)(FLASH->OBR >> 8);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value
+  */
+uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET)
+  */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+  
+  if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
+  {
+    readstatus = SET;
+  }
+  else
+  {
+    readstatus = RESET;
+  }
+  return readstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or 
+  *         disabled.
+  *   This parameter can be any combination of the following values:     
+  *     @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+  *     @arg FLASH_IT_ERR: FLASH Error Interrupt 
+  * @retval None 
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *     @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *     @arg FLASH_FLAG_EOP: FLASH End of Programming flag        
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+  *     @arg FLASH_FLAG_EOP: FLASH End of Programming flag                
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status FLASHstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    FLASHstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+    { 
+      FLASHstatus = FLASH_ERROR_WRP;
+    }
+    else 
+    {
+      if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
+      {
+        FLASHstatus = FLASH_ERROR_PROGRAM; 
+      }
+      else
+      {
+        FLASHstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the FLASH Status */
+  return FLASHstatus;
+}
+
+/**
+  * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the FLASH Status */
+  status = FLASH_GetStatus();
+  
+  /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetStatus();
+    Timeout--;
+  }
+  
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c
new file mode 100644
index 0000000..2d81b08
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c
@@ -0,0 +1,1585 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_i2c.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Inter-Integrated circuit (I2C):
+  *           + Initialization and Configuration
+  *           + Communications handling
+  *           + SMBUS management
+  *           + I2C registers management
+  *           + Data transfers management
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+ ============================================================================
+                     ##### How to use this driver #####
+ ============================================================================
+   [..]
+   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+       function for I2C1 or I2C2.
+   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+       RCC_AHBPeriphClockCmd() function. 
+   (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+            Function (AF) using GPIO_PinAFConfig() function.
+       (++) Configure the desired pin in alternate function by:
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, OpenDrain and speed via 
+            GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function.
+   (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address 
+       using the I2C_Init() function.
+   (#) Optionally you can enable/configure the following parameters without
+       re-initialization (i.e there is no need to call again I2C_Init() function):
+       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+       (++) Enable the general call using the I2C_GeneralCallCmd() function.
+       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+       (++) For SMBus Mode: 
+            (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
+   (#) Enable the NVIC and the corresponding interrupt using the function
+       I2C_ITConfig() if you need to use interrupt mode.
+   (#) When using the DMA mode 
+      (++) Configure the DMA using DMA_Init() function.
+      (++) Active the needed channel Request using I2C_DMACmd() function.
+   (#) Enable the I2C using the I2C_Cmd() function.
+   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+       transfers.
+   [..]        
+   (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
+       must be enabled by setting the driving capability control bit in SYSCFG.
+       
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK          ((uint32_t)0x00CFE0FF)  /*<! I2C CR1 clear register Mask */
+#define CR2_CLEAR_MASK          ((uint32_t)0x07FF7FFF)  /*<! I2C CR2 clear register Mask */
+#define TIMING_CLEAR_MASK       ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
+#define ERROR_IT_MASK           ((uint32_t)0x00003F00)  /*<! I2C Error interrupt register Mask */
+#define TC_IT_MASK              ((uint32_t)0x000000C0)  /*<! I2C TC interrupt register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the I2C Mode,
+         I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
+
+    [..] The I2C_Init() function follows the I2C configuration procedures (these procedures 
+         are available in reference manual).
+         
+    [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
+         states machines are reset and communication control bits, as well as status bits come 
+         back to their reset value.
+         
+    [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
+         HSI and Digital filters must be disabled.
+         
+    [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
+         configured using I2C_OwnAddress2Config() function.
+         
+    [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of 
+         each byte in slave mode when NBYTES is set to 0x01. 
+             
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
+  assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+  /* Disable I2Cx Peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear I2Cx CR1 register */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: analog and digital filter */
+  /* Set ANFOFF bit according to I2C_AnalogFilter value */
+  /* Set DFN bits according to I2C_DigitalFilter value */
+  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+  
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+  /*---------------------------- I2Cx TIMING Configuration -------------------*/
+  /* Configure I2Cx: Timing */
+  /* Set TIMINGR bits according to I2C_Timing */
+  /* Write to I2Cx TIMING */
+  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+  /* Enable I2Cx Peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Clear tmpreg local variable */
+  tmpreg = 0;
+  /* Clear OAR1 register */
+  I2Cx->OAR1 = (uint32_t)tmpreg;
+  /* Clear OAR2 register */
+  I2Cx->OAR2 = (uint32_t)tmpreg;
+  /* Configure I2Cx: Own Address1 and acknowledged address */
+  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+  /* Set OA1 bits according to I2C_OwnAddress1 value */
+  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+                      (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+  /* Write to I2Cx OAR1 */
+  I2Cx->OAR1 = tmpreg;
+  /* Enable Own Address1 acknowledgement */
+  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+  /*---------------------------- I2Cx MODE Configuration ---------------------*/
+  /* Configure I2Cx: mode */
+  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+  tmpreg = I2C_InitStruct->I2C_Mode;
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 |= tmpreg;
+
+  /*---------------------------- I2Cx ACK Configuration ----------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear I2Cx CR2 register */
+  tmpreg &= CR2_CLEAR_MASK;
+  /* Configure I2Cx: acknowledgement */
+  /* Set NACK bit according to I2C_Ack value */
+  tmpreg |= I2C_InitStruct->I2C_Ack;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+  /*---------------- Reset I2C init structure parameters values --------------*/
+  /* Initialize the I2C_Timing member */
+  I2C_InitStruct->I2C_Timing = 0;
+  /* Initialize the I2C_AnalogFilter member */
+  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  /* Initialize the I2C_DigitalFilter member */
+  I2C_InitStruct->I2C_DigitalFilter = 0;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Disable peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /* Perform a dummy read to delay the disable of peripheral for minimum
+     3 APB clock cycles to perform the software reset functionality */
+  *(__IO uint32_t *)(uint32_t)I2Cx; 
+
+  /* Enable peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_ERRI: Error interrupt mask
+  *     @arg I2C_IT_TCI: Transfer Complete interrupt mask
+  *     @arg I2C_IT_STOPI: Stop Detection interrupt mask
+  *     @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+  *     @arg I2C_IT_ADDRI: Address Match interrupt mask  
+  *     @arg I2C_IT_RXI: RX interrupt mask
+  *     @arg I2C_IT_TXI: TX interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR1 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable clock stretching */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);    
+  }
+  else
+  {
+    /* Disable clock stretching  */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C wakeup from stop mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx stop mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable wakeup from stop mode */
+    I2Cx->CR1 |= I2C_CR1_WUPEN;   
+  }
+  else
+  {
+    /* Disable wakeup from stop mode */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C own address 2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C own address 2.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable own address 2 */
+    I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+  }
+  else
+  {
+    /* Disable own address 2 */
+    I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+  }
+}    
+
+/**
+  * @brief  Configures the I2C slave own address 2 and mask.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Mask: specifies own address 2 mask to be programmed.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_OA2_NoMask: no mask.
+  *     @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+  *     @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+  *     @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+  *     @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+  *     @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+  *     @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+  *     @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+  * @retval None
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_OWN_ADDRESS2(Address));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+  
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0]  */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+            (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the I2C general call mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C general call mode.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable general call mode */
+    I2Cx->CR1 |= I2C_CR1_GCEN;
+  }
+  else
+  {
+    /* Disable general call mode */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C slave byte control.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C slave byte control.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable slave byte control */
+    I2Cx->CR1 |= I2C_CR1_SBC;
+  }
+  else
+  {
+    /* Disable slave byte control */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+  }
+}
+
+/**
+  * @brief  Configures the slave address to be transmitted after start generation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @note   This function should be called before generating start condition.  
+  * @retval None
+  */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+               
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx SADD bit [9:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}
+  
+/**
+  * @brief  Enables or disables the I2C 10-bit addressing mode for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit addressing mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note   This function should be called before generating start condition.  
+  * @retval None
+  */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit addressing mode */
+    I2Cx->CR2 |= I2C_CR2_ADD10;
+  }
+  else
+  {
+    /* Disable 10-bit addressing mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+  }
+} 
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group2 Communications handling functions
+ *  @brief   Communications handling functions 
+ *
+@verbatim
+ ===============================================================================
+                  ##### Communications handling functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions that handles I2C communication.
+    
+    [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
+         mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
+         
+    [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
+         this configuration should be done before generating start condition in master 
+         mode.
+         
+    [..] When switching from master write operation to read operation in 10Bit addressing
+         mode, master can only sends the 1st 7 bits of the 10 bit address, followed by 
+         Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.        
+         
+    [..] In master mode, when transferring more than 255 bytes Reload mode should be used
+         to handle communication. In the first phase of transfer, Nbytes should be set to 
+         255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
+         function should be called to handle remaining communication.
+         
+    [..] In master mode, when software end mode is selected when all data is transferred
+         TC flag is set I2C_TransferHandling() function should be called to generate STOP
+         or generate ReStart.                      
+             
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the I2C automatic end mode (stop condition is 
+  *         automatically sent when nbytes data are transferred).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C automatic end mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note   This function has effect if Reload mode is disabled.   
+  * @retval None
+  */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto end mode */
+    I2Cx->CR2 |= I2C_CR2_AUTOEND;
+  }
+  else
+  {
+    /* Disable Auto end mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C nbytes reload mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the nbytes reload mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto Reload mode */
+    I2Cx->CR2 |= I2C_CR2_RELOAD;
+  }
+  else
+  {
+    /* Disable Auto Reload mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+  }
+}
+
+/**
+  * @brief  Configures the number of bytes to be transmitted/received.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  * @retval None
+  */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx Nbytes bit [7:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+  /* Set I2Cx Nbytes */
+  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}  
+  
+/**
+  * @brief  Configures the type of transfer request for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Direction: specifies the transfer request direction to be programmed.
+  *    This parameter can be one of the following values:
+  *     @arg I2C_Direction_Transmitter: Master request a write transfer
+  *     @arg I2C_Direction_Receiver: Master request a read transfer 
+  * @retval None
+  */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction == I2C_Direction_Transmitter)
+  {
+    /* Request a write Transfer */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+  }
+  else
+  {
+    /* Request a read Transfer */
+    I2Cx->CR2 |= I2C_CR2_RD_WRN;
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR2 |= I2C_CR2_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR2 |= I2C_CR2_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the I2C 10-bit header only mode with read direction.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit header only mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note   This mode can be used only when switching from master transmitter mode 
+  *         to master receiver mode.        
+  * @retval None
+  */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit header only mode */
+    I2Cx->CR2 |= I2C_CR2_HEAD10R;
+  }
+  else
+  {
+    /* Disable 10-bit header only mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+  }
+}    
+
+/**
+  * @brief  Generates I2C communication Acknowledge.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the Acknowledge.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable ACK generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);    
+  }
+  else
+  {
+    /* Enable NACK generation */
+    I2Cx->CR2 |= I2C_CR2_NACK;
+  }
+}
+
+/**
+  * @brief  Returns the I2C slave matched address .
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the slave matched address .
+  */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+  * @brief  Returns the I2C slave received request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received request.
+  */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+  uint32_t tmpreg = 0;
+  uint16_t direction = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+  
+  /* If write transfer is requested */
+  if (tmpreg == 0)
+  {
+    /* write transfer is requested */
+    direction = I2C_Direction_Transmitter;
+  }
+  else
+  {
+    /* Read transfer is requested */
+    direction = I2C_Direction_Receiver;
+  }  
+  return direction;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  ReloadEndMode: new state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Reload_Mode: Enable Reload mode .
+  *     @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+  *     @arg I2C_SoftEnd_Mode: Enable Software end mode.
+  * @param  StartStopMode: new state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_No_StartStop: Don't Generate stop and start condition.
+  *     @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+  *     @arg I2C_Generate_Start_Read: Generate Restart for read request.
+  *     @arg I2C_Generate_Start_Write: Generate Restart for write request.
+  * @retval None
+  */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));  
+  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+  assert_param(IS_START_STOP_MODE(StartStopMode));
+    
+  /* Get the CR2 register value */
+  tmpreg = I2Cx->CR2;
+  
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+  
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+            (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+  
+  /* update CR2 register */
+  I2Cx->CR2 = tmpreg;  
+}  
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group3 SMBUS management functions
+ *  @brief   SMBUS management functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### SMBUS management functions #####
+ ===============================================================================   
+    [..] This section provides a set of functions that handles SMBus communication
+         and timeouts detection.
+    
+    [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusDevice.
+         
+    [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusHost.         
+         
+    [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
+         function.
+         
+    [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be 
+         configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() 
+         function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
+         the detection.
+         
+    [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
+         function followed by the call of I2C_ClockTimeoutCmd(). When adding to this 
+         procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition 
+         (both SCL and SDA high) is detected also.                
+                          
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables I2C SMBus alert.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx SMBus alert.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable SMBus alert */
+    I2Cx->CR1 |= I2C_CR1_ALERTEN;   
+  }
+  else
+  {
+    /* Disable SMBus alert */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Clock Timeout (SCL Timeout detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx clock Timeout.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Extended clock Timeout.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA 
+  *         high detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Idle clock Timeout.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); 
+  }
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus 
+  *   idle SCL and SDA high when TIDLE = 1).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutA to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+    
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTA bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+  /* Set I2Cx TIMEOUTA */
+  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutB to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTB bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+  /* Set I2Cx TIMEOUTB */
+  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables I2C PEC calculation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_PECEN;   
+  }
+  else
+  {
+    /* Disable PEC calculation */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C PEC transmission/reception request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC transmission/reception request */
+    I2Cx->CR1 |= I2C_CR2_PECBYTE;   
+  }
+  else
+  {
+    /* Disable PEC transmission/reception request */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); 
+  }
+}
+
+/**
+  * @brief  Returns the I2C PEC.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the PEC .
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+  * @}
+  */  
+  
+  
+/** @defgroup I2C_Group4 I2C registers management functions
+ *  @brief   I2C registers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### I2C registers management functions #####
+ ===============================================================================  
+    [..] This section provides a functions that allow user the management of 
+         I2C registers.
+         
+@endverbatim
+  * @{
+  */
+
+  /**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Register: specifies the register to read.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Register_CR1: CR1 register.
+  *     @arg I2C_Register_CR2: CR2 register.
+  *     @arg I2C_Register_OAR1: OAR1 register.
+  *     @arg I2C_Register_OAR2: OAR2 register.
+  *     @arg I2C_Register_TIMINGR: TIMING register.
+  *     @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+  *     @arg I2C_Register_ISR: ISR register.
+  *     @arg I2C_Register_ICR: ICR register.
+  *     @arg I2C_Register_PECR: PECR register.
+  *     @arg I2C_Register_RXDR: RXDR register.
+  *     @arg I2C_Register_TXDR: TXDR register.
+  * @retval The value of the read register.
+  */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t)I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @}
+  */  
+  
+/** @defgroup I2C_Group5 Data transfers management functions
+ *  @brief   Data transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### Data transfers management functions #####
+ =============================================================================== 
+    [..] This subsection provides a set of functions allowing to manage 
+         the I2C data transfers.
+         
+    [..] The read access of the I2C_RXDR register can be done using 
+         the I2C_ReceiveData() function and returns the received value.
+         Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
+         function and stores the written data into TXDR.
+@endverbatim
+  * @{
+  */  
+  
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Write in the DR register the data to be sent */
+  I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->RXDR;
+}  
+
+/**
+  * @}
+  */ 
+  
+  
+/** @defgroup I2C_Group6 DMA transfers management functions
+ *  @brief   DMA transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================  
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel 
+         requests:
+         (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+@endverbatim
+  * @{
+  */  
+    
+/**
+  * @brief  Enables or disables the I2C DMA interface.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_DMAReq_Tx: Tx DMA transfer request
+  *     @arg I2C_DMAReq_Rx: Rx DMA transfer request
+  * @param  NewState: new state of the selected I2C DMA transfer request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR1 |= I2C_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+  }
+}
+/**
+  * @}
+  */  
+
+
+/** @defgroup I2C_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions  #####
+ =============================================================================== 
+    [..] This section provides functions allowing to configure the I2C Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) .
+
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the I2C communication can be managed by 15 flags:
+        (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
+        (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
+        (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
+        (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
+        (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
+        (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+        (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+    [..]
+        (@)Do not use the BUSY flag to handle each data transmission or reception.It is 
+           better to use the TXIS and RXNE flags instead.
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
+         and 15 pending bits: 
+    [..] Interrupt Source:
+        (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
+        (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
+        (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
+        (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
+        (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.  
+        (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
+        (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
+
+    [..] Pending Bits:
+        (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
+        (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
+        (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_IT_BERR: to indicate the status of Bus error flag.
+        (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
+
+    [..] In this Mode it is advised to use the following functions:
+         (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+         (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+@endverbatim
+  * @{
+  */  
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FLAG_TXE: Transmit data register empty
+  *     @arg I2C_FLAG_TXIS: Transmit interrupt status
+  *     @arg I2C_FLAG_RXNE: Receive data register not empty
+  *     @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *     @arg I2C_FLAG_NACKF: NACK received flag
+  *     @arg I2C_FLAG_STOPF: STOP detection flag
+  *     @arg I2C_FLAG_TC: Transfer complete (master mode)
+  *     @arg I2C_FLAG_TCR: Transfer complete reload
+  *     @arg I2C_FLAG_BERR: Bus error
+  *     @arg I2C_FLAG_ARLO: Arbitration lost
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun
+  *     @arg I2C_FLAG_PECERR: PEC error in reception
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *     @arg I2C_FLAG_ALERT: SMBus Alert
+  *     @arg I2C_FLAG_BUSY: Bus busy
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t tmpreg = 0;
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+  
+  /* Get flag status */
+  tmpreg &= I2C_FLAG;
+  
+  if(tmpreg != 0)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}  
+  
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *     @arg I2C_FLAG_NACKF: NACK received flag
+  *     @arg I2C_FLAG_STOPF: STOP detection flag
+  *     @arg I2C_FLAG_BERR: Bus error
+  *     @arg I2C_FLAG_ARLO: Arbitration lost
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun
+  *     @arg I2C_FLAG_PECERR: PEC error in reception
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *     @arg I2C_FLAG_ALERT: SMBus Alert
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_FLAG;
+  }
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_IT_TXIS: Transmit interrupt status
+  *     @arg I2C_IT_RXNE: Receive data register not empty
+  *     @arg I2C_IT_ADDR: Address matched (slave mode)
+  *     @arg I2C_IT_NACKF: NACK received flag
+  *     @arg I2C_IT_STOPF: STOP detection flag
+  *     @arg I2C_IT_TC: Transfer complete (master mode)
+  *     @arg I2C_IT_TCR: Transfer complete reload
+  *     @arg I2C_IT_BERR: Bus error
+  *     @arg I2C_IT_ARLO: Arbitration lost
+  *     @arg I2C_IT_OVR: Overrun/Underrun
+  *     @arg I2C_IT_PECERR: PEC error in reception
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *     @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t tmpreg = 0;
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  /* If Error interrupt */
+  if((uint32_t)(I2C_IT & ERROR_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+  }
+  /* If TC interrupt */
+  else if((uint32_t)(I2C_IT & TC_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+  }
+  else
+  {
+    enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+  }
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+
+  /* Get flag status */
+  tmpreg &= I2C_IT;
+
+  /* Check the status of the specified I2C flag */
+  if((tmpreg != RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_IT status */
+  return bitstatus;
+}
+  
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_ADDR: Address matched (slave mode)
+  *     @arg I2C_IT_NACKF: NACK received flag
+  *     @arg I2C_IT_STOPF: STOP detection flag
+  *     @arg I2C_IT_BERR: Bus error
+  *     @arg I2C_IT_ARLO: Arbitration lost
+  *     @arg I2C_IT_OVR: Overrun/Underrun
+  *     @arg I2C_IT_PECERR: PEC error in reception
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *     @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_IT;
+}
+
+/**
+  * @}
+  */  
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c
new file mode 100644
index 0000000..10d6c15
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c
@@ -0,0 +1,575 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_opamp.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral: 
+  *           + OPAMP Configuration
+  *           + OPAMP calibration
+  *
+  @verbatim
+  
+  ==============================================================================
+                        ##### OPAMP Peripheral Features #####
+  ==============================================================================
+                   
+  [..]
+      The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
+              
+      (+) The OPAMPs non inverting input can be selected among the list shown by
+          table below.
+  
+      (+) The OPAMPs inverting input can be selected among the list shown by
+          table below.
+  
+      (+) The OPAMPs outputs can be internally connected to the inverting input 
+          (follower mode)
+      (+) The OPAMPs outputs can be internally connected to resistor feedback
+          output (Programmable Gain Amplifier mode)
+  
+      (+) The OPAMPs outputs can be internally connected to ADC
+  
+      (+) The OPAMPs can be calibrated to compensate the offset compensation
+  
+      (+) Timer-controlled Mux for automatic switch of inverting and
+          non-inverting input
+  
+  OPAMPs inverting/non-inverting inputs:
+    +--------------------------------------------------------------+     
+    |                 |        | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+    |-----------------|--------|--------|--------|--------|--------|
+    |                 | PGA    |  OK    |  OK    |  OK    |  OK    |
+    | Inverting Input | Vout   |  OK    |  OK    |  OK    |  OK    |
+    |                 | IO1    |  PC5   |  PC5   |  PB10  |  PB10  |
+    |                 | IO2    |  PA3   |  PA5   |  PB2   |  PD8   |
+    |-----------------|--------|--------|--------|--------|--------|
+    |                 | IO1    |  PA7   |  PD14  |  PB13  |  PD11  |
+    |  Non Inverting  | IO2    |  PA5   |  PB14  |  PA5   |  PB11  |
+    |    Input        | IO3    |  PA3   |  PB0   |  PA1   |  PA4   |
+    |                 | IO4    |  PA1   |  PA7   |  PB0   |  PB13  |
+    +--------------------------------------------------------------+  
+  
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  This driver provides functions to configure and program the OPAMP 
+  of all STM32F30x devices.
+  
+  To use the OPAMP, perform the following steps:
+ 
+  (#) Enable the SYSCFG APB clock to get write access to OPAMP
+      register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+  (#) Configure the OPAMP input in analog mode using GPIO_Init()
+  
+  (#) Configure the OPAMP using OPAMP_Init() function:
+      (++) Select the inverting input
+      (++) Select the non-inverting inverting input
+    
+  (#) Enable the OPAMP using OPAMP_Cmd() function
+    
+  @endverbatim
+      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_opamp.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup OPAMP 
+  * @brief OPAMP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define OPAMP_CSR_DEFAULT_MASK                    ((uint32_t)0xFFFFFF93)
+#define OPAMP_CSR_TIMERMUX_MASK                   ((uint32_t)0xFFFFF8FF)
+#define OPAMP_CSR_TRIMMING_MASK                   ((uint32_t)0x0000001F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup OPAMP_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes OPAMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the OPAMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  None
+  * @retval None
+  */
+void OPAMP_DeInit(uint32_t OPAMP_Selection)
+{
+  /*!< Set OPAMP_CSR register to reset value */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
+}
+
+/**
+  * @brief  Initializes the OPAMP peripheral according to the specified parameters
+  *         in OPAMP_InitStruct
+  * @note   If the selected OPAMP is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains 
+  *         the configuration information for the specified OPAMP peripheral.
+  *           - OPAMP_InvertingInput specifies the inverting input of OPAMP
+  *           - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+  * @retval None
+  */
+void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+  assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+  /*!< Get the OPAMPx_CSR register value */
+  tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+  /*!< Clear the inverting and non inverting bits selection bits */
+  tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
+
+  /*!< Configure OPAMP: inverting and non inverting inputs */
+  tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
+
+  /*!< Write to OPAMPx_CSR register */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+  * @brief  Fills each OPAMP_InitStruct member with its default value.
+  * @param  OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+  OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
+  OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
+}
+
+/**
+  * @brief  Configure the feedback resistor gain.
+  * @note   If the selected OPAMP is locked, gain configuration can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  NewState: new state of the OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
+  assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
+
+  /* Reset the configuration bits */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
+
+  /* Set the new configuration */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
+}
+
+/**
+  * @brief  Configure the OPAMP's internal reference.
+  * @note   This feature is used when calibration enabled or OPAMP's reference
+  *         connected to the non inverting input.
+  * @note   If the selected OPAMP is locked, Vref configuration can't be performed.
+  *         To unlock the configuration, perform a system reset.  
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  OPAMP_Vref: This parameter can be:
+  *           OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
+  *           OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
+  *           OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
+  *           OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
+  * @retval None
+  */
+void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_VREF(OPAMP_Vref));
+
+  /*!< Get the OPAMPx_CSR register value */
+  tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+  /*!< Clear the CALSEL bits */
+  tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
+
+  /*!< Configure OPAMP reference */
+  tmpreg |= (uint32_t)(OPAMP_Vref);
+
+  /*!< Write to OPAMPx_CSR register */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+  * @brief  Connnect the internal reference to the OPAMP's non inverting input.
+  * @note   If the selected OPAMP is locked, Vref configuration can't be performed.
+  *         To unlock the configuration, perform a system reset.  
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  NewState: new state of the OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Connnect the internal reference to the OPAMP's non inverting input */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
+  }
+  else
+  {
+    /* Disconnnect the internal reference to the OPAMP's non inverting input */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
+  }
+}
+
+/**
+  * @brief  Enables or disables connecting the OPAMP's internal reference to ADC.
+  * @note   If the selected OPAMP is locked, Vref connection can't be performed.
+  *         To unlock the configuration, perform a system reset.  
+  * @param  NewState: new state of the Vrefint output.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable output internal reference */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
+  }
+  else
+  {
+    /* Disable output internal reference */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
+  }
+}
+
+/**
+  * @brief  Configure the OPAMP peripheral (secondary inputs) for timer-controlled
+  *          mux mode according to the specified parameters in OPAMP_InitStruct.
+  * @note   If the selected OPAMP is locked, timer-controlled mux configuration
+  *         can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains 
+  *         the configuration information for the specified OPAMP peripheral.
+  *           - OPAMP_InvertingInput specifies the inverting input of OPAMP
+  *           - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+  * @note   PGA and Vout can't be selected as seconadry inverting input.
+  * @retval None
+  */
+void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+  assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+  /*!< Get the OPAMPx_CSR register value */
+  tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+  /*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
+  tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
+
+  /*!< Configure OPAMP: secondary inverting and non inverting inputs */
+  tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
+
+  /*!< Write to OPAMPx_CSR register */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+  * @brief  Enable or disable the timer-controlled mux mode.
+  * @note   If the selected OPAMP is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  NewState: new state of the OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the timer-controlled Mux mode */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
+  }
+  else
+  {
+    /* Disable the timer-controlled Mux mode */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
+  }
+}
+
+/**
+  * @brief  Enable or disable the OPAMP peripheral.
+  * @note   If the selected OPAMP is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  NewState: new state of the OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected OPAMPx peripheral */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
+  }
+  else
+  {
+    /* Disable the selected OPAMPx peripheral */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) during calibration of the selected OPAMP. 
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  *           - OPAMP output is low when the non-inverting input is at a lower
+  *             voltage than the inverting input
+  *           - OPAMP output is high when the non-inverting input is at a higher
+  *             voltage than the inverting input
+  * @note OPAMP ouput level is provided only during calibration phase.
+  * @retval Returns the selected OPAMP output level: low or high.
+  *       
+  */
+uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
+{
+  uint32_t opampout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+
+  /* Check if selected OPAMP output is high */
+  if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
+  {
+    opampout = OPAMP_OutputLevel_High;
+  }
+  else
+  {
+    opampout = OPAMP_OutputLevel_Low;
+  }
+
+  /* Return the OPAMP output level */
+  return (uint32_t)(opampout);
+}
+
+/**
+  * @brief  Select the trimming mode.
+  * @param  OffsetTrimming: the selected offset trimming mode. 
+  *   This parameter  can be one of the following values:
+  *     @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
+  *                                  calibration
+  *     @arg OPAMP_Trimming_User: user trimming values are used for offset
+  *                               calibration
+  * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
+  *       function or OPAMP_OffsetTrimLowPowerConfig() function to adjust 
+  *       trimming value.
+  * @retval None
+  */
+void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
+
+  /* Reset USERTRIM bit */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
+
+  /* Select trimming mode */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
+}
+
+/**
+  * @brief  Configure the trimming value of the OPAMP.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  OPAMP_Input: the selected OPAMP input. 
+  *   This parameter can be one of the following values:
+  *         @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
+  *         @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
+  * @param  OPAMP_TrimValue: the trimming value. This parameter can be any value lower
+  *         or equal to 0x0000001F. 
+  * @retval None
+  */
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_INPUT(OPAMP_Input));
+  assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
+
+  /*!< Get the OPAMPx_CSR register value */
+  tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+  /*!< Clear the trimming bits */
+  tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<<OPAMP_Input));
+
+  /*!< Configure the new trimming value */
+  tmpreg |= (uint32_t)(OPAMP_TrimValue<<OPAMP_Input);
+
+  /*!< Write to OPAMPx_CSR register */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+  * @brief  Start or stop the calibration of selected OPAMP peripheral.
+  * @note   If the selected OPAMP is locked, start/stop can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @param  NewState: new state of the OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Start the OPAMPx calibration */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_CALON);
+  }
+  else
+  {
+    /* Stop the OPAMPx calibration */
+    *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_CALON);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_Group2 OPAMP configuration locking function
+ *  @brief   OPAMP1,...OPAMP4 configuration locking function
+ *           OPAMP1,...OPAMP4 configuration can be locked each separately.
+ *           Unlocking is performed by system reset.
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Configuration Lock function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected OPAMP configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the OPAMP configuration, perform a system reset.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *          This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+  *          to select the OPAMP peripheral.
+  * @retval None
+  */
+void OPAMP_LockConfig(uint32_t OPAMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+
+  /* Set the lock bit corresponding to selected OPAMP */
+  *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_LOCK);
+}
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c
new file mode 100644
index 0000000..7ab2dcc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c
@@ -0,0 +1,2598 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_rtc.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A and Alarm B) configuration
+  *           + WakeUp Timer configuration
+  *           + Daylight Saving configuration
+  *           + Output pin Configuration
+  *           + Smooth digital Calibration configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + Output Type Config configuration
+  *           + Shift control synchronisation  
+  *           + Interrupts and flags management       
+  *                     
+  @verbatim
+       
+ ===============================================================================     
+                          ##### RTC Operating Condition #####
+ ===============================================================================
+    [..] The real-time clock (RTC) and the RTC backup registers can be powered
+         from the VBAT voltage when the main VDD supply is powered off.
+         To retain the content of the RTC backup registers and supply the RTC 
+         when VDD is turned off, VBAT pin can be connected to an optional
+         standby voltage supplied by a battery or by another source.
+  
+    [..] To allow the RTC to operate even when the main digital supply (VDD) 
+         is turned off, the VBAT pin powers the following blocks:
+           (#) The RTC
+           (#) The LSE oscillator
+           (#) PC13 to PC15 I/Os (when available)
+  
+    [..] When the backup domain is supplied by VDD (analog switch connected 
+         to VDD), the following functions are available:
+           (#) PC14 and PC15 can be used as either GPIO or LSE pins
+           (#) PC13 can be used as a GPIO or as the RTC_AF pin
+  
+    [..] When the backup domain is supplied by VBAT (analog switch connected 
+         to VBAT because VDD is not present), the following functions are available:
+           (#) PC14 and PC15 can be used as LSE pins only
+           (#) PC13 can be used as the RTC_AF pin 
+
+                        ##### Backup Domain Reset #####
+ ===============================================================================
+    [..] The backup domain reset sets all RTC registers and the RCC_BDCR 
+         register to their reset values. 
+         A backup domain reset is generated when one of the following events
+         occurs:
+           (#) Software reset, triggered by setting the BDRST bit in the 
+               RCC Backup domain control register (RCC_BDCR). You can use the
+               RCC_BackupResetCmd().
+           (#) VDD or VBAT power on, if both supplies have previously been
+               powered off.
+                         
+                        ##### Backup Domain Access #####
+ ===============================================================================
+    [..] After reset, the backup domain (RTC registers and RTC backup data 
+         registers) is protected against possible unwanted write accesses. 
+    [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
+         (#) Enable the Power Controller (PWR) APB1 interface clock using the
+             RCC_APB1PeriphClockCmd() function.
+         (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
+         (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+         (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+              
+                         ##### How to use this driver #####
+ ===============================================================================
+    [..]     
+        (+) Enable the backup domain access (see description in the section above)
+         (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
+             RTC hour format using the RTC_Init() function.
+                
+    *** Time and Date configuration ***
+    ===================================    
+    [..]     
+         (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+             and RTC_SetDate() functions.
+         (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+             functions.
+         (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
+         (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+             hour to the RTC Calendar.    
+                
+    *** Alarm configuration ***
+    ===========================    
+    [..]
+         (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+         (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function.
+         (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+         (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+              
+    *** RTC Wakeup configuration ***
+    ================================    
+    [..]
+         (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+             function.
+         (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+             function  
+         (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+         (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+             function.
+                
+    *** Outputs configuration ***
+    =============================  
+    [..] The RTC has 2 different outputs:
+         (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+             and WaKeUp signals.          
+             To output the selected RTC signal on RTC_AF pin, use the 
+             RTC_OutputConfig() function.                
+         (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
+             To output the RTC Clock on RTC_AF pin, use the RTC_CalibOutputCmd()
+             function.                
+                
+    *** Smooth digital Calibration configuration ***
+    ================================================    
+    [..]
+         (+) Configure the RTC Original Digital Calibration Value and the corresponding
+             calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() 
+             function.                                                       
+                
+    *** TimeStamp configuration ***
+    ===============================    
+    [..]
+         (+) Configure the RTC_AF trigger and enables the RTC TimeStamp 
+             using the RTC_TimeStampCmd() function.
+         (+) To read the RTC TimeStamp Time and Date register, use the 
+             RTC_GetTimeStamp() function.
+         (+) To read the RTC TimeStamp SubSecond register, use the 
+             RTC_GetTimeStampSubSecond() function.    
+
+    *** Tamper configuration ***
+    ============================    
+    [..]
+         (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+             function. 
+         (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+             filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
+         (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+             function.
+         (+) Configure the Tamper precharge or discharge duration using 
+             RTC_TamperPinsPrechargeDuration() function.
+         (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+         (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+         (+) Enable the Time stamp on Tamper detection event using  
+             RTC_TSOnTamperDetecCmd() function.     
+
+    *** Backup Data Registers configuration ***
+    ===========================================    
+    [..]
+         (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+             function.  
+         (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+             function.  
+                                  
+                         ##### RTC and low power modes #####
+ =============================================================================== 
+    [..] The MCU can be woken up from a low power mode by an RTC alternate 
+         function.
+    [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+         RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+         These RTC alternate functions can wake up the system from the Stop 
+         and Standby lowpower modes.
+         The system can also wake up from low power modes without depending 
+         on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+         or the RTC wakeup events.
+    [..] The RTC provides a programmable time base for waking up from the 
+         Stop or Standby mode at regular intervals.
+         Wakeup from STOP and Standby modes is possible only when the RTC 
+         clock source is LSE or LSI.
+           
+                ##### Selection of RTC_AF alternate functions #####
+ ===============================================================================
+    [..] The RTC_AF pin (PC13) can be used for the following purposes:
+         (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
+         (+) AFO_ALARM output      
+         (+) AFO_CALIB output
+         (+) AFI_TAMPER
+         (+) AFI_TIMESTAMP
+                         
+ +------------------------------------------------------------------------------------------+
+ |     Pin         |RTC ALARM |RTC CALIB |RTC TAMPER |RTC TIMESTAMP |PC13MODE|  PC13VALUE   |
+ |  configuration  | OUTPUT   | OUTPUT   |  INPUT    |    INPUT     |  bit   |     bit      |
+ |  and function   | ENABLED  | ENABLED  | ENABLED   |   ENABLED    |        |              |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |   Alarm out     |          |          |           |              | Don't  |              |
+ |   output OD     |     1    |Don't care|Don't care | Don't care   | care   |      0       |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |   Alarm out     |          |          |           |              | Don't  |              |
+ |   output PP     |     1    |Don't care|Don't care | Don't care   | care   |      1       |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | Calibration out |          |          |           |              | Don't  |              |
+ |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |  TAMPER input   |          |          |           |              | Don't  |              |
+ |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |  TIMESTAMP and  |          |          |           |              | Don't  |              |
+ |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
+ |   floating      |          |          |           |              |        |              |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ | TIMESTAMP input |          |          |           |              | Don't  |              |
+ |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |   Output PP     |     0    |    0     |     0     |      0       |   1    | PC13 output  |
+ |    Forced       |          |          |           |              |        |              |
+ |-----------------|----------|----------|-----------|--------------|--------|--------------|
+ |  Wakeup Pin or  |     0    |    0     |     0     |      0       |   0    | Don't care   |
+ |  Standard GPIO  |          |          |           |              |        |              |
+ +------------------------------------------------------------------------------------------+
+    
+  @endverbatim
+                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+                                            RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
+                                            RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00002000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00002000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..] This section provide functions allowing to initialize and configure the RTC
+         Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+         Write protection, enter and exit the RTC initialization mode, RTC registers
+         synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
+             split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the 
+                  asynchronous prescaler to a high value to minimize consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To Configure the RTC Calendar, user application should enter initialization
+             mode. In this mode, the calendar counter is stopped and its value 
+             can be updated. When the initialization sequence is complete, the 
+             calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar 
+             initialization, calendar update or after wakeup from low power modes 
+             the software must first clear the RSF flag. The software must then 
+             wait until it is set again before reading the calendar, which means 
+             that the calendar registers have been correctly copied into the RTC_TR 
+             and RTC_DR shadow registers. The RTC_WaitForSynchro() function 
+             implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR = (uint32_t)0x00000000;
+    RTC->DR = (uint32_t)0x00002101;
+    
+    /* Reset All CR bits except CR[2:0] */
+    RTC->CR &= (uint32_t)0x00000007;
+  
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Reset all RTC CR register bits */
+      RTC->CR        &= (uint32_t)0x00000000;
+      RTC->WUTR      = (uint32_t)0x0000FFFF;
+      RTC->PRER      = (uint32_t)0x007F00FF;
+      RTC->ALRMAR    = (uint32_t)0x00000000;
+      RTC->ALRMBR    = (uint32_t)0x00000000;
+      RTC->SHIFTR    = (uint32_t)0x00000000;
+      RTC->CALR       = (uint32_t)0x00000000;
+      RTC->ALRMASSR  = (uint32_t)0x00000000;
+      RTC->ALRMBSSR  = (uint32_t)0x00000000;
+
+      /* Reset ISR register and exit initialization mode */
+      RTC->ISR = (uint32_t)0x00000000;
+      
+      /* Reset Tamper and alternate functions configuration register */
+      RTC->TAFCR = 0x00000000;
+      
+      /* Wait till the RTC RSF flag is set */
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+  
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized  
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+  
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;    
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+    
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;   
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;    
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode  
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+     
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }        
+  }
+  else
+  {
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
+  {
+    /* Bypass shadow mode */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+    
+    /* Clear RSF flag */
+    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    
+    /* Wait the registers to be synchronised */
+    do
+    {
+      synchrostatus = RTC->ISR & RTC_ISR_RSF;
+      synchrocounter++;  
+    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;
+  } 
+  
+  return (status);
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;   
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;    
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Time and Date configuration functions #####
+ ===============================================================================  
+    [..] This section provide functions allowing to program and read the RTC Calendar
+         (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format 
+  *     @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.     
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }  
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  }  
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format 
+  *     @arg RTC_Format_BCD:  BCD data format
+  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.     
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);   
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+  
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format 
+  *     @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format 
+  *     @arg RTC_Format_BCD: BCD data format
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+        ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to program and read the RTC Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format 
+  *     @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.     
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  } 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    RTC->ALRMAR = (uint32_t)tmpreg;
+  }
+  else
+  {
+    RTC->ALRMBR = (uint32_t)tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;   
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format 
+  *     @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)(RTC->ALRMAR);
+  }
+  else
+  {
+    tmpreg = (uint32_t)(RTC->ALRMBR);
+  }
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B  
+  * @param  NewState: new state of the specified alarm.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Configures the RTC AlarmA/B Subseconds value and mask.
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *   This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_AlarmSubSecondMask_All    : All Alarm SS fields are masked.
+  *                                          There is no comparison on sub seconds for Alarm.
+  *     @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
+  *                                          Only SS[0] is compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
+  *                                          Only SS[1:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
+  *                                          Only SS[2:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
+  *                                          Only SS[3:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
+  *                                          Only SS[4:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
+  *                                          Only SS[5:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
+  *                                          Only SS[6:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
+  *                                          Only SS[7:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
+  *                                          Only SS[8:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                          Only SS[9:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                          Only SS[10:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                          Only SS[11:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                          Only SS[12:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14   : SS[14] is don't care in Alarm comparison.
+  *                                          Only SS[13:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_None   : SS[14:0] are compared and must match
+  *                                          to activate alarm
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+  
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    /* Configure the AlarmA SubSecond register */
+    RTC->ALRMASSR = tmpreg;
+  }
+  else
+  {
+    /* Configure the Alarm B SubSecond register */
+    RTC->ALRMBSSR = tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  } 
+  
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### WakeUp Timer configuration functions #####
+ ===============================================================================  
+    [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
+  *     @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
+  *     @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
+  *     @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
+  *     @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
+  *     @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the RTC Wakeup counter.
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
+  *   This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC WakeUp timer counter value.
+  * @param  None
+  * @retval The RTC WakeUp Counter value.
+  */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Enables or Disables the RTC WakeUp timer.
+  * @param  NewState: new state of the WakeUp timer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Daylight Saving configuration functions #####
+ ===============================================================================  
+    [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *     @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                            in CR register to store the operation.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_StoreOperation_Reset: BCK Bit Reset
+  *     @arg RTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Output pin Configuration function #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Output_Disable: No output selected
+  *     @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+  *     @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
+  *     @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *   This parameter can be one of the following:
+  *     @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  *     @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ *  @brief   Digital Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Digital Calibration configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative 
+  *         pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  { 
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput : Select the Calibration output Selection .
+  *   This parameter can be one of the following values:
+  *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *     @arg RTC_CalibOutput_1Hz  : A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
+  *   This parameter can be can be one of the following values:
+  *     @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
+  *     @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
+  *     @arg RTC_SmoothCalibPeriod_8sec  : The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_SmoothCalibPlusPulses_Set  : Add one RTCCLK puls every 2**11 pulses.
+  *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *   This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### TimeStamp configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *   This parameter can be one of the following:
+  *     @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                    edge of the related pin.
+  *     @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                     falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Gets the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format 
+  *     @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Gets the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Tampers configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Tamper_1: Select Tamper 1.
+  *     @arg RTC_Tamper_2: Select Tamper 2.
+  *     @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *                            stimulates tamper event. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ 
+  /* Check if the  active level for Tamper is rising edge (Low level)*/
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Tamper_1: Select Tamper 1.
+  *     @arg RTC_Tamper_2: Select Tamper 2.
+  *     @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                    samples at the active level 
+  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                    samples at the active level
+  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                    samples at the active level 
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 32768
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 16384
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 8192
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 4096
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 2048
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 1024
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 512  
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
+  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+          ##### Backup Data Registers configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 Output Type Config configuration functions
+ *  @brief   Output Type Config configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+            ##### Output Type Config configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *     @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Shift control synchronisation functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+  *   This parameter can be one of the following values :
+  *     @arg RTC_ShiftAdd1S_Set  : Add one second to the clock calendar. 
+  *     @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+    
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+                ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..] All RTC interrupts are connected to the EXTI controller.
+         (+) To enable the RTC Alarm interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 17 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B)
+                  using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+         (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 20 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using
+                  the NVIC_Init() function.
+             (++) Configure the RTC to generate the RTC wakeup timer event using the 
+                  RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() 
+                  functions.
+         (+) To enable the RTC Tamper interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to detect the RTC tamper event using the 
+                  RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+         (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to detect the RTC time-stamp event using the 
+                  RTC_TimeStampCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_TS:  Time Stamp interrupt mask
+  *     @arg RTC_IT_WUT:  WakeUp Timer interrupt mask
+  *     @arg RTC_IT_ALRB:  Alarm B interrupt mask
+  *     @arg RTC_IT_ALRA:  Alarm A interrupt mask
+  *     @arg RTC_IT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified RTC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_FLAG_RECALPF: RECALPF event flag
+  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag   
+  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *     @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+  *     @arg RTC_FLAG_TSF: Time Stamp event flag
+  *     @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *     @arg RTC_FLAG_ALRBF: Alarm B flag
+  *     @arg RTC_FLAG_ALRAF: Alarm A flag
+  *     @arg RTC_FLAG_INITF: Initialization mode flag
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *     @arg RTC_FLAG_INITS: Registers Configured flag
+  *     @argRTC_FLAG_SHPF  : Shift operation pending flag.  
+  *     @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
+  *     @arg RTC_FLAG_ALRBWF: Alarm B Write flag
+  *     @arg RTC_FLAG_ALRAWF: Alarm A write flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag 
+  *     @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
+  *     @arg RTC_FLAG_TSF: Time Stamp event flag
+  *     @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *     @arg RTC_FLAG_ALRBF: Alarm B flag
+  *     @arg RTC_FLAG_ALRAF: Alarm A flag
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));    
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_IT_TS: Time Stamp interrupt 
+  *     @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *     @arg RTC_IT_ALRB: Alarm B interrupt 
+  *     @arg RTC_IT_ALRA: Alarm A interrupt 
+  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt 
+  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt 
+  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_TS: Time Stamp interrupt 
+  *     @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *     @arg RTC_IT_ALRB: Alarm B interrupt 
+  *     @arg RTC_IT_ALRA: Alarm A interrupt 
+  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt 
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c
new file mode 100644
index 0000000..42addcd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c
@@ -0,0 +1,1410 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_spi.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + Hardware CRC Calculation
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  
+  
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
+            function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
+            function for SPI2.
+        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd()
+            function. 
+        (#) Peripherals alternate function: 
+            (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+            (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+            (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+            (++) Call GPIO_Init() function.
+        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+            function in SPI mode. In I2S mode, program the Mode, Standard, Data Format,
+            MCLK Output, Audio frequency and Polarity using I2S_Init() function.
+        (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select 
+            at which threshold the RXNE event is generated.     
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            SPI_I2S_ITConfig() if you need to use interrupt mode. 
+        (#) When using the DMA mode 
+            (++) Configure the DMA using DMA_Init() function.
+            (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+            I2S_Cmd().
+        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+        (#) Optionally you can enable/configure the following parameters without
+            re-initialization (i.e there is no need to call again SPI_Init() function):
+            (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+                 is programmed as Data direction parameter using the SPI_Init() function
+                 it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
+                 using the SPI_BiDirectionalLineConfig() function.
+            (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
+                 using the SPI_Init() function it can be possible to manage the 
+                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+            (++) Reconfigure the data size using the SPI_DataSizeConfig() function.  
+            (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
+        (#) To use the CRC Hardware calculation feature refer to the Peripheral 
+            CRC hardware Calculation subsection.
+    [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI 
+         peripheral is able to manage sending and receiving data simultaneously
+         using two data lines. Each SPI peripheral has an extended block called I2Sxext
+         (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+         The extension block is not a full SPI IP, it is used only as I2S slave to
+         implement full duplex mode. The extension block uses the same clock sources
+         as its master.          
+         To configure I2S full duplex you have to:
+        (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. 
+        (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to  
+            I2S_Init() function.
+        (#) Call I2S_Cmd() for SPIx then for its extended block.
+        (#) Configure interrupts or DMA requests and to get/clear flag status, 
+            use I2Sxext instance for the extension block.
+        [..] Functions that can be called with I2Sxext instances are:
+             I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(), 
+             SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
+             SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
+        [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
+        [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);   
+             I2S_StructInit(&I2SInitStruct);
+             I2SInitStruct.Mode = I2S_Mode_MasterTx;     
+             I2S_Init(SPI3, &I2SInitStruct);
+             I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
+             I2S_Cmd(SPI3, ENABLE);
+             I2S_Cmd(SPI3ext, ENABLE);
+             ...
+             while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+             {}
+             SPI_I2S_SendData16(SPI3, txdata[i]);
+             ...  
+             while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
+             {}
+             rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext);
+             ...          
+    [..]
+    (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() 
+        just after calling the function SPI_Init().  
+              
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_spi.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK       ((uint16_t)0x3040)
+#define CR2_LDMA_MASK        ((uint16_t)0x9FFF)
+
+#define I2SCFGR_CLEAR_MASK   ((uint16_t)0xF040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions allowing to initialize the SPI Direction,
+         SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+         Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+    [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
+         and Slave mode (details for these procedures are available in reference manual).
+    [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
+         use the following function to manage the NSS bit:
+         void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+    [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
+         is selected, use the follwoing function to enable the NSS output feature.
+         void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+    [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the 
+         following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+         And it can be managed by software in the SPI Motorola mode using this function: 
+         void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+    [..] This section provides also functions to initialize the I2S Mode, Standard, 
+         Data Format, MCLK Output, Audio frequency and Polarity.
+    [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
+         and Slave mode.
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values.
+  * @param  SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode.
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+  }
+  else
+  {
+    if (SPIx == SPI3)
+    {
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* Initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* Initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+  /* Configuring the SPI in master mode */
+  if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)
+  {
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+    /* Get the SPIx CR1 value */
+    tmpreg = SPIx->CR1;
+    /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+    tmpreg &= CR1_CLEAR_MASK;
+    /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+       master/slave mode, CPOL and CPHA */
+    /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+    /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+    /* Set LSBFirst bit according to SPI_FirstBit value */
+    /* Set BR bits according to SPI_BaudRatePrescaler value */
+    /* Set CPOL bit according to SPI_CPOL value */
+    /* Set CPHA bit according to SPI_CPHA value */
+    tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) |
+                         (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) |
+                         (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | 
+                         SPI_InitStruct->SPI_FirstBit)));
+    /* Write to SPIx CR1 */
+    SPIx->CR1 = tmpreg;
+    /*-------------------------Data Size Configuration -----------------------*/
+    /* Get the SPIx CR2 value */
+    tmpreg = SPIx->CR2;
+    /* Clear DS[3:0] bits */
+    tmpreg &= (uint16_t)~SPI_CR2_DS;
+    /* Configure SPIx: Data Size */
+    tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+    /* Write to SPIx CR2 */
+    SPIx->CR2 = tmpreg;
+  }
+  /* Configuring the SPI in slave mode */
+  else
+  {
+/*---------------------------- Data size Configuration -----------------------*/
+    /* Get the SPIx CR2 value */
+    tmpreg = SPIx->CR2;
+    /* Clear DS[3:0] bits */
+    tmpreg &= (uint16_t)~SPI_CR2_DS;
+    /* Configure SPIx: Data Size */
+    tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+    /* Write to SPIx CR2 */
+    SPIx->CR2 = tmpreg;
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+    /* Get the SPIx CR1 value */
+    tmpreg = SPIx->CR1;
+    /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+    tmpreg &= CR1_CLEAR_MASK;
+    /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+       master/salve mode, CPOL and CPHA */
+    /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+    /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+    /* Set LSBFirst bit according to SPI_FirstBit value */
+    /* Set BR bits according to SPI_BaudRatePrescaler value */
+    /* Set CPOL bit according to SPI_CPOL value */
+    /* Set CPHA bit according to SPI_CPHA value */
+    tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) | 
+                         (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) | 
+                         (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | 
+                         SPI_InitStruct->SPI_FirstBit)));
+
+    /* Write to SPIx CR1 */
+    SPIx->CR1 = tmpreg;
+  }
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *   parameters in the I2S_InitStruct.
+  * @param  SPIx:To select the SPIx peripheral, where x can be: 2 or 3 
+  *         in I2S mode. 
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *   contains the configuration information for the specified SPI peripheral
+  *   configured in I2S mode.
+  * @note
+  *  The function calculates the optimal prescaler needed to obtain the most 
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *  and the product configuration). But in case the prescaler value is greater 
+  *  than 511, the default value (0x02) will be configured instead.     
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint32_t sourceclock = 0;
+
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  SPIx->I2SPR = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);      
+
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the floating point */
+    tmp = tmp / 10;
+
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \
+                       (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\
+                       I2S_InitStruct->I2S_CPOL)));
+
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= SPI_CR1_SPE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TI Mode.
+  * @note    This function can be called only after the SPI_Init() function has 
+  *          been called. 
+  * @note    When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
+  *          are not taken into consideration and are configured by hardware 
+  *          respectively to the TI mode requirements.  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.  
+  * @param  NewState: new state of the selected SPI TI communication mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 |= SPI_CR2_FRF;
+  }
+  else
+  {
+    /* Disable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in 
+  *         I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. 
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *   For the SPIx peripheral this parameter can be one of the following values:
+  *     @arg SPI_DataSize_4b: Set data size to 4 bits
+  *     @arg SPI_DataSize_5b: Set data size to 5 bits
+  *     @arg SPI_DataSize_6b: Set data size to 6 bits
+  *     @arg SPI_DataSize_7b: Set data size to 7 bits
+  *     @arg SPI_DataSize_8b: Set data size to 8 bits
+  *     @arg SPI_DataSize_9b: Set data size to 9 bits
+  *     @arg SPI_DataSize_10b: Set data size to 10 bits
+  *     @arg SPI_DataSize_11b: Set data size to 11 bits
+  *     @arg SPI_DataSize_12b: Set data size to 12 bits
+  *     @arg SPI_DataSize_13b: Set data size to 13 bits
+  *     @arg SPI_DataSize_14b: Set data size to 14 bits
+  *     @arg SPI_DataSize_15b: Set data size to 15 bits
+  *     @arg SPI_DataSize_16b: Set data size to 16 bits
+  * @retval None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  uint16_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
+  /* Read the CR2 register */
+  tmpreg = SPIx->CR2;
+  /* Clear DS[3:0] bits */
+  tmpreg &= (uint16_t)~SPI_CR2_DS;
+  /* Set new DS[3:0] bits value */
+  tmpreg |= SPI_DataSize;
+  SPIx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the FIFO reception threshold for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. 
+  * @param  SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO 
+  *          level is greater or equal to 1/2. 
+  *     @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 
+  *          level is greater or equal to 1/4. 
+  * @retval None
+  */
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
+
+  /* Clear FRXTH bit */
+  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
+
+  /* Set new FRXTH bit value */
+  SPIx->CR2 |= SPI_RxFIFOThreshold;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. 
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
+  *     @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @note    This function can be called only after the SPI_Init() function has 
+  *          been called.  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Configures the full duplex mode for the I2Sx peripheral using its
+  *         extension I2Sxext according to the specified parameters in the 
+  *         I2S_InitStruct.
+  * @param  I2Sxext: where x can be  2 or 3 to select the I2S peripheral extension block.
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified I2S peripheral
+  *         extension.
+  * 
+  * @note   The structure pointed by I2S_InitStruct parameter should be the same
+  *         used for the master I2S peripheral. In this case, if the master is 
+  *         configured as transmitter, the slave will be receiver and vice versa.
+  *         Or you can force a different mode by modifying the field I2S_Mode to the
+  *         value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.    
+  *         
+  * @note   The I2S full duplex extension can be configured in slave mode only.    
+  *  
+  * @retval None
+  */
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, tmp = 0;
+  
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  I2Sxext->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = I2Sxext->I2SCFGR;
+  
+  /* Get the mode to be configured for the extended I2S */
+  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
+  {
+    tmp = I2S_Mode_SlaveRx;
+  }
+  else
+  {
+    if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
+    {
+      tmp = I2S_Mode_SlaveTx;
+    }
+  }
+
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+ 
+  /* Write to SPIx I2SCFGR */  
+  I2Sxext->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @note    This function can be called only after the SPI_Init() function has 
+  *          been called and the NSS hardware management mode is selected. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the NSS pulse management mode.
+  * @note    This function can be called only after the SPI_Init() function has 
+  *          been called. 
+  * @note    When TI mode is selected, the control bits NSSP is not taken into 
+  *          consideration and are configured by hardware respectively to the 
+  *          TI mode requirements. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. 
+  * @param  NewState: new state of the NSS pulse management mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the NSS pulse management mode */
+    SPIx->CR2 |= SPI_CR2_NSSP;
+  }
+  else
+  {
+    /* Disable the NSS pulse management mode */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);    
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions allowing to manage the SPI or I2S 
+         data transfers.
+    [..] In reception, data are received and then stored into an internal Rx buffer while 
+         In transmission, data are first stored into an internal Tx buffer before being 
+         transmitted.
+    [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
+         function and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+         can be done using SPI_I2S_SendData() function and stores the written data into 
+         Tx buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits a Data through the SPIx peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
+{
+  uint32_t spixbase = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  *(__IO uint8_t *) spixbase = Data;
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  
+  SPIx->DR = (uint16_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx peripheral. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
+{
+  uint32_t spixbase = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  return *(__IO uint8_t *) spixbase;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx peripheral. 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
+{  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  
+  return SPIx->DR;
+}
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Hardware CRC Calculation functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
+         calculation.
+    [..] SPI communication using CRC is possible through the following procedure:
+         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+             Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+             function.
+         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+         (#) Enable the SPI using the SPI_Cmd() function
+         (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
+             SPI_TransmitCRC() function to indicate that after transmission of the last 
+             data, the CRC should be transmitted.
+         (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+             bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+             value. 
+             If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+             can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+    [..]
+    (@)
+         (+@) It is advised to don't read the calculate CRC values during the communication.
+         (+@) When the SPI is in slave mode, be careful to enable CRC calculation only 
+              when the clock is stable, that is, when the clock is in the steady state. 
+              If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+              to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+              the value of the SPE bit.
+         (+@) With high bitrate frequencies, be careful when transmitting the CRC.
+              As the number of used CPU cycles has to be as low as possible in the CRC 
+              transfer phase, it is forbidden to call software functions in the CRC 
+              transmission sequence to avoid errors in the last data and CRC reception. 
+              In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+              of the last data.
+         (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+              degradation of the SPI speed performance due to CPU accesses impacting the 
+              SPI bandwidth.
+         (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is 
+              used, the NSS pin needs to be kept low between the data phase and the CRC 
+              phase.
+         (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+              calculation takes place even if a high level is applied on the NSS pin. 
+              This may happen for example in case of a multislave environment where the 
+              communication master addresses slaves alternately.
+         (+@) Between a slave deselection (high level on NSS) and a new slave selection 
+              (low level on NSS), the CRC value should be cleared on both master and slave
+              sides in order to resynchronize the master and slave for their respective 
+              CRC calculation.
+    [..]          
+    (@) To clear the CRC, follow the procedure below:
+         (#@) Disable SPI using the SPI_Cmd() function.
+         (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+         (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+         (#@) Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the CRC calculation length for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRCLength: specifies the SPI CRC calculation length.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
+  *     @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
+  * @retval None
+  */
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
+
+  /* Clear CRCL bit */
+  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
+
+  /* Set new CRCL bit value */
+  SPIx->CR1 |= SPI_CRCLength;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= SPI_CR1_CRCEN;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+  }
+}
+
+/**
+  * @brief  Transmits the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRC_Tx: Selects Tx CRC register
+  *     @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim   
+ ===============================================================================
+                  ##### DMA transfers management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI DMA transfer request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Configures the number of data to transfer type(Even/Odd) for the DMA
+  *         last transfers and for the selected SPI.
+  * @note   This function have a meaning only if DMA mode is selected and if 
+  *         the packing mode is used (data length <= 8 and DMA transfer size halfword)  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
+  *          and number of data for reception Even.
+  *     @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
+  *          and number of data for reception Even.
+  *     @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
+  *          and number of data for reception Odd.
+  *     @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd
+  *          and number of data for reception Odd.
+  * @retval None
+  */
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
+
+  /* Clear LDMA_TX and LDMA_RX bits */
+  SPIx->CR2 &= CR2_LDMA_MASK;
+
+  /* Set new LDMA_TX and LDMA_RX bits value */
+  SPIx->CR2 |= SPI_LastDMATransfer; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim   
+ ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions allowing to configure the SPI/I2S 
+         Interrupts sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+         (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register.
+         (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register.
+         (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+         (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.              
+         (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
+         (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
+         (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
+         (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+         (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+    [..]
+         (@) Do not use the BSY flag to handle each data transmission or reception.
+             It is better to use the TXE and RXNE flags instead.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+         (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
+         and 5 pending bits: 
+    [..] Pending Bits:
+         (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
+         (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
+         (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
+         (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
+         (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
+    [..] Interrupt Source:
+         (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+             interrupt.  
+         (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+             empty interrupt.
+         (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+  *** FIFO Status ***
+  ===================
+    [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
+         following function:
+         (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); 
+
+  *** DMA Mode ***
+  ================
+    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
+         (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Returns the current SPIx Transmission FIFO filled level.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The Transmission FIFO filling state.
+  *   - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
+  *   - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *   - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
+  *   - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Transmission FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Returns the current SPIx Reception FIFO filled level.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The Reception FIFO filling state.
+  *   - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
+  *   - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *   - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
+  *   - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Reception FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Checks whether the specified SPI flag is set or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *     @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
+  *     @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
+  *     @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
+  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.   
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *   This function clears only CRCERR flag.
+  * @note OVR (OverRun error) flag is cleared by software sequence: a read 
+  *       operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *       operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *       operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *       write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
+
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *     @arg SPI_IT_MODF: Mode Fault interrupt.
+  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *     @arg I2S_IT_UDR: Underrun interrupt.  
+  *     @arg SPI_I2S_IT_FRE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S_IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI_I2S_IT IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c
new file mode 100644
index 0000000..77de7da
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c
@@ -0,0 +1,3995 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_tim.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM peripheral:
+  *            + TimeBase management
+  *            + Output Compare management
+  *            + Input Capture management
+  *            + Advanced-control timers (TIM1 and TIM8) specific features  
+  *            + Interrupts, DMA and flags management
+  *            + Clocks management
+  *            + Synchronization management
+  *            + Specific interface management
+  *            + Specific remapping management      
+  *              
+  @verbatim
+    
+  ==============================================================================
+                       ##### How to use this driver #####
+  ==============================================================================
+   [..] This driver provides functions to configure and program the TIM 
+        of all stm32f30x devices.
+        These functions are split in 9 groups: 
+     
+        (#) TIM TimeBase management: this group includes all needed functions 
+            to configure the TM Timebase unit:
+                 (++) Set/Get Prescaler
+                 (++) Set/Get Autoreload  
+                 (++) Counter modes configuration
+                 (++) Set Clock division  
+                 (++) Select the One Pulse mode
+                 (++) Update Request Configuration
+                 (++) Update Disable Configuration
+                 (++) Auto-Preload Configuration 
+                 (++) Enable/Disable the counter     
+                   
+       (#) TIM Output Compare management: this group includes all needed 
+           functions to configure the Capture/Compare unit used in Output 
+           compare mode: 
+                 (++) Configure each channel, independently, in Output Compare mode
+                 (++) Select the output compare modes
+                 (++) Select the Polarities of each channel
+                 (++) Set/Get the Capture/Compare register values
+                 (++) Select the Output Compare Fast mode 
+                 (++) Select the Output Compare Forced mode  
+                 (++) Output Compare-Preload Configuration 
+                 (++) Clear Output Compare Reference
+                 (++) Select the OCREF Clear signal
+                 (++) Enable/Disable the Capture/Compare Channels    
+                    
+        (#) TIM Input Capture management: this group includes all needed 
+            functions to configure the Capture/Compare unit used in 
+            Input Capture mode:
+                 (++) Configure each channel in input capture mode
+                 (++) Configure Channel1/2 in PWM Input mode
+                 (++) Set the Input Capture Prescaler
+                 (++) Get the Capture/Compare values      
+                     
+        (#) Advanced-control timers (TIM1 and TIM8) specific features
+                 (++) Configures the Break input, dead time, Lock level, the OSSI,
+                      the OSSR State and the AOE(automatic output enable)
+                 (++) Enable/Disable the TIM peripheral Main Outputs
+                 (++) Select the Commutation event
+                 (++) Set/Reset the Capture Compare Preload Control bit
+                               
+        (#) TIM interrupts, DMA and flags management
+                 (++) Enable/Disable interrupt sources
+                 (++) Get flags status
+                 (++) Clear flags/ Pending bits
+                 (++) Enable/Disable DMA requests 
+                 (++) Configure DMA burst mode
+                 (++) Select CaptureCompare DMA request  
+                
+        (#) TIM clocks management: this group includes all needed functions 
+            to configure the clock controller unit:
+                 (++) Select internal/External clock
+                 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
+         
+        (#) TIM synchronization management: this group includes all needed 
+            functions to configure the Synchronization unit:
+                 (++) Select Input Trigger  
+                 (++) Select Output Trigger  
+                 (++) Select Master Slave Mode 
+                 (++) ETR Configuration when used as external trigger   
+       
+        (#) TIM specific interface management, this group includes all 
+            needed functions to use the specific TIM interface:
+                 (++) Encoder Interface Configuration
+                 (++) Select Hall Sensor   
+           
+        (#) TIM specific remapping management includes the Remapping 
+            configuration of specific timers               
+     
+  @endverbatim
+      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_tim.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_MASK      ((uint16_t)0x00FF) 
+#define CCMR_OFFSET        ((uint16_t)0x0018)
+#define CCER_CCE_SET       ((uint16_t)0x0001)  
+#define	CCER_CCNE_SET      ((uint16_t)0x0004) 
+#define CCMR_OC13M_MASK    ((uint32_t)0xFFFEFF8F)
+#define CCMR_OC24M_MASK    ((uint32_t)0xFEFF8FFF) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### TimeBase management functions #####
+ ===============================================================================  
+  
+             
+    *** TIM Driver: how to use it in Timing(Time base) Mode ***
+    ============================================================ 
+    [..]
+    To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+    (#) Enable TIM clock using 
+        RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function               
+    (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.   
+    (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure 
+        the Time Base unit
+        with the corresponding configuration        
+    (#) Enable the NVIC if you need to generate the update interrupt.        
+    (#) Enable the corresponding interrupt using the function 
+        TIM_ITConfig(TIMx, TIM_IT_Update)      
+    (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+    [..]                  
+    (@) All other functions can be used separately to modify, if needed,
+        a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @retval None
+
+  */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+ 
+  if (TIMx == TIM1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  } 
+  else if (TIMx == TIM2) 
+  {     
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+  }  
+  else if (TIMx == TIM3)
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+  }  
+  else if (TIMx == TIM4)
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+  }   
+  else if (TIMx == TIM6)  
+  {    
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+  }  
+  else if (TIMx == TIM7)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+  }  
+  else if (TIMx == TIM8)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
+  }    
+  else if (TIMx == TIM15)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);  
+  }  
+  else if (TIMx == TIM16) 
+  {       
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);  
+  }  
+  else
+  { 
+    if (TIMx == TIM17) 
+    {     
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); 
+    }   
+  }
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+  tmpcr1 = TIMx->CR1;  
+
+  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || 
+     (TIMx == TIM3)|| (TIMx == TIM4)) 
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+  }
+ 
+  if((TIMx != TIM6) && (TIMx != TIM7))
+  {
+    /* Set the clock division */
+    tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+    
+  if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) || 
+      (TIMx == TIM16) || (TIMx == TIM17))  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler 
+     and the repetition counter(only for TIM1 and TIM8) value immediatly */
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;          
+}
+
+/**
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Configures the TIMx Prescaler.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+  *            @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+  * @retval None
+  */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+  /* Set or reset the UG Bit */
+  TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIMx Counter Mode to be used.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CounterMode_Up: TIM Up Counting Mode
+  *            @arg TIM_CounterMode_Down: TIM Down Counting Mode
+  *            @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+  *            @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+  *            @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+  * @retval None
+  */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+  tmpcr1 = TIMx->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
+
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+
+  /* Write to TIMx CR1 register */
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIMx Counter Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
+{
+  /* Check the parameters */
+   assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Set the Counter Register value */
+  TIMx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TIMx Autoreload Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/**
+  * @brief  Gets the TIMx Counter value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @retval Counter Register value
+  */
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/**
+  * @brief  Gets the TIMx Prescaler value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/**
+  * @brief  Enables or Disables the TIMx Update event.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx UDIS bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TIMx->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_UpdateSource: specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_UpdateSource_Regular: Source of update is the counter
+  *                 overflow/underflow or the setting of UG bit, or an update
+  *                 generation through the slave mode controller.
+  *            @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TIMx->CR1 |= TIM_CR1_URS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
+  }
+}
+
+/**
+  * @brief  Sets or resets the update interrupt flag (UIF)status bit Remapping.
+  *         when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]  
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  NewState: new state of the UIFREMAP bit.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_UIFREMAP;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
+  }  
+}
+
+/**
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx peripheral Preload register
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TIMx->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
+  }
+}
+
+/**
+  * @brief  Selects the TIMx's One Pulse Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OPMode_Single
+  *            @arg TIM_OPMode_Repetitive
+  * @retval None
+  */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+
+  /* Reset the OPM Bit */
+  TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+  * @brief  Sets the TIMx Clock Division value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
+  * @param  TIM_CKD: specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CKD_DIV1: TDTS = Tck_tim
+  *            @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+  *            @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+
+  /* Reset the CKD Bits */
+  TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
+
+  /* Set the CKD value */
+  TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select 
+  *        the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Output Compare management functions #####
+ ===============================================================================  
+       
+  *** TIM Driver: how to use it in Output Compare Mode ***
+  ======================================================== 
+  [..] 
+  To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+       
+       (#) Configure the TIM pins by configuring the corresponding GPIO pins
+       
+       (#) Configure the Time base unit as described in the first part of this driver, 
+           if needed, else the Timer will run with the default configuration:
+           (++) Autoreload value = 0xFFFF
+           (++) Prescaler value = 0x0000
+           (++) Counter mode = Up counting
+           (++) Clock Division = TIM_CKD_DIV1   
+       (#) Fill the TIM_OCInitStruct with the desired parameters including:
+           (++) The TIM Output Compare mode: TIM_OCMode
+           (++) TIM Output State: TIM_OutputState
+           (++) TIM Pulse value: TIM_Pulse
+           (++) TIM Output Compare Polarity : TIM_OCPolarity
+       
+       (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the 
+           corresponding configuration
+       
+       (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+ [..]      
+       (@) All other functions can be used separately to modify, if needed,
+           a specific feature of the Timer. 
+          
+       (@) In case of PWM mode, this function is mandatory:
+           TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 
+              
+       (@) If the corresponding interrupt or DMA request are needed, the user should:
+                (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 
+                (#@) Enable the corresponding interrupt (or DMA request) using the function 
+                     TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIMx Channel1 according to the specified parameters in
+  *         the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
+  tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+  
+  /* Set the Output State */
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+    
+  if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
+    
+    /* Set the Output N State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel2 according to the specified parameters 
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
+  tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
+  
+  /* Set the Output State */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
+    /* Reset the Output N State */
+    tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
+    
+    /* Set the Output N State */
+    tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel3 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
+  tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
+  
+  /* Set the Output State */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
+    
+    /* Set the Output N State */
+    tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
+    tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel4 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
+  tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
+  
+  /* Set the Output State */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+    
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel5 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 5: Reset the CC5E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR3 register value */
+  tmpccmrx = TIMx->CCMR3;
+  
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
+
+  /* Set the Output State */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR3 = tmpccmrx;
+    
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel6 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 5: Reset the CC5E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR3 register value */
+  tmpccmrx = TIMx->CCMR3;
+  
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
+
+  /* Set the Output State */
+  tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR3 = tmpccmrx;
+    
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Selects the TIM Group Channel 5 and Channel 1, 
+            OC1REFC is the logical AND of OC1REFC and OC5REF.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the GC5C1 Bit */
+    TIMx->CCR5 |= TIM_CCR5_GC5C1;
+  }
+  else
+  {
+    /* Reset the GC5C1 Bit */
+    TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
+  }
+}
+
+/**
+  * @brief  Selects the TIM Group Channel 5 and Channel 2, 
+            OC2REFC is the logical AND of OC2REFC and OC5REF.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the GC5C2 Bit */
+    TIMx->CCR5 |= TIM_CCR5_GC5C2;
+  }
+  else
+  {
+    /* Reset the GC5C2 Bit */
+    TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
+  }
+}
+
+
+/**
+  * @brief  Selects the TIM Group Channel 5 and Channel 3, 
+            OC3REFC is the logical AND of OC3REFC and OC5REF.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the GC5C3 Bit */
+    TIMx->CCR5 |= TIM_CCR5_GC5C3;
+  }
+  else
+  {
+    /* Reset the GC5C3 Bit */
+    TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
+  }
+}
+
+/**
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+  TIM_OCInitStruct->TIM_Pulse = 0x00000000;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Selects the TIM Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode. If needed, user has to enable this channel using
+  *         TIM_CCxCmd() and TIM_CCxNCmd() functions.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
+  *           This parameter can be one of the following values:
+  *            @arg TIM_OCMode_Timing
+  *            @arg TIM_OCMode_Active
+  *            @arg TIM_OCMode_Toggle
+  *            @arg TIM_OCMode_PWM1
+  *            @arg TIM_OCMode_PWM2
+  *            @arg TIM_ForcedAction_Active
+  *            @arg TIM_ForcedAction_InActive
+  *            @arg TIM_OCMode_Retrigerrable_OPM1
+  *            @arg TIM_OCMode_Retrigerrable_OPM2
+  *            @arg TIM_OCMode_Combined_PWM1
+  *            @arg TIM_OCMode_Combined_PWM2
+  *            @arg TIM_OCMode_Asymmetric_PWM1
+  *            @arg TIM_OCMode_Asymmetric_PWM2            
+  * @retval None
+  */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode) /* to be updated*/
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_OCM(TIM_OCMode));
+
+  tmp = (uint32_t) TIMx;
+  tmp += CCMR_OFFSET;
+
+  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp1;
+
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+  {
+    tmp += (TIM_Channel>>1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
+   
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
+  }
+  else
+  {
+    tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
+    
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare1 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare2 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare3 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare4 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare5 Register value
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  Compare5: specifies the Capture Compare5 register new value.
+  * @retval None
+  */
+void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+
+  /* Set the Capture Compare5 Register value */
+  TIMx->CCR5 = Compare5;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare6 Register value
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  Compare6: specifies the Capture Compare5 register new value.
+  * @retval None
+  */
+void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+
+  /* Set the Capture Compare6 Register value */
+  TIMx->CCR6 = Compare6;
+}
+
+/**
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC1REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+  * @param  TIMx: where x can be   1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC2REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC3REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC4REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 5 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC5REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
+  * @retval None
+  */
+void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC5M Bits */
+  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr3 |= (uint32_t)(TIM_ForcedAction);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Forces the TIMx output 6 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC5REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
+  * @retval None
+  */
+void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC6M Bits */
+  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR5.
+  * @param  TIMx: where x can be  1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC5PE Bit */
+  tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr3 |= (uint32_t)(TIM_OCPreload);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR6.
+  * @param  TIMx: where x can be  1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC5PE Bit */
+  tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= ((uint32_t)TIM_OCFast << 8);
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint32_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= ((uint32_t)TIM_OCFast << 8);
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TIM_OCClear;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= ((uint32_t)TIM_OCClear << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TIM_OCClear;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= ((uint32_t)TIM_OCClear << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF5 signal on an external event
+  * @param  TIMx: where x can be  1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC5CE Bit */
+  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr3 |= (uint32_t)(TIM_OCClear);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF6 signal on an external event
+  * @param  TIMx: where x can be  1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint32_t tmpccmr3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr3 = TIMx->CCMR3;
+
+  /* Reset the OC5CE Bit */
+  tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr3 |= ((uint32_t)TIM_OCClear << 8);
+
+  /* Write to TIMx CCMR3 register */
+  TIMx->CCMR3 = tmpccmr3;
+}
+
+/**
+  * @brief  Selects the OCReference Clear source.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
+  *     @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.  
+  * @retval None
+  */
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
+
+  /* Set the TIM_OCReferenceClear source */
+  TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
+  TIMx->SMCR |=  TIM_OCReferenceClear;
+}
+
+/**
+  * @brief  Configures the TIMx channel 1 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
+  tmpccer |= TIM_OCPolarity;
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 1N polarity.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint32_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+   
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
+  tmpccer |= TIM_OCNPolarity;
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 2 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
+  tmpccer |= ((uint32_t)TIM_OCPolarity << 4);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 2N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+  
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
+  tmpccer |= ((uint32_t)TIM_OCNPolarity << 4);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 3 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC3P;
+  tmpccer |= ((uint32_t)TIM_OCPolarity << 8);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 3N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint32_t tmpccer = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+    
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
+  tmpccer |= ((uint32_t)TIM_OCNPolarity << 8);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 4 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC4P;
+  tmpccer |= ((uint32_t)TIM_OCPolarity << 12);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 5 polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC5 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC5P Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC5P;
+  tmpccer |= ((uint32_t)TIM_OCPolarity << 16);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 6 polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC6 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint32_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC6P Bit */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  tmpccer |= ((uint32_t)TIM_OCPolarity << 20);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  *            @arg TIM_Channel_5: TIM Channel 5
+  *            @arg TIM_Channel_6: TIM Channel 6    
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCX(TIM_CCx));
+
+  tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= (uint32_t)(~tmp);
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
+  */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+  tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= (uint32_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Input Capture management functions #####
+ ===============================================================================  
+         
+  *** TIM Driver: how to use it in Input Capture Mode ***
+  =======================================================
+  [..] 
+  To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+      (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+       
+      (#) Configure the TIM pins by configuring the corresponding GPIO pins
+       
+      (#) Configure the Time base unit as described in the first part of this driver,
+          if needed, else the Timer will run with the default configuration:
+          (++) Autoreload value = 0xFFFF
+          (++) Prescaler value = 0x0000
+          (++) Counter mode = Up counting
+          (++) Clock Division = TIM_CKD_DIV1
+          
+      (#) Fill the TIM_ICInitStruct with the desired parameters including:
+          (++) TIM Channel: TIM_Channel
+          (++) TIM Input Capture polarity: TIM_ICPolarity
+          (++) TIM Input Capture selection: TIM_ICSelection
+          (++) TIM Input Capture Prescaler: TIM_ICPrescaler
+          (++) TIM Input CApture filter value: TIM_ICFilter
+       
+      (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the 
+          corresponding configuration and to measure only frequency or duty cycle of the input signal,
+          or,
+          Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty cycle of the input signal
+          
+      (#) Enable the NVIC or the DMA to read the measured frequency. 
+          
+      (#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
+          using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 
+       
+      (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+       
+      (#) Use TIM_GetCapturex(TIMx); to read the captured value.
+  [..]        
+      (@) All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM peripheral according to the specified parameters
+  *         in the TIM_ICInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+  {
+    /* TI3 Configuration */
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {
+    /* TI4 Configuration */
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Configures the TIM peripheral according to the specified parameters
+  *         in the TIM_ICInitStruct to measure an external PWM signal.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    icoppositepolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TIM_ICPolarity_Rising;
+  }
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    icoppositeselection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TIM_ICSelection_DirectTI;
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI2 Configuration */
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  { 
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI1 Configuration */
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 1 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @retval Capture Compare 1 Register value.
+  */
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 2 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 3 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 3 Register value.
+  */
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 4 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 4 Register value.
+  */
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC1PSC Bits */
+  TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
+
+  /* Set the IC1PSC value */
+  TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC2PSC Bits */
+  TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
+
+  /* Set the IC2PSC value */
+  TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC3PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
+
+  /* Set the IC3PSC value */
+  TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC4PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
+
+  /* Set the IC4PSC value */
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
+ *  @brief   Advanced-control timers (TIM1 and TIM8) specific features
+ *
+@verbatim   
+ ===============================================================================
+     ##### Advanced-control timers (TIM1 and TIM8) specific features #####
+ ===============================================================================  
+       
+  *** TIM Driver: how to use the Break feature ***
+  ================================================ 
+  [..]
+  After configuring the Timer channel(s) in the appropriate Output Compare mode: 
+                         
+       (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+           Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
+           AOE(automatic output enable).
+               
+       (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+          
+       (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
+          
+       (#) Once the break even occurs, the Timer's output signals are put in reset
+           state or in a known state (according to the configuration made in
+           TIM_BDTRConfig() function).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval None
+  */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+  * @brief  Configures the Break1 feature.
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_Break1Polarity: specifies the Break1 polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Break1Polarity_Low: Break1 input is active low
+  *            @arg TIM_Break1Polarity_High: Break1 input is active high
+  * @param  TIM_Break1Filter: specifies the Break1 filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
+{   /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
+
+  /* Reset the BKP and BKF Bits */
+  TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF);
+  /* Configure the Break1 polarity and filter */
+  TIMx->BDTR |=	TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16);
+}
+
+/**
+  * @brief  Configures the Break2 feature.
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_Break2Polarity: specifies the Break2 polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Break2Polarity_Low: Break2 input is active low
+  *            @arg TIM_Break2Polarity_High: Break2 input is active high
+  * @param  TIM_Break2Filter: specifies the Break2 filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
+
+  /* Reset the BKP and BKF Bits */
+  TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F);
+
+  /* Configure the Break1 polarity and filter */
+  TIMx->BDTR |=	TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20);
+}
+
+/**
+  * @brief  Enables or disables the TIM Break1 input.
+  * @param  TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM Break1 input.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Break1 */
+    TIMx->BDTR |= TIM_BDTR_BKE;
+  }
+  else
+  {
+    /* Disable the Break1 */
+    TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
+  } 
+}
+
+/**
+  * @brief  Enables or disables the TIM Break2 input.
+  * @param  TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM Break2 input.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Break1 */
+    TIMx->BDTR |= TIM_BDTR_BK2E;
+  }
+  else
+  {
+    /* Disable the Break1 */
+    TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
+  }
+}
+
+/**
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
+  * @param  TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Main Output */
+    TIMx->BDTR |= TIM_BDTR_MOE;
+  }
+  else
+  {
+    /* Disable the TIM Main Output */
+    TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
+  }  
+}
+
+/**
+  * @brief  Selects the TIM peripheral Commutation event.
+  * @param  TIMx: where x can be  1, 8, 15, 16 or 17 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TIMx->CR2 |= TIM_CR2_CCUS;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
+  }
+}
+
+/**
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TIMx->CR2 |= TIM_CR2_CCPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+         ##### Interrupts, DMA and flags management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM interrupts.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral.
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *  
+  * @note   For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
+  * @note   For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
+  *          TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
+  *          be used: TIM_IT_Update or TIM_IT_CC1   
+  * @note   TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 
+  *        
+  * @param  NewState: new state of the TIM interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (uint16_t)~TIM_IT;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx event to be generate by software.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_EventSource: specifies the event source.
+  *          This parameter can be one or more of the following values:	   
+  *            @arg TIM_EventSource_Update: Timer update Event source
+  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EventSource_COM: Timer COM event source  
+  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *            @arg TIM_EventSource_Break: Timer Break event source
+  * 
+  * @note   TIM6 and TIM7 can only generate an update event. 
+  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+  *        
+  * @retval None
+  */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+ 
+  /* Set the event sources */
+  TIMx->EGR = TIM_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM flag is set or not.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
+  *            @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag  
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.    
+  *
+  * @retval The new state of TIM_FLAG (SET or RESET).
+  */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
+{ 
+  ITStatus bitstatus = RESET;  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+  
+  if ((TIMx->SR & TIM_FLAG) != RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's pending flags.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
+  *            @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag               
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+  *    
+  * @retval None
+  */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+   
+  /* Clear the flags */
+  TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TIM interrupt has occurred or not.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+  *     
+  * @retval The new state of the TIM_IT(SET or RESET).
+  */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_IT(TIM_IT));
+   
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's interrupt pending bits.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM1 update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+  *      
+  * @retval None
+  */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Clear the IT pending Bit */
+  TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+  * @brief  Configures the TIMx's DMA interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_DMABase: DMA Base address.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMABase_CR1  
+  *            @arg TIM_DMABase_CR2
+  *            @arg TIM_DMABase_SMCR
+  *            @arg TIM_DMABase_DIER
+  *            @arg TIM1_DMABase_SR
+  *            @arg TIM_DMABase_EGR
+  *            @arg TIM_DMABase_CCMR1
+  *            @arg TIM_DMABase_CCMR2
+  *            @arg TIM_DMABase_CCER
+  *            @arg TIM_DMABase_CNT   
+  *            @arg TIM_DMABase_PSC   
+  *            @arg TIM_DMABase_ARR
+  *            @arg TIM_DMABase_RCR
+  *            @arg TIM_DMABase_CCR1
+  *            @arg TIM_DMABase_CCR2
+  *            @arg TIM_DMABase_CCR3  
+  *            @arg TIM_DMABase_CCR4
+  *            @arg TIM_DMABase_BDTR
+  *            @arg TIM_DMABase_DCR
+  * @param  TIM_DMABurstLength: DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+
+  /* Set the DMA Base and the DMA Burst Length */
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's DMA Requests.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  TIM_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_DMA_Update: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_Trigger: TIM Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIMx->DIER |= TIM_DMASource; 
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
+  }
+}
+
+/**
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIMx->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group6 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Clocks management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx internal Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
+}
+
+/**
+  * @brief  Configures the TIMx Internal Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  TIM_InputTriggerSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TIMx Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15  
+  *         to select the TIM peripheral.
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *            @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *            @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  ICFilter: specifies the filter value.
+  *          This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
+
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                            uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+
+  /* Select the External clock mode1 */
+  tmpsmcr |= TIM_SlaveMode_External1;
+
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+  tmpsmcr |= TIM_TS_ETRF;
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= TIM_SMCR_ECE;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group7 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Synchronization management functions #####
+ ===============================================================================  
+                         
+  *** TIM Driver: how to use it in synchronization Mode ***
+  ========================================================= 
+  [..] Case of two/several Timers
+       
+       (#) Configure the Master Timers using the following functions:
+           (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 
+           (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);  
+       (#) Configure the Slave Timers using the following functions: 
+           (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+           (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+          
+  [..] Case of Timers and external trigger(ETR pin)
+           
+       (#) Configure the External trigger using this function:
+           (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                                   uint16_t ExtTRGFilter);
+       (#) Configure the Slave Timers using the following functions: 
+           (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+           (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx: where x can be  1, 2, 3, 4, 8 or 15  
+  *         to select the TIM peripheral.
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+
+  /* Set the Input Trigger source */
+  tmpsmcr |= TIM_InputTriggerSource;
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
+  *     
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
+  *   This parameter can be one of the following values:
+  *
+  *  - For all TIMx
+  *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
+  *
+  *  - For all TIMx except TIM6 and TIM7
+  *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                                     is to be set, as soon as a capture or compare match occurs(TRGO)
+  *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode2 (TRGO2).
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  *     
+  * @param  TIM_TRGO2Source: specifies the Trigger Output source.
+  *   This parameter can be one of the following values:
+  *
+  *  - For all TIMx
+  *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                                     is to be set, as soon as a capture or compare match occurs(TRGO2)
+  *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising  are used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
+  *            @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
+
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGO2Source;
+}
+
+/**
+  * @brief  Selects the TIMx Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize 
+  *                                      the counter and triggers an update of the registers
+  *            @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high
+  *            @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI
+  *            @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
+  *            @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
+  *                                                      reinitializes the counter, generates an update 
+  *                                                      of the registers and starts the counter.
+  * @retval None
+  */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+
+  /* Reset the SMS Bits */
+  TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
+
+  /* Select the Slave Mode */
+  TIMx->SMCR |= (uint32_t)TIM_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral.
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                             and its slaves (through TRGO)
+  *            @arg TIM_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+  /* Reset the MSM Bit */
+  TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
+  
+  /* Set or Reset the MSM Bit */
+  TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx: where x can be  1, 2, 3, 4 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMCR_ETR_MASK;
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group8 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+              ##### Specific interface management functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx Encoder Interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM 
+  *         peripheral.
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *            @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *            @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                       on the level of the other input.
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+  tmpsmcr |= TIM_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 
+  *         peripheral.
+  * @param  NewState: new state of the TIMx Hall sensor interface.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group9 Specific remapping management function
+ *  @brief   Specific remapping management function
+ *
+@verbatim   
+ ===============================================================================
+               ##### Specific remapping management function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM16 Remapping input Capabilities.
+  * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral.
+  * @param TIM_Remap: specifies the TIM input reampping source.
+  *   This parameter can be one of the following values:
+  *            @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
+  *            @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
+  *            @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.  
+  *            @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock. 
+  *            @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
+  *            @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
+  *            @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.  
+  *            @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
+  *            @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
+  *            @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3. 
+  *            @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
+  *            @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
+  *            @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
+  *            @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
+  *            @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
+  *            @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.  
+  * @retval : None
+  */
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
+{
+ /* Check the parameters */
+  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+  assert_param(IS_TIM_REMAP(TIM_Remap));
+
+  /* Set the Timer remapping configuration */
+  TIMx->OR =  TIM_Remap;
+}
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 
+  *         to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge  
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0, tmpccer = 0;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
+  tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4));
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge   
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
+  tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12);
+  tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge         
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge     
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c
new file mode 100644
index 0000000..641a104
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c
@@ -0,0 +1,2084 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_usart.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):
+  *           + Initialization and Configuration
+  *           + STOP Mode
+  *           + AutoBaudRate
+  *           + Data transfers
+  *           + Multi-Processor Communication
+  *           + LIN mode
+  *           + Half-duplex mode
+  *           + Smartcard mode
+  *           + IrDA mode
+  *           + RS485 mode  
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *           
+  *  @verbatim  
+ ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================
+      [..]
+          (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+             function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
+             function for USART2, USART3, UART4 and UART5.
+          (#)  According to the USART mode, enable the GPIO clocks using
+              RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
+              or and SCLK).
+          (#) Peripheral's alternate function:
+              (++) Connect the pin to the desired peripherals' Alternate
+                   Function (AF) using GPIO_PinAFConfig() function.
+              (++) Configure the desired pin in alternate function by:
+                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+              (++) Select the type, pull-up/pull-down and output speed via
+                   GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+              (++) Call GPIO_Init() function.
+          (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+             flow control and Mode(Receiver/Transmitter) using the SPI_Init()
+             function.
+          (#) For synchronous mode, enable the clock and program the polarity,
+             phase and last bit using the USART_ClockInit() function.
+          (#) Enable the NVIC and the corresponding interrupt using the function
+             USART_ITConfig() if you need to use interrupt mode.
+          (#) When using the DMA mode:
+              (++) Configure the DMA using DMA_Init() function.
+              (++) Active the needed channel Request using USART_DMACmd() function.
+          (#) Enable the USART using the USART_Cmd() function.
+          (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
+      [..]
+              Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+              for more details.
+
+   @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_usart.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
+#define CR1_CLEAR_MASK            ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
+                                              USART_CR1_PS | USART_CR1_TE | \
+                                              USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK      ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
+#define CR3_CLEAR_MASK            ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK                   ((uint32_t)0x000000FF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim 
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================  
+  [..]
+      This subsection provides a set of functions allowing to initialize the USART 
+      in asynchronous and in synchronous modes.
+       (+) For the asynchronous mode only these parameters can be configured: 
+            (++) Baud Rate.
+            (++) Word Length. 
+            (++) Stop Bit.
+            (++) Parity: If the parity is enabled, then the MSB bit of the data written
+                 in the data register is transmitted but is changed by the parity bit.
+                 Depending on the frame length defined by the M bit (8-bits or 9-bits),
+                 the possible USART frame formats are as listed in the following table:
+    [..]
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+    [..]
+           (++) Hardware flow control.
+           (++) Receiver/transmitter modes.
+    [..] The USART_Init() function follows the USART  asynchronous configuration 
+         procedure(details for the procedure are available in reference manual.
+        (+) For the synchronous mode in addition to the asynchronous mode parameters
+            these parameters should be also configured:
+            (++) USART Clock Enabled.
+            (++) USART polarity.
+            (++) USART phase.
+            (++) USART LastBit.
+    [..] These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }
+  else
+  {
+    if  (USARTx == UART5)
+    {
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t divider = 0, apbclock = 0, tmpreg = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+  
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  
+  /* Disable USART */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  
+  /*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+  
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+  
+  /*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+  
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+    USART_InitStruct->USART_Mode;
+  
+  /* Write to USART CR1 */
+  USARTx->CR1 = tmpreg;
+  
+  /*---------------------------- USART CR3 Configuration -----------------------*/
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+  
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  
+  /* Write to USART CR3 */
+  USARTx->CR3 = tmpreg;
+  
+  /*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  
+  if (USARTx == USART1)
+  {
+    apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
+  }
+  else if (USARTx == USART2)
+  {
+    apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
+  }
+  else if (USARTx == USART3)
+  {
+    apbclock = RCC_ClocksStatus.USART3CLK_Frequency;
+  }
+  else if (USARTx == UART4)
+  {
+    apbclock = RCC_ClocksStatus.UART4CLK_Frequency;
+  }
+  else 
+  {
+    apbclock = RCC_ClocksStatus.UART5CLK_Frequency;
+  }  
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* (divider * 10) computing in case Oversampling mode is 8 Samples */
+    divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* (divider * 10) computing in case Oversampling mode is 16 Samples */
+    divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  
+  /* round the divider : if fractional part i greater than 0.5 increment divider */
+  if (tmpreg >=  (USART_InitStruct->USART_BaudRate) / 2)
+  {
+    divider++;
+  } 
+  
+  /* Implement the divider in case Oversampling mode is 8 Samples */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* get the LSB of divider and shift it to the right by 1 bit */
+    tmpreg = (divider & (uint16_t)0x000F) >> 1;
+    
+    /* update the divider value */
+    divider = (divider & (uint16_t)0xFFF0) | tmpreg;
+  }
+  
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)divider;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified
+  *         USART peripheral.
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+  /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                       USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_UE;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's transmitter or receiver.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_Direction: specifies the USART direction.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_Mode_Tx: USART Transmitter
+  *         @arg USART_Mode_Rx: USART Receiver
+  * @param  NewState: new state of the USART transfer direction.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MODE(USART_DirectionMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART's transfer interface by setting the TE and/or RE bits 
+       in the USART CR1 register */
+    USARTx->CR1 |= USART_DirectionMode;
+  }
+  else
+  {
+    /* Disable the USART's transfer interface by clearing the TE and/or RE bits
+       in the USART CR3 register */
+    USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART 8x oversampling mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note
+  *   This function has to be called before calling USART_Init()
+  *   function in order to have correct baudrate Divider value.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_OVER8;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note
+  *   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_ONEBIT;
+  }
+  else
+  {
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's most significant bit first 
+  *         transmitted/received following the start bit.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART most significant bit first
+  *         transmitted/received following the start bit.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note
+  *   This function has to be called before calling USART_Cmd() function. 
+  * @retval None
+  */
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the most significant bit first transmitted/received following the
+       start bit by setting the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_MSBFIRST;
+  }
+  else
+  {
+    /* Disable the most significant bit first transmitted/received following the
+       start bit by clearing the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
+  }
+}
+
+/**
+  * @brief  Enables or disables the binary data inversion.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new defined levels for the USART data.
+  *         This parameter can be: ENABLE or DISABLE.
+  *   @arg  ENABLE: Logical data from the data register are send/received in negative
+  *         logic. (1=L, 0=H). The parity bit is also inverted.
+  *   @arg  DISABLE: Logical data from the data register are send/received in positive
+  *         logic. (1=H, 0=L) 
+  * @note
+  *   This function has to be called before calling USART_Cmd() function. 
+  * @retval None
+  */
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the binary data inversion feature by setting the DATAINV bit in
+       the CR2 register */
+    USARTx->CR2 |= USART_CR2_DATAINV;
+  }
+  else
+  {
+    /* Disable the binary data inversion feature by clearing the DATAINV bit in
+       the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Pin(s) active level inversion.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_InvPin: specifies the USART pin(s) to invert.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_InvPin_Tx: USART Tx pin active level inversion.
+  *         @arg USART_InvPin_Rx: USART Rx pin active level inversion.
+  * @param  NewState: new active level status for the USART pin(s).
+  *         This parameter can be: ENABLE or DISABLE.
+  *          - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
+  *          - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
+  * @note
+  *   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the active level inversion for selected pins by setting the TXINV 
+       and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 |= USART_InvPin;
+  }
+  else
+  {
+    /* Disable the active level inversion for selected requests by clearing the 
+       TXINV and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 &= (uint32_t)~USART_InvPin;
+  }
+}
+
+/**
+  * @brief  Enables or disables the swap Tx/Rx pins.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USARTx TX/RX pins pinout.
+  *         This parameter can be: ENABLE or DISABLE.
+  *         @arg ENABLE: The TX and RX pins functions are swapped.
+  *         @arg DISABLE: TX/RX pins are used as defined in standard pinout
+  * @note
+  *   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_SWAP;
+  }
+  else
+  {
+    /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the receiver Time Out feature.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USARTx receiver Time Out.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_RTOEN;
+  }
+  else
+  {
+    /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
+  }
+}
+
+/**
+  * @brief  Sets the receiver Time Out value.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_ReceiverTimeOut: specifies the Receiver Time Out value.
+  * @retval None
+  */
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
+
+  /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
+  /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR |= USART_ReceiverTimeOut;
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_Prescaler: specifies the prescaler clock.  
+  * @note
+  *   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= USART_GTPR_GT;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group2 STOP Mode functions
+ *  @brief   STOP Mode functions
+ *
+@verbatim
+ ===============================================================================
+                        ##### STOP Mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         WakeUp from STOP mode.
+
+    [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
+         or LSI.
+         
+    [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
+         function.
+         
+    [..] After configuring the source of WakeUp and before entering in Stop Mode 
+         USART_STOPModeCmd() function should be called to allow USART WakeUp.
+                           
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the specified USART peripheral in STOP Mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral state in stop mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note
+  *   This function has to be called when USART clock is set to HSI or LSE.
+  * @retval None
+  */
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
+       register */
+    USARTx->CR1 |= USART_CR1_UESM;
+  }
+  else
+  {
+    /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
+       register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method form stop mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_WakeUp: specifies the selected USART wakeup method.
+  *         This parameter can be one of the following values:
+  *         @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
+  *         @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
+  *         @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
+  * @note
+  *   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
+  USARTx->CR3 |= USART_WakeUpSource;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group3 AutoBaudRate functions
+ *  @brief   AutoBaudRate functions 
+ *
+@verbatim
+ ===============================================================================
+                       ##### AutoBaudRate functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the AutoBaudRate detections.
+         
+    [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
+         The character patterns used to calculate baudrate must be chosen by calling 
+         USART_AutoBaudRateConfig() function. These function take as parameter :
+        (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
+        (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. 
+                          
+    [..] At any later time, another request for AutoBaudRate detection can be performed
+         using USART_RequestCmd() function.
+         
+    [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
+         that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
+         indicate that this procedure is completed without success. USART_GetFlagStatus () 
+         function should be used to monitor the status of these flags.  
+             
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the Auto Baud Rate.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USARTx auto baud rate.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_ABREN;
+  }
+  else
+  {
+    /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
+  }
+}
+
+/**
+  * @brief  Selects the USART auto baud rate method.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_AutoBaudRate: specifies the selected USART auto baud rate method.
+  *         This parameter can be one of the following values:
+  *         @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
+  *         @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
+  *         @arg USART_AutoBaudRate_0x7FFrame: 0x7F frame.
+  *         @arg USART_AutoBaudRate_0x55Frame: 0x55 frame.
+  * @note
+  *   This function has to be called before calling USART_Cmd() function. 
+  * @retval None
+  */
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
+  USARTx->CR2 |= USART_AutoBaudRate;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group4 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the USART data transfers.
+    [..] During an USART reception, data shifts in least significant bit first 
+         through the RX pin. When a transmission is taking place, a write instruction to 
+         the USART_TDR register stores the data in the shift register.
+    [..] The read access of the USART_RDR register can be done using 
+         the USART_ReceiveData() function and returns the RDR value.
+         Whereas a write access to the USART_TDR can be done using USART_SendData()
+         function and stores the written data into TDR.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+
+  /* Transmit Data */
+  USARTx->TDR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Receive Data */
+  return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Multi-Processor Communication functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         multiprocessor communication.
+    [..] For instance one of the USARTs can be the master, its TX output is
+         connected to the RX input of the other USART. The others are slaves,
+         their respective TX outputs are logically ANDed together and connected 
+         to the RX input of the master. USART multiprocessor communication is 
+         possible through the following procedure:
+         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Configures the wake up methode (USART_WakeUp_IdleLine or 
+             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only 
+             for the slaves.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() 
+             function.
+    [..] The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Clear the USART address */
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
+  /* Set the USART address node */
+  USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
+}
+
+/**
+  * @brief  Enables or disables the USART's mute mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART mute mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode by setting the MME bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_MME;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method from mute mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *         This parameter can be one of the following values:
+  *         @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *         @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
+
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Configure the the USART Address detection length.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_AddressLength: specifies the USART address length detection.
+  *         This parameter can be one of the following values:
+  *         @arg USART_AddressLength_4b: 4-bit address length detection 
+  *         @arg USART_AddressLength_7b: 7-bit address length detection 
+  * @retval None
+  */
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
+  USARTx->CR2 |= USART_AddressLength;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group6 LIN mode functions
+ *  @brief   LIN mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                       ##### LIN mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         LIN Mode communication.
+    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance 
+         with the LIN standard.
+    [..] Only this LIN Feature is supported by the USART IP:
+         (+) LIN Master Synchronous Break send capability and LIN slave break 
+             detection capability :  13-bit break generation and 10/11 bit break 
+             detection.
+    [..] USART LIN Master transmitter communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Send the break character using USART_SendBreak() function.
+    [..] USART LIN Master receiver communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the break detection length 
+             using the USART_LINBreakDetectLengthConfig() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         [..]
+         (@) In LIN mode, the following bits must be kept cleared:
+             (+@) CLKEN in the USART_CR2 register.
+             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *         This parameter can be one of the following values:
+  *         @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *         @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART's LIN mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART LIN mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_LINEN;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Half-duplex mode function #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Half-duplex communication.
+    [..] The USART can be configured to follow a single-wire half-duplex protocol 
+         where the TX and RX lines are internally connected.
+    [..] USART Half duplex communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+             or Mode receiver and hardware flow control values using the USART_Init()
+            function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         [..]
+         (@) The RX pin is no longer used.
+         (@) In Half-duplex mode the following bits must be kept cleared:
+             (+@) LINEN and CLKEN bits in the USART_CR2 register.
+             (+@) SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's Half Duplex communication.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the USART Communication.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_HDSEL;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group8 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Smartcard mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Smartcard communication.
+    [..] The Smartcard interface is designed to support asynchronous protocol 
+         Smartcards as defined in the ISO 7816-3 standard. The USART can provide 
+         a clock to the smartcard through the SCLK output. In smartcard mode, 
+         SCLK is not associated to the communication but is simply derived from 
+         the internal peripheral input clock through a 5-bit prescaler.
+    [..] Smartcard communication is possible through the following procedure:
+         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() 
+             function.
+         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() 
+             function.
+         (#) Program the USART clock using the USART_ClockInit() function as following:
+             (++) USART Clock enabled.
+             (++) USART CPOL Low.
+             (++) USART CPHA on first edge.
+             (++) USART Last Bit Clock Enabled.
+         (#) Program the Smartcard interface using the USART_Init() function as 
+             following:
+             (++) Word Length = 9 Bits.
+             (++) 1.5 Stop Bit.
+             (++) Even parity.
+             (++) BaudRate = 12096 baud.
+             (++) Hardware flow control disabled (RTS and CTS signals).
+             (++) Tx and Rx enabled
+         (#) Optionally you can enable the parity error interrupt using 
+             the USART_ITConfig() function.
+         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+    [..] 
+  Please refer to the ISO 7816-3 specification for more details.
+    [..] 
+         (@) It is also possible to choose 0.5 stop bit for receiving but it is 
+             recommended to use 1.5 stop bits for both transmitting and receiving 
+             to avoid switching between the two configurations.
+         (@) In smartcard mode, the following bits must be kept cleared:
+             (+@) LINEN bit in the USART_CR2 register.
+             (+@) HDSEL and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= USART_GTPR_PSC;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Enables or disables the USART's Smart Card mode.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3.
+  * @param  NewState: new state of the Smart Card mode.
+  *         This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3.
+  * @param  NewState: new state of the NACK transmission.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
+  }
+}
+
+/**
+  * @brief  Sets the Smart Card number of retries in transmit and receive.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3.
+  * @param  USART_AutoCount: specifies the Smart Card auto retry count.
+  * @retval None
+  */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
+  /* Clear the USART auto retry count */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
+  /* Set the USART auto retry count*/
+  USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
+}
+
+/**
+  * @brief  Sets the Smart Card Block length.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3.
+  * @param  USART_BlockLength: specifies the Smart Card block length.
+  * @retval None
+  */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+
+  /* Clear the Smart card block length */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
+  /* Set the Smart Card block length */
+  USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group9 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                        ##### IrDA mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         IrDA communication.
+    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, 
+         any data on the IrDA receive line will be ignored by the IrDA decoder 
+         and if the Receiver is busy, data on the TX from the USART to IrDA will 
+         not be encoded by IrDA. While receiving data, transmission should be 
+         avoided as the data to be transmitted could be corrupted.
+    [..] IrDA communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Configures the IrDA pulse width by configuring the prescaler using  
+             the USART_SetPrescaler() function.
+         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal 
+             mode using the USART_IrDAConfig() function.
+         (#) Enable the IrDA using the USART_IrDACmd() function.
+         (#) Enable the USART using the USART_Cmd() function.         
+    [..]
+    (@) A pulse of width less than two and greater than one PSC period(s) may or 
+        may not be rejected.
+    (@) The receiver set up time should be managed by software. The IrDA physical 
+        layer specification specifies a minimum of 10 ms delay between 
+        transmission and reception (IrDA is a half duplex protocol).
+    (@) In IrDA mode, the following bits must be kept cleared:
+        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        (+@) SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *         This parameter can be one of the following values:
+  *         @arg USART_IrDAMode_LowPower
+  *         @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface. 
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the IrDA mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group10 RS485 mode function
+ *  @brief   RS485 mode function 
+ *
+@verbatim  
+ ===============================================================================
+                        ##### RS485 mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         RS485 flow control.
+    [..] RS485 flow control (Driver enable feature) handling is possible through
+         the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Enable the Driver Enable using the USART_DECmd() function.
+         (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
+             function.
+         (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() 
+             function and deassertion time using the USART_SetDEDeassertionTime()
+             function.    
+         (#) Enable the USART using the USART_Cmd() function.
+      [..]  
+       (@) The assertion and dessertion times are expressed in sample time units (1/8 or 
+            1/16 bit time, depending on the oversampling rate).
+       
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DE functionality.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  NewState: new state of the driver enable mode.
+  *         This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the DE functionality by setting the DEM bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_DEM;
+  }
+  else
+  {
+    /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
+  }
+}
+
+/**
+  * @brief  Configures the USART's DE polarity
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_DEPolarity: specifies the DE polarity.
+  *         This parameter can be one of the following values:
+  *         @arg USART_DEPolarity_Low
+  *         @arg USART_DEPolarity_High
+  * @retval None
+  */
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
+  USARTx->CR3 |= USART_DEPolarity;
+}
+
+/**
+  * @brief  Sets the specified RS485 DE assertion time
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_AssertionTime: specifies the time between the activation of the DE
+  *          signal and the beginning of the start bit
+  * @retval None
+  */
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); 
+
+  /* Clear the DE assertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
+  /* Set the new value for the DE assertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
+}
+
+/**
+  * @brief  Sets the specified RS485 DE deassertion time
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_DeassertionTime: specifies the time between the middle of the last 
+  *         stop bit in a transmitted message and the de-activation of the DE signal
+  * @retval None
+  */
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); 
+
+  /* Clear the DE deassertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
+  /* Set the new value for the DE deassertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group11 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel 
+         requests:
+         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, 
+             FunctionalState NewState).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_DMAReq_Tx: USART DMA transmit request
+  *         @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_1234_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint32_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's DMA interface when reception error occurs.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4.
+  * @param  USART_DMAOnError: specifies the DMA status in case of reception error.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA  
+  *          reception error is asserted.
+  *         @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA 
+  *          reception error is asserted.
+  * @retval None
+  */
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_1234_PERIPH(USARTx));
+  assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); 
+  
+  /* Clear the DMA Reception error detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
+  /* Set the new value for the DMA Reception error detection bit */
+  USARTx->CR3 |= USART_DMAOnError;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group12 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to configure the 
+         USART Interrupts sources, Requests and check or clear the flags or pending bits status. 
+         The user should identify which mode will be used in his application to 
+         manage the communication: Polling mode, Interrupt mode.
+         
+ *** Polling Mode ***
+ ====================
+    [..] In Polling Mode, the SPI communication can be managed by these flags:
+         (#) USART_FLAG_REACK: to indicate the status of the Receive Enable 
+             acknowledge flag
+         (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable 
+             acknowledge flag.
+         (#) USART_FLAG_WUF: to indicate the status of the Wake up flag.
+         (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
+         (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
+         (#) USART_FLAG_CMF: to indicate the status of the Character match flag.
+         (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
+         (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
+         (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
+         (#) USART_FLAG_EOBF: to indicate the status of the End of block flag.
+         (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.
+         (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input 
+             bit status.
+         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
+         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
+         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
+         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
+         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
+         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
+         (#) USART_FLAG_NE: to indicate if a noise error occur.
+         (#) USART_FLAG_FE: to indicate if a frame error occur.
+         (#) USART_FLAG_PE: to indicate if a parity error occur.
+         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+               
+ *** Interrupt Mode ***
+ ======================
+    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt 
+         sources and 10 pending bits:
+         (+) Pending Bits:
+             (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
+             (##) USART_IT_CM: to indicate the status of Character match interrupt.
+             (##) USART_IT_EOB: to indicate the status of End of block interrupt.
+             (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
+             (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
+             (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
+             (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
+             (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
+             (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
+             (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
+             (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
+             (##) USART_IT_PE: to indicate the status of Parity Error interrupt.  
+              
+         (+) Interrupt Source:
+             (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
+             (##) USART_IT_CM: specifies the interrupt source for Character match 
+                  interrupt.
+             (##) USART_IT_EOB: specifies the interrupt source for End of block
+                  interrupt.
+             (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
+                  interrupt.
+             (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
+             (##) USART_IT_LBD: specifies the interrupt source for LIN Break 
+                  detection interrupt.
+             (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data 
+                  Register empty interrupt.
+             (##) USART_IT_TC: specifies the interrupt source for Transmission 
+                  complete interrupt.
+             (##) USART_IT_RXNE: specifies the interrupt source for Receive Data 
+                  register not empty interrupt.
+             (##) USART_IT_IDLE: specifies the interrupt source for Idle line 
+                  detection interrupt.
+             (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
+             (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
+                  (Frame error, noise error, overrun error)
+             -@@- Some parameters are coded in order to use them as interrupt 
+                 source or as pending bits.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
+         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
+         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *         @arg USART_IT_WU:  Wake up interrupt.
+  *         @arg USART_IT_CM:  Character match interrupt.
+  *         @arg USART_IT_EOB:  End of block interrupt.
+  *         @arg USART_IT_RTO:  Receive time out interrupt.
+  *         @arg USART_IT_CTS:  CTS change interrupt.
+  *         @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *         @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *         @arg USART_IT_TC:  Transmission complete interrupt.
+  *         @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *         @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *         @arg USART_IT_PE:  Parity Error interrupt.
+  *         @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0, itpos = 0, itmask = 0;
+  uint32_t usartxbase = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_MASK;
+  itmask = (((uint32_t)0x01) << itpos);
+
+  if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x04;
+  }
+  else if (usartreg == 0x03) /* The IT is in CR3 register */
+  {
+    usartxbase += 0x08;
+  }
+  else /* The IT is in CR1 register */
+  {
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables the specified USART's Request.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_Request: specifies the USART request.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_Request_TXFRQ: Transmit data flush ReQuest
+  *         @arg USART_Request_RXFRQ: Receive data flush ReQuest
+  *         @arg USART_Request_MMRQ: Mute Mode ReQuest
+  *         @arg USART_Request_SBKRQ: Send Break ReQuest
+  *         @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
+  * @param  NewState: new state of the DMA interface when reception error occurs.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_REQUEST(USART_Request));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
+       register.*/
+    USARTx->RQR |= USART_Request;
+  }
+  else
+  {
+    /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
+       register.*/
+    USARTx->RQR &= (uint32_t)~USART_Request;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's Overrun detection.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_OVRDetection: specifies the OVR detection status in case of OVR error.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error 
+  *          is asserted.
+  *         @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error 
+  *          is asserted.
+  * @retval None
+  */
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
+  
+  /* Clear the OVR detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
+  /* Set the new value for the OVR detection bit */
+  USARTx->CR3 |= USART_OVRDetection;
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *         @arg USART_FLAG_REACK:  Receive Enable acknowledge flag.
+  *         @arg USART_FLAG_TEACK:  Transmit Enable acknowledge flag.
+  *         @arg USART_FLAG_WUF:  Wake up flag.
+  *         @arg USART_FLAG_RWU:  Receive Wake up flag.
+  *         @arg USART_FLAG_SBK:  Send Break flag.
+  *         @arg USART_FLAG_CMF:  Character match flag.
+  *         @arg USART_FLAG_BUSY:  Busy flag.
+  *         @arg USART_FLAG_ABRF:  Auto baud rate flag.
+  *         @arg USART_FLAG_ABRE:  Auto baud rate error flag.
+  *         @arg USART_FLAG_EOBF:  End of block flag.
+  *         @arg USART_FLAG_RTOF:  Receive time out flag.
+  *         @arg USART_FLAG_nCTSS:  Inverted nCTS input bit status.
+  *         @arg USART_FLAG_CTS:  CTS Change flag.
+  *         @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *         @arg USART_FLAG_TXE:  Transmit data register empty flag.
+  *         @arg USART_FLAG_TC:  Transmission Complete flag.
+  *         @arg USART_FLAG_RXNE:  Receive data register not empty flag.
+  *         @arg USART_FLAG_IDLE:  Idle Line detection flag.
+  *         @arg USART_FLAG_ORE:  OverRun Error flag.
+  *         @arg USART_FLAG_NE:  Noise Error flag.
+  *         @arg USART_FLAG_FE:  Framing Error flag.
+  *         @arg USART_FLAG_PE:  Parity Error flag.
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+  
+  if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *         @arg USART_FLAG_WUF:  Wake up flag.
+  *         @arg USART_FLAG_CMF:  Character match flag.
+  *         @arg USART_FLAG_EOBF:  End of block flag.
+  *         @arg USART_FLAG_RTOF:  Receive time out flag.
+  *         @arg USART_FLAG_CTS:  CTS Change flag.
+  *         @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *         @arg USART_FLAG_TC:  Transmission Complete flag.
+  *         @arg USART_FLAG_IDLE:  IDLE line detected flag.
+  *         @arg USART_FLAG_ORE:  OverRun Error flag.
+  *         @arg USART_FLAG_NE: Noise Error flag.
+  *         @arg USART_FLAG_FE: Framing Error flag.
+  *         @arg USART_FLAG_PE:   Parity Errorflag.
+  *
+  * @note
+  *   - RXNE pending bit is cleared by a read to the USART_RDR register 
+  *     (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
+  *     (USART_RequestCmd()).
+  *   - TC flag can be also cleared by software sequence: a read operation to 
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *     to USART_TDR register (USART_SendData()).
+  *   - TXE flag is cleared by a write to the USART_TDR register 
+  *     (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
+  *     (USART_RequestCmd()).
+  *   - SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
+  *     (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+     
+  USARTx->ICR = USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *         This parameter can be one of the following values:
+  *         @arg USART_IT_WU:  Wake up interrupt.
+  *         @arg USART_IT_CM:  Character match interrupt.
+  *         @arg USART_IT_EOB:  End of block interrupt.
+  *         @arg USART_IT_RTO:  Receive time out interrupt.
+  *         @arg USART_IT_CTS:  CTS change interrupt.
+  *         @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *         @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *         @arg USART_IT_TC:  Transmission complete interrupt.
+  *         @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *         @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *         @arg USART_IT_ORE:  OverRun Error interrupt.
+  *         @arg USART_IT_NE:  Noise Error interrupt.
+  *         @arg USART_IT_FE:  Framing Error interrupt.
+  *         @arg USART_IT_PE:  Parity Error interrupt.
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0, usartreg = 0;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+  
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_MASK;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x10;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->ISR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: Select the USART peripheral. This parameter can be one of the 
+  *         following values: USART1 or USART2 or USART3 or UART4 or UART5.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *         @arg USART_IT_WU:  Wake up interrupt.
+  *         @arg USART_IT_CM:  Character match interrupt.
+  *         @arg USART_IT_EOB:  End of block interrupt.
+  *         @arg USART_IT_RTO:  Receive time out interrupt.
+  *         @arg USART_IT_CTS:  CTS change interrupt.
+  *         @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *         @arg USART_IT_TC:  Transmission complete interrupt.
+  *         @arg USART_IT_IDLE:  IDLE line detected interrupt.
+  *         @arg USART_IT_ORE:  OverRun Error interrupt.
+  *         @arg USART_IT_NE:  Noise Error interrupt.
+  *         @arg USART_IT_FE:  Framing Error interrupt.
+  *         @arg USART_IT_PE:  Parity Error interrupt.
+  * @note
+  *   - RXNE pending bit is cleared by a read to the USART_RDR register 
+  *     (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register USART_RQR
+  *     (USART_RequestCmd()).
+  *   - TC pending bit can be also cleared by software sequence: a read 
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *     operation to USART_TDR register (USART_SendData()).
+  *   - TXE pending bit is cleared by a write to the USART_TDR register 
+  *     (USART_SendData()) or by writing 1 to the TXFRQ in the register USART_RQR
+  *     (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+  
+  bitpos = USART_IT >> 0x10;
+  itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
+  USARTx->ICR = (uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c
new file mode 100644
index 0000000..6e7f25e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:
+  *           + Prescaler, Refresh window and Counter configuration
+  *           + WWDG activation
+  *           + Interrupts and flags management
+  *             
+  *  @verbatim
+  *    
+  ==============================================================================
+                           ##### WWDG features #####
+  ==============================================================================
+                                        
+    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
+        time period, unless the program refreshes the counter (downcounter) 
+        before to reach 0x3F value (i.e. a reset is generated when the counter
+        value rolls over from 0x40 to 0x3F). 
+    [..] An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This 
+        implies that the counter must be refreshed in a limited window.
+            
+    [..] Once enabled the WWDG cannot be disabled except by a system reset.
+         
+    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+        reset occurs.
+            
+    [..] The WWDG counter input clock is derived from the APB clock divided 
+        by a programmable prescaler.
+              
+    [..] WWDG counter clock = PCLK1 / Prescaler.
+    [..] WWDG timeout = (WWDG counter clock) * (counter value).
+                     
+    [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms. 
+
+                     ##### How to use this driver #####
+  ============================================================================== 
+    [..]         
+          (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 
+              function.
+            
+          (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
+                           
+          (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
+            
+          (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+             When the WWDG is enabled the counter value should be configured to 
+             a value greater than 0x40 to prevent generating an immediate reset.     
+            
+          (#) Optionally you can enable the Early wakeup interrupt which is 
+             generated when the counter reach 0x40.
+             Once enabled this interrupt cannot be disabled except by a system reset.
+                 
+          (#) Then the application program must refresh the WWDG counter at regular
+             intervals during normal operation to prevent an MCU reset, using
+             WWDG_SetCounter() function. This operation must occur only when
+             the counter value is lower than the refresh window value, 
+             programmed using WWDG_SetWindowValue().         
+
+  @endverbatim  
+                             
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------------------- WWDG registers bit mask ---------------------------- */
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
+#define BIT_MASK          ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+    ##### Prescaler, Refresh window and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_MASK;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset. 
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  WWDG->CFR |= WWDG_CFR_EWI;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset).  
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_MASK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ *  @brief   WWDG activation functions 
+ *
+@verbatim   
+  ==============================================================================
+                    ##### WWDG activation function #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset).
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+              ##### Interrupts and flags management functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/Release_Notes.html
new file mode 100644
index 0000000..4db70fc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/Release_Notes.html
@@ -0,0 +1,954 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head>
+<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
+<link rel="File-List" href="Release_Notes_for_STM32F2xx_StdPeriph_Driver_files/filelist.xml">
+<link rel="Edit-Time-Data" href="Release_Notes_for_STM32F45x_StdPeriph_Driver_files/editdata.mso"><!--[if !mso]>
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+</style>
+<![endif]-->
+
+
+
+<title>Release Notes for STM32F37x Standard Peripherals Library Drivers</title><!--[if gte mso 9]><xml>
+ <o:DocumentProperties>
+  <o:Author>STMicroelectronics</o:Author>
+  <o:LastAuthor>Raouf Hosni</o:LastAuthor>
+  <o:Revision>39</o:Revision>
+  <o:TotalTime>137</o:TotalTime>
+  <o:Created>2009-02-27T19:26:00Z</o:Created>
+  <o:LastSaved>2010-10-15T11:07:00Z</o:LastSaved>
+  <o:Pages>3</o:Pages>
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+
+<p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;"><o:p>&nbsp;</o:p></span></p>
+
+<div align="center">
+
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+ <tbody><tr style="">
+  <td style="padding: 0in;" valign="top">
+  <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+   <tbody><tr style="">
+    <td style="padding: 0in 5.4pt;" valign="top">
+    <p class="MsoNormal"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+    </td>
+   </tr>
+   <tr style="">
+    <td style="padding: 1.5pt;">
+    <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for STM32F37x Standard
+    Peripherals Library Drivers (StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
+    <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
+    2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+    <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+    </td>
+   </tr>
+  </tbody></table>
+  <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
+  <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+   <tbody><tr style="">
+    <td style="padding: 0in;" valign="top">
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+    <ol style="margin-top: 0in;" start="1" type="1">
+     <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#History">STM32F37x&nbsp;Standard Peripherals Library Drivers
+         update History</a><o:p></o:p></span></li>
+     <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#License">License</a><o:p></o:p></span></li>
+    </ol>
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F37x
+    Standard Peripherals Library Drivers&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 /20-September-2012<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">First official release for 
+<span style="font-style: italic; font-weight: bold;">STM32F37x devices</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt;"><o:p></o:p></span><ul style="margin-top: 0in;" type="disc">
+    </ul>
+    
+    
+    
+    
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+    complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
+    Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32f3" target="_blank">www.st.com/stm32f3</a></span></u></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p><p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+    </td>
+   </tr>
+  </tbody></table>
+  <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+  </td>
+ </tr>
+</tbody></table>
+
+</div>
+
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_adc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_adc.h
new file mode 100644
index 0000000..7503f14
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_adc.h
@@ -0,0 +1,449 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_adc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_ADC_H
+#define __STM32F37X_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+
+typedef struct
+{
+
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannels) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /*!< Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+
+#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
+
+#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigConv_T19_TRGO              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T19_CC3               ADC_CR2_EXTSEL_0
+#define ADC_ExternalTrigConv_T19_CC4               ADC_CR2_EXTSEL_1
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO               ADC_CR2_EXTSEL_2
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigConv_None                  ((uint32_t)0x000E0000)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T19_TRGO)  || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_T19_CC3)  || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_T19_CC4)  || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2)   || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO)  || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4)   || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11) || \
+                                   ((REGTRIG) == ADC_ExternalTrigConv_None))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align 
+  * @{
+  */
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ADC_CR2_ALIGN
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels 
+  * @{
+  */
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+#define ADC_Channel_18                              ((uint8_t)0x12)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0)  || \
+                                 ((CHANNEL) == ADC_Channel_1)  || \
+                                 ((CHANNEL) == ADC_Channel_2)  || \
+                                 ((CHANNEL) == ADC_Channel_3)  || \
+                                 ((CHANNEL) == ADC_Channel_4)  || \
+                                 ((CHANNEL) == ADC_Channel_5)  || \
+                                 ((CHANNEL) == ADC_Channel_6)  || \
+                                 ((CHANNEL) == ADC_Channel_7)  || \
+                                 ((CHANNEL) == ADC_Channel_8)  || \
+                                 ((CHANNEL) == ADC_Channel_9)  || \
+                                 ((CHANNEL) == ADC_Channel_10) || \
+                                 ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || \
+                                 ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || \
+                                 ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || \
+                                 ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time 
+  * @{
+  */
+
+#define ADC_SampleTime_1Cycles5                    ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                    ADC_SMPR2_SMP0_0
+#define ADC_SampleTime_13Cycles5                   ADC_SMPR2_SMP0_1
+#define ADC_SampleTime_28Cycles5                   ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                   ADC_SMPR2_SMP0_2
+#define ADC_SampleTime_55Cycles5                   ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                   ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                  ((uint8_t)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_7Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_13Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_41Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_55Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_71Cycles5) || \
+                                  ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */
+
+#define ADC_ExternalTrigInjecConv_T19_CC1           ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T19_CC2           ADC_CR2_JEXTSEL_0
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ADC_CR2_JEXTSEL_1
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4            ADC_CR2_JEXTSEL_2
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x00006000)
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T19_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T19_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)|| \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_None))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */
+
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ADC_CR1_AWDEN
+#define ADC_AnalogWatchdog_AllInjecEnable          ADC_CR1_JAWDEN
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0220)
+#define ADC_IT_AWD                                 ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_JEOC))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */
+
+#define ADC_FLAG_AWD                               ADC_SR_AWD
+#define ADC_FLAG_EOC                               ADC_SR_EOC
+#define ADC_FLAG_JEOC                              ADC_SR_JEOC
+#define ADC_FLAG_JSTRT                             ADC_SR_JSTRT
+#define ADC_FLAG_STRT                              ADC_SR_STRT
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t ADC_Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_can.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_can.h
new file mode 100644
index 0000000..4d32853
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_can.h
@@ -0,0 +1,640 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_can.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CAN_H
+#define __STM32F37X_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) ((PERIPH) == CAN1)
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+                                This parameter can be set either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. 
+                        This parameter can be a value of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted.
+                        This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. 
+                        This parameter can be a value of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED    CAN_InitStatus_Failed
+#define CANINITOK        CAN_InitStatus_Success
+/**
+  * @}
+  */
+
+/** @defgroup CAN_mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+ /**
+  * @defgroup CAN_operating_mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+                                    ((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_OperatingMode_status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_FilterNumber 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_FilterMode 
+  * @{
+  */
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_FilterScale 
+  * @{
+  */
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_FilterFIFO
+  * @{
+  */
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/* Legacy defines */
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+/* Legacy defines */
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
+/* Legacy defines */	
+#define CANTXFAILED                  CAN_TxStatus_Failed
+#define CANTXOK                      CAN_TxStatus_Ok
+#define CANTXPENDING                 CAN_TxStatus_Pending
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */	
+#define CANSLEEPFAILED   CAN_Sleep_Failed
+#define CANSLEEPOK       CAN_Sleep_Ok
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Error_Code_constants
+  * @{
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_CAN_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_cec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_cec.h
new file mode 100644
index 0000000..b1df688
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_cec.h
@@ -0,0 +1,301 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_cec.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the CEC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0XX_CEC_H
+#define __STM32F0XX_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+  
+/** 
+  * @brief  CEC Init structure definition  
+  */
+typedef struct
+{
+  uint32_t CEC_SignalFreeTime;     /*!< Specifies the CEC Signal Free Time configuration.
+                                   This parameter can be a value of @ref CEC_Signal_Free_Time */
+  uint32_t CEC_RxTolerance;        /*!< Specifies the CEC Reception Tolerance.
+                                   This parameter can be a value of @ref CEC_RxTolerance */
+  uint32_t CEC_StopReception;      /*!< Specifies the CEC Stop Reception.
+                                   This parameter can be a value of @ref CEC_Stop_Reception */
+  uint32_t CEC_BitRisingError;     /*!< Specifies the CEC Bit Rising Error generation.
+                                   This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
+  uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
+                                   This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
+  uint32_t CEC_BRDNoGen;           /*!< Specifies the CEC Broadcast Error generation.
+                                   This parameter can be a value of @ref CEC_BDR_No_Gen */
+  uint32_t CEC_SFTOption;          /*!< Specifies the CEC Signal Free Time option.
+                                   This parameter can be a value of @ref CEC_SFT_Option */
+
+}CEC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CEC_Signal_Free_Time
+  * @{
+  */
+#define CEC_SignalFreeTime_Standard     ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard     */
+#define CEC_SignalFreeTime_1T           ((uint32_t)0x00000001) /*!< CEC  1.5 nominal data bit periods */
+#define CEC_SignalFreeTime_2T           ((uint32_t)0x00000002) /*!< CEC  2.5 nominal data bit periods */
+#define CEC_SignalFreeTime_3T           ((uint32_t)0x00000003) /*!< CEC  3.5 nominal data bit periods */
+#define CEC_SignalFreeTime_4T           ((uint32_t)0x00000004) /*!< CEC  4.5 nominal data bit periods */
+#define CEC_SignalFreeTime_5T           ((uint32_t)0x00000005) /*!< CEC  5.5 nominal data bit periods */
+#define CEC_SignalFreeTime_6T           ((uint32_t)0x00000006) /*!< CEC  6.5 nominal data bit periods */
+#define CEC_SignalFreeTime_7T           ((uint32_t)0x00000007) /*!< CEC  7.5 nominal data bit periods */
+
+#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
+                                       ((TIME) == CEC_SignalFreeTime_1T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_2T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_3T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_4T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_5T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_6T)|| \
+                                       ((TIME) == CEC_SignalFreeTime_7T))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_RxTolerance
+  * @{
+  */
+#define CEC_RxTolerance_Standard        ((uint32_t)0x00000000) /*!< Standard Tolerance Margin              */
+#define CEC_RxTolerance_Extended        CEC_CFGR_RXTOL         /*!< Extended Tolerance Margin              */
+
+#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
+                                        ((TOLERANCE) == CEC_RxTolerance_Extended))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Stop_Reception
+  * @{
+  */
+#define CEC_StopReception_Off           ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE)    */
+#define CEC_StopReception_On            CEC_CFGR_BRESTP        /*!< RX Stop on bit Rising Error (BRE)       */
+
+#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
+                                          ((RECEPTION) == CEC_StopReception_Off))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Bit_Rising_Error_Generation
+  * @{
+  */
+#define CEC_BitRisingError_Off          ((uint32_t)0x00000000)  /*!< Bit Rising Error generation turned Off */
+#define CEC_BitRisingError_On           CEC_CFGR_BREGEN         /*!< Bit Rising Error generation turned On */
+
+#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
+                                        ((ERROR) == CEC_BitRisingError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Long_Bit_Error_Generation
+  * @{
+  */
+#define CEC_LongBitPeriodError_Off      ((uint32_t)0x00000000)  /*!< Long Bit Period Error generation turned Off */
+#define CEC_LongBitPeriodError_On       CEC_CFGR_LREGEN         /*!< Long Bit Period Error generation turned On */
+
+#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
+                                             ((ERROR) == CEC_LongBitPeriodError_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_SFT_Option
+  * @{
+  */
+#define CEC_SFTOption_Off              ((uint32_t)0x00000000)  /*!< SFT option turned Off                      */
+#define CEC_SFTOption_On               CEC_CFGR_SFTOPT         /*!< SFT option turned On                       */
+
+#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
+                                   ((OPTION) == CEC_SFTOption_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BDR_No_Gen
+  * @{
+  */
+
+#define CEC_BRDNoGen_Off      ((uint32_t)0x00000000)  /*!< Broadcast Bit Rising Error generation turned Off */
+#define CEC_BRDNoGen_On       CEC_CFGR_BRDNOGEN       /*!< Broadcast Bit Rising Error generation turned On  */
+ 
+#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
+                                        ((ERROR) == CEC_BRDNoGen_On))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Own_Address
+  * @{
+  */
+#define IS_CEC_ADDRESS(ADDRESS)         ((ADDRESS) < 0x10)
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Interrupt_Configuration_definition
+  * @{
+  */
+#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
+#define CEC_IT_TXERR                    CEC_IER_TXERRIE
+#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
+#define CEC_IT_TXEND                    CEC_IER_TXENDIE
+#define CEC_IT_TXBR                     CEC_IER_TXBRIE
+#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
+#define CEC_IT_LBPE                     CEC_IER_LBPEIE
+#define CEC_IT_SBPE                     CEC_IER_SBPEIE
+#define CEC_IT_BRE                      CEC_IER_BREIEIE
+#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
+#define CEC_IT_RXEND                    CEC_IER_RXENDIE
+#define CEC_IT_RXBR                     CEC_IER_RXBRIE
+
+#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
+
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
+                           ((IT) == CEC_IT_TXERR)|| \
+                           ((IT) == CEC_IT_TXUDR)|| \
+                           ((IT) == CEC_IT_TXEND)|| \
+                           ((IT) == CEC_IT_TXBR)|| \
+                           ((IT) == CEC_IT_ARBLST)|| \
+                           ((IT) == CEC_IT_RXACKE)|| \
+                           ((IT) == CEC_IT_LBPE)|| \
+                           ((IT) == CEC_IT_SBPE)|| \
+                           ((IT) == CEC_IT_BRE)|| \
+                           ((IT) == CEC_IT_RXOVR)|| \
+                           ((IT) == CEC_IT_RXEND)|| \
+                           ((IT) == CEC_IT_RXBR))
+/**
+  * @}
+  */
+
+/** @defgroup CEC_ISR_register_flags_definition
+  * @{
+  */
+#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR                  CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND                  CEC_ISR_TXEND
+#define CEC_FLAG_TXBR                   CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE                   CEC_ISR_LBPE
+#define CEC_FLAG_SBPE                   CEC_ISR_SBPE
+#define CEC_FLAG_BRE                    CEC_ISR_BRE
+#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND                  CEC_ISR_RXEND
+#define CEC_FLAG_RXBR                   CEC_ISR_RXBR
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
+                               ((FLAG) == CEC_FLAG_TXERR)|| \
+                               ((FLAG) == CEC_FLAG_TXUDR)|| \
+                               ((FLAG) == CEC_FLAG_TXEND)|| \
+                               ((FLAG) == CEC_FLAG_TXBR)|| \
+                               ((FLAG) == CEC_FLAG_ARBLST)|| \
+                               ((FLAG) == CEC_FLAG_RXACKE)|| \
+                               ((FLAG) == CEC_FLAG_LBPE)|| \
+                               ((FLAG) == CEC_FLAG_SBPE)|| \
+                               ((FLAG) == CEC_FLAG_BRE)|| \
+                               ((FLAG) == CEC_FLAG_RXOVR)|| \
+                               ((FLAG) == CEC_FLAG_RXEND)|| \
+                               ((FLAG) == CEC_FLAG_RXBR))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the CEC configuration to the default reset state *****/
+void CEC_DeInit(void);
+
+/* CEC_Initialization and Configuration functions *****************************/
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ListenModeCmd(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_OwnAddressClear(void);
+
+/* CEC_Data transfers functions ***********************************************/
+void CEC_SendData(uint8_t Data);
+uint8_t CEC_ReceiveData(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessage(void);
+
+/* CEC_Interrupts and flags management functions ******************************/
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+void CEC_ClearFlag(uint16_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_CEC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_comp.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_comp.h
new file mode 100644
index 0000000..d85d77a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_comp.h
@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_comp.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the COMP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_COMP_H
+#define __STM32F37X_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+
+  uint32_t COMP_InvertingInput;     /*!< Selects the inverting input of the comparator.
+                                          This parameter can be a value of @ref COMP_InvertingInput */
+
+  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
+                                          This parameter can be a value of @ref COMP_Output */
+
+  uint32_t COMP_OutputPol;           /*!< Selects the output polarity of the comparator.
+                                          This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
+                                          This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
+                                         and allows to adjust the speed/consumption.
+                                          This parameter can be a value of @ref COMP_Mode */
+
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP_Selection_COMP1                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
+#define COMP_Selection_COMP2                    ((uint32_t)0x00000010) /*!< COMP2 Selection */
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+                                    ((PERIPH) == COMP_Selection_COMP2))
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_1_2VREFINT          COMP_CSR_COMP1INSEL_0  /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_3_4VREFINT          COMP_CSR_COMP1INSEL_1  /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1OUT1            COMP_CSR_COMP1INSEL_2  /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC1OUT2            ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
+#define COMP_InvertingInput_DAC2OUT1            ((uint32_t)0x00000070) /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
+#define COMP_InvertingInput_IO                  ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_VREFINT)    || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1OUT1)   || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1OUT2)   || \
+                                        ((INPUT) == COMP_InvertingInput_DAC2OUT1)   || \
+                                        ((INPUT) == COMP_InvertingInput_IO))
+/**
+  * @}
+  */ 
+  
+/** @defgroup COMP_Output
+  * @{
+  */
+
+#define COMP_Output_None                  ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
+#define COMP_Output_TIM5IC4               ((uint32_t)0x00000600) /*!< COMP output connected to TIM5 Input Capture 4 */
+#define COMP_Output_TIM4IC1               ((uint32_t)0x00000200) /*!< COMP output connected to TIM4 Input Capture 1 */
+#define COMP_Output_TIM5OCREFCLR          COMP_CSR_COMP1OUTSEL   /*!< COMP output connected to TIM5 OCREF Clear */
+#define COMP_Output_TIM4OCREFCLR          ((uint32_t)0x00000300) /*!< COMP output connected to TIM4 OCREF Clear */
+#define COMP_Output_TIM15BKIN             COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM15 Break Input (BKIN) */
+#define COMP_Output_TIM16BKIN             COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM16 Break Input (BKIN) */
+#define COMP_Output_TIM2IC4               COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
+#define COMP_Output_TIM2OCREFCLR          ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
+#define COMP_Output_TIM3IC1               ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
+#define COMP_Output_TIM3OCREFCLR          COMP_CSR_COMP1OUTSEL   /*!< COMP output connected to TIM3 OCREF Clear */
+
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
+                                ((OUTPUT) == COMP_Output_TIM5IC4)      || \
+                                ((OUTPUT) == COMP_Output_TIM4IC1)      || \
+                                ((OUTPUT) == COMP_Output_TIM5OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TIM4OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TIM15BKIN)    || \
+                                ((OUTPUT) == COMP_Output_TIM16BKIN)    || \
+                                ((OUTPUT) == COMP_Output_TIM2IC4)      || \
+                                ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
+                                ((OUTPUT) == COMP_Output_TIM3IC1)      || \
+                                ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputPolarity
+  * @{
+  */
+#define COMP_OutputPol_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
+#define COMP_OutputPol_Inverted             COMP_CSR_COMP1POL       /*!< COMP output on GPIO is inverted */
+
+#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted)  || \
+                                 ((POL) == COMP_OutputPol_Inverted))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_Hysteresis
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the hysteresis level */
+#define COMP_Hysteresis_No                         0x00000000           /*!< No hysteresis */
+#define COMP_Hysteresis_Low                        COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
+#define COMP_Hysteresis_Medium                     COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
+#define COMP_Hysteresis_High                       COMP_CSR_COMP1HYST   /*!< Hysteresis level high */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Low) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
+                                           ((HYSTERESIS) == COMP_Hysteresis_High))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Mode
+  * @{
+  */
+/* Please refer to the electrical characteristics in the device datasheet for
+   the power consumption values */
+#define COMP_Mode_HighSpeed                     0x00000000           /*!< High Speed */
+#define COMP_Mode_MediumSpeed                   COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
+#define COMP_Mode_LowPower                      COMP_CSR_COMP1MODE_1 /*!< Low power mode */
+#define COMP_Mode_UltraLowPower                 COMP_CSR_COMP1MODE   /*!< Ultra-low power mode */
+
+#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_UltraLowPower) || \
+                               ((MODE) == COMP_Mode_LowPower)      || \
+                               ((MODE) == COMP_Mode_MediumSpeed)   || \
+                               ((MODE) == COMP_Mode_HighSpeed))
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel
+  * @{
+  */ 
+/* When output polarity is not inverted, comparator output is high when
+   the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OutputLevel_High                   COMP_CSR_COMP1OUT
+/* When output polarity is not inverted, comparator output is low when
+   the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
+void COMP_SwitchCmd(FunctionalState NewState);
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* COMP configuration locking function ****************************************/
+void COMP_LockConfig(uint32_t COMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dac.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dac.h
new file mode 100644
index 0000000..650544e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dac.h
@@ -0,0 +1,314 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_dac.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_DAC_H
+#define __STM32F37X_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+ 
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+  
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
+                                   ((PERIPH) == DAC2))
+
+#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+  
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DACx_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_T18_TRGO               ((uint32_t)0x0000001C) /*!< TIM18 TRGO selected as external conversion trigger for DAC2 channel1 */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T18_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+                                 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */ 
+  
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)   
+  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(DAC_TypeDef* DACx);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_DAC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dbgmcu.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dbgmcu.h
new file mode 100644
index 0000000..6d5d656
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dbgmcu.h
@@ -0,0 +1,113 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_DBGMCU_H
+#define __STM32F37X_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */ 
+#define DBGMCU_SLEEP                          DBGMCU_CR_DBG_SLEEP
+#define DBGMCU_STOP                           DBGMCU_CR_DBG_STOP
+#define DBGMCU_STANDBY                        DBGMCU_CR_DBG_STANDBY
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP
+#define DBGMCU_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP
+#define DBGMCU_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP
+#define DBGMCU_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP
+#define DBGMCU_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP
+#define DBGMCU_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP
+#define DBGMCU_TIM12_STOP            DBGMCU_APB1_FZ_DBG_TIM12_STOP
+#define DBGMCU_TIM13_STOP            DBGMCU_APB1_FZ_DBG_TIM13_STOP
+#define DBGMCU_TIM14_STOP            DBGMCU_APB1_FZ_DBG_TIM14_STOP
+#define DBGMCU_TIM18_STOP            DBGMCU_APB1_FZ_DBG_TIM18_STOP
+#define DBGMCU_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP
+#define DBGMCU_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP
+#define DBGMCU_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
+#define DBGMCU_CAN1_STOP             DBGMCU_APB1_FZ_DBG_CAN1_STOP
+
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE000) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM15_STOP            DBGMCU_APB2_FZ_DBG_TIM15_STOP
+#define DBGMCU_TIM16_STOP            DBGMCU_APB2_FZ_DBG_TIM16_STOP
+#define DBGMCU_TIM17_STOP            DBGMCU_APB2_FZ_DBG_TIM17_STOP
+#define DBGMCU_TIM19_STOP            DBGMCU_APB2_FZ_DBG_TIM19_STOP
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFC3) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_DBGMCU_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dma.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dma.h
new file mode 100644
index 0000000..a9fa181
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_dma.h
@@ -0,0 +1,436 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_dma.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_DMA_H
+#define __STM32F37X_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structures definition
+  */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction     */
+
+  uint16_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction.    */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode     */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size        */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size            */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level              */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory            */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+  
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */
+
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST              DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+                         ((DIR) == DMA_DIR_PeripheralDST))
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */
+
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable           DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+                                            ((STATE) == DMA_PeripheralInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */
+
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable               DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+                                        ((STATE) == DMA_MemoryInc_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */
+
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define DMA_Mode_Circular                  DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              DMA_CCR_PL
+#define DMA_Priority_High                  DMA_CCR_PL_1
+#define DMA_Priority_Medium                DMA_CCR_PL_0
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory 
+  * @{
+  */
+
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition
+  * @{
+  */
+
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+  
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions******************************************************/ 
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_exti.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_exti.h
new file mode 100644
index 0000000..2f1bad9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_exti.h
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_exti.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_EXTI_H
+#define __STM32F37X_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+  * @brief  EXTI Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0  */
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1  */
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2  */
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3  */
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4  */
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5  */
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6  */
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7  */
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8  */
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9  */
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 
+                                                      Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< Internal interrupt line 17 
+                                                      Connected to the RTC Alarm 
+                                                      event */
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< Internal interrupt line 18 
+                                                      Connected to the USB Device
+                                                      Wakeup from suspend event */
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< Internal interrupt line 19
+                                                      Connected to the RTC Tamper
+                                                      and Time Stamp events */
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< Internal interrupt line 20
+                                                      Connected to the RTC wakeup
+                                                      event */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< Internal interrupt line 21
+                                                      Connected to the Comparator 1
+                                                      event */
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< Internal interrupt line 22
+                                                      Connected to the Comparator 2
+                                                      event */
+#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< Internal interrupt line 23
+                                                      Connected to the I2C1 wakeup
+                                                      event */
+#define EXTI_Line24      ((uint32_t)0x01000000)  /*!< Internal interrupt line 24
+                                                      Connected to the I2C2 wakeup
+                                                      event */
+#define EXTI_Line25      ((uint32_t)0x02000000)  /*!< Internal interrupt line 25
+                                                      Connected to the USART1 wakeup
+                                                      event */
+#define EXTI_Line26      ((uint32_t)0x04000000)  /*!< Internal interrupt line 26
+                                                      Connected to the USART2 wakeup
+                                                      event */
+#define EXTI_Line27      ((uint32_t)0x08000000)  /*!< Internal interrupt line 27
+                                                      Connected to the CEC wakeup
+                                                      event */
+#define EXTI_Line28      ((uint32_t)0x10000000)  /*!< Internal interrupt line 28
+                                                      Connected to the USART3 wakeup
+                                                      event */
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x00) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                ((LINE) == EXTI_Line22))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_EXTI_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_flash.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_flash.h
new file mode 100644
index 0000000..6a194b0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_flash.h
@@ -0,0 +1,412 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_flash.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_FLASH_H
+#define __STM32F37X_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief FLASH Status  
+  */ 
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup FLASH_Latency 
+  * @{
+  */ 
+#define FLASH_Latency_0                ((uint8_t)0x0000)    /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                FLASH_ACR_LATENCY_0  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                FLASH_ACR_LATENCY_1  /*!< FLASH Two Latency cycles */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+   
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE  /*!< End of programming interrupt source */
+#define FLASH_IT_ERR                   FLASH_CR_ERRIE  /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+  * @}
+  */
+/** @defgroup FLASH_Address 
+  * @{
+  */
+  
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_DATA_ADDRESS 
+  * @{
+  */  
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Write_Protection 
+  * @{
+  */
+  
+
+#define OB_WRP_Pages0to1               ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_Pages2to3               ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_Pages4to5               ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_Pages6to7               ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_Pages8to9               ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_Pages10to11             ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_Pages12to13             ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_Pages14to15             ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_Pages16to17             ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_Pages18to19             ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_Pages20to21             ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_Pages22to23             ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_Pages24to25             ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_Pages26to27             ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_Pages28to29             ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_Pages30to31             ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_Pages32to33             ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_Pages34to35             ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_Pages36to37             ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_Pages38to39             ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_Pages40to41             ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_Pages42to43             ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_Pages44to45             ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_Pages46to47             ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_Pages48to49             ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_Pages50to51             ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_Pages52to53             ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_Pages54to55             ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_Pages56to57             ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_Pages58to59             ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_Pages60to61             ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define OB_WRP_Pages62to127            ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
+
+#define OB_WRP_AllPages                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection 
+  * @{
+  */ 
+
+/** 
+  * @brief  FLASH_Read_Protection_Level  
+  */ 
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 
+                                                it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint8_t)0x01)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_BOOT1
+  * @{
+  */
+
+#define OB_BOOT1_RESET                 ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET                   ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
+  * @{
+  */
+
+#define OB_VDDA_ANALOG_ON              ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF             ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+  * @}
+  */ 
+/** @defgroup FLASH_Option_Bytes_VDD_Analog_Monitoring
+  * @{
+  */
+
+#define OB_VDD_SD12_ON              ((uint8_t)0x80) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDD_SD12_OFF             ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDD_SD12(MODE) (((MODE) == OB_VDD_SD12_ON) || ((MODE) == OB_VDD_SD12_OFF))
+
+/**
+  * @}
+  */     
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable 
+  * @{
+  */
+
+#define OB_SRAM_PARITY_SET              ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET            ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+  * @}
+  */ 
+      
+/** @defgroup FLASH_Flags 
+  * @{
+  */ 
+
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY     /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR               FLASH_SR_PGERR   /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP     /*!< FLASH End of Programming flag */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys 
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+#define FLASH_OPTKEY1            FLASH_KEY1
+#define FLASH_OPTKEY2            FLASH_KEY2
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Timeout_definition 
+  * @{
+  */ 
+
+#define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x000B0000) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Legacy 
+  * @{
+  */
+#define FLASH_WRProt_Pages0to1	       OB_WRP_Pages0to1
+#define FLASH_WRProt_Pages2to3	       OB_WRP_Pages2to3
+#define FLASH_WRProt_Pages4to5	       OB_WRP_Pages4to5
+#define FLASH_WRProt_Pages6to7	       OB_WRP_Pages6to7
+#define FLASH_WRProt_Pages8to9	       OB_WRP_Pages8to9
+#define FLASH_WRProt_Pages10to11	   OB_WRP_Pages10to11
+#define FLASH_WRProt_Pages12to13	   OB_WRP_Pages12to13
+#define FLASH_WRProt_Pages14to15	   OB_WRP_Pages14to15
+#define FLASH_WRProt_Pages16to17	   OB_WRP_Pages16to17
+#define FLASH_WRProt_Pages18to19	   OB_WRP_Pages18to19
+#define FLASH_WRProt_Pages20to21	   OB_WRP_Pages20to21
+#define FLASH_WRProt_Pages22to23	   OB_WRP_Pages22to23
+#define FLASH_WRProt_Pages24to25	   OB_WRP_Pages24to25
+#define FLASH_WRProt_Pages26to27	   OB_WRP_Pages26to27
+#define FLASH_WRProt_Pages28to29	   OB_WRP_Pages28to29
+#define FLASH_WRProt_Pages30to31	   OB_WRP_Pages30to31
+#define FLASH_WRProt_Pages32to33	   OB_WRP_Pages32to33
+#define FLASH_WRProt_Pages34to35	   OB_WRP_Pages34to35
+#define FLASH_WRProt_Pages36to37	   OB_WRP_Pages36to37
+#define FLASH_WRProt_Pages38to39	   OB_WRP_Pages38to39
+#define FLASH_WRProt_Pages40to41	   OB_WRP_Pages40to41
+#define FLASH_WRProt_Pages42to43	   OB_WRP_Pages42to43
+#define FLASH_WRProt_Pages44to45	   OB_WRP_Pages44to45
+#define FLASH_WRProt_Pages46to47	   OB_WRP_Pages46to47
+#define FLASH_WRProt_Pages48to49	   OB_WRP_Pages48to49
+#define FLASH_WRProt_Pages50to51	   OB_WRP_Pages50to51
+#define FLASH_WRProt_Pages52to53	   OB_WRP_Pages52to53
+#define FLASH_WRProt_Pages54to55	   OB_WRP_Pages54to55
+#define FLASH_WRProt_Pages56to57	   OB_WRP_Pages56to57
+#define FLASH_WRProt_Pages58to59	   OB_WRP_Pages58to59
+#define FLASH_WRProt_Pages60to61	   OB_WRP_Pages60to61
+#define FLASH_WRProt_Pages62to127	   OB_WRP_Pages62to127
+
+#define FLASH_WRProt_AllPages          OB_WRP_AllPages
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+/* FLASH Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_VDD_SD12Config(uint8_t OB_VDD_SD12);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* FLASH Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+
+/** @defgroup FLASH_Legacy 
+  * @{
+  */
+#define FLASH_EraseOptionBytes               FLASH_OB_Erase
+#define FLASH_EnableWriteProtection	         FLASH_OB_EnableWRP
+#define FLASH_UserOptionByteConfig	         FLASH_OB_UserConfig
+#define FLASH_ProgramOptionByteData          FLASH_OB_ProgramData
+#define FLASH_GetUserOptionByte	             FLASH_OB_GetUser
+#define FLASH_GetWriteProtectionOptionByte   FLASH_OB_GetWRP
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_FLASH_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_gpio.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_gpio.h
new file mode 100644
index 0000000..1b19dca
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_gpio.h
@@ -0,0 +1,387 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_gpio.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the GPIO 
+  *          firmware library. 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_GPIO_H
+#define __STM32F37X_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+ 
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF))  
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                     ((PERIPH) == GPIOB) || \
+                                     ((PERIPH) == GPIOD))
+/** @defgroup Configuration_Mode_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+  * @}
+  */
+
+/** @defgroup Output_type_enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+  * @}
+  */
+
+/** @defgroup Output_Maximum_frequency_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_Speed_Level_1  = 0x01, /*!< Medium Speed */
+  GPIO_Speed_Level_2  = 0x02, /*!< Fast Speed   */
+  GPIO_Speed_Level_3  = 0x03  /*!< High Speed   */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+                              ((SPEED) == GPIO_Speed_Level_3))
+/**
+  * @}
+  */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration 
+  * @{
+  */
+typedef enum
+{
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+/**
+  * @}
+  */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+  * @{
+  */
+typedef enum
+{
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+  * @}
+  */
+
+/**
+  * @brief  GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef   */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef  */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef  */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef   */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected    */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected    */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected    */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected    */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected    */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected    */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected    */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected    */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected    */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected    */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected   */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected   */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected   */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected   */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected   */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected   */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternate_function_selection_define 
+  * @{
+  */
+
+/** 
+  * @brief  AF 0 selection
+  */
+#define GPIO_AF_0            ((uint8_t)0x00) /* MCO, JTMS-SWDAT, JTCK-SWCLK, JTDI,
+                                               JTDO, JTRST, TRACECLK, TRACED, TRACEWO */
+/**
+  * @brief  AF 1 selection
+  */
+#define GPIO_AF_1            ((uint8_t)0x01) /* TIM2, TIM15, TIM16, TIM17, OUT */
+
+/**
+  * @brief  AF 2 selection
+  */
+#define GPIO_AF_2            ((uint8_t)0x02) /* TIM3, TIM4, TIM5, TIM13, TIM14, TIM19 */
+
+/**
+  * @brief  AF 3 selection
+  */
+#define GPIO_AF_3            ((uint8_t)0x03) /* Touch */
+
+/**
+  * @brief  AF 4 selection
+  */
+#define GPIO_AF_4            ((uint8_t)0x04) /* I2C1, I2C2 */
+
+/**
+  * @brief  AF 5 selection
+  */
+#define GPIO_AF_5            ((uint8_t)0x05) /* SPI1, SPI2, IR_OUT */
+
+/** 
+  * @brief  AF 6 selection
+  */
+#define GPIO_AF_6            ((uint8_t)0x06) /* SPI1, SPI3, CEC, IR_OUT */
+
+/** 
+  * @brief  AF 7 selection
+  */
+#define GPIO_AF_7            ((uint8_t)0x07) /* USART1, USART2, USART3, CAN, CEC*/
+
+/**
+  * @brief  AF 8 selection
+  */
+#define GPIO_AF_8            ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT */
+
+/**
+  * @brief  AF 9 selection
+  */
+#define GPIO_AF_9            ((uint8_t)0x09) /* CAN, TIM12, TIM13, TIM14, TIM15 */
+
+/**
+  * @brief  AF 10 selection
+  */
+#define GPIO_AF_10            ((uint8_t)0x0A) /* TIM2, TIM3, TIM4, TIM12, TIM17 */
+
+/**
+  * @brief  AF 11 selection
+  */
+#define GPIO_AF_11            ((uint8_t)0x0B) /* TIM19 */
+
+/**
+  * @brief  AF 14 selection
+  */
+#define GPIO_AF_14            ((uint8_t)0x0E) /* USBDM, USBDP */
+
+/**
+  * @brief  AF 15 selection
+  */
+#define GPIO_AF_15            ((uint8_t)0x0F) /* OUT */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
+                          ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
+                          ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
+                          ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
+                          ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
+                          ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
+                          ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Speed_Legacy 
+  * @{
+  */
+
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1   /*!< Fast Speed:10MHz   */
+#define GPIO_Speed_2MHz  GPIO_Speed_Level_2   /*!< Medium Speed:2MHz  */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3   /*!< High Speed:50MHz   */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_GPIO_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_i2c.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_i2c.h
new file mode 100644
index 0000000..2cdb3eb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_i2c.h
@@ -0,0 +1,476 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_i2c.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the I2C firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_I2C_H
+#define __STM32F37X_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  I2C Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t I2C_Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                         This parameter must be set by referring to I2C_Timing_Config_Tool*/
+
+  uint32_t I2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
+                                         This parameter can be a value of @ref I2C_Analog_Filter*/
+
+  uint32_t I2C_DigitalFilter;       /*!< Configures the digital noise filter.
+                                         This parameter can be a number between 0x00 and 0x0F*/
+
+  uint32_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode*/
+
+  uint32_t I2C_OwnAddress1;         /*!< Specifies the device own address 1.
+                                         This parameter can be a 7-bit or 10-bit address*/
+
+  uint32_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement*/
+
+  uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address*/
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
+                                         ((PERIPH) == I2C2))
+
+/** @defgroup I2C_Analog_Filter 
+  * @{
+  */
+
+#define I2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable        I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_AnalogFilter_Enable) || \
+                                         ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+  * @}
+  */
+     
+/** @defgroup I2C_Digital_Filter
+  * @{
+  */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice            I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost              I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2C) || \
+                                         ((MODE) == I2C_Mode_SMBusDevice) || \
+                                         ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint32_t)0x00000000)
+#define I2C_Ack_Disable                 I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK)                 (((ACK) == I2C_Ack_Enable) || \
+                                         ((ACK) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit   I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_own_address1
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define I2C_Direction_Transmitter       ((uint16_t)0x0000)
+#define I2C_Direction_Receiver          ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                         ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DMA_transfer_requests 
+  * @{
+  */
+
+#define I2C_DMAReq_Tx                   I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx                   I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_slave_address
+  * @{
+  */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_own_address2
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address2_mask
+  * @{
+  */
+
+#define I2C_OA2_NoMask                  ((uint8_t)0x00)
+#define I2C_OA2_Mask01                  ((uint8_t)0x01)                 
+#define I2C_OA2_Mask02                  ((uint8_t)0x02)
+#define I2C_OA2_Mask03                  ((uint8_t)0x03)
+#define I2C_OA2_Mask04                  ((uint8_t)0x04)
+#define I2C_OA2_Mask05                  ((uint8_t)0x05)
+#define I2C_OA2_Mask06                  ((uint8_t)0x06)
+#define I2C_OA2_Mask07                  ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NoMask) || \
+                                         ((MASK) == I2C_OA2_Mask01) || \
+                                         ((MASK) == I2C_OA2_Mask02) || \
+                                         ((MASK) == I2C_OA2_Mask03) || \
+                                         ((MASK) == I2C_OA2_Mask04) || \
+                                         ((MASK) == I2C_OA2_Mask05) || \
+                                         ((MASK) == I2C_OA2_Mask06) || \
+                                         ((MASK) == I2C_OA2_Mask07))  
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_timeout
+  * @{
+  */
+
+#define IS_I2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR            ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR           ((uint8_t)0x14)
+#define I2C_Register_ISR                ((uint8_t)0x18)
+#define I2C_Register_ICR                ((uint8_t)0x1C)
+#define I2C_Register_PECR               ((uint8_t)0x20)
+#define I2C_Register_RXDR               ((uint8_t)0x24)
+#define I2C_Register_TXDR               ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CR1) || \
+                                         ((REGISTER) == I2C_Register_CR2) || \
+                                         ((REGISTER) == I2C_Register_OAR1) || \
+                                         ((REGISTER) == I2C_Register_OAR2) || \
+                                         ((REGISTER) == I2C_Register_TIMINGR) || \
+                                         ((REGISTER) == I2C_Register_TIMEOUTR) || \
+                                         ((REGISTER) == I2C_Register_ISR) || \
+                                         ((REGISTER) == I2C_Register_ICR) || \
+                                         ((REGISTER) == I2C_Register_PECR) || \
+                                         ((REGISTER) == I2C_Register_RXDR) || \
+                                         ((REGISTER) == I2C_Register_TXDR))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+#define  I2C_FLAG_TXE                   I2C_ISR_TXE
+#define  I2C_FLAG_TXIS                  I2C_ISR_TXIS
+#define  I2C_FLAG_RXNE                  I2C_ISR_RXNE
+#define  I2C_FLAG_ADDR                  I2C_ISR_ADDR
+#define  I2C_FLAG_NACKF                 I2C_ISR_NACKF
+#define  I2C_FLAG_STOPF                 I2C_ISR_STOPF
+#define  I2C_FLAG_TC                    I2C_ISR_TC
+#define  I2C_FLAG_TCR                   I2C_ISR_TCR
+#define  I2C_FLAG_BERR                  I2C_ISR_BERR
+#define  I2C_FLAG_ARLO                  I2C_ISR_ARLO
+#define  I2C_FLAG_OVR                   I2C_ISR_OVR
+#define  I2C_FLAG_PECERR                I2C_ISR_PECERR
+#define  I2C_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
+#define  I2C_FLAG_ALERT                 I2C_ISR_ALERT
+#define  I2C_FLAG_BUSY                  I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+                                         ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+                                         ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+                                         ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+                                         ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+                                         ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+                                         ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+                                         ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define  I2C_IT_TXIS                    I2C_ISR_TXIS
+#define  I2C_IT_RXNE                    I2C_ISR_RXNE
+#define  I2C_IT_ADDR                    I2C_ISR_ADDR
+#define  I2C_IT_NACKF                   I2C_ISR_NACKF
+#define  I2C_IT_STOPF                   I2C_ISR_STOPF
+#define  I2C_IT_TC                      I2C_ISR_TC
+#define  I2C_IT_TCR                     I2C_ISR_TCR
+#define  I2C_IT_BERR                    I2C_ISR_BERR
+#define  I2C_IT_ARLO                    I2C_ISR_ARLO
+#define  I2C_IT_OVR                     I2C_ISR_OVR
+#define  I2C_IT_PECERR                  I2C_ISR_PECERR
+#define  I2C_IT_TIMEOUT                 I2C_ISR_TIMEOUT
+#define  I2C_IT_ALERT                   I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+                               
+#define IS_I2C_GET_IT(IT)               (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+                                         ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+                                         ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+                                         ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+                                         ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+                                         ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+                                         ((IT) == I2C_IT_ALERT))
+                               
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ReloadEndMode_definition 
+  * @{
+  */
+
+#define  I2C_Reload_Mode                I2C_CR2_RELOAD
+#define  I2C_AutoEnd_Mode               I2C_CR2_AUTOEND
+#define  I2C_SoftEnd_Mode               ((uint32_t)0x00000000)
+
+                              
+#define IS_RELOAD_END_MODE(MODE)        (((MODE) == I2C_Reload_Mode) || \
+                                         ((MODE) == I2C_AutoEnd_Mode) || \
+                                         ((MODE) == I2C_SoftEnd_Mode))
+                               
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_StartStopMode_definition 
+  * @{
+  */
+
+#define  I2C_No_StartStop                 ((uint32_t)0x00000000)
+#define  I2C_Generate_Stop                I2C_CR2_STOP
+#define  I2C_Generate_Start_Read          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_Generate_Start_Write         I2C_CR2_START
+
+                              
+#define IS_START_STOP_MODE(MODE)        (((MODE) == I2C_Generate_Stop) || \
+                                         ((MODE) == I2C_Generate_Start_Read) || \
+                                         ((MODE) == I2C_Generate_Start_Write) || \
+                                         ((MODE) == I2C_No_StartStop))
+                               
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/*  SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_I2C_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_iwdg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_iwdg.h
new file mode 100644
index 0000000..dc3fc94
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_iwdg.h
@@ -0,0 +1,140 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_IWDG_H
+#define __STM32F37X_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+
+#define IWDG_FLAG_PVU               IWDG_SR_PVU
+#define IWDG_FLAG_RVU               IWDG_SR_RVU
+#define IWDG_FLAG_WVU               IWDG_SR_WVU
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)  || \
+                            ((FLAG) == IWDG_FLAG_WVU))
+
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_misc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_misc.h
new file mode 100644
index 0000000..9beedb6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_misc.h
@@ -0,0 +1,204 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_misc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_MISC_H
+#define __STM32F37X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32f37x.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+
+/**  
+  *
+@verbatim
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority
+  ============================================================================================================================
+@endverbatim
+*/
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_pwr.h
new file mode 100644
index 0000000..9af54d2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_pwr.h
@@ -0,0 +1,203 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_pwr.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_PWR_H
+#define __STM32F37X_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level
+  * @{
+  */ 
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7 
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_WakeUp_Pins
+  * @{
+  */
+
+#define PWR_WakeUpPin_1                 PWR_CSR_EWUP1
+#define PWR_WakeUpPin_2                 PWR_CSR_EWUP2
+#define PWR_WakeUpPin_3                 PWR_CSR_EWUP3
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
+                                ((PIN) == PWR_WakeUpPin_2) || \
+                                ((PIN) == PWR_WakeUpPin_3))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SDADC_Analog
+  * @{
+  */
+
+#define PWR_SDADCAnalog_1                 PWR_CR_SDADC1EN
+#define PWR_SDADCAnalog_2                 PWR_CR_SDADC2EN
+#define PWR_SDADCAnalog_3                 PWR_CR_SDADC3EN
+#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADCAnalog_1) || \
+                                     ((SDADC) == PWR_SDADCAnalog_2) || \
+                                     ((SDADC) == PWR_SDADCAnalog_3))
+/**
+  * @}
+  */
+ 
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/ 
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration function  ****************************************/ 
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* SDADC Analog configuration function  ****************************************/ 
+void PWR_SDADCAnalogCmd(uint32_t PWR_SDADCAnalog, FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_rcc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_rcc.h
new file mode 100644
index 0000000..8bd575f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_rcc.h
@@ -0,0 +1,603 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_rcc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the RCC 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_RCC_H
+#define __STM32F37X_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK1_Frequency;
+  uint32_t PCLK2_Frequency;
+  uint32_t ADCCLK_Frequency;
+  uint32_t SDADCCLK_Frequency;
+  uint32_t CECCLK_Frequency;
+  uint32_t I2C1CLK_Frequency;
+  uint32_t I2C2CLK_Frequency;
+  uint32_t USART1CLK_Frequency;
+  uint32_t USART2CLK_Frequency;
+  uint32_t USART3CLK_Frequency;
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup RCC_HSE_configuration 
+  * @{
+  */
+
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+  * @}
+  */ 
+ 
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
+  */
+
+#define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
+#define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_PREDIV1
+ 
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_PLL_Multiplication_Factor 
+  * @{
+  */
+
+#define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
+#define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
+#define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
+#define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
+#define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
+#define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
+#define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
+#define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
+#define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
+#define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
+#define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
+#define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
+#define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
+#define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
+#define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                             ((MUL) == RCC_PLLMul_16))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PREDIV1_division_factor
+  * @{
+  */
+#define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
+#define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
+#define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
+#define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
+#define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
+#define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
+#define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
+#define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
+#define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
+#define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
+#define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
+#define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
+#define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
+#define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
+#define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
+#define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
+
+#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+                                 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+  * @}
+  */
+ 
+/** @defgroup RCC_System_Clock_Source 
+  * @{
+  */
+
+#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+
+#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_APB1_APB2_Clock_Source
+  * @{
+  */
+
+#define RCC_HCLK_Div1                    RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_Div2                    RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_Div4                    RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_Div8                    RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_Div16                   RCC_CFGR_PPRE1_DIV16
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_ADC_clock_source 
+  * @{
+  */
+
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_SDADC_clock_source 
+  * @{
+  */
+
+#define RCC_SDADCCLK_SYSCLK_Div2                   ((uint32_t)0x80000000)
+#define RCC_SDADCCLK_SYSCLK_Div4                   ((uint32_t)0x88000000)
+#define RCC_SDADCCLK_SYSCLK_Div6                   ((uint32_t)0x90000000)
+#define RCC_SDADCCLK_SYSCLK_Div8                   ((uint32_t)0x98000000)
+#define RCC_SDADCCLK_SYSCLK_Div10                  ((uint32_t)0xA0000000)
+#define RCC_SDADCCLK_SYSCLK_Div12                  ((uint32_t)0xA8000000)
+#define RCC_SDADCCLK_SYSCLK_Div14                  ((uint32_t)0xB0000000)
+#define RCC_SDADCCLK_SYSCLK_Div16                  ((uint32_t)0xB8000000)
+#define RCC_SDADCCLK_SYSCLK_Div20                  ((uint32_t)0xC0000000)
+#define RCC_SDADCCLK_SYSCLK_Div24                  ((uint32_t)0xC8000000)
+#define RCC_SDADCCLK_SYSCLK_Div28                  ((uint32_t)0xD0000000)
+#define RCC_SDADCCLK_SYSCLK_Div32                  ((uint32_t)0xD8000000)
+#define RCC_SDADCCLK_SYSCLK_Div36                  ((uint32_t)0xE0000000)
+#define RCC_SDADCCLK_SYSCLK_Div40                  ((uint32_t)0xE8000000)
+#define RCC_SDADCCLK_SYSCLK_Div44                  ((uint32_t)0xF0000000)
+#define RCC_SDADCCLK_SYSCLK_Div48                  ((uint32_t)0xF8000000)
+
+#define IS_RCC_SDADCCLK(SDADCCLK) (((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div2) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div4) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div6) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div8) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div10) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div12) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div14) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div16) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div20) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div24) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div28) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div32) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div36) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div40) || \
+                                   ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div44) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div48))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CEC_clock_source 
+  * @{
+  */
+
+#define RCC_CECCLK_HSI_Div244            ((uint32_t)0x00000000)
+#define RCC_CECCLK_LSE                   RCC_CFGR3_CECSW
+
+#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_I2C_clock_source 
+  * @{
+  */
+
+#define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
+#define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
+
+#define RCC_I2C2CLK_HSI                   ((uint32_t)0x10000000)
+#define RCC_I2C2CLK_SYSCLK                ((uint32_t)0x10000020)
+
+#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
+                               ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_USART_clock_source 
+  * @{
+  */
+
+#define RCC_USART1CLK_PCLK                  ((uint32_t)0x10000000)
+#define RCC_USART1CLK_SYSCLK                ((uint32_t)0x10000001)
+#define RCC_USART1CLK_LSE                   ((uint32_t)0x10000002)
+#define RCC_USART1CLK_HSI                   ((uint32_t)0x10000003)
+
+#define RCC_USART2CLK_PCLK                  ((uint32_t)0x20000000)
+#define RCC_USART2CLK_SYSCLK                ((uint32_t)0x20010000)
+#define RCC_USART2CLK_LSE                   ((uint32_t)0x20020000)
+#define RCC_USART2CLK_HSI                   ((uint32_t)0x20030000)
+
+#define RCC_USART3CLK_PCLK                  ((uint32_t)0x30000000)
+#define RCC_USART3CLK_SYSCLK                ((uint32_t)0x30040000)
+#define RCC_USART3CLK_LSE                   ((uint32_t)0x30080000)
+#define RCC_USART3CLK_HSI                   ((uint32_t)0x300C0000)
+
+#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
+                                   ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
+                                   ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
+                                   ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI))
+
+/**
+  * @}
+  */
+       
+/** @defgroup RCC_Interrupt_Source 
+  * @{
+  */
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
+
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+                           
+
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_LSE_Configuration 
+  * @{
+  */
+
+#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_LSE_ON                       RCC_BDCR_LSEON
+#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+
+#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
+#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
+#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
+
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Drive_Configuration 
+  * @{
+  */
+
+#define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
+#define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
+#define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
+#define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
+#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
+                                 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
+/**
+  * @}
+  */
+  
+/** @defgroup RCC_AHB_Peripherals 
+  * @{
+  */
+
+#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
+#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
+#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
+#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
+#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
+#define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
+#define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
+#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
+#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
+#define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
+#define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
+#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
+
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripherals 
+  * @{
+  */
+
+#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
+#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
+#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
+#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
+#define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
+#define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
+#define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
+#define RCC_APB2Periph_TIM19             RCC_APB2ENR_TIM19EN
+#define RCC_APB2Periph_SDADC1            RCC_APB2ENR_SDADC1EN
+#define RCC_APB2Periph_SDADC2            RCC_APB2ENR_SDADC2EN
+#define RCC_APB2Periph_SDADC3            RCC_APB2ENR_SDADC3EN
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF8F08DFE) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_APB1_Peripherals 
+  * @{
+  */
+#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
+#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
+#define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN
+#define RCC_APB1Periph_TIM5              RCC_APB1ENR_TIM5EN
+#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
+#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
+#define RCC_APB1Periph_TIM12             RCC_APB1ENR_TIM12EN
+#define RCC_APB1Periph_TIM13             RCC_APB1ENR_TIM13EN
+#define RCC_APB1Periph_TIM14             RCC_APB1ENR_TIM14EN
+#define RCC_APB1Periph_TIM18             RCC_APB1ENR_TIM18EN
+#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
+#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
+#define RCC_APB1Periph_SPI3              RCC_APB1ENR_SPI3EN
+#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
+#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
+#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
+#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
+#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
+#define RCC_APB1Periph_CAN1              RCC_APB1ENR_CAN1EN
+#define RCC_APB1Periph_DAC2              RCC_APB1ENR_DAC2EN
+#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
+#define RCC_APB1Periph_DAC1              RCC_APB1ENR_DAC1EN
+#define RCC_APB1Periph_CEC               RCC_APB1ENR_CECEN
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x89193400) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Clock_Source
+  * @{
+  */
+
+#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
+#define RCC_MCOSource_LSI                ((uint8_t)0x02)
+#define RCC_MCOSource_LSE                ((uint8_t)0x03)
+#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
+#define RCC_MCOSource_HSI                ((uint8_t)0x05)
+#define RCC_MCOSource_HSE                ((uint8_t)0x06)
+#define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
+
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
+                                    ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_HSE) || \
+                                    ((SOURCE) == RCC_MCOSource_LSI)  || ((SOURCE) == RCC_MCOSource_LSE) || \
+                                    ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
+/**
+  * @}
+  */ 
+
+/** @defgroup RCC_USB_Device_clock_source 
+  * @{
+  */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag 
+  * @{
+  */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
+#define RCC_FLAG_V18PWRRSTF              ((uint8_t)0x57)
+#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
+
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+                           ((FLAG) == RCC_FLAG_V18PWRRSTF))
+
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint32_t RCC_LSE);
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCOSource);
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_SDADCCLKConfig(uint32_t RCC_SDADCCLK);
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_RCC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_sdadc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_sdadc.h
new file mode 100644
index 0000000..3d33b12
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_sdadc.h
@@ -0,0 +1,455 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_sdadc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the SDADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_SDADC_H
+#define __STM32F37X_SDADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SDADC Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t SDADC_Channel;                    /*!< Select the regular channel.
+                                                  This parameter can be any value of @ref SDADC_Channel_Selection */
+
+  FunctionalState SDADC_ContinuousConvMode;  /*!< Specifies whether the conversion is performed in
+                                                  Continuous or Single mode.
+                                                  This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState SDADC_FastConversionMode;  /*!< Specifies whether the conversion is performed in
+                                                  fast mode.
+                                                  This parameter can be set to ENABLE or DISABLE. */
+
+}SDADC_InitTypeDef;
+
+/** 
+  * @brief  SDADC Analog Inputs Configuration structure definition  
+  */
+
+typedef struct
+{
+  uint32_t SDADC_InputMode;      /*!< Specifies the input structure type (single ended, differential...)
+                                      This parameter can be any value of @ref SDADC_InputMode */
+
+  uint32_t SDADC_Gain;           /*!< Specifies the gain setting.
+                                      This parameter can be any value of @ref SDADC_Gain */
+
+  uint32_t SDADC_CommonMode;     /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2).
+                                      This parameter can be any value of @ref SDADC_CommonMode */
+
+  uint32_t SDADC_Offset;         /*!< Specifies the 12-bit offset value.
+                                      This parameter can be any value lower or equal to 0x00000FFF */
+}SDADC_AINStructTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDADC_Exported_Constants
+  * @{
+  */
+
+#define IS_SDADC_ALL_PERIPH(PERIPH) (((PERIPH) == SDADC1) || \
+                                     ((PERIPH) == SDADC2) || \
+                                     ((PERIPH) == SDADC3))
+
+#define IS_SDADC_SLAVE_PERIPH(PERIPH) (((PERIPH) == SDADC2) || \
+                                       ((PERIPH) == SDADC3))
+
+/** @defgroup SDADC_Channel_Selection
+  * @{
+  */
+
+/* SDADC Channels ------------------------------------------------------------*/
+/* The SDADC channels are defined as follow:
+   - in 16-bit LSB the channel mask is set
+   - in 16-bit MSB the channel number is set 
+   e.g. for channel 5 definition:  
+        - the channel mask is 0x00000020 (bit 5 is set) 
+        - the channel number 5 is 0x00050000 
+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#define SDADC_Channel_0                              ((uint32_t)0x00000001)
+#define SDADC_Channel_1                              ((uint32_t)0x00010002)
+#define SDADC_Channel_2                              ((uint32_t)0x00020004)
+#define SDADC_Channel_3                              ((uint32_t)0x00030008)
+#define SDADC_Channel_4                              ((uint32_t)0x00040010)
+#define SDADC_Channel_5                              ((uint32_t)0x00050020)
+#define SDADC_Channel_6                              ((uint32_t)0x00060040)
+#define SDADC_Channel_7                              ((uint32_t)0x00070080)
+#define SDADC_Channel_8                              ((uint32_t)0x00080100)
+
+/* Just one channel of the 9 channels can be selected for regular conversion */
+#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_Channel_0)  || \
+                                           ((CHANNEL) == SDADC_Channel_1)  || \
+                                           ((CHANNEL) == SDADC_Channel_2)  || \
+                                           ((CHANNEL) == SDADC_Channel_3)  || \
+                                           ((CHANNEL) == SDADC_Channel_4)  || \
+                                           ((CHANNEL) == SDADC_Channel_5)  || \
+                                           ((CHANNEL) == SDADC_Channel_6)  || \
+                                           ((CHANNEL) == SDADC_Channel_7)  || \
+                                           ((CHANNEL) == SDADC_Channel_8))
+
+/* Any or all of the 9 channels can be selected for injected conversion */
+#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_Conf 
+  * @{
+  */
+  
+#define SDADC_Conf_0                              ((uint32_t)0x00000000) /*!< Configuration 0 selected */
+#define SDADC_Conf_1                              ((uint32_t)0x00000001) /*!< Configuration 1 selected */
+#define SDADC_Conf_2                              ((uint32_t)0x00000002) /*!< Configuration 2 selected */
+
+#define IS_SDADC_CONF(CONF) (((CONF) == SDADC_Conf_0)  || \
+                             ((CONF) == SDADC_Conf_1)  || \
+                             ((CONF) == SDADC_Conf_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_InputMode
+  * @{
+  */
+
+#define SDADC_InputMode_Diff                      ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */
+#define SDADC_InputMode_SEOffset                  SDADC_CONF0R_SE0_0     /*!< Conversions are executed in single ended offset mode */
+#define SDADC_InputMode_SEZeroReference           SDADC_CONF0R_SE0       /*!< Conversions are executed in single ended zero-volt reference mode */
+
+#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_InputMode_Diff)     || \
+                                   ((MODE) == SDADC_InputMode_SEOffset) || \
+                                   ((MODE) == SDADC_InputMode_SEZeroReference))
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_Gain 
+  * @{
+  */
+
+#define SDADC_Gain_1                              ((uint32_t)0x00000000)  /*!< Gain equal to 1 */
+#define SDADC_Gain_2                              SDADC_CONF0R_GAIN0_0    /*!< Gain equal to 2 */
+#define SDADC_Gain_4                              SDADC_CONF0R_GAIN0_1    /*!< Gain equal to 4 */
+#define SDADC_Gain_8                              ((uint32_t)0x00300000)  /*!< Gain equal to 8 */
+#define SDADC_Gain_16                             SDADC_CONF0R_GAIN0_2    /*!< Gain equal to 16 */
+#define SDADC_Gain_32                             ((uint32_t)0x00500000)  /*!< Gain equal to 32 */
+#define SDADC_Gain_1_2                            SDADC_CONF0R_GAIN0      /*!< Gain equal to 1/2 */
+
+#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_Gain_1)  || \
+                             ((GAIN) == SDADC_Gain_2)  || \
+                             ((GAIN) == SDADC_Gain_4)  || \
+                             ((GAIN) == SDADC_Gain_8)  || \
+                             ((GAIN) == SDADC_Gain_16)  || \
+                             ((GAIN) == SDADC_Gain_32)  || \
+                             ((GAIN) == SDADC_Gain_1_2))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_CommonMode
+  * @{
+  */
+
+#define SDADC_CommonMode_VSSA                      ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */
+#define SDADC_CommonMode_VDDA_2                    SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
+#define SDADC_CommonMode_VDDA                      SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
+
+#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_CommonMode_VSSA)   || \
+                                    ((MODE) == SDADC_CommonMode_VDDA_2) || \
+                                    ((MODE) == SDADC_CommonMode_VDDA))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_Offset
+  * @{
+  */
+
+#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_ExternalTrigger_sources
+  * @{
+  */
+#define SDADC_ExternalTrigInjecConv_T13_CC1               ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T14_CC1               ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T16_CC1               ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_T17_CC1               ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T12_CC1               ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T12_CC2               ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_T15_CC2               ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T2_CC3                ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T2_CC4                ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_T3_CC1                ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T3_CC2                ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T3_CC3                ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_T4_CC1                ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T4_CC2                ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T4_CC3                ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_T19_CC2               ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */
+#define SDADC_ExternalTrigInjecConv_T19_CC3               ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */
+#define SDADC_ExternalTrigInjecConv_T19_CC4               ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */
+#define SDADC_ExternalTrigInjecConv_Ext_IT11              ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+#define SDADC_ExternalTrigInjecConv_Ext_IT15              ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+
+#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_ExternalTrigInjecConv_T13_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T14_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T16_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T17_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T12_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T12_CC2)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T15_CC2)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T2_CC3)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T2_CC4)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T3_CC1)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T3_CC2)  || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T3_CC3) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T4_CC1) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T4_CC2) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T4_CC3) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T19_CC2) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T19_CC3) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_T19_CC4) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_Ext_IT11) || \
+                                          ((INJTRIG) == SDADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
+  */ 
+#define SDADC_ExternalTrigInjecConvEdge_None               ((uint32_t) 0x00000000)
+#define SDADC_ExternalTrigInjecConvEdge_Rising             SDADC_CR2_JEXTEN_0
+#define SDADC_ExternalTrigInjecConvEdge_Falling            SDADC_CR2_JEXTEN_1
+#define SDADC_ExternalTrigInjecConvEdge_RisingFalling      SDADC_CR2_JEXTEN
+
+#define IS_SDADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == SDADC_ExternalTrigInjecConvEdge_None)    || \
+                                            ((EDGE) == SDADC_ExternalTrigInjecConvEdge_Rising)  || \
+                                            ((EDGE) == SDADC_ExternalTrigInjecConvEdge_Falling) || \
+                                            ((EDGE) == SDADC_ExternalTrigInjecConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDADC_DMATransfer_modes 
+  * @{
+  */ 
+#define SDADC_DMATransfer_Regular                SDADC_CR1_RDMAEN          /*!< DMA requests enabled for regular conversions */
+#define SDADC_DMATransfer_Injected               SDADC_CR1_JDMAEN          /*!< DMA requests enabled for injected conversions */
+
+#define IS_SDADC_DMA_TRANSFER(TRANSFER)  (((TRANSFER) == SDADC_DMATransfer_Regular)  || \
+                                          ((TRANSFER) == SDADC_DMATransfer_Injected))
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_CalibrationSequence 
+  * @{
+  */ 
+#define SDADC_CalibrationSequence_1                   ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
+#define SDADC_CalibrationSequence_2                   SDADC_CR2_CALIBCNT_0   /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
+#define SDADC_CalibrationSequence_3                   SDADC_CR2_CALIBCNT_1   /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
+
+#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE)  (((SEQUENCE) == SDADC_CalibrationSequence_1)  || \
+                                            ((SEQUENCE) == SDADC_CalibrationSequence_2)  || \
+                                            ((SEQUENCE) == SDADC_CalibrationSequence_3))
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_VREF
+  * @{
+  */
+
+#define SDADC_VREF_Ext                            ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */
+#define SDADC_VREF_VREFINT1                       SDADC_CR1_REFV_0       /*!< The reference voltage is forced internally to 1.22V VREFINT */
+#define SDADC_VREF_VREFINT2                       SDADC_CR1_REFV_1       /*!< The reference voltage is forced internally to 1.8V VREFINT */
+#define SDADC_VREF_VDDA                           SDADC_CR1_REFV         /*!< The reference voltage is forced internally to VDDA */
+
+#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_Ext)      || \
+                             ((VREF) == SDADC_VREF_VREFINT1) || \
+                             ((VREF) == SDADC_VREF_VREFINT2) || \
+                             ((VREF) == SDADC_VREF_VDDA))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_interrupts_definition
+  * @{
+  */
+
+#define SDADC_IT_EOCAL                               ((uint32_t)0x00000001) /*!< End of calibration flag */
+#define SDADC_IT_JEOC                                ((uint32_t)0x00000002) /*!< End of injected conversion flag */
+#define SDADC_IT_JOVR                                ((uint32_t)0x00000004) /*!< Injected conversion overrun flag */
+#define SDADC_IT_REOC                                ((uint32_t)0x00000008) /*!< End of regular conversion flag */
+#define SDADC_IT_ROVR                                ((uint32_t)0x00000010) /*!< Regular conversion overrun flag */
+
+#define IS_SDADC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFE0) == 0x00000000) && ((IT) != 0x00000000))
+
+#define IS_SDADC_GET_IT(IT) (((IT) == SDADC_IT_EOCAL) || ((IT) == SDADC_IT_JEOC) || \
+                             ((IT) == SDADC_IT_JOVR)  || ((IT) == SDADC_IT_REOC) || \
+                             ((IT) == SDADC_IT_ROVR))
+
+#define IS_SDADC_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFFFEA) == 0x00000000) && ((IT) != 0x00000000))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDADC_flags_definition
+  * @{
+  */
+
+#define SDADC_FLAG_EOCAL                             ((uint32_t)0x00000001) /*!< End of calibration flag */
+#define SDADC_FLAG_JEOC                              ((uint32_t)0x00000002) /*!< End of injected conversion flag */
+#define SDADC_FLAG_JOVR                              ((uint32_t)0x00000004) /*!< Injected conversion overrun flag */
+#define SDADC_FLAG_REOC                              ((uint32_t)0x00000008) /*!< End of regular conversion flag */
+#define SDADC_FLAG_ROVR                              ((uint32_t)0x00000010) /*!< Regular conversion overrun flag */
+#define SDADC_FLAG_CALIBIP                           ((uint32_t)0x00001000) /*!< Calibration in progress status */
+#define SDADC_FLAG_JCIP                              ((uint32_t)0x00002000) /*!< Injected conversion in progress status */
+#define SDADC_FLAG_RCIP                              ((uint32_t)0x00004000) /*!< Regular conversion in progress status */
+#define SDADC_FLAG_STABIP                            ((uint32_t)0x00008000) /*!< Stabilization in progress status */
+#define SDADC_FLAG_INITRDY                           ((uint32_t)0x80000000) /*!< Initialization mode is ready */
+
+#define IS_SDADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFE0) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_SDADC_GET_FLAG(FLAG) (((FLAG) == SDADC_FLAG_EOCAL) || ((FLAG) == SDADC_FLAG_JEOC)   || \
+                                 ((FLAG) == SDADC_FLAG_JOVR)  || ((FLAG)== SDADC_FLAG_REOC)    || \
+                                 ((FLAG) == SDADC_FLAG_ROVR)  || ((FLAG)== SDADC_FLAG_CALIBIP) || \
+                                 ((FLAG) == SDADC_FLAG_JCIP)  || ((FLAG)== SDADC_FLAG_RCIP)    || \
+                                 ((FLAG) == SDADC_FLAG_STABIP)  || ((FLAG)== SDADC_FLAG_INITRDY))
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/* Function used to set the SDADC configuration to the default reset state ****/
+void SDADC_DeInit(SDADC_TypeDef* SDADCx);
+
+/* Initialization and Configuration functions *********************************/
+void SDADC_Init(SDADC_TypeDef* SDADCx, SDADC_InitTypeDef* SDADC_InitStruct);
+void SDADC_StructInit(SDADC_InitTypeDef* SDADC_InitStruct);
+void SDADC_AINInit(SDADC_TypeDef* SDADCx, uint32_t SDADC_Conf, SDADC_AINStructTypeDef* SDADC_AINStruct);
+void SDADC_AINStructInit(SDADC_AINStructTypeDef* SDADC_AINStruct);
+void SDADC_ChannelConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_Channel, uint32_t SDADC_Conf);
+void SDADC_Cmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_InitModeCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_FastConversionCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_VREFSelect(uint32_t SDADC_VREF);
+void SDADC_CalibrationSequenceConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_CalibrationSequence);
+void SDADC_StartCalibration(SDADC_TypeDef* SDADCx);
+
+/* Regular Channels Configuration functions ***********************************/
+void SDADC_ChannelSelect(SDADC_TypeDef* SDADCx, uint32_t SDADC_Channel);
+void SDADC_ContinuousModeCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_SoftwareStartConv(SDADC_TypeDef* SDADCx);
+int16_t SDADC_GetConversionValue(SDADC_TypeDef* SDADCx);
+void SDADC_RegularSynchroSDADC1(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+uint32_t SDADC_GetConversionSDADC12Value(void);
+uint32_t SDADC_GetConversionSDADC13Value(void);
+
+/* Injected channels Configuration functions **********************************/
+void SDADC_SoftwareStartInjectedConv(SDADC_TypeDef* SDADCx);
+void SDADC_InjectedChannelSelect(SDADC_TypeDef* SDADCx, uint32_t SDADC_Channel);
+void SDADC_DelayStartInjectedConvCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_InjectedContinuousModeCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_ExternalTrigInjectedConvConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_ExternalTrigInjecConv);
+void SDADC_ExternalTrigInjectedConvEdgeConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_ExternalTrigInjecConvEdge);
+uint32_t SDADC_GetInjectedChannel(SDADC_TypeDef* SDADCx);
+int16_t SDADC_GetInjectedConversionValue(SDADC_TypeDef* SDADCx, uint32_t* SDADC_Channel);
+void SDADC_InjectedSynchroSDADC1(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+uint32_t SDADC_GetInjectedConversionSDADC12Value(void);
+uint32_t SDADC_GetInjectedConversionSDADC13Value(void);
+
+/* Power saving functions *****************************************************/
+void SDADC_PowerDownCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_StandbyCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+void SDADC_SlowClockCmd(SDADC_TypeDef* SDADCx, FunctionalState NewState);
+
+/* Regular/Injected Channels DMA Configuration functions **********************/
+void SDADC_DMAConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_DMATransfer, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SDADC_ITConfig(SDADC_TypeDef* SDADCx, uint32_t SDADC_IT, FunctionalState NewState);
+FlagStatus SDADC_GetFlagStatus(SDADC_TypeDef* SDADCx, uint32_t SDADC_FLAG);
+void SDADC_ClearFlag(SDADC_TypeDef* SDADCx, uint32_t SDADC_FLAG);
+ITStatus SDADC_GetITStatus(SDADC_TypeDef* SDADCx, uint32_t SDADC_IT);
+void SDADC_ClearITPendingBit(SDADC_TypeDef* SDADCx, uint32_t SDADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_SDADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_spi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_spi.h
new file mode 100644
index 0000000..710ad94
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_spi.h
@@ -0,0 +1,586 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_spi.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_SPI_H
+#define __STM32F37X_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI mode (Master/Slave).
+                                         This parameter can be a value of @ref SPI_mode */
+  
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref SPI_I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref SPI_I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size
+  * @{
+  */
+
+#define SPI_DataSize_4b                 ((uint16_t)0x0300)
+#define SPI_DataSize_5b                 ((uint16_t)0x0400)
+#define SPI_DataSize_6b                 ((uint16_t)0x0500)
+#define SPI_DataSize_7b                 ((uint16_t)0x0600)
+#define SPI_DataSize_8b                 ((uint16_t)0x0700)
+#define SPI_DataSize_9b                 ((uint16_t)0x0800)
+#define SPI_DataSize_10b                ((uint16_t)0x0900)
+#define SPI_DataSize_11b                ((uint16_t)0x0A00)
+#define SPI_DataSize_12b                ((uint16_t)0x0B00)
+#define SPI_DataSize_13b                ((uint16_t)0x0C00)
+#define SPI_DataSize_14b                ((uint16_t)0x0D00)
+#define SPI_DataSize_15b                ((uint16_t)0x0E00)
+#define SPI_DataSize_16b                ((uint16_t)0x0F00)
+#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
+                                ((SIZE) == SPI_DataSize_5b) || \
+                                ((SIZE) == SPI_DataSize_6b) || \
+                                ((SIZE) == SPI_DataSize_7b) || \
+                                ((SIZE) == SPI_DataSize_8b) || \
+                                ((SIZE) == SPI_DataSize_9b) || \
+                                ((SIZE) == SPI_DataSize_10b) || \
+                                ((SIZE) == SPI_DataSize_11b) || \
+                                ((SIZE) == SPI_DataSize_12b) || \
+                                ((SIZE) == SPI_DataSize_13b) || \
+                                ((SIZE) == SPI_DataSize_14b) || \
+                                ((SIZE) == SPI_DataSize_15b) || \
+                                ((SIZE) == SPI_DataSize_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length
+  * @{
+  */
+
+#define SPI_CRCLength_8b                ((uint16_t)0x0000)
+#define SPI_CRCLength_16b               SPI_CR1_CRCL
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
+                                   ((LENGTH) == SPI_CRCLength_16b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   SPI_CR1_CPOL
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  SPI_CR1_CPHA
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    SPI_CR1_SSM
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           SPI_I2SPR_MCKOE
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   SPI_I2SCFGR_CKPOL
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold 
+  * @{
+  */
+
+#define SPI_RxFIFOThreshold_HF          ((uint16_t)0x0000)
+#define SPI_RxFIFOThreshold_QF          SPI_CR2_FRXTH
+#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
+                                             ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               SPI_CR2_TXDMAEN
+#define SPI_I2S_DMAReq_Rx               SPI_CR2_RXDMAEN
+#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_last_DMA_transfers
+  * @{
+  */
+
+#define SPI_LastDMATransfer_TxEvenRxEven   ((uint16_t)0x0000)
+#define SPI_LastDMATransfer_TxOddRxEven    ((uint16_t)0x4000)
+#define SPI_LastDMATransfer_TxEvenRxOdd    ((uint16_t)0x2000)
+#define SPI_LastDMATransfer_TxOddRxOdd     ((uint16_t)0x6000)
+#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
+                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
+/**
+  * @}
+  */
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         SPI_CR1_SSI
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_transmission_fifo_status_level 
+  * @{
+  */ 
+
+#define SPI_TransmissionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_TransmissionFIFOStatus_1QuarterFull    ((uint16_t)0x0800) 
+#define SPI_TransmissionFIFOStatus_HalfFull        ((uint16_t)0x1000) 
+#define SPI_TransmissionFIFOStatus_Full            ((uint16_t)0x1800)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_reception_fifo_status_level 
+  * @{
+  */ 
+#define SPI_ReceptionFIFOStatus_Empty           ((uint16_t)0x0000)
+#define SPI_ReceptionFIFOStatus_1QuarterFull    ((uint16_t)0x0200) 
+#define SPI_ReceptionFIFOStatus_HalfFull        ((uint16_t)0x0400) 
+#define SPI_ReceptionFIFOStatus_Full            ((uint16_t)0x0600)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               SPI_SR_RXNE
+#define SPI_I2S_FLAG_TXE                SPI_SR_TXE
+#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
+#define I2S_FLAG_UDR                    SPI_SR_UDR
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
+#define SPI_FLAG_MODF                   SPI_SR_MODF
+#define SPI_I2S_FLAG_OVR                SPI_SR_OVR
+#define SPI_I2S_FLAG_BSY                SPI_SR_BSY
+#define SPI_I2S_FLAG_FRE                SPI_SR_FRE
+
+
+
+#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
+                                   ((FLAG) == I2S_FLAG_UDR))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_syscfg.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_syscfg.h
new file mode 100644
index 0000000..391161e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_syscfg.h
@@ -0,0 +1,249 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*!< Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_SYSCFG_H
+#define __STM32F37X_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*!< Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_EXTI_Pin_sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
+
+
+#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
+                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_DMA_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_DMARemap_TIM17              SYSCFG_CFGR1_TIM17_DMA_RMP        /* Remap TIM17 DMA requests from channel1 to channel2 */
+#define SYSCFG_DMARemap_TIM16              SYSCFG_CFGR1_TIM16_DMA_RMP        /* Remap TIM16 DMA requests from channel3 to channel4 */
+#define SYSCFG_DMARemap_TIM6DAC1Ch1        SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP  /* Remap TIM6/DAC1 Ch1 DMA requests from DMA2 channel3 to DMA1 channel3 */
+#define SYSCFG_DMARemap_TIM7DAC1Ch2        SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP  /* Remap TIM7/DAC1 Ch2 DMA requests from DMA2 channel4 to DMA1 channel4 */
+#define SYSCFG_DMARemap_TIM18DAC2Ch1       SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP  /* Remap TIM18/DAC2 Ch1 DMA requests from DMA2 channel5 to DMA1 channel5 */
+  
+#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17)       || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM16)       || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM6DAC1Ch1) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM7DAC1Ch2) || \
+                                    ((REMAP) == SYSCFG_DMARemap_TIM18DAC2Ch1))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_I2C_FastModePlus_Config 
+  * @{
+  */ 
+#define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_FMP_PB6  /* Enable Fast Mode Plus on PB6 */
+#define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_FMP_PB7  /* Enable Fast Mode Plus on PB7 */
+#define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_FMP_PB8  /* Enable Fast Mode Plus on PB8 */
+#define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_FMP_PB9  /* Enable Fast Mode Plus on PB9 */
+#define SYSCFG_I2CFastModePlus_I2C1      SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on I2C1 pins */
+#define SYSCFG_I2CFastModePlus_I2C2      SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins */
+
+#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB7)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB8)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_PB9)  || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
+                                ((PIN) == SYSCFG_I2CFastModePlus_I2C2))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupt_Config 
+  * @{
+  */ 
+#define SYSCFG_IT_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Inexact Interrupt enable (interrupt disabled by default) */
+#define SYSCFG_IT_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Input denormal Interrupt enable */
+#define SYSCFG_IT_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Overflow Interrupt enable */
+#define SYSCFG_IT_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Underflow Interrupt enable */
+#define SYSCFG_IT_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Divide-by-zero Interrupt enable */
+#define SYSCFG_IT_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Invalid operation Interrupt enable */
+
+#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Lock_Config 
+  * @{
+  */ 
+#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK          /*!< Connects the PVD event to the Break Input of TIM15/TIM16/TIM17 */
+#define SYSCFG_Break_SRAMParity              SYSCFG_CFGR2_SRAM_PARITY_LOCK  /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM15/TIM16/TIM17 */
+#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM4 to the break input of TIM15/TIM16/TIM17 */
+
+#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
+                                       ((CONFIG) == SYSCFG_Break_SRAMParity) || \
+                                       ((CONFIG) == SYSCFG_Break_Lockup))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_flags_definition 
+  * @{
+  */
+
+#define SYSCFG_FLAG_PE               SYSCFG_CFGR2_SRAM_PE
+
+#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the SYSCFG configuration to the default reset state **/
+void SYSCFG_DeInit(void);
+
+/* SYSCFG configuration functions *********************************************/ 
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
+void SYSCFG_VBATMonitoringCmd(FunctionalState NewState);
+void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_SYSCFG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_tim.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_tim.h
new file mode 100644
index 0000000..02fd8d8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_tim.h
@@ -0,0 +1,1195 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_tim.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the TIM 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_TIM_H
+#define __STM32F37X_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TIM Time Base Init structure definition
+  * @note   This structure is used with all TIMx except for TIM6, TIM7 and TIM18.    
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF
+                                       ( or 0xFFFFFFFF for TIM2 and TIM5) */ 
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM15, TIM16 and TIM17 . */
+
+} TIM_TimeBaseInitTypeDef;       
+
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                   @note This parameter is valid only for TIM15, TIM16 and TIM17. */
+
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF 
+                                   for TIM2) */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM15, TIM16 and TIM17. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM15, TIM16 and TIM17. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM15, TIM16 and TIM17. */
+
+} TIM_OCInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/** 
+  * @brief  TIM_BDTR structure definition 
+  * @note   This structure is used only with TIM15, TIM16 and TIM17.    
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants 
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM5) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM12)|| \
+                                   ((PERIPH) == TIM13)|| \
+                                   ((PERIPH) == TIM14)|| \
+                                   ((PERIPH) == TIM15)|| \
+                                   ((PERIPH) == TIM16)|| \
+                                   ((PERIPH) == TIM17)|| \
+                                   ((PERIPH) == TIM18)|| \
+                                   ((PERIPH) == TIM19))
+
+/* LIST1: TIM 14 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM14)
+
+/* LIST2: TIM 15 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17)) 
+
+/* LIST3: TIM 2, 3, 4, 5 and 19 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM19)) 
+
+/* LIST4: TIM 2, 3, 4, 5, 15, 16, 17 and 19*/
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM15)|| \
+                                     ((PERIPH) == TIM16)|| \
+                                     ((PERIPH) == TIM17) || \
+                                     ((PERIPH) == TIM19))
+
+/* LIST5: TIM 2, 3, 4, 5, 15 and 19 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM15) || \
+                                     ((PERIPH) == TIM19)) 
+
+/* LIST6: TIM 2, 3, 4, 5, 12, 15 and 19 */
+#define IS_TIM_LIST6_PERIPH(PERIPH)  (((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM19))
+
+/* LIST7: TIM 2, 3, 4, 5, 6, 7, 12, 15, 18 and 19 */
+#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM18)|| \
+                                      ((PERIPH) == TIM19))
+
+/* LIST8: TIM 2, 3, 4, 5, 12, 13, 14, 15, 16, 17 and 19 */
+#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM12)|| \
+                                      ((PERIPH) == TIM13)|| \
+                                      ((PERIPH) == TIM14)|| \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM16)|| \
+                                      ((PERIPH) == TIM17)|| \
+                                      ((PERIPH) == TIM19))
+
+/* LIST9: TIM 2, 3, 4, 5, 6, 7, 15, 16, 17, 18 and 19 */
+#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM2) || \
+                                      ((PERIPH) == TIM3) || \
+                                      ((PERIPH) == TIM4) || \
+                                      ((PERIPH) == TIM5) || \
+                                      ((PERIPH) == TIM6) || \
+                                      ((PERIPH) == TIM7) || \
+                                      ((PERIPH) == TIM15)|| \
+                                      ((PERIPH) == TIM16)|| \
+                                      ((PERIPH) == TIM17)|| \
+                                      ((PERIPH) == TIM18)|| \
+                                      ((PERIPH) == TIM19))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_state
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_state 
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_state 
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_N_state 
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Polarity 
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Lock_level 
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY)      (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                           ((POLARITY) == TIM_ICPolarity_Falling))
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                           ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                           ((POLARITY) == TIM_ICPolarity_BothEdge))                                      
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_interrupt_sources 
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_OR) || \
+                               ((BASE) == TIM_DMABase_DCR))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Forced_Action 
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Update_Source 
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Flags 
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+                               
+                               
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OCReferenceClear 
+  * @{
+  */
+#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
+#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
+#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
+                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Remap 
+  * @{
+  */
+#define TIM14_GPIO                      ((uint16_t)0x0000)
+#define TIM14_RTC_CLK                   ((uint16_t)0x0001)
+#define TIM14_HSEDiv32                  ((uint16_t)0x0002)
+#define TIM14_MCO                       ((uint16_t)0x0003)
+
+#define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM14_GPIO)|| \
+                                  ((TIM_REMAP) == TIM14_RTC_CLK) || \
+                                  ((TIM_REMAP) == TIM14_HSEDiv32) || \
+                                  ((TIM_REMAP) == TIM14_MCO))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Legacy 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Advanced-control timers (TIM15, TIM16 and TIM17) specific features*******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/                   
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F37X_TIM_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_usart.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_usart.h
new file mode 100644
index 0000000..0cdfc73
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/inc/stm32f37x_usart.h
@@ -0,0 +1,592 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_usart.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_USART_H
+#define __STM32F37X_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+   
+   
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+  uint32_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint32_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint32_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint32_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control*/
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition
+  */ 
+
+typedef struct
+{
+  uint32_t USART_Clock;             /*!< Specifies whether the USART clock is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Clock */
+
+  uint32_t USART_CPOL;              /*!< Specifies the steady state of the serial clock.
+                                         This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint32_t USART_CPHA;              /*!< Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint32_t USART_LastBit;           /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                         data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                         This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+
+#define USART_WordLength_8b                  ((uint32_t)0x00000000)
+#define USART_WordLength_9b                  USART_CR1_M
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+
+#define USART_StopBits_1                     ((uint32_t)0x00000000)
+#define USART_StopBits_2                     USART_CR2_STOP_1
+#define USART_StopBits_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+
+#define USART_Parity_No                      ((uint32_t)0x00000000)
+#define USART_Parity_Even                    USART_CR1_PCE
+#define USART_Parity_Odd                     (USART_CR1_PCE | USART_CR1_PS) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+
+#define USART_Mode_Rx                        USART_CR1_RE
+#define USART_Mode_Tx                        USART_CR1_TE
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
+                              ((MODE) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+
+#define USART_HardwareFlowControl_None       ((uint32_t)0x00000000)
+#define USART_HardwareFlowControl_RTS        USART_CR3_RTSE
+#define USART_HardwareFlowControl_CTS        USART_CR3_CTSE
+#define USART_HardwareFlowControl_RTS_CTS    (USART_CR3_RTSE | USART_CR3_CTSE)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+  
+#define USART_Clock_Disable                  ((uint32_t)0x00000000)
+#define USART_Clock_Enable                   USART_CR2_CLKEN
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint32_t)0x00000000)
+#define USART_CPOL_High                      USART_CR2_CPOL
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint32_t)0x00000000)
+#define USART_CPHA_2Edge                     USART_CR2_CPHA
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint32_t)0x00000000)
+#define USART_LastBit_Enable                 USART_CR2_LBCL
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      USART_CR3_DMAT
+#define USART_DMAReq_Rx                      USART_CR3_DMAR
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
+                                  ((DMAREQ) != (uint32_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DMA_Recception_Error
+  * @{
+  */
+
+#define USART_DMAOnError_Enable              ((uint32_t)0x00000000)
+#define USART_DMAOnError_Disable             USART_CR3_DDRE
+#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
+                                       ((DMAERROR) == USART_DMAOnError_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_MuteMode_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint32_t)0x00000000)
+#define USART_WakeUp_AddressMark             USART_CR1_WAKE
+#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                          ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Address_Detection
+  * @{
+  */ 
+
+#define USART_AddressLength_4b               ((uint32_t)0x00000000)
+#define USART_AddressLength_7b               USART_CR2_ADDM7
+#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
+                                             ((ADDRESS) == USART_AddressLength_7b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_StopMode_WakeUp_methods 
+  * @{
+  */ 
+
+#define USART_WakeUpSource_AddressMatch      ((uint32_t)0x00000000)
+#define USART_WakeUpSource_StartBit          USART_CR3_WUS_1
+#define USART_WakeUpSource_RXNE              (USART_CR3_WUS_0 | USART_CR3_WUS_1)
+#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
+                                                ((SOURCE) == USART_WakeUpSource_StartBit) || \
+                                                ((SOURCE) == USART_WakeUpSource_RXNE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b       ((uint32_t)0x00000000)
+#define USART_LINBreakDetectLength_11b       USART_CR2_LBDL
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              USART_CR3_IRLP
+#define USART_IrDAMode_Normal                ((uint32_t)0x00000000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_DE_Polarity 
+  * @{
+  */
+
+#define USART_DEPolarity_High                ((uint32_t)0x00000000)
+#define USART_DEPolarity_Low                 USART_CR3_DEP
+#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
+                                        ((POLARITY) == USART_DEPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Inversion_Pins 
+  * @{
+  */
+
+#define USART_InvPin_Tx                      USART_CR2_TXINV
+#define USART_InvPin_Rx                      USART_CR2_RXINV
+#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
+                                       ((PIN) != (uint32_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_AutoBaudRate_Mode 
+  * @{
+  */
+
+#define USART_AutoBaudRate_StartBit          ((uint32_t)0x00000000)
+#define USART_AutoBaudRate_FallingEdge       USART_CR2_ABRMODE_0
+#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
+                                          ((MODE) == USART_AutoBaudRate_FallingEdge))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_OVR_DETECTION
+  * @{
+  */
+
+#define USART_OVRDetection_Enable            ((uint32_t)0x00000000)
+#define USART_OVRDetection_Disable           USART_CR3_OVRDIS
+#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
+                                    ((OVR) == USART_OVRDetection_Disable))
+/**
+  * @}
+  */ 
+/** @defgroup USART_Request 
+  * @{
+  */
+
+#define USART_Request_ABRRQ                  USART_RQR_ABRRQ
+#define USART_Request_SBKRQ                  USART_RQR_SBKRQ
+#define USART_Request_MMRQ                   USART_RQR_MMRQ
+#define USART_Request_RXFRQ                  USART_RQR_RXFRQ
+#define USART_Request_TXFRQ                  USART_RQR_TXFRQ
+
+#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
+                                   ((REQUEST) == USART_Request_RXFRQ) || \
+                                   ((REQUEST) == USART_Request_MMRQ) || \
+                                   ((REQUEST) == USART_Request_SBKRQ) || \
+                                   ((REQUEST) == USART_Request_ABRRQ))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+#define USART_FLAG_REACK                     USART_ISR_REACK
+#define USART_FLAG_TEACK                     USART_ISR_TEACK
+#define USART_FLAG_WU                        USART_ISR_WUF
+#define USART_FLAG_RWU                       USART_ISR_RWU
+#define USART_FLAG_SBK                       USART_ISR_SBKF
+#define USART_FLAG_CM                        USART_ISR_CMF
+#define USART_FLAG_BUSY                      USART_ISR_BUSY
+#define USART_FLAG_ABRF                      USART_ISR_ABRF
+#define USART_FLAG_ABRE                      USART_ISR_ABRE
+#define USART_FLAG_EOB                       USART_ISR_EOBF
+#define USART_FLAG_RTO                       USART_ISR_RTOF
+#define USART_FLAG_nCTSS                     USART_ISR_CTS 
+#define USART_FLAG_CTS                       USART_ISR_CTSIF
+#define USART_FLAG_LBD                       USART_ISR_LBD
+#define USART_FLAG_TXE                       USART_ISR_TXE
+#define USART_FLAG_TC                        USART_ISR_TC
+#define USART_FLAG_RXNE                      USART_ISR_RXNE
+#define USART_FLAG_IDLE                      USART_ISR_IDLE
+#define USART_FLAG_ORE                       USART_ISR_ORE
+#define USART_FLAG_NE                        USART_ISR_NE
+#define USART_FLAG_FE                        USART_ISR_FE
+#define USART_FLAG_PE                        USART_ISR_PE
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                             ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
+                             ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
+                             ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
+                             ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
+                             ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
+                             ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
+
+#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
+                                   ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
+                                   ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
+                                   ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
+                                   ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
+                                   ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @brief USART Interrupt definition
+  * USART_IT possible values
+  * Elements values convention: 0xZZZZYYXX
+  *   XX: Position of the corresponding Interrupt
+  *   YY: Register index
+  *   ZZZZ: Flag position
+  * @{
+  */
+
+#define USART_IT_WU                          ((uint32_t)0x00140316)
+#define USART_IT_CM                          ((uint32_t)0x0011010E)
+#define USART_IT_EOB                         ((uint32_t)0x000C011B)
+#define USART_IT_RTO                         ((uint32_t)0x000B011A)
+#define USART_IT_PE                          ((uint32_t)0x00000108)
+#define USART_IT_TXE                         ((uint32_t)0x00070107)
+#define USART_IT_TC                          ((uint32_t)0x00060106)
+#define USART_IT_RXNE                        ((uint32_t)0x00050105)
+#define USART_IT_IDLE                        ((uint32_t)0x00040104)
+#define USART_IT_LBD                         ((uint32_t)0x00080206)
+#define USART_IT_CTS                         ((uint32_t)0x0009030A) 
+#define USART_IT_ERR                         ((uint32_t)0x00000300)
+#define USART_IT_ORE                         ((uint32_t)0x00030300)
+#define USART_IT_NE                          ((uint32_t)0x00020300)
+#define USART_IT_FE                          ((uint32_t)0x00010300)
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
+                                ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                                ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
+                             ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                             ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
+                               ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
+                               ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
+                               ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
+                               ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
+/**
+  * @}
+  */
+
+/** @defgroup USART_Global_definition 
+  * @{
+  */
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
+#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
+#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
+#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and Configuration functions *********************************/
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
+
+/* STOP Mode functions ********************************************************/
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
+
+/* AutoBaudRate functions *****************************************************/
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
+
+/* Data transfers functions ***************************************************/
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* RS485 mode functions *******************************************************/
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F37X_USART_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c
new file mode 100644
index 0000000..2d4989e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c
@@ -0,0 +1,1485 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_adc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Converter (ADC) peripheral:
+  *           + Initialization and Configuration
+  *           + Analog Watchdog configuration
+  *           + Temperature Sensor, Vrefint (Internal Reference Voltage)
+  *             and VBAT (Voltage battery) management
+  *           + Regular Channels Configuration
+  *           + Regular Channels DMA Configuration
+  *           + Injected channels Configuration
+  *           + Interrupts and flags management
+  *         
+  *  @verbatim
+================================================================================
+                      ##### How to use this driver #####
+================================================================================
+    [..]
+    (#) Enable the ADC interface clock using 
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+    (#) ADC pins configuration
+       (++) Enable the clock for the ADC GPIOs using the following function:
+            RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
+       (++) Configure these ADC pins in analog mode using GPIO_Init();
+    (#) Configure the data alignment using the ADC_Init() function.
+    (#) Activate the ADC peripheral using ADC_Cmd() function.
+
+    *** Regular channels group configuration ***
+    ============================================
+    [..] 
+    (+) To configure the ADC regular channels group features, use 
+        ADC_Init() and ADC_RegularChannelConfig() functions.
+    (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
+        function.
+    (+) To configure and activate the Discontinuous mode, use the
+        ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
+    (+) To read the ADC converted values, use the ADC_GetConversionValue()
+        function.
+
+    *** DMA for Regular channels group features configuration ***
+    =============================================================
+    [..]
+    (+) To enable the DMA mode for regular channels group, use the 
+        ADC_DMACmd() function.
+             
+    *** Injected channels group configuration ***
+    =============================================
+    [..]    
+    (+) To configure the ADC Injected channels group features, use 
+        ADC_InjectedChannelConfig() function.
+    (+) To activate the Injected Discontinuous mode, use the 
+        ADC_InjectedDiscModeCmd() function.  
+    (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+        function.
+    (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() function.
+
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_adc.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CR2 register Mask */
+#define ADC_CR2_CLEAR_MASK         ((uint32_t)0xFFF1F7FD)
+/* ADC SQRx mask */
+#define ADC_SQR_SQ_SET             ((uint32_t)0x0000001F)
+/* ADC JSQRx mask */
+#define ADC_JSQR_JSQ_SET           ((uint32_t)0x0000001F)
+/* ADC SMPRx mask */
+#define ADC_SMPR_SMP_SET           ((uint32_t)0x00000007)
+/* ADC JDRx registers offset */
+#define ADC_JDR_OFFSET             ((uint8_t)0x28)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to:
+        (+) Scan Conversion Mode (multichannels or one channel) for regular group
+        (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
+            regular group
+        (+) External trigger Edge and source of regular group, 
+        (+) Converted data alignment (left or right)
+        (+) The number of ADC conversions that will be done using the sequencer
+            for regular channel group
+        (+) Enable or disable the ADC peripheral
+        (+) Start/Reset the calibration
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ADCx peripheral registers to their default reset values.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Enable ADC1 reset state */
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+  /* Release ADC1 from reset state */
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear SCAN bit */
+  tmpreg1 &= (uint32_t)(~ADC_CR1_SCAN);
+  /* Configure ADCx: scan conversion mode */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  tmpreg1 |= (uint32_t)((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8);
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN and EXTSEL bits */
+  tmpreg1 &= ADC_CR2_CLEAR_MASK;
+  /* Configure ADCx: external trigger event and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= (uint32_t) (~ADC_SQR1_L);
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfChannel value */
+  tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+  tmpreg1 |= (uint32_t)tmpreg2 << 20;
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @param  ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Reset ADC init structure parameters values */
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T19_TRGO;
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+  /* Initialize the ADC_NbrOfChannel member */
+  ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= ADC_CR2_ADON;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
+  }
+}
+
+/**
+  * @brief  Starts the selected ADC calibration process.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC calibration process */  
+  ADCx->CR2 |= ADC_CR2_CAL;
+}
+
+/**
+  * @brief  Resets the selected ADC calibration registers.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Resets the selected ADC calibration registers */  
+  ADCx->CR2 |= ADC_CR2_RSTCAL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
+ *  @brief   Analog Watchdog configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Analog Watchdog configuration functions ##### 
+ ===============================================================================  
+
+    [..] This section provides functions allowing to configure the Analog Watchdog
+         (AWD) feature in the ADC.
+  
+    [..] A typical configuration Analog Watchdog is done following these steps :
+         (#) The ADC guarded channel(s) is (are) selected using the 
+             ADC_AnalogWatchdogSingleChannelConfig() function.
+         (#) The Analog watchdog lower and higher threshold are configured using
+             the ADC_AnalogWatchdogThresholdsConfig() function.
+         (#) The Analog watchdog is enabled and configured to enable the check,
+             on one or more channels, using the  ADC_AnalogWatchdogCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+  *            @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+  *            @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *            @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on  all regular channel
+  *            @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on  all injected channel
+  *            @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *            @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, AWDENJ and AWDSGL bits */
+  tmpreg &= (uint32_t) (~(ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL));
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *          This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *          This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= (uint32_t)(~ADC_CR1_AWDCH);
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group3 Temperature Sensor- Vrefint (Internal Reference Voltage) and VBAT management function
+ *  @brief   Temperature Sensor- Vrefint (Internal Reference Voltage) and VBAT management function
+ *
+@verbatim   
+ ===============================================================================
+ ##### Temperature Sensor, Vrefint and VBAT management function #####
+ ===============================================================================  
+
+    [..]  This section provides a function allowing to enable/ disable the internal 
+          connections between the ADC and the Temperature Sensor, the Vrefint
+          and the VBAT sources.
+
+    [..] A typical configuration to get the Temperature sensor and Vrefint channels 
+         voltages is done following these steps :
+         (#) Enable the internal connection of Temperature sensor and Vrefint sources 
+             with the ADC channels using ADC_TempSensorVrefintCmd() function.
+             Enable the internal connection of VBAT using SYSCFG_VBATMonitoringCmd(ENABLE);
+         (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint and/or 
+            ADC_Channel_Vbat using ADC_RegularChannelConfig()
+            or ADC_InjectedChannelConfig() functions 
+         (#) Get the voltage values, using ADC_GetConversionValue() or  
+             ADC_GetInjectedConversionValue().
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 |= ADC_CR2_TSVREFE;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC1->CR2 &= (uint32_t) (~ADC_CR2_TSVREFE);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group4 Regular Channels Configuration functions
+ *  @brief   Regular Channels Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Regular Channels Configuration functions  #####
+ ===============================================================================  
+
+    [..] This section provides functions allowing to manage the ADC regular channels,
+         it is composed of 2 sub sections : 
+  
+         (#) Configuration and management functions for regular channels: This subsection 
+             provides functions allowing to configure the ADC regular channels :    
+             (++) Configure the rank in the regular group sequencer for each channel
+             (++) Configure the sampling time for each channel
+             (++) select the conversion Trigger for regular channels
+             (++) select the desired EOC event behavior configuration
+             (++) Activate the continuous Mode  (*)
+             (++) Activate the Discontinuous Mode 
+             -@@- Please Note that the following features for regular channels
+                  are configured using the ADC_Init() function :
+                  (+@@) scan mode activation 
+                  (+@@) continuous mode activation (**) 
+                  (+@@) External trigger source  
+                  (+@@) External trigger edge 
+                  (+@@) number of conversion in the regular channels group sequencer.
+     
+             -@@- (*) and (**) are performing the same configuration
+     
+         (#) Get the conversion data: This subsection provides an important function in 
+             the ADC peripheral since it returns the converted data of the current 
+             regular channel. When the Conversion value is read, the EOC Flag is 
+             automatically cleared.
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *            @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *            @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *            @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *            @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *            @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *            @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *            @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SMPR_SMP_SET << (3 * (ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SMPR_SMP_SET << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SQR_SQ_SET << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SQR_SQ_SET << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SQR_SQ_SET << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADCx conversion through external trigger.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of conversion.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion on external event */
+    ADCx->CR2 |= ADC_CR2_EXTTRIG;
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event */
+    ADCx->CR2 &= (uint32_t) (~ADC_CR2_EXTTRIG);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC software start conversion .
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Enable the selected ADC conversion on external event and start the selected
+     ADC conversion */
+    ADCx->CR2 |= (uint32_t)(ADC_CR2_SWSTART | ADC_CR2_EXTTRIG);
+
+}
+
+/**
+  * @brief  Gets the selected ADC Software start conversion Status.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the ADC continuous conversion mode 
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC continuous conversion mode
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC continuous conversion mode */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
+  }
+  else
+  {
+    /* Disable the selected ADC continuous conversion mode */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
+  }
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel
+  *         count value. This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= (uint32_t)(~ADC_CR1_DISCNUM);
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on regular group channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= ADC_CR1_DISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
+ *  @brief   Regular Channels DMA Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Regular Channels DMA Configuration functions #####
+ =============================================================================== 
+
+    [..] This section provides functions allowing to configure the DMA for
+         ADC regular channels. Since converted regular channel values are stored
+         into a unique data register, it is useful to use DMA for conversion of
+         more than one regular channel. This avoids the loss of the data already
+         stored in the ADC Data register. 
+         When the DMA mode is enabled (using the ADC_DMACmd() function), after
+         each conversion of a regular channel, a DMA request is generated.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= ADC_CR2_DMA;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= (uint32_t) (~ADC_CR2_DMA);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group6 Injected channels Configuration functions
+ *  @brief   Injected channels Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Injected channels Configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to configure the ADC Injected
+         channels, it is composed of 2 sub sections : 
+         (#) Configuration functions for Injected channels: This subsection provides 
+             functions allowing to configure the ADC injected channels :    
+             (++) Configure the rank in the injected group sequencer for each channel
+             (++) Configure the sampling time for each channel    
+             (++) Activate the Auto injected Mode  
+             (++) Activate the Discontinuous Mode 
+             (++) Scan mode activation  
+             (++) External/software trigger source   
+             (++) External trigger edge 
+             (++) Injected channels sequencer.
+    
+         (#) Get the Specified Injected channel conversion data: This subsection 
+             provides an important function in the ADC peripheral since it returns
+             the converted data of the specific injected channel.
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  * @param  Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+  *            @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+  *            @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+  *            @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles	
+  *            @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles	
+  *            @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles	
+  *            @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles	
+  *            @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SMPR_SMP_SET << (3*(ADC_Channel - 10));
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = ADC_SMPR_SMP_SET << (3 * ADC_Channel);
+    /* Clear the old channel sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new channel sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & ADC_JSQR_JL)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = ADC_JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  Length: The sequencer length. 
+  *          This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequence length JL bits */
+  tmpreg1 &= (uint32_t)(~ADC_JSQR_JL);
+  /* Set the injected sequence length JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  ADC_Offset: the offset value for the selected ADC injected channel
+  *          This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t ADC_Offset)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(ADC_Offset));  
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)ADC_Offset;
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+  *            @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+  *            @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+  *            @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+  *            @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+  *            @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+  *            @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+  *                                                       capture compare4 event selected (for ADC1 and ADC2)                       
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)                         
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+  *            @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)                         
+  *            @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)                        
+  *            @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+  *                                          by external trigger (for ADC1, ADC2 and ADC3)
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= (uint32_t) (~ADC_CR2_JEXTSEL);
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the ADCx injected channels conversion through
+  *         external trigger
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC external trigger start of
+  *         injected conversion.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC external event selection for injected group */
+    ADCx->CR2 |= ADC_CR2_JEXTTRIG;
+  }
+  else
+  {
+    /* Disable the selected ADC external event selection for injected group */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_JEXTTRIG);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected ADC start of the injected 
+  *         channels conversion.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC software start injected conversion.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC conversion for injected group on external event and start the selected
+       ADC injected conversion */
+    ADCx->CR2 |= (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG);
+  }
+  else
+  {
+    /* Disable the selected ADC conversion on external event for injected group and stop the selected
+       ADC injected conversion */
+    ADCx->CR2 &= (uint32_t) ~(ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG);
+  }
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= ADC_CR1_JAUTO;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= ADC_CR1_JDISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= (uint32_t) (~ADC_CR1_JDISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + ADC_JDR_OFFSET;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp);   
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ =============================================================================== 
+
+    [..] This section provides functions allowing to configure the ADC Interrupts,
+         get the status and clear flags and Interrupts pending bits.
+  
+    [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided
+         into 3 groups:
+  
+  *** Flags and Interrupts for ADC regular channels ***
+  =====================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_EOC : Regular channel end of conversion to indicate 
+                the end of sequence of regular GROUP conversions
+           (##) ADC_FLAG_STRT: Regular channel start to indicate when regular
+                CHANNEL conversion starts.
+
+        (+)Interrupts :
+           (##) ADC_IT_EOC : specifies the interrupt source for Regular channel
+                end of conversion event.
+  
+  
+  *** Flags and Interrupts for ADC Injected channels ***
+  ======================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_JEOC : Injected channel end of conversion to indicate
+                at the end of injected GROUP conversion
+           (##) ADC_FLAG_JSTRT : Injected channel start to indicate when injected
+                GROUP conversion starts.
+
+        (+)Interrupts :
+           (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
+                end of conversion event.
+
+  *** General Flags and Interrupts for the ADC ***
+  ================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_AWD : Analog watchdog + to indicate if the converted voltage
+                              crosses the programmed thresholds values.
+        (+)Interrupts :
+           (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.  
+
+    [..] The user should identify which mode will be used in his application to
+         manage the ADC controller events: Polling mode or Interrupt mode.
+  
+    [..] In the Polling Mode it is advised to use the following functions:
+         (+) ADC_GetFlagStatus() : to check if flags events occur. 
+         (+) ADC_ClearFlag()     : to clear the flags events.
+      
+    [..] In the Interrupt Mode it is advised to use the following functions:
+         (+) ADC_ITConfig()       : to enable or disable the interrupt source.
+         (+) ADC_GetITStatus()    : to check if Interrupt occurs.
+         (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                       (corresponding Flag). 
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @param  NewState: new state of the specified ADC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = ADC_IT >> 8;
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+  * @brief  Gets the selected ADC calibration status.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval The new state of ADC calibration (SET or RESET).
+  */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of CAL bit */
+  if ((ADCx->CR2 & ADC_CR2_CAL) != (uint32_t)RESET)
+  {
+    /* CAL bit is set: calibration on going */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CAL bit is reset: end of calibration */
+    bitstatus = RESET;
+  }
+  /* Return the CAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Gets the selected ADC reset calibration registers status.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @retval The new state of ADC reset calibration registers (SET or RESET).
+  */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Check the status of RSTCAL bit */
+  if ((ADCx->CR2 & ADC_CR2_RSTCAL) != (uint32_t)RESET)
+  {
+    /* RSTCAL bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RSTCAL bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RSTCAL bit status */
+  return  bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c
new file mode 100644
index 0000000..e020584
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c
@@ -0,0 +1,1669 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_can.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Controller area network (CAN) peripheral:           
+  *           + Initialization and Configuration 
+  *           + CAN Frames Transmission 
+  *           + CAN Frames Reception    
+  *           + Operation modes switch  
+  *           + Error management          
+  *           + Interrupts and flags        
+  *         
+  *  @verbatim
+================================================================================
+                      ##### How to use this driver #####
+================================================================================
+    [..]
+    (#) Enable the CAN controller interface clock using 
+        RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 
+
+    (#) CAN pins configuration
+       (++) Enable the clock for the CAN GPIOs using the following function:
+            RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+       (++) Connect the involved CAN pins to AF9 using the following function 
+            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); 
+       (++) Configure these CAN pins in alternate function mode by calling
+            the function  GPIO_Init();   
+    (#) Initialise and configure the CAN using CAN_Init() and 
+        CAN_FilterInit() functions.   
+
+    (#) Transmit the desired CAN frame using CAN_Transmit() function.
+
+    (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
+        function.
+
+    (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
+        function.  
+
+    (#) Receive a CAN frame using CAN_Recieve() function.
+
+    (#) Release the receive FIFOs using CAN_FIFORelease() function.
+
+    (#) Return the number of pending received frames using 
+        CAN_MessagePending() function.            
+
+    (#) To control CAN events you can use one of the following two methods:
+       (++) Check on CAN flags using the CAN_GetFlagStatus() function.  
+       (++) Use CAN interrupts through the function CAN_ITConfig() at 
+            initialization phase and CAN_GetITStatus() function into 
+            interrupt routines to check if the event has occurred or not.
+            After checking on a flag you should clear it using CAN_ClearFlag()
+            function. And after checking on an interrupt event you should 
+            clear it using CAN_ClearITPendingBit() function.            
+
+  *  @endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_can.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CAN 
+  * @brief CAN driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CAN Master Control Register bits */
+#define MCR_DBF           ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ       ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT         ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR     ((uint32_t)0x08000000) 
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R    ((uint32_t)0x04000000) 
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R    ((uint32_t)0x02000000) 
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR     ((uint32_t)0x01000000) 
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR     ((uint32_t)0x00F00000) 
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02) 
+
+#define CAN_MODE_MASK     ((uint32_t) 0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/** @defgroup CAN_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to 
+         (#) Initialize the CAN peripherals : Prescaler, operating mode, the maximum number 
+             of time quanta to perform resynchronization, the number of time quanta in
+             Bit Segment 1 and 2 and many other modes. 
+         (#) Configures the CAN reception filter.
+         (#) Select the start bank filter for slave CAN.
+         (#) Enables or disables the Debug Freeze mode for CAN
+         (#) Enables or disables the CAN Time Trigger Operation communication mode
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @retval None
+  */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+ 
+  if (CANx == CAN1)
+  {
+    /* Enable CAN1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+    /* Release CAN1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
+  *         the configuration information for the CAN peripheral.
+  * @retval Constant indicates initialization succeed which will be 
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
+  */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Exit from sleep mode */
+  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  CANx->MCR |= CAN_MCR_INRQ ;
+
+  /* Wait the acknowledge */
+  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  /* Check acknowledge */
+  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else 
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+    /* Request leave initialisation */
+    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+   /* Wait the acknowledge */
+   wait_ack = 0;
+
+   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+   {
+     wait_ack++;
+   }
+
+    /* ...and check acknowledged */
+    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
+  *         contains the configuration information.
+  * @retval None
+  */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+
+  /* Filter Deactivation */
+  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CAN1->FS1R |= filter_number_bit_pos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+  }
+  
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN1->FA1R |= filter_number_bit_pos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Fills each CAN_InitStruct member with its default value.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
+  * @retval None
+  */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+  
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+  
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+  
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+  
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+  
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+  
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+  
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+  
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+  
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+  
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+  
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+  * @brief  Select the start bank filter for slave CAN.
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
+  * @retval None
+  */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+  
+  /* Enter Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+  
+  /* Select the start slave bank */
+  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+  
+  /* Leave Initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Enables or disables the DBG Freeze for CAN.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: new state of the CAN peripheral. 
+  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *          during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *          or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Debug Freeze  */
+    CANx->MCR |= MCR_DBF;
+  }
+  else
+  {
+    /* Disable Debug Freeze */
+    CANx->MCR &= ~MCR_DBF;
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
+  *         sent over the CAN bus.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
+  *         When enabled, Time stamp (TIME[15:0]) value is  sent in the last two
+  *         data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] 
+  *         in data byte 7. 
+  * @retval None
+  */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TTCM mode */
+    CANx->MCR |= CAN_MCR_TTCM;
+
+    /* Set TGT bits */
+    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+  }
+  else
+  {
+    /* Disable the TTCM mode */
+    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+    /* Reset TGT bits */
+    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group2 CAN Frames Transmission functions
+ *  @brief    CAN Frames Transmission functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### CAN Frames Transmission functions ##### 
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (#) Initiate and transmit a CAN frame message (if there is an empty mailbox).
+         (#) Check the transmission status of a CAN Frame
+         (#) Cancel a transmit request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+  * @retval The number of the mailbox that is used for transmission or
+  *         CAN_TxStatus_NoMailBox if there is no empty mailbox.
+  */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    /* Set up the Id */
+    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+    if (TxMessage->IDE == CAN_Id_Standard)
+    {
+      assert_param(IS_CAN_STDID(TxMessage->StdId));  
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+                                                  TxMessage->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+                                                  TxMessage->IDE | \
+                                                  TxMessage->RTR);
+    }
+    
+    /* Set up the DLC */
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
+    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
+                                             ((uint32_t)TxMessage->Data[4]));
+    /* Request transmission */
+    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+  }
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  Checks the transmission status of a CAN Frame.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  TransmitMailbox: the number of the mailbox that is used for transmission.
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, 
+  *         CAN_TxStatus_Failed in an other case.
+  */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ 
+  switch (TransmitMailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+      break;
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+      break;
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+      break;
+    default:
+      state = CAN_TxStatus_Failed;
+      break;
+  }
+  switch (state)
+  {
+      /* transmit pending  */
+    case (0x0): state = CAN_TxStatus_Pending;
+      break;
+      /* transmit failed  */
+     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+      break;
+      /* transmit succeeded  */
+    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+      break;
+    default: state = CAN_TxStatus_Failed;
+      break;
+  }
+  return (uint8_t) state;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  Mailbox: Mailbox number.
+  * @retval None
+  */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+  /* abort transmission */
+  switch (Mailbox)
+  {
+    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+      break;
+    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+      break;
+    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+      break;
+    default:
+      break;
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group3 CAN Frames Reception functions
+ *  @brief    CAN Frames Reception functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### CAN Frames Reception functions ##### 
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (#) Receive a correct CAN frame
+         (#) Release a specified receive FIFO (2 FIFOs are available)
+         (#) Return the number of the pending received CAN frames
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
+  *         CAN DLC, CAN data and FMI number.
+  * @retval None
+  */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Get the Id */
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  if (RxMessage->IDE == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Releases the specified receive FIFO.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Returns the number of pending received messages.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval NbMessage : which is the number of pending message.
+  */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+  return message_pending;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group4 CAN Operation modes functions
+ *  @brief    CAN Operation modes functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### CAN Operation modes functions  ##### 
+ ===============================================================================  
+    [..] This section provides functions allowing to select the CAN Operation modes
+         (#) sleep mode
+         (#) normal mode 
+         (#) initialization mode
+
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Selects the CAN Operation mode.
+  * @param  CAN_OperatingMode: CAN Operating Mode.
+  *          This parameter can be one of @ref CAN_OperatingMode_status.
+  * @retval status of the requested mode which can be 
+  *         - CAN_ModeStatus_Failed:  CAN failed entering the specific mode 
+  *         - CAN_ModeStatus_Success: CAN Succeed entering the specific mode 
+  */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+  
+  /* Timeout for INAK or also for SLAK bits*/
+  uint32_t timeout = INAK_TIMEOUT; 
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    /* Request initialisation */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
+    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    /* Request Sleep mode */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/**
+  * @brief  Enters the Sleep (low power) mode.
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
+  */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Request Sleep mode */
+   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+  {
+    /* Sleep mode not entered */
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+  /* return sleep mode status */
+   return (uint8_t)sleepstatus;
+}
+
+/**
+  * @brief  Wakes up the CAN peripheral from sleep mode .
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
+  */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+  uint32_t wait_slak = SLAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Wake up request */
+  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+    
+  /* Sleep mode status */
+  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+  {
+   wait_slak--;
+  }
+  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+  {
+   /* wake up done : Sleep mode exited */
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+  /* return wakeup status */
+  return (uint8_t)wakeupstatus;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group5 CAN Bus Error management functions
+ *  @brief    CAN Bus Error management functions 
+ *
+@verbatim    
+ ===============================================================================
+          ##### CAN Bus Error management functions  ##### 
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+         (#) Return the CANx's last error code (LEC)
+         (#) Return the CANx Receive Error Counter (REC)
+         (#) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+    [..] 
+         (@) If TEC is greater than 255, The CAN is in bus-off state.
+         (@) If REC or TEC are greater than 96, an Error warning flag occurs.
+         (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Returns the CANx's last error code (LEC).
+  * @param  CANx: where x can be 1 to select the CAN1 peripheral.
+  * @retval Error code: 
+  *          - CAN_ErrorCode_NoErr: No Error  
+  *          - CAN_ErrorCode_StuffErr: Stuff Error
+  *          - CAN_ErrorCode_FormErr: Form Error
+  *          - CAN_ErrorCode_ACKErr : Acknowledgment Error
+  *          - CAN_ErrorCode_BitRecessiveErr: Bit Recessive Error
+  *          - CAN_ErrorCode_BitDominantErr: Bit Dominant Error
+  *          - CAN_ErrorCode_CRCErr: CRC Error
+  *          - CAN_ErrorCode_SoftwareSetErr: Software Set Error  
+  */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+  uint8_t errorcode=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the error code*/
+  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+  
+  /* Return the error code*/
+  return errorcode;
+}
+
+/**
+  * @brief  Returns the CANx Receive Error Counter (REC).
+  * @note   In case of an error during reception, this counter is incremented 
+  *         by 1 or by 8 depending on the error condition as defined by the CAN 
+  *         standard. After every successful reception, the counter is 
+  *         decremented by 1 or reset to 120 if its value was higher than 128. 
+  *         When the counter value exceeds 127, the CAN controller enters the 
+  *         error passive state.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN Receive Error Counter. 
+  */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the Receive Error Counter*/
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+  
+  /* Return the Receive Error Counter*/
+  return counter;
+}
+
+
+/**
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
+  */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+  
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  return counter;
+}
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Group6 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+          ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+    [..] This section provides functions allowing to configure the CAN Interrupts and 
+         to get the status and clear flags and Interrupts pending bits.
+         
+         The CAN provides 14 Interrupts sources and 15 Flags:
+
+  *** Flags ***
+  =============
+    [..]The 15 flags can be divided on 4 groups: 
+
+        (+)Transmit Flags
+           (##) CAN_FLAG_RQCP0, 
+           (##) CAN_FLAG_RQCP1, 
+           (##) CAN_FLAG_RQCP2  : Request completed MailBoxes 0, 1 and 2  Flags
+                Set when when the last request (transmit or abort) has 
+                been performed. 
+
+        (+)Receive Flags
+           (##) CAN_FLAG_FMP0,
+           (##) CAN_FLAG_FMP1   : FIFO 0 and 1 Message Pending Flags 
+                set to signal that messages are pending in the receive 
+                FIFO.
+                These Flags are cleared only by hardware. 
+           (##) CAN_FLAG_FF0,
+           (##) CAN_FLAG_FF1    : FIFO 0 and 1 Full Flags
+                set when three messages are stored in the selected 
+                FIFO.
+           (##) CAN_FLAG_FOV0
+           (##) CAN_FLAG_FOV1   : FIFO 0 and 1 Overrun Flags
+                set when a new message has been received and passed 
+                the filter while the FIFO was full.         
+
+        (+)Operating Mode Flags
+           (##) CAN_FLAG_WKU    : Wake up Flag
+                set to signal that a SOF bit has been detected while 
+                the CAN hardware was in Sleep mode. 
+                
+           (##) CAN_FLAG_SLAK   : Sleep acknowledge Flag
+                Set to signal that the CAN has entered Sleep Mode. 
+    
+        (+)Error Flags
+           (##) CAN_FLAG_EWG    : Error Warning Flag
+                Set when the warning limit has been reached (Receive 
+                Error Counter or Transmit Error Counter greater than 96). 
+                This Flag is cleared only by hardware.
+           (##) CAN_FLAG_EPV    : Error Passive Flag
+                Set when the Error Passive limit has been reached 
+                (Receive Error Counter or Transmit Error Counter 
+                greater than 127).
+                This Flag is cleared only by hardware.
+           (##) CAN_FLAG_BOF    : Bus-Off Flag
+                set when CAN enters the bus-off state. The bus-off 
+                state is entered on TEC overflow, greater than 255.
+                This Flag is cleared only by hardware.
+           (##) CAN_FLAG_LEC    : Last error code Flag
+                set If a message has been transferred (reception or
+                transmission) with error, and the error code is hold.              
+                
+  *** Interrupts ***
+  ==================
+    [..]The 14 interrupts can be divided on 4 groups: 
+  
+        (+)Transmit interrupt
+           (##) CAN_IT_TME   :  Transmit mailbox empty Interrupt
+                if enabled, this interrupt source is pending when 
+                no transmit request are pending for Tx mailboxes.      
+
+        (+)Receive Interrupts
+           (##) CAN_IT_FMP0,
+           (##) CAN_IT_FMP1  :  FIFO 0 and FIFO1 message pending Interrupts
+                if enabled, these interrupt sources are pending when 
+                messages are pending in the receive FIFO.
+                The corresponding interrupt pending bits are cleared 
+                only by hardware.
+           (##) CAN_IT_FF0,              
+           (##) CAN_IT_FF1   :  FIFO 0 and FIFO1 full Interrupts
+                if enabled, these interrupt sources are pending when
+                three messages are stored in the selected FIFO.
+           (##) CAN_IT_FOV0,        
+           (##) CAN_IT_FOV1    :  FIFO 0 and FIFO1 overrun Interrupts        
+                if enabled, these interrupt sources are pending when
+                a new message has been received and passed the filter
+                while the FIFO was full.
+
+        (+)Operating Mode Interrupts
+           (##) CAN_IT_WKU     :  Wake-up Interrupt
+                if enabled, this interrupt source is pending when 
+                a SOF bit has been detected while the CAN hardware was 
+                in Sleep mode.
+                                  
+           (##) CAN_IT_SLK     :  Sleep acknowledge Interrupt
+                if enabled, this interrupt source is pending when 
+                the CAN has entered Sleep Mode.       
+
+        (+)Error Interrupts 
+           (##) CAN_IT_EWG     :  Error warning Interrupt 
+                if enabled, this interrupt source is pending when
+                the warning limit has been reached (Receive Error 
+                Counter or Transmit Error Counter=96). 
+                
+           (##) CAN_IT_EPV     :  Error passive Interrupt        
+                if enabled, this interrupt source is pending when
+                the Error Passive limit has been reached (Receive 
+                Error Counter or Transmit Error Counter>127).
+                
+           (##) CAN_IT_BOF     :  Bus-off Interrupt
+                if enabled, this interrupt source is pending when
+                CAN enters the bus-off state. The bus-off state is 
+                entered on TEC overflow, greater than 255.
+                This Flag is cleared only by hardware.
+                
+           (##) CAN_IT_LEC     :  Last error code Interrupt        
+                if enabled, this interrupt source is pending  when
+                a message has been transferred (reception or
+                transmission) with error, and the error code is hold.
+                
+           (##) CAN_IT_ERR     :  Error Interrupt
+                if enabled, this interrupt source is pending when 
+                an error condition is pending.      
+
+  *** Managing the CAN controller events ***
+  ==========================================
+    [..]The user should identify which mode will be used in his application to manage 
+        the CAN controller events: Polling mode or Interrupt mode.
+        (+)In the Polling Mode it is advised to use the following functions:
+           (##) CAN_GetFlagStatus() : to check if flags events occur. 
+           (##) CAN_ClearFlag()     : to clear the flags events.
+
+        (+)In the Interrupt Mode it is advised to use the following functions:
+           (##) CAN_ITConfig()       : to enable or disable the interrupt source.
+           (##) CAN_GetITStatus()    : to check if Interrupt occurs.
+           (##) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag).
+             -@@-This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts 
+                 pending bits since there are cleared only by hardware. 
+  
+@endverbatim
+  * @{
+  */ 
+/**
+  * @brief  Enables or disables the specified CANx interrupts.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+  *          This parameter can be: 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @param  NewState: new state of the CAN interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CANx interrupt */
+    CANx->IER |= CAN_IT;
+  }
+  else
+  {
+    /* Disable the selected CANx interrupt */
+    CANx->IER &= ~CAN_IT;
+  }
+}
+/**
+  * @brief  Checks whether the specified CAN flag is set or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag   
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag   
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag  
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag      
+  * @retval The new state of CAN_FLAG (SET or RESET).
+  */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+  
+
+  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CAN's pending flags.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag 
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag  
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag        
+  * @retval None
+  */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+  
+  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+  {
+    /* Clear the selected CAN flags */
+    CANx->ESR = (uint32_t)RESET;
+  }
+  else /* MSR or TSR or RF0R or RF1R */
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF0R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF1R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+    {
+      /* Transmit Flags */
+      CANx->TSR = (uint32_t)(flagtmp);
+    }
+    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+    {
+      /* Operating mode Flags */
+      CANx->MSR = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @retval The current state of CAN_IT (SET or RESET).
+  */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  ITStatus itstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  
+  /* check the interrupt enable bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+   /* in case the Interrupt is enabled, .... */
+    switch (CAN_IT)
+    {
+      case CAN_IT_TME:
+        /* Check CAN_TSR_RQCPx bits */
+        itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
+        break;
+      case CAN_IT_FMP0:
+        /* Check CAN_RF0R_FMP0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
+        break;
+      case CAN_IT_FF0:
+        /* Check CAN_RF0R_FULL0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
+        break;
+      case CAN_IT_FOV0:
+        /* Check CAN_RF0R_FOVR0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
+        break;
+      case CAN_IT_FMP1:
+        /* Check CAN_RF1R_FMP1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
+        break;
+      case CAN_IT_FF1:
+        /* Check CAN_RF1R_FULL1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
+        break;
+      case CAN_IT_FOV1:
+        /* Check CAN_RF1R_FOVR1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
+        break;
+      case CAN_IT_WKU:
+        /* Check CAN_MSR_WKUI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
+        break;
+      case CAN_IT_SLK:
+        /* Check CAN_MSR_SLAKI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
+        break;
+      case CAN_IT_EWG:
+        /* Check CAN_ESR_EWGF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
+        break;
+      case CAN_IT_EPV:
+        /* Check CAN_ESR_EPVF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
+        break;
+      case CAN_IT_BOF:
+        /* Check CAN_ESR_BOFF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
+        break;
+      case CAN_IT_LEC:
+        /* Check CAN_ESR_LEC bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
+        break;
+      case CAN_IT_ERR:
+        /* Check CAN_MSR_ERRI bit */ 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
+        break;
+      default:
+        /* in case of error, return RESET */
+        itstatus = RESET;
+        break;
+    }
+  }
+  else
+  {
+   /* in case the Interrupt is not enabled, return RESET */
+    itstatus  = RESET;
+  }
+  
+  /* Return the CAN_IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the CANx's interrupt pending bits.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt 
+  * @retval None
+  */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+    case CAN_IT_TME:
+      /* Clear CAN_TSR_RQCPx (rc_w1)*/
+      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
+      break;
+    case CAN_IT_FF0:
+      /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FULL0; 
+      break;
+    case CAN_IT_FOV0:
+      /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FOVR0; 
+      break;
+    case CAN_IT_FF1:
+      /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FULL1;  
+      break;
+    case CAN_IT_FOV1:
+      /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FOVR1; 
+      break;
+    case CAN_IT_WKU:
+      /* Clear CAN_MSR_WKUI (rc_w1)*/
+      CANx->MSR = CAN_MSR_WKUI;  
+      break;
+    case CAN_IT_SLK:
+      /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
+      CANx->MSR = CAN_MSR_SLAKI;   
+      break;
+    case CAN_IT_EWG:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI;
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ 
+      break;
+    case CAN_IT_EPV:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+      break;
+    case CAN_IT_BOF:
+      /* Clear CAN_MSR_ERRI (rc_w1) */ 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+       break;
+    case CAN_IT_LEC:
+      /*  Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+      break;
+    case CAN_IT_ERR:
+      /*Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
+       break;
+    default:
+       break;
+   }
+}
+ /**
+  * @}
+  */
+
+/**
+  * @brief  Checks whether the CAN interrupt has occurred or not.
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
+  * @param  It_Bit: specifies the interrupt source bit to check.
+  * @retval The new state of the CAN Interrupt (SET or RESET).
+  */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    /* CAN_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_IT is reset */
+    pendingbitstatus = RESET;
+  }
+  return pendingbitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c
new file mode 100644
index 0000000..1dd33b8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c
@@ -0,0 +1,620 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_cec.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Consumer Electronics Control (CEC) peripheral:
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + Interrupts and flags management
+  *               
+  *  @verbatim
+  ==============================================================================
+                            ##### CEC features #####
+  ==============================================================================
+      [..] This device provides some features:
+           (#) Supports HDMI-CEC specification 1.4.
+           (#) Supports two source clocks(HSI/244 or LSE).
+           (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
+               It can genarate an interrupt in the CEC clock domain that the CPU 
+               wakes up from the low power mode.
+           (#) Configurable Signal Free Time before of transmission start. The 
+               number of nominal data bit periods waited before transmission can be
+               ruled by Hardware or Software.
+           (#) Configurable Peripheral Address (multi-addressing configuration).
+           (#) Supports listen mode.The CEC Messages addressed to different destination
+               can be received without interfering with CEC bus when Listen mode option is enabled.
+           (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
+           (#) Error detection with configurable error bit generation.
+           (#) Arbitration lost error in the case of two CEC devices starting at the same time.
+
+                            ##### How to use this driver ##### 
+  ==============================================================================
+      [..] This driver provides functions to configure and program the CEC device,
+       follow steps below:
+           (#) The source clock can be configured using:
+               (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) 
+               (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
+           (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
+           (#) Peripherals alternate function.
+               (++) Connect the pin to the desired peripherals' Alternate Function (AF) using 
+               GPIO_PinAFConfig() function.
+               (++) Configure the desired pin in alternate function by:
+               GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+               (++) Select the type open-drain and output speed via GPIO_OType 
+               and GPIO_Speed members.
+               (++) Call GPIO_Init() function.
+           (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation 
+               and Bit error generation using the CEC_Init() function.
+               The function CEC_Init() must be called when the CEC peripheral is disabled.
+           (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
+           (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
+           (#) Enable the NVIC and the corresponding interrupt using the function 
+               CEC_ITConfig() if you need to use interrupt mode.
+               CEC_ITConfig() must be called before enabling the CEC peripheral.
+           (#) Enable the CEC using the CEC_Cmd() function.
+           (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
+           (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() 
+           (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() 
+               and Receive the last transmitted byte using CEC_ReceiveDataByte().
+           (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
+      [..]
+           (@) If the listen mode is enabled, Stop reception generation and Bit error generation 
+               must be in reset state.
+           (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
+               must be called before CEC_StartOfMessage().
+  
+   @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_cec.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CEC 
+  * @brief CEC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BROADCAST_ADDRESS      ((uint32_t)0x0000F)      /* Broadcast address  */
+#define CFGR_CLEAR_MASK        ((uint32_t)0x7000FE00)   /* CFGR register Mask */
+
+/* ------------- CEC registers bit address in the alias region -------------- */
+#define CEC_OFFSET                (CEC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+/* Alias word address of CECEN bit */
+#define CR_OFFSET                 (CEC_OFFSET + 0x00)
+#define CECEN_BitNumber           0x00
+#define CR_CECEN_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CECEN_BitNumber * 4))
+
+/* Alias word address of TXSOM bit */
+#define TXSOM_BitNumber           0x01
+#define CR_TXSOM_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXSOM_BitNumber * 4))
+
+/* Alias word address of TXEOM bit */
+#define TXEOM_BitNumber           0x02
+#define CR_TXEOM_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TXEOM_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of LSTN bit */
+#define CFGR_OFFSET               (CEC_OFFSET + 0x04)
+#define LSTN_BitNumber            0x1F
+#define CFGR_LSTN_BB              (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (LSTN_BitNumber * 4))
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Private_Functions
+  * @{
+  */
+
+/** @defgroup CEC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim  
+ ===============================================================================
+                            ##### Initialization and Configuration functions #####
+ ===============================================================================
+      [..] This section provides functions allowing to initialize:
+            (+) CEC own addresses
+            (+) CEC Signal Free Time
+            (+) CEC Rx Tolerance
+            (+) CEC Stop Reception
+            (+) CEC Bit Rising Error
+            (+) CEC Long Bit Period Error
+      [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
+           Messages addressed to different destination can be received when Listen mode is 
+           enabled without interfering with CEC bus.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes all CEC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CEC_DeInit(void)
+{
+  /* Enable all CEC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
+
+  /* Release all CEC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CEC peripheral according to the specified 
+  *         parameters in the CEC_InitStruct. 
+  * @note   The CEC parameters must be configured before enabling the CEC peripheral.
+  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
+  *         contains the configuration information for the specified
+  *         CEC peripheral.
+  * @retval None
+  */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
+  assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
+  assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
+  assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
+  assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
+  assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
+  assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
+
+  /*---------------------------- CEC CFGR Configuration ----------------------*/
+  /* Get the CEC CFGR value */
+  tmpreg = CEC->CFGR;
+
+  /* Clear CFGR bits */
+  tmpreg &= CFGR_CLEAR_MASK;
+
+  /* Configure the CEC peripheral */
+  tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
+             CEC_InitStruct->CEC_StopReception  | CEC_InitStruct->CEC_BitRisingError |
+             CEC_InitStruct->CEC_LongBitPeriodError|CEC_InitStruct->CEC_BRDNoGen |
+             CEC_InitStruct->CEC_SFTOption);
+
+  /* Write to CEC CFGR  register */
+  CEC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Fills each CEC_InitStruct member with its default value.
+  * @param  CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
+{
+  CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
+  CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
+  CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
+  CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
+  CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
+  CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
+  CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
+}
+
+/**
+  * @brief  Enables or disables the CEC peripheral.
+  * @param  NewState: new state of the CEC peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_Cmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_CECEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the CEC Listen Mode.
+  * @param  NewState: new state of the Listen Mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ListenModeCmd(FunctionalState NewState)
+{ 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CFGR_LSTN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Defines the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+  uint32_t tmp =0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+  tmp = 1 <<(CEC_OwnAddress + 16);
+  /* Set the CEC own address */
+  CEC->CFGR |= tmp;
+}
+
+/**
+  * @brief  Clears the Own Address of the CEC device.
+  * @param  CEC_OwnAddress: The CEC own address.
+  * @retval None
+  */
+void CEC_OwnAddressClear(void)
+{
+  /* Set the CEC own address */
+  CEC->CFGR = 0x0;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group2 Data transfers functions
+ *  @brief    Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                            ##### Data transfers functions #####
+ ===============================================================================
+    [..] This section provides functions allowing the CEC data transfers.The read 
+         access of the CEC_RXDR register can be done using the CEC_ReceiveData()function 
+         and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be 
+         done using CEC_SendData() function.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the CEC peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void CEC_SendData(uint8_t Data)
+{
+  /* Transmit Data */
+  CEC->TXDR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the CEC peripheral.
+  * @param  None
+  * @retval The received data.
+  */
+uint8_t CEC_ReceiveData(void)
+{
+  /* Receive Data */
+  return (uint8_t)(CEC->RXDR);
+}
+
+/**
+  * @brief  Starts a new message.
+  * @param  None
+  * @retval None
+  */
+void CEC_StartOfMessage(void)
+{
+  /* Starts of new message */
+  *(__IO uint32_t *) CR_TXSOM_BB = (uint32_t)0x1;
+}
+
+/**
+  * @brief  Transmits message with an EOM bit.
+  * @param  None
+  * @retval None
+  */
+void CEC_EndOfMessage(void)
+{
+  /* The data byte will be transmitted with an EOM bit */
+  *(__IO uint32_t *) CR_TXEOM_BB = (uint32_t)0x1;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Group3 Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions
+*
+@verbatim
+ ===============================================================================
+                            ##### Interrupts and flags management functions ##### 
+ ===============================================================================
+    [..] This section provides functions allowing to configure the CEC Interrupts
+         sources and check or clear the flags or pending bits status.
+    [..] The user should identify which mode will be used in his application to manage
+         the communication: Polling mode or Interrupt mode.
+  
+    [..] In polling mode, the CEC can be managed by the following flags:
+            (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
+            (+) CEC_FLAG_TXERR  : to indicate an error occurs during transmission mode.
+                                  The initiator detects low impedance in the CEC line.
+            (+) CEC_FLAG_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                                  The transmission is enabled while the software has not yet 
+                                  loaded any value into the TXDR register.
+            (+) CEC_FLAG_TXEND  : to indicate the end of successful transmission.
+            (+) CEC_FLAG_TXBR   : to indicate the next transmission data has to be written to TXDR.
+            (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                  starting at the same time.
+            (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
+            (+) CEC_FLAG_LBPE   : to indicate a long bit period error generated during receive mode.
+            (+) CEC_FLAG_SBPE   : to indicate a short bit period error generated during receive mode.
+            (+) CEC_FLAG_BRE    : to indicate a bit rising error generated during receive mode.
+            (+) CEC_FLAG_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                                  A byte is not yet received while a new byte is stored in the RXDR register.
+            (+) CEC_FLAG_RXEND  : to indicate the end Of reception
+            (+) CEC_FLAG_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                  stored into the RXDR buffer.
+    [..]
+           (@)In this Mode, it is advised to use the following functions:
+              FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
+              void CEC_ClearFlag(uint16_t CEC_FLAG);
+
+    [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
+           (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge 
+           (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
+           (+) CEC_IT_TXERR  : to indicate an error occurs during transmission mode.
+                               The initiator detects low impedance in the CEC line.
+           (+) CEC_IT_TXUDR  : to indicate if an underrun error occurs in transmission mode.
+                               The transmission is enabled while the software has not yet 
+                               loaded any value into the TXDR register.
+           (+) CEC_IT_TXEND  : to indicate the end of successful transmission.
+           (+) CEC_IT_TXBR   : to indicate the next transmission data has to be written to TXDR register.
+           (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
+                                starting at the same time.
+           (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
+           (+) CEC_IT_LBPE   : to indicate a long bit period error generated during receive mode.
+           (+) CEC_IT_SBPE   : to indicate a short bit period error generated during receive mode.
+           (+) CEC_IT_BRE    : to indicate a bit rising error generated during receive mode.
+           (+) CEC_IT_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
+                               A byte is not yet received while a new byte is stored in the RXDR register.
+           (+) CEC_IT_RXEND  : to indicate the end Of reception
+           (+) CEC_IT_RXBR   : to indicate a new byte has been received from the CEC line and 
+                                stored into the RXDR buffer.
+    [..]
+           (@)In this Mode it is advised to use the following functions:
+              void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
+              ITStatus CEC_GetITStatus(uint16_t CEC_IT);
+              void CEC_ClearITPendingBit(uint16_t CEC_IT);
+              
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the selected CEC interrupts.
+  * @param  CEC_IT: specifies the CEC interrupt source to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @param  NewState: new state of the selected CEC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CEC interrupt */
+    CEC->IER |= CEC_IT;
+  }
+  else
+  {
+    CEC_IT =~CEC_IT;
+    /* Disable the selected CEC interrupt */
+    CEC->IER &= CEC_IT;
+  }
+}
+
+/**
+  * @brief  Gets the CEC flag status.
+  * @param  CEC_FLAG: specifies the CEC flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error.
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun.
+  *            @arg CEC_FLAG_RXEND: End Of Reception.
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.
+  * @retval The new state of CEC_FLAG (SET or RESET)
+  */
+FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) 
+{
+  FlagStatus bitstatus = RESET;
+
+  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+
+  /* Check the status of the specified CEC flag */
+  if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
+  {
+    /* CEC flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC flag is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC flag status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CEC's pending flags.
+  * @param  CEC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_FLAG_TXERR: Tx Error
+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request
+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost
+  *            @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge 
+  *            @arg CEC_FLAG_LBPE: Rx Long period Error
+  *            @arg CEC_FLAG_SBPE: Rx Short period Error
+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error
+  *            @arg CEC_FLAG_RXOVR: Rx Overrun
+  *            @arg CEC_FLAG_RXEND: End Of Reception
+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearFlag(uint16_t CEC_FLAG)
+{
+  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+  /* Clear the selected CEC flag */
+  CEC->ISR = CEC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified CEC interrupt has occurred or not.
+  * @param  CEC_IT: specifies the CEC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error.
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
+  *            @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
+  *            @arg CEC_IT_TXBR: Tx-Byte Request.
+  *            @arg CEC_IT_ARBLST: Arbitration Lost.
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
+  *            @arg CEC_IT_LBPE: Rx Long period Error.
+  *            @arg CEC_IT_SBPE: Rx Short period Error.
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error.
+  *            @arg CEC_IT_RXOVR: Rx Overrun.
+  *            @arg CEC_IT_RXEND: End Of Reception.
+  *            @arg CEC_IT_RXBR: Rx-Byte Received 
+  * @retval The new state of CEC_IT (SET or RESET).
+  */
+ITStatus CEC_GetITStatus(uint16_t CEC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CEC_GET_IT(CEC_IT));
+
+  /* Get the CEC IT enable bit status */
+  enablestatus = (CEC->IER & CEC_IT);
+
+  /* Check the status of the specified CEC interrupt */
+  if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* CEC interrupt is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CEC interrupt is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CEC interrupt status */
+  return  bitstatus;
+
+}
+
+/**
+  * @brief  Clears the CEC's interrupt pending bits.
+  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
+  *            @arg CEC_IT_TXERR: Tx Error
+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun
+  *            @arg CEC_IT_TXEND: End of Transmission
+  *            @arg CEC_IT_TXBR: Tx-Byte Request
+  *            @arg CEC_IT_ARBLST: Arbitration Lost
+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
+  *            @arg CEC_IT_LBPE: Rx Long period Error
+  *            @arg CEC_IT_SBPE: Rx Short period Error
+  *            @arg CEC_IT_BRE: Rx Bit Rising Error
+  *            @arg CEC_IT_RXOVR: Rx Overrun
+  *            @arg CEC_IT_RXEND: End Of Reception
+  *            @arg CEC_IT_RXBR: Rx-Byte Received
+  * @retval None
+  */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+  assert_param(IS_CEC_IT(CEC_IT));
+
+  /* Clear the selected CEC interrupt pending bits */
+  CEC->ISR = CEC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c
new file mode 100644
index 0000000..5360729
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c
@@ -0,0 +1,407 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_comp.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the comparators (COMP1 and COMP2) peripheral: 
+  *           + Comparators configuration
+  *           + Window mode control
+  *
+  *  @verbatim
+  *    
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]           
+         The device integrates two analog comparators COMP1 and COMP2:
+   
+         (+) The non inverting input is set to PA1 for COMP1 and to PA3
+             for COMP2.
+  
+         (+) The inverting input can be selected among: DAC_OUT1, 
+             1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
+             I/O (PA0 for COMP1 and PA2 for COMP2)
+  
+         (+) The COMP output is internally is available using COMP_GetOutputLevel()
+             and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
+             and PA2, PA7, PA12 for COMP2
+  
+         (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
+             and TIM3)
+  
+         (+) The two comparators COMP1 and COMP2 can be combined in window
+             mode and only COMP1 non inverting (PA1) can be used as non-
+             inverting input.
+  
+         (+) The two comparators COMP1 and COMP2 have interrupt capability 
+             with wake-up from Sleep and Stop modes (through the EXTI controller).
+             COMP1 and COMP2 outputs are internally connected to EXTI Line 21
+             and EXTI Line 22 respectively.
+                   
+
+                     ##### How to configure the comparator #####
+ ===============================================================================
+    [..] 
+           This driver provides functions to configure and program the Comparators 
+           of all STM32F37x devices.
+             
+    [..]   To use the comparator, perform the following steps:
+  
+         (#) Enable the SYSCFG APB clock to get write access to comparator
+             register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+         (#) Configure the comparator input in analog mode using GPIO_Init()
+  
+         (#) Configure the comparator output in alternate function mode
+             using GPIO_Init() and use GPIO_PinAFConfig() function to map the
+             comparator output to the GPIO pin
+  
+         (#) Configure the comparator using COMP_Init() function:
+                 (++)  Select the inverting input
+                 (++)  Select the output polarity  
+                 (++)  Select the output redirection
+                 (++)  Select the hysteresis level
+                 (++)  Select the power mode
+    
+         (#) Enable the comparator using COMP_Cmd() function
+  
+         (#) If required enable the COMP interrupt by configuring and enabling
+             EXTI line in Interrupt mode and selecting the desired sensitivity
+             level using EXTI_Init() function. After that enable the comparator
+             interrupt vector using NVIC_Init() function.
+  
+     @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_comp.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CSR register Mask */
+#define COMP_CSR_CLEAR_MASK              ((uint32_t)0x00003FFE)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup COMP_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+               ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Deinitializes COMP peripheral registers to their default reset values.
+  * @note   Deinitialization can't be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  None
+  * @retval None
+  */
+void COMP_DeInit(void)
+{
+  COMP->CSR = ((uint32_t)0x00000000);    /*!< Set COMP_CSR register to reset value */
+}
+
+/**
+  * @brief  Initializes the COMP peripheral according to the specified parameters
+  *         in COMP_InitStruct
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @note   By default, PA1 is selected as COMP1 non inverting input.
+  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains 
+  *         the configuration information for the specified COMP peripheral.
+  * @retval None
+  */
+void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
+  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
+  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
+  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
+  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
+
+  /*!< Get the COMP_CSR register value */
+  tmpreg = COMP->CSR;
+
+  /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ 
+  tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
+
+  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
+  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
+  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
+  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
+  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
+  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */   
+  tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
+                       COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
+                       COMP_InitStruct->COMP_Mode)<<COMP_Selection);
+
+  /*!< Write to COMP_CSR register */
+  COMP->CSR = tmpreg;  
+}
+
+/**
+  * @brief  Fills each COMP_InitStruct member with its default value.
+  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
+{
+  COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
+  COMP_InitStruct->COMP_Output = COMP_Output_None;
+  COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
+  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
+  COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
+}
+
+/**
+  * @brief  Enable or disable the COMP peripheral.
+  * @note   If the selected comparator is locked, enable/disable can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  COMP_Selection: the selected comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected
+  * @param  NewState: new state of the COMP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, the comparator compares the non inverting input with 
+  *         the inverting input and the comparison result is available on comparator output.
+  * @note   When disabled, the comparator doesn't perform comparison and the 
+  *         output level is low.
+  * @retval None
+  */
+void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected COMP peripheral */
+    COMP->CSR |= (uint32_t) (1<<COMP_Selection);
+  }
+  else
+  {
+    /* Disable the selected COMP peripheral  */
+    COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
+  }
+}
+
+/**
+  * @brief  Close or Open the SW1 switch.
+  * @note   This switch is solely intended to redirect signals onto high
+  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
+  * @param  NewState: New state of the analog switch.
+  *          This parameter can be: ENABLE or DISABLE. 
+  * @note   When enabled, the SW1 is closed; PA1 is connected to PA4
+  * @note   When disabled, the SW1 switch is open; PA1 is disconnected from PA4
+  * @retval None
+  */
+void COMP_SwitchCmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close SW1 switch */
+    COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
+  }
+  else
+  {
+    /* Open SW1 switch */
+    COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
+  }
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator. 
+  * @note   The output level depends on the selected polarity.
+  * @note   If the polarity is not inverted:
+  *          - Comparator output is low when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is high when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @note   If the polarity is inverted:
+  *          - Comparator output is high when the non-inverting input is at a lower
+  *            voltage than the inverting input
+  *          - Comparator output is low when the non-inverting input is at a higher
+  *            voltage than the inverting input
+  * @param  COMP_Selection: the selected comparator. 
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 selected
+  *            @arg COMP_Selection_COMP2: COMP2 selected  
+  * @retval Returns the selected comparator output level: low or high.
+  *       
+  */
+uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
+{
+  uint32_t compout = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if selected comparator output is high */
+  if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
+  {
+    compout = COMP_OutputLevel_High;
+  }
+  else
+  {
+    compout = COMP_OutputLevel_Low;
+  }
+
+  /* Return the comparator output level */
+  return (uint32_t)(compout);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group2 Window mode control function
+ *  @brief   Window mode control function 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Window mode control function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the window mode.
+  * @note   In window mode, COMP1 and COMP2 non inverting inputs are connected
+  *         together and only COMP1 non inverting input (PA1) can be used.
+  * @param  NewState: new state of the window mode.
+  *          This parameter can be :
+  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
+  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group3 COMP configuration locking function
+ *  @brief   COMP1 and COMP2 configuration locking function
+ *           COMP1 and COMP2 configuration can be locked each separately.
+ *           Unlocking is performed by system reset.
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Configuration Lock function #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+  * @note   Locking the configuration means that all control bits are read-only.
+  *         To unlock the comparator configuration, perform a system reset.
+  * @param  COMP_Selection: selects the comparator to be locked 
+  *          This parameter can be a value of the following values:
+  *            @arg COMP_Selection_COMP1: COMP1 configuration is locked.
+  *            @arg COMP_Selection_COMP2: COMP2 configuration is locked.  
+  * @retval None
+  */
+void COMP_LockConfig(uint32_t COMP_Selection)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Set the lock bit corresponding to selected comparator */
+  COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c
new file mode 100644
index 0000000..1563055
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c
@@ -0,0 +1,746 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_dac.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *           + DAC channels configuration: trigger, output buffer, data format
+  *           + DMA management
+  *           + Interrupts and flags management
+
+  * @verbatim
+  *
+ ===============================================================================
+                        ##### DAC Peripheral features #####
+ ===============================================================================
+    [..] The device integrates three 12-bit Digital Analog Converters:
+         (#) DAC1 integrates two DAC channels:
+             (++) DAC1 channel 1 with DAC1_OUT1 as output
+             (++) DAC1 channel 2 with DAC1_OUT2 as output
+             (++) The two channels can be used independently or simultaneously (dual mode)
+   
+         (#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output 
+   
+    [..] The Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+         and DACx_OUTy is available once writing to DHRx register using 
+         DAC_SetChannel1Data()/DAC_SetChannel2Data.
+      
+    [..] Digital to Analog conversion can be triggered by:
+         (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+             The used pin (GPIOx_Pin9) must be configured in input mode.
+  
+         (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM18
+             (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+             The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+             (++) TIM5 is applicable only for DAC1
+             (++) TIM18 is applicable only for DAC2
+      
+         (#) Software using DAC_Trigger_Software
+  
+    [..] Each DAC channel integrates an output buffer that can be used to 
+         reduce the output impedance, and to drive external loads directly
+         without having to add an external operational amplifier.
+         To enable, the output buffer use  
+         DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+         before caliing DAC_Init() function
+    
+    [..] Refer to the device datasheet for more details about output impedance
+         value with and without output buffer.
+  
+    [..] Both DAC1 channels can be used to generate
+         (#) Noise wave using DAC_WaveGeneration_Noise
+         (#) Triangle wave using DAC_WaveGeneration_Triangle
+          
+    [..] Wave generation can be disabled using DAC_WaveGeneration_None
+  
+    [..] The DAC data format can be:
+         (#) 8-bit right alignment using DAC_Align_8b_R
+         (#) 12-bit left alignment using DAC_Align_12b_L
+         (#) 12-bit right alignment using DAC_Align_12b_R
+  
+    [..] The analog output voltage on each DAC channel pin is determined
+         by the following equation: DAC_OUTx = VREF+ * DOR / 4095
+         with  DOR is the Data Output Register
+         VEF+ is the input voltage reference (refer to the device datasheet)
+         e.g. To set DAC_OUT1 to 0.7V, use
+         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+         Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  
+    [..] A DMA1 request can be generated when an external trigger (but not
+         a software trigger) occurs if DMA1 requests are enabled using
+         DAC_DMACmd()
+         DMA1 requests are mapped as following:
+         (+) DAC channel1 is mapped on DMA1 channel3 which must be already 
+             configured
+         (+) DAC channel2 is mapped on DMA1 channel4 which must be already 
+             configured
+  
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable DAC APB1 clock to get write access to DAC registers
+             using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+
+         (+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
+             in analog mode.
+
+         (+) Configure the DAC channel using DAC_Init()
+
+         (+) Enable the DAC channel using DAC_Cmd()
+  
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_dac.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim
+ ===============================================================================
+  ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(DAC_TypeDef* DACx)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+
+  if (DACx == DAC1)
+  {
+    /* Enable DAC1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
+    /* Release DAC1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
+  }
+  else
+  {
+    /* Enable DAC2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
+    /* Release DAC2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified 
+  *         parameters in the DAC_InitStruct.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+  *         contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DACx->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DACx->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the DAC channel is enabled the trigger source can no more
+  *         be modified.
+  * @retval None
+  */
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *         triggers.
+  * @param  DACx: where x can be 1 to select the DAC1 peripheral.
+  * @note   Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_LIST1_PERIPH(DACx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DACx->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DACx: where x can be 1 to select the DAC1 peripheral.
+  * @note   Wave generation is not available in DAC2.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_LIST1_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DACx->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DACx->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DACx; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DACx: where x can be 1 to select the DAC peripheral.
+  * @note   This function is available only for DAC1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_LIST1_PERIPH(DACx));
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DACx;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DACx: where x can be 1 to select the DAC peripheral.
+  * @note   This function isn't applicable for DAC2.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *         holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *         holding register.
+  * @note In dual mode, a unique register access is required to write in both
+  *       DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_LIST1_PERIPH(DACx));
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DACx;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DACx;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                    ##### DMA management functions #####
+ =============================================================================== 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  *         When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM4, TIM6, TIM7 or TIM9  but not a software trigger) occurs
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.
+  * @param  DAC_Channel: the selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which 
+  *       must be already configured. 
+  * @retval None
+  */
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before
+  *         the acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DACx->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: thee selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note   The DMA underrun occurs when a second external trigger arrives before
+  *         the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag                          
+  * @retval None
+  */
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DACx->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.  
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before
+  *         the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DACx: where x can be 1 or 2 to select the DAC peripheral.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @retval None
+  */
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_PERIPH(DACx));
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DACx->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c
new file mode 100644
index 0000000..911745e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c
@@ -0,0 +1,858 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_dma.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):
+  *           + Initialization and Configuration
+  *           + Data Counter
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    (#) Enable The DMA controller clock using 
+        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or 
+        using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
+    (#) Enable and configure the peripheral to be connected to the DMA channel
+       (except for internal SRAM / FLASH memories: no initialization is necessary).
+    (#) For a given Channel, program the Source and Destination addresses, 
+        the transfer Direction, the Buffer Size, the Peripheral and Memory 
+        Incrementation mode and Data Size, the Circular or Normal mode, 
+        the channel transfer Priority and the Memory-to-Memory transfer 
+        mode (if needed) using the DMA_Init() function.
+    (#) Enable the NVIC and the corresponding interrupt(s) using the function 
+        DMA_ITConfig() if you need to use DMA interrupts.
+    (#) Enable the DMA channel using the DMA_Cmd() function.
+    (#) Activate the needed channel Request using PPP_DMACmd() function for 
+        any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) 
+        The function allowing this operation is provided in each PPP peripheral 
+        driver (ie. SPI_DMACmd for SPI peripheral).
+    (#) Optionally, you can configure the number of data to be transferred
+        when the channel is disabled (ie. after each Transfer Complete event
+        or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+        And you can get the number of remaining data to be transferred using 
+        the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
+        enabled and running).
+    (#) To control DMA events you can use one of the following two methods:
+        (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
+        (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+             phase and DMA_GetITStatus() function into interrupt routines in
+             communication phase.
+             After checking on a flag you should clear it using DMA_ClearFlag()
+             function. And after checking on an interrupt event you should 
+             clear it using DMA_ClearITPendingBit() function.
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_dma.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask        ((uint32_t)0x10000000) /* DMA2 FLAG mask                     */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions 
+  * @{
+  */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to initialize the DMA channel 
+         source and destination addresses, incrementation and data sizes, transfer 
+         direction, buffer size, circular/normal mode selection, memory-to-memory 
+         mode selection and channel priority value.
+    [..] The DMA_Init() function follows the DMA configuration procedures as described 
+         in reference manual (RM0313).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DMAy Channelx registers to their default reset
+  *         values.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+  /* Disable the selected DMAy Channelx */
+  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+  /* Reset DMAy Channelx control register */
+  DMAy_Channelx->CCR  = 0;
+
+  /* Reset DMAy Channelx remaining bytes register */
+  DMAy_Channelx->CNDTR = 0;
+
+  /* Reset DMAy Channelx peripheral address register */
+  DMAy_Channelx->CPAR  = 0;
+
+  /* Reset DMAy Channelx memory address register */
+  DMAy_Channelx->CMAR = 0;
+
+  if (DMAy_Channelx == DMA1_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel1 */
+    DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel2 */
+    DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel3 */
+    DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel4 */
+    DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel5)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel5 */
+    DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel6)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel6 */
+    DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA1_Channel7)
+  {
+    /* Reset interrupt pending bits for DMA1 Channel7 */
+    DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel1)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel1 */
+    DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel2)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel2 */
+    DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel3)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel3 */
+    DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
+  }
+  else if (DMAy_Channelx == DMA2_Channel4)
+  {
+    /* Reset interrupt pending bits for DMA2 Channel4 */
+    DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
+  }
+  else
+  { 
+    if (DMAy_Channelx == DMA2_Channel5)
+    {
+      /* Reset interrupt pending bits for DMA2 Channel5 */
+      DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Channelx according to the specified parameters 
+  *         in the DMA_InitStruct.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+  /* Get the DMAy_Channelx CCR value */
+  tmpreg = DMAy_Channelx->CCR;
+
+  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= CCR_CLEAR_MASK;
+
+  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+  /* Set DIR bit according to DMA_DIR value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set the MEM2MEM bit according to DMA_M2M value */
+  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+  /* Write to DMAy Channelx CCR */
+  DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+  /* Write to DMAy Channelx CPAR */
+  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+  /* Write to DMAy Channelx CMAR */
+  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  NewState: new state of the DMAy Channelx. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Channelx */
+    DMAy_Channelx->CCR |= DMA_CCR_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ *  @brief   Data Counter functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### Data Counter functions #####
+ ===============================================================================
+    [..] This subsection provides function allowing to configure and read the buffer 
+         size (number of data to be transferred).The DMA data counter can be written 
+         only when the DMA channel is disabled (ie. after transfer complete event).
+    [..] The following function can be used to write the Channel data counter value:
+         (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t 
+             DataNumber).
+    -@- It is advised to use this function rather than DMA_Init() in situations 
+        where only the Data buffer needs to be reloaded.
+    [..] The DMA data counter can be read to indicate the number of remaining transfers 
+         for the relative DMA channel. This counter is decremented at the end of each 
+         data transfer and when the transfer is complete: 
+         (+) If Normal mode is selected: the counter is set to 0.
+         (+) If Circular mode is selected: the counter is reloaded with the initial 
+         value(configured before enabling the DMA channel).
+    [..] The following function can be used to read the Channel data counter value:
+         (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DataNumber: The number of data units in the current DMAy Channelx
+  *         transfer.
+  * @note   This function can only be used when the DMAy_Channelx is disabled.
+  * @retval None
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+  /* Write to DMAy Channelx CNDTR */
+  DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current
+  *         DMAy Channelx transfer.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @retval The number of remaining data units in the current DMAy Channelx
+  *         transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  /* Return the number of remaining data units for DMAy Channelx */
+  return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides functions allowing to configure the DMA Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the DMA controller events: Polling mode or Interrupt mode. 
+  *** Polling Mode ***
+  ====================
+    [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller 
+         number  x : DMA channel number ).
+         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
+         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
+         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
+         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
+             above occurred.
+    -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
+        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+    [..]In this Mode it is advised to use the following functions:
+        (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+        (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] Each DMA channel can be managed through 4 Interrupts:
+    (+) Interrupt Source
+       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
+            event.
+       (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete 
+            event.
+       (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
+       (##) DMA_IT_GL : to indicate that at least one of the interrupts described 
+            above occurred.
+    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
+        the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
+    [..]In this Mode it is advised to use the following functions:
+        (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, 
+            FunctionalState NewState);
+        (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+        (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DMAy Channelx interrupts.
+  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
+  *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
+  *         or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask
+  *            @arg DMA_IT_HT: Half transfer interrupt mask
+  *            @arg DMA_IT_TE: Transfer error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMAy_Channelx->CCR |= DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMAy_Channelx->CCR &= ~DMA_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
+  * @param  DMAy_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  *     
+  * @note   The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags 
+  *         relative to the same channel is set (Transfer Complete, Half-transfer 
+  *         Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or 
+  *         DMAy_FLAG_TEx). 
+  *      
+  * @retval The new state of DMAy_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR ;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+  }
+
+  /* Check the status of the specified DMAy flag */
+  if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+  {
+    /* DMAy_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the DMAy_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's pending flags.
+  * @param  DMAy_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+  *            @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+  *            @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+  *            @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+  *            @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+  *            @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+  *            @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+  *            @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+  *            @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+  *            @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+  *            @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+  *            @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+  *            @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+  *            @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+  *            @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+  *            @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+  *            @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+  *            @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+  *            @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+  *            @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+  *            @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+  *            @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+  *            @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+  *            @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+  *            @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+  *            @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+  *            @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+  *            @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+  *            @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+  *            @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+  *            @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+  *            @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+  *            @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+  *            @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+  *            @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+  *            @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+  *            @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+  *            @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+  *            @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+  *            @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+  *            @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+  *            @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+  *            @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+  *            @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+  *            @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+  *            @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+  *            @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+  *            @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+  *
+  * @note   Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+  *         relative to the same channel (Transfer Complete, Half-transfer Complete and
+  *         Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+  *
+  * @retval None
+  */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+  if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy flags */
+    DMA2->IFCR = DMAy_FLAG;
+  }
+  else
+  {
+    /* Clear the selected DMAy flags */
+    DMA1->IFCR = DMAy_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
+  * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *            @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *            @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *            @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *            @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *            @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *            @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *            @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *            @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *            @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *            @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *            @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *            @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *            @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *            @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *            @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *            @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *            @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *            @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *            @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *            @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  *     
+  * @note   The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other 
+  *         interrupts relative to the same channel is set (Transfer Complete, 
+  *         Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, 
+  *         DMAy_IT_HTx or DMAy_IT_TEx). 
+  *      
+  * @retval The new state of DMAy_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+  /* Calculate the used DMA */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Get DMA2 ISR register value */
+    tmpreg = DMA2->ISR;
+  }
+  else
+  {
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR;
+  }
+
+  /* Check the status of the specified DMAy interrupt */
+  if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+  {
+    /* DMAy_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMAy_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DMAy_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Channelx's interrupt pending bits.
+  * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+  *          This parameter can be any combination (for the same DMA) of the following values:
+  *            @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+  *            @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+  *            @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+  *            @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+  *            @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+  *            @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+  *            @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+  *            @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+  *            @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+  *            @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+  *            @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+  *            @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+  *            @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+  *            @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+  *            @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+  *            @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+  *            @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+  *            @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+  *            @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+  *            @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+  *            @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+  *            @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+  *            @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+  *            @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+  *            @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+  *            @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+  *            @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+  *            @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+  *            @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+  *            @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+  *            @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+  *            @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+  *            @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+  *            @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+  *            @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+  *            @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+  *            @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+  *            @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+  *            @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+  *            @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+  *            @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+  *            @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+  *            @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+  *            @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+  *            @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+  *            @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+  *            @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+  *            @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+  *     
+  * @note   Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other 
+  *         interrupts relative to the same channel (Transfer Complete, Half-transfer 
+  *         Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and 
+  *         DMAy_IT_TEx).  
+  *        
+  * @retval None
+  */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+  /* Calculate the used DMAy */
+  if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA2->IFCR = DMAy_IT;
+  }
+  else
+  {
+    /* Clear the selected DMAy interrupt pending bits */
+    DMA1->IFCR = DMAy_IT;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c
new file mode 100644
index 0000000..7427916
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c
@@ -0,0 +1,320 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_exti.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:
+  *           + Initialization and Configuration
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+  ==============================================================================
+                            ##### EXTI features ##### 
+  ==============================================================================
+    [..] External interrupt/event lines are mapped as following:
+         (#) All available GPIO pins are connected to the 16 external 
+             interrupt/event lines from EXTI0 to EXTI15.
+         (#) EXTI line 16 is connected to the PVD output
+         (#) EXTI line 17 is connected to the RTC Alarm event
+         (#) EXTI line 18 is connected to USB Device wakeup event  
+         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
+         (#) EXTI line 20 is connected to the RTC wakeup event  
+         (#) EXTI line 21 is connected to the Comparator 1 wakeup event 
+         (#) EXTI line 22 is connected to the Comparator 2 wakeup event
+         (#) EXTI line 23 is connected to the I2C1 wakeup event
+         (#) EXTI line 24 is connected to the I2C2 wakeup event  
+         (#) EXTI line 25 is connected to the USART1 wakeup event
+         (#) EXTI line 26 is connected to the USART2 wakeup event  
+         (#) EXTI line 27 is connected to the CEC wakeup event
+         (#) EXTI line 28 is connected to the USART3 wakeup event 
+
+                       ##### How to use this driver ##### 
+  ==============================================================================
+    [..] In order to use an I/O pin as an external interrupt source, follow
+         steps below:
+    (#) Configure the I/O in input mode using GPIO_Init()
+    (#) Select the input source pin for the EXTI line using 
+        SYSCFG_EXTILineConfig().
+    (#) Select the mode(interrupt, event) and configure the trigger selection 
+       (Rising, falling or both) using EXTI_Init(). For the internal interrupt,
+       the trigger selection is not needed( the active edge is always the rising one).
+    (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
+    (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
+    [..]
+    (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_exti.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE     ((uint32_t)0x00000)        /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Initialization and Configuration functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x1F800000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x01FFFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  *          - EXTI_Line specifies the EXTI line (EXTI0....EXTI28).
+  *          - EXTI_Mode specifies which EXTI line is used as interrupt or an event.
+  *          - EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
+  *            pending bit will be set.
+  *          - EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 
+  *         contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+    /* Select the trigger for the selected interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..28).
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Interrupts and flags management functions #####
+  ==============================================================================
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x(0..28).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+   FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..28).
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be (0..28).
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+  enablestatus =  EXTI->IMR & EXTI_Line;
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..28).
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c
new file mode 100644
index 0000000..6847a6b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c
@@ -0,0 +1,528 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_gpio.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:
+  *           + Initialization and Configuration functions
+  *           + GPIO Read and Write functions
+  *           + GPIO Alternate functions configuration functions
+  *
+  *  @verbatim
+  *
+  *
+    ===========================================================================
+                         ##### How to use this driver #####
+    ===========================================================================
+      [..]
+      (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+      (#) Configure the GPIO pin(s) using GPIO_Init()
+          Four possible configuration are available for each pin:
+         (++) Input: Floating, Pull-up, Pull-down.
+         (++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
+                      Open Drain (Pull-up, Pull-down or no Pull).
+              In output mode, the speed is configurable: Low, Medium, Fast or High.
+         (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
+                                  Open Drain (Pull-up, Pull-down or no Pull).
+         (++) Analog: required mode when a pin is to be used as ADC channel,
+              DAC output or comparator input.
+      (#) Peripherals alternate function:
+         (++) For ADC, DAC and comparators, configure the desired pin in 
+              analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+         (++) For other peripherals (TIM, USART...):
+              (+++) Connect the pin to the desired peripherals' Alternate 
+                    Function (AF) using GPIO_PinAFConfig() function. For PortC, 
+                    PortD and PortF, no configuration is needed.
+              (+++) Configure the desired pin in alternate function mode using
+                    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+              (+++) Select the type, pull-up/pull-down and output speed via 
+                    GPIO_PuPd, GPIO_OType and GPIO_Speed members
+              (+++) Call GPIO_Init() function
+      (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+      (#) To set/reset the level of a pin configured in output mode use
+          GPIO_SetBits()/GPIO_ResetBits()
+      (#) During and just after reset, the alternate functions are not active and 
+          the GPIO pins are configured in input floating mode (except JTAG pins).
+      (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose 
+          (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE 
+          has priority over the GPIO function.
+      (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose 
+          (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has 
+          the priority over the GPIO function. 
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions 
+  * @{
+  */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+                    ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset 
+  *         values.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if(GPIOx == GPIOA)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+  }
+  else if(GPIOx == GPIOB)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+  }
+  else if(GPIOx == GPIOC)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+  }
+  else if(GPIOx == GPIOD)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+  }
+  else if(GPIOx == GPIOE)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+  }
+  else
+  {
+    if(GPIOx == GPIOF)
+    {
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified 
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that 
+  *         contains the configuration information for the specified GPIO
+  *         peripheral.
+  * @note   The configured pins can be:
+  *         GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOC, GPIOD and GPIOE;
+  *         GPIO_Pin_0 -> GPIO_Pin_10 and GPIO_Pin_14 -> GPIO_Pin_15 for GPIOB;
+  *         GPIO_Pin_0 -> GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9 and GPIO_Pin_10 
+  *         for GPIOF.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /*-------------------------- Configure the port pins -----------------------*/
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration */
+        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      /* Pull-up Pull down resistor configuration */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next device reset.
+  * @param  GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit */
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                      ##### GPIO Read and Write #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOC, GPIOD or GPIOE;
+  *         (0..10 & 14..15) for GPIOB;
+  *         (0..2, 4, 6, 9..10) for GPIOF.
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval The input port pin value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the port bit to read.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOC, GPIOD or GPIOE;
+  *         (0..10 & 14..15) for GPIOB;
+  *         (0..2, 4, 6, 9..10) for GPIOF.
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOC, GPIOD or GPIOE;
+  *         (0..10 & 14..15) for GPIOB;
+  *         (0..2, 4, 6, 9..10) for GPIOF.
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOC, GPIOD or GPIOE;
+  *         (0..10 & 14..15) for GPIOB;
+  *         (0..2, 4, 6, 9..10) for GPIOF.
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @note   This parameter can be GPIO_Pin_x where x can be:
+  *         (0..15) for GPIOA, GPIOC, GPIOD or GPIOE;
+  *         (0..10 & 14..15) for GPIOB;
+  *         (0..2, 4, 6, 9..10) for GPIOF.
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enumeration values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data 
+  *                  register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ *  @brief   GPIO Alternate functions configuration functions
+ *
+@verbatim   
+ ===============================================================================
+          ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *          This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AF: selects the pin to be used as Alternate function.  
+  *          This parameter can be one of the following value:
+  *            @arg GPIO_AF_0: MCO, JTMS-SWDAT, JTCK-SWCLK, JTDI,JTDO, JTRST, TRACECLK, TRACED, TRACEWO.
+  *            @arg GPIO_AF_1: TIM2, TIM15, TIM16, TIM17, OUT.
+  *            @arg GPIO_AF_2: TIM3, TIM4, TIM5, TIM13, TIM14, TIM19.
+  *            @arg GPIO_AF_3: Touch Sence.
+  *            @arg GPIO_AF_4: I2C1, I2C2.
+  *            @arg GPIO_AF_5: SPI1, SPI2, IR_OUT.
+  *            @arg GPIO_AF_6: SPI1, SPI3, CEC, IR_OUT.
+  *            @arg GPIO_AF_7: USART1, USART2, USART3, CAN, CEC.
+  *            @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT.
+  *            @arg GPIO_AF_9: CAN, TIM12, TIM13, TIM14, TIM15.
+  *            @arg GPIO_AF_10: TIM2, TIM3, TIM4, TIM12, TIM17.
+  *            @arg GPIO_AF_11: TIM19.
+  *            @arg GPIO_AF_14: USBDM, USBDP.
+  *            @arg GPIO_AF_15: OUT.
+  * @note   The pin should already been configured in Alternate Function mode(AF)
+  *         using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  * @note   Refer to the Alternate function mapping table in the device datasheet 
+  *         for the detailed mapping of the system and peripherals'alternate 
+  *         function I/O pins.
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c
new file mode 100644
index 0000000..1c2584b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c
@@ -0,0 +1,1585 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_i2c.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Inter-Integrated circuit (I2C):
+  *           + Initialization and Configuration
+  *           + Communications handling
+  *           + SMBUS management
+  *           + I2C registers management
+  *           + Data transfers management
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+ ============================================================================
+                     ##### How to use this driver #####
+ ============================================================================
+   [..]
+   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+       function for I2C1 or I2C2.
+   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+       RCC_AHBPeriphClockCmd() function. 
+   (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+            Function (AF) using GPIO_PinAFConfig() function.
+       (++) Configure the desired pin in alternate function by:
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, OpenDrain and speed via 
+            GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function.
+   (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address 
+       using the I2C_Init() function.
+   (#) Optionally you can enable/configure the following parameters without
+       re-initialization (i.e there is no need to call again I2C_Init() function):
+       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+       (++) Enable the general call using the I2C_GeneralCallCmd() function.
+       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+       (++) For SMBus Mode:
+            (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
+   (#) Enable the NVIC and the corresponding interrupt using the function
+       I2C_ITConfig() if you need to use interrupt mode.
+   (#) When using the DMA mode 
+      (++) Configure the DMA using DMA_Init() function.
+      (++) Active the needed channel Request using I2C_DMACmd() function.
+   (#) Enable the I2C using the I2C_Cmd() function.
+   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+       transfers.
+   [..]        
+   (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
+       must be enabled by setting the driving capability control bit in SYSCFG.
+       
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK          ((uint32_t)0x00CFE0FF)  /*<! I2C CR1 clear register Mask */
+#define CR2_CLEAR_MASK          ((uint32_t)0x07FF7FFF)  /*<! I2C CR2 clear register Mask */
+#define TIMING_CLEAR_MASK       ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
+#define ERROR_IT_MASK           ((uint32_t)0x00003F00)  /*<! I2C Error interrupt register Mask */
+#define TC_IT_MASK              ((uint32_t)0x000000C0)  /*<! I2C TC interrupt register Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the I2C Mode,
+         I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
+
+    [..] The I2C_Init() function follows the I2C configuration procedures (these procedures 
+         are available in reference manual).
+
+    [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
+         states machines are reset and communication control bits, as well as status bits come 
+         back to their reset value.
+
+    [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
+         HSI and Digital filters must be disabled.
+
+    [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
+         configured using I2C_OwnAddress2Config() function.
+
+    [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of 
+         each byte in slave mode when NBYTES is set to 0x01.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified
+  *         parameters in the I2C_InitStruct.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *         contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
+  assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+  /* Disable I2Cx Peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear I2Cx CR1 register */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: analog and digital filter */
+  /* Set ANFOFF bit according to I2C_AnalogFilter value */
+  /* Set DFN bits according to I2C_DigitalFilter value */
+  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+  
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+  /*---------------------------- I2Cx TIMING Configuration -------------------*/
+  /* Configure I2Cx: Timing */
+  /* Set TIMINGR bits according to I2C_Timing */
+  /* Write to I2Cx TIMING */
+  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+  /* Enable I2Cx Peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Clear tmpreg local variable */
+  tmpreg = 0;
+  /* Clear OAR1 register */
+  I2Cx->OAR1 = (uint32_t)tmpreg;
+  /* Clear OAR2 register */
+  I2Cx->OAR2 = (uint32_t)tmpreg;
+  /* Configure I2Cx: Own Address1 and acknowledged address */
+  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+  /* Set OA1 bits according to I2C_OwnAddress1 value */
+  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+                      (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+  /* Write to I2Cx OAR1 */
+  I2Cx->OAR1 = tmpreg;
+  /* Enable Own Address1 acknowledgement */
+  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+  /*---------------------------- I2Cx MODE Configuration ---------------------*/
+  /* Configure I2Cx: mode */
+  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+  tmpreg = I2C_InitStruct->I2C_Mode;
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 |= tmpreg;
+
+  /*---------------------------- I2Cx ACK Configuration ----------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear I2Cx CR2 register */
+  tmpreg &= CR2_CLEAR_MASK;
+  /* Configure I2Cx: acknowledgement */
+  /* Set NACK bit according to I2C_Ack value */
+  tmpreg |= I2C_InitStruct->I2C_Ack;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+  /*---------------- Reset I2C init structure parameters values --------------*/
+  /* Initialize the I2C_Timing member */
+  I2C_InitStruct->I2C_Timing = 0;
+  /* Initialize the I2C_AnalogFilter member */
+  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  /* Initialize the I2C_DigitalFilter member */
+  I2C_InitStruct->I2C_DigitalFilter = 0;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Disable peripheral */
+  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+  /* Perform a dummy read to delay the disable of peripheral for minimum
+     3 APB clock cycles to perform the software reset functionality */
+  *(__IO uint32_t *)(uint32_t)I2Cx; 
+
+  /* Enable peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ERRI: Error interrupt mask
+  *            @arg I2C_IT_TCI: Transfer Complete interrupt mask
+  *            @arg I2C_IT_STOPI: Stop Detection interrupt mask
+  *            @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+  *            @arg I2C_IT_ADDRI: Address Match interrupt mask  
+  *            @arg I2C_IT_RXI: RX interrupt mask
+  *            @arg I2C_IT_TXI: TX interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR1 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable clock stretching */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);    
+  }
+  else
+  {
+    /* Disable clock stretching  */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C wakeup from stop mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx stop mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable wakeup from stop mode */
+    I2Cx->CR1 |= I2C_CR1_WUPEN;   
+  }
+  else
+  {
+    /* Disable wakeup from stop mode */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C own address 2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C own address 2.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable own address 2 */
+    I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+  }
+  else
+  {
+    /* Disable own address 2 */
+    I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+  }
+}    
+
+/**
+  * @brief  Configures the I2C slave own address 2 and mask.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Mask: specifies own address 2 mask to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_OA2_NoMask: no mask.
+  *            @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+  *            @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+  *            @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+  * @retval None
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_OWN_ADDRESS2(Address));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+  
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0]  */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+            (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the I2C general call mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C general call mode.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable general call mode */
+    I2Cx->CR1 |= I2C_CR1_GCEN;
+  }
+  else
+  {
+    /* Disable general call mode */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C slave byte control.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C slave byte control.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable slave byte control */
+    I2Cx->CR1 |= I2C_CR1_SBC;
+  }
+  else
+  {
+    /* Disable slave byte control */
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+  }
+}
+
+/**
+  * @brief  Configures the slave address to be transmitted after start generation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+               
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx SADD bit [9:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+  /* Set I2Cx SADD */
+  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}
+  
+/**
+  * @brief  Enables or disables the I2C 10-bit addressing mode for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit addressing mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function should be called before generating start condition.
+  * @retval None
+  */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit addressing mode */
+    I2Cx->CR2 |= I2C_CR2_ADD10;
+  }
+  else
+  {
+    /* Disable 10-bit addressing mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+  }
+} 
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group2 Communications handling functions
+ *  @brief   Communications handling functions 
+ *
+@verbatim
+ ===============================================================================
+                  ##### Communications handling functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions that handles I2C communication.
+
+    [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
+         mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
+
+    [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
+         this configuration should be done before generating start condition in master 
+         mode.
+
+    [..] When switching from master write operation to read operation in 10Bit addressing
+         mode, master can only sends the 1st 7 bits of the 10 bit address, followed by 
+         Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
+
+    [..] In master mode, when transferring more than 255 bytes Reload mode should be used
+         to handle communication. In the first phase of transfer, Nbytes should be set to 
+         255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
+         function should be called to handle remaining communication.
+
+    [..] In master mode, when software end mode is selected when all data is transferred
+         TC flag is set I2C_TransferHandling() function should be called to generate STOP
+         or generate ReStart.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the I2C automatic end mode (stop condition is 
+  *         automatically sent when nbytes data are transferred).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C automatic end mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has effect if Reload mode is disabled.
+  * @retval None
+  */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto end mode */
+    I2Cx->CR2 |= I2C_CR2_AUTOEND;
+  }
+  else
+  {
+    /* Disable Auto end mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+  }
+} 
+
+/**
+  * @brief  Enables or disables the I2C nbytes reload mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the nbytes reload mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Auto Reload mode */
+    I2Cx->CR2 |= I2C_CR2_RELOAD;
+  }
+  else
+  {
+    /* Disable Auto Reload mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+  }
+}
+
+/**
+  * @brief  Configures the number of bytes to be transmitted/received.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  * @retval None
+  */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->CR2;
+
+  /* Reset I2Cx Nbytes bit [7:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+  /* Set I2Cx Nbytes */
+  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+  /* Store the new register value */
+  I2Cx->CR2 = tmpreg;
+}  
+  
+/**
+  * @brief  Configures the type of transfer request for the master.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Direction: specifies the transfer request direction to be programmed.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Direction_Transmitter: Master request a write transfer
+  *            @arg I2C_Direction_Receiver: Master request a read transfer 
+  * @retval None
+  */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction == I2C_Direction_Transmitter)
+  {
+    /* Request a write Transfer */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+  }
+  else
+  {
+    /* Request a read Transfer */
+    I2Cx->CR2 |= I2C_CR2_RD_WRN;
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR2 |= I2C_CR2_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+  }
+}  
+  
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR2 |= I2C_CR2_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the I2C 10-bit header only mode with read direction.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C 10-bit header only mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This mode can be used only when switching from master transmitter mode 
+  *         to master receiver mode.
+  * @retval None
+  */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable 10-bit header only mode */
+    I2Cx->CR2 |= I2C_CR2_HEAD10R;
+  }
+  else
+  {
+    /* Disable 10-bit header only mode */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+  }
+}    
+
+/**
+  * @brief  Generates I2C communication Acknowledge.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the Acknowledge.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable ACK generation */
+    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);    
+  }
+  else
+  {
+    /* Enable NACK generation */
+    I2Cx->CR2 |= I2C_CR2_NACK;
+  }
+}
+
+/**
+  * @brief  Returns the I2C slave matched address .
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the slave matched address .
+  */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+  * @brief  Returns the I2C slave received request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received request.
+  */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+  uint32_t tmpreg = 0;
+  uint16_t direction = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+  
+  /* If write transfer is requested */
+  if (tmpreg == 0)
+  {
+    /* write transfer is requested */
+    direction = I2C_Direction_Transmitter;
+  }
+  else
+  {
+    /* Read transfer is requested */
+    direction = I2C_Direction_Receiver;
+  }  
+  return direction;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address to be programmed.
+  * @param  Number_Bytes: specifies the number of bytes to be programmed.
+  *          This parameter must be a value between 0 and 255.
+  * @param  ReloadEndMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Reload_Mode: Enable Reload mode .
+  *            @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+  *            @arg I2C_SoftEnd_Mode: Enable Software end mode.
+  * @param  StartStopMode: new state of the I2C START condition generation.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_No_StartStop: Don't Generate stop and start condition.
+  *            @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+  *            @arg I2C_Generate_Start_Read: Generate Restart for read request.
+  *            @arg I2C_Generate_Start_Write: Generate Restart for write request.
+  * @retval None
+  */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SLAVE_ADDRESS(Address));  
+  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+  assert_param(IS_START_STOP_MODE(StartStopMode));
+    
+  /* Get the CR2 register value */
+  tmpreg = I2Cx->CR2;
+  
+  /* clear tmpreg specific bits */
+  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+  
+  /* update tmpreg */
+  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+            (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+  
+  /* update CR2 register */
+  I2Cx->CR2 = tmpreg;  
+}  
+
+/**
+  * @}
+  */
+
+
+/** @defgroup I2C_Group3 SMBUS management functions
+ *  @brief   SMBUS management functions 
+ *
+@verbatim
+ ===============================================================================
+                      ##### SMBUS management functions #####
+ ===============================================================================  
+    [..] This section provides a set of functions that handles SMBus communication
+         and timeouts detection.
+
+    [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusDevice.
+
+    [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
+         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
+         I2C_Mode_SMBusHost.
+
+    [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
+         function.
+
+    [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be 
+         configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() 
+         function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
+         the detection.
+
+    [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
+         function followed by the call of I2C_ClockTimeoutCmd(). When adding to this 
+         procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition 
+         (both SCL and SDA high) is detected also.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables I2C SMBus alert.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx SMBus alert.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable SMBus alert */
+    I2Cx->CR1 |= I2C_CR1_ALERTEN;   
+  }
+  else
+  {
+    /* Disable SMBus alert */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Clock Timeout (SCL Timeout detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Extended clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA 
+  *         high detection).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Idle clock Timeout.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Clock Timeout */
+    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;   
+  }
+  else
+  {
+    /* Disable Clock Timeout */    
+    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); 
+  }
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus 
+  *         idle SCL and SDA high when TIDLE = 1).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutA to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+    
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTA bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+  /* Set I2Cx TIMEOUTA */
+  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Timeout: specifies the TimeoutB to be programmed. 
+  * @retval None
+  */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_TIMEOUT(Timeout));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->TIMEOUTR;
+
+  /* Reset I2Cx TIMEOUTB bit [11:0] */
+  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+  /* Set I2Cx TIMEOUTB */
+  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+  /* Store the new register value */
+  I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables I2C PEC calculation.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_PECEN;   
+  }
+  else
+  {
+    /* Disable PEC calculation */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); 
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C PEC transmission/reception request.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC transmission/reception request */
+    I2Cx->CR1 |= I2C_CR2_PECBYTE;   
+  }
+  else
+  {
+    /* Disable PEC transmission/reception request */    
+    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); 
+  }
+}
+
+/**
+  * @brief  Returns the I2C PEC.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the PEC .
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the slave matched address in the SR1 register */
+  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+  * @}
+  */  
+
+
+/** @defgroup I2C_Group4 I2C registers management functions
+ *  @brief   I2C registers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### I2C registers management functions #####
+ ===============================================================================  
+    [..] This section provides a functions that allow user the management of 
+         I2C registers.
+
+@endverbatim
+  * @{
+  */
+
+  /**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_Register: specifies the register to read.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Register_CR1: CR1 register.
+  *            @arg I2C_Register_CR2: CR2 register.
+  *            @arg I2C_Register_OAR1: OAR1 register.
+  *            @arg I2C_Register_OAR2: OAR2 register.
+  *            @arg I2C_Register_TIMINGR: TIMING register.
+  *            @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+  *            @arg I2C_Register_ISR: ISR register.
+  *            @arg I2C_Register_ICR: ICR register.
+  *            @arg I2C_Register_PECR: PECR register.
+  *            @arg I2C_Register_RXDR: RXDR register.
+  *            @arg I2C_Register_TXDR: TXDR register.
+  * @retval The value of the read register.
+  */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t)I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *) tmp);
+}
+
+/**
+  * @}
+  */  
+  
+/** @defgroup I2C_Group5 Data transfers management functions
+ *  @brief   Data transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### Data transfers management functions #####
+ =============================================================================== 
+    [..] This subsection provides a set of functions allowing to manage 
+         the I2C data transfers.
+
+    [..] The read access of the I2C_RXDR register can be done using 
+         the I2C_ReceiveData() function and returns the received value.
+         Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
+         function and stores the written data into TXDR.
+@endverbatim
+  * @{
+  */  
+  
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Write in the DR register the data to be sent */
+  I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->RXDR;
+}  
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup I2C_Group6 DMA transfers management functions
+ *  @brief   DMA transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================  
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel 
+         requests:
+         (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+@endverbatim
+  * @{
+  */  
+    
+/**
+  * @brief  Enables or disables the I2C DMA interface.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_DMAReq_Tx: Tx DMA transfer request
+  *            @arg I2C_DMAReq_Rx: Rx DMA transfer request
+  * @param  NewState: new state of the selected I2C DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR1 |= I2C_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+  }
+}
+/**
+  * @}
+  */  
+
+
+/** @defgroup I2C_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions  #####
+ =============================================================================== 
+    [..] This section provides functions allowing to configure the I2C Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).
+
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the I2C communication can be managed by 15 flags:
+        (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
+        (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
+        (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
+        (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
+        (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
+        (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+        (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+    [..]
+        (@)Do not use the BUSY flag to handle each data transmission or reception.It is 
+           better to use the TXIS and RXNE flags instead.
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
+         and 15 pending bits: 
+    [..] Interrupt Source:
+        (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
+        (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
+        (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
+        (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
+        (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
+        (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
+        (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
+
+    [..] Pending Bits:
+        (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
+        (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
+        (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
+        (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
+        (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
+        (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
+        (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
+        (#) I2C_IT_BERR: to indicate the status of Bus error flag.
+        (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
+        (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
+        (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
+        (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+        (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+        (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+@endverbatim
+  * @{
+  */  
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_FLAG_TXE: Transmit data register empty
+  *            @arg I2C_FLAG_TXIS: Transmit interrupt status
+  *            @arg I2C_FLAG_RXNE: Receive data register not empty
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_TC: Transfer complete (master mode)
+  *            @arg I2C_FLAG_TCR: Transfer complete reload
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  *            @arg I2C_FLAG_BUSY: Bus busy
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t tmpreg = 0;
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+  
+  /* Get flag status */
+  tmpreg &= I2C_FLAG;
+  
+  if(tmpreg != 0)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  return bitstatus;
+} 
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_ADDR: Address matched (slave mode)
+  *            @arg I2C_FLAG_NACKF: NACK received flag
+  *            @arg I2C_FLAG_STOPF: STOP detection flag
+  *            @arg I2C_FLAG_BERR: Bus error
+  *            @arg I2C_FLAG_ARLO: Arbitration lost
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun
+  *            @arg I2C_FLAG_PECERR: PEC error in reception
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_FLAG_ALERT: SMBus Alert
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_FLAG;
+  }
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_TXIS: Transmit interrupt status
+  *            @arg I2C_IT_RXNE: Receive data register not empty
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_TC: Transfer complete (master mode)
+  *            @arg I2C_IT_TCR: Transfer complete reload
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t tmpreg = 0;
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  /* If Error interrupt */
+  if ((uint32_t)(I2C_IT & ERROR_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+  }
+  /* If TC interrupt */
+  else if ((uint32_t)(I2C_IT & TC_IT_MASK))
+  {
+    enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+  }
+  else
+  {
+    enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+  }
+  
+  /* Get the ISR register value */
+  tmpreg = I2Cx->ISR;
+
+  /* Get flag status */
+  tmpreg &= I2C_IT;
+
+  /* Check the status of the specified I2C flag */
+  if((tmpreg != RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the I2C_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_ADDR: Address matched (slave mode)
+  *            @arg I2C_IT_NACKF: NACK received flag
+  *            @arg I2C_IT_STOPF: STOP detection flag
+  *            @arg I2C_IT_BERR: Bus error
+  *            @arg I2C_IT_ARLO: Arbitration lost
+  *            @arg I2C_IT_OVR: Overrun/Underrun
+  *            @arg I2C_IT_PECERR: PEC error in reception
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+  *            @arg I2C_IT_ALERT: SMBus Alert
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Clear the selected flag */
+  I2Cx->ICR = I2C_IT;
+}
+
+/**
+  * @}
+  */  
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c
new file mode 100644
index 0000000..aa07736
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c
@@ -0,0 +1,295 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           + Prescaler and Counter configuration
+  *           + IWDG activation
+  *           + Flag management
+  *
+  *  @verbatim  
+  *  
+  ============================================================================== 
+                          ##### IWDG features #####
+  ============================================================================== 
+    [..] The IWDG can be started by either software or hardware (configurable
+         through option byte).
+             
+    [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+         thus stays active even if the main clock fails.
+         Once the IWDG is started, the LSI is forced ON and cannot be disabled
+         (LSI cannot be disabled too), and the counter starts counting down from 
+         the reset value of 0xFFF. When it reaches the end of count value (0x000)
+         a system reset is generated.
+         The IWDG counter should be reloaded at regular intervals to prevent
+         an MCU reset.
+                             
+    [..] The IWDG is implemented in the VDD voltage domain that is still functional
+         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+              
+    [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+         reset occurs.
+              
+    [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32F37x
+         devices provide the capability to measure the LSI frequency (LSI clock
+         should be seleted as RTC clock which is internally connected to TIM14 CH1
+         input capture). The measured value can be used to have an IWDG timeout with
+         an acceptable accuracy. 
+         For more information, please refer to the STM32F37x Reference manual.
+            
+                          ##### How to use this driver ##### 
+  ============================================================================== 
+    [..] This driver allows to use IWDG peripheral with either window option enabled
+         or disabled. To do so follow one of the two procedures below.
+    (#) Window option is enabled:    
+        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+             in software mode (no need to enable the LSI, it will be enabled
+             by hardware).        
+        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+        (++) Configure the IWDG counter value using IWDG_SetReload() function.
+             This value will be loaded in the IWDG counter each time the counter
+             is reloaded, then the IWDG will start counting down from this value.
+        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+        (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
+
+    (#) Window option is disabled:    
+        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+        (++) Configure the IWDG counter value using IWDG_SetReload() function.
+             This value will be loaded in the IWDG counter each time the counter
+             is reloaded, then the IWDG will start counting down from this value.
+        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+        (++) reload the IWDG counter at regular intervals during normal operation 
+             to prevent an MCU reset, using IWDG_ReloadCounter() function.
+        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+             in software mode (no need to enable the LSI, it will be enabled
+             by hardware).
+              
+    @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_iwdg.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+  ==============================================================================
+            ##### Prescaler and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *          This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+
+/**
+  * @brief  Sets the IWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  * @retval None
+  */
+void IWDG_SetWindowValue(uint16_t WindowValue)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
+  IWDG->WINR = WindowValue;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+ ==============================================================================
+                          ##### IWDG activation function #####
+ ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Flag management function ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
+  *            @arg IWDG_FLAG_WVU: Counter Window Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c
new file mode 100644
index 0000000..3cc59f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c
@@ -0,0 +1,589 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_pwr.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Backup Domain Access
+  *           + PVD configuration
+  *           + WakeUp pins configuration
+  *           + SDADC Analog configuration
+  *           + Low Power modes configuration
+  *           + Flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function
+ *
+@verbatim
+  ==============================================================================
+                   ##### Backup Domain Access function #####
+  ==============================================================================
+
+    [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
+         and RTC backup registers) are protected against possible stray write accesses.
+    [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the Backup domain registers.
+  * @note   If the HSE divided by 32 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the Backup domain registers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim
+  ==============================================================================
+                    ##### PVD configuration functions #####
+  ==============================================================================
+  [..]
+  (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
+      selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+  (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+      PVD threshold. This event is internally connected to the EXTI line16
+      and can generate an interrupt if enabled through the EXTI registers.
+  (+) The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *             @arg PWR_PVDLevel_0
+  *             @arg PWR_PVDLevel_1
+  *             @arg PWR_PVDLevel_2
+  *             @arg PWR_PVDLevel_3
+  *             @arg PWR_PVDLevel_4
+  *             @arg PWR_PVDLevel_5
+  *             @arg PWR_PVDLevel_6
+  *             @arg PWR_PVDLevel_7
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pins configuration functions
+ *  @brief   WakeUp pins configuration functions 
+ *
+@verbatim
+  ==============================================================================
+               ##### WakeUp pin configuration functions #####
+  ==============================================================================
+
+  (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are 
+      forced in input pull down configuration and are active on rising edges.
+  (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
+      WakeUp Pin 3 on PE.06.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
+  *          This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the EWUPx pin */
+    PWR->CSR |= PWR_WakeUpPin;
+  }
+  else
+  {
+    /* Disable the EWUPx pin */
+    PWR->CSR &= ~PWR_WakeUpPin;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group4 SDADC Analog part configuration function
+ *  @brief   SDADC Analog configuration function 
+ *
+@verbatim
+
+  ==============================================================================
+               ##### SDADC analog configuration functions #####
+  ==============================================================================
+  [..]
+  (+) The SDADC peripherals are per default in deep power down mode, in order to
+      be used their analog part should be enabled and though by calling the 
+      PWR_SDADCAnalogCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  PWR_SDADCAnalog: specifies the SDADC.
+  *          This parameter can be: PWR_SDADCAnalog_1, PWR_SDADCAnalog_2 or PWR_SDADCAnalog_3.
+  * @param  NewState: new state of the SDADC Analog functionality.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_SDADCAnalogCmd(uint32_t PWR_SDADCAnalog, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_PWR_SDADC_ANALOG(PWR_SDADCAnalog));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDADCx analog */
+    PWR->CR |= PWR_SDADCAnalog;
+  }
+  else
+  {
+    /* Disable the SDADCx analog */
+    PWR->CR &= ~PWR_SDADCAnalog;
+  }   
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup PWR_Group5 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim
+  ==============================================================================
+              ##### Low Power modes configuration functions #####
+  ==============================================================================
+
+    [..] The devices feature three low-power modes:
+    (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+    (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+    (+) Standby mode: VCORE domain powered off
+
+  *** Sleep mode *** 
+  ==================
+  [..] 
+    (+) Entry:
+        (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
+    (+) Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
+             controller (NVIC) can wake up the device from Sleep mode.
+
+  *** Stop mode *** 
+  =================
+  [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
+       the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register 
+       contents are preserved.
+       The voltage regulator can be configured either in normal or low-power mode.
+
+    (+) Entry:
+        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+             function with regulator in LowPower or with Regulator ON.
+    (+) Exit:
+        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
+             or any internal IPs (I2C, UASRT or CEC) wakeup event.
+
+  *** Standby mode *** 
+  ====================
+  [..] The Standby mode allows to achieve the lowest power consumption. It is based 
+       on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+       The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 
+       oscillator and the HSE oscillator are also switched off. SRAM and register 
+       contents are lost except for the Backup domain (RTC registers, RTC backup 
+       registers and Standby circuitry).
+   
+  [..] The voltage regulator is OFF.
+
+    (+) Entry:
+        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    (+) Exit:
+        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+  *** Auto-wakeup (AWU) from low-power mode *** 
+  =============================================
+  [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper 
+       event, a time-stamp event, or a comparator event, without depending on an 
+       external interrupt (Auto-wakeup mode).
+
+    (+) RTC auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+
+    (+) RTC auto-wakeup (AWU) from the Standby mode
+        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+
+    (+) Comparator auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
+             event, it is necessary to:
+             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 
+                   to be sensitive to to the selected edges (falling, rising or falling 
+                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+             (+++) Configure the comparator to generate the event.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+  
+  /* Clear SLEEPDEEP bit of Cortex-M4 System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *             @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *             @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *             @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, 
+  *             time-stamp, RTC Alarm out, or RTC clock calibration out.
+  *          - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex-M4 System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group6 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim
+  ==============================================================================
+                       ##### Flags management functions #####
+  ==============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                 was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), 
+  *                 RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                 resumed from StandBy mode.
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                 by the PWR_PVDCmd() function.
+  *            @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This 
+  *                 flag indicates the state of the internal voltage reference, VREFINT.
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c
new file mode 100644
index 0000000..934352d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c
@@ -0,0 +1,1655 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_rcc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Reset and clock control (RCC) peripheral:
+  *           + Internal/external clocks, PLL, CSS and MCO configuration
+  *           + System, AHB and APB busses clocks configuration
+  *           + Peripheral clocks configuration
+  *           + Interrupts and flags management
+  *
+ @verbatim
+
+ ===============================================================================
+                        ##### RCC specific features #####
+ ===============================================================================
+    [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, 
+         all peripherals are off except internal SRAM, Flash and SWD.
+         (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+             all peripherals mapped on these busses are running at HSI speed.
+         (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
+         (#) All GPIOs are in input floating state, except the SWD pins which
+             are assigned to be used for debug purpose.
+    [..] Once the device started from reset, the user application has to:
+         (#) Configure the clock source to be used to drive the System clock
+             (if the application needs higher frequency/performance)
+         (#) Configure the System clock frequency and Flash settings
+         (#) Configure the AHB and APB busses prescalers
+         (#) Enable the clock for the peripheral(s) to be used
+         (#) Configure the clock source(s) for peripherals which clocks are not
+             derived from the System clock (SDADC, CEC, I2C, USART, RTC and IWDG)
+
+ @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber          0x16
+#define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET                (RCC_OFFSET + 0x24)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* RCC Flag Mask */
+#define FLAG_MASK                 ((uint8_t)0x1F)
+
+/* CFGR register byte 3 (Bits[31:23]) base address */
+#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x40021007)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define CR_BYTE2_ADDRESS          ((uint32_t)0x40021002)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+static __I uint8_t SDADCPrescTable[16] = {2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, 48};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
+ *
+@verbatim
+ ===============================================================================
+ ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the internal/external clocks,
+         PLL, CSS and MCO.
+         (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly 
+             or through the PLL as System clock source.
+             The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
+         (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+         (#) HSE (high-speed external), 4 to 72 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+             LSE can be used also to clock the USART and CEC peripherals.
+         (#) PLL (clocked by HSI or HSE), for System clock.
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs 
+             (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled. 
+             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
+             exception vector.   
+         (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
+             PLL (divided by 2) clock on PA8 pin.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  * @note      HSI ON and used as system clock source 
+  * @note      HSE and PLL OFF
+  * @note      AHB, APB1 and APB2 prescalers set to 1.
+  * @note      CSS and MCO OFF
+  * @note      All interrupts disabled
+  * @note   However, this function doesn't modify the configuration of the
+  * @note      Peripheral clocks
+  * @note      LSI, LSE and RTC clocks
+  * @param  None
+  * @retval None
+  */
+void RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function resets the CSSON bit, so if the Clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
+  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
+
+  /* Set the new HSE configuration -------------------------------------------*/
+  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
+
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @note   This function waits on HSERDY flag to be set and return SUCCESS if 
+  *         this flag is set, otherwise returns ERROR if the timeout is reached 
+  *         and this flag is not set. The timeout value is defined by the constant
+  *         HSE_STARTUP_TIMEOUT in stm32f37x.h file. You can tailor it depending
+  *         on the HSE crystal used in your application.
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: HSE oscillator is stable and ready to use
+  *          - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+  
+  /* Wait till HSE is ready and if timeout is reached exit */
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;  
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }  
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
+  *          This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
+  
+  tmpreg = RCC->CR;
+  
+  /* Clear HSITRIM[4:0] bits */
+  tmpreg &= ~RCC_CR_HSITRIM;
+  
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+  
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   After enabling the HSI, the application software should wait on 
+  *         HSIRDY flag to be set indicating that HSI clock is stable and can
+  *         be used to clock the PLL and/or system clock.
+  * @note   HSI can not be stopped if it is used directly or through the PLL
+  *         as system clock. In this case, you have to select another source 
+  *         of the system clock then stop the HSI.
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the HSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @note   As the LSE is in the Backup domain and write access is denied to this
+  *         domain after reset, you have to enable write access using 
+  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
+  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_LSEConfig(uint32_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEON);
+
+  /* Reset LSEBYP bit */
+  RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
+
+  /* Configure LSE */
+  RCC->BDCR |= RCC_LSE;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE) drive capability.
+  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
+  * @retval None
+  */
+void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
+  
+  /* Clear LSEDRV[1:0] bits */
+  RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
+
+  /* Set the LSE Drive */
+  RCC->BDCR |= RCC_LSEDrive;
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @param  NewState: new state of the LSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the PLL clock source and multiplication factor.
+  * @note   This function must be used only when the PLL is disabled.
+  *
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
+  *            @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+  * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+  *         PLL source).
+  *
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
+  *          This parameter can be RCC_PLLMul_x where x:[2,16] 
+  *
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+  /* Clear PLL Source [16] and Multiplier [21:18] bits */
+  RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
+
+  /* Set the PLL Source and Multiplier */
+  RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
+}
+
+/**
+  * @brief  Enables or disables the PLL.
+  * @note   After enabling the PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The PLL can not be disabled if it is used as system clock source
+  * @note   The PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the PLL.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the PREDIV1 division factor.
+  * @note   This function must be used only when the PLL is disabled.
+  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+  *          This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+  * @retval None
+  */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+  tmpreg = RCC->CFGR2;
+  /* Clear PREDIV1[3:0] bits */
+  tmpreg &= ~(RCC_CFGR2_PREDIV1);
+
+  /* Set the PREDIV1 division factor */
+  tmpreg |= RCC_PREDIV1_Div;
+
+  /* Store the new value */
+  RCC->CFGR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
+  * @param  NewState: new state of the Clock Security System.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Selects the clock source to output on MCO pin (PA8).
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCOSource_NoClock: No clock selected.
+  *            @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
+  *            @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
+  *            @arg RCC_MCOSource_SYSCLK: System clock selected.
+  *            @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
+  *            @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
+  *            @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
+  * @retval None
+  */
+void RCC_MCOConfig(uint8_t RCC_MCOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
+    
+  /* Select MCO clock source and prescaler */
+  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS =  RCC_MCOSource; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
+ *  @brief   System, AHB and APB busses clocks configuration functions
+ *
+@verbatim
+ ===============================================================================
+     ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
+ ===============================================================================
+
+    [..] This section provide functions allowing to configure the System, AHB, APB1 and 
+         APB2 busses clocks.
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable prescaler
+             and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
+             APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through 
+             configurable prescalers and used to clock the peripherals mapped on these busses.
+             You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+             (+@) The FLASH program/erase clock  which is always HSI 8MHz clock.
+             (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
+             (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+             (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
+             (+@) The CEC clock which can be derived from HSI 8MHz or LSE. 
+             (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE
+                  divided by a programmable prescaler).
+                  The System clock (SYSCLK) frequency must be higher or equal to the RTC
+                  clock frequency.
+             (+@) IWDG clock which is always the LSI clock.
+       
+         (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
+             Depending on the maximum frequency, the FLASH wait states (WS) should be 
+             adapted accordingly:
+        +---------------------------------+
+        |  Wait states  |   HCLK clock    |
+        |   (Latency)   | frequency (MHz) |
+        |-------------- |-----------------|
+        |0WS(1CPU cycle)| 0 < HCLK <= 24  |
+        |---------------|-----------------| 
+        |1WS(2CPU cycle)|24 < HCLK <=48   |
+        |---------------|-----------------| 
+        |2WS(3CPU cycle)|48 < HCLK <= 72  |
+        +---------------------------------+
+
+         (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and 
+             prefetch is disabled.
+    [..] It is recommended to use the following software sequences to tune the number
+         of wait states needed to access the Flash memory with the CPU frequency (HCLK).
+         (+) Increasing the CPU frequency
+         (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" 
+              function
+         (++) Check that Flash Prefetch buffer activation is taken into account by 
+              reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
+         (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
+         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+         (++) Check that the new CPU clock source is taken into account by reading 
+              the clock source status, using "RCC_GetSYSCLKSource()" function 
+         (+) Decreasing the CPU frequency
+         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
+         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
+         (++) Check that the new CPU clock source is taken into account by reading 
+              the clock source status, using "RCC_GetSYSCLKSource()" function
+         (++) Program the new number of WS, using "FLASH_SetLatency()" function
+         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
+         (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" 
+              function
+         (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
+              using the FLASH_GetPrefetchBufferStatus() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready. 
+  *         You can use RCC_GetSYSCLKSource() function to know which clock is
+  *         currently used as system clock source.  
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source 
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
+  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear SW[1:0] bits */
+  tmpreg &= ~RCC_CFGR_SW;
+  
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can be one 
+  *         of the following values:
+  *           - 0x00: HSI used as system clock
+  *           - 0x04: HSE used as system clock  
+  *           - 0x08: PLL used as system clock
+  */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
+  *                     the system clock (SYSCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
+  *            @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
+  *            @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
+  *            @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
+  *            @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
+  *            @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
+  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear HPRE[3:0] bits */
+  tmpreg &= ~RCC_CFGR_HPRE;
+  
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+  tmpreg |= RCC_SYSCLK;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the Low Speed APB clock (PCLK1).
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HCLK_Div1: APB1 clock = HCLK
+  *            @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+  *            @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+  *            @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+  *            @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+  
+  tmpreg = RCC->CFGR;
+  /* Clear PPRE1[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE1;
+  
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+  
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the High Speed APB clock (PCLK2).
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *             @arg RCC_HCLK_Div1: APB2 clock = HCLK
+  *             @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+  *             @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+  *             @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+  *             @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+  
+  tmpreg = RCC->CFGR;
+  /* Clear PPRE2[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE2;
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK << 3;
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADC clock (ADCCLK).
+  * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
+  *         the APB2 clock (PCLK2).
+  *          This parameter can be one of the following values:
+  *             @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+  *             @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+  *             @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+  *             @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+  * @retval None
+  */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+ 
+  /* Check the parameters */
+  assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+  
+  /* Clear ADCPRE[1:0] bits */
+  RCC->CFGR &= ~RCC_CFGR_ADCPRE;
+  
+  /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+  RCC->CFGR |= RCC_PCLK2;
+}
+
+/**
+  * @brief  Configures the SDADC clock (SDADCCLK).
+  * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
+  *         the system clock (SYSCLK).
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SDADCCLK_SYSCLK_Div2: SDADC clock = SYSCLK/2
+  *             @arg RCC_SDADCCLK_SYSCLK_Div4: SDADC clock = SYSCLK/4
+  *             @arg RCC_SDADCCLK_SYSCLK_Div6: SDADC clock = SYSCLK/6
+  *             @arg RCC_SDADCCLK_SYSCLK_Div8: SDADC clock = SYSCLK/8
+  *             @arg RCC_SDADCCLK_SYSCLK_Div10: SDADC clock = SYSCLK/10
+  *             @arg RCC_SDADCCLK_SYSCLK_Div12: SDADC clock = SYSCLK/12
+  *             @arg RCC_SDADCCLK_SYSCLK_Div14: SDADC clock = SYSCLK/14
+  *             @arg RCC_SDADCCLK_SYSCLK_Div16: SDADC clock = SYSCLK/16
+  *             @arg RCC_SDADCCLK_SYSCLK_Div20: SDADC clock = SYSCLK/20
+  *             @arg RCC_SDADCCLK_SYSCLK_Div24: SDADC clock = SYSCLK/24
+  *             @arg RCC_SDADCCLK_SYSCLK_Div28: SDADC clock = SYSCLK/28
+  *             @arg RCC_SDADCCLK_SYSCLK_Div32: SDADC clock = SYSCLK/32
+  *             @arg RCC_SDADCCLK_SYSCLK_Div36: SDADC clock = SYSCLK/36
+  *             @arg RCC_SDADCCLK_SYSCLK_Div40: SDADC clock = SYSCLK/40
+  *             @arg RCC_SDADCCLK_SYSCLK_Div44: SDADC clock = SYSCLK/44
+  *             @arg RCC_SDADCCLK_SYSCLK_Div48: SDADC clock = SYSCLK/48                       
+  * @retval None
+  */
+void RCC_SDADCCLKConfig(uint32_t RCC_SDADCCLK)
+{   
+  /* Check the parameters */
+  assert_param(IS_RCC_SDADCCLK(RCC_SDADCCLK));
+  
+  /* Clear ADCPRE[1:0] bits */
+  RCC->CFGR &= ~RCC_CFGR_SDADCPRE;
+  
+  /* Set SDADCPRE[4:0] bits according to RCC_PCLK2 value */
+  RCC->CFGR |= RCC_SDADCCLK;
+}
+
+/**
+  * @brief  Configures the CEC clock (CECCLK).
+  * @param  RCC_CECCLK: defines the CEC clock source. This clock is derived 
+  *         from the HSI or LSE clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
+  *             @arg RCC_CECCLK_LSE: CEC clock = LSE
+  * @retval None
+  */
+void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
+{ 
+  /* Check the parameters */
+  assert_param(IS_RCC_CECCLK(RCC_CECCLK));
+
+  /* Clear CECSW bit */
+  RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
+  /* Set CECSW bits according to RCC_CECCLK value */
+  RCC->CFGR3 |= RCC_CECCLK;
+}
+
+/**
+  * @brief  Configures the I2C clock (I2CCLK).
+  * @param  RCC_I2CCLK: defines the I2C clock source. This clock is derived 
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
+  *             @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
+  * @note  x can be 1 or 2  
+  * @retval None
+  */
+void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
+{ 
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
+
+  tmp = (RCC_I2CCLK >> 28);
+  
+  /* Clear I2CSW bit */
+  if (tmp == 0)
+  {
+    RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
+  }
+  else
+  {
+    RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
+  }
+  /* Set I2CSW bits according to RCC_I2CCLK value */
+  RCC->CFGR3 |= RCC_I2CCLK;
+}
+
+/**
+  * @brief  Configures the USART clock (USARTCLK).
+  * @param  RCC_USARTCLK: defines the USART clock source. This clock is derived 
+  *         from the HSI or System clock.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
+  *             @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
+  *             @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
+  *             @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
+  * @note  x can be 1, 2 or 3  
+  * @retval None
+  */
+void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
+{ 
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
+
+  tmp = (RCC_USARTCLK >> 28);
+
+  /* Clear USARTSW[1:0] bit */
+  switch (tmp)
+  {
+    case 0x01:  /* clear USART1SW */
+      RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
+      break;
+    case 0x02:  /* clear USART2SW */
+      RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
+      break;
+    case 0x03:  /* clear USART3SW */
+      RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
+      break;
+  default:
+      break;
+  }
+
+  /* Set USARTSW bits according to RCC_USARTCLK value */
+  RCC->CFGR3 |= RCC_USARTCLK;
+}
+
+/**
+  * @brief  Configures the USB clock (USBCLK).
+  * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
+  *         derived from the PLL output.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
+  *                  clock source
+  *             @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+  * @retval None
+  */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+  *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+
+/**
+  * @brief  Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
+  * @note    The frequency returned by this function is not the real frequency
+  *           in the chip. It is calculated based on the predefined constant and
+  *           the source selected by RCC_SYSCLKConfig():
+  *                                              
+  * @note     If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
+  *                                              
+  * @note     If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
+  *                          
+  * @note     If SYSCLK source is PLL, function returns constant HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  * @note     (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *               8 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().   
+  *    
+  * @note     (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                return wrong result.
+  *                
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.   
+  *             
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold 
+  *         the clocks frequencies. 
+  *     
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+  *         must be called to update the structure's field. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  *    
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp]; 
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+  /* Get PCLK1 prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
+  tmp = tmp >> 8;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+  
+  /* Get PCLK2 prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
+  tmp = tmp >> 11;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+  
+  /* Get ADCCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_ADCPRE;
+  tmp = tmp >> 14;
+  presc = ADCPrescTable[tmp];
+  /* ADCCLK clock frequency */
+  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+  
+  /* Get SDADCCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_SDADCPRE;
+  tmp = (tmp >> 27) & 0x0F;
+  presc = SDADCPrescTable[tmp];
+  /* ADCCLK clock frequency */
+  RCC_Clocks->SDADCCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc;
+  
+  /* CECCLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
+  {
+    /* CEC Clock is HSI/244 */
+    RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
+  }
+  else
+  {
+    /* CECC Clock is LSE Osc. */
+    RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
+  }
+  
+  /* I2C1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
+  {
+    /* I2C1 Clock is HSI Osc. */
+    RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
+  }
+  else
+  {
+    /* I2C1 Clock is System Clock */
+    RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+
+  /* I2C2CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
+  {
+    /* I2C2 Clock is HSI Osc. */
+    RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
+  }
+  else
+  {
+    /* I2C2 Clock is System Clock */
+    RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+
+  /* USART1CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
+  {
+    /* USART Clock is PCLK */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
+  {
+    /* USART Clock is System Clock */
+    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
+  {
+    /* USART Clock is LSE Osc. */
+    RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
+  {
+    /* USART Clock is HSI Osc. */
+    RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
+  }
+
+  /* USART2CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
+  {
+    /* USART Clock is PCLK */
+    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
+  {
+    /* USART Clock is System Clock */
+    RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
+  {
+    /* USART Clock is LSE Osc. */
+    RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
+  {
+    /* USART Clock is HSI Osc. */
+    RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
+  }    
+
+  /* USART3CLK clock frequency */
+  if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
+  {
+    /* USART Clock is PCLK */
+    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
+  {
+    /* USART Clock is System Clock */
+    RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
+  {
+    /* USART Clock is LSE Osc. */
+    RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
+  }
+  else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
+  {
+    /* USART Clock is HSI Osc. */
+    RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
+  }  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ *  @brief   Peripheral clocks configuration functions 
+ *
+@verbatim
+ ===============================================================================
+             #####Peripheral clocks configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the Peripheral clocks. 
+         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 (HSE
+             divided by 32).
+         (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
+             except internal SRAM, Flash and SWD. Before to start using a peripheral you
+             have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
+             RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
+         (#) To reset the peripherals configuration (to the default state after device reset)
+             you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
+             RCC_APB1PeriphResetCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the RTC
+  *         is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
+  *             
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+  *            @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
+  *       
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  *             
+  * @note   The maximum input clock frequency for RTC is 2MHz (when using HSE as
+  *         RTC clock source).
+  *                          
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+  
+  /* Select the RTC clock source */
+  RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock source was selected
+  *         using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @param  NewState: new state of the Backup domain reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the AHB peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.    
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA: GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB: GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC: GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD: GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE: GPIOE clock
+  *             @arg RCC_AHBPeriph_GPIOF: GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:    TS clock
+  *             @arg RCC_AHBPeriph_CRC:   CRC clock
+  *             @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)  
+  *             @arg RCC_AHBPeriph_SRAM:  SRAM clock
+  *             @arg RCC_AHBPeriph_DMA2:  DMA2 clock
+  *             @arg RCC_AHBPeriph_DMA1:  DMA1 clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    RCC->AHBENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG:      SYSCFG clock
+  *             @arg RCC_APB2Periph_ADC1:        ADC1 clock
+  *             @arg RCC_APB2Periph_SPI1:        SPI1 clock
+  *             @arg RCC_APB2Periph_USART1:      USART1 clock
+  *             @arg RCC_APB2Periph_TIM15:       TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:       TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:       TIM17 clock
+  *             @arg RCC_APB2Periph_TIM19:       TIM19 clock
+  *             @arg RCC_APB2Periph_SDADC1:      SDADC1 clock
+  *             @arg RCC_APB2Periph_SDADC2:      SDADC2 clock
+  *             @arg RCC_APB2Periph_SDADC3:      SDADC3 clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:      TIM2 clock
+  *           @arg RCC_APB1Periph_TIM3:      TIM3 clock
+  *           @arg RCC_APB1Periph_TIM4:      TIM4 clock
+  *           @arg RCC_APB1Periph_TIM5:      TIM5 clock
+  *           @arg RCC_APB1Periph_TIM6:      TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:      TIM7 clock
+  *           @arg RCC_APB1Periph_TIM12:     TIM12 clock
+  *           @arg RCC_APB1Periph_TIM13:     TIM13 clock
+  *           @arg RCC_APB1Periph_TIM14:     TIM14 clock
+  *           @arg RCC_APB1Periph_TIM18:     TIM18 clock
+  *           @arg RCC_APB1Periph_WWDG:      WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:      SPI2 clock
+  *           @arg RCC_APB1Periph_SPI3:      SPI3 clock
+  *           @arg RCC_APB1Periph_USART2:    USART2 clock
+  *           @arg RCC_APB1Periph_USART3:    USART3 clock
+  *           @arg RCC_APB1Periph_I2C1:      I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:      I2C2 clock
+  *           @arg RCC_APB1Periph_USB:       USB clock
+  *           @arg RCC_APB1Periph_CAN1:      CAN1 clock
+  *           @arg RCC_APB1Periph_DAC2:      DAC2 clock
+  *           @arg RCC_APB1Periph_PWR:       PWR clock
+  *           @arg RCC_APB1Periph_DAC1:      DAC1 clock
+  *           @arg RCC_APB1Periph_CEC:       CEC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB peripheral reset.
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
+  *             @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
+  *             @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
+  *             @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
+  *             @arg RCC_AHBPeriph_GPIOE:         GPIOE clock
+  *             @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
+  *             @arg RCC_AHBPeriph_TS:            TS clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRSTR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;
+  }
+}
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_APB2Periph_SYSCFG:      SYSCFG clock
+  *             @arg RCC_APB2Periph_ADC1:        ADC1 clock
+  *             @arg RCC_APB2Periph_SPI1:        SPI1 clock
+  *             @arg RCC_APB2Periph_USART1:      USART1 clock
+  *             @arg RCC_APB2Periph_TIM15:       TIM15 clock
+  *             @arg RCC_APB2Periph_TIM16:       TIM16 clock
+  *             @arg RCC_APB2Periph_TIM17:       TIM17 clock
+  *             @arg RCC_APB2Periph_TIM19:       TIM19 clock
+  *             @arg RCC_APB2Periph_SDADC1:      SDADC1 clock
+  *             @arg RCC_APB2Periph_SDADC2:      SDADC2 clock
+  *             @arg RCC_APB2Periph_SDADC3:      SDADC3 clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *           @arg RCC_APB1Periph_TIM2:      TIM2 clock
+  *           @arg RCC_APB1Periph_TIM3:      TIM3 clock
+  *           @arg RCC_APB1Periph_TIM4:      TIM4 clock
+  *           @arg RCC_APB1Periph_TIM5:      TIM5 clock  
+  *           @arg RCC_APB1Periph_TIM6:      TIM6 clock
+  *           @arg RCC_APB1Periph_TIM7:      TIM7 clock
+  *           @arg RCC_APB1Periph_TIM12:     TIM12 clock
+  *           @arg RCC_APB1Periph_TIM13:     TIM13 clock
+  *           @arg RCC_APB1Periph_TIM14:     TIM14 clock
+  *           @arg RCC_APB1Periph_TIM18:     TIM18 clock
+  *           @arg RCC_APB1Periph_WWDG:      WWDG clock
+  *           @arg RCC_APB1Periph_SPI2:      SPI2 clock
+  *           @arg RCC_APB1Periph_SPI3:      SPI3 clock
+  *           @arg RCC_APB1Periph_USART2:    USART2 clock
+  *           @arg RCC_APB1Periph_USART3:    USART3 clock
+  *           @arg RCC_APB1Periph_I2C1:      I2C1 clock
+  *           @arg RCC_APB1Periph_I2C2:      I2C2 clock
+  *           @arg RCC_APB1Periph_USB:       USB clock
+  *           @arg RCC_APB1Periph_CAN1:      CAN1 clock
+  *           @arg RCC_APB1Periph_DAC2:      DAC2 clock
+  *           @arg RCC_APB1Periph_PWR:       PWR clock
+  *           @arg RCC_APB1Periph_DAC1:      DAC1 clock
+  *           @arg RCC_APB1Periph_CEC:       CEC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
+  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
+  *         automatically generated. The NMI will be executed indefinitely, and 
+  *         since NMI has higher priority than any other IRQ (and main program)
+  *         the application will be stacked in the NMI ISR unless the CSS interrupt
+  *         pending bit is cleared.
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  * @param  NewState: new state of the specified RCC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_IT(RCC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready  
+  *             @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *             @arg RCC_FLAG_PLLRDY: PLL clock ready
+  *             @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *             @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *             @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset 
+  *             @arg RCC_FLAG_PINRST: Pin reset
+  *             @arg RCC_FLAG_V18PWRRSTF: Voltage regulator reset
+  *             @arg RCC_FLAG_PORRST: POR/PDR reset
+  *             @arg RCC_FLAG_SFTRST: Software reset
+  *             @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *             @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *             @arg RCC_FLAG_LPWRRST: Low Power reset
+  * @retval The new state of RCC_FLAG (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+
+   if (tmp == 0)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 1)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else                       /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_MASK;
+
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, 
+  *         RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST, RCC_FLAG_V18PWRRSTF.
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RMVF bit to clear the reset flags */
+  RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of RCC_IT (SET or RESET).
+  */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_GET_IT(RCC_IT));
+  
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *             @arg RCC_IT_LSERDY: LSE ready interrupt
+  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *             @arg RCC_IT_HSERDY: HSE ready interrupt
+  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
+  *             @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+  
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c
new file mode 100644
index 0000000..bc24893
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c
@@ -0,0 +1,2597 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_rtc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A and Alarm B) configuration
+  *           + WakeUp Timer configuration
+  *           + Daylight Saving configuration
+  *           + Output pin Configuration
+  *           + Original Digital Calibration configuration  
+  *           + Digital Calibration configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + Output Type Config configuration
+  *           + Shift control synchronisation  
+  *           + Interrupts and flags management       
+  *                     
+  @verbatim
+  ===============================================================================
+                    ##### Backup Domain Operating Condition #####
+ ===============================================================================
+    [..] The real-time clock (RTC) and the RTC backup registers can be powered
+         from the VBAT voltage when the main VDD supply is powered off.
+         To retain the content of the RTC backup registers and supply the RTC 
+         when VDD is turned off, VBAT pin can be connected to an optional
+         standby voltage supplied by a battery or by another source.
+  
+    [..] To allow the RTC to operate even when the main digital supply (VDD) 
+         is turned off, the VBAT pin powers the following blocks:
+           (#) The RTC
+           (#) The LSE oscillator
+           (#) PC13 to PC15 I/Os I/Os (when available)
+  
+    [..] When the backup domain is supplied by VDD (analog switch connected 
+         to VDD), the following functions are available:
+           (#) PC14 and PC15 can be used as either GPIO or LSE pins
+           (#) PC13 can be used as a GPIO or as the RTC_AF pin
+  
+    [..] When the backup domain is supplied by VBAT (analog switch connected 
+         to VBAT because VDD is not present), the following functions are available:
+           (#) PC14 and PC15 can be used as LSE pins only
+           (#) PC13 can be used as the RTC_AF pin 
+  
+                     ##### Backup Domain Reset #####
+ ===============================================================================
+    [..] The backup domain reset sets all RTC registers and the RCC_BDCR 
+         register to their reset values. 
+         A backup domain reset is generated when one of the following events
+         occurs:
+           (#) Software reset, triggered by setting the BDRST bit in the 
+               RCC Backup domain control register (RCC_BDCR). You can use the
+               RCC_BackupResetCmd().
+           (#) VDD or VBAT power on, if both supplies have previously been
+               powered off.
+  
+                     ##### Backup Domain Access #####
+ ===============================================================================
+    [..] After reset, the backup domain (RTC registers and RTC backup data 
+         registers) is protected against possible unwanted write accesses. 
+    [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
+         (#) Enable the Power Controller (PWR) APB1 interface clock using the
+             RCC_APB1PeriphClockCmd() function.
+         (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
+         (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+         (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+                                                                                           
+  
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (+) Enable the backup domain access (see description in the section above)
+        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
+            RTC hour format using the RTC_Init() function.
+  
+ ***Time and Date configuration ***
+ ==================================
+     [..]
+        (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+            and RTC_SetDate() functions.
+        (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+            functions.
+        (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
+        (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+            hour to the RTC Calendar.
+  
+ ***Alarm configuration ***
+ ========================== 
+     [..]  
+        (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+        (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function  
+        (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+        (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+ 
+ ***RTC Wakeup configuration***
+ ========================== 
+    [..]  
+        (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+            function.
+        (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+            function  
+        (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+        (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+            function.
+  
+ ***Outputs configuration ***
+ ============================
+    [..] The RTC has 2 different outputs:
+        (+) AFO_ALARM: this output is used to manage the RTC Alarm A.
+            To output the selected RTC signal on RTC_AF pin, use the 
+            RTC_OutputConfig() function.                
+        (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
+            To output the RTC Clock on RTC_AF pin, use the RTC_CalibOutputCmd()
+            function.                
+  
+ ***Original Digital Calibration configuration ***
+ =================================    
+    [..] Configure the RTC Original Digital Calibration Value and the corresponding
+         calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
+         function.
+  
+ ***TimeStamp configuration ***
+ ==============================
+    [..]  
+        (+) Configure the RTC_AF trigger and enables the RTC TimeStamp 
+            using the RTC_TimeStampCmd() function.
+        (+) To read the RTC TimeStamp Time and Date register, use the 
+            RTC_GetTimeStamp() function.
+        (+) To read the RTC TimeStamp SubSecond register, use the 
+            RTC_GetTimeStampSubSecond() function.
+  
+ ***Tamper configuration ***
+ ===========================
+    [..]   
+        (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+            function. 
+        (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+            filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function
+        (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+            function.
+        (+) Configure the Tamper precharge or discharge duration using 
+            RTC_TamperPinsPrechargeDuration() function.
+        (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+        (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+        (+) Enable the Time stamp on Tamper detection event using  
+            RTC_TSOnTamperDetecCmd() function.     
+  
+ ***Backup Data Registers configuration ***
+ ==========================================
+    [..]  
+        (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+            function.  
+        (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+            function.  
+  
+                       ##### RTC and low power modes #####
+ ===============================================================================
+    [..] The MCU can be woken up from a low power mode by an RTC alternate 
+         function.
+    [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper 
+         event detection and RTC time stamp event detection.
+         These RTC alternate functions can wake up the system from the Stop 
+         and Standby lowpower modes.
+         The system can also wake up from low power modes without depending 
+         on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
+    [..] The RTC provides a programmable time base for waking up from the 
+         Stop or Standby mode at regular intervals.
+         Wakeup from STOP and Standby modes is possible only when the RTC 
+         clock source is LSE or LSI.
+  
+               ##### Selection of RTC_AF alternate functions #####
+ ===============================================================================
+    [..] The RTC_AF pin (PC13) can be used for the following purposes:
+         (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
+         (+) AFO_ALARM output       
+         (+) AFO_CALIB output
+         (+) AFI_TAMPER
+         (+) AFI_TIMESTAMP
+                           
+   +------------------------------------------------------------------------------------------+
+   |     Pin         |RTC ALARM |RTC CALIB |RTC TAMPER |RTC TIMESTAMP |PC13MODE|  PC13VALUE   |
+   |  configuration  | OUTPUT   | OUTPUT   |  INPUT    |    INPUT     |  bit   |     bit      |
+   |  and function   | ENABLED  | ENABLED  | ENABLED   |   ENABLED    |        |              |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output OD     |     1    |Don't care|Don't care | Don't care   | care   |      0       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output PP     |     1    |Don't care|Don't care | Don't care   | care   |      1       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | Calibration out |          |          |           |              | Don't  |              |
+   |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TAMPER input   |          |          |           |              | Don't  |              |
+   |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TIMESTAMP and  |          |          |           |              | Don't  |              |
+   |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
+   |   floating      |          |          |           |              |        |              |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | TIMESTAMP input |          |          |           |              | Don't  |              |
+   |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Output PP     |     0    |    0     |     0     |      0       |   1    | PC13 output  |
+   |    Forced       |          |          |           |              |        |              |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  Wakeup Pin or  |     0    |    0     |     0     |      0       |   0    | Don't care   |
+   |  Standard GPIO  |          |          |           |              |        |              |
+   +------------------------------------------------------------------------------------------+
+  
+ @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+                                            RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
+                                            RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00002000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00004000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to initialize and configure the RTC
+         Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+         Write protection, enter and exit the RTC initialization mode, RTC registers
+         synchronization check and reference clock detection enable.
+  
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the
+                  asynchronous prescaler to a high value to minimize consumption.
+
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+
+         (#) To Configure the RTC Calendar, user application should enter initialization
+             mode. In this mode, the calendar counter is stopped and its value can be 
+             updated. When the initialization sequence is complete, the calendar restarts 
+             counting after 4 RTCCLK cycles.
+
+         (#) To read the calendar through the shadow registers after Calendar initialization,
+             calendar update or after wakeup from low power modes the software must first 
+             clear the RSF flag. The software must then wait until it is set again before 
+             reading the calendar, which means that the calendar registers have been 
+             correctly copied into the RTC_TR and RTC_DR shadow registers.
+             The RTC_WaitForSynchro() function implements the above software sequence 
+            (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR = (uint32_t)0x00000000;
+    RTC->DR = (uint32_t)0x00002101;
+    
+    /* Reset All CR bits except CR[2:0] */
+    RTC->CR &= (uint32_t)0x00000007;
+  
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Reset all RTC CR register bits */
+      RTC->CR        &= (uint32_t)0x00000000;
+      RTC->WUTR      = (uint32_t)0x0000FFFF;
+      RTC->PRER      = (uint32_t)0x007F00FF;
+      RTC->ALRMAR    = (uint32_t)0x00000000;
+      RTC->ALRMBR    = (uint32_t)0x00000000;
+      RTC->SHIFTR    = (uint32_t)0x00000000;
+      RTC->CALR       = (uint32_t)0x00000000;
+      RTC->ALRMASSR  = (uint32_t)0x00000000;
+      RTC->ALRMBSSR  = (uint32_t)0x00000000;
+
+      /* Reset ISR register and exit initialization mode */
+      RTC->ISR = (uint32_t)0x00000000;
+      
+      /* Reset Tamper and alternate functions configuration register */
+      RTC->TAFCR = 0x00000000;
+      
+      /* Wait till the RTC RSF flag is set */
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+  
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized  
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+  
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;    
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+    
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;   
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;    
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode  
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+     
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }        
+  }
+  else
+  {
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+    
+  /* Clear RSF flag */
+  RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    
+  /* Wait the registers to be synchronised */
+  do
+  {
+    synchrostatus = RTC->ISR & RTC_ISR_RSF;
+    synchrocounter++;  
+  } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+    
+  if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return (status);
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;   
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;    
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Time and Date configuration functions #####
+ ===============================================================================
+    [..]  This section provide functions allowing to program and read the RTC
+          Calendar (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }  
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  }  
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.     
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);   
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+  
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim
+ ===============================================================================
+         ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC 
+         Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  } 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    RTC->ALRMAR = (uint32_t)tmpreg;
+  }
+  else
+  {
+    RTC->ALRMBR = (uint32_t)tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;   
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)(RTC->ALRMAR);
+  }
+  else
+  {
+    tmpreg = (uint32_t)(RTC->ALRMBR);
+  }
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  NewState: new state of the specified alarm.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *          This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
+  *                                             There is no comparison on sub seconds for Alarm.
+  *            @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
+  *                                                Only SS[0] is compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
+  *                                                Only SS[1:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
+  *                                                Only SS[2:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
+  *                                                Only SS[3:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
+  *                                                Only SS[4:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
+  *                                                Only SS[5:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
+  *                                                Only SS[6:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
+  *                                                Only SS[7:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
+  *                                                Only SS[8:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                                 Only SS[9:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                                 Only SS[10:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                                 Only SS[11:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                                 Only SS[12:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
+  *                                              Only SS[13:0] are compared
+  *            @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+  
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    /* Configure the AlarmA SubSecond register */
+    RTC->ALRMASSR = tmpreg;
+  }
+  else
+  {
+    /* Configure the Alarm B SubSecond register */
+    RTC->ALRMBSSR = tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  } 
+  
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### WakeUp Timer configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_WakeUpClock_RTCCLK_Div16
+  *            @arg RTC_WakeUpClock_RTCCLK_Div8
+  *            @arg RTC_WakeUpClock_RTCCLK_Div4
+  *            @arg RTC_WakeUpClock_RTCCLK_Div2
+  *            @arg RTC_WakeUpClock_CK_SPRE_16bits
+  *            @arg RTC_WakeUpClock_CK_SPRE_17bits
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the RTC Wakeup counter.
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
+  *          This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC WakeUp timer counter value.
+  * @param  None
+  * @retval The RTC WakeUp Counter value.
+  */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Enables or Disables the RTC WakeUp timer.
+  * @param  NewState: new state of the WakeUp timer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Daylight Saving configuration functions #####
+ ===============================================================================  
+   [..] This section provides functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *            @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                             in CR register to store the operation.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Output pin Configuration function #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Output_Disable: No output selected
+  *            @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+  *            @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
+  *            @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *          This parameter can be one of the following:
+  *            @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                          ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  *            @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                         ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ *  @brief   Digital Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Digital Calibration configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  { 
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput: Select the Calibration output Selection .
+  *          This parameter can be one of the following values:
+  *            @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *            @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *          This parameter can be can be one of the following values:
+  *            @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
+  *            @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
+  *            @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
+  *            @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *          This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### TimeStamp configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following:
+  *            @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                           edge of the related pin.
+  *            @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                            falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Tampers configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  *            @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *                            stimulates tamper event. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *            @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ 
+  /* Check if the  active level for Tamper is rising edge (Low level)*/
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Tamper_1: Select Tamper 1.
+  *            @arg RTC_Tamper_2: Select Tamper 2.
+  *            @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *            @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                           samples at the active level 
+  *            @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                           samples at the active level
+  *            @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                           samples at the active level 
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 32768
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                                         with a frequency =  RTCCLK / 16384
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 8192
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 4096
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 2048
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                                        with a frequency =  RTCCLK / 1024
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 512  
+  *            @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                                       with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+  *            @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
+  *            @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *          This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+          ##### Backup Data Registers configuration functions ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                                 specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 Output Type Config configuration functions
+ *  @brief   Output Type Config configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+            ##### Output Type Config configuration functions ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *            @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Shift control synchronisation functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
+  *          This parameter can be one of the following values :
+  *            @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. 
+  *            @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+    
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..] All RTC interrupts are connected to the EXTI controller.
+ 
+         (+) To enable the RTC Alarm interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 17 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) 
+                  using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+
+         (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 20 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to generate the RTC wakeup timer event using the 
+                  RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() 
+                  functions.
+
+         (+) To enable the RTC Tamper interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to detect the RTC tamper event using the 
+                  RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+         (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
+             (++) Configure and enable the EXTI Line 19 in interrupt mode and select 
+                  the rising edge sensitivity using the EXTI_Init() function.
+             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+                  the NVIC_Init() function.
+             (++) Configure the RTC to detect the RTC time-stamp event using the 
+                  RTC_TimeStampCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS:  Time Stamp interrupt mask
+  *            @arg RTC_IT_WUT:  WakeUp Timer interrupt mask
+  *            @arg RTC_IT_ALRB:  Alarm B interrupt mask
+  *            @arg RTC_IT_ALRA:  Alarm A interrupt mask
+  *            @arg RTC_IT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified RTC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FLAG_RECALPF: RECALPF event flag
+  *            @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag   
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_INITF: Initialization mode flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *            @arg RTC_FLAG_INITS: Registers Configured flag
+  *            @argRTC_FLAG_SHPF  : Shift operation pending flag.  
+  *            @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
+  *            @arg RTC_FLAG_ALRBWF: Alarm B Write flag
+  *            @arg RTC_FLAG_ALRAWF: Alarm A write flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
+  *            @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag 
+  *            @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));    
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt 
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt 
+  *            @arg RTC_IT_TAMP3: Tamper3 event interrupt
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *            @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  *            @arg RTC_IT_TAMP3: Tamper3 event interrupt 
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c
new file mode 100644
index 0000000..5f1fda5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c
@@ -0,0 +1,1302 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_spi.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + Hardware CRC Calculation
+  *           + DMA transfers management
+  *           + Interrupts and flags management 
+  *
+  *  @verbatim
+
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
+            function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
+            function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)
+            for SPI3.
+  
+        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using 
+            RCC_AHBPeriphClockCmd() function. 
+  
+        (#) Peripherals alternate function: 
+           (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+           (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+           (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+           (++) Call GPIO_Init() function.
+  
+        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+            function.In I2S mode, program the Mode, Standard, Data Format, MCLK 
+            Output, Audio frequency and Polarity using I2S_Init() function.
+  
+        (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select 
+            at which threshold the RXNE event is generated.
+
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            SPI_ITConfig() if you need to use interrupt mode. 
+  
+        (#) When using the DMA mode 
+           (++) Configure the DMA using DMA_Init() function.
+           (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+   
+        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+            I2S_Cmd().
+   
+        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  
+        (#) Optionally, you can enable/configure the following parameters without
+            re-initialization (i.e there is no need to call again SPI_Init() function):
+           (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+                 is programmed as Data direction parameter using the SPI_Init() 
+                 function it can be possible to switch between SPI_Direction_Tx 
+                 or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
+           (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
+                 using the SPI_Init() function it can be possible to manage the 
+                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+           (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
+           (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.  
+  
+        (#) To use the CRC Hardware calculation feature refer to the Peripheral 
+            CRC hardware Calculation subsection.
+  
+    @endverbatim 
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_spi.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK       ((uint16_t)0x3040)
+#define CR1_CLEAR_MASK2      ((uint16_t)0xFFFB)
+#define CR2_LDMA_MASK        ((uint16_t)0x9FFF)
+
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the SPI Direction,
+         SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+         Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+
+    [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
+         and Slave mode (details for these procedures are available in reference manual).
+         
+    [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
+         use the following function to manage the NSS bit:
+         void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+
+    [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
+         is selected, use the follwoing function to enable the NSS output feature.
+         void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+    [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:
+         void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+         And it can be managed by software in the SPI Motorola mode using this function: 
+         void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+    [..] This section provides also functions to initialize the I2S Mode, Standard, 
+         Data Format, MCLK Output, Audio frequency and Polarity.
+  
+    [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
+         and Slave mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+  }
+  else
+  {
+    if (SPIx == SPI3)
+    {
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* Initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* Initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+  
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+  
+  /*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+  master/slave mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI bit according to SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
+                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
+                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+  /*-------------------------Data Size Configuration -----------------------*/
+  /* Get the SPIx CR2 value */
+  tmpreg = SPIx->CR2;
+  /* Clear DS[3:0] bits */
+  tmpreg &=(uint16_t)~SPI_CR2_DS;
+  /* Configure SPIx: Data Size */
+  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
+  /* Write to SPIx CR2 */
+  SPIx->CR2 = tmpreg;
+  
+  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+  
+  /*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear MSTR bit */
+  tmpreg &= CR1_CLEAR_MASK2;
+  /* Configure SPIx: master/slave mode */  
+  /* Set MSTR bit according to SPI_Mode */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);  
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;  
+  
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note   This function calculates the optimal prescaler needed to obtain the most 
+  *         accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *         and the product configuration). But in case the prescaler value is greater 
+  *         than 511, the default value (0x02) will be configured instead.
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint32_t sourceclock = 0;
+
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
+  SPIx->I2SPR = 0x0002;
+
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);      
+
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
+
+    /* Compute the Real divider depending on the MCLK output state with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the floating point */
+    tmp = tmp / 10;
+
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+  /* Write to SPIx I2SCFGR */
+  SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= SPI_CR1_SPE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TI Mode.
+  *
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
+  *         are not taken into consideration and are configured by hardware 
+  *         respectively to the TI mode requirements.
+  *
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the selected SPI TI communication mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 |= SPI_CR2_FRF;
+  }
+  else
+  {
+    /* Disable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3  to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *         For the SPIx peripheral this parameter can be one of the following values:
+  *            @arg SPI_DataSize_4b: Set data size to 4 bits
+  *            @arg SPI_DataSize_5b: Set data size to 5 bits
+  *            @arg SPI_DataSize_6b: Set data size to 6 bits
+  *            @arg SPI_DataSize_7b: Set data size to 7 bits
+  *            @arg SPI_DataSize_8b: Set data size to 8 bits
+  *            @arg SPI_DataSize_9b: Set data size to 9 bits
+  *            @arg SPI_DataSize_10b: Set data size to 10 bits
+  *            @arg SPI_DataSize_11b: Set data size to 11 bits
+  *            @arg SPI_DataSize_12b: Set data size to 12 bits
+  *            @arg SPI_DataSize_13b: Set data size to 13 bits
+  *            @arg SPI_DataSize_14b: Set data size to 14 bits
+  *            @arg SPI_DataSize_15b: Set data size to 15 bits
+  *            @arg SPI_DataSize_16b: Set data size to 16 bits
+  * @retval None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  uint16_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
+  /* Read the CR2 register */
+  tmpreg = SPIx->CR2;
+  /* Clear DS[3:0] bits */
+  tmpreg &= (uint16_t)~SPI_CR2_DS;
+  /* Set new DS[3:0] bits value */
+  tmpreg |= SPI_DataSize;
+  SPIx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the FIFO reception threshold for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO 
+  *                                         level is greater or equal to 1/2. 
+  *            @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 
+  *                                         level is greater or equal to 1/4. 
+  * @retval None
+  */
+void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
+
+  /* Clear FRXTH bit */
+  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
+
+  /* Set new FRXTH bit value */
+  SPIx->CR2 |= SPI_RxFIFOThreshold;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3  to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Direction_Tx: Selects Tx transmission direction
+  *            @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  *            @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called and the NSS hardware management mode is selected. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= SPI_CR2_SSOE;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the NSS pulse management mode.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits NSSP is not taken into 
+  *         consideration and are configured by hardware respectively to the 
+  *         TI mode requirements. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the NSS pulse management mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the NSS pulse management mode */
+    SPIx->CR2 |= SPI_CR2_NSSP;
+  }
+  else
+  {
+    /* Disable the NSS pulse management mode */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);    
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to manage the SPI or I2S 
+         data transfers.
+
+    [..] In reception, data are received and then stored into an internal Rx buffer while 
+         In transmission, data are first stored into an internal Tx buffer before being 
+         transmitted.
+
+    [..] The read access of the SPI_DR register can be done using 
+         SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.
+         SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function
+         and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+         can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)
+         and SPI_I2S_SendData16() (when data size is superior than 8bits) function 
+         and stores the written data into Tx buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
+{
+  uint32_t spixbase = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  *(__IO uint8_t *) spixbase = Data;
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  SPIx->DR = (uint16_t)Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
+{
+  uint32_t spixbase = 0x00;
+  
+  spixbase = (uint32_t)SPIx; 
+  spixbase += 0x0C;
+  
+  return *(__IO uint8_t *) spixbase;
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPIx peripheral. 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
+{
+  return SPIx->DR;
+}
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Hardware CRC Calculation functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
+         calculation.SPI communication using CRC is possible through the following procedure:
+
+         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+             Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+             function.
+         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+         (#) Enable the SPI using the SPI_Cmd() function
+         (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
+             SPI_TransmitCRC() function to indicate that after transmission of the last 
+             data, the CRC should be transmitted.
+         (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+             bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+             value. 
+             If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+             can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+
+    -@-
+       (+@) It is advised to don't read the calculate CRC values during the communication.
+       (+@) When the SPI is in slave mode, be careful to enable CRC calculation only 
+       when the clock is stable, that is, when the clock is in the steady state. 
+       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+       to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+       the value of the SPE bit.
+       (+@) With high bitrate frequencies, be careful when transmitting the CRC.
+       As the number of used CPU cycles has to be as low as possible in the CRC 
+       transfer phase, it is forbidden to call software functions in the CRC 
+       transmission sequence to avoid errors in the last data and CRC reception. 
+       In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+       of the last data.
+       (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+       degradation of the SPI speed performance due to CPU accesses impacting the 
+       SPI bandwidth.
+       (+@) When the STM32F37x are configured as slaves and the NSS hardware mode is 
+       used, the NSS pin needs to be kept low between the data phase and the CRC 
+       phase.
+       (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+       calculation takes place even if a high level is applied on the NSS pin. 
+       This may happen for example in case of a multislave environment where the 
+       communication master addresses slaves alternately.
+       (+@) Between a slave deselection (high level on NSS) and a new slave selection 
+       (low level on NSS), the CRC value should be cleared on both master and slave
+       sides in order to resynchronize the master and slave for their respective 
+       CRC calculation.
+
+    -@- To clear the CRC, follow the procedure below:
+       (#@) Disable SPI using the SPI_Cmd() function
+       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the CRC calculation length for the selected SPI.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRCLength: specifies the SPI CRC calculation length.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
+  *            @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
+  * @retval None
+  */
+void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
+
+  /* Clear CRCL bit */
+  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
+
+  /* Set new CRCL bit value */
+  SPIx->CR1 |= SPI_CRCLength;
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called.   
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral..
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= SPI_CR1_CRCEN;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+  }
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRC_Tx: Selects Tx CRC register
+  *            @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim   
+ ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================
+    [..] This section provides two functions that can be used only in DMA mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  *            @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @brief  Configures the number of data to transfer type(Even/Odd) for the DMA
+  *         last transfers and for the selected SPI.
+  * @note   This function have a meaning only if DMA mode is selected and if 
+  *         the packing mode is used (data length <= 8 and DMA transfer size halfword)  
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
+  *                                                   and number of data for reception Even.
+  *            @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
+  *                                                  and number of data for reception Even.
+  *            @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
+  *                                                  and number of data for reception Odd.
+  *            @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
+  *                                                 and number of data for reception Odd.
+  * @retval None
+  */
+void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
+
+  /* Clear LDMA_TX and LDMA_RX bits */
+  SPIx->CR2 &= CR2_LDMA_MASK;
+
+  /* Set new LDMA_TX and LDMA_RX bits value */
+  SPIx->CR2 |= SPI_LastDMATransfer; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim   
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode. 
+
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+        (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
+        (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
+        (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+        (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
+        (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
+        (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
+        (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
+        (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+        (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+
+    [..]
+        (@)Do not use the BSY flag to handle each data transmission or reception. It is better 
+           to use the TXE and RXNE flags instead.
+
+    [..] In this Mode it is advised to use the following functions:
+        (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+        (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
+         and 5 pending bits: 
+    [..] Pending Bits:
+        (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
+        (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
+        (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
+        (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
+        (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
+
+    [..] Interrupt Source:
+        (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+            interrupt.  
+        (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+            empty interrupt.
+        (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+
+    [..] In this Mode it is advised to use the following functions:
+         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+  *** FIFO Status ***
+  ===================
+    [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
+         following function:
+         (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); 
+
+  *** DMA Mode ***
+  ================
+    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel 
+         requests:
+        (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+        (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+
+    [..] In this Mode it is advised to use the following function:
+        (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  *            @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  *            @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Returns the current SPIx Transmission FIFO filled level.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The Transmission FIFO filling state.
+  *          - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
+  *          - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *          - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
+  *          - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Transmission FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
+}
+
+/**
+  * @brief  Returns the current SPIx Reception FIFO filled level.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The Reception FIFO filling state.
+  *          - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
+  *          - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *          - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
+  *          - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
+  */
+uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
+{
+  /* Get the SPIx Reception FIFO level bits */
+  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
+}
+
+/**
+  * @brief  Checks whether the specified SPI flag is set or not.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.  
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *            @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *            @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *            @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *            @arg SPI_FLAG_MODF: Mode Fault flag.
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.
+  *            @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
+  *            @arg I2S_FLAG_UDR: Underrun Error flag.
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag.   
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *         This function clears only CRCERR flag.
+  * @note   OVR (OverRun error) flag is cleared by software sequence: a read 
+  *         operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by  
+  *         a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  * @note   MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *         operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
+  *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
+
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *            @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *            @arg SPI_IT_MODF: Mode Fault interrupt.
+  *            @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *            @arg I2S_IT_UDR: Underrun interrupt.  
+  *            @arg SPI_I2S_IT_FRE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S_IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI_I2S_IT IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c
new file mode 100644
index 0000000..87ffb75
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c
@@ -0,0 +1,378 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the SYSCFG peripheral:
+  *           + Remapping the memory mapped at 0x00000000  
+  *           + Remapping the DMA channels
+  *           + Enabling I2C fast mode plus driving capability for I2C pins   
+  *           + Configuring the EXTI lines connection to the GPIO port
+  *           + Configuring the CLASSB requirements
+  *   
+  *  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+  
+               The SYSCFG registers can be accessed only when the SYSCFG 
+               interface APB clock is enabled.
+               To enable SYSCFG APB clock use:
+               RCC_APB2PeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_syscfg.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Reset value od SYSCFG_CFGR1 register */
+#define CFGR1_CLEAR_MASK            ((uint32_t)0x7C000000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
+ *  @brief   SYSCFG Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+        ##### SYSCFG Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SYSCFG registers to their default reset values.
+  * @param  None
+  * @retval None
+  * @note   MEM_MODE bits are not affected by APB reset.
+  * @note   MEM_MODE bits took the value from the user option bytes.
+  * @note   CFGR2 register is not affected by APB reset.
+  * @note   CLASSB configuration bits are locked when set.
+  * @note   To unlock the configuration, perform a system reset.
+  */
+void SYSCFG_DeInit(void)
+{
+  /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
+  SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
+
+  /* Set FPU Interrupt Enable bits to default value */
+  SYSCFG->CFGR1 |= 0x7C000000;
+
+  /* Set EXTICRx registers to reset value */
+  SYSCFG->EXTICR[0] = 0;
+  SYSCFG->EXTICR[1] = 0;
+  SYSCFG->EXTICR[2] = 0;
+  SYSCFG->EXTICR[3] = 0;
+
+  /* Set CFGR2 register to reset value */
+  SYSCFG->CFGR2 = 0;
+}
+
+/**
+  * @brief  Configures the memory mapping at address 0x00000000.
+  * @param  SYSCFG_MemoryRemap: selects the memory remapping.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
+{
+  uint32_t tmpctrl = 0;
+
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
+
+  /* Get CFGR1 register value */
+  tmpctrl = SYSCFG->CFGR1;
+
+  /* Clear MEM_MODE bits */
+  tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
+
+  /* Set the new MEM_MODE bits value */
+  tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
+
+  /* Set CFGR1 register with the new memory remap configuration */
+  SYSCFG->CFGR1 = tmpctrl;
+}
+
+/**
+  * @brief  Configure the DMA channels remapping.
+  * @param  SYSCFG_DMARemap: selects the DMA channels remap.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA1 requests from channel1 to channel2
+  *            @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA1 requests from channel3 to channel4
+  *            @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 channel1 DMA requests from DMA2 channel 3 to DMA1 channel 3
+  *            @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC1 channel2 DMA requests from DMA2 channel 4 to DMA1 channel 4
+  *            @arg SYSCFG_DMARemap_TIM18DAC2Ch1: Remap TIM18/DAC2 channel1 DMA requests from DMA2 channel 5 to DMA1 channel 5
+  * @param  NewState: new state of the DMA channel remapping. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When enabled, DMA channel of the selected peripheral is remapped
+  * @note   When disabled, Default DMA channel is mapped to the selected peripheral
+  * @note   By default TIM17 DMA requests is mapped to channel 1, 
+  *         use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
+  *         TIM17 DMA requests to channel 2 and use
+  *         SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
+  *         TIM17 DMA requests to channel 1 (default mapping)
+  * @retval None
+  */
+void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Remap the DMA channel */
+    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
+  }
+  else
+  {
+    /* use the default DMA channel mapping */
+    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
+  }
+}
+
+/**
+  * @brief  Configure the I2C fast mode plus driving capability.
+  * @param  SYSCFG_I2CFastModePlus: selects the pin.
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
+  *            @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
+  *            @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
+  *            @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
+  *            @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
+  *            @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
+  * @param  NewState: new state of the DMA channel remapping. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   ENABLE: Enable fast mode plus driving capability for selected I2C pin
+  * @note   DISABLE: Disable fast mode plus driving capability for selected I2C pin
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter
+  *        For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using SYSCFG_I2CFastModePlus_I2C2 parameter
+  * @retval None
+  */
+void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable fast mode plus driving capability for selected I2C pin */
+    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
+  }
+  else
+  {
+    /* Disable fast mode plus driving capability for selected I2C pin */
+    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
+  }
+}
+
+/**
+  * @brief Control the VBAT monitoring
+  * @param  NewState: new state of the VBAT connection to ADC channel 18. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   ENABLE: Enable VBAT monitoring by connecting internally VBAT to ADC channel 18
+  * @note   DISABLE: Disable VBAT monitoring by disconnecting VBAT from ADC channel 18
+  * @retval None
+  */
+void SYSCFG_VBATMonitoringCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable VBAT monitoring */
+    SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
+  }
+  else
+  {
+    /* Disable VBAT monitoring */
+    SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_CFGR1_VBAT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected SYSCFG interrupts.
+  * @param  SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *           @arg SYSCFG_IT_IXC: Inexact Interrupt
+  *           @arg SYSCFG_IT_IDC: Input denormal Interrupt
+  *           @arg SYSCFG_IT_OFC: Overflow Interrupt
+  *           @arg SYSCFG_IT_UFC: Underflow Interrupt
+  *           @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
+  *           @arg SYSCFG_IT_IOC: Invalid operation Interrupt
+  * @param  NewState: new state of the specified SDADC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SYSCFG_IT(SYSCFG_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SYSCFG interrupts */
+    SYSCFG->CFGR1 |= SYSCFG_IT;
+  }
+  else
+  {
+    /* Disable the selected SYSCFG interrupts */
+    SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
+  }
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx: selects the GPIO port to be used as source 
+  *                               for EXTI lines where x can be (A, B, C, D, E or F).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *          This parameter can be EXTI_PinSourcex where x can be (0..15)
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Connect the selected parameter to the break input of TIM15/TIM16/TIM17.
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  * @param  SYSCFG_Break: selects the configuration to be connected to break
+  *         input of TIM15/TIM16/TIM17
+  *          This parameter can be any combination of the following values:
+  *            @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM15/TIM16/TIM17.
+  *            @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM15/TIM16/TIM17 .
+  *            @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM4 to the break input of TIM15/TIM16/TIM17.
+  * @retval None
+  */
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
+
+  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
+}
+
+/**
+  * @brief  Checks whether the specified SYSCFG flag is set or not.
+  * @param  SYSCFG_Flag: specifies the SYSCFG flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+  * @retval The new state of SYSCFG_Flag (SET or RESET).
+  */
+FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+  /* Check the status of the specified SPI flag */
+  if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
+  {
+    /* SYSCFG_Flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SYSCFG_Flag is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SYSCFG_Flag status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clear the selected SYSCFG flag.
+  * @param  SYSCFG_Flag: selects the flag to be cleared.
+  *          This parameter can be any combination of the following values:
+  *            @arg SYSCFG_FLAG_PE: SRAM parity error flag.
+  * @retval None
+  */
+void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
+
+  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c
new file mode 100644
index 0000000..f6b2f8a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c
@@ -0,0 +1,2003 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_usart.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):
+  *           + Initialization and Configuration
+  *           + STOP Mode
+  *           + AutoBaudRate
+  *           + Data transfers
+  *           + Multi-Processor Communication
+  *           + LIN mode
+  *           + Half-duplex mode
+  *           + Smartcard mode
+  *           + IrDA mode
+  *           + RS485 mode  
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *           
+  *  @verbatim
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
+            function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
+            function for USART2 and USART3.
+        (#) According to the USART mode, enable the GPIO clocks using 
+            RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
+            or and SCLK). 
+        (#) Peripheral's alternate function: 
+           (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+           (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+           (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+           (++) Call GPIO_Init() function.        
+        (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+            flow control and Mode(Receiver/Transmitter) using the SPI_Init()
+            function.  
+        (#) For synchronous mode, enable the clock and program the polarity,
+            phase and last bit using the USART_ClockInit() function.  
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            USART_ITConfig() if you need to use interrupt mode.   
+        (#) When using the DMA mode: 
+           (++) Configure the DMA using DMA_Init() function.
+           (++) Active the needed channel Request using USART_DMACmd() function.   
+        (#) Enable the USART using the USART_Cmd() function.   
+        (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.   
+    [..]
+            Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+            for more details.
+            
+@endverbatim
+       
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_usart.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
+#define CR1_CLEAR_MASK            ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
+                                              USART_CR1_PS | USART_CR1_TE | \
+                                              USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK      ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
+#define CR3_CLEAR_MASK            ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK                   ((uint32_t)0x000000FF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+        This subsection provides a set of functions allowing to initialize the USART 
+        in asynchronous and in synchronous modes.
+        (+) For the asynchronous mode only these parameters can be configured: 
+          (++) Baud Rate.
+          (++) Word Length.
+          (++) Stop Bit.
+          (++) Parity: If the parity is enabled, then the MSB bit of the data written
+               in the data register is transmitted but is changed by the parity bit.
+               Depending on the frame length defined by the M bit (8-bits or 9-bits),
+               the possible USART frame formats are as listed in the following table:
+
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+
+          (++) Hardware flow control.
+          (++) Receiver/transmitter modes.
+    [..] The USART_Init() function follows the USART  asynchronous configuration 
+         procedure(details for the procedure are available in reference manual.
+        (+) For the synchronous mode in addition to the asynchronous mode parameters
+            these parameters should be also configured:
+           (++) USART Clock Enabled.
+           (++) USART polarity.
+           (++) USART phase.
+           (++) USART LastBit.
+    [..] These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);    
+  }
+  else 
+  {
+    if  (USARTx == USART3)
+    {
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+    }
+  }  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t divider = 0, apbclock = 0, tmpreg = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+  
+  /* Disable USART */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+
+  /* Write to USART CR1 */
+  USARTx->CR1 = tmpreg;
+
+  /*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+  /* Write to USART CR3 */
+  USARTx->CR3 = tmpreg;
+
+  /*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  
+  if (USARTx == USART1)
+  {
+    apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
+  }
+  else if (USARTx == USART2)
+  {
+    apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
+  }
+  else 
+  {
+    apbclock = RCC_ClocksStatus.USART3CLK_Frequency;
+  }  
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* (divider * 10) computing in case Oversampling mode is 8 Samples */
+    divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* (divider * 10) computing in case Oversampling mode is 16 Samples */
+    divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
+    tmpreg  = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
+  }
+  
+  /* round the divider : if fractional part i greater than 0.5 increment divider */
+  if (tmpreg >=  (USART_InitStruct->USART_BaudRate) / 2)
+  {
+    divider++;
+  } 
+  
+  /* Implement the divider in case Oversampling mode is 8 Samples */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* get the LSB of divider and shift it to the right by 1 bit */
+    tmpreg = (divider & (uint16_t)0x000F) >> 1;
+    
+    /* update the divider value */
+    divider = (divider & (uint16_t)0xFFF0) | tmpreg;
+  }
+  
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)divider;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *         specified parameters in the USART_ClockInitStruct.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified 
+  *         USART peripheral.  
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+  /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                       USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
+  /* Write to USART CR2 */
+  USARTx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USARTx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_UE;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's transmitter or receiver.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_Direction: specifies the USART direction.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_Mode_Tx: USART Transmitter
+  *            @arg USART_Mode_Rx: USART Receiver
+  * @param  NewState: new state of the USART transfer direction.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MODE(USART_DirectionMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART's transfer interface by setting the TE and/or RE bits 
+       in the USART CR1 register */
+    USARTx->CR1 |= USART_DirectionMode;
+  }
+  else
+  {
+    /* Disable the USART's transfer interface by clearing the TE and/or RE bits
+       in the USART CR3 register */
+    USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART 8x oversampling mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Init() function
+  *         in order to have correct baudrate Divider value.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_OVER8;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_ONEBIT;
+  }
+  else
+  {
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's most significant bit first 
+  *         transmitted/received following the start bit.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART most significant bit first
+  *         transmitted/received following the start bit.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the most significant bit first transmitted/received following the 
+       start bit by setting the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_MSBFIRST;
+  }
+  else
+  {
+    /* Disable the most significant bit first transmitted/received following the 
+       start bit by clearing the MSBFIRST bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
+  }
+}
+
+/**
+  * @brief  Enables or disables the binary data inversion.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new defined levels for the USART data.
+  *          This parameter can be:
+  *            @arg ENABLE: Logical data from the data register are send/received in negative
+  *                          logic (1=L, 0=H). The parity bit is also inverted.
+  *            @arg DISABLE: Logical data from the data register are send/received in positive
+  *                          logic (1=H, 0=L) 
+  * @note   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the binary data inversion feature by setting the DATAINV bit in 
+       the CR2 register */
+    USARTx->CR2 |= USART_CR2_DATAINV;
+  }
+  else
+  {
+    /* Disable the binary data inversion feature by clearing the DATAINV bit in 
+       the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Pin(s) active level inversion.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_InvPin: specifies the USART pin(s) to invert.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_InvPin_Tx: USART Tx pin active level inversion.
+  *            @arg USART_InvPin_Rx: USART Rx pin active level inversion.
+  * @param  NewState: new active level status for the USART pin(s).
+  *          This parameter can be:
+  *            @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
+  *            @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the active level inversion for selected pins by setting the TXINV 
+       and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 |= USART_InvPin;
+  }
+  else
+  {
+    /* Disable the active level inversion for selected requests by clearing the 
+       TXINV and/or RXINV bits in the USART CR2 register */
+    USARTx->CR2 &= (uint32_t)~USART_InvPin;
+  }
+}
+
+/**
+  * @brief  Enables or disables the swap Tx/Rx pins.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USARTx TX/RX pins pinout.
+  *          This parameter can be:
+  *            @arg ENABLE: The TX and RX pins functions are swapped.
+  *            @arg DISABLE: TX/RX pins are used as defined in standard pinout
+  * @note   This function has to be called before calling USART_Cmd() function.
+  * @retval None
+  */
+void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_SWAP;
+  }
+  else
+  {
+    /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the receiver Time Out feature.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USARTx receiver Time Out.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_RTOEN;
+  }
+  else
+  {
+    /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
+  }
+}
+
+/**
+  * @brief  Sets the receiver Time Out value.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_ReceiverTimeOut: specifies the Receiver Time Out value.
+  * @retval None
+  */
+void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
+
+  /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
+  /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
+     register  */
+  USARTx->RTOR |= USART_ReceiverTimeOut;
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_Prescaler: specifies the prescaler clock. 
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= USART_GTPR_GT;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group2 STOP Mode functions
+ *  @brief   STOP Mode functions
+ *
+@verbatim
+ ===============================================================================
+                        ##### STOP Mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         WakeUp from STOP mode.
+
+    [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
+         or LSI.
+         
+    [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
+         function.
+         
+    [..] After configuring the source of WakeUp and before entering in Stop Mode 
+         USART_STOPModeCmd() function should be called to allow USART WakeUp.
+                           
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART peripheral in STOP Mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USARTx peripheral state in stop mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   This function has to be called when USART clock is set to HSI or LSE.
+  * @retval None
+  */
+void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
+       register */
+    USARTx->CR1 |= USART_CR1_UESM;
+  }
+  else
+  {
+    /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
+       register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method form stop mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_WakeUp: specifies the selected USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
+  *            @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
+  *            @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
+  * @note   This function has to be called before calling USART_Cmd() function.  
+  * @retval None
+  */
+void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
+  USARTx->CR3 |= USART_WakeUpSource;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group3 AutoBaudRate functions
+ *  @brief   AutoBaudRate functions 
+ *
+@verbatim
+ ===============================================================================
+                       ##### AutoBaudRate functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the AutoBaudRate detections.
+         
+    [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
+         The character patterns used to calculate baudrate must be chosen by calling 
+         USART_AutoBaudRateConfig() function. These function take as parameter :
+        (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
+        (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. 
+                          
+    [..] At any later time, another request for AutoBaudRate detection can be performed
+         using USART_RequestCmd() function.
+         
+    [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
+         that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
+         indicate that this procedure is completed without success. USART_GetFlagStatus () 
+         function should be used to monitor the status of these flags.  
+             
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Auto Baud Rate.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USARTx auto baud rate.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 |= USART_CR2_ABREN;
+  }
+  else
+  {
+    /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 
+       register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
+  }
+}
+
+/**
+  * @brief  Selects the USART auto baud rate method.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_AutoBaudRate: specifies the selected USART auto baud rate method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
+  *            @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
+  * @note   This function has to be called before calling USART_Cmd() function. 
+  * @retval None
+  */
+void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
+  USARTx->CR2 |= USART_AutoBaudRate;
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group4 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the USART data transfers.
+    [..] During an USART reception, data shifts in least significant bit first 
+         through the RX pin. When a transmission is taking place, a write instruction to 
+         the USART_TDR register stores the data in the shift register.
+    [..] The read access of the USART_RDR register can be done using 
+         the USART_ReceiveData() function and returns the RDR value.
+         Whereas a write access to the USART_TDR can be done using USART_SendData()
+         function and stores the written data into TDR.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->TDR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim   
+ ===============================================================================
+             ##### Multi-Processor Communication functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         multiprocessor communication.
+    [..] For instance one of the USARTs can be the master, its TX output is
+         connected to the RX input of the other USART. The others are slaves,
+         their respective TX outputs are logically ANDed together and connected 
+         to the RX input of the master. USART multiprocessor communication is 
+         possible through the following procedure:
+         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Configures the wake up methode (USART_WakeUp_IdleLine or 
+             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only 
+             for the slaves.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() 
+             function.
+    [..] The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART address */
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
+  /* Set the USART address node */
+  USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
+}
+
+/**
+  * @brief  Enables or disables the USART's mute mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART mute mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode by setting the MME bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_MME;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
+    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
+  }
+}
+
+/**
+  * @brief  Selects the USART WakeUp method from mute mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *            @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
+
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @brief  Configure the the USART Address detection length.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_AddressLength: specifies the USART address length detection.
+  *          This parameter can be one of the following values:
+  *            @arg USART_AddressLength_4b: 4-bit address length detection 
+  *            @arg USART_AddressLength_7b: 7-bit address length detection 
+  * @retval None
+  */
+void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
+  USARTx->CR2 |= USART_AddressLength;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group6 LIN mode functions
+ *  @brief   LIN mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                       ##### LIN mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         LIN Mode communication.
+    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance 
+         with the LIN standard.
+    [..] Only this LIN Feature is supported by the USART IP:
+         (+) LIN Master Synchronous Break send capability and LIN slave break 
+             detection capability :  13-bit break generation and 10/11 bit break 
+             detection.
+    [..] USART LIN Master transmitter communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Send the break character using USART_SendBreak() function.
+    [..] USART LIN Master receiver communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the break detection length 
+             using the USART_LINBreakDetectLengthConfig() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         -@- In LIN mode, the following bits must be kept cleared:
+             (+@) CLKEN in the USART_CR2 register.
+             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+         (#) Enable the USART using the USART_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *          This parameter can be one of the following values:
+  *            @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *            @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART's LIN mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART LIN mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_LINEN;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Half-duplex mode function #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Half-duplex communication.
+    [..] The USART can be configured to follow a single-wire half-duplex protocol 
+         where the TX and RX lines are internally connected.
+    [..] USART Half duplex communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+             or Mode receiver and hardware flow control values using the USART_Init()
+            function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         -@- The RX pin is no longer used.
+         -@- In Half-duplex mode the following bits must be kept cleared:
+             (+@) LINEN and CLKEN bits in the USART_CR2 register.
+             (+@) SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's Half Duplex communication.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the USART Communication.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_HDSEL;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group8 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                     ##### Smartcard mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Smartcard communication.
+    [..] The Smartcard interface is designed to support asynchronous protocol 
+         Smartcards as defined in the ISO 7816-3 standard. The USART can provide 
+         a clock to the smartcard through the SCLK output. In smartcard mode, 
+         SCLK is not associated to the communication but is simply derived from 
+         the internal peripheral input clock through a 5-bit prescaler.
+    [..] Smartcard communication is possible through the following procedure:
+         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() 
+             function.
+         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() 
+             function.
+         (#) Program the USART clock using the USART_ClockInit() function as following:
+             (++) USART Clock enabled.
+             (++) USART CPOL Low.
+             (++) USART CPHA on first edge.
+             (++) USART Last Bit Clock Enabled.
+         (#) Program the Smartcard interface using the USART_Init() function as 
+             following:
+             (++) Word Length = 9 Bits.
+             (++) 1.5 Stop Bit.
+             (++) Even parity.
+             (++) BaudRate = 12096 baud.
+             (++) Hardware flow control disabled (RTS and CTS signals).
+             (++) Tx and Rx enabled
+         (#) Optionally you can enable the parity error interrupt using 
+             the USART_ITConfig() function.
+         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
+         (#) Enable the USART using the USART_Cmd() function.
+    [..] 
+  Please refer to the ISO 7816-3 specification for more details.
+    [..] 
+         (@) It is also possible to choose 0.5 stop bit for receiving but it is 
+             recommended to use 1.5 stop bits for both transmitting and receiving 
+             to avoid switching between the two configurations.
+         (@) In smartcard mode, the following bits must be kept cleared:
+             (+@) LINEN bit in the USART_CR2 register.
+             (+@) HDSEL and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= USART_GTPR_PSC;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Enables or disables the USART's Smart Card mode.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the NACK transmission.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
+  }
+}
+
+/**
+  * @brief  Sets the Smart Card number of retries in transmit and receive.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_AutoCount: specifies the Smart Card auto retry count.
+  * @retval None
+  */
+void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
+  /* Clear the USART auto retry count */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
+  /* Set the USART auto retry count*/
+  USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
+}
+
+/**
+  * @brief  Sets the Smart Card Block length.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_BlockLength: specifies the Smart Card block length.
+  * @retval None
+  */
+void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  /* Clear the Smart card block length */
+  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
+  /* Set the Smart Card block length */
+  USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group9 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                        ##### IrDA mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         IrDA communication.
+    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, 
+         any data on the IrDA receive line will be ignored by the IrDA decoder 
+         and if the Receiver is busy, data on the TX from the USART to IrDA will 
+         not be encoded by IrDA. While receiving data, transmission should be 
+         avoided as the data to be transmitted could be corrupted.
+    [..] IrDA communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Configures the IrDA pulse width by configuring the prescaler using  
+             the USART_SetPrescaler() function.
+         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal 
+             mode using the USART_IrDAConfig() function.
+         (#) Enable the IrDA using the USART_IrDACmd() function.
+         (#) Enable the USART using the USART_Cmd() function.         
+    [..]
+    (@) A pulse of width less than two and greater than one PSC period(s) may or 
+        may not be rejected.
+    (@) The receiver set up time should be managed by software. The IrDA physical 
+        layer specification specifies a minimum of 10 ms delay between 
+        transmission and reception (IrDA is a half duplex protocol).
+    (@) In IrDA mode, the following bits must be kept cleared:
+        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        (+@) SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IrDAMode_LowPower
+  *            @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the IrDA mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group10 RS485 mode function
+ *  @brief  RS485 mode function 
+ *
+@verbatim  
+ ===============================================================================
+                        ##### RS485 mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         RS485 flow control.
+    [..] RS485 flow control (Driver enable feature) handling is possible through
+         the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Enable the Driver Enable using the USART_DECmd() function.
+         (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
+             function.
+         (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() 
+             function and deassertion time using the USART_SetDEDeassertionTime()
+             function.    
+         (#) Enable the USART using the USART_Cmd() function.
+      -@-  
+       (+@) The assertion and dessertion times are expressed in sample time units (1/8 or 
+            1/16 bit time, depending on the oversampling rate).
+       
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DE functionality.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  NewState: new state of the driver enable mode.
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the DE functionality by setting the DEM bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_DEM;
+  }
+  else
+  {
+    /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
+    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
+  }
+}
+
+/**
+  * @brief  Configures the USART's DE polarity
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_DEPolarity: specifies the DE polarity.
+  *          This parameter can be one of the following values:
+  *            @arg USART_DEPolarity_Low
+  *            @arg USART_DEPolarity_High
+  * @retval None
+  */
+void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
+
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
+  USARTx->CR3 |= USART_DEPolarity;
+}
+
+/**
+  * @brief  Sets the specified RS485 DE assertion time
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_DEAssertionTime: specifies the time between the activation of
+  *         the DE signal and the beginning of the start bit
+  * @retval None
+  */
+void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); 
+
+  /* Clear the DE assertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
+  /* Set the new value for the DE assertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
+}
+
+/**
+  * @brief  Sets the specified RS485 DE deassertion time
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_DeassertionTime: specifies the time between the middle of the last 
+  *         stop bit in a transmitted message and the de-activation of the DE signal
+  * @retval None
+  */
+void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); 
+
+  /* Clear the DE deassertion time */
+  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
+  /* Set the new value for the DE deassertion time */
+  USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group11 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+    [..] This section provides two functions that can be used only in DMA mode.
+    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel 
+         requests:
+         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, 
+             FunctionalState NewState).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_DMAReq_Tx: USART DMA transmit request
+  *            @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint32_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's DMA interface when reception error occurs.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_DMAOnError: specifies the DMA status in case of reception error.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA  
+  *                                          reception error is asserted.
+  *            @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA 
+  *                                           reception error is asserted.
+  * @retval None
+  */
+void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); 
+  
+  /* Clear the DMA Reception error detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
+  /* Set the new value for the DMA Reception error detection bit */
+  USARTx->CR3 |= USART_DMAOnError;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group12 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to configure the 
+         USART Interrupts sources, Requests and check or clear the flags or pending bits status. 
+         The user should identify which mode will be used in his application to 
+         manage the communication: Polling mode, Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+    [..] In Polling Mode, the SPI communication can be managed by these flags:
+         (#) USART_FLAG_REACK: to indicate the status of the Receive Enable 
+             acknowledge flag
+         (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable 
+             acknowledge flag.
+         (#) USART_FLAG_WU: to indicate the status of the Wake up flag.
+         (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
+         (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
+         (#) USART_FLAG_CM: to indicate the status of the Character match flag.
+         (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
+         (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
+         (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
+         (#) USART_FLAG_EOB: to indicate the status of the End of block flag.
+         (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag.
+         (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input 
+             bit status.
+         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
+         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
+         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
+         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
+         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
+         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
+         (#) USART_FLAG_NE: to indicate if a noise error occur.
+         (#) USART_FLAG_FE: to indicate if a frame error occur.
+         (#) USART_FLAG_PE: to indicate if a parity error occur.
+         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+
+ *** Interrupt Mode ***
+ ======================
+    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt 
+         sources and 10 pending bits:
+         (+) Pending Bits:
+             (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
+             (##) USART_IT_CM: to indicate the status of Character match interrupt.
+             (##) USART_IT_EOB: to indicate the status of End of block interrupt.
+             (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
+             (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
+             (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
+             (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
+             (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
+             (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
+             (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
+             (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
+             (##) USART_IT_PE: to indicate the status of Parity Error interrupt.  
+
+         (+) Interrupt Source:
+             (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
+             (##) USART_IT_CM: specifies the interrupt source for Character match 
+                  interrupt.
+             (##) USART_IT_EOB: specifies the interrupt source for End of block
+                  interrupt.
+             (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
+                  interrupt.
+             (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
+             (##) USART_IT_LBD: specifies the interrupt source for LIN Break 
+                  detection interrupt.
+             (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data 
+                  Register empty interrupt.
+             (##) USART_IT_TC: specifies the interrupt source for Transmission 
+                  complete interrupt.
+             (##) USART_IT_RXNE: specifies the interrupt source for Receive Data 
+                  register not empty interrupt.
+             (##) USART_IT_IDLE: specifies the interrupt source for Idle line 
+                  detection interrupt.
+             (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
+             (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
+                  (Frame error, noise error, overrun error)
+             -@@- Some parameters are coded in order to use them as interrupt 
+                 source or as pending bits.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
+         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
+         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *            @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *            @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0, itpos = 0, itmask = 0;
+  uint32_t usartxbase = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_MASK;
+  itmask = (((uint32_t)0x01) << itpos);
+
+  if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x04;
+  }
+  else if (usartreg == 0x03) /* The IT is in CR3 register */
+  {
+    usartxbase += 0x08;
+  }
+  else /* The IT is in CR1 register */
+  {
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Enables the specified USART's Request.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_Request: specifies the USART request.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_Request_TXFRQ: Transmit data flush ReQuest
+  *            @arg USART_Request_RXFRQ: Receive data flush ReQuest
+  *            @arg USART_Request_MMRQ: Mute Mode ReQuest
+  *            @arg USART_Request_SBKRQ: Send Break ReQuest
+  *            @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
+  * @param  NewState: new state of the DMA interface when reception error occurs.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_REQUEST(USART_Request));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
+       register.*/
+    USARTx->RQR |= USART_Request;
+  }
+  else
+  {
+    /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
+       register.*/
+    USARTx->RQR &= (uint32_t)~USART_Request;
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART's Overrun detection.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_OVRDetection: specifies the OVR detection status in case of OVR error.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_OVRDetection_Enable: OVR error detection enabled when
+  *                                            the USART OVR error is asserted.
+  *            @arg USART_OVRDetection_Disable: OVR error detection disabled when
+  *                                             the USART OVR error is asserted.
+  * @retval None
+  */
+void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
+  
+  /* Clear the OVR detection bit */
+  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
+  /* Set the new value for the OVR detection bit */
+  USARTx->CR3 |= USART_OVRDetection;
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_FLAG_REACK:  Receive Enable acknowledge flag.
+  *            @arg USART_FLAG_TEACK:  Transmit Enable acknowledge flag.
+  *            @arg USART_FLAG_WU:  Wake up flag.
+  *            @arg USART_FLAG_RWU:  Receive Wake up flag.
+  *            @arg USART_FLAG_SBK:  Send Break flag.
+  *            @arg USART_FLAG_CM:  Character match flag.
+  *            @arg USART_FLAG_BUSY:  Busy flag.
+  *            @arg USART_FLAG_ABRF:  Auto baud rate flag.
+  *            @arg USART_FLAG_ABRE:  Auto baud rate error flag.
+  *            @arg USART_FLAG_EOB:  End of block flag.
+  *            @arg USART_FLAG_RTO:  Receive time out flag.
+  *            @arg USART_FLAG_nCTSS:  Inverted nCTS input bit status.
+  *            @arg USART_FLAG_CTS:  CTS Change flag.
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg USART_FLAG_TXE:  Transmit data register empty flag.
+  *            @arg USART_FLAG_TC:  Transmission Complete flag.
+  *            @arg USART_FLAG_RXNE:  Receive data register not empty flag.
+  *            @arg USART_FLAG_IDLE:  Idle Line detection flag.
+  *            @arg USART_FLAG_ORE:  OverRun Error flag.
+  *            @arg USART_FLAG_NE:  Noise Error flag.
+  *            @arg USART_FLAG_FE:  Framing Error flag.
+  *            @arg USART_FLAG_PE:  Parity Error flag.
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+  
+  if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_FLAG_WU:  Wake up flag.
+  *            @arg USART_FLAG_CM:  Character match flag.
+  *            @arg USART_FLAG_EOB:  End of block flag.
+  *            @arg USART_FLAG_RTO:  Receive time out flag.
+  *            @arg USART_FLAG_CTS:  CTS Change flag.
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg USART_FLAG_TC:  Transmission Complete flag.
+  *            @arg USART_FLAG_IDLE:  IDLE line detected flag.
+  *            @arg USART_FLAG_ORE:  OverRun Error flag.
+  *            @arg USART_FLAG_NE: Noise Error flag.
+  *            @arg USART_FLAG_FE: Framing Error flag.
+  *            @arg USART_FLAG_PE:   Parity Errorflag.
+  *   
+  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
+  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
+  *           USART_RQR (USART_RequestCmd()).
+  * @note     TC flag can be also cleared by software sequence: a read operation
+  *           to USART_SR register (USART_GetFlagStatus()) followed by a write 
+  *           operation to USART_TDR register (USART_SendData()).
+  * @note     TXE flag is cleared by a write to the USART_TDR register (USART_SendData())
+  *           or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()).
+  * @note     SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
+  *           (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+     
+  USARTx->ICR = USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *            @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
+  *            @arg USART_IT_IDLE:  Idle line detection interrupt.
+  *            @arg USART_IT_ORE:  OverRun Error interrupt.
+  *            @arg USART_IT_NE:  Noise Error interrupt.
+  *            @arg USART_IT_FE:  Framing Error interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0, usartreg = 0;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+  
+  /* Get the USART register index */
+  usartreg = (((uint16_t)USART_IT) >> 0x08);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_MASK;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x10;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->ISR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: where x can be 1 or 2 or 3 to select the USART peripheral.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_WU:  Wake up interrupt.
+  *            @arg USART_IT_CM:  Character match interrupt.
+  *            @arg USART_IT_EOB:  End of block interrupt.
+  *            @arg USART_IT_RTO:  Receive time out interrupt.
+  *            @arg USART_IT_CTS:  CTS change interrupt.
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *            @arg USART_IT_TC:  Transmission complete interrupt.
+  *            @arg USART_IT_IDLE:  IDLE line detected interrupt.
+  *            @arg USART_IT_ORE:  OverRun Error interrupt.
+  *            @arg USART_IT_NE:  Noise Error interrupt.
+  *            @arg USART_IT_FE:  Framing Error interrupt.
+  *            @arg USART_IT_PE:  Parity Error interrupt.
+  *
+  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
+  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register 
+  *           USART_RQR (USART_RequestCmd()).
+  * @note     TC pending bit can be also cleared by software sequence: a read 
+  *           operation to USART_SR register (USART_GetITStatus()) followed by  
+  *           a write operation to USART_TDR register (USART_SendData()).
+  * @note     TXE pending bit is cleared by a write to the USART_TDR register 
+  *           (USART_SendData()) or by writing 1 to the TXFRQ in the register 
+  *           USART_RQR (USART_RequestCmd()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
+{
+  uint32_t bitpos = 0, itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+  
+  bitpos = USART_IT >> 0x10;
+  itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
+  USARTx->ICR = (uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c
new file mode 100644
index 0000000..76fc17d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:
+  *           + Prescaler, Refresh window and Counter configuration
+  *           + WWDG activation
+  *           + Interrupts and flags management
+  *             
+  *  @verbatim
+  *    
+  ============================================================================== 
+                           ##### WWDG features ##### 
+  ============================================================================== 
+    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
+        time period, unless the program refreshes the counter (downcounter) 
+        before to reach 0x3F value (i.e. a reset is generated when the counter
+        value rolls over from 0x40 to 0x3F). 
+    [..] An MCU reset is also generated if the counter value is refreshed
+         before the counter has reached the refresh window value. This 
+         implies that the counter must be refreshed in a limited window.
+
+    [..] Once enabled the WWDG cannot be disabled except by a system reset.
+
+    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+         reset occurs.
+
+    [..] The WWDG counter input clock is derived from the APB clock divided 
+         by a programmable prescaler.
+
+    [..] WWDG counter clock = PCLK1 / Prescaler.
+    [..] WWDG timeout = (WWDG counter clock) * (counter value).
+
+    [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
+
+                       ##### How to use this driver ##### 
+  ==============================================================================
+    [..]
+        (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 
+            function.
+              
+        (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
+                             
+        (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
+              
+        (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+            When the WWDG is enabled the counter value should be configured to 
+            a value greater than 0x40 to prevent generating an immediate reset.
+              
+        (#) Optionally you can enable the Early wakeup interrupt which is 
+            generated when the counter reach 0x40.
+            Once enabled this interrupt cannot be disabled except by a system reset.
+                   
+        (#) Then the application program must refresh the WWDG counter at regular
+            intervals during normal operation to prevent an MCU reset, using
+            WWDG_SetCounter() function. This operation must occur only when
+            the counter value is lower than the refresh window value, 
+            programmed using WWDG_SetWindowValue().
+  
+  *  @endverbatim  
+  *                             
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_rcc.h"
+
+/** @addtogroup STM32F37x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
+#define BIT_MASK          ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+    ##### Prescaler, Refresh window and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *            @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *            @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *            @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *          This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_MASK;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset. 
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *          This parameter must be a number between 0x40 and 0x7F (to prevent 
+  *          generating an immediate reset).
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_MASK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ *  @brief   WWDG activation functions 
+ *
+@verbatim   
+  ==============================================================================
+                     ##### WWDG activation function #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *          This parameter must be a number between 0x40 and 0x7F (to prevent 
+  *          generating an immediate reset).
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Interrupts and flags management functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/Release_Notes.html
new file mode 100644
index 0000000..640ffcd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/Release_Notes.html
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+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32L1xx Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>
+<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+<tbody>
+<tr style="">
+<td style="padding: 0cm;" valign="top">
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+<ol style="margin-top: 0cm;" start="1" type="1">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
+</ol>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx Standard Peripherals Library Drivers update history<o:p></o:p></span></h2>
+
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 05-March-2012<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 24-January-2012<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version for <span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span> devices.</span><br>
+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new drivers for new peripherals on </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li>
+              <ul style="font-weight: bold; font-style: italic;">
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_aes.h/.c </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_fsmc.h/.c </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_opamp.h/.c </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_sdio.h/.c </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_adc.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new channel for ADC Bank B</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function to select between Bank A and Bank B: void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_BankSelection);</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update ADC_InjectedChannelConfig() and ADC_RegularChannelConfig() to support new ADC channels.<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_comp.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void COMP_SW1SwitchConfig(FunctionalState NewState);<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dbgmcu.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter for TIM5<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dma.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add DMA2 support<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_exti.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new EXTI Line 23 connected to TS channel acquisition event<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new pages definitions for Write protection</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flag FLASH_FLAG_OPTVERRUSR</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+new functions: FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(),
+FLASH_OB_BootConfig(), FLASH_OB_GetWRP1(), FLASH_OB_GetWRP2(),
+FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update
+functions to avoid STM32L1XX_MD workaround on Data EEPROM (FAST)
+halfword/byte erase: DATA_EEPROM_FastProgramByte(),
+DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte() and
+DATA_EEPROM_ProgramHalfWord().</span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash_ramfunc.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update
+FLASH_ProgramHalfPage(), FLASH_ProgramParallelHalfPage(),
+DATA_EEPROM_EraseDoubleWord() and DATA_EEPROM_ProgramDoubleWord()
+functions.</span></li>
+
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_gpio.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new GPIO port definition.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new alternate functions for new peripherals.<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_i2c.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rcc.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupt for RCC_IT_LSECSS</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for new peripherals</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: RCC_LSEClockSecuritySystemCmd()<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rtc.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SYNCH_PREDIV max value changed to 0x7FFF</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for RTC Alarm Sub Second "RTC_Alarm_Sub_Seconds_Masks" and Alarm Sub Second max value (0x7FFF)</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+new definitions for: RTC_Calib_Output_selection,
+RTC_Smooth_calib_period, RTC_Smooth_calib_Plus_pulses,
+RTC_Smooth_calib_Minus_pulses.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions: RTC_TamperTrigger_LowLevel and RTC_TamperTrigger_HighLevel.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+new definitions for RTC_Tamper_Filter, RTC_Tamper_Sampling_Frequencies,
+RTC_Tamper_Pin_Precharge_Duration, RTC_Tamper_2 and RTC_Tamper_3.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new&nbsp; RTC_Add_1_Second_Parameter and RTC_Substract_Fraction_Of_Second_Value defintions.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new Backup registers definitions from RTC_BKP_DR20 to RTC_BKP_DR31.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: RTC_FLAG_RECALPF, RTC_FLAG_TAMP3F and RTC_FLAG_TAMP2F</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupts definitions RTC_IT_TAMP2 and RTC_IT_TAMP3</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: <span style="font-style: italic;">RTC_BypassShadowCmd(),
+RTC_GetSubSecond(), RTC_AlarmSubSecondConfig(),
+RTC_GetAlarmSubSecond(), RTC_CalibOutputConfig(),
+RTC_SmoothCalibConfig(), RTC_GetTimeStampSubSecond(),
+RTC_TamperFilterConfig(), RTC_TamperSamplingFreqConfig(),
+RTC_TamperPinsPrechargeDuration(), RTC_TimeStampOnTamperDetectionCmd(),
+RTC_TamperPullUpCmd(), RTC_SynchroShiftConfig().</span><br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_spi.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for I2S</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new structure "I2S_InitTypeDef"</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter: I2S_Mode, I2S_Standard, I2S_Data_Format, I2S_MCLK_Output, I2S_Audio_Frequency and I2S_Clock_Polarity.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 2 interrupts: I2S_IT_UDR and SPI_I2S_IT_FRE</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: I2S_FLAG_CHSIDE, I2S_FLAG_UDR and SPI_I2S_FLAG_FRE</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: I2S_Init(), I2S_StructInit() and I2S_Cmd()<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_syscfg.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Add support for new port: EXTI_PortSourceGPIOF and EXTI_PortSourceGPIOG</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new remap for FSMC: SYSCFG_MemoryRemap_FSMC</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new RI Channels and new RI IOSwitch</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: SYSCFG_GetBootMode() and SYSCFG_RIChannelSpeedConfig()<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_tim.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support TIM 32-bit</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change TIM_Period and TIM_Pulse to be declared as 32-bit</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the "TIM_DMABase_RCR": the RCR register is not present on STM32L1xx family.<br>
+                  </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add </span><span style="font-size: 10pt; font-family: Verdana;">new parameter: </span><span style="font-size: 10pt; font-family: Verdana;">TIM_DMABase_OR <br>
+                  </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change "TIM_DMABurstLength_1Byte" to "TIM_DMABurstLength_1Transfer"</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
+new TIM_Remap: TIM2_TIM10_OC, TIM2_TIM5_TRGO, TIM3_TIM11_OC,
+TIM3_TIM5_TRGO, TIM10_ETR_LSE, TIM10_ETR_TIM9_TRGO, TIM11_ETR_LSE and
+TIM11_ETR_TIM9_TRGO.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update TIM_RemapConfig() function coding.</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comments to support TIM5.<br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_usart.h/.c</span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support UART4 and UART5</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comment<br>
+                  </span></li>
+              </ul>
+            </ul>
+            <p class="MsoNormal"><br>
+            </p>
+
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 31-December-2010<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
+
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span>
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+<hr align="center" size="2" width="100%"></span></div>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+</td>
+</tr>
+</tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+</body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/misc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/misc.h
new file mode 100644
index 0000000..17aa038
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/misc.h
@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be a value of @ref IRQn_Type 
+                                                   (For the complete STM32 Devices IRQ Channels list, please
+                                                    refer to stm32l1xx.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+
+/**  
+  *
+@verbatim   
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------    
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
+                         |                                   |                             |   0 bits for subpriority                       
+  ============================================================================================================================
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0005FFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_adc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_adc.h
new file mode 100644
index 0000000..ea49833
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_adc.h
@@ -0,0 +1,650 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_adc.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_ADC_H
+#define __STM32L1xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  ADC Init structure definition  
+  */
+  
+typedef struct
+{
+  uint32_t ADC_Resolution;                /*!< Selects the resolution of the conversion.
+                                               This parameter can be a value of @ref ADC_Resolution */
+  
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion is performed in
+                                               Scan (multichannel) or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */
+  
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  
+  uint32_t ADC_ExternalTrigConvEdge;      /*!< Selects the external trigger Edge and enables the
+                                               trigger of a regular group. This parameter can be a value
+                                               of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+  
+  uint32_t ADC_ExternalTrigConv;          /*!< Defines the external trigger used to start the analog
+                                               to digital conversion of regular channels. This parameter
+                                               can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+  
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data alignment is left or right.
+                                               This parameter can be a value of @ref ADC_data_align */
+  
+  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions that will be done
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 27. */
+}ADC_InitTypeDef;
+
+typedef struct 
+{                                              
+  uint32_t ADC_Prescaler;                 /*!< Selects the ADC prescaler.
+                                               This parameter can be a value 
+                                               of @ref ADC_Prescaler */
+}ADC_CommonInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
+#define IS_ADC_DMA_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
+
+/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase 
+  * @{
+  */ 
+#define ADC_PowerDown_Delay                        ((uint32_t)0x00010000)
+#define ADC_PowerDown_Idle                         ((uint32_t)0x00020000)
+#define ADC_PowerDown_Idle_Delay                   ((uint32_t)0x00030000)
+
+#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
+                                 ((DWON) == ADC_PowerDown_Idle) || \
+                                 ((DWON) == ADC_PowerDown_Idle_Delay))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Prescaler 
+  * @{
+  */ 
+#define ADC_Prescaler_Div1                         ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div2                         ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div4                         ((uint32_t)0x00020000)
+
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div2) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div4))
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup ADC_Resolution 
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
+#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
+#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConvEdge_None              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising            ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling           ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling     ((uint32_t)0x30000000)
+
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                                    ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+  * @{
+  */ 
+
+/* TIM2 */
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
+
+/* TIM3 */
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_CC3                ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x04000000)
+
+/* TIM4 */
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T4_TRGO               ((uint32_t)0x09000000)
+
+/* TIM6 */
+#define ADC_ExternalTrigConv_T6_TRGO               ((uint32_t)0x0A000000)
+
+/* TIM9 */
+#define ADC_ExternalTrigConv_T9_CC2                ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T9_TRGO               ((uint32_t)0x01000000)
+
+/* EXTI */
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3)  || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+  
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+/* ADC Bank A Channels -------------------------------------------------------*/  
+#define ADC_Channel_0                              ((uint8_t)0x00)
+#define ADC_Channel_1                              ((uint8_t)0x01)
+#define ADC_Channel_2                              ((uint8_t)0x02)
+#define ADC_Channel_3                              ((uint8_t)0x03)
+
+#define ADC_Channel_6                              ((uint8_t)0x06)
+#define ADC_Channel_7                              ((uint8_t)0x07)
+#define ADC_Channel_8                              ((uint8_t)0x08)
+#define ADC_Channel_9                              ((uint8_t)0x09)
+#define ADC_Channel_10                             ((uint8_t)0x0A)
+#define ADC_Channel_11                             ((uint8_t)0x0B)
+#define ADC_Channel_12                             ((uint8_t)0x0C)
+
+
+/* ADC Bank B Channels -------------------------------------------------------*/  
+#define ADC_Channel_0b                             ADC_Channel_0
+#define ADC_Channel_1b                             ADC_Channel_1
+#define ADC_Channel_2b                             ADC_Channel_2
+#define ADC_Channel_3b                             ADC_Channel_3
+
+#define ADC_Channel_6b                             ADC_Channel_6
+#define ADC_Channel_7b                             ADC_Channel_7
+#define ADC_Channel_8b                             ADC_Channel_8
+#define ADC_Channel_9b                             ADC_Channel_9
+#define ADC_Channel_10b                            ADC_Channel_10
+#define ADC_Channel_11b                            ADC_Channel_11
+#define ADC_Channel_12b                            ADC_Channel_12
+
+/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
+#define ADC_Channel_4                              ((uint8_t)0x04)
+#define ADC_Channel_5                              ((uint8_t)0x05)
+
+#define ADC_Channel_13                             ((uint8_t)0x0D)
+#define ADC_Channel_14                             ((uint8_t)0x0E)
+#define ADC_Channel_15                             ((uint8_t)0x0F)
+#define ADC_Channel_16                             ((uint8_t)0x10)
+#define ADC_Channel_17                             ((uint8_t)0x11)
+#define ADC_Channel_18                             ((uint8_t)0x12)
+#define ADC_Channel_19                             ((uint8_t)0x13)
+#define ADC_Channel_20                             ((uint8_t)0x14)
+#define ADC_Channel_21                             ((uint8_t)0x15)
+#define ADC_Channel_22                             ((uint8_t)0x16)
+#define ADC_Channel_23                             ((uint8_t)0x17)
+#define ADC_Channel_24                             ((uint8_t)0x18)
+#define ADC_Channel_25                             ((uint8_t)0x19)
+
+#define ADC_Channel_27                             ((uint8_t)0x1B)
+#define ADC_Channel_28                             ((uint8_t)0x1C)
+#define ADC_Channel_29                             ((uint8_t)0x1D)
+#define ADC_Channel_30                             ((uint8_t)0x1E)
+#define ADC_Channel_31                             ((uint8_t)0x1F)
+
+#define ADC_Channel_TempSensor                     ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                        ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0)  || ((CHANNEL) == ADC_Channel_1)  || \
+                                 ((CHANNEL) == ADC_Channel_2)  || ((CHANNEL) == ADC_Channel_3)  || \
+                                 ((CHANNEL) == ADC_Channel_4)  || ((CHANNEL) == ADC_Channel_5)  || \
+                                 ((CHANNEL) == ADC_Channel_6)  || ((CHANNEL) == ADC_Channel_7)  || \
+                                 ((CHANNEL) == ADC_Channel_8)  || ((CHANNEL) == ADC_Channel_9)  || \
+                                 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
+                                 ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
+                                 ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
+                                 ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
+                                 ((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
+                                 ((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
+                                 ((CHANNEL) == ADC_Channel_31))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+
+#define ADC_SampleTime_4Cycles                     ((uint8_t)0x00)
+#define ADC_SampleTime_9Cycles                     ((uint8_t)0x01)
+#define ADC_SampleTime_16Cycles                    ((uint8_t)0x02)
+#define ADC_SampleTime_24Cycles                    ((uint8_t)0x03)
+#define ADC_SampleTime_48Cycles                    ((uint8_t)0x04)
+#define ADC_SampleTime_96Cycles                    ((uint8_t)0x05)
+#define ADC_SampleTime_192Cycles                   ((uint8_t)0x06)
+#define ADC_SampleTime_384Cycles                   ((uint8_t)0x07)
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_9Cycles)   || \
+                                  ((TIME) == ADC_SampleTime_16Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_24Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_48Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_96Cycles)  || \
+                                  ((TIME) == ADC_SampleTime_192Cycles) || \
+                                  ((TIME) == ADC_SampleTime_384Cycles))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Delay_length 
+  * @{
+  */ 
+
+#define ADC_DelayLength_None                       ((uint8_t)0x00)
+#define ADC_DelayLength_Freeze                     ((uint8_t)0x10)
+#define ADC_DelayLength_7Cycles                    ((uint8_t)0x20)
+#define ADC_DelayLength_15Cycles                   ((uint8_t)0x30)
+#define ADC_DelayLength_31Cycles                   ((uint8_t)0x40)
+#define ADC_DelayLength_63Cycles                   ((uint8_t)0x50)
+#define ADC_DelayLength_127Cycles                  ((uint8_t)0x60)
+#define ADC_DelayLength_255Cycles                  ((uint8_t)0x70)
+
+#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None)      || \
+                                     ((LENGTH) == ADC_DelayLength_Freeze)    || \
+                                     ((LENGTH) == ADC_DelayLength_7Cycles)   || \
+                                     ((LENGTH) == ADC_DelayLength_15Cycles)  || \
+                                     ((LENGTH) == ADC_DelayLength_31Cycles)  || \
+                                     ((LENGTH) == ADC_DelayLength_63Cycles)  || \
+                                     ((LENGTH) == ADC_DelayLength_127Cycles) || \
+                                     ((LENGTH) == ADC_DelayLength_255Cycles))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None)    || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising)  || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */ 
+
+
+/* TIM2 */
+#define ADC_ExternalTrigInjecConv_T2_TRGO          ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_CC1           ((uint32_t)0x00030000)
+
+/* TIM3 */
+#define ADC_ExternalTrigInjecConv_T3_CC4           ((uint32_t)0x00040000)
+
+/* TIM4 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO          ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1           ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2           ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3           ((uint32_t)0x00080000)
+
+/* TIM7 */
+#define ADC_ExternalTrigInjecConv_T7_TRGO          ((uint32_t)0x000A0000)
+
+/* TIM9 */
+#define ADC_ExternalTrigInjecConv_T9_CC1           ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T9_TRGO          ((uint32_t)0x00010000)
+
+/* TIM10 */
+#define ADC_ExternalTrigInjecConv_T10_CC1          ((uint32_t)0x00090000)
+
+/* EXTI */
+#define ADC_ExternalTrigInjecConv_Ext_IT15         ((uint32_t)0x000F0000)
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3)  || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */ 
+#define ADC_InjectedChannel_1                      ((uint8_t)0x18)
+#define ADC_InjectedChannel_2                      ((uint8_t)0x1C)
+#define ADC_InjectedChannel_3                      ((uint8_t)0x20)
+#define ADC_InjectedChannel_4                      ((uint8_t)0x24)
+
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+  
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200) 
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable)        || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable)      || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable)           || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable)         || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable)   || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+  
+#define ADC_IT_AWD                                 ((uint16_t)0x0106) 
+#define ADC_IT_EOC                                 ((uint16_t)0x0205) 
+#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
+#define ADC_IT_OVR                                 ((uint16_t)0x201A) 
+ 
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+  
+#define ADC_FLAG_AWD                               ((uint16_t)0x0001)
+#define ADC_FLAG_EOC                               ((uint16_t)0x0002)
+#define ADC_FLAG_JEOC                              ((uint16_t)0x0004)
+#define ADC_FLAG_JSTRT                             ((uint16_t)0x0008)
+#define ADC_FLAG_STRT                              ((uint16_t)0x0010)
+#define ADC_FLAG_OVR                               ((uint16_t)0x0020)
+#define ADC_FLAG_ADONS                             ((uint16_t)0x0040)
+#define ADC_FLAG_RCNR                              ((uint16_t)0x0100)
+#define ADC_FLAG_JCNR                              ((uint16_t)0x0200) 
+  
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
+   
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD)   || ((FLAG) == ADC_FLAG_EOC)  || \
+                               ((FLAG) == ADC_FLAG_JEOC)  || ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT)  || ((FLAG)== ADC_FLAG_OVR)   || \
+                               ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR)  || \
+                               ((FLAG) == ADC_FLAG_JCNR))
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+  
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */
+   
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */
+   
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */ 
+  
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */
+   
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */ 
+  
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */
+   
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ADC_Bank_Selection 
+  * @{
+  */ 
+#define ADC_Bank_A                                 ((uint8_t)0x00)
+#define ADC_Bank_B                                 ((uint8_t)0x01)  
+#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A)   || ((BANK) == ADC_Bank_B))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the ADC configuration to the default reset state *****/   
+void ADC_DeInit(ADC_TypeDef* ADCx); 
+
+/* Initialization and Configuration functions *********************************/ 
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
+
+/* Power saving functions *****************************************************/
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_ADC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_aes.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_aes.h
new file mode 100644
index 0000000..46dcc01
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_aes.h
@@ -0,0 +1,236 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_aes.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the AES firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_AES_H
+#define __STM32L1xx_AES_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup AES
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief   AES Init structure definition
+  */
+typedef struct
+{
+  uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
+                               This parameter can be a value of @ref AES_possible_Operation_modes */
+  uint32_t AES_Chaining;  /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
+                               This parameter can be a value of @ref AES_possible_chaining_modes */
+  uint32_t AES_DataType;  /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
+                               This parameter can be a value of @ref AES_Data_Types */
+}AES_InitTypeDef;
+
+/** 
+  * @brief   AES Key(s) structure definition
+  */ 
+typedef struct
+{
+  uint32_t AES_Key0;  /*!< Key[31:0]   */
+  uint32_t AES_Key1;  /*!< Key[63:32]  */
+  uint32_t AES_Key2;  /*!< Key[95:64]  */
+  uint32_t AES_Key3;  /*!< Key[127:96] */
+}AES_KeyInitTypeDef;
+
+/** 
+  * @brief   AES Initialization Vectors (IV) structure definition
+  */ 
+typedef struct
+{
+  uint32_t AES_IV0;  /*!< Init Vector IV[31:0]   */
+  uint32_t AES_IV1;  /*!< Init Vector IV[63:32]  */
+  uint32_t AES_IV2;  /*!< Init Vector IV[95:64]  */
+  uint32_t AES_IV3;  /*!< Init Vector IV[127:96] */
+}AES_IVInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup AES_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup AES_possible_Operation_modes
+  * @{
+  */  
+#define AES_Operation_Encryp               ((uint32_t)0x00000000) /*!< AES in Encryption mode */
+#define AES_Operation_KeyDeriv             AES_CR_MODE_0          /*!< AES in Key Derivation mode */
+#define AES_Operation_Decryp               AES_CR_MODE_1          /*!< AES in Decryption mode */
+#define AES_Operation_KeyDerivAndDecryp    AES_CR_MODE            /*!< AES in Key Derivation and Decryption mode */
+
+#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp)    || \
+                                ((OPERATION) == AES_Operation_KeyDeriv)  || \
+                                ((OPERATION) == AES_Operation_Decryp)    || \
+                                ((OPERATION) == AES_Operation_KeyDerivAndDecryp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup AES_possible_chaining_modes
+  * @{
+  */ 
+#define AES_Chaining_ECB                   ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
+#define AES_Chaining_CBC                   AES_CR_CHMOD_0         /*!< AES in CBC chaining mode */
+#define AES_Chaining_CTR                   AES_CR_CHMOD_1         /*!< AES in CTR chaining mode */
+
+#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
+                                   ((CHAINING) == AES_Chaining_CBC) || \
+                                   ((CHAINING) == AES_Chaining_CTR))
+/**
+  * @}
+  */
+
+/** @defgroup AES_Data_Types
+  * @{
+  */ 
+#define AES_DataType_32b                   ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
+#define AES_DataType_16b                   AES_CR_DATATYPE_0      /*!< 16-bit data. Each half word is swapped */
+#define AES_DataType_8b                    AES_CR_DATATYPE_1      /*!< 8-bit data. All bytes are swapped */
+#define AES_DataType_1b                    AES_CR_DATATYPE        /*!< 1-bit data. In the word all bits are swapped */
+
+#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
+                                    ((DATATYPE) == AES_DataType_16b)|| \
+                                    ((DATATYPE) == AES_DataType_8b) || \
+                                    ((DATATYPE) == AES_DataType_1b))
+/**
+  * @}
+  */
+
+/** @defgroup AES_Flags
+  * @{
+  */ 
+#define AES_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
+#define AES_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
+#define AES_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
+
+#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF)    || \
+                           ((FLAG) == AES_FLAG_RDERR)  || \
+                           ((FLAG) == AES_FLAG_WRERR))
+/**
+  * @}
+  */ 
+
+/** @defgroup AES_Interrupts
+  * @{
+  */ 
+#define AES_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
+#define AES_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
+
+#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
+#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_DMA_Transfer_modes
+  * @{
+  */ 
+#define AES_DMATransfer_In                 AES_CR_DMAINEN                     /*!< DMA requests enabled for input transfer phase */
+#define AES_DMATransfer_Out                AES_CR_DMAOUTEN                    /*!< DMA requests enabled for input transfer phase */
+#define AES_DMATransfer_InOut              (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
+
+#define IS_AES_DMA_TRANSFER(TRANSFER)   (((TRANSFER) == AES_DMATransfer_In)  || \
+                                         ((TRANSFER) == AES_DMATransfer_Out)  || \
+                                         ((TRANSFER) == AES_DMATransfer_InOut))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Initialization and configuration functions *********************************/
+void AES_DeInit(void);
+void AES_Init(AES_InitTypeDef* AES_InitStruct);
+void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
+void AES_Cmd(FunctionalState NewState);
+
+/* Structures initialization functions ****************************************/
+void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
+void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
+
+/* AES Read and Write functions **********************************************/  
+void AES_WriteSubData(uint32_t Data);
+uint32_t AES_ReadSubData(void);
+void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
+void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
+
+/* DMA transfers management function ******************************************/
+void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
+FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
+void AES_ClearFlag(uint32_t AES_FLAG);
+ITStatus AES_GetITStatus(uint32_t AES_IT);
+void AES_ClearITPendingBit(uint32_t AES_IT);
+
+/* High Level AES functions **************************************************/
+ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_AES_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_comp.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_comp.h
new file mode 100644
index 0000000..efec1ee
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_comp.h
@@ -0,0 +1,187 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_comp.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the COMP firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_COMP_H
+#define __STM32L1xx_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  COMP Init structure definition  
+  */
+  
+typedef struct
+{
+  uint32_t COMP_Speed;               /*!< Defines the speed of comparator 2.
+                                          This parameter can be a value of @ref COMP_Speed */
+  uint32_t COMP_InvertingInput;      /*!< Selects the inverting input of the comparator 2.
+                                          This parameter can be a value of @ref COMP_InvertingInput */
+  uint32_t COMP_OutputSelect;        /*!< Selects the output redirection of the comparator 2.
+                                          This parameter can be a value of @ref COMP_OutputSelect */
+   
+}COMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+   
+/** @defgroup COMP_Exported_Constants
+  * @{
+  */ 
+
+#define COMP_OutputLevel_High                   ((uint32_t)0x00000001)
+#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+
+#define COMP_Selection_COMP1                    ((uint32_t)0x00000001)
+#define COMP_Selection_COMP2                    ((uint32_t)0x00000002)
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+                                    ((PERIPH) == COMP_Selection_COMP2))
+ 
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_InvertingInput
+  * @{
+  */
+
+#define COMP_InvertingInput_None                ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
+#define COMP_InvertingInput_IO                  ((uint32_t)0x00040000)
+#define COMP_InvertingInput_VREFINT             ((uint32_t)0x00080000)
+#define COMP_InvertingInput_3_4VREFINT          ((uint32_t)0x000C0000)
+#define COMP_InvertingInput_1_2VREFINT          ((uint32_t)0x00100000)
+#define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00140000)
+#define COMP_InvertingInput_DAC1                ((uint32_t)0x00180000)
+#define COMP_InvertingInput_DAC2                ((uint32_t)0x001C0000)
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
+                                        ((INPUT) == COMP_InvertingInput_IO) || \
+                                        ((INPUT) == COMP_InvertingInput_VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1) || \
+                                        ((INPUT) == COMP_InvertingInput_DAC2))
+/**
+  * @}
+  */ 
+
+/** @defgroup COMP_OutputSelect
+  * @{
+  */
+
+#define COMP_OutputSelect_TIM2IC4               ((uint32_t)0x00000000)
+#define COMP_OutputSelect_TIM2OCREFCLR          ((uint32_t)0x00200000)
+#define COMP_OutputSelect_TIM3IC4               ((uint32_t)0x00400000)
+#define COMP_OutputSelect_TIM3OCREFCLR          ((uint32_t)0x00600000)
+#define COMP_OutputSelect_TIM4IC4               ((uint32_t)0x00800000)
+#define COMP_OutputSelect_TIM4OCREFCLR          ((uint32_t)0x00A00000)
+#define COMP_OutputSelect_TIM10IC1              ((uint32_t)0x00C00000)
+#define COMP_OutputSelect_None                  ((uint32_t)0x00E00000)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
+                                ((OUTPUT) == COMP_OutputSelect_None))
+/**
+  * @}
+  */ 
+  
+/** @defgroup COMP_Speed
+  * @{
+  */
+
+#define COMP_Speed_Slow                         ((uint32_t)0x00000000)
+#define COMP_Speed_Fast                         ((uint32_t)0x00001000)
+
+#define IS_COMP_SPEED(SPEED)    (((SPEED) == COMP_Speed_Slow) || \
+                                 ((SPEED) == COMP_Speed_Fast))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the COMP configuration to the default reset state ****/
+void COMP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
+void COMP_Cmd(FunctionalState NewState);
+uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
+void COMP_SW1SwitchConfig(FunctionalState NewState);
+
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+
+/* Internal Reference Voltage (VREFINT) output function ***********************/
+void COMP_VrefintOutputCmd(FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_COMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dbgmcu.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dbgmcu.h
new file mode 100644
index 0000000..04d0c24
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dbgmcu.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the DBGMCU 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_DBGMCU_H
+#define __STM32L1xx_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */
+
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00000008)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x00000010)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_DBGMCU_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dma.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dma.h
new file mode 100644
index 0000000..8971e77
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dma.h
@@ -0,0 +1,435 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_dma.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_DMA_H
+#define __STM32L1xx_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note: The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                        This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+                                   ((PERIPH) == DMA1_Channel2) || \
+                                   ((PERIPH) == DMA1_Channel3) || \
+                                   ((PERIPH) == DMA1_Channel4) || \
+                                   ((PERIPH) == DMA1_Channel5) || \
+                                   ((PERIPH) == DMA1_Channel6) || \
+                                   ((PERIPH) == DMA1_Channel7) || \
+                                   ((PERIPH) == DMA2_Channel1) || \
+                                   ((PERIPH) == DMA2_Channel2) || \
+                                   ((PERIPH) == DMA2_Channel3) || \
+                                   ((PERIPH) == DMA2_Channel4) || \
+                                   ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */
+
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+                         ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */
+
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */
+
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */
+
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */
+
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_memory_to_memory 
+  * @{
+  */
+
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupts_definition 
+  * @{
+  */
+
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Buffer_Size 
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the DMA configuration to the default reset state *****/ 
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
new file mode 100644
index 0000000..cb16d9f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
@@ -0,0 +1,199 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_exti.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_EXTI_H
+#define __STM32L1xx_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 
+                                                      Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< External interrupt line 17 
+                                                      Connected to the RTC Alarm 
+                                                      event */
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< External interrupt line 18 
+                                                      Connected to the USB Device 
+                                                      FS Wakeup from suspend event */
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< External interrupt line 19 
+                                                      Connected to the RTC Tamper 
+                                                      and Time Stamp events */ 
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 
+                                                      Connected to the RTC Wakeup 
+                                                      event */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 
+                                                      Connected to the Comparator 1 
+                                                      event */
+
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 
+                                                      Connected to the Comparator 2
+                                                      event */
+
+#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< External interrupt line 23 
+                                                      Comparator channel acquisition event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_EXTI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_flash.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_flash.h
new file mode 100644
index 0000000..202ffc2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_flash.h
@@ -0,0 +1,464 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_flash.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_FLASH_H
+#define __STM32L1xx_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  FLASH Status  
+  */ 
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup FLASH_Latency 
+  * @{
+  */ 
+#define FLASH_Latency_0                ((uint8_t)0x00)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint8_t)0x01)  /*!< FLASH One Latency cycle */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */
+   
+#define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
+#define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Address 
+  * @{
+  */
+  
+#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))  
+
+/**
+  * @}
+  */ 
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */
+  
+#define OB_WRP_Pages0to15              ((uint32_t)0x00000001) /* Write protection of Sector0 */
+#define OB_WRP_Pages16to31             ((uint32_t)0x00000002) /* Write protection of Sector1 */
+#define OB_WRP_Pages32to47             ((uint32_t)0x00000004) /* Write protection of Sector2 */
+#define OB_WRP_Pages48to63             ((uint32_t)0x00000008) /* Write protection of Sector3 */
+#define OB_WRP_Pages64to79             ((uint32_t)0x00000010) /* Write protection of Sector4 */
+#define OB_WRP_Pages80to95             ((uint32_t)0x00000020) /* Write protection of Sector5 */
+#define OB_WRP_Pages96to111            ((uint32_t)0x00000040) /* Write protection of Sector6 */
+#define OB_WRP_Pages112to127           ((uint32_t)0x00000080) /* Write protection of Sector7 */
+#define OB_WRP_Pages128to143           ((uint32_t)0x00000100) /* Write protection of Sector8 */
+#define OB_WRP_Pages144to159           ((uint32_t)0x00000200) /* Write protection of Sector9 */
+#define OB_WRP_Pages160to175           ((uint32_t)0x00000400) /* Write protection of Sector10 */
+#define OB_WRP_Pages176to191           ((uint32_t)0x00000800) /* Write protection of Sector11 */
+#define OB_WRP_Pages192to207           ((uint32_t)0x00001000) /* Write protection of Sector12 */
+#define OB_WRP_Pages208to223           ((uint32_t)0x00002000) /* Write protection of Sector13 */
+#define OB_WRP_Pages224to239           ((uint32_t)0x00004000) /* Write protection of Sector14 */
+#define OB_WRP_Pages240to255           ((uint32_t)0x00008000) /* Write protection of Sector15 */
+#define OB_WRP_Pages256to271           ((uint32_t)0x00010000) /* Write protection of Sector16 */
+#define OB_WRP_Pages272to287           ((uint32_t)0x00020000) /* Write protection of Sector17 */
+#define OB_WRP_Pages288to303           ((uint32_t)0x00040000) /* Write protection of Sector18 */
+#define OB_WRP_Pages304to319           ((uint32_t)0x00080000) /* Write protection of Sector19 */
+#define OB_WRP_Pages320to335           ((uint32_t)0x00100000) /* Write protection of Sector20 */
+#define OB_WRP_Pages336to351           ((uint32_t)0x00200000) /* Write protection of Sector21 */
+#define OB_WRP_Pages352to367           ((uint32_t)0x00400000) /* Write protection of Sector22 */
+#define OB_WRP_Pages368to383           ((uint32_t)0x00800000) /* Write protection of Sector23 */
+#define OB_WRP_Pages384to399           ((uint32_t)0x01000000) /* Write protection of Sector24 */
+#define OB_WRP_Pages400to415           ((uint32_t)0x02000000) /* Write protection of Sector25 */
+#define OB_WRP_Pages416to431           ((uint32_t)0x04000000) /* Write protection of Sector26 */
+#define OB_WRP_Pages432to447           ((uint32_t)0x08000000) /* Write protection of Sector27 */
+#define OB_WRP_Pages448to463           ((uint32_t)0x10000000) /* Write protection of Sector28 */
+#define OB_WRP_Pages464to479           ((uint32_t)0x20000000) /* Write protection of Sector29 */
+#define OB_WRP_Pages480to495           ((uint32_t)0x40000000) /* Write protection of Sector30 */
+#define OB_WRP_Pages496to511           ((uint32_t)0x80000000) /* Write protection of Sector31 */
+
+#define OB_WRP_AllPages                ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define OB_WRP1_Pages512to527          ((uint32_t)0x00000001) /* Write protection of Sector32 */
+#define OB_WRP1_Pages528to543          ((uint32_t)0x00000002) /* Write protection of Sector33 */
+#define OB_WRP1_Pages544to559          ((uint32_t)0x00000004) /* Write protection of Sector34 */
+#define OB_WRP1_Pages560to575          ((uint32_t)0x00000008) /* Write protection of Sector35 */
+#define OB_WRP1_Pages576to591          ((uint32_t)0x00000010) /* Write protection of Sector36 */
+#define OB_WRP1_Pages592to607          ((uint32_t)0x00000020) /* Write protection of Sector37 */
+#define OB_WRP1_Pages608to623          ((uint32_t)0x00000040) /* Write protection of Sector38 */
+#define OB_WRP1_Pages624to639          ((uint32_t)0x00000080) /* Write protection of Sector39 */
+#define OB_WRP1_Pages640to655          ((uint32_t)0x00000100) /* Write protection of Sector40 */
+#define OB_WRP1_Pages656to671          ((uint32_t)0x00000200) /* Write protection of Sector41 */
+#define OB_WRP1_Pages672to687          ((uint32_t)0x00000400) /* Write protection of Sector42 */
+#define OB_WRP1_Pages688to703          ((uint32_t)0x00000800) /* Write protection of Sector43 */
+#define OB_WRP1_Pages704to719          ((uint32_t)0x00001000) /* Write protection of Sector44 */
+#define OB_WRP1_Pages720to735          ((uint32_t)0x00002000) /* Write protection of Sector45 */
+#define OB_WRP1_Pages736to751          ((uint32_t)0x00004000) /* Write protection of Sector46 */
+#define OB_WRP1_Pages752to767          ((uint32_t)0x00008000) /* Write protection of Sector47 */
+#define OB_WRP1_Pages768to783          ((uint32_t)0x00010000) /* Write protection of Sector48 */
+#define OB_WRP1_Pages784to799          ((uint32_t)0x00020000) /* Write protection of Sector49 */
+#define OB_WRP1_Pages800to815          ((uint32_t)0x00040000) /* Write protection of Sector50 */
+#define OB_WRP1_Pages816to831          ((uint32_t)0x00080000) /* Write protection of Sector51 */
+#define OB_WRP1_Pages832to847          ((uint32_t)0x00100000) /* Write protection of Sector52 */
+#define OB_WRP1_Pages848to863          ((uint32_t)0x00200000) /* Write protection of Sector53 */
+#define OB_WRP1_Pages864to879          ((uint32_t)0x00400000) /* Write protection of Sector54 */
+#define OB_WRP1_Pages880to895          ((uint32_t)0x00800000) /* Write protection of Sector55 */
+#define OB_WRP1_Pages896to911          ((uint32_t)0x01000000) /* Write protection of Sector56 */
+#define OB_WRP1_Pages912to927          ((uint32_t)0x02000000) /* Write protection of Sector57 */
+#define OB_WRP1_Pages928to943          ((uint32_t)0x04000000) /* Write protection of Sector58 */
+#define OB_WRP1_Pages944to959          ((uint32_t)0x08000000) /* Write protection of Sector59 */
+#define OB_WRP1_Pages960to975          ((uint32_t)0x10000000) /* Write protection of Sector60 */
+#define OB_WRP1_Pages976to991          ((uint32_t)0x20000000) /* Write protection of Sector61 */
+#define OB_WRP1_Pages992to1007         ((uint32_t)0x40000000) /* Write protection of Sector62 */
+#define OB_WRP1_Pages1008to1023        ((uint32_t)0x80000000) /* Write protection of Sector63 */
+
+#define OB_WRP1_AllPages               ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define OB_WRP2_Pages1024to1039        ((uint32_t)0x00000001) /* Write protection of Sector64 */
+#define OB_WRP2_Pages1040to1055        ((uint32_t)0x00000002) /* Write protection of Sector65 */
+#define OB_WRP2_Pages1056to1071        ((uint32_t)0x00000004) /* Write protection of Sector66 */
+#define OB_WRP2_Pages1072to1087        ((uint32_t)0x00000008) /* Write protection of Sector67 */
+#define OB_WRP2_Pages1088to1103        ((uint32_t)0x00000010) /* Write protection of Sector68 */
+#define OB_WRP2_Pages1104to1119        ((uint32_t)0x00000020) /* Write protection of Sector69 */
+#define OB_WRP2_Pages1120to1135        ((uint32_t)0x00000040) /* Write protection of Sector70 */
+#define OB_WRP2_Pages1136to1151        ((uint32_t)0x00000080) /* Write protection of Sector71 */
+#define OB_WRP2_Pages1152to1167        ((uint32_t)0x00000100) /* Write protection of Sector72 */
+#define OB_WRP2_Pages1168to1183        ((uint32_t)0x00000200) /* Write protection of Sector73 */
+#define OB_WRP2_Pages1184to1199        ((uint32_t)0x00000400) /* Write protection of Sector74 */
+#define OB_WRP2_Pages1200to1215        ((uint32_t)0x00000800) /* Write protection of Sector75 */
+#define OB_WRP2_Pages1216to1231        ((uint32_t)0x00001000) /* Write protection of Sector76 */
+#define OB_WRP2_Pages1232to1247        ((uint32_t)0x00002000) /* Write protection of Sector77 */
+#define OB_WRP2_Pages1248to1263        ((uint32_t)0x00004000) /* Write protection of Sector78 */
+#define OB_WRP2_Pages1264to1279        ((uint32_t)0x00008000) /* Write protection of Sector79 */
+#define OB_WRP2_Pages1280to1295        ((uint32_t)0x00010000) /* Write protection of Sector80 */
+#define OB_WRP2_Pages1296to1311        ((uint32_t)0x00020000) /* Write protection of Sector81 */
+#define OB_WRP2_Pages1312to1327        ((uint32_t)0x00040000) /* Write protection of Sector82 */
+#define OB_WRP2_Pages1328to1343        ((uint32_t)0x00080000) /* Write protection of Sector83 */
+#define OB_WRP2_Pages1344to1359        ((uint32_t)0x00100000) /* Write protection of Sector84 */
+#define OB_WRP2_Pages1360to1375        ((uint32_t)0x00200000) /* Write protection of Sector85 */
+#define OB_WRP2_Pages1376to1391        ((uint32_t)0x00400000) /* Write protection of Sector86 */
+#define OB_WRP2_Pages1392to1407        ((uint32_t)0x00800000) /* Write protection of Sector87 */
+#define OB_WRP2_Pages1408to1423        ((uint32_t)0x01000000) /* Write protection of Sector88 */
+#define OB_WRP2_Pages1424to1439        ((uint32_t)0x02000000) /* Write protection of Sector89 */
+#define OB_WRP2_Pages1440to1455        ((uint32_t)0x04000000) /* Write protection of Sector90 */
+#define OB_WRP2_Pages1456to1471        ((uint32_t)0x08000000) /* Write protection of Sector91 */
+#define OB_WRP2_Pages1472to1487        ((uint32_t)0x10000000) /* Write protection of Sector92 */
+#define OB_WRP2_Pages1488to1503        ((uint32_t)0x20000000) /* Write protection of Sector93 */
+#define OB_WRP2_Pages1504to1519        ((uint32_t)0x40000000) /* Write protection of Sector94 */
+#define OB_WRP2_Pages1520to1535        ((uint32_t)0x80000000) /* Write protection of Sector95 */
+
+#define OB_WRP2_AllPages               ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_Read_Protection 
+  * @{
+  */ 
+
+/** 
+  * @brief  Read Protection Level  
+  */ 
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 
+                                                it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */ 
+
+/** @defgroup Option_Bytes_IWatchdog 
+  * @{
+  */
+
+#define OB_IWDG_SW                     ((uint8_t)0x10)  /*!< Software WDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware WDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STOP 
+  * @{
+  */
+
+#define OB_STOP_NoRST                  ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_nRST_STDBY 
+  * @{
+  */
+
+#define OB_STDBY_NoRST                 ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_BOOT
+  * @{
+  */
+
+#define OB_BOOT_BANK2                  ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                            and this parameter is selected the device will boot from Bank 2 
+                                                            or Bank 1, depending on the activation of the bank */
+#define OB_BOOT_BANK1                  ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
+                                                            and this parameter is selected the device will boot from Bank1(Default) */
+#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
+
+/**
+  * @}
+  */
+
+/** @defgroup Option_Bytes_BOR_Level 
+  * @{
+  */
+
+#define OB_BOR_OFF       ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD 
+                                              power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
+#define OB_BOR_LEVEL1    ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply    */
+#define OB_BOR_LEVEL2    ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply    */
+#define OB_BOR_LEVEL3    ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply    */
+#define OB_BOR_LEVEL4    ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply  */
+#define OB_BOR_LEVEL5    ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply    */
+
+#define IS_OB_BOR_LEVEL(LEVEL)  (((LEVEL) == OB_BOR_OFF) || \
+                                 ((LEVEL) == OB_BOR_LEVEL1) || \
+                                 ((LEVEL) == OB_BOR_LEVEL2) || \
+                                 ((LEVEL) == OB_BOR_LEVEL3) || \
+                                 ((LEVEL) == OB_BOR_LEVEL4) || \
+                                 ((LEVEL) == OB_BOR_LEVEL5))
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Flags 
+  * @{
+  */ 
+
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY  /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP  /*!< FLASH End of Programming flag */
+#define FLASH_FLAG_ENDHV               FLASH_SR_ENHV  /*!< FLASH End of High Voltage flag */
+#define FLASH_FLAG_READY               FLASH_SR_READY  /*!< FLASH Ready flag after low power mode */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR  /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_SIZERR              FLASH_SR_SIZERR  /*!< FLASH Size error flag  */
+#define FLASH_FLAG_OPTVERR             FLASH_SR_OPTVERR  /*!< FLASH Option Validity error flag  */
+#define FLASH_FLAG_OPTVERRUSR          FLASH_SR_OPTVERRUSR  /*!< FLASH Option User Validity error flag  */
+ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
+                                  ((FLAG) ==  FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
+                                  ((FLAG) ==  FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
+                                  ((FLAG) ==  FLASH_FLAG_OPTVERRUSR))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys 
+  * @{
+  */ 
+
+#define FLASH_PDKEY1               ((uint32_t)0x04152637) /*!< Flash power down key1 */
+#define FLASH_PDKEY2               ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                              to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_PEKEY1               ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
+#define FLASH_PEKEY2               ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
+                                                               to unlock the write access to the FLASH_PECR register and
+                                                               data EEPROM */
+
+#define FLASH_PRGKEY1              ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
+#define FLASH_PRGKEY2              ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
+                                                               to unlock the program memory */
+
+#define FLASH_OPTKEY1              ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
+#define FLASH_OPTKEY2              ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                              unlock the write access to the option byte block */
+/**
+  * @}
+  */
+  
+/** @defgroup Timeout_definition 
+  * @{
+  */ 
+#define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x8000)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup CMSIS_Legacy 
+  * @{
+  */
+#if defined ( __ICCARM__ )   
+#define InterruptType_ACTLR_DISMCYCINT_Msk         IntType_ACTLR_DISMCYCINT_Msk
+#endif
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+  
+/** 
+  * @brief  FLASH memory functions that can be executed from FLASH.  
+  */  
+/* FLASH Interface configuration functions ************************************/  
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+void FLASH_ReadAccess64Cmd(FunctionalState NewState);
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
+
+/* FLASH Memory Programming functions *****************************************/   
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
+
+/* DATA EEPROM Programming functions ******************************************/  
+void DATA_EEPROM_Unlock(void);
+void DATA_EEPROM_Lock(void);
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
+FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
+FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
+
+/* Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
+FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
+FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+uint32_t FLASH_OB_GetWRP1(void);
+uint32_t FLASH_OB_GetWRP2(void);
+FlagStatus FLASH_OB_GetRDP(void);
+uint8_t FLASH_OB_GetBOR(void);
+
+/* Interrupts and flags management functions **********************************/  
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/** 
+  * @brief  FLASH memory functions that should be executed from internal SRAM.
+  *         These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
+  *         file.
+  */ 
+__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
+__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
+__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
+__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
+__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
+__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_FLASH_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_fsmc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_fsmc.h
new file mode 100644
index 0000000..1f6a277
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_fsmc.h
@@ -0,0 +1,438 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_fsmc.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_FSMC_H
+#define __STM32L1xx_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note It is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address hold time.
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note It is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the data setup time.
+                                             This parameter can be a value between 0 and 0xFF.
+                                             @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the bus turnaround.
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note It is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                             This parameter can be a value between 1 and 0xF.
+                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
+                                          multiplexed on the databus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
+                                          the corresponding memory bank.
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
+                                          This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
+                                          valid only with synchronous burst Flash memories.
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+                                       
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
+                                          valid only with asynchronous Flash memories.
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
+                                          the Flash memory in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
+                                          memory, valid only when accessing Flash memories in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
+                                          clock cycle before the wait state or during the wait state,
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
+}FSMC_NORSRAMInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+/**
+  * @}
+  */
+
+/** @defgroup NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))
+                              
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D)) 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+/* NOR/SRAM Controller functions **********************************************/
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
new file mode 100644
index 0000000..fb072b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
@@ -0,0 +1,391 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_gpio.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the GPIO 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_GPIO_H
+#define __STM32L1xx_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOH) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG))
+
+/** @defgroup Configuration_Mode_enumeration 
+  * @{
+  */ 
+typedef enum
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef;
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+  * @}
+  */
+
+/** @defgroup Output_type_enumeration
+  * @{
+  */ 
+typedef enum
+{ GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+  * @}
+  */
+
+/** @defgroup Output_Maximum_frequency_enumeration 
+  * @{
+  */ 
+typedef enum
+{ 
+  GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */
+  GPIO_Speed_2MHz   = 0x01, /*!< Low Speed */
+  GPIO_Speed_10MHz  = 0x02, /*!< Medium Speed */
+  GPIO_Speed_40MHz  = 0x03  /*!< High Speed */
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+                              ((SPEED) == GPIO_Speed_10MHz)||  ((SPEED) == GPIO_Speed_40MHz))
+/**
+  * @}
+  */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration 
+  * @{
+  */ 
+typedef enum
+{ GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+/**
+  * @}
+  */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+  * @{
+  */
+typedef enum
+{ Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+  * @}
+  */
+
+/** 
+  * @brief  GPIO Init structure definition
+  */ 
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup GPIO_pins_define 
+  * @{
+  */
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Alternat_function_selection_define 
+  * @{
+  */
+
+/** 
+  * @brief  AF 0 selection  
+  */ 
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /*!< RTC 50/60 Hz Alternate Function mapping */
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping */
+#define GPIO_AF_RTC_AF1       ((uint8_t)0x00)  /*!< RTC_AF1 Alternate Function mapping */
+#define GPIO_AF_WKUP          ((uint8_t)0x00)  /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /*!< SWJ (SW and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping */
+
+/** 
+  * @brief  AF 1 selection  
+  */ 
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */
+/** 
+  * @brief  AF 2 selection  
+  */ 
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5          ((uint8_t)0x02)  /*!< TIM5 Alternate Function mapping */
+/** 
+  * @brief  AF 3 selection  
+  */ 
+#define GPIO_AF_TIM9           ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10          ((uint8_t)0x03)  /*!< TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11          ((uint8_t)0x03)  /*!< TIM11 Alternate Function mapping */
+/** 
+  * @brief  AF 4 selection  
+  */ 
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */
+/** 
+  * @brief  AF 5 selection  
+  */ 
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+/** 
+  * @brief  AF 6 selection  
+  */ 
+#define GPIO_AF_SPI3          ((uint8_t)0x06)  /*!< SPI3 Alternate Function mapping */
+/** 
+  * @brief  AF 7 selection  
+  */ 
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping */
+/** 
+  * @brief  AF 8 selection  
+  */ 
+#define GPIO_AF_UART4         ((uint8_t)0x08)  /*!< UART4 Alternate Function mapping */
+#define GPIO_AF_UART5         ((uint8_t)0x08)  /*!< UART5 Alternate Function mapping */
+/** 
+  * @brief  AF 10 selection  
+  */ 
+#define GPIO_AF_USB           ((uint8_t)0xA)  /*!< USB Full speed device  Alternate Function mapping */
+/** 
+  * @brief  AF 11 selection  
+  */ 
+#define GPIO_AF_LCD           ((uint8_t)0x0B)  /*!< LCD Alternate Function mapping */
+/** 
+  * @brief  AF 12 selection  
+  */ 
+#define GPIO_AF_FSMC           ((uint8_t)0x0C)  /*!< FSMC Alternate Function mapping */
+#define GPIO_AF_SDIO           ((uint8_t)0x0C)  /*!< SDIO Alternate Function mapping */
+/** 
+  * @brief  AF 14 selection  
+  */ 
+#define GPIO_AF_RI            ((uint8_t)0x0E)  /*!< RI Alternate Function mapping */
+
+/** 
+  * @brief  AF 15 selection  
+  */ 
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO)    || \
+                          ((AF) == GPIO_AF_RTC_AF1)  || ((AF) == GPIO_AF_WKUP)   || \
+                          ((AF) == GPIO_AF_SWJ)      || ((AF) == GPIO_AF_TRACE)  || \
+                          ((AF) == GPIO_AF_TIM2)     || ((AF)== GPIO_AF_TIM3)    || \
+                          ((AF) == GPIO_AF_TIM4)     || ((AF)== GPIO_AF_TIM9)    || \
+                          ((AF) == GPIO_AF_TIM10)    || ((AF)== GPIO_AF_TIM11)   || \
+                          ((AF) == GPIO_AF_I2C1)     || ((AF) == GPIO_AF_I2C2)   || \
+                          ((AF) == GPIO_AF_SPI1)     || ((AF) == GPIO_AF_SPI2)   || \
+                          ((AF) == GPIO_AF_USART1)   || ((AF) == GPIO_AF_USART2) || \
+                          ((AF) == GPIO_AF_USART3)   || ((AF) == GPIO_AF_USB)    || \
+                          ((AF) == GPIO_AF_LCD)      || ((AF) == GPIO_AF_RI)     || \
+                          ((AF) == GPIO_AF_TIM5)     || ((AF) == GPIO_AF_SPI3)   || \
+                          ((AF) == GPIO_AF_UART4)    || ((AF) == GPIO_AF_UART5)  || \
+                          ((AF) == GPIO_AF_FSMC)     || ((AF) == GPIO_AF_SDIO)   || \
+                          ((AF) == GPIO_AF_EVENTOUT))
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Legacy 
+  * @{
+  */
+    
+#define GPIO_Mode_AIN GPIO_Mode_AN
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+  
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_GPIO_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
new file mode 100644
index 0000000..6159e4e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
@@ -0,0 +1,703 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_i2c.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_I2C_H
+#define __STM32L1xx_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2))
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_NACK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/**
+ ===============================================================================
+               I2C Master Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *  managed before the current byte end of transfer, then user may check on EV7 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *  In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/**
+ ===============================================================================
+               I2C Slave Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *  managed before the current byte end of transfer, then user may check on EV2 
+  *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *  In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*
+ ===============================================================================
+                          End of Events Description
+ ===============================================================================
+ */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+
+/* PEC management functions ***************************************************/ 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+
+/* Interrupts, events and flags management functions **************************/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/*
+
+ ===============================================================================
+                          I2C State Monitoring Functions
+ ===============================================================================
+  This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+          - When to use
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0038).
+             - It is also suitable for users who need to define their own events.
+
+          - Limitations
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     Note
+         For error management, it is advised to use the following functions:
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+             Where x is the peripheral instance (I2C1, I2C2 ...)
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communciation status.
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          - When to use
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             - The returned value could be compared to events already defined in 
+               the library (stm32l1xx_i2c.h) or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          - Limitations
+             - User may need to define his own events.
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          - When to use
+             - This function could be used for specific applications or in debug 
+               phase.
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             - Function may need to be called twice or more in order to monitor 
+               one single event.
+
+   For detailed description of Events, please refer to section I2C_Events in 
+   stm32l1xx_i2c.h file.
+
+*/
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring
+ ===============================================================================
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/*
+ ===============================================================================
+                          2. Advanced state monitoring
+ ===============================================================================
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring
+ ===============================================================================
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_I2C_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_opamp.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_opamp.h
new file mode 100644
index 0000000..c23135b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_opamp.h
@@ -0,0 +1,187 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_opamp.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the operational
+  *          amplifiers (opamp) firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_OPAMP_H
+#define __STM32L1xx_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup OPAMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup OPAMP_Selection
+  * @{
+  */
+
+#define OPAMP_Selection_OPAMP1                    OPAMP_CSR_OPA1PD
+#define OPAMP_Selection_OPAMP2                    OPAMP_CSR_OPA2PD
+#define OPAMP_Selection_OPAMP3                    OPAMP_CSR_OPA3PD
+
+#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
+                                     ((PERIPH) == OPAMP_Selection_OPAMP2) || \
+                                     ((PERIPH) == OPAMP_Selection_OPAMP3))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup OPAMP_Switches
+  * @{
+  */
+
+/* OPAMP1 Switches */
+#define OPAMP_OPAMP1Switch3           OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */
+#define OPAMP_OPAMP1Switch4           OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */
+#define OPAMP_OPAMP1Switch5           OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */
+#define OPAMP_OPAMP1Switch6           OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */
+#define OPAMP_OPAMP1SwitchANA         OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */
+
+/* OPAMP2 Switches */
+#define OPAMP_OPAMP2Switch3           OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */
+#define OPAMP_OPAMP2Switch4           OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */
+#define OPAMP_OPAMP2Switch5           OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */
+#define OPAMP_OPAMP2Switch6           OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */
+#define OPAMP_OPAMP2Switch7           OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */
+#define OPAMP_OPAMP2SwitchANA         OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */
+
+/* OPAMP3 Switches */
+#define OPAMP_OPAMP3Switch3           OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */
+#define OPAMP_OPAMP3Switch4           OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */
+#define OPAMP_OPAMP3Switch5           OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */
+#define OPAMP_OPAMP3Switch6           OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */
+#define OPAMP_OPAMP3SwitchANA         OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */
+
+#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup OPAMP_Trimming
+  * @{
+  */
+
+#define OPAMP_Trimming_Factory        ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_Trimming_User           OPAMP_OTR_OT_USER /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
+                                     ((TRIMMING) == OPAMP_Trimming_User))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup OPAMP_Input
+  * @{
+  */
+
+#define OPAMP_Input_NMOS              OPAMP_CSR_OPA1CAL_H /*!< NMOS input */
+#define OPAMP_Input_PMOS              OPAMP_CSR_OPA1CAL_L /*!< PMOS input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \
+                               ((INPUT) == OPAMP_Input_PMOS))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup OPAMP_TrimValue
+  * @{
+  */
+
+#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_PowerRange
+  * @{
+  */
+
+#define OPAMP_PowerRange_Low          ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */
+#define OPAMP_PowerRange_High         OPAMP_CSR_AOP_RANGE    /*!< High power range is selected (VDDA is higher than 2.4V) */
+
+#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \
+                               ((RANGE) == OPAMP_PowerRange_High))
+
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Initialization and Configuration functions *********************************/
+void OPAMP_DeInit(void);
+void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);
+
+/* Calibration functions ******************************************************/
+void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_OPAMP_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
new file mode 100644
index 0000000..e6f28a6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_pwr.h
@@ -0,0 +1,213 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_pwr.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_PWR_H
+#define __STM32L1xx_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7 /* External input analog voltage 
+                                                          (Compare internally to VREFINT) */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_WakeUp_Pins 
+  * @{
+  */
+
+#define PWR_WakeUpPin_1                 ((uint32_t)0x00000000)
+#define PWR_WakeUpPin_2                 ((uint32_t)0x00000004)
+#define PWR_WakeUpPin_3                 ((uint32_t)0x00000008)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
+                                ((PIN) == PWR_WakeUpPin_2) || \
+                                ((PIN) == PWR_WakeUpPin_3))
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWR_Voltage_Scaling_Ranges
+  * @{
+  */
+
+#define PWR_VoltageScaling_Range1       PWR_CR_VOS_0
+#define PWR_VoltageScaling_Range2       PWR_CR_VOS_1
+#define PWR_VoltageScaling_Range3       PWR_CR_VOS
+
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
+                                             ((RANGE) == PWR_VoltageScaling_Range2) || \
+                                             ((RANGE) == PWR_VoltageScaling_Range3))
+/**
+  * @}
+  */    
+  
+/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPSDSR
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry 
+  * @{
+  */
+
+#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
+ 
+/**
+  * @}
+  */
+  
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF
+#define PWR_FLAG_VOS                    PWR_CSR_VOSF
+#define PWR_FLAG_REGLP                  PWR_CSR_REGLPF
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
+                               ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* RTC Domain Access function *************************************************/ 
+void PWR_RTCAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/ 
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
+
+/* Ultra Low Power mode configuration functions *******************************/ 
+void PWR_FastWakeUpCmd(FunctionalState NewState);
+void PWR_UltraLowPowerCmd(FunctionalState NewState);
+
+/* Voltage Scaling configuration functions ************************************/ 
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
+
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterLowPowerRunMode(FunctionalState NewState);
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rtc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rtc.h
new file mode 100644
index 0000000..a63d780
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rtc.h
@@ -0,0 +1,896 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_rtc.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the RTC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_RTC_H
+#define __STM32L1xx_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7FFF */ 
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef; 
+
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
+#define RTC_Weekday_Saturday           ((uint8_t)0x06)
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions 
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)  
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)  
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)  
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define RTC_Alarm_B                       ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA) || \
+                               ((OUTPUT) == RTC_Output_AlarmB) || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Coarse_Calibration_Definitions 
+  * @{
+  */ 
+#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
+#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+                                 ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for 
+                                                      input tamper 1 */
+#define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for 
+                                                      input tamper 2 */
+#define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for 
+                                                      input tamper 3 */
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+#define RTC_BKP_DR20                      ((uint32_t)0x00000014)
+#define RTC_BKP_DR21                      ((uint32_t)0x00000015)
+#define RTC_BKP_DR22                      ((uint32_t)0x00000016)
+#define RTC_BKP_DR23                      ((uint32_t)0x00000017)
+#define RTC_BKP_DR24                      ((uint32_t)0x00000018)
+#define RTC_BKP_DR25                      ((uint32_t)0x00000019)
+#define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
+#define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
+#define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
+#define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
+#define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
+#define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
+                                           ((BKP) == RTC_BKP_DR1) || \
+                                           ((BKP) == RTC_BKP_DR2) || \
+                                           ((BKP) == RTC_BKP_DR3) || \
+                                           ((BKP) == RTC_BKP_DR4) || \
+                                           ((BKP) == RTC_BKP_DR5) || \
+                                           ((BKP) == RTC_BKP_DR6) || \
+                                           ((BKP) == RTC_BKP_DR7) || \
+                                           ((BKP) == RTC_BKP_DR8) || \
+                                           ((BKP) == RTC_BKP_DR9) || \
+                                           ((BKP) == RTC_BKP_DR10) || \
+                                           ((BKP) == RTC_BKP_DR11) || \
+                                           ((BKP) == RTC_BKP_DR12) || \
+                                           ((BKP) == RTC_BKP_DR13) || \
+                                           ((BKP) == RTC_BKP_DR14) || \
+                                           ((BKP) == RTC_BKP_DR15) || \
+                                           ((BKP) == RTC_BKP_DR16) || \
+                                           ((BKP) == RTC_BKP_DR17) || \
+                                           ((BKP) == RTC_BKP_DR18) || \
+                                           ((BKP) == RTC_BKP_DR19) || \
+                                           ((BKP) == RTC_BKP_DR20) || \
+                                           ((BKP) == RTC_BKP_DR21) || \
+                                           ((BKP) == RTC_BKP_DR22) || \
+                                           ((BKP) == RTC_BKP_DR23) || \
+                                           ((BKP) == RTC_BKP_DR24) || \
+                                           ((BKP) == RTC_BKP_DR25) || \
+                                           ((BKP) == RTC_BKP_DR26) || \
+                                           ((BKP) == RTC_BKP_DR27) || \
+                                           ((BKP) == RTC_BKP_DR28) || \
+                                           ((BKP) == RTC_BKP_DR29) || \
+                                           ((BKP) == RTC_BKP_DR30) || \
+                                           ((BKP) == RTC_BKP_DR31))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP3F                   ((uint32_t)0x00008000)
+#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
+                                ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                                ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
+#define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
+
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_WUT) || \
+                           ((IT) == RTC_IT_ALRB)  || ((IT) == RTC_IT_ALRA) || \
+                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
+                           ((IT) == RTC_IT_TAMP3))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Legacy 
+  * @{
+  */ 
+#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the RTC configuration to the default reset state *****/ 
+ErrorStatus RTC_DeInit(void);
+
+
+/* Initialization and Configuration functions *********************************/ 
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/ 
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/ 
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/ 
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/ 
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/ 
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Coarse and Smooth Calibration configuration functions **********************/
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/ 
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/ 
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/ 
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* Output Type Config configuration functions *********************************/ 
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/ 
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_RTC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_sdio.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_sdio.h
new file mode 100644
index 0000000..501be5d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_sdio.h
@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_sdio.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_SDIO_H
+#define __STM32L1xx_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                           enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                           disabled when the bus is idle.
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
+                                           This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
+                                This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_soucres 
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type 
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State 
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State 
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers 
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+/*  Function used to set the SDIO configuration to the default reset state ****/
+void SDIO_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+
+/* DMA transfers management functions *****************************************/
+void SDIO_DMACmd(FunctionalState NewState);
+
+/* Command path state machine (CPSM) management functions *********************/
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions ************************/
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+
+/* SDIO IO Cards mode management functions ************************************/
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+
+/* CE-ATA mode management functions *******************************************/
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_SDIO_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
new file mode 100644
index 0000000..d6e0b4b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
@@ -0,0 +1,524 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_spi.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_SPI_H
+#define __STM32L1xx_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref SPI_I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref SPI_I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+  
+
+/** @defgroup SPI_I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+            
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_IT_CRCERR)   || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_OVR)  || ((IT) == I2S_IT_UDR) ||\
+                               ((IT) == SPI_I2S_IT_FRE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_FRE                ((uint16_t)0x0100)
+
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_FRE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Legacy 
+  * @{
+  */
+
+#define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
+#define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
+#define SPI_IT_TXE                   SPI_I2S_IT_TXE
+#define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
+#define SPI_IT_ERR                   SPI_I2S_IT_ERR
+#define SPI_IT_OVR                   SPI_I2S_IT_OVR
+#define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
+#define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
+#define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
+#define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
+#define SPI_DeInit                   SPI_I2S_DeInit
+#define SPI_ITConfig                 SPI_I2S_ITConfig
+#define SPI_DMACmd                   SPI_I2S_DMACmd
+#define SPI_SendData                 SPI_I2S_SendData
+#define SPI_ReceiveData              SPI_I2S_ReceiveData
+#define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
+#define SPI_ClearFlag                SPI_I2S_ClearFlag
+#define SPI_GetITStatus              SPI_I2S_GetITStatus
+#define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the SPI configuration to the default reset state *****/ 
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32L1xx_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
new file mode 100644
index 0000000..9c6b303
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_usart.h
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_USART_H
+#define __STM32L1xx_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
+                               This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
+                               This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4) || \
+                                     ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3))
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @{
+  */
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+/** @defgroup USART_Legacy 
+  * @{
+  */
+#define USART_IT_ORE                          USART_IT_ORE_ER               
+/**
+  * @}
+  */
+
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
+                             ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
+                             ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the USART configuration to the default reset state ***/ 
+void USART_DeInit(USART_TypeDef* USARTx);
+
+/* Initialization and Configuration functions *********************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendBreak(USART_TypeDef* USARTx);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_USART_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c
new file mode 100644
index 0000000..4f0047c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,251 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+/**
+  *
+@verbatim
+ *******************************************************************************
+                   ##### Interrupts configuration functions #####
+ *******************************************************************************
+    [..] This section provide functions allowing to configure the NVIC interrupts 
+         (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
+         (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() 
+             function according to the following table.
+             The table below gives the allowed values of the preemption priority 
+             and subpriority according to the Priority Grouping configuration 
+             performed by NVIC_PriorityGroupConfig function.
+  ============================================================================================================================
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
+  ============================================================================================================================
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for preemption priority
+                         |                                   |                             |   4 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for preemption priority
+                         |                                   |                             |   3 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for preemption priority
+                         |                                   |                             |   2 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for preemption priority
+                         |                                   |                             |   1 bits for subpriority
+  ----------------------------------------------------------------------------------------------------------------------------
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for preemption priority
+                         |                                   |                             |   0 bits for subpriority
+  ============================================================================================================================
+
+
+         (#) Enable and Configure the priority of the selected IRQ Channels.  
+
+        -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
+            the IRQ priority will be managed only by subpriority.
+            The sub-priority is only used to sort pending exception priorities, 
+            and does not affect active exceptions.
+        -@- Lower priority values gives higher priority.
+        -@- Priority Order:
+            (#@) Lowest Preemption priority.
+            (#@) Lowest Subpriority.
+            (#@) Lowest hardware priority (IRQn position).
+  
+@endverbatim
+*/
+
+/**
+  * @brief  Configures the priority grouping: preemption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
+  *                                4 bits for subpriority.
+  *     @note When NVIC_PriorityGroup_0 is selected, it will no be any nested 
+  *           interrupt. This interrupts priority is managed only with subpriority.  
+  *     @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
+  *                                3 bits for subpriority.
+  *     @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
+  *                                2 bits for subpriority.
+  *     @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
+  *                                1 bits for subpriority.
+  *     @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
+  *                                0 bits for subpriority.
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c
new file mode 100644
index 0000000..25bb499
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c
@@ -0,0 +1,1909 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_adc.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
+  *           + Initialization and Configuration
+  *           + Power saving
+  *           + Analog Watchdog configuration
+  *           + Temperature Sensor & Vrefint (Voltage Reference internal) management 
+  *           + Regular Channels Configuration
+  *           + Regular Channels DMA Configuration
+  *           + Injected channels Configuration
+  *           + Interrupts and flags management
+  *         
+  *  @verbatim
+================================================================================
+                      ##### How to use this driver #####
+================================================================================
+    [..]
+    (#) Configure the ADC Prescaler, conversion resolution and data alignment 
+        using the ADC_Init() function.
+    (#) Activate the ADC peripheral using ADC_Cmd() function.
+    
+    *** Regular channels group configuration ***
+    ============================================
+    [..]
+    (+) To configure the ADC regular channels group features, use 
+        ADC_Init() and ADC_RegularChannelConfig() functions.
+    (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+        function.
+    (+) To configurate and activate the Discontinuous mode, use the 
+        ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
+    (+) To read the ADC converted values, use the ADC_GetConversionValue()
+        function.
+  
+    *** DMA for Regular channels group features configuration ***
+    =============================================================
+    [..]
+    (+) To enable the DMA mode for regular channels group, use the 
+               ADC_DMACmd() function.
+    (+) To enable the generation of DMA requests continuously at the end
+               of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() 
+               function.
+             
+    *** Injected channels group configuration ***
+    =============================================
+    [..]
+    (+) To configure the ADC Injected channels group features, use 
+        ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
+        functions.
+    (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+        function.
+    (+) To activate the Injected Discontinuous mode, use the 
+        ADC_InjectedDiscModeCmd() function.
+    (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+        function.
+    (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() 
+        function.
+
+  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_RESET         ((uint32_t)0xFFFF1FFF)
+   
+/* ADC AWDCH mask */
+#define CR1_AWDCH_RESET           ((uint32_t)0xFFFFFFE0) 
+  
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMODE_RESET         ((uint32_t)0xFF3FFDFF)
+  
+/* CR1 register Mask */
+#define CR1_CLEAR_MASK            ((uint32_t)0xFCFFFEFF) 
+   
+/* ADC DELAY mask */            
+#define CR2_DELS_RESET            ((uint32_t)0xFFFFFF0F)
+   
+/* ADC JEXTEN mask */
+#define CR2_JEXTEN_RESET          ((uint32_t)0xFFCFFFFF)
+  
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_RESET         ((uint32_t)0xFFF0FFFF)
+  
+/* CR2 register Mask */
+#define CR2_CLEAR_MASK            ((uint32_t)0xC0FFF7FD)
+
+/* ADC SQx mask */
+#define SQR5_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR4_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR3_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR2_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR1_SQ_SET               ((uint32_t)0x0000001F)
+
+/* ADC L Mask */
+#define SQR1_L_RESET              ((uint32_t)0xFE0FFFFF) 
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_SET              ((uint32_t)0x0000001F) 
+ 
+/* ADC JL mask */
+#define JSQR_JL_SET               ((uint32_t)0x00300000) 
+#define JSQR_JL_RESET             ((uint32_t)0xFFCFFFFF) 
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_SET             ((uint32_t)0x00000007)  
+#define SMPR2_SMP_SET             ((uint32_t)0x00000007)
+#define SMPR3_SMP_SET             ((uint32_t)0x00000007) 
+#define SMPR0_SMP_SET             ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_OFFSET                ((uint8_t)0x30)   
+  
+/* ADC CCR register Mask */
+#define CR_CLEAR_MASK             ((uint32_t)0xFFFCFFFF) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions.
+ *
+@verbatim    
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+        (+) Initialize and configure the ADC Prescaler.
+        (+) ADC Conversion Resolution (12bit..6bit).
+        (+) Scan Conversion Mode (multichannel or one channel) for regular group.
+        (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for 
+            regular group.
+        (+) External trigger Edge and source of regular group.
+        (+) Converted data alignment (left or right).
+        (+) The number of ADC conversions that will be done using the sequencer 
+            for regular channel group.
+        (+) Enable or disable the ADC peripheral.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  if(ADCx == ADC1)
+  {
+    /* Enable ADC1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+    /* Release ADC1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters
+  *         in the ADC_InitStruct.
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains 
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)               
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); 
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); 
+  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); 
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));    
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
+  
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear RES and SCAN bits */ 
+  tmpreg1 &= CR1_CLEAR_MASK;
+  /* Configure ADCx: scan conversion mode and resolution */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  /* Set RES bit according to ADC_Resolution value */ 
+  tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+  
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
+  tmpreg1 &= CR2_CLEAR_MASK;
+  /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ 
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 
+              ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+  
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  /* Clear L bits */
+  tmpreg1 &= SQR1_L_RESET;
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfConversion value */ 
+  tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
+  tmpreg1 |= ((uint32_t)tmpreg2 << 20);
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @note   This function is used to initialize the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)                            
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Resolution member */
+  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+
+  /* Initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+  /* Initialize the ADC_ExternalTrigConvEdge member */
+  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;
+
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+  /* Initialize the ADC_NbrOfConversion member */
+  ADC_InitStruct->ADC_NbrOfConversion = 1;
+}
+
+/**
+  * @brief  Initializes the ADCs peripherals according to the specified parameters
+  *          in the ADC_CommonInitStruct.
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure 
+  *         that contains the configuration information (Prescaler) for ADC1 peripheral.
+  * @retval None
+  */
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)                           
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
+
+  /*---------------------------- ADC CCR Configuration -----------------*/
+  /* Get the ADC CCR value */
+  tmpreg = ADC->CCR;
+
+  /* Clear ADCPRE bit */ 
+  tmpreg &= CR_CLEAR_MASK;
+  
+  /* Configure ADCx: ADC prescaler according to ADC_Prescaler */                
+  tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler);        
+                
+  /* Write to ADC CCR */
+  ADC->CCR = tmpreg;
+}
+
+/**
+  * @brief  Fills each ADC_CommonInitStruct member with its default value.
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)                      
+{
+  /* Reset ADC init structure parameters values */
+  /* Initialize the ADC_Prescaler member */
+  ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the ADCx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
+  }
+}
+
+/**
+  * @brief  Selects the specified ADC Channels Bank.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_Bank: ADC Channels Bank.
+  *     @arg ADC_Bank_A: ADC Channels Bank A.
+  *     @arg ADC_Bank_B: ADC Channels Bank B.
+  * @retval None
+  */
+void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_BANK(ADC_Bank));
+
+  if (ADC_Bank != ADC_Bank_A)
+  {
+    /* Set the ADC_CFG bit to select the ADC Bank B channels */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_CFG;
+  }
+  else
+  {
+    /* Reset the ADC_CFG bit to select the ADC Bank A channels */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_CFG);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 Power saving functions
+ *  @brief   Power saving functions 
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Power saving functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to reduce power consumption.
+    [..] The two function must be combined to get the maximal benefits:
+         When the ADC frequency is higher than the CPU one, it is recommended to:
+         (#) Insert a freeze delay :
+             ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze).
+         (#) Enable the power down in Idle and Delay phases :
+             ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the ADC Power Down during Delay and/or Idle phase.
+  * @note   ADC power-on and power-off can be managed by hardware to cut the 
+  *         consumption when the ADC is not converting.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_PowerDown: The ADC power down configuration.
+  *         This parameter can be one of the following values:
+  *     @arg ADC_PowerDown_Delay:      ADC is powered down during delay phase.
+  *     @arg ADC_PowerDown_Idle:       ADC is powered down during Idle phase.
+  *     @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases.
+  * @note   The ADC can be powered down:
+  * @note   During the hardware delay insertion (using the ADC_PowerDown_Delay
+  *           parameter).
+  *           => The ADC is powered up again at the end of the delay.
+  * @note   During the ADC is waiting for a trigger event ( using the 
+  *           ADC_PowerDown_Idle parameter).
+  *           => The ADC is powered up at the next trigger event.
+  * @note   During the hardware delay insertion or the ADC is waiting for a 
+  *           trigger event (using the ADC_PowerDown_Idle_Delay parameter).
+  *            => The ADC is powered up only at the end of the delay and at the
+  *              next trigger event.
+  * @param  NewState: new state of the ADCx power down.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the ADC power-down during Delay and/or Idle phase */
+    ADCx->CR1 |= ADC_PowerDown;
+  }
+  else
+  {
+    /* Disable The ADC power-down during Delay and/or Idle phase */
+    ADCx->CR1 &= (uint32_t)~ADC_PowerDown;
+  }
+}
+
+/**
+  * @brief  Defines the length of the delay which is applied after a conversion 
+  *         or a sequence of conversion.
+  * @note   When the CPU clock is not fast enough to manage the data rate, a 
+  *         Hardware delay can be introduced between ADC conversions to reduce 
+  *         this data rate.
+  * @note   The Hardware delay is inserted after :
+  *         - each regular conversion.
+  *         - after each sequence of injected conversions.
+  * @note   No Hardware delay is inserted between conversions of different groups.
+  * @note   When the hardware delay is not enough, the Freeze Delay Mode can be 
+  *         selected and a new conversion can start only if all the previous data 
+  *         of the same group have been treated:
+  *         - for a regular conversion: once the ADC conversion data register has 
+  *           been read (using ADC_GetConversionValue() function) or if the EOC 
+  *           Flag has been cleared (using ADC_ClearFlag() function).
+  *         - for an injected conversion: when the JEOC bit has been cleared 
+  *           (using ADC_ClearFlag() function).
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_DelayLength: The length of delay which is applied after a 
+  *         conversion or a sequence of conversion. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_DelayLength_None: No delay.
+  *     @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.
+  *     @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles.
+  *     @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles	
+  *     @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles	
+  *     @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles	
+  *     @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles	
+  *     @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles	
+  * @retval None
+  */
+void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)
+{
+  uint32_t tmpreg = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));
+
+  /* Get the old register value */    
+  tmpreg = ADCx->CR2;
+  /* Clear the old delay length */
+  tmpreg &= CR2_DELS_RESET;
+  /* Set the delay length */
+  tmpreg |= ADC_DelayLength;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group3 Analog Watchdog configuration functions
+ *  @brief   Analog Watchdog configuration functions. 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Analog Watchdog configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the Analog Watchdog
+         (AWD) feature in the ADC.
+    [..] A typical configuration Analog Watchdog is done following these steps :
+         (#) the ADC guarded channel(s) is (are) selected using the 
+             ADC_AnalogWatchdogSingleChannelConfig() function.
+         (#) The Analog watchdog lower and higher threshold are configured using 
+             the ADC_AnalogWatchdogThresholdsConfig() function.
+         (#) The Analog watchdog is enabled and configured to enable the check, 
+             on one or more channels, using the  ADC_AnalogWatchdogCmd() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular
+  *         or injected channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single 
+  *          regular channel.
+  *     @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single 
+  *          injected channel.
+  *     @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a 
+  *          single regular or injected channel.
+  *     @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular 
+  *          channel.
+  *     @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected 
+  *          channel.
+  *     @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all 
+  *           regular and injected channels.
+  *     @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog.
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear AWDEN, JAWDEN and AWDSGL bits */   
+  tmpreg &= CR1_AWDMODE_RESET;
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *         This parameter must be a 12bit value.
+  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
+  *         This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  *     @arg ADC_Channel_18: ADC Channel18 selected
+  *     @arg ADC_Channel_19: ADC Channel19 selected
+  *     @arg ADC_Channel_20: ADC Channel20 selected
+  *     @arg ADC_Channel_21: ADC Channel21 selected
+  *     @arg ADC_Channel_22: ADC Channel22 selected
+  *     @arg ADC_Channel_23: ADC Channel23 selected
+  *     @arg ADC_Channel_24: ADC Channel24 selected
+  *     @arg ADC_Channel_25: ADC Channel25 selected
+  *     @arg ADC_Channel_27: ADC Channel27 selected
+  *     @arg ADC_Channel_28: ADC Channel28 selected
+  *     @arg ADC_Channel_29: ADC Channel29 selected
+  *     @arg ADC_Channel_30: ADC Channel30 selected
+  *     @arg ADC_Channel_31: ADC Channel31 selected
+  *     @arg ADC_Channel_0b: ADC Channel0b selected
+  *     @arg ADC_Channel_1b: ADC Channel1b selected
+  *     @arg ADC_Channel_2b: ADC Channel2b selected
+  *     @arg ADC_Channel_3b: ADC Channel3b selected
+  *     @arg ADC_Channel_6b: ADC Channel6b selected
+  *     @arg ADC_Channel_7b: ADC Channel7b selected
+  *     @arg ADC_Channel_8b: ADC Channel8b selected
+  *     @arg ADC_Channel_9b: ADC Channel9b selected
+  *     @arg ADC_Channel_10b: ADC Channel10b selected
+  *     @arg ADC_Channel_11b: ADC Channel11b selected
+  *     @arg ADC_Channel_12b: ADC Channel12b selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_RESET;
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function
+ *  @brief   Temperature Sensor & Vrefint (Voltage Reference internal) management function.
+ *
+@verbatim   
+ =========================================================================================
+ ##### Temperature Sensor and Vrefint (Voltage Reference internal) management function #####
+ =========================================================================================
+    [..] This section provides a function allowing to enable/ disable the internal 
+         connections between the ADC and the Temperature Sensor and the Vrefint 
+         source.
+    [..] A typical configuration to get the Temperature sensor and Vrefint channels 
+         voltages is done following these steps :
+         (#) Enable the internal connection of Temperature sensor and Vrefint sources 
+             with the ADC channels using ADC_TempSensorVrefintCmd() function.
+         (#) select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using 
+             ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions.
+         (#) Get the voltage values, using ADC_GetConversionValue() or 
+             ADC_GetInjectedConversionValue().
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channel.
+  * @param  NewState: new state of the temperature sensor and Vref int channels.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)                
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group5 Regular Channels Configuration functions
+ *  @brief   Regular Channels Configuration functions.
+ *
+@verbatim   
+ ===============================================================================
+            ##### Regular Channels Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to manage the ADC regular channels,
+         it is composed of 2 sub sections :
+         (#) Configuration and management functions for regular channels: This 
+             subsection provides functions allowing to configure the ADC regular 
+             channels :
+             (++) Configure the rank in the regular group sequencer for each channel.
+             (++) Configure the sampling time for each channel.
+             (++) select the conversion Trigger for regular channels.
+             (++) select the desired EOC event behavior configuration.
+             (++) Activate the continuous Mode  (*).
+             (++) Activate the Discontinuous Mode.
+             -@@- Please Note that the following features for regular channels are 
+                  configurated using the ADC_Init() function : 
+                  (+@@) scan mode activation.
+                  (+@@) continuous mode activation (**).
+                  (+@@) External trigger source.
+                  (+@@) External trigger edge.
+                  (+@@) number of conversion in the regular channels group sequencer.
+             -@@- (*) and (**) are performing the same configuration.
+         (#) Get the conversion data: This subsection provides an important function 
+             in the ADC peripheral since it returns the converted data of the current 
+             regular channel. When the Conversion value is read, the EOC Flag is 
+             automatically cleared.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sampling time.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  *     @arg ADC_Channel_18: ADC Channel18 selected 
+  *     @arg ADC_Channel_19: ADC Channel19 selected
+  *     @arg ADC_Channel_20: ADC Channel20 selected
+  *     @arg ADC_Channel_21: ADC Channel21 selected
+  *     @arg ADC_Channel_22: ADC Channel22 selected
+  *     @arg ADC_Channel_23: ADC Channel23 selected
+  *     @arg ADC_Channel_24: ADC Channel24 selected
+  *     @arg ADC_Channel_25: ADC Channel25 selected
+  *     @arg ADC_Channel_27: ADC Channel27 selected
+  *     @arg ADC_Channel_28: ADC Channel28 selected
+  *     @arg ADC_Channel_29: ADC Channel29 selected
+  *     @arg ADC_Channel_30: ADC Channel30 selected
+  *     @arg ADC_Channel_31: ADC Channel31 selected 
+  *     @arg ADC_Channel_0b: ADC Channel0b selected
+  *     @arg ADC_Channel_1b: ADC Channel1b selected
+  *     @arg ADC_Channel_2b: ADC Channel2b selected
+  *     @arg ADC_Channel_3b: ADC Channel3b selected
+  *     @arg ADC_Channel_6b: ADC Channel6b selected
+  *     @arg ADC_Channel_7b: ADC Channel7b selected
+  *     @arg ADC_Channel_8b: ADC Channel8b selected
+  *     @arg ADC_Channel_9b: ADC Channel9b selected
+  *     @arg ADC_Channel_10b: ADC Channel10b selected
+  *     @arg ADC_Channel_11b: ADC Channel11b selected
+  *     @arg ADC_Channel_12b: ADC Channel12b selected   
+  * @param  Rank: The rank in the regular group sequencer. This parameter
+  *               must be between 1 to 28.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected 
+  *         channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
+  *     @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
+  *     @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
+  *     @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles	
+  *     @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles	
+  *     @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles	
+  *     @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles	
+  *     @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+
+  /* If ADC_Channel_30 or ADC_Channel_31 is selected */
+  if (ADC_Channel > ADC_Channel_29)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR0;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR0 = tmpreg1;
+  }
+  /* If ADC_Channel_20 ... ADC_Channel_29 is selected */
+  else if (ADC_Channel > ADC_Channel_19)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  /* If ADC_Channel_10 ... ADC_Channel_19 is selected */
+  else if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR3 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR5;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR5 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR4;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR4 = tmpreg1;
+  }  
+  /* For Rank 13 to 18 */
+  else if (Rank < 19)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+    
+  /* For Rank 19 to 24 */
+  else if (Rank < 25)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }   
+  
+  /* For Rank 25 to 28 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the regular channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Enable the selected ADC conversion for regular group */
+  ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+}
+
+/**
+  * @brief  Gets the selected ADC Software start regular conversion Status.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the EOC on each regular channel conversion.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC EOC flag rising
+  *    This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC EOC rising on each regular channel conversion */
+    ADCx->CR2 |= ADC_CR2_EOCS;
+  }
+  else
+  {
+    /* Disable the selected ADC EOC rising on each regular channel conversion */
+    ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC continuous conversion mode.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC continuous conversion mode.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC continuous conversion mode */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
+  }
+  else
+  {
+    /* Disable the selected ADC continuous conversion mode */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
+  }
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular
+  *         group channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel count value.
+  *         This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_RESET;
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group
+  *         channel for the specified ADC.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode on regular 
+  *         group channel.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions
+ *  @brief   Regular Channels DMA Configuration functions.
+ *
+@verbatim   
+ ===============================================================================
+          ##### Regular Channels DMA Configuration functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the DMA for ADC regular 
+         channels.Since converted regular channel values are stored into a unique 
+         data register, it is useful to use DMA for conversion of more than one 
+         regular channel. This avoids the loss of the data already stored in the 
+         ADC Data register.
+         When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+         conversion of a regular channel, a DMA request is generated.
+    [..] Depending on the "DMA disable selection" configuration (using the 
+         ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA 
+         transfer, two possibilities are allowed:
+         (+) No new DMA request is issued to the DMA controller (feature DISABLED).
+         (+) Requests can continue to be generated (feature ENABLED).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_DMA_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode).
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC EOC flag rising
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request after last transfer */
+    ADCx->CR2 |= ADC_CR2_DDS;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request after last transfer */
+    ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group7 Injected channels Configuration functions
+ *  @brief   Injected channels Configuration functions.
+ *
+@verbatim   
+ ===============================================================================
+            ##### Injected channels Configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the ADC Injected channels,
+         it is composed of 2 sub sections : 
+         (#) Configuration functions for Injected channels: This subsection provides 
+             functions allowing to configure the ADC injected channels :
+             (++) Configure the rank in the injected group sequencer for each channel.
+             (++) Configure the sampling time for each channel.
+             (++) Activate the Auto injected Mode.
+             (++) Activate the Discontinuous Mode.
+             (++) scan mode activation.
+             (++) External/software trigger source.
+             (++) External trigger edge.
+             (++) injected channels sequencer.
+    
+         (#) Get the Specified Injected channel conversion data: This subsection 
+             provides an important function in the ADC peripheral since it returns 
+             the converted data of the specific injected channel.
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_Channel: the ADC channel to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_Channel_0: ADC Channel0 selected
+  *     @arg ADC_Channel_1: ADC Channel1 selected
+  *     @arg ADC_Channel_2: ADC Channel2 selected
+  *     @arg ADC_Channel_3: ADC Channel3 selected
+  *     @arg ADC_Channel_4: ADC Channel4 selected
+  *     @arg ADC_Channel_5: ADC Channel5 selected
+  *     @arg ADC_Channel_6: ADC Channel6 selected
+  *     @arg ADC_Channel_7: ADC Channel7 selected
+  *     @arg ADC_Channel_8: ADC Channel8 selected
+  *     @arg ADC_Channel_9: ADC Channel9 selected
+  *     @arg ADC_Channel_10: ADC Channel10 selected
+  *     @arg ADC_Channel_11: ADC Channel11 selected
+  *     @arg ADC_Channel_12: ADC Channel12 selected
+  *     @arg ADC_Channel_13: ADC Channel13 selected
+  *     @arg ADC_Channel_14: ADC Channel14 selected
+  *     @arg ADC_Channel_15: ADC Channel15 selected
+  *     @arg ADC_Channel_16: ADC Channel16 selected
+  *     @arg ADC_Channel_17: ADC Channel17 selected
+  *     @arg ADC_Channel_18: ADC Channel18 selected 
+  *     @arg ADC_Channel_19: ADC Channel19 selected
+  *     @arg ADC_Channel_20: ADC Channel20 selected
+  *     @arg ADC_Channel_21: ADC Channel21 selected
+  *     @arg ADC_Channel_22: ADC Channel22 selected
+  *     @arg ADC_Channel_23: ADC Channel23 selected
+  *     @arg ADC_Channel_24: ADC Channel24 selected
+  *     @arg ADC_Channel_25: ADC Channel25 selected
+  *     @arg ADC_Channel_27: ADC Channel27 selected
+  *     @arg ADC_Channel_28: ADC Channel28 selected
+  *     @arg ADC_Channel_29: ADC Channel29 selected
+  *     @arg ADC_Channel_30: ADC Channel30 selected
+  *     @arg ADC_Channel_31: ADC Channel31 selected 
+  *     @arg ADC_Channel_0b: ADC Channel0b selected
+  *     @arg ADC_Channel_1b: ADC Channel1b selected
+  *     @arg ADC_Channel_2b: ADC Channel2b selected
+  *     @arg ADC_Channel_3b: ADC Channel3b selected
+  *     @arg ADC_Channel_6b: ADC Channel6b selected
+  *     @arg ADC_Channel_7b: ADC Channel7b selected
+  *     @arg ADC_Channel_8b: ADC Channel8b selected
+  *     @arg ADC_Channel_9b: ADC Channel9b selected
+  *     @arg ADC_Channel_10b: ADC Channel10b selected
+  *     @arg ADC_Channel_11b: ADC Channel11b selected
+  *     @arg ADC_Channel_12b: ADC Channel12b selected   
+  * @param  Rank: The rank in the injected group sequencer. This parameter
+  *         must be between 1 to 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected 
+  *         channel. This parameter can be one of the following values:
+  *     @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
+  *     @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
+  *     @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
+  *     @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles	
+  *     @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles	
+  *     @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles	
+  *     @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles	
+  *     @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  
+  /* If ADC_Channel_30 or ADC_Channel_31 is selected */
+  if (ADC_Channel > ADC_Channel_29)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR0;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR0_SMP_SET << (3 * (ADC_Channel - 30));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 30));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR0 = tmpreg1;
+  }
+  /* If ADC_Channel_20 ... ADC_Channel_29 is selected */
+  else if (ADC_Channel > ADC_Channel_19)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }  
+  /* If ADC_Channel_10 ... ADC_Channel_19 is selected */
+  else if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR3;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR3 = tmpreg1;
+  }
+  
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JL_SET)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ 
+  tmpreg2 = (uint32_t)(JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ 
+  tmpreg2 = (uint32_t)(((uint32_t)(ADC_Channel)) << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  Length: The sequencer length.
+  *         This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Clear the old injected sequence length JL bits */
+  tmpreg1 &= JSQR_JL_RESET;
+  /* Set the injected sequence length JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected.
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected.
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected.
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected.
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *         This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));  
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+  *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected 
+  *    conversion. This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected 
+  *     @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected 
+  *     @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
+  *     @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
+  *     @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
+  *     @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected 
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected 
+  *     @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
+  *     @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected
+  *     @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected
+  *     @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_RESET;
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADCx external trigger edge for injected channels conversion.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger
+  *         edge to start injected conversion.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for 
+  *          injected conversion.
+  *     @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge
+  *     @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge
+  *     @arg ADC_ExternalTrigConvEdge_RisingFalling: detection on 
+  *          both rising and falling edge
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
+
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external trigger edge for injected group */
+  tmpreg &= CR2_JEXTEN_RESET;
+  /* Set the new external trigger edge for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConvEdge;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the injected 
+  *         channels.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC conversion for injected group */
+  ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC auto injected
+  *         conversion.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group
+  *         channel for the specified ADC.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode
+  *         on injected group channel. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *     @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *     @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *     @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDR_OFFSET;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group8 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions.
+ *
+@verbatim   
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the ADC Interrupts 
+         and get the status and clear flags and Interrupts pending bits.
+  
+    [..] The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 
+         3 groups:
+  *** Flags and Interrupts for ADC regular channels ***
+  =====================================================
+    [..]
+        (+)Flags :
+           (##) ADC_FLAG_OVR : Overrun detection when regular converted data are 
+                lost.
+           (##) ADC_FLAG_EOC : Regular channel end of conversion + to indicate 
+                (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
+                the end of :
+                (+++) a regular CHANNEL conversion.
+                (+++) sequence of regular GROUP conversions.
+
+
+           (##) ADC_FLAG_STRT: Regular channel start + to indicate when regular 
+                CHANNEL conversion starts.
+           (##) ADC_FLAG_RCNR: Regular channel not ready + to indicate if a new 
+                regular conversion can be launched.
+        (+)Interrupts :
+           (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection 
+                event.
+           (##) ADC_IT_EOC : specifies the interrupt source for Regular channel 
+                end of conversion event.
+  
+  *** Flags and Interrupts for ADC Injected channels ***
+  ======================================================
+        (+)Flags :
+           (##) ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at 
+                the end of injected GROUP conversion.
+           (##) ADC_FLAG_JSTRT: Injected channel start +  to indicate hardware when 
+                injected GROUP conversion starts.
+           (##) ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new 
+                injected conversion can be launched.
+        (+)Interrupts 
+           (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel 
+                end of conversion event.
+  *** General Flags and Interrupts for the ADC ***
+  ================================================
+        (+)Flags :
+           (##) ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage 
+                crosses the programmed thresholds values.
+           (##) ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready 
+                to convert.
+        (+)Interrupts :
+           (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog 
+                event.
+  
+    [..] The user should identify which mode will be used in his application to 
+         manage the ADC controller events: Polling mode or Interrupt mode.
+  
+    [..] In the Polling Mode it is advised to use the following functions:
+         (+) ADC_GetFlagStatus() : to check if flags events occur.
+         (+) ADC_ClearFlag()     : to clear the flags events.
+  
+    [..] In the Interrupt Mode it is advised to use the following functions:
+         (+) ADC_ITConfig()       : to enable or disable the interrupt source.
+         (+) ADC_GetITStatus()    : to check if Interrupt occurs.
+         (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+             (corresponding Flag).
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt
+  *     @arg ADC_IT_OVR: overrun interrupt
+  * @param  NewState: new state of the specified ADC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)  
+{
+  uint32_t itmask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT)); 
+
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  itmask = (uint32_t)0x01 << itmask;    
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  *     @arg ADC_FLAG_OVR: Overrun flag
+  *     @arg ADC_FLAG_ADONS: ADC ON status
+  *     @arg ADC_FLAG_RCNR: Regular channel not ready
+  *     @arg ADC_FLAG_JCNR: Injected channel not ready
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ADC_FLAG_AWD: Analog watchdog flag
+  *     @arg ADC_FLAG_EOC: End of conversion flag
+  *     @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *     @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *     @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  *     @arg ADC_FLAG_OVR: overrun flag
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt
+  *     @arg ADC_IT_OVR: Overrun interrupt
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (uint32_t)((uint32_t)ADC_IT >> 8);
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); 
+
+  /* Check the status of the specified ADC interrupt */
+  if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {                                                         
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *   This parameter can be one of the following values:
+  *     @arg ADC_IT_EOC: End of conversion interrupt
+  *     @arg ADC_IT_AWD: Analog watchdog interrupt
+  *     @arg ADC_IT_JEOC: End of injected conversion interrupt
+  *     @arg ADC_IT_OVR: Overrun interrupt
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT)); 
+
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes.c
new file mode 100644
index 0000000..7728543
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes.c
@@ -0,0 +1,599 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_aes.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the AES peripheral:           
+  *           + Configuration
+  *           + Read/Write operations
+  *           + DMA transfers management  
+  *           + Interrupts and flags management
+  * 
+  *  @verbatim
+ ===============================================================================
+                        ##### AES Peripheral features #####
+ ===============================================================================
+....[..]
+   (#) The Advanced Encryption Standard hardware accelerator (AES) can be used
+       to both encipher and decipher data using AES algorithm.
+   (#) The AES supports 4 operation modes:
+       (++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
+       (++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
+       (++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
+       (++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
+   (#) Moreover 3 chaining modes are supported:
+       (++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
+       (++) Cipher block chaining (CBC): Each block is XORed with the previous block
+       (++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
+          plain text to give the cipher text
+  (#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
+  (#) The AES peripheral supports write/read error handling with interrupt capability.
+  (#) Automatic data flow control with support of direct memory access (DMA) using
+      2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
+      (DMA2 Channel3).
+
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) AES AHB clock must be enabled to get write access to AES registers 
+            using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
+        (#) Initialize the key using AES_KeyInit().
+        (#) Configure the AES operation mode using AES_Init().
+        (#) If required, enable interrupt source using AES_ITConfig() and
+            enable the AES interrupt vector using NVIC_Init().
+        (#) If required, when using the DMA mode.
+            (##) Configure the DMA using DMA_Init().
+            (##) Enable DMA requests using AES_DMAConfig().
+        (#) Enable the AES peripheral using AES_Cmd().
+    @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_aes.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup AES 
+  * @brief AES driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CR_CLEAR_MASK  ((uint32_t)0xFFFFFF81)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup AES_Private_Functions
+  * @{
+  */
+
+/** @defgroup AES_Group1 Initialization and configuration
+ *  @brief   Initialization and configuration.
+ *
+@verbatim
+ ===============================================================================
+                ##### Initialization and configuration #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */  
+
+  /**
+  * @brief  Deinitializes AES peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void AES_DeInit(void)
+{
+  /* Enable AES reset state */
+  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
+  /* Release AES from reset state */
+  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
+}
+
+/**
+  * @brief  Initializes the AES peripheral according to the specified parameters
+  *         in the AES_InitStruct:
+  *           - AES_Operation: specifies the operation mode (encryption, decryption...).
+  *           - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
+  *           - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
+  * @note   If AES is already enabled, use AES_Cmd(DISABLE) before setting the new 
+  *         configuration (When AES is enabled, setting configuration is forbidden).
+  * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure that contains 
+  *         the configuration information for AES peripheral.
+  * @retval None
+  */
+void AES_Init(AES_InitTypeDef* AES_InitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
+  assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
+  assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));
+
+  /* Get AES CR register value */
+  tmpreg = AES->CR;
+  
+  /* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
+  tmpreg &= (uint32_t)CR_CLEAR_MASK;
+  
+  tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);
+
+  AES->CR = (uint32_t) tmpreg;
+}
+
+/**
+  * @brief  Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
+  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
+  *         contains the configuration information for the specified AES Keys.
+  * @note   This function must be called while the AES is disabled.
+  * @note   In encryption, key derivation and key derivation + decryption modes,
+  *         AES_KeyInitStruct must contain the encryption key.
+  *         In decryption mode, AES_KeyInitStruct must contain the decryption key.
+  * @retval None
+  */
+void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
+{
+  AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
+  AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
+  AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
+  AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
+}
+
+/**
+  * @brief  Initializes the AES Initialization Vector IV according to 
+  *         the specified parameters in the AES_IVInitStruct.
+  * @param  AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
+  *         contains the configuration information for the specified AES IV.
+  * @note   When ECB chaining mode is selected, Initialization Vector IV has no
+  *         meaning.
+  *         When CTR chaining mode is selected, AES_IV0 contains the CTR value.
+  *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
+  * @retval None
+  */
+void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
+{
+  AES->IVR0 = AES_IVInitStruct->AES_IV0;
+  AES->IVR1 = AES_IVInitStruct->AES_IV1;
+  AES->IVR2 = AES_IVInitStruct->AES_IV2;
+  AES->IVR3 = AES_IVInitStruct->AES_IV3;
+}
+
+/**
+  * @brief  Enable or disable the AES peripheral.
+  * @param  NewState: new state of the AES peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   The key must be written while AES is disabled.
+  * @retval None
+  */
+void AES_Cmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the AES peripheral */
+    AES->CR |= (uint32_t) AES_CR_EN;   /**< AES Enable */
+  }
+  else
+  {
+    /* Disable the AES peripheral */
+    AES->CR &= (uint32_t)(~AES_CR_EN);  /**< AES Disable */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group2 Structures initialization functions
+ *  @brief   Structures initialization.
+ *
+@verbatim
+ ===============================================================================
+              ##### Structures initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Fills each AES_InitStruct member with its default value.
+  * @param  AES_InitStruct: pointer to an AES_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
+{
+  AES_InitStruct->AES_Operation = AES_Operation_Encryp;
+  AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
+  AES_InitStruct->AES_DataType = AES_DataType_32b;
+}
+
+/**
+  * @brief  Fills each AES_KeyInitStruct member with its default value.
+  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which 
+  *         will be initialized.
+  * @retval None
+  */
+void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
+{
+  AES_KeyInitStruct->AES_Key0 = 0x00000000;
+  AES_KeyInitStruct->AES_Key1 = 0x00000000;
+  AES_KeyInitStruct->AES_Key2 = 0x00000000;
+  AES_KeyInitStruct->AES_Key3 = 0x00000000;
+}
+
+/**
+  * @brief  Fills each AES_IVInitStruct member with its default value.
+  * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
+{
+  AES_IVInitStruct->AES_IV0 = 0x00000000;
+  AES_IVInitStruct->AES_IV1 = 0x00000000;
+  AES_IVInitStruct->AES_IV2 = 0x00000000;
+  AES_IVInitStruct->AES_IV3 = 0x00000000;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group3 AES Read and Write
+ *  @brief   AES Read and Write.
+ *
+@verbatim
+ ===============================================================================
+                  ##### AES Read and Write functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write data in DINR register to be processed by AES peripheral.
+  * @note   To process 128-bit data (4 * 32-bit), this function must be called
+  *         four times to write the 128-bit data in the 32-bit register DINR.
+  * @note   When an unexpected write to DOUTR register is detected, WRERR flag is
+  *         set.
+  * @param  Data: The data to be processed.
+  * @retval None
+  */
+void AES_WriteSubData(uint32_t Data)
+{
+  /* Write Data */
+  AES->DINR = Data;
+}
+
+/**
+  * @brief  Returns the data in DOUTR register processed by AES peripheral.
+  * @note   This function must be called four times to get the 128-bit data.
+  * @note   When an unexpected read of DINR register is detected, RDERR flag is
+  *         set.
+  * @retval The processed data.
+  */
+uint32_t AES_ReadSubData(void)
+{
+  /* Read Data */
+  return AES->DOUTR;
+}
+
+/**
+  * @brief  Read the Key value.
+  * @param  AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
+  *         will contain the key.
+  * @note   When the key derivation mode is selected, AES must be disabled
+  *         (AES_Cmd(DISABLE)) before reading the decryption key.
+  *         Reading the key while the AES is enabled will return unpredictable
+  *         value.
+  * @retval None
+  */
+void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
+{
+  AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
+  AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
+  AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
+  AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
+}
+
+/**
+  * @brief  Read the Initialization Vector IV value.
+  * @param  AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
+  *         will contain the Initialization Vector IV.
+  * @note   When the AES is enabled Reading the Initialization Vector IV value
+  *         will return 0. The AES must be disabled using AES_Cmd(DISABLE)
+  *         to get the right value.
+  * @note   When ECB chaining mode is selected, Initialization Vector IV has no
+  *         meaning.
+  *         When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
+  *         AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
+  * @retval None
+  */
+void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
+{
+  AES_IVInitStruct->AES_IV0 = AES->IVR0;
+  AES_IVInitStruct->AES_IV1 = AES->IVR1;
+  AES_IVInitStruct->AES_IV2 = AES->IVR2;
+  AES_IVInitStruct->AES_IV3 = AES->IVR3;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management function.
+ *
+@verbatim
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the AES DMA interface.
+  * @param  AES_DMATransfer: Specifies the AES DMA transfer.
+  *   This parameter can be one of the following values:
+  *     @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
+  *     @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
+  *     @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
+  * @param  NewState Indicates the new state of the AES DMA interface.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @note   The DMA has no action in key derivation mode.
+  * @retval None
+  */
+void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer */
+    AES->CR |= (uint32_t) AES_DMATransfer;
+  }
+  else
+  {
+    /* Disable the DMA transfer */
+    AES->CR &= (uint32_t)(~AES_DMATransfer);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions.
+ *
+@verbatim
+
+ ===============================================================================
+           ##### Interrupts and flags management functions #####
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified AES interrupt.
+  * @param  AES_IT: Specifies the AES interrupt source to enable/disable.
+  *     This parameter can be any combinations of the following values:
+  *     @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF 
+  *                     flag is set an interrupt is generated.
+  *     @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
+  *                      flags (RDERR) or write error flag (WRERR) is set,
+  *                      an interrupt is generated.
+  * @param  NewState: The new state of the AES interrupt source.
+  *                   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_AES_IT(AES_IT));
+
+  if (NewState != DISABLE)
+  {
+    AES->CR |= (uint32_t) AES_IT;    /**< AES_IT Enable */
+  }
+  else
+  {
+    AES->CR &= (uint32_t)(~AES_IT);  /**< AES_IT Disable */
+  }
+}
+
+/**
+  * @brief  Checks whether the specified AES flag is set or not.
+  * @param  AES_FLAG specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
+  *                        he computation phase is completed.
+  *     @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
+  *                          operation of DOUTR register is detected.
+  *     @arg AES_FLAG_WRERR: Write Error Flag  is set when an unexpected write
+  *                          operation in DINR is detected.
+  * @retval FlagStatus (SET or RESET)
+  */
+FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check parameters */
+  assert_param(IS_AES_FLAG(AES_FLAG));
+
+  if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+    
+  /* Return the AES_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the AES flags.
+  * @param  AES_FLAG: specifies the flag to clear.
+  *         This parameter can be:
+  *     @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
+  *                        bit in CR register.
+  *     @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in 
+  *                          CR register.
+  *     @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
+  *                          CR register.
+  * @retval None
+  */
+void AES_ClearFlag(uint32_t AES_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_AES_FLAG(AES_FLAG));
+
+  /* Check if AES_FLAG is AES_FLAG_CCF */
+  if (AES_FLAG == AES_FLAG_CCF)
+  {
+    /* Clear CCF flag by setting CCFC bit */
+    AES->CR |= (uint32_t) AES_CR_CCFC;
+  }
+  else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
+  {
+    /* Clear RDERR and WRERR flags by setting ERRC bit */
+    AES->CR |= (uint32_t) AES_CR_ERRC;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified AES interrupt has occurred or not.
+  * @param  AES_IT: Specifies the AES interrupt pending bit to check.
+  *         This parameter can be:
+  *     @arg AES_IT_CC: Computation Complete Interrupt.
+  *     @arg AES_IT_ERR: Error Interrupt.
+  * @retval ITStatus The new state of AES_IT (SET or RESET).
+  */
+ITStatus AES_GetITStatus(uint32_t AES_IT)
+{
+  ITStatus itstatus = RESET;
+  uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;
+
+  /* Check parameters */
+  assert_param(IS_AES_GET_IT(AES_IT));
+
+  cciebitstatus = AES->CR & AES_CR_CCIE;
+  ccfbitstatus =  AES->SR & AES_SR_CCF;
+
+  /* Check if AES_IT is AES_IT_CC */
+  if (AES_IT == AES_IT_CC)
+  {
+    /* Check the status of the specified AES interrupt */
+    if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
+    {
+      /* Interrupt occurred */
+      itstatus = SET;
+    }
+    else
+    {
+      /* Interrupt didn't occur */
+      itstatus = RESET;
+    }
+  }
+  else /* AES_IT is AES_IT_ERR */
+  {
+    /* Check the status of the specified AES interrupt */
+    if ((AES->CR & AES_CR_ERRIE) != RESET)
+    {
+      /* Check if WRERR or RDERR flags are set */
+      if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
+      {
+        /* Interrupt occurred */
+        itstatus = SET;
+      }
+      else
+      {
+        /* Interrupt didn't occur */
+        itstatus = RESET;
+      }
+    }
+    else
+    {
+      /* Interrupt didn't occur */
+      itstatus = (ITStatus) RESET;
+    }
+  }
+
+  /* Return the AES_IT status */
+  return itstatus;
+}
+
+/**
+  * @brief  Clears the AES's interrupt pending bits.
+  * @param  AES_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combinations of the following values:
+  *     @arg AES_IT_CC: Computation Complete Interrupt.
+  *     @arg AES_IT_ERR: Error Interrupt.
+  * @retval None
+  */
+void AES_ClearITPendingBit(uint32_t AES_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_AES_IT(AES_IT));
+
+  /* Clear the interrupt pending bit */
+  AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes_util.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes_util.c
new file mode 100644
index 0000000..f7dd9a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes_util.c
@@ -0,0 +1,679 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_aes_util.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using AES in ECB/CBC/CTR modes.
+  *
+  *  @verbatim
+
+================================================================================
+                        ##### How to use this driver #####
+================================================================================
+          [..]
+           (#) Enable The AES controller clock using 
+               RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.
+
+           (#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
+           (#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.
+
+           (#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
+           (#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.
+
+           (#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
+           (#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.
+
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_aes.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup AES 
+  * @brief AES driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AES_CC_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup AES_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup AES_Group6 High Level AES functions
+ *  @brief   High Level AES functions 
+ *
+@verbatim
+================================================================================
+                         ##### High Level AES functions #####
+================================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt using AES in ECB Mode
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+
+  /* AES Key initialisation */
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_Encryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+    /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+    
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+  
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @brief  Decrypt using AES in ECB Mode
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+
+  /* AES Key initialisation */
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+     /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+    
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @brief  Encrypt using AES in CBC Mode
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  AES_IVInitTypeDef AES_IVInitStructure;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+
+  /* AES Key initialisation*/
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES Initialization Vectors */
+  AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
+  AES_IVInit(&AES_IVInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_Encryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+    /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+    
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @brief  Decrypt using AES in CBC Mode
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  AES_IVInitTypeDef AES_IVInitStructure;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+  
+  /* AES Key initialisation*/
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES Initialization Vectors */
+  AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
+  AES_IVInit(&AES_IVInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+    /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @brief  Encrypt using AES in CTR Mode
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  AES_IVInitTypeDef AES_IVInitStructure;
+
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+
+  /* AES key initialisation*/
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES Initialization Vectors */
+  AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));
+  AES_IVInit(&AES_IVInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_Encryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+    /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @brief  Decrypt using AES in CTR Mode
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
+  * @param  Key: Key used for AES algorithm.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16 bytes.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  AES_InitTypeDef AES_InitStructure;
+  AES_KeyInitTypeDef  AES_KeyInitStructure;
+  AES_IVInitTypeDef AES_IVInitStructure;
+
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t ivaddr     = (uint32_t)InitVectors;
+  __IO uint32_t counter = 0;
+  uint32_t ccstatus = 0;
+  uint32_t i = 0;
+
+  /* AES Key initialisation*/
+  AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
+  keyaddr += 4;
+  AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
+  AES_KeyInit(&AES_KeyInitStructure);
+
+  /* AES Initialization Vectors */
+  AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
+  ivaddr += 4;
+  AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
+  AES_IVInit(&AES_IVInitStructure);
+
+  /* AES configuration */
+  AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
+  AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
+  AES_InitStructure.AES_DataType = AES_DataType_8b;
+  AES_Init(&AES_InitStructure);
+
+  /* Enable AES */
+  AES_Cmd(ENABLE);
+
+  for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
+  {
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    AES_WriteSubData(*(uint32_t*)(inputaddr));
+    inputaddr += 4;
+    
+    /* Wait for CCF flag to be set */
+    counter = 0;
+    do
+    {
+      ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
+      counter++;
+    }while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
+
+    if (ccstatus == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Clear CCF flag */
+      AES_ClearFlag(AES_FLAG_CCF);
+    
+      /* Read cipher text */
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+      *(uint32_t*)(outputaddr) = AES_ReadSubData();
+      outputaddr += 4;
+    }
+  }
+
+  /* Disable AES before starting new processing */
+  AES_Cmd(DISABLE);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_crc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_crc.c
new file mode 100644
index 0000000..66170d3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_crc.c
@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_crc.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_crc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC.
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed.
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register.
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c
new file mode 100644
index 0000000..233bfad
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c
@@ -0,0 +1,687 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_dac.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *          + DAC channels configuration: trigger, output buffer, data format
+  *          + DMA management      
+  *          + Interrupts and flags management
+
+  * @verbatim      
+  *   
+ ===============================================================================
+                        ##### DAC Peripheral features #####
+ ===============================================================================
+    [..] The device integrates two 12-bit Digital Analog Converters that can 
+         be used independently or simultaneously (dual mode):
+         (#) DAC channel1 with DAC_OUT1 (PA4) as output.
+         (#) DAC channel2 with DAC_OUT2 (PA5) as output.
+  
+    [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+         and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using 
+         DAC_SetChannel1Data()/DAC_SetChannel2Data.
+  
+    [..] Digital to Analog conversion can be triggered by:
+         (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+             The used pin (GPIOx_Pin9) must be configured in input mode.
+         (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 
+             (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
+             The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+         (#) Software using DAC_Trigger_Software.
+  
+    [..] Each DAC channel integrates an output buffer that can be used to 
+         reduce the output impedance, and to drive external loads directly
+         without having to add an external operational amplifier.
+         To enable, the output buffer use  
+         DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+            
+    [..] Refer to the device datasheet for more details about output impedance
+         value with and without output buffer.
+  
+    [..] Both DAC channels can be used to generate:
+         (#) Noise wave using DAC_WaveGeneration_Noise
+         (#) Triangle wave using DAC_WaveGeneration_Triangle
+  
+    [..] Wave generation can be disabled using DAC_WaveGeneration_None.
+  
+    [..] The DAC data format can be:
+         (#) 8-bit right alignment using DAC_Align_8b_R
+         (#) 12-bit left alignment using DAC_Align_12b_L
+         (#) 12-bit right alignment using DAC_Align_12b_R
+  
+    [..] The analog output voltage on each DAC channel pin is determined
+         by the following equation: DAC_OUTx = VREF+ * DOR / 4095
+         with  DOR is the Data Output Register.
+         VEF+ is the input voltage reference (refer to the device datasheet)
+         e.g. To set DAC_OUT1 to 0.7V, use
+         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+         Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.
+  
+    [..] A DMA1 request can be generated when an external trigger (but not
+         a software trigger) occurs if DMA1 requests are enabled using
+         DAC_DMACmd()
+    [..] DMA1 requests are mapped as following:
+         (#) DAC channel1 is mapped on DMA1 channel3 which must be already 
+             configured.
+         (#) DAC channel2 is mapped on DMA1 channel4 which must be already 
+             configured.
+  
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (+) DAC APB clock must be enabled to get write access to DAC registers using
+            RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+        (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+        (+) Configure the DAC channel using DAC_Init()
+        (+) Enable the DAC channel using DAC_Cmd()
+
+   @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_dac.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format.
+ *
+@verbatim
+ ===============================================================================
+  ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified 
+  *         parameters in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected.
+  *     @arg DAC_Channel_2: DAC Channel2 selected.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+  *         contains the configuration information for the specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+     mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *      This parameter can be: ENABLE or DISABLE.
+  * @note When the DAC channel is enabled the trigger source can no more
+  *       be modified.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *         triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Wave_Noise: noise wave generation
+  *     @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @note   
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *         holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *         holding register.
+  * @note In dual mode, a unique register access is required to write in both
+  *       DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### DMA management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  *         When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM4, TIM6, TIM7 or TIM9  but not a software trigger) occurs.
+  * @param  DAC_Channel: the selected DAC channel.
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which 
+  *  must be already configured. 
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *   This parameter can be the following value:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: thee selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *   This parameter can be only of the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *   This parameter can be the following value:
+  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *   This parameter can be one of the following values:
+  *     @arg DAC_Channel_1: DAC Channel1 selected
+  *     @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *   This parameter can be the following values:
+  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dbgmcu.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dbgmcu.c
new file mode 100644
index 0000000..b38918b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dbgmcu.c
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_dbgmcu.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+  *     @arg DBGMCU_RTC_STOP:
+  *       + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when 
+  *         Core is halted.
+  *       + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar 
+  *         and Wakeup counter stopped when Core is halted.
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is 
+  *                                     halted
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is 
+  *                                     halted
+  * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
+  * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
index b6290d5..d9ee18d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
@@ -1,28 +1,71 @@
 /**
   ******************************************************************************
-  * @file    stm32f10x_exti.c
+  * @file    stm32l1xx_exti.c
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    11-March-2011
-  * @brief   This file provides all the EXTI firmware functions.
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:           
+  *           + Initialization and Configuration
+  *           + Interrupts and flags management
+  *
+  *  @verbatim  
+  ============================================================================== 
+                            ##### EXTI features ##### 
+  ============================================================================== 
+    [..] External interrupt/event lines are mapped as following:
+         (#) All available GPIO pins are connected to the 16 external 
+             interrupt/event lines from EXTI0 to EXTI15.
+         (#) EXTI line 16 is connected to the PVD output.
+         (#) EXTI line 17 is connected to the RTC Alarm event.
+         (#) EXTI line 18 is connected to the USB Device FS wakeup event.
+         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
+         (#) EXTI line 20 is connected to the RTC Wakeup event.
+         (#) EXTI line 21 is connected to the Comparator 1 wakeup event.
+         (#) EXTI line 22 is connected to the Comparator 2 wakeup event.
+         (#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.
+         
+            
+                       ##### How to use this driver ##### 
+  ==============================================================================   
+    [..] In order to use an I/O pin as an external interrupt source, follow
+         steps below:
+    (#) Configure the I/O in input mode using GPIO_Init()
+    (#) Select the input source pin for the EXTI line using 
+        SYSCFG_EXTILineConfig()
+    (#) Select the mode(interrupt, event) and configure the trigger 
+        selection (Rising, falling or both) using EXTI_Init()
+    (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+    [..]
+	(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+            
+  *  @endverbatim                  
+  *
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_exti.h"
+#include "stm32l1xx_exti.h"
 
-/** @addtogroup STM32F10x_StdPeriph_Driver
+/** @addtogroup STM32L1xx_StdPeriph_Driver
   * @{
   */
 
@@ -31,49 +74,28 @@
   * @{
   */
 
-/** @defgroup EXTI_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Defines
-  * @{
-  */
-
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
 #define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
 
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
 
-/** @defgroup EXTI_Private_Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Private_FunctionPrototypes
+/** @defgroup EXTI_Private_Functions
   * @{
   */
 
-/**
-  * @}
-  */
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+            ##### Initialization and Configuration functions #####
+  ==============================================================================  
 
-/** @defgroup EXTI_Private_Functions
+@endverbatim
   * @{
   */
 
@@ -88,14 +110,19 @@ void EXTI_DeInit(void)
   EXTI->EMR = 0x00000000;
   EXTI->RTSR = 0x00000000; 
   EXTI->FTSR = 0x00000000; 
-  EXTI->PR = 0x000FFFFF;
+  EXTI->PR = 0x00FFFFFF;
 }
 
 /**
   * @brief  Initializes the EXTI peripheral according to the specified
-  *         parameters in the EXTI_InitStruct.
+  *   parameters in the EXTI_InitStruct.
+  *    EXTI_Line specifies the EXTI line (EXTI0....EXTI23).
+  *    EXTI_Mode specifies which EXTI line is used as interrupt or an event.
+  *    EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
+  *                 pending bit will be set.
+  *    EXTI_LineCmd controls (Enable/Disable) the EXTI line.
   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
-  *         that contains the configuration information for the EXTI peripheral.
+  *   that contains the configuration information for the EXTI peripheral.
   * @retval None
   */
 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
@@ -151,7 +178,7 @@ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
 /**
   * @brief  Fills each EXTI_InitStruct member with its reset value.
   * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
-  *         be initialized.
+  *   be initialized.
   * @retval None
   */
 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
@@ -163,9 +190,10 @@ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
 }
 
 /**
-  * @brief  Generates a Software interrupt.
-  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
   * @retval None
   */
 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
@@ -177,10 +205,26 @@ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
 }
 
 /**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Interrupts and flags management functions #####
+  ============================================================================== 
+  
+@endverbatim
+  * @{
+  */
+
+/**
   * @brief  Checks whether the specified EXTI line flag is set or not.
   * @param  EXTI_Line: specifies the EXTI line flag to check.
   *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  *   EXTI_Linex: External interrupt line x where x(0..23).
   * @retval The new state of EXTI_Line (SET or RESET).
   */
 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
@@ -203,7 +247,7 @@ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
 /**
   * @brief  Clears the EXTI's line pending flags.
   * @param  EXTI_Line: specifies the EXTI lines flags to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
   * @retval None
   */
 void EXTI_ClearFlag(uint32_t EXTI_Line)
@@ -218,7 +262,7 @@ void EXTI_ClearFlag(uint32_t EXTI_Line)
   * @brief  Checks whether the specified EXTI line is asserted or not.
   * @param  EXTI_Line: specifies the EXTI line to check.
   *   This parameter can be:
-  *     @arg EXTI_Linex: External interrupt line x where x(0..19)
+  *   EXTI_Linex: External interrupt line x where x(0..23).
   * @retval The new state of EXTI_Line (SET or RESET).
   */
 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
@@ -243,7 +287,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
 /**
   * @brief  Clears the EXTI's line pending bits.
   * @param  EXTI_Line: specifies the EXTI lines to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..23).
   * @retval None
   */
 void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
@@ -266,4 +310,8 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c
new file mode 100644
index 0000000..9bd1e86
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c
@@ -0,0 +1,1652 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_flash.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides all the Flash firmware functions. These functions 
+  *          can be executed from Internal FLASH or Internal SRAM memories. 
+  *          The functions that should be called from SRAM are defined inside 
+  *          the "stm32l1xx_flash_ramfunc.c" file.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH peripheral:
+  *            + FLASH Interface configuration
+  *            + FLASH Memory Programming
+  *            + DATA EEPROM Programming
+  *            + Option Bytes Programming
+  *            + Interrupts and flags management
+  *
+  *  @verbatim
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..] This driver provides functions to configure and program the Flash 
+         memory of all STM32L1xx devices.
+    [..] These functions are split in 5 groups:
+         (#) FLASH Interface configuration functions: this group includes 
+             the management of following features:
+             (++) Set the latency.
+             (++) Enable/Disable the prefetch buffer.
+             (++) Enable/Disable the 64 bit Read Access. 
+             (++) Enable/Disable the RUN PowerDown mode.
+             (++) Enable/Disable the SLEEP PowerDown mode.  
+    
+         (#) FLASH Memory Programming functions: this group includes all 
+             needed functions to erase and program the main memory:
+             (++) Lock and Unlock the Flash interface.
+             (++) Erase function: Erase Page.
+             (++) Program functions: Fast Word and Half Page(should be 
+                  executed from internal SRAM).
+      
+         (#) DATA EEPROM Programming functions: this group includes all 
+             needed functions to erase and program the DATA EEPROM memory:
+             (++) Lock and Unlock the DATA EEPROM interface.
+             (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase 
+             (++) Double Word (should be executed from internal SRAM).
+             (++) Program functions: Fast Program Byte, Fast Program Half-Word, 
+                  FastProgramWord, Program Byte, Program Half-Word, 
+                  Program Word and Program Double-Word (should be executed 
+                  from internal SRAM).
+      
+         (#) FLASH Option Bytes Programming functions: this group includes 
+             all needed functions to:
+             (++) Lock and Unlock the Flash Option bytes.
+             (++) Set/Reset the write protection.
+             (++) Set the Read protection Level.
+             (++) Set the BOR level.
+             (++) rogram the user option Bytes.
+             (++) Launch the Option Bytes loader.
+             (++) Get the Write protection.
+             (++) Get the read protection status.
+             (++) Get the BOR level.
+             (++) Get the user option bytes.
+    
+         (#) FLASH Interrupts and flag management functions: this group 
+             includes all needed functions to:
+             (++) Enable/Disable the flash interrupt sources.
+             (++) Get flags status.
+             (++) Clear flags.
+             (++) Get Flash operation status.
+             (++) Wait for last flash operation.
+
+  *  @endverbatim
+  *                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_flash.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+  
+/* FLASH Mask */
+#define WRP01_MASK                 ((uint32_t)0x0000FFFF)
+#define WRP23_MASK                 ((uint32_t)0xFFFF0000)
+#define WRP45_MASK                 ((uint32_t)0x0000FFFF)
+#define WRP67_MASK                 ((uint32_t)0xFFFF0000)
+#define WRP89_MASK                 ((uint32_t)0x0000FFFF)
+#define WRP1011_MASK               ((uint32_t)0xFFFF0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+ 
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+  *  @brief   FLASH Interface configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+             ##### FLASH Interface configuration functions #####
+  ==============================================================================
+
+    [..] FLASH_Interface configuration_Functions, includes the following functions:
+     (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
+    [..] To correctly read data from Flash memory, the number of wait states (LATENCY) 
+         must be correctly programmed according to the frequency of the CPU clock 
+        (HCLK) and the supply voltage of the device.
+  [..] 
+  ----------------------------------------------------------------
+ |  Wait states  |                HCLK clock frequency (MHz)      |
+ |               |------------------------------------------------|
+ |   (Latency)   |            voltage range       | voltage range |
+ |               |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
+ |               |----------------|---------------|---------------|
+ |               |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
+ |-------------- |----------------|---------------|---------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
+ |---------------|----------------|---------------|---------------|
+ |1WS(2CPU cycle)|2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
+  ----------------------------------------------------------------
+  [..]
+     (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+     (+) void FLASH_ReadAccess64Cmd(FunctionalState NewState);
+     (+) void FLASH_RUNPowerDownCmd(FunctionalState NewState);
+     (+) void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
+     (+) void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+  [..]     
+  Here below the allowed configuration of Latency, 64Bit access and prefetch buffer
+  [..]  
+  --------------------------------------------------------------------------------
+ |               |              ACC64 = 0         |              ACC64 = 1        |
+ |   Latency     |----------------|---------------|---------------|---------------|
+ |               |   PRFTEN = 0   |   PRFTEN = 1  |   PRFTEN = 0  |   PRFTEN = 1  |
+ |---------------|----------------|---------------|---------------|---------------|
+ |0WS(1CPU cycle)|     YES        |     NO        |     YES       |     YES       |
+ |---------------|----------------|---------------|---------------|---------------|
+ |1WS(2CPU cycle)|     NO         |     NO        |     YES       |     YES       |
+  --------------------------------------------------------------------------------
+  [..]
+   All these functions don't need the unlock sequence.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the code latency value.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_Latency_0: FLASH Zero Latency cycle.
+  *     @arg FLASH_Latency_1: FLASH One Latency cycle.
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+   uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+  
+  /* Read the ACR register */
+  tmpreg = FLASH->ACR;  
+  
+  /* Sets the Latency value */
+  tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+  tmpreg |= FLASH_Latency;
+  
+  /* Write the ACR register */
+  FLASH->ACR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param  NewState: new state of the FLASH prefetch buffer.
+  *              This parameter can be: ENABLE or DISABLE. 
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+  }
+  else
+  {
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables read access to flash by 64 bits.
+  * @param  NewState: new state of the FLASH read access mode.
+  *              This parameter can be: ENABLE or DISABLE.
+  * @note    If this bit is set, the Read access 64 bit is used.
+  *          If this bit is reset, the Read access 32 bit is used.
+  * @note    This bit cannot be written at the same time as the LATENCY and 
+  *          PRFTEN bits.
+  *          To reset this bit, the LATENCY should be zero wait state and the 
+  *          prefetch off.
+  * @retval None
+  */
+void FLASH_ReadAccess64Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_ACC64;
+  }
+  else
+  {
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64));
+  }
+}
+
+/**
+  * @brief  Enable or disable the power down mode during Sleep mode.
+  * @note   This function is used to power down the FLASH when the system is in SLEEP LP mode.
+  * @param  NewState: new state of the power down mode during sleep mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_SLEEPPowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */
+    FLASH->ACR |= FLASH_ACR_SLEEP_PD;
+  }
+  else
+  {
+    /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */
+    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ *  @brief   FLASH Memory Programming functions
+ *
+@verbatim   
+  ==============================================================================
+                ##### FLASH Memory Programming functions ##### 
+  ==============================================================================
+
+    [..] The FLASH Memory Programming functions, includes the following functions:
+    (+) void FLASH_Unlock(void);
+    (+) void FLASH_Lock(void);
+    (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+    (+) FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
+   
+    [..] Any operation of erase or program should follow these steps:
+    (#) Call the FLASH_Unlock() function to enable the flash control register and 
+        program memory access.
+    (#) Call the desired function to erase page or program data.
+    (#) Call the FLASH_Lock() to disable the flash program memory access 
+       (recommended to protect the FLASH memory against possible unwanted operation).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH control register and program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)
+  {
+    /* Unlocking the data memory and FLASH_PECR register access */
+    DATA_EEPROM_Unlock();
+  
+    /* Unlocking the program memory access */
+    FLASH->PRGKEYR = FLASH_PRGKEY1;
+    FLASH->PRGKEYR = FLASH_PRGKEY2;  
+  }
+}
+
+/**
+  * @brief  Locks the Program memory access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the PRGLOCK Bit to lock the program memory access */
+  FLASH->PECR |= FLASH_PECR_PRGLOCK;
+}
+
+/**
+  * @brief  Erases a specified page in program memory.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_Lock() to disable the flash memory access 
+  *         (recommended to protect the FLASH memory against possible unwanted operation)
+  * @param  Page_Address: The page address in program memory to be erased.
+  * @note   A Page is erased in the Program memory only if the address to load 
+  *         is the start address of a page (multiple of 256 bytes).
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+ 
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to erase the page */
+
+    /* Set the ERASE bit */
+    FLASH->PECR |= FLASH_PECR_ERASE;
+
+    /* Set PROG bit */
+    FLASH->PECR |= FLASH_PECR_PROG;
+  
+    /* Write 00000000h to the first word of the program page to erase */
+    *(__IO uint32_t *)Page_Address = 0x00000000;
+ 
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    /* If the erase operation is completed, disable the ERASE and PROG bits */
+    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
+    FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);   
+  }     
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address in program memory.
+  * @note   To correctly run this function, the FLASH_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_Lock() to disable the flash memory access
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @retval FLASH Status: The returned value can be:  
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* If the previous operation is completed, proceed to program the new  word */  
+    *(__IO uint32_t *)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);       
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Group3 DATA EEPROM Programming functions
+ *  @brief   DATA EEPROM Programming functions
+ *
+@verbatim   
+ ===============================================================================
+                     ##### DATA EEPROM Programming functions ##### 
+ ===============================================================================  
+ 
+    [..] The DATA_EEPROM Programming_Functions, includes the following functions:
+        (+) void DATA_EEPROM_Unlock(void);
+        (+) void DATA_EEPROM_Lock(void);
+        (+) FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
+        (+) FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
+        (+) FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
+        (+) FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
+        (+) FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
+        (+) FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
+        (+) FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
+        (+) FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
+        (+) FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
+   
+    [..] Any operation of erase or program should follow these steps:
+    (#) Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access
+        and Flash program erase control register access.
+    (#) Call the desired function to erase or program data.
+    (#) Call the DATA_EEPROM_Lock() to disable the data EEPROM access
+        and Flash program erase control register access(recommended
+        to protect the DATA_EEPROM against possible unwanted operation).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the data memory and FLASH_PECR register access.
+  * @param  None
+  * @retval None
+  */
+void DATA_EEPROM_Unlock(void)
+{
+  if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
+  {  
+    /* Unlocking the Data memory and FLASH_PECR register access*/
+    FLASH->PEKEYR = FLASH_PEKEY1;
+    FLASH->PEKEYR = FLASH_PEKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the Data memory and FLASH_PECR register access.
+  * @param  None
+  * @retval None
+  */
+void DATA_EEPROM_Lock(void)
+{
+  /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
+  FLASH->PECR |= FLASH_PECR_PELOCK;
+}
+
+/**
+  * @brief  Enables or disables DATA EEPROM fixed Time programming (2*Tprog).
+  * @param  NewState: new state of the DATA EEPROM fixed Time programming mode.
+  *         This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW;
+  }
+  else
+  {
+    FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+  }
+}
+
+/**
+  * @brief  Erase a byte in data memory.
+  * @param  Address: specifies the address to be erased.
+  * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP 
+  *         density devices.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Write "00h" to valid address in the data memory" */
+    *(__IO uint8_t *) Address = (uint8_t)0x00;
+  }
+   
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Erase a halfword in data memory.
+  * @param  Address: specifies the address to be erased.
+  * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP 
+  *         density devices.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Write "0000h" to valid address in the data memory" */
+    *(__IO uint16_t *) Address = (uint16_t)0x0000;
+  }
+   
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Erase a word in data memory.
+  * @param  Address: specifies the address to be erased.
+  * @note   For STM32L1XX_MD, A data memory word is erased in the data memory only 
+  *         if the address to load is the start address of a word (multiple of a word).
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Write "00000000h" to valid address in the data memory" */
+    *(__IO uint32_t *) Address = 0x00000000;
+  }
+   
+  /* Return the erase status */
+  return status;
+}
+
+/**
+  * @brief  Write a Byte at a specified address in data memory.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @note   This function assumes that the is data word is already erased.
+  * @retval FLASH Status: The returned value can be:
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+  uint32_t tmp = 0, tmpaddr = 0;
+#endif
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address)); 
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+  if(status == FLASH_COMPLETE)
+  {
+    /* Clear the FTDW bit */
+    FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+    if(Data != (uint8_t)0x00) 
+    {
+      /* If the previous operation is completed, proceed to write the new Data */
+      *(__IO uint8_t *)Address = Data;
+            
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    else
+    {
+      tmpaddr = Address & 0xFFFFFFFC;
+      tmp = * (__IO uint32_t *) tmpaddr;
+      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
+      tmp &= ~tmpaddr;
+      status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
+      status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
+    }       
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+    /* If the previous operation is completed, proceed to write the new Data */
+    *(__IO uint8_t *)Address = Data;
+            
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+#endif  
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @brief  Writes a half word at a specified address in data memory.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @note   This function assumes that the is data word is already erased.
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or  FLASH_TIMEOUT. 
+  */
+FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+  uint32_t tmp = 0, tmpaddr = 0;
+#endif
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    
+  if(status == FLASH_COMPLETE)
+  {
+    /* Clear the FTDW bit */
+    FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+    if(Data != (uint16_t)0x0000) 
+    {
+      /* If the previous operation is completed, proceed to write the new data */
+      *(__IO uint16_t *)Address = Data;
+  
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    else
+    {
+      if((Address & 0x3) != 0x3)
+      {
+        tmpaddr = Address & 0xFFFFFFFC;
+        tmp = * (__IO uint32_t *) tmpaddr;
+        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
+        tmp &= ~tmpaddr;        
+        status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
+        status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
+      }
+      else
+      {
+        DATA_EEPROM_FastProgramByte(Address, 0x00);
+        DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
+      }
+    }
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+    /* If the previous operation is completed, proceed to write the new data */
+    *(__IO uint16_t *)Address = Data;
+  
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+#endif
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address in data memory.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to the data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @note   This function assumes that the is data word is already erased.
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* Clear the FTDW bit */
+    FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW));
+  
+    /* If the previous operation is completed, proceed to program the new data */    
+    *(__IO uint32_t *)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);       
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @brief  Write a Byte at a specified address in data memory without erase.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before 
+  *         this function to configure the Fixed Time Programming.
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+  uint32_t tmp = 0, tmpaddr = 0;
+#endif
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address)); 
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+    if(Data != (uint8_t) 0x00)
+    {  
+      *(__IO uint8_t *)Address = Data;
+    
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+    }
+    else
+    {
+      tmpaddr = Address & 0xFFFFFFFC;
+      tmp = * (__IO uint32_t *) tmpaddr;
+      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
+      tmp &= ~tmpaddr;        
+      status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
+      status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
+    }
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+    *(__IO uint8_t *)Address = Data;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+#endif
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @brief  Writes a half word at a specified address in data memory without erase.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before 
+  *         this function to configure the Fixed Time Programming
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @retval FLASH Status: The returned value can be:
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
+  */
+FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+  uint32_t tmp = 0, tmpaddr = 0;
+#endif
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+#if !defined (STM32L1XX_HD) && !defined (STM32L1XX_MDP)
+    if(Data != (uint16_t)0x0000)
+    {
+      *(__IO uint16_t *)Address = Data;
+   
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+    }
+    else
+    {
+      if((Address & 0x3) != 0x3)
+      {
+        tmpaddr = Address & 0xFFFFFFFC;
+        tmp = * (__IO uint32_t *) tmpaddr;
+        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
+        tmp &= ~tmpaddr;          
+        status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC);
+        status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp);
+      }
+      else
+      {
+        DATA_EEPROM_FastProgramByte(Address, 0x00);
+        DATA_EEPROM_FastProgramByte(Address + 1, 0x00);
+      }
+    }
+#elif defined (STM32L1XX_HD) || defined (STM32L1XX_MDP)
+    *(__IO uint16_t *)Address = Data;
+   
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+#endif
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word at a specified address in data memory without erase.
+  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
+  *         must be called before.
+  *         Call the DATA_EEPROM_Lock() to he data EEPROM access
+  *         and Flash program erase control register access(recommended to protect 
+  *         the DATA_EEPROM against possible unwanted operation).
+  * @note   The function  DATA_EEPROM_FixedTimeProgramCmd() can be called before 
+  *         this function to configure the Fixed Time Programming.
+  * @param  Address: specifies the address to be written.
+  * @param  Data: specifies the data to be written.
+  * @retval FLASH Status: The returned value can be:
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or  FLASH_TIMEOUT. 
+  */
+FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_DATA_ADDRESS(Address));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {
+    *(__IO uint32_t *)Address = Data;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  }
+  /* Return the Write Status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group4 Option Bytes Programming functions
+ *  @brief   Option Bytes Programming functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Option Bytes Programming functions ##### 
+  ==============================================================================  
+
+    [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
+    (+) void FLASH_OB_Unlock(void);
+    (+) void FLASH_OB_Lock(void);
+    (+) void FLASH_OB_Launch(void);
+    (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+    (+) FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
+    (+) FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);   
+    (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+    (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+    (+) FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
+    (+) uint8_t FLASH_OB_GetUser(void);
+    (+) uint32_t FLASH_OB_GetWRP(void);
+    (+) uint32_t FLASH_OB_GetWRP1(void);
+    (+) uint32_t FLASH_OB_GetWRP2(void);     
+    (+) FlagStatus FLASH_OB_GetRDP(void);
+    (+) uint8_t FLASH_OB_GetBOR(void);
+    (+) FLASH_Status FLASH_OB_BootConfig(uint16_t OB_BOOT);
+   
+    [..] Any operation of erase or program should follow these steps:
+    (#) Call the FLASH_OB_Unlock() function to enable the Flash option control 
+        register access.
+    (#) Call one or several functions to program the desired option bytes.
+        (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable 
+             the desired sector write protection.
+        (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level.
+        (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure 
+             the user option Bytes: IWDG, STOP and the Standby.
+        (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level.
+        (++) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes			.
+    (#) Once all needed option bytes to be programmed are correctly written, call the
+        FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
+    (#) Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended
+        to protect the option Bytes against possible unwanted operations).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Unlock(void)
+{
+  if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)
+  {
+    /* Unlocking the data memory and FLASH_PECR register access */
+    DATA_EEPROM_Unlock();
+  
+    /* Unlocking the option bytes block access */
+    FLASH->OPTKEYR = FLASH_OPTKEY1;
+    FLASH->OPTKEYR = FLASH_OPTKEY2;
+  }
+}
+
+/**
+  * @brief  Locks the option bytes block access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the option bytes block access */
+  FLASH->PECR |= FLASH_PECR_OPTLOCK;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Launch(void)
+{
+  /* Set the OBL_Launch bit to lauch the option byte loading */
+  FLASH->PECR |= FLASH_PECR_OBL_LAUNCH;
+}
+
+/**
+  * @brief  Write protects the desired pages.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *        (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_WRP: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  * @param  value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511
+  * @param  OB_WRP_AllPages
+  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
+{
+  uint32_t WRP01_Data = 0, WRP23_Data = 0;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+     
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+  if(status == FLASH_COMPLETE)
+  {
+    if (NewState != DISABLE)
+    {
+      WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01));
+      WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); 
+      tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data);
+      OB->WRP01 = tmp1;
+      
+      tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data);
+      OB->WRP23 = tmp2;      
+    }             
+    
+    else
+    {
+      WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01));
+      WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); 
+
+      tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data);
+      OB->WRP01 = tmp1;
+      
+      tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data);
+      OB->WRP23 = tmp2;
+    }
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  }
+
+  /* Return the write protection operation Status */
+  return status;      
+}
+
+/**
+  * @brief  Write protects the desired pages.
+  * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP 
+  *         density devices.
+  *         To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_WRP1: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  *     @arg  value between OB_WRP_Pages512to527 and OB_WRP_Pages1008to1023
+  *     @arg OB_WRP_AllPages
+  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState)
+{
+  uint32_t WRP45_Data = 0, WRP67_Data = 0;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP1));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+     
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+  if(status == FLASH_COMPLETE)
+  {
+    if (NewState != DISABLE)
+    {
+      WRP45_Data = (uint16_t)(((OB_WRP1 & WRP45_MASK) | OB->WRP45));
+      WRP67_Data = (uint16_t)((((OB_WRP1 & WRP67_MASK)>>16 | OB->WRP67))); 
+      tmp1 = (uint32_t)(~(WRP45_Data) << 16)|(WRP45_Data);
+      OB->WRP45 = tmp1;
+      
+      tmp2 = (uint32_t)(~(WRP67_Data) << 16)|(WRP67_Data);
+      OB->WRP67 = tmp2;      
+    }             
+    
+    else
+    {
+      WRP45_Data = (uint16_t)(~OB_WRP1 & (WRP45_MASK & OB->WRP45));
+      WRP67_Data = (uint16_t)((((~OB_WRP1 & WRP67_MASK)>>16 & OB->WRP67))); 
+
+      tmp1 = (uint32_t)((~WRP45_Data) << 16)|(WRP45_Data);
+      OB->WRP45 = tmp1;
+      
+      tmp2 = (uint32_t)((~WRP67_Data) << 16)|(WRP67_Data);
+      OB->WRP67 = tmp2;
+    }
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  }
+
+  /* Return the write protection operation Status */
+  return status;      
+}
+
+/**
+  * @brief  Write protects the desired pages.
+  * @note   This function can be used only for STM32L1XX_HD density devices.
+  *         To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_WRP2: specifies the address of the pages to be write protected.
+  *   This parameter can be:
+  *     @arg  value between OB_WRP_Pages1024to1039 and OB_WRP_Pages1520to1535
+  *     @arg OB_WRP_AllPages
+  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState)
+{
+  uint32_t WRP89_Data = 0, WRP1011_Data = 0;
+  
+  FLASH_Status status = FLASH_COMPLETE;
+  uint32_t tmp1 = 0, tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP2));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+     
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ 
+  if(status == FLASH_COMPLETE)
+  {
+    if (NewState != DISABLE)
+    {
+      WRP89_Data = (uint16_t)(((OB_WRP2 & WRP89_MASK) | OB->WRP89));
+      WRP1011_Data = (uint16_t)((((OB_WRP2 & WRP1011_MASK)>>16 | OB->WRP1011))); 
+      tmp1 = (uint32_t)(~(WRP89_Data) << 16)|(WRP89_Data);
+      OB->WRP89 = tmp1;
+      
+      tmp2 = (uint32_t)(~(WRP1011_Data) << 16)|(WRP1011_Data);
+      OB->WRP1011 = tmp2;      
+    }             
+    
+    else
+    {
+      WRP89_Data = (uint16_t)(~OB_WRP2 & (WRP89_MASK & OB->WRP89));
+      WRP1011_Data = (uint16_t)((((~OB_WRP2 & WRP1011_MASK)>>16 & OB->WRP1011))); 
+
+      tmp1 = (uint32_t)((~WRP89_Data) << 16)|(WRP89_Data);
+      OB->WRP89 = tmp1;
+      
+      tmp2 = (uint32_t)((~WRP1011_Data) << 16)|(WRP1011_Data);
+      OB->WRP1011 = tmp2;
+    }
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  }
+
+  /* Return the write protection operation Status */
+  return status;      
+}
+
+/**
+  * @brief  Enables or disables the read out protection.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  FLASH_ReadProtection_Level: specifies the read protection level. 
+  *   This parameter can be:
+  *     @arg OB_RDP_Level_0: No protection
+  *     @arg OB_RDP_Level_1: Read protection of the memory
+  *     @arg OB_RDP_Level_2: Chip protection
+  *     @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  uint8_t tmp1 = 0;
+  uint32_t tmp2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_RDP(OB_RDP));
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  /* calculate the option byte to write */
+  tmp1 = (uint8_t)(~(OB_RDP ));
+  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP));
+  
+  if(status == FLASH_COMPLETE)
+  {         
+   /* program read protection level */
+    OB->RDP = tmp2;
+  }
+  
+  /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+     
+  /* Return the Read protection operation Status */
+  return status;            
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_IWDG: Selects the WDG mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_IWDG_SW: Software WDG selected
+  *     @arg OB_IWDG_HW: Hardware WDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *     @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *   This parameter can be one of the following values:
+  *     @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+  uint32_t tmp = 0, tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Get the User Option byte register */
+  tmp1 = (FLASH->OBR & 0x000F0000) >> 16;
+    
+  /* Calculate the user option byte to write */ 
+  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10));
+  tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Write the User Option Byte */              
+    OB->USER = tmp; 
+  }
+  
+  /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+       
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs the FLASH brownout reset threshold level Option Byte.
+  * @note   To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_BOR: Selects the brownout reset threshold level.
+  *   This parameter can be one of the following values:
+  *     @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD 
+  *                      power supply reaches the PDR(Power Down Reset) threshold (1.5V)
+  *     @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
+  *     @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
+  *     @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
+  *     @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
+  *     @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
+  * @retval FLASH Status: The returned value can be: 
+  * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+  uint32_t tmp = 0, tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOR_LEVEL(OB_BOR));
+
+  /* Get the User Option byte register */
+  tmp1 = (FLASH->OBR & 0x00F00000) >> 16;
+     
+  /* Calculate the option byte to write */
+  tmp = (uint32_t)~(OB_BOR | tmp1)<<16;
+  tmp |= (OB_BOR | tmp1);
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Write the BOR Option Byte */            
+    OB->USER = tmp; 
+  }
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+        
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Configures to boot from Bank1 or Bank2.
+  * @note   This function can be used only for STM32L1XX_HD density devices.
+  *         To correctly run this function, the FLASH_OB_Unlock() function
+  *         must be called before.
+  *         Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
+  *         (recommended to protect the FLASH memory against possible unwanted operation).
+  * @param  OB_BOOT: select the FLASH Bank to boot from.
+  *   This parameter can be one of the following values:
+  *     @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
+  *        depending on the activation of the bank. The active banks are checked in
+  *        the following order: Bank2, followed by Bank1.
+  *        The active bank is recognized by the value programmed at the base address
+  *        of the respective bank (corresponding to the initial stack pointer value
+  *        in the interrupt vector table).
+  *     @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash
+  *        position and this parameter is selected the device will boot from Bank1(Default).
+  *        For more information, please refer to AN2606 from www.st.com. 
+  * @retval FLASH Status: The returned value can be: 
+  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT)
+{
+  FLASH_Status status = FLASH_COMPLETE; 
+  uint32_t tmp = 0, tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_BANK(OB_BOOT));
+
+  /* Get the User Option byte register */
+  tmp1 = (FLASH->OBR & 0x007F0000) >> 16;
+     
+  /* Calculate the option byte to write */
+  tmp = (uint32_t)~(OB_BOOT | tmp1)<<16;
+  tmp |= (OB_BOOT | tmp1);
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+  
+  if(status == FLASH_COMPLETE)
+  {  
+    /* Write the BOOT Option Byte */            
+    OB->USER = tmp; 
+  }
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+       
+  /* Return the Option Byte program Status */
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval The FLASH User Option Bytes.
+  */
+uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return (uint8_t)(FLASH->OBR >> 20);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value.
+  */
+uint32_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @note   This function can be used only for STM32L1XX_HD and STM32L1XX_MDP 
+  *         density devices.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value.
+  */
+uint32_t FLASH_OB_GetWRP1(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR1);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @note   This function can be used only for STM32L1XX_HD density devices.
+  * @param  None
+  * @retval The FLASH Write Protection Option Bytes value.
+  */
+uint32_t FLASH_OB_GetWRP2(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (uint32_t)(FLASH->WRPR2);
+}
+
+/**
+  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status(SET or RESET).
+  */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+  
+  if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0)
+  {
+    readstatus = SET;
+  }
+  else
+  {
+    readstatus = RESET;
+  }
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @param  None
+  * @retval The FLASH User Option Bytes.
+  */
+uint8_t FLASH_OB_GetBOR(void)
+{
+  /* Return the BOR level */
+  return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+  ==============================================================================
+              ##### Interrupts and flags management functions #####
+  ==============================================================================    
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or 
+  *         disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+  *     @arg FLASH_IT_ERR: FLASH Error Interrupt
+  * @retval None 
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->PECR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->PECR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode
+  *     @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH size error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *     @arg FLASH_FLAG_SIZERR: FLASH size error flag    
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: 
+  *   FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status FLASHstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    FLASHstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+    { 
+      FLASHstatus = FLASH_ERROR_WRP;
+    }
+    else 
+    {
+      if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)
+      {
+        FLASHstatus = FLASH_ERROR_PROGRAM; 
+      }
+      else
+      {
+        FLASHstatus = FLASH_COMPLETE;
+      }
+    }
+  }
+  /* Return the FLASH Status */
+  return FLASHstatus;
+}
+
+
+/**
+  * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
+  * @param  Timeout: FLASH programming Timeout.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, 
+  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+  */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  __IO FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the FLASH Status */
+  status = FLASH_GetStatus();
+  
+  /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+  while((status == FLASH_BUSY) && (Timeout != 0x00))
+  {
+    status = FLASH_GetStatus();
+    Timeout--;
+  }
+  
+  if(Timeout == 0x00 )
+  {
+    status = FLASH_TIMEOUT;
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+  /**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_fsmc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_fsmc.c
new file mode 100644
index 0000000..989b87a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_fsmc.c
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_fsmc.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the FSMC peripheral:
+  *           + Initialization 
+  *           + Interrupts and flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_fsmc.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
+ *  @brief   NOR/SRAM Controller functions 
+ *
+  @verbatim
+  ==============================================================================
+                  ##### NOR-SRAM Controller functions #####
+  ==============================================================================
+    [..] The following sequence should be followed to configure the FSMC to 
+         interface with SRAM, PSRAM, NOR or OneNAND memory connected to the 
+         NOR/SRAM Bank: 
+    (#) Enable the clock for the FSMC and associated GPIOs using the following 
+        functions: 
+        (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); 
+        (++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE); 
+    (#) FSMC pins configuration  
+        (++) Connect the involved FSMC pins to AF12 using the following function  
+             GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
+        (++) Configure these FSMC pins in alternate function mode by calling the
+             function GPIO_Init();
+    (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: 
+        FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure; and fill the 
+        FSMC_NORSRAMInitStructure variable with the allowed values of the 
+        structure member.
+    (#) Initialize the NOR/SRAM Controller by calling the function 
+        FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);  
+    (#) Then enable the NOR/SRAM Bank, for example: 
+        FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);   
+    (#) At this stage you can read/write from/to the memory connected to the 
+        NOR/SRAM Bank.
+   
+@endverbatim
+
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *   reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval None
+  */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  
+  /* FSMC_Bank1_NORSRAM1 */
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+  {
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+  else
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
+
+/**
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
+  *   parameters in the FSMC_NORSRAMInitStruct.
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+  *   structure that contains the configuration information for 
+  *   the FSMC NOR/SRAM specified Banks.                       
+  * @retval None
+  */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+  {
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
+  }
+  
+  /* Bank1 NOR/SRAM timing register configuration */
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+  {
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+  }
+  else
+  {
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef 
+  *   structure which will be initialized.
+  * @retval None
+  */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *   This parameter can be one of the following values:
+  *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
new file mode 100644
index 0000000..c0aa121
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
@@ -0,0 +1,557 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_gpio.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:           
+  *           + Initialization and Configuration
+  *           + GPIO Read and Write
+  *           + GPIO Alternate functions configuration
+  * 
+  *  @verbatim
+    ===========================================================================
+                         ##### How to use this driver #####
+    ===========================================================================
+      [..]
+      (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+      (#) Configure the GPIO pin(s) using GPIO_Init()
+          Four possible configuration are available for each pin:
+         (++) Input: Floating, Pull-up, Pull-down.
+         (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
+              Open Drain (Pull-up, Pull-down or no Pull).
+              In output mode, the speed is configurable: Very Low, Low,
+              Medium or High.
+         (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
+              Open Drain (Pull-up, Pull-down or no Pull).
+         (++) Analog: required mode when a pin is to be used as ADC channel,
+              DAC output or comparator input.
+      (#) Peripherals alternate function:
+          (++) For ADC, DAC and comparators, configure the desired pin in 
+               analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+          (++) For other peripherals (TIM, USART...):
+              (+++) Connect the pin to the desired peripherals' Alternate 
+                    Function (AF) using GPIO_PinAFConfig() function.
+              (+++) Configure the desired pin in alternate function mode using
+                    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+              (+++) Select the type, pull-up/pull-down and output speed via 
+                    GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+              (+++) Call GPIO_Init() function.
+      (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+      (#) To set/reset the level of a pin configured in output mode use
+          GPIO_SetBits()/GPIO_ResetBits()
+      (#) During and just after reset, the alternate functions are not 
+          active and the GPIO pins are configured in input floating mode
+          (except JTAG pins).
+      (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
+          general-purpose (PC14 and PC15, respectively) when the LSE
+          oscillator is off. The LSE has priority over the GPIO function.
+      (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+          general-purpose PH0 and PH1, respectively, when the HSE 
+          oscillator is off. The HSE has priority over the GPIO function.
+    @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim   
+ ===============================================================================
+                    ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset 
+  *         values.
+  *         By default, The GPIO pins are configured in input floating mode
+  *         (except JTAG pins).
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if(GPIOx == GPIOA)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);  
+  }
+  else if(GPIOx == GPIOB)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+  }
+  else if(GPIOx == GPIOC)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+  }
+  else if(GPIOx == GPIOD)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+  }
+  else if(GPIOx == GPIOE)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+  }
+  else if(GPIOx == GPIOF)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+  }
+  else if(GPIOx == GPIOG)
+  {
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, DISABLE);
+  }   
+  else
+  {
+    if(GPIOx == GPIOH)
+    {
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified 
+  *         parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that 
+  *         contains the configuration information for the specified GPIO
+  *         peripheral.
+
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /* -------------------------Configure the port pins---------------- */
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /*Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration */
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      /* Pull-up Pull down resistor configuration */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  *         The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  *         The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                      ##### GPIO Read and Write #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the port bit to read.
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @note  This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *        accesses. In this way, there is no risk of an IRQ occurring between
+  *        the read and the modify access.
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BSRRL = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @note  This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *        accesses. In this way, there is no risk of an IRQ occurring between
+  *        the read and the modify access.
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  
+  GPIOx->BSRRH = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be one of the BitAction enum values:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+  
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRRL = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRRH = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data 
+  *                  register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins..
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ *  @brief   GPIO Alternate functions configuration functions
+ *
+@verbatim   
+ ===============================================================================
+          ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AFSelection: selects the pin to used as Alternat function.
+  *   This parameter can be one of the following values:
+  *     @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization
+  *     @arg GPIO_AF_MCO: Microcontroller clock output
+  *     @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,
+  *                           512 Hz clock output (with an LSE oscillator of 32.768 kHz)
+  *     @arg GPIO_AF_WKUP: wakeup
+  *     @arg GPIO_AF_SWJ: SWJ (SW and JTAG)
+  *     @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
+  *     @arg GPIO_AF_TIM2c: Connect TIM2 pins to AF1
+  *     @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
+  *     @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
+  *     @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
+  *     @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
+  *     @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
+  *     @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
+  *     @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
+  *     @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
+  *     @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
+  *     @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
+  *     @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
+  *     @arg GPIO_AF_USART1: Connect USART1 pins to AF7
+  *     @arg GPIO_AF_USART2: Connect USART2 pins to AF7
+  *     @arg GPIO_AF_USART3: Connect USART3 pins to AF7
+  *     @arg GPIO_AF_UART4: Connect UART4 pins to AF8
+  *     @arg GPIO_AF_UART5: Connect UART5 pins to AF8
+  *     @arg GPIO_AF_USB: Connect USB pins to AF10
+  *     @arg GPIO_AF_LCD: Connect LCD pins to AF11
+  *     @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
+  *     @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
+  *     @arg GPIO_AF_RI: Connect RI pins to AF14
+  *     @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal
+  * @note The pin should already been configured in Alternate Function mode(AF)
+  *        using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  * @note Please refer to the Alternate function mapping table in the device 
+  *        datasheet for the detailed mapping of the system and peripherals'
+  *        alternate function I/O pins.  
+  * @note EVENTOUT is not mapped on PH0, PH1 and PH2.  
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+  
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c
new file mode 100644
index 0000000..c356696
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c
@@ -0,0 +1,1364 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_i2c.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Inter-integrated circuit (I2C)
+  *           + Initialization and Configuration
+  *           + Data transfers
+  *           + PEC management
+  *           + DMA transfers management
+  *           + Interrupts, events and flags management 
+  *           
+  *  @verbatim
+  *    
+  * ============================================================================
+  *                    ##### How to use this driver #####
+  * ============================================================================
+   [..]
+   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+       function for I2C1 or I2C2.
+   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+       RCC_AHBPeriphClockCmd() function. 
+   (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+            Function (AF) using GPIO_PinAFConfig() function.
+       (++) Configure the desired pin in alternate function by:
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, pull-up/pull-down and output speed via 
+            GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function.
+   (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
+       Address using the I2C_Init() function.
+   (#) Optionally you can enable/configure the following parameters without
+       re-initialization (i.e there is no need to call again I2C_Init() function):
+       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+       (++) Enable the general call using the I2C_GeneralCallCmd() function.
+       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+       (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
+            function.
+       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+       (++) For SMBus Mode: 
+            (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function.
+            (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function.
+   (#) Enable the NVIC and the corresponding interrupt using the function
+       I2C_ITConfig() if you need to use interrupt mode.
+   (#) When using the DMA mode 
+      (++) Configure the DMA using DMA_Init() function.
+      (++) Active the needed channel Request using I2C_DMACmd() or
+           I2C_DMALastTransferCmd() function.
+   (#) Enable the I2C using the I2C_Cmd() function.
+   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+       transfers. 
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_rcc.h"
+
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK          ((uint16_t)0xFBF5)      /*<! I2C registers Masks */
+#define FLAG_MASK               ((uint32_t)0x00FFFFFF)  /*<! I2C FLAG mask */
+#define ITEN_MASK               ((uint32_t)0x07000000)  /*<! I2C Interrupt Enable mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Enable I2C1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+    /* Release I2C1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+  }
+  else
+  {
+    /* Enable I2C2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+    /* Release I2C2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the I2Cx peripheral according to the specified 
+  *         parameters in the I2C_InitStruct.
+  * @note   To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency 
+  *         (I2C peripheral input clock) must be a multiple of 10 MHz.  
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+  *   contains the configuration information for the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+  uint16_t tmpreg = 0, freqrange = 0;
+  uint16_t result = 0x04;
+  uint32_t pclk1 = 8000000;
+  RCC_ClocksTypeDef  rcc_clocks;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear frequency FREQ[5:0] bits */
+  tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
+  /* Get pclk1 frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  pclk1 = rcc_clocks.PCLK1_Frequency;
+  /* Set frequency bits depending on pclk1 value */
+  freqrange = (uint16_t)(pclk1 / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable the selected I2C peripheral to configure TRISE */
+  I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;  
+    }
+    /* Set speed value for standard mode */
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time for standard mode */
+    I2Cx->TRISE = freqrange + 1; 
+  }
+  /* Configure speed in fast mode */
+  /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
+     input clock) must be a multiple of 10 MHz */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+      /* Set DUTY bit */
+      result |= I2C_DutyCycle_16_9;
+    }
+
+    /* Test if CCR value is under 0x1*/
+    if ((result & I2C_CCR_CCR) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (uint16_t)0x0001;  
+    }
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= (uint16_t)(result | I2C_CCR_FS);
+    /* Set Maximum Rise Time for fast mode */
+    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
+  }
+
+  /* Write to I2Cx CCR */
+  I2Cx->CCR = tmpreg;
+  /* Enable the selected I2C peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR1 |= I2C_CR1_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR1 |= I2C_CR1_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C Acknowledgement.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR1 |= I2C_CR1_ACK;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C general call feature.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C General call.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CR1 |= I2C_CR1_ENGC;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C software reset.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR1 |= I2C_CR1_SWRST;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
+  }
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+  *     @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C ARP.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx ARP. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CR1 |= I2C_CR1_ENARP;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C Clock stretching.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *     @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CCR &= I2C_DutyCycle_2;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
+  }
+}
+
+/**
+  * @brief  Transmits the address byte to select the slave device.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Address: specifies the slave address which will be transmitted.
+  * @param  I2C_Direction: specifies whether the I2C device will be a
+  *   Transmitter or a Receiver. This parameter can be one of the following values:
+  *     @arg I2C_Direction_Transmitter: Transmitter mode
+  *     @arg I2C_Direction_Receiver: Receiver mode
+  * @retval None.
+  */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address bit0 for read */
+    Address |= I2C_OAR1_ADD0;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group2 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted.
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->DR;
+}
+
+/**
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
+  *         This function is useful in I2C Master Receiver mode when the number
+  *         of data to be received is equal to 2. In this case, this function 
+  *         should be called (with parameter I2C_NACKPosition_Next) before data 
+  *         reception starts,as described in the 2-byte reception procedure 
+  *         recommended in Reference Manual in Section: Master receiver.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_NACKPosition: specifies the NACK position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+  *          received byte.
+  *     @arg I2C_NACKPosition_Current: indicates that current byte is the last 
+  *          received byte.
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
+  *          is intended to used in SMBUS mode.
+  *            
+  * @retval None
+  */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+  
+  /* Check the input parameter */
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
+  {
+    /* Next byte in shift register is the last received byte */
+    I2Cx->CR1 |= I2C_NACKPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is the last received byte */
+    I2Cx->CR1 &= I2C_NACKPosition_Current;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group3 PEC management functions
+ *  @brief   PEC management functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### PEC management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified I2C PEC transfer.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C PEC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC transmission */
+    I2Cx->CR1 |= I2C_CR1_PEC;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC transmission */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C PEC position.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_PECPosition: specifies the PEC position. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+  *     @arg I2C_PECPosition_Current: indicates that current byte is PEC
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
+  *          is intended to used in I2C mode.
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* Next byte in shift register is PEC */
+    I2Cx->CR1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is PEC */
+    I2Cx->CR1 &= I2C_PECPosition_Current;
+  }
+}
+
+/**
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_ENPEC;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
+  }
+}
+
+/**
+  * @brief  Returns the PEC value for the specified I2C.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @retval The PEC value.
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the selected I2C PEC value */
+  return ((I2Cx->SR2) >> 8);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+  [..] This section provides functions allowing to configure the I2C DMA channels 
+       requests.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified I2C DMA requests.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR2 |= I2C_CR2_DMAEN;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
+  }
+}
+
+/**
+  * @brief  Specifies that the next DMA transfer is the last one.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA last transfer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Next DMA transfer is the last transfer */
+    I2Cx->CR2 |= I2C_CR2_LAST;
+  }
+  else
+  {
+    /* Next DMA transfer is not the last transfer */
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group5 Interrupts events and flags management functions
+ *  @brief   Interrupts, events and flags management functions
+ *
+@verbatim
+ ===============================================================================
+        ##### Interrupts, events and flags management functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to configure the I2C Interrupts 
+         sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to manage 
+         the communication: Polling mode, Interrupt mode or DMA mode. 
+
+
+                ##### I2C State Monitoring Functions #####
+ ===============================================================================   
+    [..]This I2C driver provides three different ways for I2C state monitoring
+        depending on the application requirements and constraints:
+         
+   
+     ***. Basic state monitoring (Using I2C_CheckEvent() function) ***
+     -----------------------------------------------------------------
+    [..]It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+    (+) When to use
+        (++) This function is suitable for most applications as well as for 
+             startup activity since the events are fully described in the product 
+             reference manual (RM0038).
+        (++) It is also suitable for users who need to define their own events.
+    (+) Limitations
+        (++) If an error occurs (ie. error flags are set besides to the monitored 
+             flags), the I2C_CheckEvent() function may return SUCCESS despite 
+             the communication hold or corrupted real state. 
+             In this case, it is advised to use error interrupts to monitor 
+             the error events and handle them in the interrupt IRQ handler.
+        -@@- For error management, it is advised to use the following functions:
+             (+@@) I2C_ITConfig() to configure and enable the error interrupts 
+                   (I2C_IT_ERR).
+             (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+                   Where x is the peripheral instance (I2C1, I2C2 ...).
+             (+@@) I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the
+                   I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+             (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+                   and/or I2C_GenerateStop() in order to clear the error flag and source
+                   and return to correct  communication status.
+
+     *** Advanced state monitoring (Using the function I2C_GetLastEvent()) ***
+     ------------------------------------------------------------------------- 
+    [..] Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+    (+) When to use
+       (++) This function is suitable for the same applications above but it 
+            allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+            function.
+       (++) The returned value could be compared to events already defined in 
+            the library (stm32l1xx_i2c.h) or to custom values defined by user.
+            This function is suitable when multiple flags are monitored at the 
+            same time.
+       (++) At the opposite of I2C_CheckEvent() function, this function allows 
+            user to choose when an event is accepted (when all events flags are 
+            set and no other flags are set or just when the needed flags are set 
+            like I2C_CheckEvent() function.
+
+     (+) Limitations
+         (++) User may need to define his own events.
+         (++) Same remark concerning the error management is applicable for this 
+              function if user decides to check only regular communication flags 
+              (and ignores error flags).
+      
+ 
+    *** Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ***
+    ----------------------------------------------------------------------------
+    [..] Using the function I2C_GetFlagStatus() which simply returns the status of 
+         one single flag (ie. I2C_FLAG_RXNE ...).
+         (+) When to use
+             (++) This function could be used for specific applications or in debug 
+                  phase.
+             (++) It is suitable when only one flag checking is needed (most I2C 
+                  events are monitored through multiple flags).
+         (+) Limitations: 
+             (++) When calling this function, the Status register is accessed. 
+                  Some flags are cleared when the status register is accessed. 
+                  So checking the status of one Flag, may clear other ones.
+             (++) Function may need to be called twice or more in order to monitor 
+                  one single event.
+ 
+    [..] For detailed description of Events, please refer to section I2C_Events in 
+         stm32l1xx_i2c.h file.
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2C_Register: specifies the register to read.
+  *   This parameter can be one of the following values:
+  *     @arg I2C_Register_CR1:  CR1 register.
+  *     @arg I2C_Register_CR2:   CR2 register.
+  *     @arg I2C_Register_OAR1:  OAR1 register.
+  *     @arg I2C_Register_OAR2:  OAR2 register.
+  *     @arg I2C_Register_DR:    DR register.
+  *     @arg I2C_Register_SR1:   SR1 register.
+  *     @arg I2C_Register_SR2:   SR2 register.
+  *     @arg I2C_Register_CCR:   CCR register.
+  *     @arg I2C_Register_TRISE: TRISE register.
+  * @retval The value of the read register.
+  */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_BUF: Buffer interrupt mask
+  *     @arg I2C_IT_EVT: Event interrupt mask
+  *     @arg I2C_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR2 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR2 &= (uint16_t)~I2C_IT;
+  }
+}
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring                     
+ ===============================================================================
+ */
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *   as parameter.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED:                   EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED:                      EV1
+  *     @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED:             EV1
+  *     @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED:                EV1
+  *     @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED:                    EV1
+  *     @arg I2C_EVENT_SLAVE_BYTE_RECEIVED:                                 EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF):              EV2
+  *     @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL):            EV2
+  *     @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED:                              EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF):           EV3
+  *     @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL):         EV3
+  *     @arg I2C_EVENT_SLAVE_ACK_FAILURE:                                 EV3_2
+  *     @arg I2C_EVENT_SLAVE_STOP_DETECTED:                                 EV4
+  *     @arg I2C_EVENT_MASTER_MODE_SELECT:                                  EV5
+  *     @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED:                    EV6
+  *     @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED:                       EV6
+  *     @arg I2C_EVENT_MASTER_BYTE_RECEIVED:                                EV7
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING:                            EV8
+  *     @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED:                           EV8_2
+  *     @arg I2C_EVENT_MASTER_MODE_ADDRESS10:                               EV9
+  * @note For detailed description of Events, please refer to section 
+  *        I2C_Events in stm32l1xx_i2c.h file.
+  * @retval An ErrorStatus enumeration value:
+  * - SUCCESS: Last event is equal to the I2C_EVENT
+  * - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_MASK;
+
+  /* Check whether the last event contains the I2C_EVENT */
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+  /* Return status */
+  return status;
+}
+
+/*
+ ===============================================================================
+                          2. Advanced state monitoring                   
+ ===============================================================================  
+ */
+
+/**
+  * @brief  Returns the last I2Cx Event.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  *     
+  * @note For detailed description of Events, please refer to section 
+  *    I2C_Events in stm32l1xx_i2c.h file.
+  *    
+  * @retval The last event
+  */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_MASK;
+
+  /* Return status */
+  return lastevent;
+}
+
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring                   
+ ===============================================================================  
+ */
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+  *     @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+  *     @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+  *     @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+  *     @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *     @arg I2C_FLAG_BUSY: Bus busy flag
+  *     @arg I2C_FLAG_MSL: Master/Slave flag
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *     @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *     @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+  *   Address matched flag (Slave mode)"ENDAD"
+  *     @arg I2C_FLAG_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the I2Cx peripheral base address */
+  i2cxbase = (uint32_t)I2Cx;
+  
+  /* Read flag register index */
+  i2creg = I2C_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_FLAG &= FLAG_MASK;
+  
+  if(i2creg != 0)
+  {
+    /* Get the I2Cx SR1 register address */
+    i2cxbase += 0x14;
+  }
+  else
+  {
+    /* Flag in I2Cx SR2 Register */
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+    /* Get the I2Cx SR2 register address */
+    i2cxbase += 0x18;
+  }
+  
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *     @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_FLAG_AF: Acknowledge failure flag
+  *     @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_FLAG_BERR: Bus error flag
+  *   
+
+  *@note STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
+  *     to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  *@note ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
+  *     second byte of the address in DR register.
+  *@note BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  *@note ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  *@note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+  *     register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+  *     register  (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & FLAG_MASK;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert flag
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+  *     @arg I2C_IT_PECERR: PEC error in reception flag
+  *     @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure flag
+  *     @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+  *     @arg I2C_IT_BERR: Bus error flag
+  *     @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+  *     @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+  *     @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+  *     @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+  *     @arg I2C_IT_BTF: Byte transfer finished flag
+  *     @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+  *                       Address matched flag (Slave mode)"ENDAD"
+  *     @arg I2C_IT_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_IT &= FLAG_MASK;
+
+  /* Check the status of the specified I2C flag */
+  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
+  *   This parameter can be any combination of the following values:
+  *     @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *     @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *     @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+  *     @arg I2C_IT_AF: Acknowledge failure interrupt
+  *     @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+  *     @arg I2C_IT_BERR: Bus error interrupt
+  *   
+
+  * @note STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *     to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  * @note ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
+  *     byte of the address in I2C_DR register.
+  * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *     operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
+  *     read/write to I2C_DR register (I2C_SendData()).
+  * @note ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
+  *     I2C_SR2 register ((void)(I2Cx->SR2)).
+  * @note SB (Start Bit) is cleared by software sequence: a read operation to 
+  *     I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *     I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+  /* Get the I2C flag position */
+  flagpos = I2C_IT & FLAG_MASK;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_iwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_iwdg.c
new file mode 100644
index 0000000..2769f2d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_iwdg.c
@@ -0,0 +1,266 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           + Prescaler and Counter configuration
+  *           + IWDG activation
+  *           + Flag management
+  *
+  *  @verbatim  
+  *  
+  ============================================================================== 
+                          ##### IWDG features #####
+  ============================================================================== 
+    [..] The IWDG can be started by either software or hardware (configurable
+         through option byte).
+             
+    [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+         thus stays active even if the main clock fails.
+         Once the IWDG is started, the LSI is forced ON and cannot be disabled
+         (LSI cannot be disabled too), and the counter starts counting down from 
+         the reset value of 0xFFF. When it reaches the end of count value (0x000)
+         a system reset is generated.
+         The IWDG counter should be reloaded at regular intervals to prevent
+         an MCU reset.
+                             
+    [..] The IWDG is implemented in the VDD voltage domain that is still functional
+         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+              
+    [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+         reset occurs.
+              
+    [..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
+         The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
+         devices provide the capability to measure the LSI frequency (LSI clock
+         connected internally to TIM10 CH1 input capture). The measured value
+         can be used to have an IWDG timeout with an acceptable accuracy. 
+         For more information, please refer to the STM32L1xx Reference manual.
+            
+                          ##### How to use this driver ##### 
+  ============================================================================== 
+    [..]
+    (#) Enable write access to IWDG_PR and IWDG_RLR registers using
+        IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+    (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+
+    (#) Configure the IWDG counter value using IWDG_SetReload() function.
+        This value will be loaded in the IWDG counter each time the counter
+        is reloaded, then the IWDG will start counting down from this value.
+
+    (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+        in software mode (no need to enable the LSI, it will be enabled
+        by hardware).
+
+    (#) Then the application program must reload the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        IWDG_ReloadCounter() function.
+
+    @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_iwdg.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+  ==============================================================================
+            ##### Prescaler and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *   This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+  ==============================================================================
+                          ##### IWDG activation function #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None.
+  * @retval None.
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Flag management function ##### 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_lcd.c
new file mode 100644
index 0000000..ab7702b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_lcd.c
@@ -0,0 +1,640 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_lcd.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the LCD controller (LCD) peripheral:
+  *           + Initialization and configuration
+  *           + LCD RAM memory write
+  *           + Interrupts and flags management
+  *           
+  *  @verbatim
+  
+ ===============================================================================
+                            ##### LCD Clock #####
+ ===============================================================================
+    [..] LCDCLK is the same as RTCCLK. 
+    [..] To configure the RTCCLK/LCDCLK, proceed as follows:
+         (+) Enable the Power Controller (PWR) APB1 interface clock using the
+             RCC_APB1PeriphClockCmd() function.
+         (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
+         (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+  
+    [..] The frequency generator allows you to achieve various LCD frame rates
+         starting from an LCD input clock frequency (LCDCLK) which can vary 
+         from 32 kHz up to 1 MHz.
+  
+                      ##### LCD and low power modes #####
+ ===============================================================================
+    [..] The LCD still active during STOP mode.
+  
+                      ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable LCD clock using 
+            RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function.
+        (#) Configure the LCD prescaler, divider, duty, bias and voltage source
+            using LCD_Init() function.
+        (#) Optionally you can enable/configure:
+            (++) LCD High Drive using the LCD_HighDriveCmd() function.
+            (++) LCD COM/SEG Mux using the LCD_MuxSegmentCmd() function.
+            (++) LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function.
+            (++) LCD Dead Time using the LCD_DeadTimeConfig() function  
+            (++) The LCD Blink mode and frequency using the LCD_BlinkConfig() function.
+            (++) The LCD Contrast using the LCD_ContrastConfig() function.
+        (#) Call the LCD_WaitForSynchro() function to wait for LCD_FCR register
+            synchronization.
+        (#) Call the LCD_Cmd() to enable the LCD controller.
+        (#) Wait until the LCD Controller status is enabled and the step-up
+            converter is ready using the LCD_GetFlagStatus() and
+            LCD_FLAG_ENS and LCD_FLAG_RDY flags.
+        (#) Write to the LCD RAM memory using the LCD_Write() function.
+        (#) Request an update display using the LCD_UpdateDisplayRequest()
+            function.
+        (#) Wait until the update display is finished by checking the UDD
+            flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD).
+  
+    @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup LCD 
+  * @brief LCD driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ LCD registers bit address in the alias region --------------- */
+#define LCD_OFFSET                   (LCD_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of LCDEN bit */
+#define CR_OFFSET                    (LCD_OFFSET + 0x00)
+#define LCDEN_BitNumber              0x00
+#define CR_LCDEN_BB                  (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))
+
+/* Alias word address of MUX_SEG bit */
+#define MUX_SEG_BitNumber            0x07
+#define CR_MUX_SEG_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))
+
+
+/* --- FCR Register ---*/
+
+/* Alias word address of HD bit */
+#define FCR_OFFSET                   (LCD_OFFSET + 0x04)
+#define HD_BitNumber                 0x00
+#define FCR_HD_BB                    (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))
+
+/* --- SR Register ---*/
+
+/* Alias word address of UDR bit */
+#define SR_OFFSET                    (LCD_OFFSET + 0x08)
+#define UDR_BitNumber                0x02
+#define SR_UDR_BB                    (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))
+
+#define FCR_MASK                     ((uint32_t)0xFC03FFFF)  /* LCD FCR Mask */
+#define CR_MASK                      ((uint32_t)0xFFFFFF81)  /* LCD CR Mask */
+#define PON_MASK                     ((uint32_t)0xFFFFFF8F)  /* LCD PON Mask */
+#define DEAD_MASK                    ((uint32_t)0xFFFFFC7F)  /* LCD DEAD Mask */
+#define BLINK_MASK                   ((uint32_t)0xFFFC1FFF)  /* LCD BLINK Mask */
+#define CONTRAST_MASK                ((uint32_t)0xFFFFE3FF)  /* LCD CONTRAST Mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LCD_Private_Functions
+  * @{
+  */
+
+/** @defgroup LCD_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the LCD peripheral registers to their default reset
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void LCD_DeInit(void)
+{
+  /* Enable LCD reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);
+  /* Release LCD from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);
+}
+
+/**
+  * @brief  Initializes the LCD peripheral according to the specified parameters
+  *         in the LCD_InitStruct.
+  * @note   This function can be used only when the LCD is disabled.
+  * @param  LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains
+  *         the configuration information for the specified LCD peripheral.
+  * @retval None
+  */
+void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));
+  assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));
+  assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));
+  assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias));
+  assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));
+
+  LCD->FCR &= (uint32_t)FCR_MASK;
+  LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);
+
+  LCD_WaitForSynchro();
+
+  LCD->CR &= (uint32_t)CR_MASK;
+  LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \
+                        LCD_InitStruct->LCD_VoltageSource);
+
+}
+
+/**
+  * @brief  Fills each LCD_InitStruct member with its default value.
+  * @param  LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)
+{
+/*--------------- Reset LCD init structure parameters values -----------------*/
+  LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */
+  
+  LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */
+  
+  LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */
+  
+  LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */
+  
+  LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */
+}
+
+/**
+  * @brief  Enables or disables the LCD Controller.
+  * @param  NewState: new state of the LCD peripheral.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_Cmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
+  *   This function must be called after any write operation to LCD_FCR register.
+  * @param  None
+  * @retval None
+  */
+void LCD_WaitForSynchro(void)
+{
+  /* Loop until FCRSF flag is set */
+  while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)
+  {
+  }
+}
+
+/**
+  * @brief  Enables or disables the low resistance divider. Displays with high
+  *         internal resistance may need a longer drive time to achieve
+  *         satisfactory contrast. This function is useful in this case if some
+  *         additional power consumption can be tolerated.
+  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
+  *         programmed to 1/CK_PS (LCD_PulseOnDuration_1).
+  * @param  NewState: new state of the low resistance divider.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_HighDriveCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Mux Segment.
+  * @note   This function can be used only when the LCD is disabled.
+  * @param  NewState: new state of the Mux Segment.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_MuxSegmentCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the LCD pulses on duration.
+  * @param  LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of
+  *         CK_PS (prescaled LCD clock period) pulses.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_PulseOnDuration_0: 0 pulse
+  *     @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS
+  *     @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS
+  *     @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS
+  *     @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS
+  *     @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS
+  *     @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS
+  *     @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS
+  * @retval None
+  */
+void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));
+
+  LCD->FCR &= (uint32_t)PON_MASK;
+  LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);
+}
+
+/**
+  * @brief  Configures the LCD dead time.
+  * @param  LCD_DeadTime: specifies the LCD dead time.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_DeadTime_0: No dead Time
+  *     @arg LCD_DeadTime_1: One Phase between different couple of Frame
+  *     @arg LCD_DeadTime_2: Two Phase between different couple of Frame
+  *     @arg LCD_DeadTime_3: Three Phase between different couple of Frame
+  *     @arg LCD_DeadTime_4: Four Phase between different couple of Frame
+  *     @arg LCD_DeadTime_5: Five Phase between different couple of Frame
+  *     @arg LCD_DeadTime_6: Six Phase between different couple of Frame 
+  *     @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
+  * @retval None
+  */
+void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
+
+  LCD->FCR &= (uint32_t)DEAD_MASK;
+  LCD->FCR |= (uint32_t)(LCD_DeadTime);
+}
+
+/**
+  * @brief  Configures the LCD Blink mode and Blink frequency.
+  * @param  LCD_BlinkMode: specifies the LCD blink mode.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_BlinkMode_Off:           Blink disabled
+  *     @arg LCD_BlinkMode_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
+  *     @arg LCD_BlinkMode_SEG0_AllCOM:   Blink enabled on SEG[0], all COM (up to 8
+  *                                       pixels according to the programmed duty)
+  *     @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM 
+  *                                       (all pixels)
+  * @param  LCD_BlinkFrequency: specifies the LCD blink frequency.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_BlinkFrequency_Div8:    The Blink frequency = fLcd/8
+  *     @arg LCD_BlinkFrequency_Div16:   The Blink frequency = fLcd/16
+  *     @arg LCD_BlinkFrequency_Div32:   The Blink frequency = fLcd/32
+  *     @arg LCD_BlinkFrequency_Div64:   The Blink frequency = fLcd/64
+  *     @arg LCD_BlinkFrequency_Div128:  The Blink frequency = fLcd/128
+  *     @arg LCD_BlinkFrequency_Div256:  The Blink frequency = fLcd/256
+  *     @arg LCD_BlinkFrequency_Div512:  The Blink frequency = fLcd/512
+  *     @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
+  * @retval None
+  */
+void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
+  assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
+  
+  LCD->FCR &= (uint32_t)BLINK_MASK;
+  LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);
+}
+
+/**
+  * @brief  Configures the LCD Contrast.
+  * @param  LCD_Contrast: specifies the LCD Contrast.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V
+  *     @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V
+  *     @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V
+  *     @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V
+  *     @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V
+  *     @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V
+  *     @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V
+  *     @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V
+  * @retval None
+  */
+void LCD_ContrastConfig(uint32_t LCD_Contrast)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_CONTRAST(LCD_Contrast));
+
+  LCD->FCR &= (uint32_t)CONTRAST_MASK;
+  LCD->FCR |= (uint32_t)(LCD_Contrast);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Group2  LCD RAM memory write functions
+ *  @brief    LCD RAM memory write functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### LCD RAM memory write functions #####
+ ===============================================================================
+    [..] Using its double buffer memory the LCD controller ensures the coherency 
+         of the displayed information without having to use interrupts to control 
+         LCD_RAM modification.
+
+    [..] The application software can access the first buffer level (LCD_RAM) through
+         the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag 
+         in the LCD_SR register using the LCD_UpdateDisplayRequest() function.
+
+    [..] This UDR flag (update display request) requests the updated information 
+         to be moved into the second buffer level (LCD_DISPLAY).
+
+    [..] This operation is done synchronously with the frame (at the beginning of 
+         the next frame), until the update is completed, the LCD_RAM is write 
+         protected and the UDR flag stays high.
+
+    [..] Once the update is completed another flag (UDD - Update Display Done) is 
+         set and generates an interrupt if the UDDIE bit in the LCD_FCR register 
+        is set.
+
+    [..] The time it takes to update LCD_DISPLAY is, in the worst case, one odd 
+         and one even frame.
+
+    [..] The update will not occur (UDR = 1 and UDD = 0) until the display is
+         enabled (LCDEN = 1).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a word in the specific LCD RAM.
+  * @param  LCD_RAMRegister: specifies the LCD Contrast.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_RAMRegister_0: LCD RAM Register 0
+  *     @arg LCD_RAMRegister_1: LCD RAM Register 1
+  *     @arg LCD_RAMRegister_2: LCD RAM Register 2
+  *     @arg LCD_RAMRegister_3: LCD RAM Register 3
+  *     @arg LCD_RAMRegister_4: LCD RAM Register 4
+  *     @arg LCD_RAMRegister_5: LCD RAM Register 5
+  *     @arg LCD_RAMRegister_6: LCD RAM Register 6
+  *     @arg LCD_RAMRegister_7: LCD RAM Register 7
+  *     @arg LCD_RAMRegister_8: LCD RAM Register 8
+  *     @arg LCD_RAMRegister_9: LCD RAM Register 9
+  *     @arg LCD_RAMRegister_10: LCD RAM Register 10
+  *     @arg LCD_RAMRegister_11: LCD RAM Register 11
+  *     @arg LCD_RAMRegister_12: LCD RAM Register 12
+  *     @arg LCD_RAMRegister_13: LCD RAM Register 13
+  *     @arg LCD_RAMRegister_14: LCD RAM Register 14
+  *     @arg LCD_RAMRegister_15: LCD RAM Register 15
+  * @param  LCD_Data: specifies LCD Data Value to be written.
+  * @retval None
+  */
+void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
+
+  /* Copy data bytes to RAM register */
+  LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;
+}
+
+/**
+  * @brief  Enables the Update Display Request.
+  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to
+  *         transfer the updated data to the second level buffer.
+  *         The UDR bit stays set until the end of the update and during this
+  *         time the LCD_RAM is write protected.
+  * @note   When the display is disabled, the update is performed for all
+  *         LCD_DISPLAY locations.
+  *         When the display is enabled, the update is performed only for locations
+  *         for which commons are active (depending on DUTY). For example if
+  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
+  * @param  None
+  * @retval None
+  */
+void LCD_UpdateDisplayRequest(void)
+{
+  *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified LCD interrupts.
+  * @param  LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @param NewState: new state of the specified LCD interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_IT(LCD_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    LCD->FCR |= LCD_IT;
+  }
+  else
+  {
+    LCD->FCR &= (uint32_t)~LCD_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified LCD flag is set or not.
+  * @param  LCD_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
+  *      @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR
+  *             goes from 0 to 1. On deactivation it reflects the real status of
+  *             LCD so it becomes 0 at the end of the last displayed frame.
+  *     @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
+  *       the beginning of a new frame, at the same time as the display data is
+  *       updated.
+  *     @arg LCD_FLAG_UDR: Update Display Request flag.
+  *     @arg LCD_FLAG_UDD: Update Display Done flag.
+  *     @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
+  *                        of the step-up converter.
+  *     @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
+  *       This flag is set by hardware each time the LCD_FCR register is updated
+  *       in the LCDCLK domain.
+  * @retval The new state of LCD_FLAG (SET or RESET).
+  */
+FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_LCD_GET_FLAG(LCD_FLAG));
+  
+  if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the LCD's pending flags.
+  * @param  LCD_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg LCD_FLAG_SOF: Start of Frame Interrupt
+  *     @arg LCD_FLAG_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+void LCD_ClearFlag(uint32_t LCD_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));
+    
+  /* Clear the corresponding LCD flag */
+  LCD->CLR = (uint32_t)LCD_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  LCD_IT: specifies the LCD interrupts sources to check.
+  *   This parameter can be one of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt.
+  *     @note If the device is in STOP mode (PCLK not provided) UDD will not 
+  *          generate an interrupt even if UDDIE = 1. 
+  *          If the display is not enabled the UDD interrupt will never occur.
+  * @retval The new state of the LCD_IT (SET or RESET).
+  */
+ITStatus LCD_GetITStatus(uint32_t LCD_IT)
+{
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_LCD_GET_IT(LCD_IT));
+    
+  if ((LCD->SR & LCD_IT) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the LCD's interrupt pending bits.
+  * @param  LCD_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg LCD_IT_SOF: Start of Frame Interrupt
+  *     @arg LCD_IT_UDD: Update Display Done Interrupt
+  * @retval None
+  */
+void LCD_ClearITPendingBit(uint32_t LCD_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_LCD_IT(LCD_IT));
+  
+  /* Clear the corresponding LCD pending bit */
+  LCD->CLR = (uint32_t)LCD_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_opamp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_opamp.c
new file mode 100644
index 0000000..5483560
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_opamp.c
@@ -0,0 +1,557 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_opamp.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the operational amplifiers (opamp) peripheral:
+  *           + Initialization and configuration
+  *           + Calibration management
+  *          
+  *  @verbatim
+  ==============================================================================
+                            ##### How to use this driver #####
+  ==============================================================================
+    [..] The device integrates three independent rail-to-rail operational amplifiers
+         OPAMP1, OPAMP2 and OPAMP3:
+               (+) Internal connections to the ADC.
+               (+) Internal connections to the DAC.
+               (+) Internal connection to COMP1 (only OPAMP3).
+               (+) Internal connection for unity gain (voltage follower) configuration.
+               (+) Calibration capability.
+               (+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).
+    [..]    
+         (#) COMP AHB clock must be enabled to get write access
+             to OPAMP registers using
+         (#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)
+  
+         (#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)
+             and OPAMPx_OUT in analog mode.
+   
+         (#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()
+
+         (#) Enable the OPAMP peripheral using OPAMP_Cmd()
+
+         -@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled
+             and the ADC must use the OPAMP output channel number:
+             (+@) OPAMP1 output is connected to ADC channel 3.
+             (+@) OPAMP2 output is connected to ADC channel 8.
+             (+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).
+
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_opamp.h"
+
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup OPAMP 
+  * @brief OPAMP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup OPAMP_Group1 Initialization and configuration
+ *  @brief   Initialization and configuration
+ *
+@verbatim   
+ ===============================================================================
+                            ##### Initialization and configuration #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */  
+
+/**
+  * @brief  Deinitialize the OPAMPs register to its default reset value.
+  * @note   At startup, OTR and LPOTR registers are set to factory programmed values.
+  * @param  None.
+  * @retval None.
+  */
+void OPAMP_DeInit(void)
+{
+  /*!< Set OPAMP_CSR register to reset value */
+  OPAMP->CSR = 0x00010101;
+  /*!< Set OPAMP_OTR register to reset value */
+  OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);
+  /*!< Set OPAMP_LPOTR register to reset value */
+  OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);
+}
+
+/**
+  * @brief  Close or Open the OPAMP switches.
+  * @param  OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.
+  *   This parameter can be any combinations of the following values:
+  *     @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to 
+  *                               OPAMP1 negative input (internal follower)
+  *     @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
+  *     @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
+  *     @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
+  *     @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
+  *     @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to 
+  *                               OPAMP2 negative input (internal follower)
+  *     @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
+  *     @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
+  *     @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
+  *     @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
+  *     @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
+  *     @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to 
+  *                               OPAMP3 negative input (internal follower)
+  *     @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
+  *     @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
+  *     @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
+  *     @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
+  *
+  * @param  NewState: New state of the OPAMP switch. 
+  *   This parameter can be:
+  *     ENABLE to close the OPAMP switch
+  *     or DISABLE to open the OPAMP switch
+  * @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
+  * @retval None
+  */
+void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Close the selected switches */
+    OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;
+  }
+  else
+  {
+    /* Open the selected switches */
+    OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);
+  }
+}
+
+/**
+  * @brief  Enable or disable the OPAMP peripheral.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *   This parameter can be one of the following values:
+  *     @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected
+  *     @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected
+  *     @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected
+  * @param  NewState: new state of the selected OPAMP peripheral. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected OPAMP */
+    OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);
+  }
+  else
+  {
+    /* Disable the selected OPAMP */
+    OPAMP->CSR |= (uint32_t) OPAMP_Selection;
+  }
+}
+
+/**
+  * @brief  Enable or disable the low power mode for OPAMP peripheral.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *   This parameter can be one of the following values:
+  *     @arg OPAMP_Selection_OPAMP1: OPAMP1 selected
+  *     @arg OPAMP_Selection_OPAMP2: OPAMP2 selected
+  *     @arg OPAMP_Selection_OPAMP3: OPAMP3 selected
+  * @param  NewState: new low power state of the selected OPAMP peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the selected OPAMP in low power mode */
+    OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);
+  }
+  else
+  {
+    /* Disable the low power mode for the selected OPAMP */
+    OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));
+  }
+}
+
+/**
+  * @brief  Select the OPAMP power range.
+  * @note   The OPAMP power range selection must be performed while OPAMPs are powered down.
+  * @param  OPAMP_Range: the selected OPAMP power range. 
+  *   This parameter can be one of the following values:
+  *     @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
+  *     @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
+  * @retval None
+  */
+void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));
+
+  /* Reset the OPAMP range bit */
+  OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));
+
+  /* Select the OPAMP power range */
+  OPAMP->CSR |= OPAMP_PowerRange;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup OPAMP_Group2 Calibration functions
+ *  @brief   Calibration functions
+ *
+@verbatim   
+ ===============================================================================
+                            ##### Calibration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Select the trimming mode.
+  * @param  OffsetTrimming: the selected offset trimming mode. 
+  *   This parameter  can be one of the following values:
+  *     @arg OffsetTrimming_Factory: factory trimming values are used for offset
+  *                                  calibration.
+  *     @arg OffsetTrimming_User: user trimming values are used for offset
+  *                               calibration.
+  * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
+  *       function or OPAMP_OffsetTrimLowPowerConfig() function to adjust 
+  *       trimming value.
+  * @retval None
+  */
+void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)
+{
+  /* Check the parameter */
+  assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
+
+  /* Reset the OPAMP_OTR range bit */
+  OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));
+
+  /* Select the OPAMP offset trimming  */
+  OPAMP->CSR |= OPAMP_Trimming;
+
+}
+
+/**
+  * @brief  Configure the trimming value of OPAMPs in normal mode.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *   This parameter can be one of the following values:
+  *         @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
+  *         @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
+  *         @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
+  * @param  OPAMP_Input: the selected OPAMP input. 
+  *   This parameter can be one of the following values:
+  *         @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
+  *         @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
+  * @param  OPAMP_TrimValue: the trimming value. This parameter can be any value lower
+  *         or equal to 0x0000001F. 
+  * @retval None
+  */
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_INPUT(OPAMP_Input));
+  assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
+
+  /* Get the OPAMP_OTR value */
+  tmpreg = OPAMP->OTR;
+
+  if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= OPAMP_Input;
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP1 PMOS input */
+      tmpreg &= (0xFFFFFFE0);
+      /* Set the new trimming value corresponding to OPAMP1 PMOS input */
+      tmpreg |= (OPAMP_TrimValue);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP1 NMOS input */
+      tmpreg &= (0xFFFFFC1F);
+      /* Set the new trimming value corresponding to OPAMP1 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<5);
+    }
+  }
+  else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= (uint32_t)(OPAMP_Input<<8);
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP2 PMOS input */
+      tmpreg &= (0xFFFF83FF);
+      /* Set the new trimming value corresponding to OPAMP2 PMOS input */
+      tmpreg |= (OPAMP_TrimValue<<10);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP2 NMOS input */
+      tmpreg &= (0xFFF07FFF);
+      /* Set the new trimming value corresponding to OPAMP2 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<15);
+    }
+  }
+  else
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= (uint32_t)(OPAMP_Input<<16);
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP3 PMOS input */
+      tmpreg &= (0xFE0FFFFF);
+      /* Set the new trimming value corresponding to OPAMP3 PMOS input */
+      tmpreg |= (OPAMP_TrimValue<<20);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP3 NMOS input */
+      tmpreg &= (0xC1FFFFFF);
+      /* Set the new trimming value corresponding to OPAMP3 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<25);
+    }
+  }
+
+  /* Set the OPAMP_OTR register */
+  OPAMP->OTR = tmpreg;
+}
+
+/**
+  * @brief  Configure the trimming value of OPAMPs in low power mode.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *   This parameter can be one of the following values:
+  *         @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
+  *         @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
+  *         @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
+  * @param  OPAMP_Input: the selected OPAMP input. 
+  *   This parameter can be one of the following values:
+  *         @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
+  *         @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
+  * @param  OPAMP_TrimValue: the trimming value. 
+  *    This parameter can be any value lower or equal to 0x0000001F. 
+  * @retval None
+  */
+void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  assert_param(IS_OPAMP_INPUT(OPAMP_Input));
+  assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
+
+  /* Get the OPAMP_LPOTR value */
+  tmpreg = OPAMP->LPOTR;
+
+  if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= OPAMP_Input;
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP1 PMOS input */
+      tmpreg &= (0xFFFFFFE0);
+      /* Set the new trimming value corresponding to OPAMP1 PMOS input */
+      tmpreg |= (OPAMP_TrimValue);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP1 NMOS input */
+      tmpreg &= (0xFFFFFC1F);
+      /* Set the new trimming value corresponding to OPAMP1 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<5);
+    }
+  }
+  else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= (uint32_t)(OPAMP_Input<<8);
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP2 PMOS input */
+      tmpreg &= (0xFFFF83FF);
+      /* Set the new trimming value corresponding to OPAMP2 PMOS input */
+      tmpreg |= (OPAMP_TrimValue<<10);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP2 NMOS input */
+      tmpreg &= (0xFFF07FFF);
+      /* Set the new trimming value corresponding to OPAMP2 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<15);
+    }
+  }
+  else
+  {
+    /* Reset the OPAMP inputs selection */
+    tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
+    /* Select the OPAMP input */
+    tmpreg |= (uint32_t)(OPAMP_Input<<16);
+
+    if(OPAMP_Input == OPAMP_Input_PMOS)
+    {
+      /* Reset the trimming value corresponding to OPAMP3 PMOS input */
+      tmpreg &= (0xFE0FFFFF);
+      /* Set the new trimming value corresponding to OPAMP3 PMOS input */
+      tmpreg |= (OPAMP_TrimValue<<20);
+    }
+    else
+    {
+      /* Reset the trimming value corresponding to OPAMP3 NMOS input */
+      tmpreg &= (0xC1FFFFFF);
+      /* Set the new trimming value corresponding to OPAMP3 NMOS input */
+      tmpreg |= (OPAMP_TrimValue<<25);
+    }
+  }
+
+  /* Set the OPAMP_LPOTR register */
+  OPAMP->LPOTR = tmpreg;
+}
+
+/**
+  * @brief  Checks whether the specified OPAMP calibration flag is set or not.
+  * @note   User should wait until calibration flag change the value when changing
+  *         the trimming value.
+  * @param  OPAMP_Selection: the selected OPAMP. 
+  *   This parameter can be one of the following values:
+  *     @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.
+  *     @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.
+  *     @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.
+  * @retval The new state of the OPAMP calibration flag (SET or RESET).
+  */
+FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+  
+  /* Get the CSR register value */
+  tmpreg = OPAMP->CSR;
+
+  /* Check if OPAMP1 is selected */
+  if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
+  {
+    /* Check OPAMP1 CAL bit status */
+    if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  /* Check if OPAMP2 is selected */
+  else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)
+  {
+    /* Check OPAMP2 CAL bit status */
+    if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    } 
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* Check OPAMP3 CAL bit status */
+    if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
new file mode 100644
index 0000000..15b4788
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c
@@ -0,0 +1,833 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_pwr.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           + RTC Domain Access
+  *           + PVD configuration
+  *           + WakeUp pins configuration
+  *           + Ultra Low Power mode configuration
+  *           + Voltage Scaling configuration
+  *           + Low Power modes configuration
+  *           + Flags management
+  *               
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of ULP bit */
+#define ULP_BitNumber           0x09
+#define CR_ULP_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
+
+/* Alias word address of FWU bit */
+#define FWU_BitNumber           0x0A
+#define CR_FWU_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+#define CR_VOS_MASK              ((uint32_t)0xFFFFE7FF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 RTC Domain Access function 
+ *  @brief   RTC Domain Access function  
+ *
+@verbatim   
+  ============================================================================== 
+                     ##### RTC Domain Access function #####
+  ============================================================================== 
+
+    [..] After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup 
+         registers) are protected against possible stray write accesses.
+    [..] To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @note   Before calling this function, the VOS[1:0] bits should be configured 
+  *         to "10" and the system frequency has to be configured accordingly. 
+  *         To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
+  *         function.
+  * @note   ULP and FWU bits are not reset by this function.    
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the RTC and backup registers.
+  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the 
+  *         RTC Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the RTC and backup registers.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_RTCAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+                    ##### PVD configuration functions #####
+  ==============================================================================    
+  [..]
+  (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
+      selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+  (+) The PVD can use an external input analog voltage (PVD_IN) which is compared 
+      internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode 
+      when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
+  (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+      PVD threshold. This event is internally connected to the EXTI line16
+      and can generate an interrupt if enabled through the EXTI registers.
+  (+) The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_PVDLevel_0: PVD detection level set to 1.9V.
+  *     @arg PWR_PVDLevel_1: PVD detection level set to 2.1V.
+  *     @arg PWR_PVDLevel_2: PVD detection level set to 2.3V.
+  *     @arg PWR_PVDLevel_3: PVD detection level set to 2.5V.
+  *     @arg PWR_PVDLevel_4: PVD detection level set to 2.7V.
+  *     @arg PWR_PVDLevel_5: PVD detection level set to 2.9V.
+  *     @arg PWR_PVDLevel_6: PVD detection level set to 3.1V.
+  *     @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pins configuration functions
+ *  @brief   WakeUp pins configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+               ##### WakeUp pin configuration functions #####
+  ==============================================================================   
+
+  (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are 
+      forced in input pull down configuration and are active on rising edges.
+  (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
+      WakeUp Pin 3 on PE.06.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
+  *   This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
+  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  tmp = CSR_EWUP_BB + PWR_WakeUpPin;
+  
+  *(__IO uint32_t *) (tmp) = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions
+ *  @brief   Ultra Low Power mode configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+             ##### Ultra Low Power mode configuration functions #####
+  ==============================================================================   
+  [..]
+  (+) The internal voltage reference consumption is not negligible, in particular 
+      in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()
+      function (ULP bit (Ultra low power) in the PWR_CR register) to disable the 
+      internal voltage reference. However, in this case, when exiting from the 
+      Stop/Standby mode, the functions managed through the internal voltage reference 
+      are not reliable during the internal voltage reference startup time (up to 3 ms).
+      To reduce the wakeup time, the device can exit from Stop/Standby mode without 
+      waiting for the internal voltage reference startup time. This is performed 
+      by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
+      wakeup) in the PWR_CR register) before entering Stop/Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.
+  * @param  NewState: new state of the Fast WakeUp  functionality.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_FastWakeUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Ultra Low Power mode.
+  * @param  NewState: new state of the Ultra Low Power mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_UltraLowPowerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group5 Voltage Scaling configuration functions
+ *  @brief   Voltage Scaling configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+              ##### Voltage Scaling configuration functions #####
+  ==============================================================================  
+
+    (+) The dynamic voltage scaling is a power management technique which consists in 
+        increasing or decreasing the voltage used for the digital peripherals (VCORE), 
+        according to the circumstances.
+   
+   [..] Depending on the device voltage range, the maximum frequency and FLASH wait
+        state should be adapted accordingly:
+   [..] 
+        +------------------------------------------------------------------+     
+        |   Wait states   |                HCLK clock frequency (MHz)      |
+        |                 |------------------------------------------------|     
+        |    (Latency)    |            voltage range       | voltage range | 
+        |                 |            1.65 V - 3.6 V      | 2.0 V - 3.6 V |
+        |                 |----------------|---------------|---------------|
+        |                 |     Range 3    |    Range 2    |    Range 1    |
+        |                 |  VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
+        |---------------- |----------------|---------------|---------------|             
+        | 0WS(1CPU cycle) |0 < HCLK <= 2   |0 < HCLK <= 8  |0 < HCLK <= 16 |
+        |-----------------|----------------|---------------|---------------|  
+        | 1WS(2CPU cycle) |2 < HCLK <= 4   |8 < HCLK <= 16 |16 < HCLK <= 32|
+        |-----------------|----------------|---------------|---------------|  
+        | CPU Performance |      Low       |     Medium    |     High      |
+        |-----__----------|----------------|---------------|---------------|  
+        |Power Performance|      High      |     Medium    |      Low      |                 
+        +------------------------------------------------------------------+    
+
+    (+) To modify the Product voltage range, user application has to:
+        (++) Check VDD to identify which ranges are allowed (see table above).
+        (++) Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() 
+             function and wait until it is  reset.
+        (++) Configure the Voltage range using the PWR_VoltageScalingConfig() function.
+
+    (+) When VCORE range 1 is selected and VDD drops below 2.0 V, the application must
+        reconfigure the system:
+        (++) Detect that VDD drops below 2.0 V using the PVD Level 1.
+        (++) Adapt the clock frequency to the voltage range that will be selected at next step.
+        (++) Select the required voltage range.
+        (++) When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system
+             reconfiguration is required.
+ 
+    (+) When VDD is above 2.0 V, any of the 3 voltage ranges can be selected.
+        (++) When the voltage range is above the targeted voltage range (e.g. from range 
+             1 to 2).
+        (++) Adapt the clock frequency to the lower voltage range that will be selected 
+             at next step.
+        (++) Select the required voltage range.
+        (++) When the voltage range is below the targeted voltage range (e.g. from range 
+             3 to 1).
+        (++) Select the required voltage range.
+        (++) Tune the clock frequency if needed.
+ 
+    (+) When VDD is below 2.0 V, only range 2 and 3 can be selected:
+        (++) From range 2 to range 3.
+             (+++) Adapt the clock frequency to voltage range 3.
+             (+++) Select voltage range 3.
+        (++) From range 3 to range 2.
+             (+++) Select the voltage range 2.
+             (+++) Tune the clock frequency if needed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage scaling range.
+  * @note   During voltage scaling configuration, the system clock is stopped 
+  *         until the regulator is stabilized (VOSF = 0). This must be taken 
+  *         into account during application developement, in case a critical 
+  *         reaction time to interrupt is needed, and depending on peripheral 
+  *         used (timer, communication,...).
+  *             
+  * @param  PWR_VoltageScaling: specifies the voltage scaling range.
+  *   This parameter can be:
+  *     @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).
+  *     @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).
+  *     @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) 
+  * @retval None
+  */
+void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
+  
+  tmp = PWR->CR;
+
+  tmp &= CR_VOS_MASK;
+  tmp |= PWR_VoltageScaling;
+  
+  PWR->CR = tmp & 0xFFFFFFF3;
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group6 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim   
+  ============================================================================== 
+              ##### Low Power modes configuration functions #####
+  ==============================================================================    
+
+    [..] The devices feature five low-power modes:
+    (+) Low power run mode: regulator in low power mode, limited clock frequency, 
+        limited number of peripherals running.
+    (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
+    (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, 
+        limited number of peripherals running, regulator in low power mode.
+    (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode.
+    (+) Standby mode: VCORE domain powered off.
+   
+  *** Low power run mode (LP run) *** 
+  ===================================
+      [..]
+    (+) Entry:
+        (++) Decrease the system frequency.
+        (++) The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()
+             function.
+    (+) Exit:
+        (++) The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()
+             function.
+        (++) Increase the system frequency if needed.
+
+  *** Sleep mode *** 
+  ==================
+  [..] 
+    (+) Entry:
+        (++) The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) 
+             function with regulator ON.
+    (+) Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
+             controller (NVIC) can wake up the device from Sleep mode.
+
+  *** Low power sleep mode (LP sleep) *** 
+  =======================================
+  [..] 
+    (+) Entry:
+        (++) The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()
+             function.
+        (++) Decrease the system frequency.
+        (++) The regulator is forced in low power mode and the WFI or WFE instructions
+             are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function 
+             with regulator in LowPower.
+    (+) Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
+             controller (NVIC) can wake up the device from Sleep LP mode.
+
+  *** Stop mode *** 
+  =================
+  [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
+       the HSI and the HSE RC oscillators are disabled. Internal SRAM and register 
+       contents are preserved.
+       The voltage regulator can be configured either in normal or low-power mode.
+       To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
+       sensor can be switched off before entering the Stop mode. They can be switched 
+       on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()
+       function. 
+   
+    (+) Entry:
+        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+             function with regulator in LowPower or with Regulator ON.
+    (+) Exit:
+        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+      
+  *** Standby mode *** 
+  ====================
+  [..] The Standby mode allows to achieve the lowest power consumption. It is based 
+       on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. 
+       The VCORE domain is consequently powered off. The PLL, the MSI, the HSI 
+       oscillator and the HSE oscillator are also switched off. SRAM and register 
+       contents are lost except for the RTC registers, RTC backup registers and 
+       Standby circuitry.
+   
+  [..] The voltage regulator is OFF.
+   
+  [..] To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
+       sensor can be switched off before entering the Standby mode. They can be switched 
+       on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()
+       function. 
+   
+    (+) Entry:
+        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    (+) Exit:
+        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+            tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+  *** Auto-wakeup (AWU) from low-power mode *** 
+  =============================================
+  [..]The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+      without depending on an external interrupt (Auto-wakeup mode).
+
+    (+) RTC auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
+             (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt 
+                   or Event modes) using the EXTI_Init() function.
+             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
+             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+    (+) RTC auto-wakeup (AWU) from the Standby mode
+        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
+             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                   and RTC_AlarmCmd() functions.
+        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                   function.
+             (+++) Configure the RTC to detect the tamper or time stamp event using the
+                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                   functions.
+        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
+             (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+             (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+                   RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+    (+) Comparator auto-wakeup (AWU) from the Stop mode
+        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
+             event, it is necessary to:
+             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 
+                   to be sensitive to to the selected edges (falling, rising or falling 
+                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+             (+++) Configure the comparator to generate the event.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters/Exits the Low Power Run mode.
+  * @note   Low power run mode can only be entered when VCORE is in range 2.
+  *         In addition, the dynamic voltage scaling must not be used when Low 
+  *         power run mode is selected. Only Stop and Sleep modes with regulator 
+  *         configured in Low power mode is allowed when Low power run mode is 
+  *         selected.  
+  * @note   In Low power run mode, all I/O pins keep the same state as in Run mode.
+  * @param  NewState: new state of the Low Power Run mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_EnterLowPowerRunMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    PWR->CR |= PWR_CR_LPSDSR;
+    PWR->CR |= PWR_CR_LPRUN;     
+  }
+  else
+  {
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); 
+    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);  
+  }  
+}
+
+/**
+  * @brief  Enters Sleep mode.
+  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.  
+  * @param  PWR_Regulator: specifies the regulator state in Sleep mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: Sleep mode with regulator ON
+  *     @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
+  * @note   Low power sleep mode can only be entered when VCORE is in range 2.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Low power sleep mode.
+  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
+  *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+
+  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
+  
+  /* Select the regulator state in Sleep mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+}
+
+/**
+  * @brief  Enters STOP mode.
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the MSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_Regulator_ON: STOP mode with regulator ON.
+  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.
+  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *         Reset pad (still available) 
+  *         RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, 
+  *         time-stamp, RTC Alarm out, or RTC clock calibration out.
+  *         WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.       
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP;
+  
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group7 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+                       ##### Flags management functions #####
+  ==============================================================================   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *       was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), 
+  *       RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *     @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                       resumed from StandBy mode.    
+  *     @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *       by the PWR_PVDCmd() function.
+  *     @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This 
+  *       flag indicates the state of the internal voltage reference, VREFINT.
+  *     @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for 
+  *       the internal regulator to be ready after the voltage range is changed.
+  *       The VOSF flag indicates that the regulator has reached the voltage level 
+  *       defined with bits VOS[1:0] of PWR_CR register.
+  *     @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware 
+  *       when the MCU is in Low power run mode.
+  *       When the MCU exits from Low power run mode, this flag stays SET until 
+  *       the regulator is ready in main mode. A polling on this flag is 
+  *       recommended to wait for the regulator main mode. 
+  *       This flag is RESET by hardware when the regulator is ready.       
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *   This parameter can be one of the following values:
+  *     @arg PWR_FLAG_WU: Wake Up flag
+  *     @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rtc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rtc.c
new file mode 100644
index 0000000..0cd7c5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rtc.c
@@ -0,0 +1,2675 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_rtc.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization
+  *           + Calendar (Time and Date) configuration
+  *           + Alarms (Alarm A and Alarm B) configuration
+  *           + WakeUp Timer configuration
+  *           + Daylight Saving configuration
+  *           + Output pin Configuration
+  *           + Coarse digital Calibration configuration
+  *           + Smooth digital Calibration configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + Output Type Config configuration
+  *           + Shift control synchronisation  
+  *           + Interrupts and flags management       
+  *                     
+ @verbatim
+
+ ===============================================================================
+                        ##### RTC Domain Reset #####
+ ===============================================================================
+    [..] After power-on reset, the RTC domain (RTC clock source configuration,
+         RTC registers and RTC Backup data registers) is reset. You can also
+         reset this domain by software using the RCC_RTCResetCmd() function.
+
+                    ##### RTC Operating Condition #####
+ ===============================================================================
+    [..] As long as the supply voltage remains in the operating range, 
+         the RTC never stops, regardless of the device status (Run mode, 
+         low power modes or under reset).
+
+                       ##### RTC Domain Access #####
+ ===============================================================================
+    [..] After reset, the RTC domain (RTC clock source configuration,
+         RTC registers and RTC Backup data registers) are protected against 
+         possible stray write accesses. 
+    [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+         (+) Enable the Power Controller (PWR) APB1 interface clock using the
+             RCC_APB1PeriphClockCmd() function.
+         (+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
+         (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+         (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (+) Enable the RTC domain access (see description in the section above)
+        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
+            RTC hour format using the RTC_Init() function.
+ ***Time and Date configuration ***
+ ==================================
+    [..]
+        (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+            and RTC_SetDate() functions.
+        (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+            functions.
+        (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
+        (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+            hour to the RTC Calendar.    
+
+ ***Alarm configuration ***
+ ==========================
+    [..]
+        (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+        (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
+        (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+        (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+
+ ***RTC Wakeup configuration ***
+ ===============================
+    [..]
+        (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+            function.
+        (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+            function.
+        (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+        (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+            function.
+
+ ***Outputs configuration ***
+ ============================
+    [..] The RTC has 2 different outputs:
+        (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+            and WaKeUp signals.
+            To output the selected RTC signal on RTC_AF1 pin, use the 
+            RTC_OutputConfig() function.
+        (+) AFO_CALIB: this output is 512Hz signal or 1Hz.
+            To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
+            function.
+
+ ***Smooth digital Calibration configuration ***
+ ===============================================
+    [..]
+        (+) Configure the RTC Original Digital Calibration Value and the corresponding
+            calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() 
+            function.
+
+ ***Coarse digital Calibration configuration ***
+ ===============================================
+    [..]
+        (+) Configure the RTC Coarse Calibration Value and the corresponding
+            sign using the RTC_CoarseCalibConfig() function.
+        (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() 
+            function.
+
+ ***TimeStamp configuration ***
+ ==============================
+    [..]
+        (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp 
+            using the RTC_TimeStampCmd() function.
+        (+) To read the RTC TimeStamp Time and Date register, use the 
+            RTC_GetTimeStamp() function.
+        (+) To read the RTC TimeStamp SubSecond register, use the 
+            RTC_GetTimeStampSubSecond() function.
+
+ ***Tamper configuration ***
+ ===========================
+    [..]
+        (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+            function. 
+        (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+            filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() 
+            function.
+        (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+            function.
+        (+) Configure the Tamper precharge or discharge duration using 
+            RTC_TamperPinsPrechargeDuration() function.
+        (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+        (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+        (+) Enable the Time stamp on Tamper detection event using  
+            RTC_TSOnTamperDetecCmd() function.     
+
+ ***Backup Data Registers configuration ***
+ ==========================================
+    [..]
+        (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+            function.  
+        (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+            function.  
+
+                       ##### RTC and low power modes #####
+ ===============================================================================
+    [..] The MCU can be woken up from a low power mode by an RTC alternate 
+         function.
+    [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+         RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+         These RTC alternate functions can wake up the system from the Stop 
+         and Standby lowpower modes.
+         The system can also wake up from low power modes without depending 
+         on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+         or the RTC wakeup events.
+    [..] The RTC provides a programmable time base for waking up from the 
+         Stop or Standby mode at regular intervals.
+         Wakeup from STOP and Standby modes is possible only when the RTC 
+         clock source is LSE or LSI.
+
+               ##### Selection of RTC_AF1 alternate functions #####
+ ===============================================================================
+    [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
+         (+) Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function.
+         (+) AFO_ALARM output.
+         (+) AFO_CALIB output.
+         (+) AFI_TAMPER.
+         (+) AFI_TIMESTAMP.
+
+   +------------------------------------------------------------------------------------------+
+   |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2  |ALARMOUTTYPE  |
+   |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |ENABLED |  AFO_ALARM   |
+   |  and function   |          |          |           |              |        |Configuration |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output OD     |     1    |    0     |Don't care | Don't care   | care   |      0       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |   Alarm out     |          |          |           |              | Don't  |              |
+   |   output PP     |     1    |    0     |Don't care | Don't care   | care   |      1       |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | Calibration out |          |          |           |              | Don't  |              |
+   |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TAMPER input   |          |          |           |              | Don't  |              |
+   |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  TIMESTAMP and  |          |          |           |              | Don't  |              |
+   |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
+   |   floating      |          |          |           |              |        |              |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   | TIMESTAMP input |          |          |           |              | Don't  |              |
+   |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  Wakeup Pin 2   |     0    |    0     |     0     |      0       |   1    |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|--------|--------------|
+   |  Standard GPIO  |     0    |    0     |     0     |      0       |   0    |  Don't care  |
+   +------------------------------------------------------------------------------------------+
+
+ @endverbatim
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+                                            RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | RTC_FLAG_RECALPF | \
+                                            RTC_FLAG_SHPF))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00002000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00002000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to initialize and configure the 
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
+         RTC registers Write protection, enter and exit the RTC initialization mode, 
+         RTC registers synchronization check and reference clock detection enable.
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. 
+             It is split into 2 programmable prescalers to minimize power consumption.
+             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+             (++) When both prescalers are used, it is recommended to configure the 
+                 asynchronous prescaler to a high value to minimize consumption.
+         (#) All RTC registers are Write protected. Writing to the RTC registers
+             is enabled by writing a key into the Write Protection register, RTC_WPR.
+         (#) To Configure the RTC Calendar, user application should enter 
+             initialization mode. In this mode, the calendar counter is stopped 
+             and its value can be updated. When the initialization sequence is 
+             complete, the calendar restarts counting after 4 RTCCLK cycles.
+         (#) To read the calendar through the shadow registers after Calendar 
+             initialization, calendar update or after wakeup from low power modes 
+             the software must first clear the RSF flag. The software must then 
+             wait until it is set again before reading the calendar, which means 
+             that the calendar registers have been correctly copied into the 
+             RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function 
+             implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR = (uint32_t)0x00000000;
+    RTC->DR = (uint32_t)0x00002101;
+    
+    /* Reset All CR bits except CR[2:0] */
+    RTC->CR &= (uint32_t)0x00000007;
+  
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Reset all RTC CR register bits */
+      RTC->CR        &= (uint32_t)0x00000000;
+      RTC->WUTR      = (uint32_t)0x0000FFFF;
+      RTC->PRER      = (uint32_t)0x007F00FF;
+      RTC->CALIBR    = (uint32_t)0x00000000;
+      RTC->ALRMAR    = (uint32_t)0x00000000;
+      RTC->ALRMBR    = (uint32_t)0x00000000;
+      RTC->SHIFTR    = (uint32_t)0x00000000;
+      RTC->CALR       = (uint32_t)0x00000000;
+      RTC->ALRMASSR  = (uint32_t)0x00000000;
+      RTC->ALRMBSSR  = (uint32_t)0x00000000;
+
+      /* Reset ISR register and exit initialization mode */
+      RTC->ISR = (uint32_t)0x00000000;
+      
+      /* Reset Tamper and alternate functions configuration register */
+      RTC->TAFCR = 0x00000000;
+      
+      /* Wait till the RTC RSF flag is set */
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+  
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized  
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+  
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;    
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+    
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;   
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;    
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode  
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+     
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }        
+  }
+  else
+  {
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+    
+  /* Clear RSF flag */
+  RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    
+  /* Wait the registers to be synchronised */
+  do
+  {
+    synchrostatus = RTC->ISR & RTC_ISR_RSF;
+    synchrocounter++;  
+  } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+    
+  if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return (status);
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;   
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;    
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+  return status;
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### Time and Date configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC 
+         Calendar (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format.
+  *     @arg RTC_Format_BCD:  BCD data format.
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }  
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  }  
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format.
+  *     @arg RTC_Format_BCD:  BCD data format.
+  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);   
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+  
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_Format_BIN:  Binary data format.
+  *     @arg RTC_Format_BCD:  BCD data format.
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format.
+  *     @arg RTC_Format_BCD: BCD data format.
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim
+ ===============================================================================
+         ##### Alarms (Alarm A and Alarm B) configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC 
+         Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format.
+  *     @arg RTC_Format_BCD: BCD data format.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A.
+  *     @arg RTC_Alarm_B: to select Alarm B.
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  } 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    RTC->ALRMAR = (uint32_t)tmpreg;
+  }
+  else
+  {
+    RTC->ALRMBR = (uint32_t)tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;   
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format.
+  *     @arg RTC_Format_BCD: BCD data format.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A.
+  *     @arg RTC_Alarm_B: to select Alarm B.
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)(RTC->ALRMAR);
+  }
+  else
+  {
+    tmpreg = (uint32_t)(RTC->ALRMBR);
+  }
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A.
+  *     @arg RTC_Alarm_B: to select Alarm B.
+  * @param  NewState: new state of the specified alarm.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.*
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A.
+  *     @arg RTC_Alarm_B: to select Alarm B.
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *   This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
+  *                                      There is no comparison on sub seconds for Alarm.
+  *     @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
+  *                                         Only SS[0] is compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
+  *                                          Only SS[1:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
+  *                                          Only SS[2:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
+  *                                          Only SS[3:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
+  *                                          Only SS[4:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
+  *                                          Only SS[5:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
+  *                                          Only SS[6:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
+  *                                          Only SS[7:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
+  *                                          Only SS[8:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                          Only SS[9:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                          Only SS[10:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                          Only SS[11:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                          Only SS[12:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
+  *                                          Only SS[13:0] are compared.
+  *     @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match
+  *                                          to activate alarm.
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+  
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    /* Configure the AlarmA SubSecond register */
+    RTC->ALRMASSR = tmpreg;
+  }
+  else
+  {
+    /* Configure the Alarm B SubSecond register */
+    RTC->ALRMBSSR = tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A.
+  *     @arg RTC_Alarm_B: to select Alarm B.
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  } 
+  
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim
+ ===============================================================================
+               ##### WakeUp Timer configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
+  *   This parameter can be one of the following values:
+  *            @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16.
+  *            @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8.
+  *            @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4.
+  *            @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2.
+  *            @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE.
+  *            @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE.
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the RTC Wakeup counter.
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp.
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
+  *   This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC WakeUp timer counter value.
+  * @param  None
+  * @retval The RTC WakeUp Counter value.
+  */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Enables or Disables the RTC WakeUp timer.
+  * @param  NewState: new state of the WakeUp timer.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim
+ ===============================================================================
+              ##### Daylight Saving configuration functions #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time).
+  *     @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time).
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                            in CR register to store the operation.
+  *   This parameter can be one of the following values:
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset.
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set.
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim
+ ===============================================================================
+                  ##### Output pin Configuration function #####
+ ===============================================================================
+    [..] This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Output_Disable: No output selected
+  *     @arg RTC_Output_AlarmA: signal of AlarmA mapped to output.
+  *     @arg RTC_Output_AlarmB: signal of AlarmB mapped to output.
+  *     @arg RTC_Output_WakeUp: signal of WakeUp mapped to output.
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal.
+  *   This parameter can be one of the following:
+  *     @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
+  *     @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL).
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Coarse and Smooth Calibrations configuration functions
+ *  @brief   Coarse and Smooth Calibrations configuration functions 
+ *
+@verbatim
+ ===============================================================================
+        ##### Coarse and Smooth Calibrations configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Coarse Calibration parameters.
+  * @param  RTC_CalibSign: specifies the sign of the calibration value.
+  *   This parameter can be  one of the following values:
+  *     @arg RTC_CalibSign_Positive: The value sign is positive.
+  *     @arg RTC_CalibSign_Negative: The value sign is negative.
+  * @param  Value: value of calibration expressed in ppm (coded on 5 bits) 
+  *                This value should be between 0 and 63 when using negative sign
+  *                with a 2-ppm step.
+  *                This value should be between 0 and 126 when using positive sign
+  *                with a 4-ppm step.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Coarse calibration are initialized
+  *          - ERROR: RTC Coarse calibration are not initialized 
+  */
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
+{
+  ErrorStatus status = ERROR;
+   
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
+  assert_param(IS_RTC_CALIB_VALUE(Value)); 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the coarse calibration value */
+    RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+* @brief  Enables or disables the Coarse calibration process.
+  * @param  NewState: new state of the Coarse calibration.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Coarse calibration are enabled/disabled
+  *          - ERROR: RTC Coarse calibration are not enabled/disabled    
+  */
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status =  ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the Coarse Calibration */
+      RTC->CR |= (uint32_t)RTC_CR_DCE;
+    }
+    else
+    { 
+      /* Disable the Coarse Calibration */
+      RTC->CR &= (uint32_t)~RTC_CR_DCE;
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative 
+  *         pin.
+  * @param  NewState: new state of the coarse calibration Output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  { 
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput : Select the Calibration output Selection .
+  *   This parameter can be one of the following values:
+  *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *     @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
+  *   This parameter can be can be one of the following values:
+  *     @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
+  *     @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
+  *     @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
+  *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *   This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim
+ ===============================================================================
+                 ##### TimeStamp configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *   This parameter can be one of the following:
+  *     @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                    edge of the related pin.
+  *     @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                     falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Format_BIN: Binary data format 
+  *     @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim
+ ===============================================================================
+                 ##### Tampers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Tamper_1: Select Tamper 1.
+  *     @arg RTC_Tamper_2: Select Tamper 2.
+  *     @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *                            stimulates tamper event. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ 
+  /* Check if the  active level for Tamper is rising edge (Low level)*/
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_Tamper_1: Select Tamper 1.
+  *     @arg RTC_Tamper_2: Select Tamper 2.
+  *     @arg RTC_Tamper_3: Select Tamper 3.
+  * @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                    samples at the active level.
+  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                    samples at the active level.
+  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                    samples at the active level.
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 32768
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 16384
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 8192
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 4096
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 2048
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 1024
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 512  
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle.
+  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle.
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim
+ ===============================================================================
+          ##### Backup Data Registers configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 Output Type Config configuration functions
+ *  @brief   Output Type Config configuration functions  
+ *
+@verbatim
+ ===============================================================================
+             ##### Output Type Config configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *     @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Shift control synchronisation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+  *   This parameter can be one of the following values :
+  *     @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. 
+  *     @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+    
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] All RTC interrupts are connected to the EXTI controller.
+         (+) To enable the RTC Alarm interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 17 in interrupt mode and select 
+             the rising edge sensitivity using the EXTI_Init() function.
+         (+) Configure and enable the RTC_Alarm IRQ channel in the NVIC using 
+             the NVIC_Init() function.
+         (+) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) 
+             using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+
+         (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 20 in interrupt mode and select 
+             the rising edge sensitivity using the EXTI_Init() function.
+         (+) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the 
+             NVIC_Init() function.
+         (+) Configure the RTC to generate the RTC wakeup timer event using the 
+             RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() 
+             functions.
+
+         (+) To enable the RTC Tamper interrupt, the following sequence is required:
+         (+) Configure and enable the EXTI Line 19 in interrupt mode and select 
+             the rising edge sensitivity using the EXTI_Init() function.
+         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+             the NVIC_Init() function.
+         (+) Configure the RTC to detect the RTC tamper event using the 
+             RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+         (+) To enable the RTC TimeStamp interrupt, the following sequence is 
+             required:
+         (+) Configure and enable the EXTI Line 19 in interrupt mode and select 
+             the rising edge sensitivity using the EXTI_Init() function.
+         (+) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using 
+             the NVIC_Init() function.
+         (+) Configure the RTC to detect the RTC time-stamp event using the 
+             RTC_TimeStampCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_TS:  Time Stamp interrupt mask.
+  *     @arg RTC_IT_WUT:  WakeUp Timer interrupt mask.
+  *     @arg RTC_IT_ALRB:  Alarm B interrupt mask.
+  *     @arg RTC_IT_ALRA:  Alarm A interrupt mask.
+  *     @arg RTC_IT_TAMP: Tamper event interrupt mask.
+  * @param  NewState: new state of the specified RTC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_FLAG_RECALPF: RECALPF event flag.
+  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+  *     @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag.
+  *     @arg RTC_FLAG_TSF: Time Stamp event flag.
+  *     @arg RTC_FLAG_WUTF: WakeUp Timer flag.
+  *     @arg RTC_FLAG_ALRBF: Alarm B flag.
+  *     @arg RTC_FLAG_ALRAF: Alarm A flag.
+  *     @arg RTC_FLAG_INITF: Initialization mode flag.
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag.
+  *     @arg RTC_FLAG_INITS: Registers Configured flag.
+  *     @argRTC_FLAG_SHPF: Shift operation pending flag.
+  *     @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag.
+  *     @arg RTC_FLAG_ALRBWF: Alarm B Write flag.
+  *     @arg RTC_FLAG_ALRAWF: Alarm A write flag.
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag.
+  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag.
+  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag.
+  *     @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag.
+  *     @arg RTC_FLAG_TSF: Time Stamp event flag.
+  *     @arg RTC_FLAG_WUTF: WakeUp Timer flag.
+  *     @arg RTC_FLAG_ALRBF: Alarm B flag.
+  *     @arg RTC_FLAG_ALRAF: Alarm A flag.
+  *     @arg RTC_FLAG_RSF: Registers Synchronized flag.
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));    
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_IT_TS: Time Stamp interrupt.
+  *     @arg RTC_IT_WUT: WakeUp Timer interrupt.
+  *     @arg RTC_IT_ALRB: Alarm B interrupt. 
+  *     @arg RTC_IT_ALRA: Alarm A interrupt. 
+  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt. 
+  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt. 
+  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt.
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_IT_TS: Time Stamp interrupt 
+  *     @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *     @arg RTC_IT_ALRB: Alarm B interrupt 
+  *     @arg RTC_IT_ALRA: Alarm A interrupt 
+  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt
+  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt
+  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt 
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
new file mode 100644
index 0000000..e866dbc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
@@ -0,0 +1,1076 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_spi.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):
+  *           + Initialization and Configuration
+  *           + Data transfers functions
+  *           + Hardware CRC Calculation
+  *           + DMA transfers management
+  *           + Interrupts and flags management
+  *
+  *  @verbatim
+    [..] The I2S feature is not implemented in STM32L1xx Ultra Low Power
+         Medium-density devices and it's supported only STM32L1xx Ultra Low Power
+         Medium-density Plus and High-density devices.
+  
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
+            function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
+            function for SPI2 or using RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE)
+            for SPI3.
+  
+        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using 
+            RCC_AHBPeriphClockCmd() function. 
+  
+        (#) Peripherals alternate function: 
+            (++) Connect the pin to the desired peripherals' Alternate 
+                 Function (AF) using GPIO_PinAFConfig() function.
+            (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+            (++) Select the type, pull-up/pull-down and output speed via 
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+            (++) Call GPIO_Init() function.
+  
+        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+            function.In I2S mode, program the Mode, Standard, Data Format, MCLK 
+            Output, Audio frequency and Polarity using I2S_Init() function.
+  
+        (#) Enable the NVIC and the corresponding interrupt using the function 
+            SPI_ITConfig() if you need to use interrupt mode. 
+  
+        (#) When using the DMA mode 
+            (++) Configure the DMA using DMA_Init() function.
+            (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
+   
+        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+            I2S_Cmd().
+   
+        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  
+        (#) Optionally, you can enable/configure the following parameters without
+            re-initialization (i.e there is no need to call again SPI_Init() function):
+            (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+                 is programmed as Data direction parameter using the SPI_Init() 
+                 function it can be possible to switch between SPI_Direction_Tx 
+                 or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
+            (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
+                 using the SPI_Init() function it can be possible to manage the 
+                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+            (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
+            (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.  
+  
+        (#) To use the CRC Hardware calculation feature refer to the Peripheral 
+            CRC hardware Calculation subsection.
+  
+    @endverbatim  
+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI 
+  * @brief SPI driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK       ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to initialize the SPI 
+         Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS 
+         Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+    [..] The SPI_Init() function follows the SPI configuration procedures for 
+         Master mode and Slave mode (details for these procedures are available 
+         in reference manual (RM0038)).
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPIx peripheral registers to their default
+  *         reset values.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *               in SPI mode or 2 or 3 in I2S mode.
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+  else
+  {
+    if (SPIx == SPI3)
+    {
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+  
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral
+  *         (configured in I2S mode).
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  * @note
+  *  The function calculates the optimal prescaler needed to obtain the most 
+  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *  and the product configuration). But in case the prescaler value is greater 
+  *  than 511, the default value (0x02) will be configured instead.     
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0;
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint32_t sourceclock = 0;
+  
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
+  SPIx->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+  
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) */
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* I2S Clock source is System clock: Get System Clock frequency */
+    RCC_GetClocksFreq(&RCC_Clocks);      
+      
+    /* Get the source clock value: based on System Clock value */
+    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
+   
+    /* Compute the Real divider depending on the MCLK output state with a flaoting point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the flaoting point */
+    tmp = tmp / 10;  
+      
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+   
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+   
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+  
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));  
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+ 
+  /* Write to SPIx I2SCFGR */  
+  SPIx->I2SCFGR = tmpreg;   
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+  
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+  
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+  
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+  
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+  
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= SPI_CR1_SPE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_DataSize_16b: Set data frame format to 16bit.
+  *     @arg SPI_DataSize_8b: Set data frame format to 8bit.
+  * @retval None.
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+  /* Set new DFF bit value */
+  SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_Direction_Tx: Selects Tx transmission direction.
+  *     @arg SPI_Direction_Rx: Selects Rx receive direction.
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally.
+  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally.
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+....[..] This section provides a set of functions allowing to manage the SPI data 
+         transfers.
+....[..] In reception, data are received and then stored into an internal Rx buffer 
+         while In transmission, data are first stored into an internal Tx buffer 
+         before being transmitted.
+....[..] The read access of the SPI_DR register can be done using the 
+         SPI_I2S_ReceiveData() function and returns the Rx buffered value. 
+         Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData() 
+         function and stores the written data into Tx buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3
+  *         in SPI mode or 2 or 3 in I2S mode.
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the data in the DR register */
+  return SPIx->DR;
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Write in the DR register the data to be sent */
+  SPIx->DR = Data;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Hardware CRC Calculation functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to manage the SPI CRC 
+         hardware calculation SPI communication using CRC is possible through 
+         the following procedure:
+         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate 
+             Prescaler, Slave Management, Peripheral Mode and CRC Polynomial 
+             values using the SPI_Init() function.
+         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+         (#) Enable the SPI using the SPI_Cmd() function.
+         (#) Before writing the last data to the TX buffer, set the CRCNext bit 
+             using the SPI_TransmitCRC() function to indicate that after 
+             transmission of the last data, the CRC should be transmitted.
+         (#) After transmitting the last data, the SPI transmits the CRC.
+             The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and 
+             compared against the SPI_RXCRCR value. 
+             If the value does not match, the SPI_FLAG_CRCERR flag is set and an 
+             interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+    -@-
+       (+@) It is advised to don't read the calculate CRC values during the communication.
+       (+@) When the SPI is in slave mode, be careful to enable CRC calculation only 
+       when the clock is stable, that is, when the clock is in the steady state. 
+       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+       to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+       the value of the SPE bit.
+       (+@) With high bitrate frequencies, be careful when transmitting the CRC.
+       As the number of used CPU cycles has to be as low as possible in the CRC 
+       transfer phase, it is forbidden to call software functions in the CRC 
+       transmission sequence to avoid errors in the last data and CRC reception. 
+       In fact, CRCNEXT bit has to be written before the end of the transmission/
+       reception of the last data.
+       (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+       degradation of the SPI speed performance due to CPU accesses impacting the 
+       SPI bandwidth.
+       (+@) When the STM32L15xxx are configured as slaves and the NSS hardware mode is 
+       used, the NSS pin needs to be kept low between the data phase and the CRC 
+       phase.
+       (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+       calculation takes place even if a high level is applied on the NSS pin. 
+       This may happen for example in case of a multislave environment where the 
+       communication master addresses slaves alternately.
+       (+@) Between a slave deselection (high level on NSS) and a new slave selection 
+       (low level on NSS), the CRC value should be cleared on both master and slave
+       sides in order to resynchronize the master and slave for their respective 
+       CRC calculation.
+    -@- To clear the CRC, follow the procedure below:
+       (#@) Disable SPI using the SPI_Cmd() function
+       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= SPI_CR1_CRCEN;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+  }
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *   This parameter can be one of the following values:
+  *     @arg SPI_CRC_Tx: Selects Tx CRC register.
+  *     @arg SPI_CRC_Rx: Selects Rx CRC register.
+  * @retval The selected CRC register value.
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim
+ ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *               in SPI mode or 2 or 3 in I2S mode.
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *   This parameter can be any combination of the following values:
+  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.
+  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.
+  * @param  NewState: new state of the selected SPI DMA transfer request.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This section provides a set of functions allowing to configure the SPI 
+         Interrupts sources and check or clear the flags or pending bits status.
+         The user should identify which mode will be used in his application to 
+         manage the communication: Polling mode, Interrupt mode or DMA mode.
+  *** Polling Mode ***
+  ====================
+    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+        (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer 
+             register.
+        (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer 
+             register.
+        (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer 
+             of the SPI.
+        (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur.
+        (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur.
+        (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur.
+        (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
+        (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+        (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+    -@- Do not use the BSY flag to handle each data transmission or reception.
+        It is better to use the TXE and RXNE flags instead.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).
+         (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG).
+
+  *** Interrupt Mode ***
+  ======================
+    [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt 
+         sources and 7 pending bits: 
+    [..] Pending Bits:
+        (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register.
+        (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register.
+        (#) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur.
+        (#) SPI_IT_MODF : to indicate if a Mode Fault error occur.
+        (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur.
+        (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
+        (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
+    [..] Interrupt Source:
+        (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+            interrupt.
+        (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+            empty interrupt.
+        (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT,
+             FunctionalState NewState).
+         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).
+         (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT).
+
+  *** DMA Mode ***
+  ================
+    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel 
+         requests:
+        (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+        (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+
+    [..] In this Mode it is advised to use the following function:
+         (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq,
+             FunctionalState NewState).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.
+  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.
+  *     @arg SPI_I2S_IT_ERR: Error interrupt mask.
+  * @param  NewState: new state of the specified SPI interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPIx/I2Sx flag is set or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *     @arg SPI_FLAG_MODF: Mode Fault flag.
+  *     @arg SPI_FLAG_CRCERR: CRC Error flag.
+  *     @arg SPI_I2S_FLAG_FRE: Format Error.
+  *     @arg I2S_FLAG_UDR: Underrun Error flag.
+  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+  
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *   This function clears only CRCERR flag.
+
+  * @note OVR (OverRun error) flag is cleared by software sequence: a read 
+  *     operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  * @note UDR (UnderRun error) flag is cleared by a read operation to 
+  *     SPI_SR register (SPI_I2S_GetFlagStatus()).   
+  * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *     operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *     write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+    
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *   This parameter can be one of the following values:
+  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *     @arg SPI_IT_MODF: Mode Fault interrupt.
+  *     @arg SPI_IT_CRCERR: CRC Error interrupt.
+  *     @arg I2S_IT_UDR: Underrun interrupt.  
+  *     @arg SPI_I2S_IT_FRE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S_IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI_I2S_IT IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.
+
+  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+  *   This function clears only CRCERR interrupt pending bit.   
+
+  *     OVR (OverRun Error) interrupt pending bit is cleared by software 
+  *     sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
+  *     followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read 
+  *     operation to SPI_SR register (SPI_I2S_GetITStatus()).   
+  * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *     a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
+  *     followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
+  *     the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->SR = (uint16_t)~itpos;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
new file mode 100644
index 0000000..e719bee
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
@@ -0,0 +1,652 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the SYSCFG and RI peripherals:
+  *           + SYSCFG Initialization and Configuration
+  *           + RI Initialization and Configuration
+  *
+@verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..] This driver provides functions for:
+         (#) Remapping the memory accessible in the code area using
+          SYSCFG_MemoryRemapConfig().
+         (#) Manage the EXTI lines connection to the GPIOs using
+             SYSCFG_EXTILineConfig().
+         (#) Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).
+         (#) Input routing of COMP1 and COMP2.
+         (#) Routing of internal reference voltage VREFINT to PB0 and PB1.
+         (#) The RI registers can be accessed only when the comparator
+             APB interface clock is enabled.
+             To enable comparator clock use:
+             RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
+             Following functions uses RI registers:
+             (++) SYSCFG_RIDeInit()
+             (++) SYSCFG_RITIMSelect()
+             (++) SYSCFG_RITIMInputCaptureConfig()
+             (++) SYSCFG_RIResistorConfig()
+             (++) SYSCFG_RIChannelSpeedConfig()
+             (++) SYSCFG_RIIOSwitchConfig()
+             (++) SYSCFG_RISwitchControlModeCmd()
+             (++) SYSCFG_RIHysteresisConfig()
+         (#) The SYSCFG registers can be accessed only when the SYSCFG
+             interface APB clock is enabled.
+             To enable SYSCFG APB clock use:
+             RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+             Following functions uses SYSCFG registers:
+             (++) SYSCFG_DeInit()  
+             (++) SYSCFG_MemoryRemapConfig()
+             (++) SYSCFG_GetBootMode()  
+             (++) SYSCFG_USBPuCmd()
+             (++) SYSCFG_EXTILineConfig()
+@endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TIM_SELECT_MASK             ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */
+#define IC_ROUTING_MASK             ((uint32_t)0x0000000F) /*!< Input Capture routing mask */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */
+
+/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
+ *  @brief   SYSCFG Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+        ##### SYSCFG Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SYSCFG registers to their default reset values.
+  * @param  None.
+  * @retval None.
+  * @Note: MEMRMP bits are not reset by APB2 reset.
+  */
+void SYSCFG_DeInit(void)
+{
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
+}
+
+/**
+  * @brief Deinitializes the RI registers to their default reset values.
+  * @param  None.
+  * @retval None.
+  */
+void SYSCFG_RIDeInit(void)
+{
+  RI->ICR     = ((uint32_t)0x00000000);    /*!< Set RI->ICR to reset value */
+  RI->ASCR1   = ((uint32_t)0x00000000);    /*!< Set RI->ASCR1 to reset value */
+  RI->ASCR2   = ((uint32_t)0x00000000);    /*!< Set RI->ASCR2 to reset value */
+  RI->HYSCR1  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR1 to reset value */
+  RI->HYSCR2  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR2 to reset value */
+  RI->HYSCR3  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR3 to reset value */
+  RI->HYSCR4  = ((uint32_t)0x00000000);    /*!< Set RI->HYSCR4 to reset value */
+}
+
+/**
+  * @brief  Changes the mapping of the specified memory.
+  * @param  SYSCFG_Memory: selects the memory remapping.
+  *   This parameter can be one of the following values:
+  *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
+  *     @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
+  *     @arg SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000  
+  *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
+}
+
+/**
+  * @brief  Returns the boot mode as configured by user.
+  * @param  None.
+  * @retval The boot mode as configured by user. The returned value can be one 
+  *         of the following values:
+  *              - 0x00000000: Boot is configured in Main Flash memory
+  *              - 0x00000100: Boot is configured in System Flash memory
+  *              - 0x00000200: Boot is configured in FSMC memory
+  *              - 0x00000300: Boot is configured in Embedded SRAM memory
+  */
+uint32_t SYSCFG_GetBootMode(void)
+{
+  return (SYSCFG->MEMRMP & SYSCFG_MEMRMP_BOOT_MODE);
+}
+
+/**
+  * @brief  Control the internal pull-up on USB DP line.
+  * @param  NewState: New state of the internal pull-up on USB DP line. 
+  *   This parameter can be ENABLE: Connect internal pull-up on USB DP line.
+  *                      or DISABLE: Disconnect internal pull-up on USB DP line.
+  * @retval None
+  */
+void SYSCFG_USBPuCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Connect internal pull-up on USB DP line */
+    SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;
+  }
+  else
+  {
+    /* Disconnect internal pull-up on USB DP line */
+    SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);
+  }
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source 
+  *                                for EXTI lines where x can be (A, B, C, D, E, F, G or H).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *         This parameter can be EXTI_PinSourcex where x can be (0..15).
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+  
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions
+ *  @brief   RI Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+        ##### RI Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the routing interface to select which Timer to be routed.
+  * @note   Routing capability can be applied only on one of the three timers
+  *         (TIM2, TIM3 or TIM4) at a time.
+  * @param  TIM_Select: Timer select.
+  *   This parameter can be one of the following values:
+  *     @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.
+  *     @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.
+  *     @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.
+  *     @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.
+  * @retval None.
+  */
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RI_TIM(TIM_Select));
+
+  /* Get the old register value */
+  tmpreg = RI->ICR;
+
+  /* Clear the TIMx select bits */
+  tmpreg &= TIM_SELECT_MASK;
+
+  /* Select the Timer */
+  tmpreg |= (TIM_Select);
+
+  /* Write to RI->ICR register */
+  RI->ICR = tmpreg;
+}
+
+/**
+  * @brief  Configures the routing interface to map Input Capture 1, 2, 3 or 4
+  *         to a selected I/O pin.
+  * @param  RI_InputCapture selects which input capture to be routed.
+  *   This parameter can be one (or combination) of the following parameters:
+  *     @arg  RI_InputCapture_IC1: Input capture 1 is selected.
+  *     @arg  RI_InputCapture_IC2: Input capture 2 is selected.
+  *     @arg  RI_InputCapture_IC3: Input capture 3 is selected.
+  *     @arg  RI_InputCapture_IC4: Input capture 4 is selected.
+  * @param  RI_InputCaptureRouting: selects which pin to be routed to Input Capture.
+  *   This parameter can be one of the following values:
+  * @param  RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15
+  *     e.g.
+  *       SYSCFG_RITIMSelect(TIM_Select_TIM2)
+  *       SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)
+  *       allows routing of Input capture IC1 of TIM2 to PA4.
+  *       For details about correspondence between RI_InputCaptureRouting_x 
+  *       and I/O pins refer to the parameters' description in the header file
+  *       or refer to the product reference manual.
+  * @note Input capture selection bits are not reset by this function.
+  *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.
+  * @note The I/O should be configured in alternate function mode (AF14) using
+  *       GPIO_PinAFConfig() function.
+  * @retval None.
+  */
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
+  assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));
+
+  /* Get the old register value */
+  tmpreg = RI->ICR;
+
+  /* Select input captures to be routed */
+  tmpreg |= (RI_InputCapture);
+
+  if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)
+  {
+    /* Clear the input capture select bits */
+    tmpreg &= (uint32_t)(~IC_ROUTING_MASK);
+
+    /* Set RI_InputCaptureRouting bits  */
+    tmpreg |= (uint32_t)( RI_InputCaptureRouting);
+  }
+
+  if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)
+  {
+    /* Clear the input capture select bits */
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));
+
+    /* Set RI_InputCaptureRouting bits  */
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4));
+  }
+
+  if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)
+  {
+    /* Clear the input capture select bits */
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));
+
+    /* Set RI_InputCaptureRouting bits  */
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));
+  }
+
+  if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)
+  {
+    /* Clear the input capture select bits */
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));
+
+    /* Set RI_InputCaptureRouting bits  */
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));
+  }
+
+  /* Write to RI->ICR register */
+  RI->ICR = tmpreg;
+}
+
+/**
+  * @brief  Configures the Pull-up and Pull-down Resistors 
+  * @param  RI_Resistor selects the resistor to connect. 
+  *   This parameter can be  one of the following values:
+  *     @arg RI_Resistor_10KPU: 10K pull-up resistor.
+  *     @arg RI_Resistor_400KPU: 400K pull-up resistor.
+  *     @arg RI_Resistor_10KPD: 10K pull-down resistor.
+  *     @arg RI_Resistor_400KPD: 400K pull-down resistor.
+  * @param  NewState: New state of the analog switch associated to the selected 
+  *         resistor.
+  *   This parameter can be:
+  *      ENABLE so the selected resistor is connected
+  *      or DISABLE so the selected resistor is disconnected.
+  * @note To avoid extra power consumption, only one resistor should be enabled
+  *       at a time.  
+  * @retval None
+  */
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RI_RESISTOR(RI_Resistor));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the resistor */
+    COMP->CSR |= (uint32_t) RI_Resistor;
+  }
+  else
+  {
+    /* Disable the Resistor */
+    COMP->CSR &= (uint32_t) (~RI_Resistor);
+  }
+}
+
+/**
+  * @brief  Configures the ADC channels speed.
+  * @param  RI_Channel selects the channel.
+  *   This parameter can be  one of the following values:
+  *     @arg RI_Channel_3: Channel 3 is selected.
+  *     @arg RI_Channel_8: Channel 8 is selected.
+  *     @arg RI_Channel_13: Channel 13 is selected.
+  * @param  RI_ChannelSpeed: The speed of the selected ADC channel
+  *   This parameter can be:
+  *      RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel 
+  *      or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.
+  * @retval None
+  */
+void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
+{
+  /* Check the parameters */
+  assert_param(IS_RI_CHANNEL(RI_Channel));
+  assert_param(IS_RI_CHANNELSPEED(RI_ChannelSpeed));
+
+  if(RI_ChannelSpeed != RI_ChannelSpeed_Fast)
+  {
+    /* Set the selected channel as a slow ADC channel */
+    COMP->CSR &= (uint32_t) (~RI_Channel);
+  }
+  else
+  {
+    /* Set the selected channel as a fast ADC channel */
+    COMP->CSR |= (uint32_t) (RI_Channel);
+  }
+}
+
+/**
+  * @brief  Close or Open the routing interface Input Output switches.
+  * @param  RI_IOSwitch: selects the I/O analog switch number.
+  *   This parameter can be one of the following values:
+  * @param RI_IOSwitch_CH0 --> RI_IOSwitch_CH15.
+  * @param RI_IOSwitch_CH18 --> RI_IOSwitch_CH25.
+  * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4.
+  * @param RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2.
+  * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3.
+  * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3.
+  * @param RI_IOSwitch_VCOMP
+  * RI_IOSwitch_CH27
+  * @param RI_IOSwitch_CH28 --> RI_IOSwitch_CH30
+  * @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4
+  * @param RI_IOSwitch_GR6_1
+  * @param RI_IOSwitch_GR6_2
+  * @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3
+  * @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_4
+  * @param RI_IOSwitch_CH0b --> RI_IOSwitch_CH3b
+  * @param RI_IOSwitch_CH6b --> RI_IOSwitch_CH12b
+  * @param RI_IOSwitch_GR6_3
+  * @param RI_IOSwitch_GR6_4
+  * @param RI_IOSwitch_GR5_4
+  
+  * @param  NewState: New state of the analog switch. 
+  *   This parameter can be 
+  *     ENABLE so the Input Output switch is closed
+  *     or DISABLE so the Input Output switch is open.
+  * @retval None
+  */
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)
+{
+  uint32_t ioswitchmask = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
+  
+  /* Read Analog switch register index */
+  ioswitchmask = RI_IOSwitch >> 31;
+  
+  /* Get Bits[30:0] of the IO switch */
+  RI_IOSwitch  &= 0x7FFFFFFF;
+  
+  
+  if (NewState != DISABLE)
+  {
+    if (ioswitchmask != 0)
+    {
+      /* Close the analog switches */
+      RI->ASCR1 |= RI_IOSwitch;
+    }
+    else
+    {
+      /* Open the analog switches */
+      RI->ASCR2 |= RI_IOSwitch;
+    }
+  }
+  else
+  {
+    if (ioswitchmask != 0)
+    {
+      /* Close the analog switches */
+      RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);
+    }
+    else
+    {
+      /* Open the analog switches */
+      RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);
+    }
+  }
+}
+
+/**
+  * @brief  Enable or disable the switch control mode.
+  * @param  NewState: New state of the switch control mode. This parameter can
+  *         be ENABLE: ADC analog switches closed if the corresponding 
+  *                    I/O switch is also closed.
+  *                    When using COMP1, switch control mode must be enabled.
+  *         or DISABLE: ADC analog switches open or controlled by the ADC interface.
+  *                    When using the ADC for acquisition, switch control mode 
+  *                    must be disabled.
+  * @note COMP1 comparator and ADC cannot be used at the same time since 
+  *       they share the ADC switch matrix.
+  * @retval None
+  */
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Switch control mode */
+    RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;
+  }
+  else
+  {
+    /* Disable the Switch control mode */
+    RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);
+  }
+}
+
+/**
+  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A..E
+  *         When the I/Os are programmed in input mode by standard I/O port 
+  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
+  *         When hysteresis is disabled, it is possible to read the 
+  *         corresponding port with a trigger level of VDDIO/2.
+  * @param  RI_Port: selects the GPIO Port.
+  *   This parameter can be one of the following values:
+  *     @arg RI_PortA: Port A is selected
+  *     @arg RI_PortB: Port B is selected
+  *     @arg RI_PortC: Port C is selected
+  *     @arg RI_PortD: Port D is selected
+  *     @arg RI_PortE: Port E is selected
+  *     @arg RI_PortF: Port F is selected
+  *     @arg RI_PortG: Port G is selected
+  *  @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.
+  *    This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
+  *  @param  NewState new state of the Hysteresis.
+  *   This parameter can be:
+  *      ENABLE so the Hysteresis is on
+  *      or DISABLE so the Hysteresis is off
+  * @retval None
+  */
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,
+                             FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RI_PORT(RI_Port));
+  assert_param(IS_RI_PIN(RI_Pin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(RI_Port == RI_PortA)
+  {  
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR1 |= (uint32_t) RI_Pin;
+    }
+  }
+  
+  else if(RI_Port == RI_PortB)
+  {
+  
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
+    }
+  }  
+ 
+  else if(RI_Port == RI_PortC)
+  {
+  
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR2 |= (uint32_t) (RI_Pin );
+    }
+  } 
+  else if(RI_Port == RI_PortD)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
+
+    }
+  }
+  else if(RI_Port == RI_PortE)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR3 |= (uint32_t) (RI_Pin );
+    }
+  }
+  else if(RI_Port == RI_PortF)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR3 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
+    }
+  }
+  else /* RI_Port == RI_PortG */
+  {
+    if (NewState != DISABLE)
+    {
+      /* Hysteresis on */
+      RI->HYSCR4 &= (uint32_t) (~((uint32_t)RI_Pin));
+    }
+    else
+    {
+      /* Hysteresis off */
+      RI->HYSCR4 |= (uint32_t) (RI_Pin);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
new file mode 100644
index 0000000..48c051f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
@@ -0,0 +1,1459 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_usart.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):           
+  *           + Initialization and Configuration
+  *           + Data transfers
+  *           + Multi-Processor Communication
+  *           + LIN mode
+  *           + Half-duplex mode
+  *           + Smartcard mode
+  *           + IrDA mode
+  *           + DMA transfers management
+  *           + Interrupts and flags management 
+  *           
+  *  @verbatim
+ ===============================================================================
+                       ##### How to use this driver #####
+ ===============================================================================
+    [..]
+        (#) Enable peripheral clock using
+            RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) function for
+            USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
+            function for USART2 and USART3.
+        (#) According to the USART mode, enable the GPIO clocks using
+            RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
+            or and SCLK).
+        (#) Peripheral's alternate function:
+            (++) Connect the pin to the desired peripherals' Alternate
+                 Function (AF) using GPIO_PinAFConfig() function.
+            (++) Configure the desired pin in alternate function by:
+                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
+            (++) Select the type, pull-up/pull-down and output speed via
+                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+            (++) Call GPIO_Init() function.
+        (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+               flow control and Mode(Receiver/Transmitter) using the SPI_Init()
+               function.
+        (#) For synchronous mode, enable the clock and program the polarity,
+            phase and last bit using the USART_ClockInit() function.
+        (#) Enable the NVIC and the corresponding interrupt using the function
+            USART_ITConfig() if you need to use interrupt mode.
+        (#) When using the DMA mode.
+            (++) Configure the DMA using DMA_Init() function.
+            (++) Active the needed channel Request using USART_DMACmd() function.
+        (#) Enable the USART using the USART_Cmd() function.
+        (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
+    [..]
+        Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+        for more details.
+  
+@endverbatim
+          
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
+#define CR1_CLEAR_MASK            ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
+                                              USART_CR1_PS | USART_CR1_TE | \
+                                              USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK      ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
+#define CR3_CLEAR_MASK            ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK                   ((uint16_t)0x001F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+        This subsection provides a set of functions allowing to initialize the USART 
+        in asynchronous and in synchronous modes.
+        (+) For the asynchronous mode only these parameters can be configured: 
+        (+) Baud Rate.
+        (+) Word Length.
+        (+) Stop Bit.
+        (+) Parity: If the parity is enabled, then the MSB bit of the data written
+          in the data register is transmitted but is changed by the parity bit.
+          Depending on the frame length defined by the M bit (8-bits or 9-bits),
+          the possible USART frame formats are as listed in the following table:
+    [..]
+   +-------------------------------------------------------------+
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+
+    [..]
+        (+) Hardware flow control.
+        (+) Receiver/transmitter modes.
+    [..] The USART_Init() function follows the USART  asynchronous configuration 
+         procedure(details for the procedure are available in reference manual 
+         (RM0038)).
+        (+) For the synchronous mode in addition to the asynchronous mode parameters
+            these parameters should be also configured:
+            (++) USART Clock Enabled.
+            (++) USART polarity.
+            (++) USART phase.
+            (++) USART LastBit.
+    [..] These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values: USART1, USART2, USART3, 
+  *   UART4 or UART5.
+  * @retval None.
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }    
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }    
+  else
+  {
+    if (USARTx == UART5)
+    { 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+  }   
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *   parameters in the USART_InitStruct.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values: USART1, USART2, USART3, 
+  *   UART4 or UART5.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that 
+  *        contains the configuration information for the specified USART peripheral.
+  * @retval None.
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+
+  /* The hardware flow control is available only for USART1, USART2 and USART3 */
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  }
+   
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+
+  /* Configure the USART Word Length, Parity and mode ----------------------- */
+  /* Set the M bits according to USART_WordLength value */
+  /* Set PCE and PS bits according to USART_Parity value */
+  /* Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+
+  /* Write to USART CR1 */
+  USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+
+  /* Configure the USART HFC -------------------------------------------------*/
+  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+  /* Write to USART CR3 */
+  USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate -------------------------------------------*/
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+  if (USARTx == USART1) 
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+
+  /* Determine the integer part */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* Integer part computing in case Oversampling mode is 8 Samples */
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    /* Integer part computing in case Oversampling mode is 16 Samples */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  tmpreg = (integerdivider / 100) << 4;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  /* Implement the fractional part in the register */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+ 
+  /* Write to USART BRR */
+  USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
+  *   which will be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *         specified parameters in the USART_ClockInitStruct.
+  * @param  USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *         structure that contains the configuration information for the specified 
+  *         USART peripheral.
+  * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+  * @retval None.
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+  *   structure which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USARTx peripheral.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_UE;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
+  }
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Prescaler: specifies the prescaler clock. 
+  * @note   The function is used for IrDA mode with UART4 and UART5.   
+  * @retval None.
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= USART_GTPR_GT;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @param USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *     USART1, USART2, USART3, UART4 or UART5.
+  * @param NewState: new state of the USART 8x oversampling mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  *
+  * @note
+  *   This function has to be called before calling USART_Init()
+  *   function in order to have correct baudrate Divider value.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_OVER8;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param NewState: new state of the USART one bit sampling method.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_ONEBIT;
+  }
+  else
+  {
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group2 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim
+ ===============================================================================
+                    ##### Data transfers functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage 
+         the USART data transfers.
+    [..] During an USART reception, data shifts in least significant bit first 
+         through the RX pin. In this mode, the USART_DR register consists of 
+         a buffer (RDR) between the internal bus and the received shift register.
+         When a transmission is taking place, a write instruction to 
+         the USART_DR register stores the data in the TDR register and which is 
+         copied in the shift register at the end of the current transmission.
+    [..] The read access of the USART_DR register can be done using 
+         the USART_ReceiveData() function and returns the RDR buffered value.
+        Whereas a write access to the USART_DR can be done using USART_SendData()
+        function and stores the written data into TDR buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  Data: the data to transmit.
+  * @retval None.
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group3 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Multi-Processor Communication functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         multiprocessor communication.
+    [..] For instance one of the USARTs can be the master, its TX output is
+         connected to the RX input of the other USART. The others are slaves,
+         their respective TX outputs are logically ANDed together and connected 
+         to the RX input of the master. USART multiprocessor communication is 
+         possible through the following procedure:
+         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Configures the wake up methode (USART_WakeUp_IdleLine or 
+             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only 
+             for the slaves.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() 
+             function.
+
+    [..] The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
+  /* Set the USART address node */
+  USARTx->CR2 |= USART_Address;
+}
+
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART mute mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_RWU;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
+  }
+}
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *   This parameter can be one of the following values:
+  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection.
+  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark.
+  * @retval None.
+  */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+  
+  USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group4 LIN mode functions
+ *  @brief   LIN mode functions 
+ *
+@verbatim
+ ===============================================================================
+                       ##### LIN mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         LIN Mode communication.
+    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance 
+         with the LIN standard.
+    [..] Only this LIN Feature is supported by the USART IP:
+         (+) LIN Master Synchronous Break send capability and LIN slave break 
+             detection capability :  13-bit break generation and 10/11 bit break 
+             detection.
+    [..] USART LIN Master transmitter communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+             using the USART_Init() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         (#) Send the break character using USART_SendBreak() function.
+    [..] USART LIN Master receiver communication is possible through the 
+         following procedure:
+         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+             Mode transmitter or Mode receiver and hardware flow control values 
+            using the USART_Init() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Configures the break detection length 
+             using the USART_LINBreakDetectLengthConfig() function.
+         (#) Enable the LIN mode using the USART_LINCmd() function.
+         -@- In LIN mode, the following bits must be kept cleared:
+             (+@) CLKEN in the USART_CR2 register.
+             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *   This parameter can be one of the following values:
+  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection.
+  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection.
+  * @retval None.
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+  
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART's LIN mode.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART LIN mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_LINEN;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
+  }
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @retval None.
+  */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Send break characters */
+  USARTx->CR1 |= USART_CR1_SBK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim
+ ===============================================================================
+                   ##### Half-duplex mode function #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART
+         Half-duplex communication.
+    [..] The USART can be configured to follow a single-wire half-duplex protocol 
+         where the TX and RX lines are internally connected.
+    [..] USART Half duplex communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+             or Mode receiver and hardware flow control values using the USART_Init()
+            function.
+         (#) Configures the USART address using the USART_SetAddress() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+         -@- The RX pin is no longer used.
+         -@- In Half-duplex mode the following bits must be kept cleared:
+             (+@) LINEN and CLKEN bits in the USART_CR2 register.
+             (+@) SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's Half Duplex communication.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the USART Communication.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_HDSEL;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group6 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim
+ ===============================================================================
+                     ##### Smartcard mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         Smartcard communication.
+    [..] The Smartcard interface is designed to support asynchronous protocol 
+         Smartcards as defined in the ISO 7816-3 standard. The USART can provide 
+         a clock to the smartcard through the SCLK output. In smartcard mode, 
+         SCLK is not associated to the communication but is simply derived from 
+         the internal peripheral input clock through a 5-bit prescaler.
+    [..] Smartcard communication is possible through the following procedure:
+         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() 
+             function.
+         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() 
+             function.
+         (#) Program the USART clock using the USART_ClockInit() function as following:
+             (++) USART Clock enabled.
+             (++) USART CPOL Low.
+             (++) USART CPHA on first edge.
+             (++) USART Last Bit Clock Enabled.
+         (#) Program the Smartcard interface using the USART_Init() function as 
+             following:
+             (++) Word Length = 9 Bits.
+             (++) 1.5 Stop Bit.
+             (++) Even parity.
+             (++) BaudRate = 12096 baud.
+             (++) Hardware flow control disabled (RTS and CTS signals).
+             (++) Tx and Rx enabled
+         (#) Optionally you can enable the parity error interrupt using 
+             the USART_ITConfig() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
+    [..] 
+  Please refer to the ISO 7816-3 specification for more details.
+    [..] 
+         (@) It is also possible to choose 0.5 stop bit for receiving but it is 
+             recommended to use 1.5 stop bits for both transmitting and receiving 
+             to avoid switching between the two configurations.
+         (@) In smartcard mode, the following bits must be kept cleared:
+             (+@) LINEN bit in the USART_CR2 register.
+             (+@) HDSEL and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2 or USART3.
+  * @param  USART_GuardTime: specifies the guard time.   
+  * @retval None.
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= USART_GTPR_PSC;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Enables or disables the USART's Smart Card mode.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2 or USART3.
+  * @param  NewState: new state of the Smart Card mode.
+  *   This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2 or USART3.
+  * @param  NewState: new state of the NACK transmission.
+  *   This parameter can be: ENABLE or DISABLE.  
+  * @retval None.
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_123_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim
+ ===============================================================================
+                        ##### IrDA mode functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to manage the USART 
+         IrDA communication.
+    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, 
+         any data on the IrDA receive line will be ignored by the IrDA decoder 
+         and if the Receiver is busy, data on the TX from the USART to IrDA will 
+         not be encoded by IrDA. While receiving data, transmission should be 
+         avoided as the data to be transmitted could be corrupted.
+
+    [..] IrDA communication is possible through the following procedure:
+         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
+             Transmitter/Receiver modes and hardware flow control values using 
+             the USART_Init() function.
+         (#) Enable the USART using the USART_Cmd() function.
+         (#) Configures the IrDA pulse width by configuring the prescaler using  
+             the USART_SetPrescaler() function.
+         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal 
+             mode using the USART_IrDAConfig() function.
+         (#) Enable the IrDA using the USART_IrDACmd() function.
+
+    [..]
+    (@) A pulse of width less than two and greater than one PSC period(s) may or 
+        may not be rejected.
+    (@) The receiver set up time should be managed by software. The IrDA physical 
+        layer specification specifies a minimum of 10 ms delay between 
+        transmission and reception (IrDA is a half duplex protocol).
+    (@) In IrDA mode, the following bits must be kept cleared:
+        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        (+@) SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IrDAMode_LowPower: USART IrDA Low Power mode selected.
+  *     @arg USART_IrDAMode_Normal: USART IrDA Normal mode selected.
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+    
+  USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  NewState: new state of the IrDA mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group8 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+               ##### DMA transfers management functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_DMAReq_Tx: USART DMA transmit request.
+  *     @arg USART_DMAReq_Rx: USART DMA receive request.
+  * @param  NewState: new state of the DMA Request sources.
+  *   This parameter can be: ENABLE or DISABLE.   
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group9 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim
+ ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+    [..] This subsection provides a set of functions allowing to configure the 
+         USART Interrupts sources, DMA channels requests and check or clear the 
+         flags or pending bits status. The user should identify which mode will 
+         be used in his application to manage the communication: Polling mode, 
+         Interrupt mode or DMA mode.
+ *** Polling Mode ***
+ ====================
+    [..] In Polling Mode, the SPI communication can be managed by 10 flags:
+         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
+         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
+         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
+         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
+         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
+         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
+         (#) USART_FLAG_NE: to indicate if a noise error occur.
+         (#) USART_FLAG_FE: to indicate if a frame error occur.
+         (#) USART_FLAG_PE: to indicate if a parity error occur.
+         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
+    [..] In this Mode it is advised to use the following functions:
+         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
+  
+ *** Interrupt Mode ***
+ ======================
+    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt 
+         sources and 10 pending bits:
+         (+) Pending Bits:
+             (##) USART_IT_TXE: to indicate the status of the transmit buffer 
+                  register.
+             (##) USART_IT_RXNE: to indicate the status of the receive buffer 
+                  register.
+             (##) USART_IT_TC: to indicate the status of the transmit operation.
+             (##) USART_IT_IDLE: to indicate the status of the Idle Line.
+             (##) USART_IT_CTS: to indicate the status of the nCTS input.
+             (##) USART_IT_LBD: to indicate the status of the LIN break detection.
+             (##) USART_IT_NE: to indicate if a noise error occur.
+             (##) USART_IT_FE: to indicate if a frame error occur.
+             (##) USART_IT_PE: to indicate if a parity error occur.
+             (##) USART_IT_ORE: to indicate if an Overrun error occur
+                  (if the RXNEIE or EIE bits are set).
+
+         (+) Interrupt Source:
+             (##) USART_IT_TXE: specifies the interrupt source for the Tx buffer 
+                  empty interrupt. 
+             (##) USART_IT_RXNE: specifies the interrupt source for the Rx buffer 
+                  not empty interrupt.
+             (##) USART_IT_TC: specifies the interrupt source for the Transmit 
+                  complete interrupt. 
+             (##) USART_IT_IDLE: specifies the interrupt source for the Idle Line 
+                  interrupt.
+             (##) USART_IT_CTS: specifies the interrupt source for the CTS interrupt. 
+             (##) USART_IT_LBD: specifies the interrupt source for the LIN break 
+                  detection interrupt. 
+             (##) USART_IT_PE: specifies the interrupt source for theparity error 
+                  interrupt. 
+             (##) USART_IT_ERR:  specifies the interrupt source for the errors 
+                  interrupt.
+             -@@- Some parameters are coded in order to use them as interrupt 
+                 source or as pending bits.
+    [..] In this Mode it is advised to use the following functions:
+         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, 
+             FunctionalState NewState).
+         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
+         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
+  
+ *** DMA Mode ***
+ ================
+    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel 
+         requests:
+         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+    [..] In this Mode it is advised to use the following function:
+         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, 
+             FunctionalState NewState).
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt.
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt.
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
+  *     @arg USART_IT_TC:   Transmission complete interrupt.
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+  *     @arg USART_IT_IDLE: Idle line detection interrupt.
+  *     @arg USART_IT_PE:   Parity Error interrupt.
+  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error).
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+    
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_MASK;
+  itmask = (((uint32_t)0x01) << itpos);
+    
+  if (usartreg == 0x01) /* The IT is in CR1 register */
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x10;
+  }
+  else /* The IT is in CR3 register */
+  {
+    usartxbase += 0x14; 
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *     @arg USART_FLAG_TXE:  Transmit data register empty flag.
+  *     @arg USART_FLAG_TC:   Transmission Complete flag.
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *     @arg USART_FLAG_IDLE: Idle Line detection flag.
+  *     @arg USART_FLAG_ORE:  OverRun Error flag.
+  *     @arg USART_FLAG_NE:   Noise Error flag.
+  *     @arg USART_FLAG_FE:   Framing Error flag.
+  *     @arg USART_FLAG_PE:   Parity Error flag.
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if (USART_FLAG == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+    
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *     @arg USART_FLAG_TC:   Transmission Complete flag.
+  *     @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  *
+  * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) flags are cleared by software 
+  *     sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
+  *     followed by a read operation to USART_DR register (USART_ReceiveData()).
+  * @note RXNE flag can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  * @note TC flag can be also cleared by software sequence: a read operation to 
+  *     USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *     to USART_DR register (USART_SendData()).
+  * @note TXE flag is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+       
+  USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *     @arg USART_IT_IDLE: Idle line detection interrupt
+  *     @arg USART_IT_ORE_RX: OverRun Error interrupt if the RXNEIE bit is set.
+  *     @arg USART_IT_ORE_ER: OverRun Error interrupt if the EIE bit is set.   
+  *     @arg USART_IT_NE:   Noise Error interrupt
+  *     @arg USART_IT_FE:   Framing Error interrupt
+  *     @arg USART_IT_PE:   Parity Error interrupt
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+
+  /* The CTS interrupt is not available for UART4 and UART5 */ 
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+    
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_MASK;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->SR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: Select the USART peripheral. 
+  *   This parameter can be one of the following values:
+  *   USART1, USART2, USART3, UART4 or UART5.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be one of the following values:
+  *     @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *     @arg USART_IT_LBD:  LIN Break detection interrupt
+  *     @arg USART_IT_TC:   Transmission complete interrupt. 
+  *     @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+  *   
+
+  * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *     error) and IDLE (Idle line detected) pending bits are cleared by 
+  *     software sequence: a read operation to USART_SR register 
+  *     (USART_GetITStatus()) followed by a read operation to USART_DR register 
+  *     (USART_ReceiveData()).
+  * @note RXNE pending bit can be also cleared by a read to the USART_DR register 
+  *     (USART_ReceiveData()).
+  * @note TC pending bit can be also cleared by software sequence: a read 
+  *     operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *     operation to USART_DR register (USART_SendData()).
+  * @note TXE pending bit is cleared only by a write to the USART_DR register 
+  *     (USART_SendData()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_123_PERIPH(USARTx));
+  } 
+    
+  bitpos = USART_IT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->SR = (uint16_t)~itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_wwdg.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_wwdg.c
new file mode 100644
index 0000000..ad49a04
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_wwdg.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.1.1
+  * @date    05-March-2012
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:           
+  *           + Prescaler, Refresh window and Counter configuration
+  *           + WWDG activation
+  *           + Interrupts and flags management
+  *             
+  *  @verbatim
+  *    
+  ============================================================================== 
+                           ##### WWDG features ##### 
+  ============================================================================== 
+    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
+        time period, unless the program refreshes the counter (downcounter) 
+        before to reach 0x3F value (i.e. a reset is generated when the counter
+        value rolls over from 0x40 to 0x3F). 
+    [..] An MCU reset is also generated if the counter value is refreshed
+         before the counter has reached the refresh window value. This 
+         implies that the counter must be refreshed in a limited window.
+
+    [..] Once enabled the WWDG cannot be disabled except by a system reset.
+
+    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+         reset occurs.
+
+    [..] The WWDG counter input clock is derived from the APB clock divided 
+         by a programmable prescaler.
+
+    [..] WWDG counter clock = PCLK1 / Prescaler.
+    [..] WWDG timeout = (WWDG counter clock) * (counter value).
+
+    [..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.
+
+                       ##### How to use this driver ##### 
+  ==============================================================================
+    [..]
+        (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 
+            function.
+              
+        (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
+                             
+        (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
+              
+        (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+            When the WWDG is enabled the counter value should be configured to 
+            a value greater than 0x40 to prevent generating an immediate reset.
+              
+        (#) Optionally you can enable the Early wakeup interrupt which is 
+            generated when the counter reach 0x40.
+            Once enabled this interrupt cannot be disabled except by a system reset.
+                   
+        (#) Then the application program must refresh the WWDG counter at regular
+            intervals during normal operation to prevent an MCU reset, using
+            WWDG_SetCounter() function. This operation must occur only when
+            the counter value is lower than the refresh window value, 
+            programmed using WWDG_SetWindowValue().
+  
+  *  @endverbatim  
+  *                             
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_wwdg.h"
+#include "stm32l1xx_rcc.h"
+
+/** @addtogroup STM32L1xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
+#define BIT_MASK          ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
+@verbatim   
+  ==============================================================================
+    ##### Prescaler, Refresh window and Counter configuration functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_MASK;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset. 
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset).
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_MASK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ *  @brief   WWDG activation functions 
+ *
+@verbatim   
+  ==============================================================================
+                     ##### WWDG activation function #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset).
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+  ==============================================================================
+                ##### Interrupts and flags management functions #####
+  ==============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html
new file mode 100644
index 0000000..cfaab7d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/Release_Notes.html
@@ -0,0 +1,871 @@
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+          <o:p>&nbsp;
+          </o:p>
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+      <div align="center">
+        <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900"> 
+          <tbody>
+            <tr style="">  
+              <td style="padding: 0in;" valign="top">  
+                <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">   
+                  <tbody>
+                    <tr style="">    
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+                        <p class="MsoNormal">
+                          <span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;">
+                            <a href="../../Release_Notes.html">Back to Release page</a>
+                          </span>
+                          <span style="font-size: 10pt;">
+                            <o:p>
+                            </o:p>
+                          </span>
+                        </p>    </td>   
+                    </tr>   
+                    <tr style="">    
+                      <td style="padding: 1.5pt;">    
+                        <h1 style="margin-bottom: 0.25in; text-align: center;" align="center">
+                          <span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for
+                          </span></h1>
+                        <h1 style="margin-bottom: 0.25in; text-align: center;" align="center">
+                          <span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">&nbsp;STM32F10x, STM32L1xx and STM32F3xx USB-FS-Device Driver
+                          </span>
+                          <span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+                            <o:p>
+                            </o:p>
+                          </span></h1>    
+                        <p class="MsoNormal" style="text-align: center;" align="center">
+                          <span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright     2012 STMicroelectronics
+                          </span>
+                          <span style="color: black;">
+                            <u1:p>
+                            </u1:p>
+                            <o:p>
+                            </o:p>
+                          </span>
+                        </p>    
+                        <p class="MsoNormal" style="text-align: center;" align="center">
+                          <span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">
+                            <img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86">
+                          </span>
+                          <span style="font-size: 10pt;">
+                            <o:p>
+                            </o:p>
+                          </span>
+                        </p>    </td>   
+                    </tr>  
+                  </tbody>
+                </table>  
+                <p class="MsoNormal">
+                  <span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;">
+                    <o:p>&nbsp;
+                    </o:p>
+                  </span>
+                </p>  
+                <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">   
+                  <tbody>
+                    <tr style="">    
+                      <td style="padding: 0in;" valign="top">    
+                        <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;">
+                          <span style="font-size: 12pt; color: white;">Contents
+                            <o:p>
+                            </o:p>
+                          </span></h2>    
+                        <ol style="margin-top: 0in;" start="1" type="1">     
+                          <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                            <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+                              <a href="#History">Update History</a>
+                              <o:p>
+                              </o:p>
+                            </span></li>     
+                          <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                            <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
+                              <a href="#License">License</a>
+                              <o:p>
+                              </o:p>
+                            </span></li>    
+                        </ol>    
+                        <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;">
+                          <a name="History"></a> <span style="font-size: 12pt; color: white;">Update History</span></h2><br>
+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 201px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.0 / 28-August-2012<o:p></o:p></span></h3>
+
+            
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+
+            
+            <ul style="margin-top: 0cm;" type="square">
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Remove support</span> of the <span style="font-weight: bold; font-style: italic;">USB OTG Full speed in device</span> (peripheral) mode embedded in the <span style="font-weight: bold; font-style: italic;">STM32F105x/7x devices</span></span></li>
+              <ul>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files starting with prefix <span style="font-style: italic;">otgd_fs</span> (ex. otgd_fs_pcd.c/.h) were removed</span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">There is no change on the <span style="font-weight: bold; font-style: italic;">API</span> dealing with the <span style="font-style: italic; font-weight: bold;">USB FS Device&nbsp; peripheral</span>, <span style="font-weight: bold; font-style: italic;">full compatibility</span> is maintained vs. V3.4.0<br>
+                  </span></li>
+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">The&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"> <span style="font-weight: bold; font-style: italic;">STM32F105x/7x devices</span></span><span style="font-size: 10pt; font-family: Verdana;"> are supported by the <span style="font-weight: bold; font-style: italic;">STM32F105/7xx, STM32F2xx and STM32F4xx USB On-The-Go Host and Device Library</span><br>
+                  </span></li>
+              </ul>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">usb_type.h: </span><span style="font-size: 10pt; font-family: Verdana;">remove Types definition (available in stm32xxx.h file, ex. stm32f10x.h)<br>
+                </span></li>
+            </ul>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 201px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.4.0 / 12-March-2012<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul>
+                        <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt; width: 200px;">
+                          <span style="font-size: 10pt; font-family: Arial; color: white;">V3.3.0 / 21-March-2011
+                          </span></h3>
+                        <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;">
+                          <b style=""><u>
+                              <span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes
+                                <o:p>
+                                </o:p>
+                              </span></u></b>
+                        </p>
+                        <ul style="margin-top: 0cm;" type="square">
+                          <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                            <span style="font-size: 10pt; font-family: Verdana;">Update library driver to support 
+                            </span>
+                            <span style="font-size: 10pt; font-family: Verdana; color: black;">
+                              <span style="font-weight: bold;">STM32L15x Medium-Density Low-Power
+                              </span> 
+                            </span>
+                            <span style="font-size: 10pt; font-family: Verdana;">devices (add STM32L1xx defines).
+                            </span></li>
+                          <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                            <span style="font-size: 10pt; font-family: Verdana;">Minor fixes:
+                            </span></li>
+                          <ul>
+                            <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                              <span style="font-size: 10pt; font-family: Verdana;">otgd_fs_cal.c: correction of iteration number in OTGD_FS_CoreInitDev() function.
+                              </span></li>
+                          </ul>
+                          <ul>
+                            <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                              <span style="font-size: 10pt; font-family: Verdana;">usb_core.c: update the remote wakeup checking condition in NoData_Setup0() function.
+                              </span></li>
+                          </ul>
+                          <ul>
+                            <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
+                              <span style="font-size: 10pt; font-family: Verdana;">otgd_fs_int.c: update the data count in case of 0 packet length in OTGD_FS_Handle_RxStatusQueueLevel_ISR() function.
+                              </span></li>
+                          </ul>
+                        </ul>
+                        <span style="font-size: 10pt; font-family: Verdana;">
+                        </span>
+                        
+                        <span style="font-size: 10pt; font-family: Verdana;">
+                        </span>
+                        <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;">
+                          <a name="License"></a>
+                          <span style="font-size: 12pt; color: white;">License
+                            <o:p>
+                            </o:p>
+                          </span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span>    
+                        <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;"><hr align="center" size="2" width="100%">    
+                          </span>
+                        </div>    
+                        <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center">
+                          <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
+    complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
+    Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;">
+                            <o:p>
+                            </o:p>
+                          </span>
+                        </p>    </td>   
+                    </tr>  
+                  </tbody>
+                </table>  
+                <p class="MsoNormal">
+                  <span style="font-size: 10pt;">
+                    <o:p>
+                    </o:p>
+                  </span>
+                </p>  </td> 
+            </tr>
+          </tbody>
+        </table>
+      </div>
+      <p class="MsoNormal">
+        <o:p>&nbsp;
+        </o:p>
+      </p>
+    </div>
+  </body></html>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h
new file mode 100644
index 0000000..bf303f7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_core.h
@@ -0,0 +1,259 @@
+/**
+  ******************************************************************************
+  * @file    usb_core.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Standard protocol processing functions prototypes
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CORE_H
+#define __USB_CORE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _CONTROL_STATE
+{
+  WAIT_SETUP,       /* 0 */
+  SETTING_UP,       /* 1 */
+  IN_DATA,          /* 2 */
+  OUT_DATA,         /* 3 */
+  LAST_IN_DATA,     /* 4 */
+  LAST_OUT_DATA,    /* 5 */
+  WAIT_STATUS_IN,   /* 7 */
+  WAIT_STATUS_OUT,  /* 8 */
+  STALLED,          /* 9 */
+  PAUSE             /* 10 */
+} CONTROL_STATE;    /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+  uint8_t *Descriptor;
+  uint16_t Descriptor_Size;
+}
+ONE_DESCRIPTOR, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+   If the return value is not SUCCESS or NOT_READY,
+   the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+  USB_SUCCESS = 0,    /* Process successfully */
+  USB_ERROR,
+  USB_UNSUPPORT,
+  USB_NOT_READY       /* The process has not been finished, endpoint will be
+                         NAK to further request */
+} RESULT;
+
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+  /* When send data out of the device,
+   CopyData() is used to get data buffer 'Length' bytes data
+   if Length is 0,
+    CopyData() returns the total length of the data
+    if the request is not supported, returns 0
+    (NEW Feature )
+     if CopyData() returns -1, the calling routine should not proceed
+     further and will resume the SETUP process by the class device
+   if Length is not 0,
+    CopyData() returns a pointer to indicate the data location
+   Usb_wLength is the data remain to be sent,
+   Usb_wOffset is the Offset of original data
+  When receive data from the host,
+   CopyData() is used to get user data buffer which is capable
+   of Length bytes data to copy data from the endpoint buffer.
+   if Length is 0,
+    CopyData() returns the available data length,
+   if Length is not 0,
+    CopyData() returns user buffer address
+   Usb_rLength is the data remain to be received,
+   Usb_rPointer is the Offset of data buffer
+  */
+  uint16_t  Usb_wLength;
+  uint16_t  Usb_wOffset;
+  uint16_t  PacketSize;
+  uint8_t   *(*CopyData)(uint16_t Length);
+}ENDPOINT_INFO;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+  uint8_t Total_Endpoint;     /* Number of endpoints that are used */
+  uint8_t Total_Configuration;/* Number of configuration available */
+}
+DEVICE;
+
+typedef union
+{
+  uint16_t w;
+  struct BW
+  {
+    uint8_t bb1;
+    uint8_t bb0;
+  }
+  bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+  uint8_t USBbmRequestType;       /* bmRequestType */
+  uint8_t USBbRequest;            /* bRequest */
+  uint16_t_uint8_t USBwValues;         /* wValue */
+  uint16_t_uint8_t USBwIndexs;         /* wIndex */
+  uint16_t_uint8_t USBwLengths;        /* wLength */
+
+  uint8_t ControlState;           /* of type CONTROL_STATE */
+  uint8_t Current_Feature;
+  uint8_t Current_Configuration;   /* Selected configuration */
+  uint8_t Current_Interface;       /* Selected interface of current configuration */
+  uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current
+                                     interface*/
+
+  ENDPOINT_INFO Ctrl_Info;
+}DEVICE_INFO;
+
+typedef struct _DEVICE_PROP
+{
+  void (*Init)(void);        /* Initialize the device */
+  void (*Reset)(void);       /* Reset routine of this device */
+
+  /* Device dependent process after the status stage */
+  void (*Process_Status_IN)(void);
+  void (*Process_Status_OUT)(void);
+
+  /* Procedure of process on setup stage of a class specified request with data stage */
+  /* All class specified requests with data stage are processed in Class_Data_Setup
+   Class_Data_Setup()
+    responses to check all special requests and fills ENDPOINT_INFO
+    according to the request
+    If IN tokens are expected, then wLength & wOffset will be filled
+    with the total transferring bytes and the starting position
+    If OUT tokens are expected, then rLength & rOffset will be filled
+    with the total expected bytes and the starting position in the buffer
+
+    If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+   CAUTION:
+    Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+    the individual classes, they will be checked and processed here.
+  */
+  RESULT (*Class_Data_Setup)(uint8_t RequestNo);
+
+  /* Procedure of process on setup stage of a class specified request without data stage */
+  /* All class specified requests without data stage are processed in Class_NoData_Setup
+   Class_NoData_Setup
+    responses to check all special requests and perform the request
+
+   CAUTION:
+    Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+    the individual classes, they will be checked and processed here.
+  */
+  RESULT (*Class_NoData_Setup)(uint8_t RequestNo);
+
+  /*Class_Get_Interface_Setting
+   This function is used by the file usb_core.c to test if the selected Interface
+   and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+   the application.
+   This function is writing by user. It should return "SUCCESS" if the Interface
+   and Alternate Setting are supported by the application or "UNSUPPORT" if they
+   are not supported. */
+
+  RESULT  (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+  uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+  uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+  uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+  /* This field is not used in current library version. It is kept only for 
+   compatibility with previous versions */
+  void* RxEP_buffer;
+   
+  uint8_t MaxPacketSize;
+
+}DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+  void (*User_GetConfiguration)(void);       /* Get Configuration */
+  void (*User_SetConfiguration)(void);       /* Set Configuration */
+  void (*User_GetInterface)(void);           /* Get Interface */
+  void (*User_SetInterface)(void);           /* Set Interface */
+  void (*User_GetStatus)(void);              /* Get Status */
+  void (*User_ClearFeature)(void);           /* Clear Feature */
+  void (*User_SetEndPointFeature)(void);     /* Set Endpoint Feature */
+  void (*User_SetDeviceFeature)(void);       /* Set Device Feature */
+  void (*User_SetDeviceAddress)(void);       /* Set Device Address */
+}
+USER_STANDARD_REQUESTS;
+
+/* Exported constants --------------------------------------------------------*/
+#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue USBwValues.w
+#define USBwValue0 USBwValues.bw.bb0
+#define USBwValue1 USBwValues.bw.bb1
+#define USBwIndex USBwIndexs.w
+#define USBwIndex0 USBwIndexs.bw.bb0
+#define USBwIndex1 USBwIndexs.bw.bb1
+#define USBwLength USBwLengths.w
+#define USBwLength0 USBwLengths.bw.bb0
+#define USBwLength1 USBwLengths.bw.bb1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t Setup0_Process(void);
+uint8_t Post0_Process(void);
+uint8_t Out0_Process(void);
+uint8_t In0_Process(void);
+
+RESULT Standard_SetEndPointFeature(void);
+RESULT Standard_SetDeviceFeature(void);
+
+uint8_t *Standard_GetConfiguration(uint16_t Length);
+RESULT Standard_SetConfiguration(void);
+uint8_t *Standard_GetInterface(uint16_t Length);
+RESULT Standard_SetInterface(void);
+uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t *Standard_GetStatus(uint16_t Length);
+RESULT Standard_ClearFeature(void);
+void SetDeviceAddress(uint8_t);
+void NOP_Process(void);
+
+extern DEVICE_PROP Device_Property;
+extern  USER_STANDARD_REQUESTS User_Standard_Requests;
+extern  DEVICE  Device_Table;
+extern DEVICE_INFO Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+#endif /* __USB_CORE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h
new file mode 100644
index 0000000..7f6e1b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_def.h
@@ -0,0 +1,92 @@
+/**
+  ******************************************************************************
+  * @file    usb_def.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Definitions related to USB Core
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DEF_H
+#define __USB_DEF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RECIPIENT_TYPE
+{
+  DEVICE_RECIPIENT,     /* Recipient device */
+  INTERFACE_RECIPIENT,  /* Recipient interface */
+  ENDPOINT_RECIPIENT,   /* Recipient endpoint */
+  OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+
+typedef enum _STANDARD_REQUESTS
+{
+  GET_STATUS = 0,
+  CLEAR_FEATURE,
+  RESERVED1,
+  SET_FEATURE,
+  RESERVED2,
+  SET_ADDRESS,
+  GET_DESCRIPTOR,
+  SET_DESCRIPTOR,
+  GET_CONFIGURATION,
+  SET_CONFIGURATION,
+  GET_INTERFACE,
+  SET_INTERFACE,
+  TOTAL_sREQUEST,  /* Total number of Standard request */
+  SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+  DEVICE_DESCRIPTOR = 1,
+  CONFIG_DESCRIPTOR,
+  STRING_DESCRIPTOR,
+  INTERFACE_DESCRIPTOR,
+  ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+  ENDPOINT_STALL,
+  DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Exported constants --------------------------------------------------------*/
+/* Definition of "USBbmRequestType" */
+#define REQUEST_TYPE      0x60  /* Mask to get request type */
+#define STANDARD_REQUEST  0x00  /* Standard request */
+#define CLASS_REQUEST     0x20  /* Class request */
+#define VENDOR_REQUEST    0x40  /* Vendor request */
+
+#define RECIPIENT         0x1F  /* Mask to get recipient */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __USB_DEF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h
new file mode 100644
index 0000000..44b528c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_init.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    usb_init.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Initialization routines & global variables
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_INIT_H
+#define __USB_INIT_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void USB_Init(void);
+
+/* External variables --------------------------------------------------------*/
+/*  The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t	EPindex;
+/*  The number of current device, it is an index to the Device_Table */
+/*extern uint8_t	Device_no; */
+/*  Points to the DEVICE_INFO structure of current device */
+/*  The purpose of this register is to speed up the execution */
+extern DEVICE_INFO*	pInformation;
+/*  Points to the DEVICE_PROP structure of current device */
+/*  The purpose of this register is to speed up the execution */
+extern DEVICE_PROP*	pProperty;
+/*  Temporary save the state of Rx & Tx status. */
+/*  Whenever the Rx or Tx state is changed, its value is saved */
+/*  in this variable first and will be set to the EPRB or EPRA */
+/*  at the end of interrupt process */
+extern USER_STANDARD_REQUESTS *pUser_Standard_Requests;
+
+extern uint16_t	SaveState ;
+extern uint16_t wInterrupt_Mask;
+
+#endif /* __USB_INIT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h
new file mode 100644
index 0000000..307ab14
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_int.h
@@ -0,0 +1,45 @@
+/**
+  ******************************************************************************
+  * @file    usb_int.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Endpoint CTR (Low and High) interrupt's service routines prototypes
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_INT_H
+#define __USB_INT_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void CTR_LP(void);
+void CTR_HP(void);
+
+/* External variables --------------------------------------------------------*/
+
+#endif /* __USB_INT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h
new file mode 100644
index 0000000..0b29100
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_mem.h
@@ -0,0 +1,45 @@
+/**
+  ******************************************************************************
+  * @file    usb_mem.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Utility prototypes functions for memory/PMA transfers
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_MEM_H
+#define __USB_MEM_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/* External variables --------------------------------------------------------*/
+
+#endif  /*__USB_MEM_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h
new file mode 100644
index 0000000..21e1670
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/inc/usb_type.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    usb_type.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Type definitions used by the USB Library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_TYPE_H
+#define __USB_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+typedef enum
+{
+  FALSE = 0, TRUE  = !FALSE
+}
+bool;
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+
+#endif /* __USB_TYPE_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c
new file mode 100644
index 0000000..3231a96
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c
@@ -0,0 +1,1033 @@
+/**
+  ******************************************************************************
+  * @file    usb_core.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Standard protocol processing (USB v2.0)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define ValBit(VAR,Place)    (VAR & (1 << Place))
+#define SetBit(VAR,Place)    (VAR |= (1 << Place))
+#define ClrBit(VAR,Place)    (VAR &= ((1 << Place) ^ 255))
+#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \
+    vSetEPTxStatus(EP_TX_VALID); \
+  }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = FALSE;
+/* Private function prototypes -----------------------------------------------*/
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Standard_GetConfiguration.
+* Description    : Return the current configuration variable address.
+* Input          : Length - How many bytes are needed.
+* Output         : None.
+* Return         : Return 1 , if the request is invalid when "Length" is 0.
+*                  Return "Buffer" if the "Length" is not 0.
+*******************************************************************************/
+uint8_t *Standard_GetConfiguration(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength =
+      sizeof(pInformation->Current_Configuration);
+    return 0;
+  }
+  pUser_Standard_Requests->User_GetConfiguration();
+  return (uint8_t *)&pInformation->Current_Configuration;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_SetConfiguration.
+* Description    : This routine is called to set the configuration value
+*                  Then each class should configure device itself.
+* Input          : None.
+* Output         : None.
+* Return         : Return USB_SUCCESS, if the request is performed.
+*                  Return USB_UNSUPPORT, if the request is invalid.
+*******************************************************************************/
+RESULT Standard_SetConfiguration(void)
+{
+
+  if ((pInformation->USBwValue0 <=
+      Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0)
+      && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+  {
+    pInformation->Current_Configuration = pInformation->USBwValue0;
+    pUser_Standard_Requests->User_SetConfiguration();
+    return USB_SUCCESS;
+  }
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Standard_GetInterface.
+* Description    : Return the Alternate Setting of the current interface.
+* Input          : Length - How many bytes are needed.
+* Output         : None.
+* Return         : Return 0, if the request is invalid when "Length" is 0.
+*                  Return "Buffer" if the "Length" is not 0.
+*******************************************************************************/
+uint8_t *Standard_GetInterface(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength =
+      sizeof(pInformation->Current_AlternateSetting);
+    return 0;
+  }
+  pUser_Standard_Requests->User_GetInterface();
+  return (uint8_t *)&pInformation->Current_AlternateSetting;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_SetInterface.
+* Description    : This routine is called to set the interface.
+*                  Then each class should configure the interface them self.
+* Input          : None.
+* Output         : None.
+* Return         : - Return USB_SUCCESS, if the request is performed.
+*                  - Return USB_UNSUPPORT, if the request is invalid.
+*******************************************************************************/
+RESULT Standard_SetInterface(void)
+{
+  RESULT Re;
+  /*Test if the specified Interface and Alternate Setting are supported by
+    the application Firmware*/
+  Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+  if (pInformation->Current_Configuration != 0)
+  {
+    if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0)
+        || (pInformation->USBwValue1 != 0))
+    {
+      return  USB_UNSUPPORT;
+    }
+    else if (Re == USB_SUCCESS)
+    {
+      pUser_Standard_Requests->User_SetInterface();
+      pInformation->Current_Interface = pInformation->USBwIndex0;
+      pInformation->Current_AlternateSetting = pInformation->USBwValue0;
+      return USB_SUCCESS;
+    }
+
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_GetStatus.
+* Description    : Copy the device request data to "StatusInfo buffer".
+* Input          : - Length - How many bytes are needed.
+* Output         : None.
+* Return         : Return 0, if the request is at end of data block,
+*                  or is invalid when "Length" is 0.
+*******************************************************************************/
+uint8_t *Standard_GetStatus(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 2;
+    return 0;
+  }
+
+  /* Reset Status Information */
+  StatusInfo.w = 0;
+
+  if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {
+    /*Get Device Status */
+    uint8_t Feature = pInformation->Current_Feature;
+
+    /* Remote Wakeup enabled */
+    if (ValBit(Feature, 5))
+    {
+      SetBit(StatusInfo0, 1);
+    }
+    else
+    {
+      ClrBit(StatusInfo0, 1);
+    }      
+
+    /* Bus-powered */
+    if (ValBit(Feature, 6))
+    {
+      SetBit(StatusInfo0, 0);
+    }
+    else /* Self-powered */
+    {
+      ClrBit(StatusInfo0, 0);
+    }
+  }
+  /*Interface Status*/
+  else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+  {
+    return (uint8_t *)&StatusInfo;
+  }
+  /*Get EndPoint Status*/
+  else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {
+    uint8_t Related_Endpoint;
+    uint8_t wIndex0 = pInformation->USBwIndex0;
+
+    Related_Endpoint = (wIndex0 & 0x0f);
+    if (ValBit(wIndex0, 7))
+    {
+      /* IN endpoint */
+      if (_GetTxStallStatus(Related_Endpoint))
+      {
+        SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+      }
+    }
+    else
+    {
+      /* OUT endpoint */
+      if (_GetRxStallStatus(Related_Endpoint))
+      {
+        SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+      }
+    }
+
+  }
+  else
+  {
+    return NULL;
+  }
+  pUser_Standard_Requests->User_GetStatus();
+  return (uint8_t *)&StatusInfo;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_ClearFeature.
+* Description    : Clear or disable a specific feature.
+* Input          : None.
+* Output         : None.
+* Return         : - Return USB_SUCCESS, if the request is performed.
+*                  - Return USB_UNSUPPORT, if the request is invalid.
+*******************************************************************************/
+RESULT Standard_ClearFeature(void)
+{
+  uint32_t     Type_Rec = Type_Recipient;
+  uint32_t     Status;
+
+
+  if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {/*Device Clear Feature*/
+    ClrBit(pInformation->Current_Feature, 5);
+    return USB_SUCCESS;
+  }
+  else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {/*EndPoint Clear Feature*/
+    DEVICE* pDev;
+    uint32_t Related_Endpoint;
+    uint32_t wIndex0;
+    uint32_t rEP;
+
+    if ((pInformation->USBwValue != ENDPOINT_STALL)
+        || (pInformation->USBwIndex1 != 0))
+    {
+      return USB_UNSUPPORT;
+    }
+
+    pDev = &Device_Table;
+    wIndex0 = pInformation->USBwIndex0;
+    rEP = wIndex0 & ~0x80;
+    Related_Endpoint = ENDP0 + rEP;
+
+    if (ValBit(pInformation->USBwIndex0, 7))
+    {
+      /*Get Status of endpoint & stall the request if the related_ENdpoint
+      is Disabled*/
+      Status = _GetEPTxStatus(Related_Endpoint);
+    }
+    else
+    {
+      Status = _GetEPRxStatus(Related_Endpoint);
+    }
+
+    if ((rEP >= pDev->Total_Endpoint) || (Status == 0)
+        || (pInformation->Current_Configuration == 0))
+    {
+      return USB_UNSUPPORT;
+    }
+
+
+    if (wIndex0 & 0x80)
+    {
+      /* IN endpoint */
+      if (_GetTxStallStatus(Related_Endpoint ))
+      {
+        ClearDTOG_TX(Related_Endpoint);
+        SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+      }
+    }
+    else
+    {
+      /* OUT endpoint */
+      if (_GetRxStallStatus(Related_Endpoint))
+      {
+        if (Related_Endpoint == ENDP0)
+        {
+          /* After clear the STALL, enable the default endpoint receiver */
+          SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
+          _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+        }
+        else
+        {
+          ClearDTOG_RX(Related_Endpoint);
+          _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+        }
+      }
+    }
+    pUser_Standard_Requests->User_ClearFeature();
+    return USB_SUCCESS;
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_SetEndPointFeature
+* Description    : Set or enable a specific feature of EndPoint
+* Input          : None.
+* Output         : None.
+* Return         : - Return USB_SUCCESS, if the request is performed.
+*                  - Return USB_UNSUPPORT, if the request is invalid.
+*******************************************************************************/
+RESULT Standard_SetEndPointFeature(void)
+{
+  uint32_t    wIndex0;
+  uint32_t    Related_Endpoint;
+  uint32_t    rEP;
+  uint32_t    Status;
+
+  wIndex0 = pInformation->USBwIndex0;
+  rEP = wIndex0 & ~0x80;
+  Related_Endpoint = ENDP0 + rEP;
+
+  if (ValBit(pInformation->USBwIndex0, 7))
+  {
+    /* get Status of endpoint & stall the request if the related_ENdpoint
+    is Disabled*/
+    Status = _GetEPTxStatus(Related_Endpoint);
+  }
+  else
+  {
+    Status = _GetEPRxStatus(Related_Endpoint);
+  }
+
+  if (Related_Endpoint >= Device_Table.Total_Endpoint
+      || pInformation->USBwValue != 0 || Status == 0
+      || pInformation->Current_Configuration == 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else
+  {
+    if (wIndex0 & 0x80)
+    {
+      /* IN endpoint */
+      _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+    }
+
+    else
+    {
+      /* OUT endpoint */
+      _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+    }
+  }
+  pUser_Standard_Requests->User_SetEndPointFeature();
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_SetDeviceFeature.
+* Description    : Set or enable a specific feature of Device.
+* Input          : None.
+* Output         : None.
+* Return         : - Return USB_SUCCESS, if the request is performed.
+*                  - Return USB_UNSUPPORT, if the request is invalid.
+*******************************************************************************/
+RESULT Standard_SetDeviceFeature(void)
+{
+  SetBit(pInformation->Current_Feature, 5);
+  pUser_Standard_Requests->User_SetDeviceFeature();
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Standard_GetDescriptorData.
+* Description    : Standard_GetDescriptorData is used for descriptors transfer.
+*                : This routine is used for the descriptors resident in Flash
+*                  or RAM
+*                  pDesc can be in either Flash or RAM
+*                  The purpose of this routine is to have a versatile way to
+*                  response descriptors request. It allows user to generate
+*                  certain descriptors with software or read descriptors from
+*                  external storage part by part.
+* Input          : - Length - Length of the data in this transfer.
+*                  - pDesc - A pointer points to descriptor struct.
+*                  The structure gives the initial address of the descriptor and
+*                  its original size.
+* Output         : None.
+* Return         : Address of a part of the descriptor pointed by the Usb_
+*                  wOffset The buffer pointed by this address contains at least
+*                  Length bytes.
+*******************************************************************************/
+uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc)
+{
+  uint32_t  wOffset;
+
+  wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+    return 0;
+  }
+
+  return pDesc->Descriptor + wOffset;
+}
+
+/*******************************************************************************
+* Function Name  : DataStageOut.
+* Description    : Data stage of a Control Write Transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DataStageOut(void)
+{
+  ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+  uint32_t save_rLength;
+
+  save_rLength = pEPinfo->Usb_rLength;
+
+  if (pEPinfo->CopyData && save_rLength)
+  {
+    uint8_t *Buffer;
+    uint32_t Length;
+
+    Length = pEPinfo->PacketSize;
+    if (Length > save_rLength)
+    {
+      Length = save_rLength;
+    }
+
+    Buffer = (*pEPinfo->CopyData)(Length);
+    pEPinfo->Usb_rLength -= Length;
+    pEPinfo->Usb_rOffset += Length;
+    PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
+
+  }
+
+  if (pEPinfo->Usb_rLength != 0)
+  {
+    vSetEPRxStatus(EP_RX_VALID);/* re-enable for next data reception */
+    SetEPTxCount(ENDP0, 0);
+    vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */
+  }
+  /* Set the next State*/
+  if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+  {
+    pInformation->ControlState = OUT_DATA;
+  }
+  else
+  {
+    if (pEPinfo->Usb_rLength > 0)
+    {
+      pInformation->ControlState = LAST_OUT_DATA;
+    }
+    else if (pEPinfo->Usb_rLength == 0)
+    {
+      pInformation->ControlState = WAIT_STATUS_IN;
+      USB_StatusIn();
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DataStageIn.
+* Description    : Data stage of a Control Read Transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DataStageIn(void)
+{
+  ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+  uint32_t save_wLength = pEPinfo->Usb_wLength;
+  uint32_t ControlState = pInformation->ControlState;
+
+  uint8_t *DataBuffer;
+  uint32_t Length;
+
+  if ((save_wLength == 0) && (ControlState == LAST_IN_DATA))
+  {
+    if(Data_Mul_MaxPacketSize == TRUE)
+    {
+      /* No more data to send and empty packet */
+      Send0LengthData();
+      ControlState = LAST_IN_DATA;
+      Data_Mul_MaxPacketSize = FALSE;
+    }
+    else 
+    {
+      /* No more data to send so STALL the TX Status*/
+      ControlState = WAIT_STATUS_OUT;
+      vSetEPTxStatus(EP_TX_STALL);
+ 
+    }
+    
+    goto Expect_Status_Out;
+  }
+
+  Length = pEPinfo->PacketSize;
+  ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA;
+
+  if (Length > save_wLength)
+  {
+    Length = save_wLength;
+  }
+
+  DataBuffer = (*pEPinfo->CopyData)(Length);
+  
+  UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length);
+
+  SetEPTxCount(ENDP0, Length);
+
+  pEPinfo->Usb_wLength -= Length;
+  pEPinfo->Usb_wOffset += Length;
+  vSetEPTxStatus(EP_TX_VALID);
+
+  USB_StatusOut();/* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+  pInformation->ControlState = ControlState;
+}
+
+/*******************************************************************************
+* Function Name  : NoData_Setup0.
+* Description    : Proceed the processing of setup request without data stage.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void NoData_Setup0(void)
+{
+  RESULT Result = USB_UNSUPPORT;
+  uint32_t RequestNo = pInformation->USBbRequest;
+  uint32_t ControlState;
+
+  if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+  {
+    /* Device Request*/
+    /* SET_CONFIGURATION*/
+    if (RequestNo == SET_CONFIGURATION)
+    {
+      Result = Standard_SetConfiguration();
+    }
+
+    /*SET ADDRESS*/
+    else if (RequestNo == SET_ADDRESS)
+    {
+      if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0)
+          || (pInformation->USBwIndex != 0)
+          || (pInformation->Current_Configuration != 0))
+        /* Device Address should be 127 or less*/
+      {
+        ControlState = STALLED;
+        goto exit_NoData_Setup0;
+      }
+      else
+      {
+        Result = USB_SUCCESS;
+      }
+    }
+    /*SET FEATURE for Device*/
+    else if (RequestNo == SET_FEATURE)
+    {
+      if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \
+          && (pInformation->USBwIndex == 0))
+      {
+        Result = Standard_SetDeviceFeature();
+      }
+      else
+      {
+        Result = USB_UNSUPPORT;
+      }
+    }
+    /*Clear FEATURE for Device */
+    else if (RequestNo == CLEAR_FEATURE)
+    {
+      if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP
+          && pInformation->USBwIndex == 0
+          && ValBit(pInformation->Current_Feature, 5))
+      {
+        Result = Standard_ClearFeature();
+      }
+      else
+      {
+        Result = USB_UNSUPPORT;
+      }
+    }
+
+  }
+
+  /* Interface Request*/
+  else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+  {
+    /*SET INTERFACE*/
+    if (RequestNo == SET_INTERFACE)
+    {
+      Result = Standard_SetInterface();
+    }
+  }
+
+  /* EndPoint Request*/
+  else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+  {
+    /*CLEAR FEATURE for EndPoint*/
+    if (RequestNo == CLEAR_FEATURE)
+    {
+      Result = Standard_ClearFeature();
+    }
+    /* SET FEATURE for EndPoint*/
+    else if (RequestNo == SET_FEATURE)
+    {
+      Result = Standard_SetEndPointFeature();
+    }
+  }
+  else
+  {
+    Result = USB_UNSUPPORT;
+  }
+
+
+  if (Result != USB_SUCCESS)
+  {
+    Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+    if (Result == USB_NOT_READY)
+    {
+      ControlState = PAUSE;
+      goto exit_NoData_Setup0;
+    }
+  }
+
+  if (Result != USB_SUCCESS)
+  {
+    ControlState = STALLED;
+    goto exit_NoData_Setup0;
+  }
+
+  ControlState = WAIT_STATUS_IN;/* After no data stage SETUP */
+
+  USB_StatusIn();
+
+exit_NoData_Setup0:
+  pInformation->ControlState = ControlState;
+  return;
+}
+
+/*******************************************************************************
+* Function Name  : Data_Setup0.
+* Description    : Proceed the processing of setup request with data stage.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Data_Setup0(void)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+  RESULT Result;
+  uint32_t Request_No = pInformation->USBbRequest;
+
+  uint32_t Related_Endpoint, Reserved;
+  uint32_t wOffset, Status;
+
+
+
+  CopyRoutine = NULL;
+  wOffset = 0;
+
+  /*GET DESCRIPTOR*/
+  if (Request_No == GET_DESCRIPTOR)
+  {
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+      uint8_t wValue1 = pInformation->USBwValue1;
+      if (wValue1 == DEVICE_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetDeviceDescriptor;
+      }
+      else if (wValue1 == CONFIG_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetConfigDescriptor;
+      }
+      else if (wValue1 == STRING_DESCRIPTOR)
+      {
+        CopyRoutine = pProperty->GetStringDescriptor;
+      }  /* End of GET_DESCRIPTOR */
+    }
+  }
+
+  /*GET STATUS*/
+  else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0)
+           && (pInformation->USBwLength == 0x0002)
+           && (pInformation->USBwIndex1 == 0))
+  {
+    /* GET STATUS for Device*/
+    if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+        && (pInformation->USBwIndex == 0))
+    {
+      CopyRoutine = Standard_GetStatus;
+    }
+
+    /* GET STATUS for Interface*/
+    else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+    {
+      if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)
+          && (pInformation->Current_Configuration != 0))
+      {
+        CopyRoutine = Standard_GetStatus;
+      }
+    }
+
+    /* GET STATUS for EndPoint*/
+    else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+    {
+      Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+      Reserved = pInformation->USBwIndex0 & 0x70;
+
+      if (ValBit(pInformation->USBwIndex0, 7))
+      {
+        /*Get Status of endpoint & stall the request if the related_ENdpoint
+        is Disabled*/
+        Status = _GetEPTxStatus(Related_Endpoint);
+      }
+      else
+      {
+        Status = _GetEPRxStatus(Related_Endpoint);
+      }
+
+      if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0)
+          && (Status != 0))
+      {
+        CopyRoutine = Standard_GetStatus;
+      }
+    }
+
+  }
+
+  /*GET CONFIGURATION*/
+  else if (Request_No == GET_CONFIGURATION)
+  {
+    if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+    {
+      CopyRoutine = Standard_GetConfiguration;
+    }
+  }
+  /*GET INTERFACE*/
+  else if (Request_No == GET_INTERFACE)
+  {
+    if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+        && (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0)
+        && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+        && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS))
+    {
+      CopyRoutine = Standard_GetInterface;
+    }
+
+  }
+  
+  if (CopyRoutine)
+  {
+    pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+    pInformation->Ctrl_Info.CopyData = CopyRoutine;
+    /* sb in the original the cast to word was directly */
+    /* now the cast is made step by step */
+    (*CopyRoutine)(0);
+    Result = USB_SUCCESS;
+  }
+  else
+  {
+    Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest);
+    if (Result == USB_NOT_READY)
+    {
+      pInformation->ControlState = PAUSE;
+      return;
+    }
+  }
+
+  if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+  {
+    /* Data is not ready, wait it */
+    pInformation->ControlState = PAUSE;
+    return;
+  }
+  if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+  {
+    /* Unsupported request */
+    pInformation->ControlState = STALLED;
+    return;
+  }
+
+
+  if (ValBit(pInformation->USBbmRequestType, 7))
+  {
+    /* Device ==> Host */
+    __IO uint32_t wLength = pInformation->USBwLength;
+     
+    /* Restrict the data length to be the one host asks for */
+    if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+    {
+      pInformation->Ctrl_Info.Usb_wLength = wLength;
+    }
+    
+    else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+    {
+      if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+      {
+        Data_Mul_MaxPacketSize = FALSE;
+      }
+      else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+      {
+        Data_Mul_MaxPacketSize = TRUE;
+      }
+    }   
+
+    pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+    DataStageIn();
+  }
+  else
+  {
+    pInformation->ControlState = OUT_DATA;
+    vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+  }
+
+  return;
+}
+
+/*******************************************************************************
+* Function Name  : Setup0_Process
+* Description    : Get the device request data and dispatch to individual process.
+* Input          : None.
+* Output         : None.
+* Return         : Post0_Process.
+*******************************************************************************/
+uint8_t Setup0_Process(void)
+{
+
+  union
+  {
+    uint8_t* b;
+    uint16_t* w;
+  } pBuf;
+  uint16_t offset = 1;
+  
+  pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+  if (pInformation->ControlState != PAUSE)
+  {
+    pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */
+    pInformation->USBbRequest = *pBuf.b++; /* bRequest */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwIndex  = ByteSwap(*pBuf.w++); /* wIndex */
+    pBuf.w += offset;  /* word not accessed because of 32 bits addressing */
+    pInformation->USBwLength = *pBuf.w; /* wLength */
+  }
+
+  pInformation->ControlState = SETTING_UP;
+  if (pInformation->USBwLength == 0)
+  {
+    /* Setup with no data stage */
+    NoData_Setup0();
+  }
+  else
+  {
+    /* Setup with data stage */
+    Data_Setup0();
+  }
+  return Post0_Process();
+}
+
+/*******************************************************************************
+* Function Name  : In0_Process
+* Description    : Process the IN token on all default endpoint.
+* Input          : None.
+* Output         : None.
+* Return         : Post0_Process.
+*******************************************************************************/
+uint8_t In0_Process(void)
+{
+  uint32_t ControlState = pInformation->ControlState;
+
+  if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+  {
+    DataStageIn();
+    /* ControlState may be changed outside the function */
+    ControlState = pInformation->ControlState;
+  }
+
+  else if (ControlState == WAIT_STATUS_IN)
+  {
+    if ((pInformation->USBbRequest == SET_ADDRESS) &&
+        (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+    {
+      SetDeviceAddress(pInformation->USBwValue0);
+      pUser_Standard_Requests->User_SetDeviceAddress();
+    }
+    (*pProperty->Process_Status_IN)();
+    ControlState = STALLED;
+  }
+
+  else
+  {
+    ControlState = STALLED;
+  }
+
+  pInformation->ControlState = ControlState;
+
+  return Post0_Process();
+}
+
+/*******************************************************************************
+* Function Name  : Out0_Process
+* Description    : Process the OUT token on all default endpoint.
+* Input          : None.
+* Output         : None.
+* Return         : Post0_Process.
+*******************************************************************************/
+uint8_t Out0_Process(void)
+{
+  uint32_t ControlState = pInformation->ControlState;
+
+  if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+  {
+    /* host aborts the transfer before finish */
+    ControlState = STALLED;
+  }
+  else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
+  {
+    DataStageOut();
+    ControlState = pInformation->ControlState; /* may be changed outside the function */
+  }
+
+  else if (ControlState == WAIT_STATUS_OUT)
+  {
+    (*pProperty->Process_Status_OUT)();
+    ControlState = STALLED;
+  }
+
+
+  /* Unexpect state, STALL the endpoint */
+  else
+  {
+    ControlState = STALLED;
+  }
+
+  pInformation->ControlState = ControlState;
+
+  return Post0_Process();
+}
+
+/*******************************************************************************
+* Function Name  : Post0_Process
+* Description    : Stall the Endpoint 0 in case of error.
+* Input          : None.
+* Output         : None.
+* Return         : - 0 if the control State is in PAUSE
+*                  - 1 if not.
+*******************************************************************************/
+uint8_t Post0_Process(void)
+{
+   
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+
+  if (pInformation->ControlState == STALLED)
+  {
+    vSetEPRxStatus(EP_RX_STALL);
+    vSetEPTxStatus(EP_TX_STALL);
+  }
+
+  return (pInformation->ControlState == PAUSE);
+}
+
+/*******************************************************************************
+* Function Name  : SetDeviceAddress.
+* Description    : Set the device and all the used Endpoints addresses.
+* Input          : - Val: device address.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SetDeviceAddress(uint8_t Val)
+{
+  uint32_t i;
+  uint32_t nEP = Device_Table.Total_Endpoint;
+
+  /* set address in every used endpoint */
+  for (i = 0; i < nEP; i++)
+  {
+    _SetEPAddress((uint8_t)i, (uint8_t)i);
+  } /* for */
+  _SetDADDR(Val | DADDR_EF); /* set device address and enable function */ 
+}
+
+/*******************************************************************************
+* Function Name  : NOP_Process
+* Description    : No operation function.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void NOP_Process(void)
+{
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c
new file mode 100644
index 0000000..0949620
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c
@@ -0,0 +1,76 @@
+/**
+  ******************************************************************************
+  * @file    usb_init.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Initialization routines & global variables
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/*  The number of current endpoint, it will be used to specify an endpoint */
+ uint8_t	EPindex;
+/*  The number of current device, it is an index to the Device_Table */
+/* uint8_t	Device_no; */
+/*  Points to the DEVICE_INFO structure of current device */
+/*  The purpose of this register is to speed up the execution */
+DEVICE_INFO *pInformation;
+/*  Points to the DEVICE_PROP structure of current device */
+/*  The purpose of this register is to speed up the execution */
+DEVICE_PROP *pProperty;
+/*  Temporary save the state of Rx & Tx status. */
+/*  Whenever the Rx or Tx state is changed, its value is saved */
+/*  in this variable first and will be set to the EPRB or EPRA */
+/*  at the end of interrupt process */
+uint16_t	SaveState ;
+uint16_t  wInterrupt_Mask;
+DEVICE_INFO	Device_Info;
+USER_STANDARD_REQUESTS  *pUser_Standard_Requests;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : USB_Init
+* Description    : USB system initialization
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Init(void)
+{
+  pInformation = &Device_Info;
+  pInformation->ControlState = 2;
+  pProperty = &Device_Property;
+  pUser_Standard_Requests = &User_Standard_Requests;
+  /* Initialize devices one by one */
+  pProperty->Init();
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c
new file mode 100644
index 0000000..dbaa331
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c
@@ -0,0 +1,195 @@
+/**
+  ******************************************************************************
+  * @file    usb_int.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Endpoint CTR (Low and High) interrupt's service routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+/* Extern variables ----------------------------------------------------------*/
+extern void (*pEpInt_IN[7])(void);    /*  Handles IN  interrupts   */
+extern void (*pEpInt_OUT[7])(void);   /*  Handles OUT interrupts   */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : CTR_LP.
+* Description    : Low priority Endpoint Correct Transfer interrupt's service
+*                  routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CTR_LP(void)
+{
+  __IO uint16_t wEPVal = 0;
+  /* stay in loop while pending interrupts */
+  while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
+  {
+    /* extract highest priority endpoint number */
+    EPindex = (uint8_t)(wIstr & ISTR_EP_ID);
+    if (EPindex == 0)
+    {
+      /* Decode and service control endpoint interrupt */
+      /* calling related service routine */
+      /* (Setup0_Process, In0_Process, Out0_Process) */
+
+      /* save RX & TX status */
+      /* and set both to NAK */
+      
+	    SaveRState = _GetENDPOINT(ENDP0);
+	    SaveTState = SaveRState & EPTX_STAT;
+	    SaveRState &=  EPRX_STAT;	
+
+	    _SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK);
+
+      /* DIR bit = origin of the interrupt */
+
+      if ((wIstr & ISTR_DIR) == 0)
+      {
+        /* DIR = 0 */
+
+        /* DIR = 0      => IN  int */
+        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
+
+        _ClearEP_CTR_TX(ENDP0);
+        In0_Process();
+
+           /* before terminate set Tx & Rx status */
+
+            _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+		  return;
+      }
+      else
+      {
+        /* DIR = 1 */
+
+        /* DIR = 1 & CTR_RX       => SETUP or OUT int */
+        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+        wEPVal = _GetENDPOINT(ENDP0);
+        
+        if ((wEPVal &EP_SETUP) != 0)
+        {
+          _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+          Setup0_Process();
+          /* before terminate set Tx & Rx status */
+
+		      _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+          return;
+        }
+
+        else if ((wEPVal & EP_CTR_RX) != 0)
+        {
+          _ClearEP_CTR_RX(ENDP0);
+          Out0_Process();
+          /* before terminate set Tx & Rx status */
+     
+		     _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+          return;
+        }
+      }
+    }/* if(EPindex == 0) */
+    else
+    {
+      /* Decode and service non control endpoints interrupt  */
+
+      /* process related endpoint register */
+      wEPVal = _GetENDPOINT(EPindex);
+      if ((wEPVal & EP_CTR_RX) != 0)
+      {
+        /* clear int flag */
+        _ClearEP_CTR_RX(EPindex);
+
+        /* call OUT service function */
+        (*pEpInt_OUT[EPindex-1])();
+
+      } /* if((wEPVal & EP_CTR_RX) */
+
+      if ((wEPVal & EP_CTR_TX) != 0)
+      {
+        /* clear int flag */
+        _ClearEP_CTR_TX(EPindex);
+
+        /* call IN service function */
+        (*pEpInt_IN[EPindex-1])();
+      } /* if((wEPVal & EP_CTR_TX) != 0) */
+
+    }/* if(EPindex == 0) else */
+
+  }/* while(...) */
+}
+
+/*******************************************************************************
+* Function Name  : CTR_HP.
+* Description    : High Priority Endpoint Correct Transfer interrupt's service 
+*                  routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CTR_HP(void)
+{
+  uint32_t wEPVal = 0;
+
+  while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
+  {
+    _SetISTR((uint16_t)CLR_CTR); /* clear CTR flag */
+    /* extract highest priority endpoint number */
+    EPindex = (uint8_t)(wIstr & ISTR_EP_ID);
+    /* process related endpoint register */
+    wEPVal = _GetENDPOINT(EPindex);
+    if ((wEPVal & EP_CTR_RX) != 0)
+    {
+      /* clear int flag */
+      _ClearEP_CTR_RX(EPindex);
+
+      /* call OUT service function */
+      (*pEpInt_OUT[EPindex-1])();
+
+    } /* if((wEPVal & EP_CTR_RX) */
+    else if ((wEPVal & EP_CTR_TX) != 0)
+    {
+      /* clear int flag */
+      _ClearEP_CTR_TX(EPindex);
+
+      /* call IN service function */
+      (*pEpInt_IN[EPindex-1])();
+
+
+    } /* if((wEPVal & EP_CTR_TX) != 0) */
+
+  }/* while(...) */
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c
new file mode 100644
index 0000000..5f2e4db
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    usb_sil.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    28-August-2012
+  * @brief   Simplified Interface Layer for Global Initialization and Endpoint
+  *          Rea/Write operations.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : USB_SIL_Init
+* Description    : Initialize the USB Device IP and the Endpoint 0.
+* Input          : None.
+* Output         : None.
+* Return         : Status.
+*******************************************************************************/
+uint32_t USB_SIL_Init(void)
+{
+  /* USB interrupts initialization */
+  /* clear pending interrupts */
+  _SetISTR(0);
+  wInterrupt_Mask = IMR_MSK;
+  /* set interrupts mask */
+  _SetCNTR(wInterrupt_Mask);
+  return 0;
+}
+
+/*******************************************************************************
+* Function Name  : USB_SIL_Write
+* Description    : Write a buffer of data to a selected endpoint.
+* Input          : - bEpAddr: The address of the non control endpoint.
+*                  - pBufferPointer: The pointer to the buffer of data to be written
+*                    to the endpoint.
+*                  - wBufferSize: Number of data to be written (in bytes).
+* Output         : None.
+* Return         : Status.
+*******************************************************************************/
+uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize)
+{
+  /* Use the memory interface function to write to the selected endpoint */
+  UserToPMABufferCopy(pBufferPointer, GetEPTxAddr(bEpAddr & 0x7F), wBufferSize);
+
+  /* Update the data length in the control register */
+  SetEPTxCount((bEpAddr & 0x7F), wBufferSize);
+  
+  return 0;
+}
+
+/*******************************************************************************
+* Function Name  : USB_SIL_Read
+* Description    : Write a buffer of data to a selected endpoint.
+* Input          : - bEpAddr: The address of the non control endpoint.
+*                  - pBufferPointer: The pointer to which will be saved the 
+*                     received data buffer.
+* Output         : None.
+* Return         : Number of received data (in Bytes).
+*******************************************************************************/
+uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer)
+{
+  uint32_t DataLength = 0;
+
+  /* Get the number of received data on the selected Endpoint */
+  DataLength = GetEPRxCount(bEpAddr & 0x7F);
+  
+  /* Use the memory interface function to write to the selected endpoint */
+  PMAToUserBufferCopy(pBufferPointer, GetEPRxAddr(bEpAddr & 0x7F), DataLength);
+
+  /* Return the number of received data */
+  return DataLength;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/MCD-ST Liberty SW License Agreement V2.pdf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/MCD-ST Liberty SW License Agreement V2.pdf
new file mode 100644
index 0000000..d61f430
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/MCD-ST Liberty SW License Agreement V2.pdf
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewd
new file mode 100644
index 0000000..5079872
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewd
@@ -0,0 +1,4627 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewp
new file mode 100644
index 0000000..bdc2d27
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.ewp
@@ -0,0 +1,3956 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
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+      <name>ARM</name>
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+          <state>STM3210E-EVAL\Obj</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+  </configuration>
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+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
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+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>ExePath</name>
+          <state>STM3210B-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210B-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210B-EVAL\List</state>
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+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
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+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
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+          <name>Input description</name>
+          <state>Full formatting.</state>
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+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
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+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
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+          <name>GOutputBinary</name>
+          <state>0</state>
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+          <name>FPU</name>
+          <version>2</version>
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+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+          <version>0</version>
+          <state>2</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>4.41A</state>
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+          <name>OGLastSavedByProductVersion</name>
+          <state>6.30.1.53141</state>
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+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F10xxB	ST STM32F10xxB</state>
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+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+          <state>1</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
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+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
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+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
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+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F10X_MD</state>
+          <state>USE_STM3210B_EVAL</state>
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+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
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+          <name>CCDebugInfo</name>
+          <state>1</state>
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+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
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+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
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+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
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+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
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+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+        <option>
+          <name>PreInclude</name>
+          <state></state>
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+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <name>IProcessorMode2</name>
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+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
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+        <option>
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+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+        <option>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>CCPosIndRwpi</name>
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+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
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+        <option>
+          <name>IccLang</name>
+          <state>0</state>
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+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
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+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
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+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
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+          <name>IccExceptions</name>
+          <state>1</state>
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+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
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+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
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+          <name>IccCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+      <archiveVersion>2</archiveVersion>
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+          <state>1</state>
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+          <name>AWarnOne</name>
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+          <state></state>
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+          <state>80</state>
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+          <state>STM3210B-EVAL_AudioSpeaker.bin</state>
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+          <name>IlinkOutputFile</name>
+          <state>AudioSpeaker.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
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+          <name>DoFill</name>
+          <state>0</state>
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+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
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+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
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+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
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+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>ExePath</name>
+          <state>STM3210E-EVAL_XL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL_XL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL_XL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
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+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
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+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
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+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
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+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
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+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
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+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
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+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.30.1.53141</state>
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+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F10xxG	ST STM32F10xxG</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
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+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>GeneralMisraVer</name>
+          <state>0</state>
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+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F10X_XL</state>
+          <state>USE_STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
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+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
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+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
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+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
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+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
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+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
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+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <version>0</version>
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+          <name>CCPosIndRwpi</name>
+          <state>0</state>
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+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
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+        <option>
+          <name>IccLang</name>
+          <state>0</state>
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+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
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+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
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+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
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+          <name>IccExceptions</name>
+          <state>1</state>
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+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
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+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
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+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
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+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
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+          <state>1</state>
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+        <option>
+          <name>AEndian</name>
+          <state>1</state>
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+          <name>ACaseSensitivity</name>
+          <state>1</state>
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+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
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+          <name>AWarnEnable</name>
+          <state>0</state>
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+          <name>AWarnWhat</name>
+          <state>0</state>
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+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
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+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
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+        <option>
+          <name>ADebug</name>
+          <state>1</state>
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+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
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+        <option>
+          <name>ADefines</name>
+          <state></state>
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+        <option>
+          <name>AList</name>
+          <state>0</state>
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+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
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+          <name>AListing</name>
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+          <name>MacDefs</name>
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+          <name>MacExps</name>
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+          <state>100</state>
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+          <state></state>
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+          <name>AExtraOptionsV2</name>
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+          <version>2</version>
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+          <state>1</state>
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+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM3210E-EVAL_XL_AudioSpeaker.bin</state>
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+          <state>1</state>
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+          <name>OOCObjCopyEnable</name>
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+      <archiveVersion>3</archiveVersion>
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+        <extensions></extensions>
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+      <archiveVersion>1</archiveVersion>
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+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
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+          <state>1</state>
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+        <option>
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+          <state>1</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
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+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <state>1</state>
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+          <name>IlinkCmsis</name>
+          <state>1</state>
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+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      <archiveVersion>0</archiveVersion>
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+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+          <name>OGChipSelectEditMenu</name>
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+      <configuration>STM3210E-EVAL_XL</configuration>
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+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dac.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_tim.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_endp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.eww
new file mode 100644
index 0000000..bff01d7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/AudioSpeaker.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\AudioSpeaker.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-AudioSpeaker</name>
+      <member>
+        <project>AudioSpeaker</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>AudioSpeaker</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>AudioSpeaker</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>AudioSpeaker</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>AudioSpeaker</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..efbc10a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/MDK-ARM/AudioSpeaker.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/MDK-ARM/AudioSpeaker.uvproj
new file mode 100644
index 0000000..063f796
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/MDK-ARM/AudioSpeaker.uvproj
@@ -0,0 +1,4415 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>STM3210B-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>4223</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM3210B-EVAL\</OutputDirectory>
+          <OutputName>STM3210B-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210B-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
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+              <IncludeLibraryModules></IncludeLibraryModules>
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+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
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+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
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+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
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+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L152VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000)</FlashDriverDll>
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+          <RegisterFile>stm32l1xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\ST\STM32L15x\STM32L15x.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
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+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
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+          <OutputName>STM32L152-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
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+          <CreateHexFile>0</CreateHexFile>
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+            <UserProg2Name></UserProg2Name>
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+          <SimDllArguments></SimDllArguments>
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+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
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+            <PeripheralDll></PeripheralDll>
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+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
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+        <Utilities>
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+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
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+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
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+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_MD, USE_STM32L152_EVAL</Define>
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+          <GroupName>User</GroupName>
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+              <FileType>1</FileType>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rapp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rapp
new file mode 100644
index 0000000..dc3a59e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rapp
@@ -0,0 +1,826 @@
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+			</Set>
+			<Set Header="LD" >
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																																								
+				</Section>
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+																																			
+		</Config>
+		
+	</Options>
+</ApplicationBuild>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rprj
new file mode 100644
index 0000000..9477f43
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/RIDE/AudioSpeaker.rprj
@@ -0,0 +1,17 @@
+
+<Project Header="Project 'AudioSpeaker'" Path=".\AudioSpeaker.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="AudioSpeaker" >
+	<ApplicationBuild Header="AudioSpeaker" Extern=".\AudioSpeaker.rapp" Path=".\AudioSpeaker.rapp" OutputFile=".\STM32L152-EVAL\AudioSpeaker.elf" Config="STM32L152-EVAL" sate="98" />
+	<Options>
+		<Config Header="Standard" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																											
+				</Section>
+																																	
+			</Set>
+																				
+		</Config>
+												
+	</Options>
+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..68c7412
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.cproject
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1054603186" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file (.lsl):" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_md.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..fc75ce1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..547d59a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
new file mode 100644
index 0000000..1233f43
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 512k;
+    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                         /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMAChannel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMAChannel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMAChannel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMAChannel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMAChannel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMAChannel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMAChannel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..a2b8070
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/i2s_codec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/i2s_codec.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
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+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
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+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..cb9c7d9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.cproject
@@ -0,0 +1,137 @@
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..d66bfae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+	<linkedResources>
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+			<name>CMSIS</name>
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+		</link>
+		<link>
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+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
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+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
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+		</link>
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+		</link>
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+		</link>
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+		</link>
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+		</link>
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+		</link>
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+			<type>1</type>
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+		</link>
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+		</link>
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+		</link>
+		<link>
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+		</link>
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+		</link>
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+		</link>
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+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
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+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
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+		</link>
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+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
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+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
new file mode 100644
index 0000000..d494039
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
@@ -0,0 +1,44 @@
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+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
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+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
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+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
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+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
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+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..ad296ee
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
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+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
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+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210B-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..65e9603
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
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+					<key>?name?</key>
+					<value></value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/readme.txt</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
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+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/i2s_codec.c</name>
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+		</link>
+		<link>
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+			<type>1</type>
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+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/stm32_it.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_desc.c</locationURI>
+		</link>
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+			<type>1</type>
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+		</link>
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+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..e058ee6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:53:23 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
new file mode 100644
index 0000000..bd4ac0c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Audio_Speaker\TrueSTUDIO\STM3210B-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210B-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..e0aa35c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/.project
new file mode 100644
index 0000000..e6f3506
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/.project
@@ -0,0 +1,235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/i2s_codec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/i2s_codec.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
new file mode 100644
index 0000000..4494ab7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Audio_Speaker\TrueSTUDIO\STM3210E-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210E-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..0fbff9c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/i2s_codec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/i2s_codec.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..d551f74
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:54:24 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32f10x_flash_ROArray.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
index 357cd39..b1c6965 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/Linker/TrueSTUDIO/stm32f10x_flash_ROArray.ld
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -1,10 +1,10 @@
 /*
 *****************************************************************************
 **
-**  File        : stm32f10x_flash_ROArray.ld
+**  File        : stm32_flash.ld
 **
-**  Abstract    : Linker script for stm32f10x_xl Device with
-**                1024KByte FLASH, 96KByte RAM
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -37,15 +37,14 @@ _estack = 0x20018000;    /* end of 96K RAM */
 
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x80;  /* required amount of stack */
+_Min_Stack_Size = 0x800; /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
 {
-  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
   RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
   MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
-  MEMORY_ARRAY (rw)  : ORIGIN = 0x20002000, LENGTH = 32
 }
 
 /* Define output sections */
@@ -69,7 +68,6 @@ SECTIONS
     *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
     *(.glue_7)         /* glue arm to thumb code */
     *(.glue_7t)        /* glue thumb to arm code */
-	*(.eh_frame)
 
     KEEP (*(.init))
     KEEP (*(.fini))
@@ -86,6 +84,8 @@ SECTIONS
       __exidx_end = .;
     } >FLASH
 
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
   .preinit_array     :
   {
     PROVIDE_HIDDEN (__preinit_array_start = .);
@@ -167,8 +167,4 @@ SECTIONS
     libm.a ( * )
     libgcc.a ( * )
   }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-  
-  .ROarraySection : {*(.ROarraySection)} >MEMORY_ARRAY
 }
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..0e3555e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32l1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_stm32l1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/i2s_codec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/i2s_codec.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Audio_Speaker/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..37e4638
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:55:31 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..51982c5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Audio_Speaker\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32_flash.ld
new file mode 100644
index 0000000..1be62d5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/TrueSTUDIO/STM32L152-EVAL/STM32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_md Device with
+**                128KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/i2s_codec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/i2s_codec.h
new file mode 100644
index 0000000..c392004
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/i2s_codec.h
@@ -0,0 +1,193 @@
+/**
+  ******************************************************************************
+  * @file    i2s_codec.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains all the functions prototypes for the I2S codec
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __I2S_CODEC_H
+#define __I2S_CODEC_H
+
+/* .WAV file format :
+
+ Endian      Offset      Length      Contents
+  big         0           4 bytes     'RIFF'             // 0x52494646
+  little      4           4 bytes     <file length - 8>
+  big         8           4 bytes     'WAVE'             // 0x57415645
+
+Next, the fmt chunk describes the sample format:
+
+  big         12          4 bytes     'fmt '          // 0x666D7420
+  little      16          4 bytes     0x00000010      // Length of the fmt data (16 bytes)
+  little      20          2 bytes     0x0001          // Format tag: 1 = PCM
+  little      22          2 bytes     <channels>      // Channels: 1 = mono, 2 = stereo
+  little      24          4 bytes     <sample rate>   // Samples per second: e.g., 22050
+  little      28          4 bytes     <bytes/second>  // sample rate * block align
+  little      32          2 bytes     <block align>   // channels * bits/sample / 8
+  little      34          2 bytes     <bits/sample>   // 8 or 16
+
+Finally, the data chunk contains the sample data:
+
+  big         36          4 bytes     'data'        // 0x64617461
+  little      40          4 bytes     <length of the data block>
+  little      44          *           <sample data>
+
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Audio file information structure */
+typedef struct
+{
+  uint32_t  RIFFchunksize;
+  uint16_t  FormatTag;
+  uint16_t  NumChannels;
+  uint32_t  SampleRate;
+  uint32_t  ByteRate;
+  uint16_t  BlockAlign;
+  uint16_t  BitsPerSample;
+  uint32_t  DataSize;
+} WAVE_FormatTypeDef;
+
+/* Error Identification structure */
+typedef enum
+{
+  Valid_WAVE_File = 0,
+  Unvalid_RIFF_ID,
+  Unvalid_WAVE_Format,
+  Unvalid_FormatChunk_ID,
+  Unsupporetd_FormatTag,
+  Unsupporetd_Number_Of_Channel,
+  Unsupporetd_Sample_Rate,
+  Unsupporetd_Bits_Per_Sample,
+  Unvalid_DataChunk_ID,
+  Unsupporetd_ExtraFormatBytes,
+  Unvalid_FactChunk_ID
+} ErrorCode;
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/* Codec output DEVICE */
+#define OutputDevice_SPEAKER          1
+#define OutputDevice_HEADPHONE        2  
+#define OutputDevice_BOTH             3
+
+/* VOLUME control constants */
+#define DEFAULT_VOL                   0x52
+#define VolumeDirection_HIGH          0xF
+#define VolumeDirection_LOW           0xA
+#define VolumeDirection_LEVEL         0x0
+#define VOLStep                       4 
+
+/* Forward and Rewind constants */
+#define STEP_FORWARD                  2 /* 2% of wave file data length*/
+#define STEP_BACK                     6 /* 6% of wave file data length*/
+
+/* Codec POWER DOWN modes */
+#define CodecPowerDown_HW             1
+#define CodecPowerDown_SW 	          2
+
+/* Audio Play STATUS */
+#define AudioPlayStatus_STOPPED       0
+#define AudioPlayStatus_PLAYING	      1
+#define AudioPlayStatus_PAUSED		    2	 
+
+/* MUTE commands */ 
+#define MUTE_ON                       1
+#define MUTE_OFF							        0
+
+/* I2S configuration parameters */
+#define I2S_STANDARD                  I2S_Standard_Phillips
+#define I2S_MCLKOUTPUT                I2S_MCLKOutput_Enable
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+ 
+  /* CONFIGURATION */
+uint32_t I2S_CODEC_Init(uint32_t OutputDevice, uint32_t Address);
+void I2S_CODEC_ReplayConfig(uint32_t Repetions);
+
+	/* AUDIO CONTROL */
+uint32_t I2S_CODEC_Play(uint32_t AudioStartPosition);
+uint32_t I2S_CODEC_Pause(void);
+uint32_t I2S_CODEC_Stop(void);	
+uint32_t I2S_CODEC_ControlVolume(uint32_t direction, uint8_t volume);
+void I2S_CODEC_Mute(uint32_t Command);
+void I2S_CODEC_ForwardPlay(uint32_t Step);
+void I2S_CODEC_RewindPlay(uint32_t Step);
+
+   /* EXTRA CONTROLS */								 
+void I2S_CODEC_PowerDown(uint32_t CodecPowerDown_Mode);
+void I2S_CODEC_Reset(void);
+uint32_t I2S_CODEC_SpeakerHeadphoneSwap(uint32_t CODEC_AudioOutput, uint32_t Address);
+uint8_t GetVar_CurrentVolume(void);
+
+/* Medium Layer Codec Functions ----------------------------------------------*/						
+void I2S_CODEC_DataTransfer(void);
+void I2S_CODEC_UpdateStatus(void);
+uint32_t GetVar_DataStartAddr(void);	
+ErrorCode I2S_CODEC_WaveParsing(uint8_t* HeaderTab);
+uint32_t GetVar_CurrentOutputDevice(void);
+
+uint32_t GetVar_AudioDataIndex(void);
+void SetVar_AudioDataIndex(uint32_t value);
+void ResetVar_AudioDataIndex(void);
+void IncrementVar_AudioDataIndex(uint32_t IncrementNumber);
+void DecrementVar_AudioDataIndex(uint32_t DecrementNumber);
+
+uint32_t GetVar_AudioReplay(void);
+void Decrement_AudioReplay(void);
+
+uint32_t GetVar_AudioPlayStatus(void);
+uint32_t SetVar_AudioPlayStatus(uint32_t Status);
+
+uint16_t GetVar_i2saudiofreq(void);
+uint32_t GetVar_AudioDataLength(void);
+
+/* Low Layer Codec Function --------------------------------------------------*/
+uint32_t SetVar_SendDummyData(void);
+uint32_t ResetVar_SendDummyData(void);
+uint32_t GetVar_SendDummyData(void);
+uint32_t AudioFile_Init(void);
+
+void I2S_GPIO_Config(void); 
+void I2S_Config(uint16_t Standard, uint16_t MCLKOutput, uint16_t AudioFreq);
+uint32_t CODEC_Config(uint16_t AudioOutput, uint16_t I2S_Standard, uint16_t I2S_MCLKOutput, uint8_t Volume);
+
+uint32_t Media_Init(void);
+void Media_BufferRead(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead);
+void Media_StartReadSequence(uint32_t ReadAddr);
+uint16_t Media_ReadHalfWord(uint32_t Offset);
+uint8_t Media_ReadByte(uint32_t Offset);
+
+void delay(__IO uint32_t nCount); 
+
+#endif /* __I2S_CODEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/platform_config.h
new file mode 100644
index 0000000..440c531
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/platform_config.h
@@ -0,0 +1,129 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+#if defined(STM32L1XX_MD)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "i2s_codec.h"
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+#define USE_STM32L152_EVAL
+
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+
+  #define USB_DISCONNECT                    GPIOD  
+  #define USB_DISCONNECT_PIN                GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT    RCC_APB2Periph_GPIOD
+
+#elif defined(USE_STM3210E_EVAL)
+
+  #define USB_DISCONNECT                    GPIOB  
+  #define USB_DISCONNECT_PIN                GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT    RCC_APB2Periph_GPIOB
+
+#elif defined (USE_STM32L152_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+#endif /* USE_STM3210B_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/stm32_it.h
new file mode 100644
index 0000000..6bc6037
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/stm32_it.h
@@ -0,0 +1,63 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_HP_CAN1_TX_IRQHandler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+void USBWakeUp_IRQHandler(void);
+void USB_FS_WKUP_IRQHandler(void);
+#ifdef USE_STM3210B_EVAL
+void TIM2_IRQHandler(void);
+#endif /* USE_STM3210B_EVAL */
+#if defined (USE_STM3210E_EVAL)
+void SPI2_IRQHandler(void);
+#endif /* USE_STM3210E_EVAL */
+					 
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/stm32f10x_conf.h
index 7277913..e08299d 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Write_Protection/stm32f10x_conf.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/stm32f10x_conf.h
@@ -1,34 +1,40 @@
 /**
   ******************************************************************************
-  * @file    FLASH/Write_Protection/stm32f10x_conf.h 
+  * @file    stm32f10x_conf.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
+  * @version V4.0.0
+  * @date    21-January-2013
   * @brief   Library configuration file.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
+
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F10x_CONF_H
 #define __STM32F10x_CONF_H
 
 /* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+/* Uncomment the line below to enable peripheral header file inclusion */
 #include "stm32f10x_adc.h"
 #include "stm32f10x_bkp.h"
 #include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
 #include "stm32f10x_crc.h"
 #include "stm32f10x_dac.h"
 #include "stm32f10x_dbgmcu.h"
@@ -37,7 +43,7 @@
 #include "stm32f10x_flash.h"
 #include "stm32f10x_fsmc.h"
 #include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
+#include "stm32f10x_i2c.h" 
 #include "stm32f10x_iwdg.h"
 #include "stm32f10x_pwr.h"
 #include "stm32f10x_rcc.h"
@@ -47,8 +53,7 @@
 #include "stm32f10x_tim.h"
 #include "stm32f10x_usart.h"
 #include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -59,13 +64,15 @@
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
   #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
@@ -75,4 +82,4 @@
 
 #endif /* __STM32F10x_CONF_H */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_istr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_istr.h
new file mode 100644
index 0000000..de6ca1c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_istr.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the peripherals header files in the user application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void USB_Istr(void);
+/* function prototypes Automatically built defining related macros */
+
+#ifdef CTR_CALLBACK
+  void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+  void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+  void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+  void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+  void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+  void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+  void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+  void ESOF_Callback(void);
+#endif
+
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+#endif /*__USB_ISTR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_pwr.h
new file mode 100644
index 0000000..af7873e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/inc/usb_pwr.h
@@ -0,0 +1,72 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+
+/* External variables --------------------------------------------------------*/
+extern __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/readme.txt
new file mode 100644
index 0000000..044f814
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/readme.txt
@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB Audio_Speaker Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+The USB-FS-Device Audio Speaker demo gives examples of how to use the STM32F10xxx 
+and STM32L15xxx USB-FS-Device peripheral to communicate with the PC host in the 
+isochronous transfer mode.
+It provides a demonstration of the correct method for configuring an isochronous
+endpoint, receiving or transmitting data from/to the host.
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain 
+ + \TASKING: contains preconfigured projects for TASKING toolchain
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain           
+ + \src: contains the Demo firmware source files
+
+Hardware environment
+====================
+This example runs on STMicroelectronics STM3210B-EVAL, STM3210E-EVAL and 
+STM32L152-EVAL evaluation boards and can be easily tailored to any other hardware.
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+    
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+     - Jumper JP6 should be not connected.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+     - Jumper JP18 (MCKI) should be connected in position 2-3.
+  
+  - STM32L152-EVAL Set-up 
+     - Jumper JP16 (Audio Out) should be not connected.
+
+
+How to use it
+=============
+ + EWARM
+    - Open the AudioSpeaker.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the AudioSpeaker.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)  
+
+ + RIDE
+    - Open the AudioSpeaker.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+        - under STM32F10B_EVAL directory: to select the project for STM32 Medium-density devices.
+        - under STM32F10E_EVAL directory: to select the project for STM32 High-density devices
+        - under STM32F10E_EVAL_XL directory: to select the project for STM32 XL-density devices
+        - under STM32L152_EVAL directory: to select the project for STM32 Medium-Density Low-Power devices
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->'build project' menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+NOTE:
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
+   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+   the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+ - Medium-density Low-Power devices are STM32L15xx microcontrollers where the flash
+   memory density ranges between 64 and 128 Kbytes.
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/hw_config.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/hw_config.c
new file mode 100644
index 0000000..74eb8ed
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/hw_config.c
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "usb_prop.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TIM2ARRValue    3273 /* 22KHz = 72MHz / 3273 */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ErrorStatus HSEStartUpStatus;
+EXTI_InitTypeDef EXTI_InitStructure;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Set_System
+* Description    : Configures Main system clocks & power
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_System(void)
+{
+#if !defined(STM32L1XX_MD) 
+  GPIO_InitTypeDef GPIO_InitStructure;
+#endif /* STM32L1XX_MD */  
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /* USB_USE_EXTERNAL_PULLUP */ 
+ 
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32xxx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32xxx.c file
+     */ 
+  
+#ifdef STM32L1XX_MD 
+  /* Enable the SYSCFG module clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+#endif /* STM32L1XX_MD */   
+
+#ifdef USE_STM3210B_EVAL
+  /* Enable GPIOB, TIM2 & TIM4 clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE);
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM4 , ENABLE);
+#endif /* USE_STM3210B_EVAL */
+
+#if !defined(STM32L1XX_MD)
+  /* Configure USB pull-up */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE);
+
+  /* Configure USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32L1XX_MD */
+
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);  
+#endif /* USB_USE_EXTERNAL_PULLUP */
+  
+  USB_Cable_Config(DISABLE);
+
+  USB_Cable_Config(ENABLE);
+
+  /* Configure the EXTI line 18 connected internally to the USB IP */
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : Set_USBClock
+* Description    : Configures USB Clock input (48MHz)
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_USBClock(void)
+{
+#ifdef STM32L1XX_MD
+  /* Enable USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+
+#else
+  /* Select USBCLK source */
+  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
+  
+  /* Enable the USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+#endif /* STM32L1XX_MD */  
+}
+
+/*******************************************************************************
+* Function Name  : Enter_LowPowerMode
+* Description    : Power-off system clocks and power while entering suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Enter_LowPowerMode(void)
+{
+  /* Set the device state to suspend */
+  bDeviceState = SUSPENDED;
+}
+
+/*******************************************************************************
+* Function Name  : Leave_LowPowerMode
+* Description    : Restores system clocks and power while exiting suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Leave_LowPowerMode(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  /* Set the device state to the correct state */
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+  else
+  {
+    bDeviceState = ATTACHED;
+  }
+  /*Enable SystemCoreClock*/
+  SystemInit();
+}
+
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config
+* Description    : Configures the USB interrupts
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+
+#ifdef STM32L1XX_MD
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable and configure the priority of the USB_HP IRQ Channel*/
+  NVIC_InitStructure.NVIC_IRQChannel = USB_HP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+  NVIC_Init(&NVIC_InitStructure); 
+
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+#else /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+  
+  /* Enable and configure the priority of the USB_LP IRQ Channel*/
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable and configure the priority of the USB_HP IRQ Channel*/
+  NVIC_InitStructure.NVIC_IRQChannel = USB_HP_CAN1_TX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure); 
+
+#endif /* STM32L1XX_MD */
+  
+  /* Audio Components Interrupt configuration */
+  Audio_Config();
+}
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config
+* Description    : Configures the USB interrupts
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Audio_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+  
+#if defined(USE_STM32L152_EVAL)
+  /* Enable the TIM2 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM6_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#elif defined(USE_STM3210B_EVAL)
+  /* Enable the TIM2 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#elif defined(USE_STM3210E_EVAL)
+  /* SPI2 IRQ Channel configuration */
+  NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+#endif /* USE_STM3210B_EVAL */
+}
+/*******************************************************************************
+* Function Name  : USB_Cable_Config
+* Description    : Software Connection/Disconnection of USB Cable
+* Input          : None.
+* Return         : Status
+*******************************************************************************/
+void USB_Cable_Config (FunctionalState NewState)
+{
+#ifdef STM32L1XX_MD
+  if (NewState != DISABLE)
+  {
+    STM32L15_USB_CONNECT;
+  }
+  else
+  {
+    STM32L15_USB_DISCONNECT;
+  }  
+
+#else  
+  if (NewState != DISABLE)
+  {
+    GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+  else
+  {
+    GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+#endif /* STM32L1XX_MD */  
+}
+
+/*******************************************************************************
+* Function Name  : Speaker_Timer_Config
+* Description    : Configure and enable the timer
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Speaker_Config(void)
+{
+#ifdef USE_STM32L152_EVAL  
+  DAC_InitTypeDef     DAC_InitStructure;
+  GPIO_InitTypeDef    GPIO_InitStructure;
+  uint16_t TIM6ARRValue = 4000;
+
+  /* TIM6 and DAC clocks enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC, ENABLE);
+
+  /* Enable GPIOA clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);  
+  
+  /* Configure DAC Channel1 and Channel2 as output */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; 
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* TIM6 Configuration */
+  TIM_DeInit(TIM6);
+
+  TIM6ARRValue = (uint32_t)(SystemCoreClock/22000); /* Audio Sample Rate = 22KHz */
+
+  /* Set the timer auto reload value dependent on the audio frequency */  
+  TIM_SetAutoreload(TIM6, TIM6ARRValue); /* 22.KHz = 32MHz / 1454 */  
+
+  /* TIM6 TRGO selection */
+  TIM_SelectOutputTrigger(TIM6, TIM_TRGOSource_Update);
+
+  /* Enable TIM6 update interrupt */
+  TIM_ITConfig(TIM6, TIM_IT_Update, ENABLE);
+
+  /* DAC deinitialize */
+  DAC_DeInit();
+  DAC_StructInit(&DAC_InitStructure);
+
+  /* Fill DAC InitStructure */
+  DAC_InitStructure.DAC_Trigger = DAC_Trigger_T6_TRGO;
+  DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None;
+  DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Disable;
+
+/* DAC Channel1: 8bit right---------------------------------------------------*/
+  /* DAC Channel1 Init */
+  DAC_Init(DAC_Channel_1, &DAC_InitStructure);
+
+  /* Enable DAC Channel1 */
+  DAC_Cmd(DAC_Channel_1, ENABLE);
+
+  /* Start TIM6 */
+  TIM_Cmd(TIM6, ENABLE);  
+  
+#elif defined(USE_STM3210B_EVAL)
+  GPIO_InitTypeDef GPIO_InitStructure;
+  TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+  TIM_OCInitTypeDef TIM_OCInitStructure;
+
+  /* Configure PB.08 as alternate function (TIM4_OC3) */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  /* TIM4 configuration */
+  TIM_TimeBaseStructure.TIM_Prescaler = 0x00; /* TIM4CLK = 72 MHz */
+  TIM_TimeBaseStructure.TIM_Period = 0xFF;   /* PWM frequency : 281.250KHz*/
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+  /* TIM4's Channel3 in PWM1 mode */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+  TIM_OCInitStructure.TIM_Pulse = 0x7F;  /* Duty cycle: 50%*/
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;  /* set high polarity */
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OC3Init(TIM4, &TIM_OCInitStructure);
+  TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);
+
+  /* TIM2 configuration */
+  TIM_TimeBaseStructure.TIM_Period = TIM2ARRValue;
+  TIM_TimeBaseStructure.TIM_Prescaler = 0x00;    /* TIM2CLK = 72 MHz */
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+  /* Output Compare Inactive Mode configuration: Channel1 */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStructure.TIM_Pulse = 0x0;
+  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
+  TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
+
+  /* Start TIM4 */
+  TIM_Cmd(TIM4, ENABLE);
+
+  /* Start TIM2 */
+  TIM_Cmd(TIM2, ENABLE);
+
+  /* Enable TIM2 update interrupt */
+  TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
+
+#else 
+  /* Configure the initialization parameters */
+  I2S_GPIO_Config();
+  I2S_Config(I2S_Standard_Phillips, I2S_MCLKOutput_Enable, I2S_AudioFreq_22k);
+  CODEC_Config(OutputDevice_SPEAKER, I2S_Standard_Phillips, I2S_MCLKOutput_Enable, 0x08);
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+
+#endif
+}
+
+/*******************************************************************************
+* Function Name  : Get_SerialNum.
+* Description    : Create the serial number string descriptor.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Get_SerialNum(void)
+{
+  uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+  
+  Device_Serial0 = *(uint32_t*)ID1;
+  Device_Serial1 = *(uint32_t*)ID2;
+  Device_Serial2 = *(uint32_t*)ID3;
+  
+  Device_Serial0 += Device_Serial2;
+
+  if (Device_Serial0 != 0)
+  {
+    IntToUnicode (Device_Serial0, &Speaker_StringSerial[2] , 8);
+    IntToUnicode (Device_Serial1, &Speaker_StringSerial[18], 4);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : HexToChar.
+* Description    : Convert Hex 32Bits value into char.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
+{
+  uint8_t idx = 0;
+  
+  for( idx = 0 ; idx < len ; idx ++)
+  {
+    if( ((value >> 28)) < 0xA )
+    {
+      pbuf[ 2* idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2* idx] = (value >> 28) + 'A' - 10; 
+    }
+    
+    value = value << 4;
+    
+    pbuf[ 2* idx + 1] = 0;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/i2s_codec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/i2s_codec.c
new file mode 100644
index 0000000..6dd4168
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/i2s_codec.c
@@ -0,0 +1,1573 @@
+/**
+  ******************************************************************************
+  * @file    i2s_codec.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the I2S Codec driver for AK4343 Audio Codec.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+#include "platform_config.h"
+#ifdef USE_STM3210E_EVAL
+/* Includes ------------------------------------------------------------------*/
+
+#include "i2s_codec.h"
+
+/* Private typedef -----------------------------------------------------------*/
+typedef enum
+{
+  LittleEndian,
+  BigEndian
+}Endianness;
+
+/* Private define ------------------------------------------------------------*/
+
+/* Audio file header size */
+#define HEADER_SIZE          100
+
+/* EvalBoard pins related to the Codec */
+#define Codec_PDN_GPIO      GPIOG
+#define Codec_PDN_Pin        GPIO_Pin_11
+
+/* Uncomment this line to enable verifying data sent to codec after each write operation */
+//#define VERIFY_WRITTENDATA
+
+/* The 7 bits Codec address mask */
+#define CODEC_ADDRESS         0x27  /* b00100111 */
+
+/* Audio Parsing Constants */
+#define  ChunkID             0x52494646  /* correspond to the letters 'RIFF' */
+#define  FileFormat          0x57415645  /* correspond to the letters 'WAVE' */
+#define  FormatID            0x666D7420  /* correspond to the letters 'fmt ' */
+#define  DataID              0x64617461  /* correspond to the letters 'data' */
+#define  FactID              0x66616374  /* correspond to the letters 'fact' */
+
+#define  WAVE_FORMAT_PCM     0x01
+#define  FormatChunkSize     0x10
+#define  Channel_MONO        0x01
+#define  Channel_STEREO      0x02
+
+#define  SampleRate_8000     8000
+#define  SampleRate_16000    16000
+#define  SampleRate_22050    22050
+#define  SampleRate_44100    44100
+#define  SampleRate_48000    48000
+#define  Bits_Per_Sample_8   8
+#define  Bits_Per_Sample_16  16
+
+#define DUMMY_DATA           0x1111
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Audio Frequency value */
+uint16_t i2saudiofreq = I2S_AudioFreq_8k;
+
+/* Header Table containing the audio file information */
+uint8_t HeaderTabIndex = 0;
+uint8_t AudioFileHeader[HEADER_SIZE];
+
+/* Audio Codec variables */
+__IO uint32_t AudioFileAddress = 0x0;
+uint32_t AudioDataLength = 0;//7000000;
+uint32_t DataStartAddr = 0x0;
+__IO uint32_t AudioDataIndex = 0;
+static __IO uint32_t AudioReplay = 0xFFFF;
+static uint32_t AudioReplayCount = 0xFFFF;
+static __IO uint32_t SendDummyData = 0;
+static __IO uint32_t AudioPlayStatus = AudioPlayStatus_STOPPED;
+static uint32_t CurrentOutputDevice = OutputDevice_HEADPHONE;
+static uint8_t CurrentVolume = DEFAULT_VOL;
+static uint32_t errorcode = 0xFF;
+static __IO uint32_t monovar = 0, tmpvar = 0;
+
+/* Wave details names table */
+WAVE_FormatTypeDef  WAVE_Format;
+__IO ErrorCode  WaveFileStatus = Unvalid_RIFF_ID;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static void NVIC_Config(void);
+static void I2C_Config(void);
+static uint32_t CODEC_WriteRegister(uint32_t RegisterAddr, uint32_t RegisterValue);
+static uint32_t CODEC_ReadRegister(uint32_t RegisterAddr);
+static uint32_t ReadUnit(uint8_t NbrOfBytes, Endianness BytesFormat);
+uint32_t AudioFile_Init(void);
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Init
+* Description    : Initializes the I2S audio codec according parameters configured
+*                    by I2S_CODEC_Config function.
+* Input          : - OutputDevice: Could be OutoutDevice_SPEAKER or
+*                      OutoutDevice_HEADPHONE.
+*                  - Address: Specifies the location of the audio file in the memory.
+* Output         : None
+* Return         : - 0: if all initializations are OK.
+*                  - 1: if memory initialization failed (LD2 is turned on).
+*                  - 2: if audio file initialization failed (LD2 is turned on).
+*                  - 3: if Codec initialization failed (LD1 is turned on).
+*******************************************************************************/
+uint32_t I2S_CODEC_Init(uint32_t OutputDevice, uint32_t Address)
+{
+  uint32_t count = 0;
+
+  /* Set the audio file address */
+  AudioFileAddress = (uint32_t) Address;
+
+  /* Configure I2S interrupt Channel */
+  NVIC_Config();
+
+  /* Configure the I2S2, I2C1 and GPIOF pins */
+  I2S_GPIO_Config();
+
+  /* Read the Audio file to extract the audio data length and frequency */
+  errorcode = AudioFile_Init();
+
+  if (errorcode < 3)
+  {
+    /* Turn on LD2 connected to PF.07 */
+    GPIO_SetBits(GPIOF, GPIO_Pin_7);
+
+    return errorcode;
+  }
+
+  /* Configure the SPI2 peripheral in I2S mode */
+  I2S_Config(I2S_STANDARD, I2S_MCLKOUTPUT, i2saudiofreq);
+
+  /* Set the current output device */
+  CurrentOutputDevice = OutputDevice;
+
+  /* Codec Configuration via I2C interface */
+  count = CODEC_Config(OutputDevice, I2S_STANDARD, I2S_MCLKOUTPUT, DEFAULT_VOL);
+
+  if (count != 0)
+  {
+    /* Turn on LD1 connected to PF.06 */
+    GPIO_SetBits(GPIOF, GPIO_Pin_6);
+
+    return 3;
+  }
+
+  /* Turn on LD4 connected to PF.09 */
+  GPIO_SetBits(GPIOF, GPIO_Pin_9);
+
+  return 0; /* Configuration is OK */
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_ReplayConfig
+* Description    : Set AudioReplay variable value .
+* Input          : Repetions: Number of repetitions
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2S_CODEC_ReplayConfig(uint32_t Repetions)
+{
+  /* Audio Replay number set by user */
+  AudioReplay = Repetions;
+
+  /* Audio Replays number remaining (if AudioReplay != 0) */
+  AudioReplayCount = Repetions;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Play
+* Description    : Plays the audio file.
+* Input          : - AudioStartPosition: Address from which the wave data begin
+* Output         : None
+* Return         : AudioDataIndex value.
+*******************************************************************************/
+uint32_t I2S_CODEC_Play(uint32_t AudioStartPosition)
+{
+  /* Send the read command to the media */
+  Media_StartReadSequence(AudioFileAddress + AudioStartPosition + 1);
+
+  /* Set Playing status to inform other modules about the codec status */
+  SetVar_AudioPlayStatus(AudioPlayStatus_PLAYING);
+
+  /* Enable the I2S2 TXE Interrupt  => Generate the clocks*/
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+
+  return AudioDataIndex;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Pause
+* Description    : Pause playing the audio file.
+* Input          : None
+* Output         : None
+* Return         : Current Position.
+*******************************************************************************/
+uint32_t I2S_CODEC_Pause()
+{
+  /* Disable the I2S2 TXE Interrupt  => stop the clocks*/
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+  /* Set Paused status to inform other modules about the codec status */
+  SetVar_AudioPlayStatus(AudioPlayStatus_PAUSED);
+
+  /* Reset local variables */
+  monovar = 0;
+  tmpvar = 0;
+
+  if (WAVE_Format.NumChannels == Channel_MONO)
+  {
+    /* Force the parity of the address */
+    AudioDataIndex &= 0xFFFFFFFE;
+  }
+  /* Return the current data pointer position */
+  return AudioDataIndex;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Stop
+* Description    : Stop playing the audio file, reset the pointer and power off
+*                : the Codec.
+* Input          : None
+* Output         : None
+* Return         : 0 if operation complete.
+*******************************************************************************/
+uint32_t I2S_CODEC_Stop()
+{
+  /* Disable the I2S2 TXE Interrupt  => stop the clocks */
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+  /* Reinitialize the audio data pointer */
+  AudioDataIndex = 0;
+
+  /* Power off the Codec to save power and protect the Codec itself */
+  I2S_CODEC_PowerDown(CodecPowerDown_SW);
+
+  /* Set Paused status to inform other modules about the codec status */
+  SetVar_AudioPlayStatus(AudioPlayStatus_STOPPED);
+
+  /* Reset local variables */
+  monovar = 0;
+  tmpvar = 0;
+
+  return 0;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_ControlVolume
+* Description    : Controls the audio volume.
+* Input          :  - direction: VolumeDirection_HIGH (0xF) to increase the volume,
+*                :     VolumeDirection_LOW (0xA) to decrease  the volume or
+*                :     VolumeDirection_LEVEL (0x0) to set a defined level of volume.
+*                :  - Volume: the step of volume increasing/decreasing (when direction == 0)
+*                :     or the volume level to be set (when direction != 0).
+* Output         : None
+* Return         : 0-> correct communication, else wrong communication
+*******************************************************************************/
+uint32_t I2S_CODEC_ControlVolume(uint32_t direction, uint8_t Volume)
+{
+  uint32_t counter = 0;
+
+  if (direction == VolumeDirection_HIGH)
+  {
+    /* Check if the volume high limit is reached */
+    if (CurrentVolume < VOLStep)
+    {
+      CurrentVolume = 0;
+    }
+    else
+    {
+      /* Save the current volume level */
+      CurrentVolume = CODEC_ReadRegister(0x0A) - Volume;
+    }
+
+    /* Set the new volume */
+    counter += CODEC_WriteRegister(0x0A, CurrentVolume);
+  }
+  else if (direction == VolumeDirection_LOW)
+  {
+    /* Check if the volume low limit is reached */
+    if (CurrentVolume > (0xFF - VOLStep))
+    {
+      CurrentVolume = 0xFF;
+    }
+    else
+    {
+      /* Save the current volume level */
+      CurrentVolume = CODEC_ReadRegister(0x0A) + Volume;
+    }
+
+    /* Set the new volume */
+    counter += CODEC_WriteRegister(0x0A, CurrentVolume);
+  }
+  else if (direction == VolumeDirection_LEVEL)
+  {
+    CurrentVolume = Volume;
+
+    /* Set the new volume */
+    counter += CODEC_WriteRegister(0x0A, Volume);
+  }
+  else
+  {
+    return 0xFF; //Error verifying the Codec registers
+  }
+
+  return counter;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Mute
+* Description    : Enable or disable the MUTE mode by software
+* Input          : - Command: could be MUTEON to mute sound or MUTEOFF to restore volume
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_Mute(uint32_t Command)
+{
+  uint32_t tmp = 0;
+
+  /* Read the current value of the config register number 0x0E */
+  tmp = CODEC_ReadRegister(0x0E);
+
+  /* Set the Mute mode */
+  if (Command == MUTE_ON)
+  {
+    tmp |= 0x20;
+  }
+  else /* MUTE_OFF Disable the Mute */
+  {
+    tmp &= 0xD1;
+  }
+
+  /* Write back the CODEC config register w/the new value */
+  CODEC_WriteRegister(0x0E, tmp);
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_ForwardPlay
+* Description    : Forward function.
+* Input          : - Step: number of steps forward
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_ForwardPlay(uint32_t Step)
+{
+  /* Pause Playing the audio file */
+  I2S_CODEC_Pause();
+
+  /* Increment the Audio pointer */
+  IncrementVar_AudioDataIndex((AudioDataLength / 100) * Step);
+
+  /* Insure the index parity */
+  AudioDataIndex &= 0xFFFFFFFE;
+
+  /* Resume playing from the new position */
+  I2S_CODEC_Play((GetVar_AudioDataIndex()));
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_RewindPlay
+* Description    : Rewind function.
+* Input          : - Step: number of steps back
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_RewindPlay(uint32_t Step)
+{
+  /* Pause Playing the audio file */
+  I2S_CODEC_Pause();
+
+  /* Increment the Audio pointer */
+  DecrementVar_AudioDataIndex((AudioDataLength / 100) * Step);
+
+  /* Insure the index parity */
+  AudioDataIndex &= 0xFFFFFFFE;
+
+  /* Resume playing from the new position */
+  I2S_CODEC_Play((GetVar_AudioDataIndex()));
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_PowerDown
+* Description    : Power down the Audio Codec.
+* Input          : - CodecPowerDown_Mode: could be CodecPowerDown_SW for power down
+*                :   after communication, CodecPowerDown_HW simply shut down the codec
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2S_CODEC_PowerDown(uint32_t CodecPowerDown_Mode)
+{
+  if (CodecPowerDown_Mode == CodecPowerDown_SW)
+  {
+    /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
+    (void)CODEC_WriteRegister(0x00, 0x40);
+    /* Power down the VCOM*/
+    (void)CODEC_WriteRegister(0x00, 0x00);
+  }
+  else /* CodecPowerDown_HW */
+  {
+    /* Power Down the Codec */
+    GPIO_ResetBits(Codec_PDN_GPIO, Codec_PDN_Pin);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_Reset
+* Description    : Reset the Audio Codec.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_Reset(void)
+{
+  /* Power Down the Codec */
+  GPIO_ResetBits(Codec_PDN_GPIO, Codec_PDN_Pin);
+
+  /* wait for a delay to allow registers erasing */
+  delay(0xFF);
+
+  /* Power On the Codec after the power off => all registers are reinitialized*/
+  GPIO_SetBits(Codec_PDN_GPIO, Codec_PDN_Pin);
+
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_SpeakerHeadphoneSwap
+* Description    : Configure the Audio Codec output to Speaker or Headphone while
+*                : the audio wave is Paused or stopped.
+* Input          : - OutputDevice: could be OutputDevice_Speaker or OutputDevice_Headphone
+*                     or OutputDevice_Both .
+*                  - Address: Specifies the audio file location in the memory.
+* Output         : None.
+* Return         : - 0: Operation done without failures.
+*                  - 1: Memory failure occur.
+*                  - 2: Audio file initialization failure occur
+*                  - 3: I2C communication failure occur
+*******************************************************************************/
+uint32_t I2S_CODEC_SpeakerHeadphoneSwap(uint32_t OutputDevice, uint32_t Address)
+{
+  uint32_t tmp_pointer = 0, err = 0;
+
+  /* Reset all Codec Registers */
+  I2S_CODEC_Reset();
+
+  /* Save the current position */
+  tmp_pointer = GetVar_AudioDataIndex();
+
+  /* Reinitialize the CODEC with the new configured parameters */
+  err = I2S_CODEC_Init(OutputDevice, Address);
+
+  if (err != 0)
+  {
+    return err;
+  }
+
+  /* Restore the last pointer position */
+  AudioDataIndex = tmp_pointer;
+
+  /* Restore the last volume level */
+  I2S_CODEC_ControlVolume(VolumeDirection_LEVEL, CurrentVolume);
+
+  /* Play from current position */
+  I2S_CODEC_Play(tmp_pointer);
+
+  return 0;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_UpdateStatus
+* Description    : Check if STOP or PAUSE command are generated and performs the
+*                :  relative action (STOP or PAUSE playing)
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_UpdateStatus(void)
+{
+  /* STOP command is generated => Stop playing the audio file */
+  if ((GetVar_AudioPlayStatus() == AudioPlayStatus_STOPPED) && (SPI_I2S_GetFlagStatus(SPI2, I2S_FLAG_CHSIDE) == SET))
+  {
+    I2S_CODEC_Stop();
+  }
+
+  /* PAUSE Command is generated => PAUSE playing the audio File */
+  if ((GetVar_AudioPlayStatus() == AudioPlayStatus_PAUSED) && (SPI_I2S_GetFlagStatus(SPI2, I2S_FLAG_CHSIDE) == SET))
+  {
+    I2S_CODEC_Pause();
+  }
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_DataStartAddr
+* Description    : returns DataStartAddr variable value (used by stm32f10x_it.c file).
+* Input          : None
+* Output         : None
+* Return         : AudioDataIndex
+*******************************************************************************/
+uint32_t GetVar_DataStartAddr(void)
+{
+  return DataStartAddr;
+}
+
+
+/*******************************************************************************
+* Function Name  : GetVar_CurrentVolume
+* Description    : returns CurrentVolume variable value (used by extern files).
+* Input          : None
+* Output         : None
+* Return         : CurrentVolume
+*******************************************************************************/
+uint8_t GetVar_CurrentVolume(void)
+{
+  return CurrentVolume;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_WaveParsing
+* Description    : Checks the format of the .WAV file and gets information about
+*                  the audio format. This is done by reading the value of a
+*                  number of parameters stored in the file header and comparing
+*                  these to the values expected authenticates the format of a
+*                  standard .WAV  file (44 bytes will be read). If  it is a valid
+*                  .WAV file format, it continues reading the header to determine
+*                  the  audio format such as the sample rate and the sampled data
+*                  size. If the audio format is supported by this application,
+*                  it retrieves the audio format in WAVE_Format structure and
+*                  returns a zero value. Otherwise the function fails and the
+*                  return value is nonzero.In this case, the return value specifies
+*                  the cause of  the function fails. The error codes that can be
+*                  returned by this function are declared in the header file.
+* Input          : None
+* Output         : None
+* Return         : Zero value if the function succeed, otherwise it return
+*                  a nonzero value which specifies the error code.
+*******************************************************************************/
+ErrorCode I2S_CODEC_WaveParsing(uint8_t* HeaderTab)
+{
+  uint32_t Temp = 0x00;
+  uint32_t ExtraFormatBytes = 0;
+
+  /* Initialize the HeaderTabIndex variable */
+  HeaderTabIndex = 0;
+
+  /* Read chunkID, must be 'RIFF' ----------------------------------------------*/
+  Temp = ReadUnit(4, BigEndian);
+  if (Temp != ChunkID)
+  {
+    return(Unvalid_RIFF_ID);
+  }
+  /* Read the file length ----------------------------------------------------*/
+  WAVE_Format.RIFFchunksize = ReadUnit(4, LittleEndian);
+
+  /* Read the file format, must be 'WAVE' ------------------------------------*/
+  Temp = ReadUnit(4, BigEndian);
+  if (Temp != FileFormat)
+  {
+    return(Unvalid_WAVE_Format);
+  }
+  /* Read the format chunk, must be 'fmt ' -----------------------------------*/
+  Temp = ReadUnit(4, BigEndian);
+  if (Temp != FormatID)
+  {
+    return(Unvalid_FormatChunk_ID);
+  }
+  /* Read the length of the 'fmt' data, must be 0x10 -------------------------*/
+  Temp = ReadUnit(4, LittleEndian);
+  if (Temp != 0x10)
+  {
+    ExtraFormatBytes = 1;
+  }
+  /* Read the audio format, must be 0x01 (PCM) -------------------------------*/
+  WAVE_Format.FormatTag = ReadUnit(2, LittleEndian);
+  if (WAVE_Format.FormatTag != WAVE_FORMAT_PCM)
+  {
+    return(Unsupporetd_FormatTag);
+  }
+  /* Read the number of channels: 0x02->Stereo 0x01->Mono --------------------*/
+  WAVE_Format.NumChannels = ReadUnit(2, LittleEndian);
+
+  /* Read the Sample Rate ----------------------------------------------------*/
+  WAVE_Format.SampleRate = ReadUnit(4, LittleEndian);
+
+  /* Update the I2S_AudioFreq value according to the .WAV file Sample Rate */
+  switch (WAVE_Format.SampleRate)
+  {
+    case SampleRate_8000 :
+      i2saudiofreq = I2S_AudioFreq_8k;
+      break;
+    case SampleRate_16000:
+      i2saudiofreq = I2S_AudioFreq_16k;
+      break;
+    case SampleRate_22050:
+      i2saudiofreq = I2S_AudioFreq_22k;
+      break;
+    case SampleRate_44100:
+      i2saudiofreq = I2S_AudioFreq_44k;
+      break;
+    case SampleRate_48000:
+      i2saudiofreq = I2S_AudioFreq_48k;
+      break;
+    default:
+      return(Unsupporetd_Sample_Rate);
+  }
+  /* Read the Byte Rate ------------------------------------------------------*/
+  WAVE_Format.ByteRate = ReadUnit(4, LittleEndian);
+
+  /* Read the block alignment ------------------------------------------------*/
+  WAVE_Format.BlockAlign = ReadUnit(2, LittleEndian);
+
+  /* Read the number of bits per sample --------------------------------------*/
+  WAVE_Format.BitsPerSample = ReadUnit(2, LittleEndian);
+  if (WAVE_Format.BitsPerSample != Bits_Per_Sample_16)
+  {
+    return(Unsupporetd_Bits_Per_Sample);
+  }
+  /* If there are Extra format bytes, these bytes will be defined in "Fact Chunk" */
+  if (ExtraFormatBytes == 1)
+  {
+    /* Read th Extra format bytes, must be 0x00 ------------------------------*/
+    Temp = ReadUnit(2, LittleEndian);
+    if (Temp != 0x00)
+    {
+      return(Unsupporetd_ExtraFormatBytes);
+    }
+    /* Read the Fact chunk, must be 'fact' -----------------------------------*/
+    Temp = ReadUnit(4, BigEndian);
+    if (Temp != FactID)
+    {
+      return(Unvalid_FactChunk_ID);
+    }
+    /* Read Fact chunk data Size ---------------------------------------------*/
+    Temp = ReadUnit(4, LittleEndian);
+
+    /* Set the index to start reading just after the header end */
+    HeaderTabIndex += Temp;
+  }
+  /* Read the Data chunk, must be 'data' -------------------------------------*/
+  Temp = ReadUnit(4, BigEndian);
+  if (Temp != DataID)
+  {
+    return(Unvalid_DataChunk_ID);
+  }
+  /* Read the number of sample data ------------------------------------------*/
+  WAVE_Format.DataSize = ReadUnit(4, LittleEndian);
+
+  /* Set the data pointer at the beginning of the effective audio data */
+  DataStartAddr += HeaderTabIndex;
+
+  return(Valid_WAVE_File);
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_AudioDataIndex
+* Description    : returns AudioDataIndex variable value (used by stm32f10x_it.c file).
+* Input          : None
+* Output         : None
+* Return         : AudioDataIndex
+*******************************************************************************/
+uint32_t GetVar_AudioDataIndex(void)
+{
+  return AudioDataIndex;
+}
+
+/*******************************************************************************
+* Function Name  : SetVar_AudioDataIndex
+* Description    : Sets AudioDataIndex variable value (used by stm32f10x_it.c file).
+* Input          : None
+* Output         : None
+* Return         : AudioDataIndex
+*******************************************************************************/
+void SetVar_AudioDataIndex(uint32_t value)
+{
+  AudioDataIndex = value;
+}
+
+/*******************************************************************************
+* Function Name  : IncrementVar_AudioDataIndex
+* Description    : Increment the AudioDataIndex variable.
+* Input          : - IncrementNumber: number of incrementations.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void IncrementVar_AudioDataIndex(uint32_t IncrementNumber)
+{
+  AudioDataIndex += (uint32_t)IncrementNumber;
+
+  if (AudioDataIndex >= AudioDataLength)
+  {
+    ResetVar_AudioDataIndex();
+    Decrement_AudioReplay();
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DecrementVar_AudioDataIndex
+* Description    : Set the AudioDataIndex variable to 1.
+* Input          : None
+* Output         : None
+* Return         : None.
+*******************************************************************************/
+void DecrementVar_AudioDataIndex(uint32_t DecrementNumber)
+{
+  if (DecrementNumber >= AudioDataIndex)
+  {
+    ResetVar_AudioDataIndex();
+  }
+  else
+  {
+    AudioDataIndex -= (uint32_t)DecrementNumber;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : ResetVar_AudioDataIndex
+* Description    : Reset the AudioDataIndex variable.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void ResetVar_AudioDataIndex(void)
+{
+  AudioDataIndex = DataStartAddr;
+
+  /* Send the read command to the media */
+  Media_StartReadSequence(AudioFileAddress + DataStartAddr + 1);
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_SendDummyData
+* Description    : returns SendDummyData variable value (used by stm32f10x_it.c file).
+* Input          : None
+* Output         : None
+* Return         : SendDummyData
+*******************************************************************************/
+uint32_t GetVar_SendDummyData(void)
+{
+  return SendDummyData;
+}
+
+/*******************************************************************************
+* Function Name  : SetVar_SendDummyData
+* Description    : Set the SendDummyData variable to 1.
+* Input          : None
+* Output         : None
+* Return         : SendDummyData
+*******************************************************************************/
+uint32_t SetVar_SendDummyData(void)
+{
+  SendDummyData = (uint32_t)0x1;
+
+  return SendDummyData;
+}
+
+/*******************************************************************************
+* Function Name  : ResetVar_SendDummyData
+* Description    : Reset the SendDummyData variable to 0.
+* Input          : None
+* Output         : None
+* Return         : SendDummyData
+*******************************************************************************/
+uint32_t ResetVar_SendDummyData(void)
+{
+  SendDummyData = (uint32_t)0;
+
+  return SendDummyData;
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_AudioPlayStatus
+* Description    : returns AudioPlayStatus variable value (used by stm32f10x_it.c file).
+* Input          : None
+* Output         : None
+* Return         : AudioPlayStatus value.
+*******************************************************************************/
+uint32_t GetVar_AudioPlayStatus(void)
+{
+  return AudioPlayStatus;
+}
+
+/*******************************************************************************
+* Function Name  : SetVar_AudioPlayStatus
+* Description    : Set the AudioDataIndex variable to Status.
+* Input          : Status: could be AudioPlayStatus_STOPPED, AudioPlayStatus_PLAYING
+*                :        or AudioPlayStatus_PAUSED.
+* Output         : None
+* Return         : AudioPlayStatus value.
+*******************************************************************************/
+uint32_t SetVar_AudioPlayStatus(uint32_t Status)
+{
+  AudioPlayStatus = (uint32_t)Status;
+
+  return AudioPlayStatus;
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_AudioReplay
+* Description    : returns AudioReplay variable value.
+* Input          : None
+* Output         : None
+* Return         : AudioReplay value.
+*******************************************************************************/
+uint32_t GetVar_AudioReplay(void)
+{
+  return AudioReplay;
+}
+
+/*******************************************************************************
+* Function Name  : SetVar_AudioReplay
+* Description    : Decrement the AudioReplayCount variable if AudioReplay is different
+*                :  from zero (infinite replaying).
+* Input          : None.
+* Output         : None
+* Return         : AudioPlayStatus value.
+*******************************************************************************/
+void Decrement_AudioReplay(void)
+{
+  if (AudioReplay != 0)
+  {
+    AudioReplayCount--;
+
+    if (AudioReplayCount == 0)
+    {
+      /* Command the Stop of the audio playing */
+      SetVar_AudioPlayStatus(AudioPlayStatus_STOPPED);
+
+      /* Reset the counter */
+      AudioReplayCount = AudioReplay;
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_CurrentOutputDevice
+* Description    : Get the current output device selected .
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint32_t GetVar_CurrentOutputDevice(void)
+{
+  return CurrentOutputDevice;
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_AudioDataLength
+* Description    : Get the current audio file data length .
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint32_t GetVar_AudioDataLength(void)
+{
+  return AudioDataLength;
+}
+
+/*******************************************************************************
+* Function Name  : GetVar_i2saudiofreq
+* Description    : Get the current audio frequency .
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t GetVar_i2saudiofreq(void)
+{
+  return i2saudiofreq;
+}
+
+/*******************************************************************************
+* Function Name  : AudioFile_Init
+* Description    : Initializes the SPI_Flash and returns the Wavadatalength variable.
+* Input          : None
+* Output         : None
+* Return         : - The length of the wave file read from the SPI_Flash
+*                  - 1 if an error occurred when initializing the memory.
+*                  - 2 if an error occurred on the audio file initialization.
+*******************************************************************************/
+uint32_t AudioFile_Init(void)
+{
+  uint32_t err = 0;
+
+  /* Initialize the media support */
+  err = Media_Init();
+
+  /* Check if Memory initialization is OK */
+  if (err != 0)
+  {
+    return 1;
+  }
+
+  /* Read a Byte buffer and store it in the Header table*/
+  Media_BufferRead(AudioFileHeader, AudioFileAddress, HEADER_SIZE);
+
+  /* Read and check the audio file Header */
+  WaveFileStatus = I2S_CODEC_WaveParsing(AudioFileHeader);
+
+  /* Check if the selected file is a correct wave file */
+  if (WaveFileStatus == Valid_WAVE_File)
+  {
+    /* Read and set the audio data length (/!\ data are counted as BYTES /!\) */
+    AudioDataLength = WAVE_Format.DataSize ;
+
+    /* Read and set the audio frequency */
+    i2saudiofreq = (uint16_t)WAVE_Format.SampleRate;
+
+    /* Return the audio file length */
+    return AudioDataLength;
+  }
+  else /* Wrong wave file */
+  {
+    return 2;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Config
+* Description    : Configure the I2Ss NVIC channel.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void NVIC_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* SPI2 IRQ Channel configuration */
+  NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_Config
+* Description    : Initializes the GPIO pins used by the codec application.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2S_GPIO_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIOB, GPIOC and AFIO clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOG |
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_AFIO, ENABLE);
+
+  /* I2S2 SD, CK and WS pins configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  /* I2S2 MCK pin configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /* LEDs pins configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+  /* I2C1 SCL PB6 and SDA PB7 pins configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  /* Enable the I2C1 APB1 clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
+
+  /* Turn Off All LEDs */
+  GPIO_ResetBits(GPIOF, GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9);
+  GPIO_ResetBits(Codec_PDN_GPIO, Codec_PDN_Pin);
+
+  /* Configure the Codec PDN pin as output PushPull */
+  GPIO_InitStructure.GPIO_Pin = Codec_PDN_Pin;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(Codec_PDN_GPIO, &GPIO_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : I2S_Config
+* Description    : Configure the I2S Peripheral.
+* Input          :  - Standard: I2S_Standard_Phillips, I2S_Standard_MSB or I2S_Standard_LSB
+*                   - MCLKOutput: I2S_MCLKOutput_Enable or I2S_MCLKOutput_Disable
+*                   - AudioFreq: I2S_AudioFreq_8K, I2S_AudioFreq_16K, I2S_AudioFreq_22K,
+*                                I2S_AudioFreq_44K or I2S_AudioFreq_48K
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void I2S_Config(uint16_t Standard, uint16_t MCLKOutput, uint16_t AudioFreq)
+{
+  I2S_InitTypeDef I2S_InitStructure;
+
+  /* Enable I2S2 APB1 clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+  /* Deinitialize SPI2 peripheral */
+  SPI_I2S_DeInit(SPI2);
+
+  /* I2S2 peripheral configuration */
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+  I2S_InitStructure.I2S_Standard = Standard;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_MCLKOutput = MCLKOutput;
+  I2S_InitStructure.I2S_AudioFreq = AudioFreq;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_Init(SPI2, &I2S_InitStructure);
+
+  /* Disable the I2S2 TXE Interrupt */
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+  /* Enable the SPI2/I2S2 peripheral */
+  I2S_Cmd(SPI2, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name  : I2C_Config
+* Description    : Configure the I2C1 Peripheral.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+static void I2C_Config(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+
+  /* I2C1 configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x33;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = 200000;
+  I2C_Init(I2C1, &I2C_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : CODEC_Config
+* Description    : Configure the Codec in Headphone mode.
+* Input          :  - OutputDevice: OutputDeviceHEADPHONE or OutputDeviceSPEAKER
+*                :  - I2S_Standard: I2S communication standard could be I2S_Standard_Phillips
+*                :       I2S_Standard_MSB or I2S_Standard_LSB.
+*                :  - I2S_MCLKOutput: could be I2S_MCLKOutput_
+*                :  - Volume:
+* Output         : None
+* Return         : 0-> correct communication, else wrong communication
+*******************************************************************************/
+uint32_t CODEC_Config(uint16_t OutputDevice, uint16_t I2S_Standard, uint16_t I2S_MCLKOutput, uint8_t Volume)
+{
+  uint32_t Standard = 0, counter = 0, PLLMode = 0;
+
+  /* Command the sending of dummy data */
+  ResetVar_SendDummyData();
+
+  /* Reset the Codec Registers */
+  I2S_CODEC_Reset();
+
+  /* Determine the I2S standard used */
+  switch (I2S_Standard)
+  {
+    case I2S_Standard_Phillips:
+      Standard = 0x03;
+      break;
+    case I2S_Standard_MSB:
+      Standard = 0x02;
+      break;
+    default :
+      Standard = 0x01;
+      break;
+  }
+
+  /* HEADPHONE codec configuration */
+  if ((OutputDevice & OutputDevice_HEADPHONE) != 0)
+  {
+    /* PLL Slave SD/WS reference mode ----------------------*/
+    if (I2S_MCLKOutput == I2S_MCLKOutput_Disable)
+    {
+      /* set the PLLMode variable */
+      PLLMode = 0x1;
+
+      /* Phillips(0x03)/MSB(0x02)/LSB(0x01) mode with PLL */
+      counter += CODEC_WriteRegister(0x04, (Standard | 0x20));
+      /* MCKI input frequency = 256.Fs */
+      counter += CODEC_WriteRegister(0x05, 0x03);
+      /* VCOM Power up (PMVCM bit)*/
+      counter += CODEC_WriteRegister(0x00, 0x40);
+      /* Enable PLL*/
+      counter += CODEC_WriteRegister(0x01, 0x01);
+    }
+    /* Ext Slave mode with no PLL --------------------------*/
+    else
+    {
+      /* Reset the PLL mode variable */
+      PLLMode = 0;
+
+      /* Phillips(0x03)/MSB(0x02)/LSB(0x01) mode with no PLL */
+      counter += CODEC_WriteRegister(0x04, Standard);
+      /* MCKI input frequency = 256.Fs */
+      counter += CODEC_WriteRegister(0x05, 0x00);
+      /* VCOM Power up (PMVCM bit)*/
+      counter += CODEC_WriteRegister(0x00, 0x40);
+    }
+
+    /* Command the sending of dummy data */
+    SetVar_SendDummyData();
+
+    /* Enable the I2S2 TXE Interrupt  => Generate the clocks*/
+    SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+
+    /* Extra Configuration (of the ALC) */
+    counter += CODEC_WriteRegister(0x06, 0x3C );
+    counter += CODEC_WriteRegister(0x08, 0xE1 );
+    counter += CODEC_WriteRegister(0x0B, 0x00 );
+    counter += CODEC_WriteRegister(0x07, 0x20 );
+    counter += CODEC_WriteRegister(0x09, 0xC1 );
+    counter += CODEC_WriteRegister(0x0C, 0xC1 );
+
+    /* MCKI is 256.Fs with no PLL */
+    counter += CODEC_WriteRegister(0x05, 0x00 );
+    /* Switch control from DAC to Headphone */
+    counter += CODEC_WriteRegister(0x0F, 0x09 );
+    /* Bass Boost and Deemphasis enable */
+    counter += CODEC_WriteRegister(0x0E, 0x18 );
+    /* Left Channel Digital Volume control */
+    counter += CODEC_WriteRegister(0x0A, Volume);
+    /* Right Channel Digital Volume control */
+    counter += CODEC_WriteRegister(0x0D, Volume);
+    /* Power up MIN and DAC (PMMIN and PMDAC bits)*/
+    counter += CODEC_WriteRegister(0x00, 0x74);
+    /* Enable Slave mode and Left/Right HP lines*/
+    counter += CODEC_WriteRegister(0x01, (0x30 | PLLMode));
+    /* Exit HP mute mode */
+    counter += CODEC_WriteRegister(0x01, (0x70 | PLLMode));
+  }
+
+  /* SPEAKER codec configuration */
+  if ((OutputDevice & OutputDevice_SPEAKER) != 0)
+  {
+    /* PLL Slave SD/WS reference mode ----------------------*/
+    if (I2S_MCLKOutput == I2S_MCLKOutput_Disable)
+    {
+      /* Phillips(0x03)/MSB(0x02)/LSB(0x01) mode with no PLL */
+      counter += CODEC_WriteRegister(0x04, (Standard | 0x20));
+      /* MCKI input frequency = 256.Fs */
+      counter += CODEC_WriteRegister(0x05, 0x03);
+      /* VCOM Power up (PMVCM bit)*/
+      counter += CODEC_WriteRegister(0x00, 0x40);
+      /* Enable PLL*/
+      counter += CODEC_WriteRegister(0x01, 0x01);
+    }
+    /* Ext Slave mode with no PLL --------------------------*/
+    else
+    {
+      /* Phillips(0x03)/MSB(0x02)/LSB(0x01) mode with no PLL */
+      counter += CODEC_WriteRegister(0x04, Standard);
+      /* MCKI input frequency = 256.Fs */
+      counter += CODEC_WriteRegister(0x05, 0x00);
+      /* VCOM Power up (PMVCM bit)*/
+      counter += CODEC_WriteRegister(0x00, 0x40);
+    }
+
+    /* Command the sending of dummy data */
+    SetVar_SendDummyData();
+
+    /* Enable the I2S2 TXE Interrupt  => Generate the clocks*/
+    SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
+
+    /* ReSelect the MCKI frequency (FS0-1 bits): 256.Fs */
+    counter += CODEC_WriteRegister(0x05, 0x02 );
+    /* Set up the path "DAC->Speaker-Amp" with no power save (DACS and SPPSN bits) */
+    counter += CODEC_WriteRegister(0x02, 0x20 );
+    /* Speaker Gain (SPKG0-1 bits): Gain=+10.65dB(ALC off)/+12.65(ALC on) */
+    counter += CODEC_WriteRegister(0x03, 0x10);
+
+    /* Extra Configuration (of the ALC) */
+    counter += CODEC_WriteRegister(0x06, 0x3C );
+    counter += CODEC_WriteRegister(0x08, 0xE1 );
+    counter += CODEC_WriteRegister(0x0B, 0x00 );
+    counter += CODEC_WriteRegister(0x07, 0x20 );
+    counter += CODEC_WriteRegister(0x09, 0x91 );
+    counter += CODEC_WriteRegister(0x0C, 0x91 );
+
+    /* Left Channel Digital Volume control */
+    counter += CODEC_WriteRegister(0x0A, Volume);
+    /* Right Channel Digital Volume control */
+    counter += CODEC_WriteRegister(0x0D, Volume);
+    /* Power up Speaker and DAC (PMSPK and PMDAC bits)*/
+    counter += CODEC_WriteRegister(0x00, 0x54);
+    /* Set up the path "DAC -> Speaker-Amp" with no power save */
+    counter += CODEC_WriteRegister(0x02, 0xA0 /*0xA1*/);
+  }
+
+  /* Disable the I2S2 TXE Interrupt */
+  SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
+
+  /* Disable the sending of Dummy data */
+  ResetVar_SendDummyData();
+
+  /* Return the counter value */
+  return counter;
+}
+
+/*******************************************************************************
+* Function Name  : CODEC_WriteRegister
+* Description    : Writes a value in a register of the audio Codec through I2C.
+* Input          :  - RegisterAddr: The target register address (between 00x and 0x24)
+*                :  - RegisterValue: The target register value to be written
+*                :  - Verify: 0-> Don't verify the written data, 1-> Verify the written data
+* Output         : None
+* Return         : - 0  -> Correct write operation
+*                : - !0 -> Incorrect write operation
+*******************************************************************************/
+uint32_t CODEC_WriteRegister(uint32_t RegisterAddr, uint32_t RegisterValue)
+{
+  uint32_t read_verif = 0;
+
+  /* Reset all I2C2 registers */
+  I2C_SoftwareResetCmd(I2C1, ENABLE);
+  I2C_SoftwareResetCmd(I2C1, DISABLE);
+
+  /* Enable the I2C1 peripheral  */
+  I2C_Cmd(I2C1, ENABLE);
+
+  /* Configure the I2C peripheral */
+  I2C_Config();
+
+  /* Begin the config sequence */
+  I2C_GenerateSTART(I2C1, ENABLE);
+
+  /* Test on EV5 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT))
+  {}
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(I2C1, CODEC_ADDRESS, I2C_Direction_Transmitter);
+
+  /* Test on EV6 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {}
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(I2C1, RegisterAddr);
+
+  /* Test on EV8 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  {}
+
+  /* Prepare the register value to be sent */
+  I2C_SendData(I2C1, RegisterValue);
+
+  /* Test on EV8 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  {}
+
+  /* End the configuration sequence */
+  I2C_GenerateSTOP(I2C1, ENABLE);
+
+  /* Verify (if needed) that the loaded data is correct  */
+#ifdef VERIFY_WRITTENDATA
+  /* Read the just written register*/
+  read_verif = CODEC_ReadRegister(RegisterAddr);
+
+  /* Load the register and verify its value  */
+  if (read_verif != RegisterValue)
+  {
+    /* Control data wrongly transferred */
+    read_verif = 1;
+  }
+  else
+  {
+    /* Control data correctly transferred */
+    read_verif = 0;
+  }
+#endif
+
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return read_verif;
+}
+
+/*******************************************************************************
+* Function Name  : CODEC_ReadRegister
+* Description    : Reads a register of the audio Codec through I2C.
+* Input          :  - RegisterAddr: The target register address (between 00x and 0x24)
+* Output         : None
+* Return         : The value of the read register
+*******************************************************************************/
+uint32_t CODEC_ReadRegister(uint32_t RegisterAddr)
+{
+  uint32_t tmp = 0;
+
+  /* Disable the I2C1 peripheral  */
+  I2C_Cmd(I2C1, DISABLE);
+
+  /* Reset all I2C2 registers */
+  I2C_SoftwareResetCmd(I2C1, ENABLE);
+  I2C_SoftwareResetCmd(I2C1, DISABLE);
+
+  /* Configure the I2C peripheral */
+  I2C_Config();
+
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(I2C1, ENABLE);
+
+  /* Test on EV5 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT))
+  {}
+
+  /* Disable Acknowledgement */
+  I2C_AcknowledgeConfig(I2C1, DISABLE);
+
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(I2C1, CODEC_ADDRESS, I2C_Direction_Transmitter);
+
+  /* Test on EV6 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {}
+
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(I2C1, RegisterAddr);
+
+  /* Test on EV8 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  {}
+
+  /* Regenerate a start condition */
+  I2C_GenerateSTART(I2C1, ENABLE);
+
+  /* Test on EV5 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT))
+  {}
+
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(I2C1, CODEC_ADDRESS, I2C_Direction_Receiver);
+
+  /* Test on EV6 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+  {}
+
+  /* Test on EV7 and clear it */
+  while (!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_RECEIVED))
+  {}
+
+  /* End the configuration sequence */
+  I2C_GenerateSTOP(I2C1, ENABLE);
+
+  /* Load the register value */
+  tmp = I2C_ReceiveData(I2C1);
+
+  /* Disable Acknowledgement */
+  I2C_AcknowledgeConfig(I2C1, ENABLE);
+
+  /* Return the read value */
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : ReadUnit
+* Description    : Reads a number of bytes from the SPI Flash and reorder them
+*                  in Big or little endian.
+* Input          : - NbrOfBytes : number of bytes to read.
+*                    This parameter must be a number between 1 and 4.
+*                  - ReadAddr : external memory address to read from.
+*                  - Endians : specifies the bytes endianness.
+*                    This parameter can be one of the following values:
+*                          - LittleEndian
+*                          - BigEndian
+* Output         : None
+* Return         : Bytes read from the SPI Flash.
+*******************************************************************************/
+static uint32_t ReadUnit(uint8_t NbrOfBytes, Endianness BytesFormat)
+{
+  uint32_t index = 0;
+  uint32_t Temp = 0;
+
+  if (BytesFormat == LittleEndian)
+  {
+    for (index = 0; index < NbrOfBytes; index++)
+    {
+      Temp |= AudioFileHeader[HeaderTabIndex++] << (index * 8);
+    }
+  }
+  else
+  {
+    for (index = NbrOfBytes; index != 0; index--)
+    {
+      Temp |= AudioFileHeader[HeaderTabIndex++] << ((index - 1) * 8);
+    }
+  }
+
+  return Temp;
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_MediaReadHalfWord
+* Description    : Read one half word from the media (SPI_Flash/NOR/NAND memories..)
+* Input          : - Offset: the address offset for read operation
+* Output         : None.
+* Return         : Data read from the media memory.
+*******************************************************************************/
+uint16_t Media_ReadHalfWord(uint32_t Offset)
+{
+  /* Test if the left channel is to be sent */
+  if (monovar == 0)
+  {
+    /* Enable the FSMC that share a pin w/ I2C1 (LBAR) */
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+    tmpvar =  (*(__IO uint16_t *) (AudioFileAddress + Offset));
+
+    /* Disable the FSMC that share a pin w/ I2C1 (LBAR) */
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
+
+    /* Increment the mono variable only if the file is in mono format */
+    if (WAVE_Format.NumChannels == Channel_MONO)
+    {
+      /* Increment the monovar variable */
+      monovar++;
+    }
+
+    /* Return the read value */
+    return tmpvar;
+  }
+  /* Right channel to be sent in mono format */
+  else
+  {
+    /* Reset the monovar variable */
+    monovar = 0;
+
+    /* Return the previous read data in mono format */
+    return tmpvar;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_MediaReadByte
+* Description    : Read one byte from the media (SPI_Flash/NOR/NAND memories..)
+* Input          : - Offset: the address offset for read operation
+* Output         : None.
+* Return         : Data read from the media memory.
+*******************************************************************************/
+uint8_t Media_ReadByte(uint32_t Offset)
+{
+  uint8_t tmp = 0;
+
+  /* Enable the FSMC that share a pin w/ I2C1 (LBAR) */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+  /* Read data from the specified location */
+  tmp =  (*(__IO uint8_t *) (AudioFileAddress + Offset));
+
+  /* Disable the FSMC that share a pin w/ I2C1 (LBAR) */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
+
+  return tmp;
+}
+
+/*******************************************************************************
+* Function Name  : Media_Init
+* Description    : Read one byte from the media (SPI_Flash/NOR/NAND memories..)
+* Input          : - Offset: the address offset for read operation
+* Output         : None.
+* Return         : - 0 if initialization is OK
+*                  - 1 if initialization failed..
+*******************************************************************************/
+uint32_t Media_Init(void)
+{
+  return 0;
+}
+
+/*******************************************************************************
+* Function Name  : Media_BufferRead
+* Description    : Read a buffer from the memory media
+* Input          : - pBuffer: Destination buffer address
+*                : - ReadAddr: start reading position
+*                : - NumByteToRead: size of the buffer to read
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Media_BufferRead(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
+{
+  /* Enable the FSMC that share a pin w/ I2C1 (LBAR) */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+  /* Read the data */
+  while (NumByteToRead--)
+  {
+    *pBuffer++ = *(__IO uint8_t *)ReadAddr++;
+  }
+
+  /* Disable the FSMC that share a pin w/ I2C1 (LBAR) */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : Media_StartReadSequence
+* Description    : Initialize reading sequence on the media.
+* Input          : - ReadAddr: start reading position
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Media_StartReadSequence(uint32_t ReadAddr)
+{
+  /* This function could be used for memories needing a start read sequence
+      like SPI_Flash memory */
+}
+
+/*******************************************************************************
+* Function Name  : I2S_CODEC_DataTransfer
+* Description    : Sends the audio data using the SPI2 peripheral and checks the
+*                :   audio playing status (if a command (Pause/Stop) is pending
+*                :   the playing status is updated). If the TXE flag interrupt
+*                :   is used to synchronize data sending, this function should be
+*                :   called in the SPI2 ISR.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void I2S_CODEC_DataTransfer(void)
+{
+  /* Audio codec configuration section -------------------------------------*/
+  if (GetVar_SendDummyData() == 1)
+  {
+    /* Send a dummy data just to generate the I2S clock */
+    SPI_I2S_SendData(SPI2, DUMMY_DATA);
+  }
+  /* Audio codec communication section -------------------------------------*/
+  else
+  {
+    /* Send the data read from the memory */
+    SPI_I2S_SendData(SPI2, (Media_ReadHalfWord(AudioDataIndex)));
+
+    /* Increment the index */
+    IncrementVar_AudioDataIndex(WAVE_Format.NumChannels);
+
+    /* Check and update the stream playing status */
+    I2S_CODEC_UpdateStatus();
+  }
+}
+/*******************************************************************************
+* Function Name  : delay
+* Description    : Inserts a delay time.
+* Input          : nCount: specifies the delay time length
+* Output         : None
+* Return         : The length of the wave file read from the SPI_Flash
+*******************************************************************************/
+void delay(__IO uint32_t nCount)
+{
+  for (; nCount != 0; nCount--);
+}
+#endif
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/main.c
new file mode 100644
index 0000000..b58c6c3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/main.c
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Audio Speaker Demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+extern uint32_t MUTE_DATA;
+extern uint16_t In_Data_Offset;
+extern uint16_t Out_Data_Offset;
+extern uint8_t Stream_Buff[24];
+extern uint8_t IT_Clock_Sent;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : main.
+* Description    : Main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+  Set_USBClock();
+  USB_Config();
+  USB_Init();
+  Speaker_Config();
+  while (1)
+  {}
+}
+
+#ifdef  USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/stm32_it.c
new file mode 100644
index 0000000..74ba641
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/stm32_it.c
@@ -0,0 +1,336 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "stm32_it.h"
+#include "usb_istr.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DUMMYDATA  0x1111
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint16_t Out_Data_Offset;
+extern uint16_t In_Data_Offset;
+extern uint8_t Stream_Buff[24];
+extern uint32_t MUTE_DATA;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSV_Handler exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32 Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : USB_HP_CAN1_TX_IRQHandler
+* Description    : This function handles USB High Priority or CAN1 TX interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USB_HP_CAN1_TX_IRQHandler(void)
+{
+  CTR_HP();
+}
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority or CAN RX0 interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+#ifdef USE_STM3210B_EVAL
+/*******************************************************************************
+* Function Name  : TIM2_IRQHandler
+* Description    : This function handles TIM2 global interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void TIM2_IRQHandler(void)
+{
+  if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET)
+  {
+    /* Clear TIM2 update interrupt */
+    TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
+
+    if ((Out_Data_Offset < In_Data_Offset) && ((uint8_t)(MUTE_DATA) == 0))
+    {
+      TIM_SetCompare3(TIM4, Stream_Buff[Out_Data_Offset]);
+      Out_Data_Offset++;
+    }
+  }
+}
+#endif /* USE_STM3210B_EVAL */
+
+#if defined (USE_STM3210E_EVAL)
+/*******************************************************************************
+* Function Name  : SPI2_IRQHandler
+* Description    : This function handles SPI2 global interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SPI2_IRQHandler(void)
+{
+  static uint8_t channel = 0;
+
+  if ((SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET))
+  {
+    /* Audio codec configuration section */
+    if (GetVar_SendDummyData() == 1)
+    {
+      /* Send a dummy data just to generate the I2S clock */
+      SPI_I2S_SendData(SPI2, DUMMYDATA);
+    }
+    
+   else if ((Out_Data_Offset < In_Data_Offset) && ((uint8_t)(MUTE_DATA) == 0))
+    {
+      if ((channel++) & 1)
+      {
+        SPI_I2S_SendData(SPI2, (uint16_t)Stream_Buff[Out_Data_Offset++]);
+      }
+      else
+      {
+        SPI_I2S_SendData(SPI2, (uint16_t)Stream_Buff[Out_Data_Offset]);
+      }
+    }
+  }
+}
+
+#endif /* USE_STM3210E_EVAL */
+
+#if defined(STM32L1XX_MD)
+
+/**
+  * @brief  This function handles TIM6 global interrupt request.
+  * @param  None
+  * @retval None
+  */
+void TIM6_IRQHandler(void)
+{
+  if (TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET)
+  {
+    /* Clear TIM6 update interrupt */
+    TIM_ClearITPendingBit(TIM6, TIM_IT_Update);
+
+    if ((Out_Data_Offset < In_Data_Offset) && ((uint8_t)(MUTE_DATA) == 0))
+    {
+      /* Set DAC Channel1 DHR register */
+      DAC_SetChannel1Data(DAC_Align_8b_R, Stream_Buff[Out_Data_Offset]);      
+      Out_Data_Offset++;
+    }
+  }
+}
+
+#endif /* STM32L1XX_XD */
+
+/*******************************************************************************
+* Function Name  : USB_HP_IRQHandler
+* Description    : This function handles USB High Priority interrupts  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USB_HP_IRQHandler(void)
+{
+  CTR_HP();
+}
+
+/*******************************************************************************
+* Function Name  : USB_WakeUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32f10x.c
new file mode 100644
index 0000000..3686a2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32f10x.c
@@ -0,0 +1,917 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_XX */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+           
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_XX */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+        
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+       
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_desc.c
new file mode 100644
index 0000000..7f56731
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_desc.c
@@ -0,0 +1,251 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Audio Speaker Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants----------------------------------------------------------*/
+/* USB Standard Device Descriptor */
+const uint8_t Speaker_DeviceDescriptor[] =
+  {
+    SPEAKER_SIZ_DEVICE_DESC,          /* bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE,           /* bDescriptorType */
+    0x00,          /* 2.00 */             /* bcdUSB */
+    0x02,
+    0x00,                                 /* bDeviceClass */
+    0x00,                                 /* bDeviceSubClass */
+    0x00,                                 /* bDeviceProtocol */
+    0x40,                                 /* bMaxPacketSize 40 */
+    0x83,                                 /* idVendor */
+    0x04,
+    0x30,                                 /* idProduct  = 0x5730*/
+    0x57,
+    0x00,          /* 2.00 */             /* bcdDevice */
+    0x02,
+    1,                                    /* iManufacturer */
+    2,                                    /* iProduct */
+    3,                                    /* iSerialNumber */
+    0x01                                  /* bNumConfigurations */
+  };
+
+/* USB Configuration Descriptor */
+/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t Speaker_ConfigDescriptor[] =
+  {
+    /* Configuration 1 */
+    0x09,                                 /* bLength */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE,    /* bDescriptorType */
+    0x6D,                                 /* wTotalLength  110 bytes*/
+    0x00,
+    0x02,                                 /* bNumInterfaces */
+    0x01,                                 /* bConfigurationValue */
+    0x00,                                 /* iConfiguration */
+    0xC0,                                 /* bmAttributes Self Powred*/
+    0x32,                                 /* bMaxPower = 100 mA*/
+    /* 09 byte*/
+
+    /* USB Speaker Standard interface descriptor */
+    SPEAKER_SIZ_INTERFACE_DESC_SIZE,      /* bLength */
+    USB_INTERFACE_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    0x00,                                 /* bInterfaceNumber */
+    0x00,                                 /* bAlternateSetting */
+    0x00,                                 /* bNumEndpoints */
+    USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+    AUDIO_SUBCLASS_AUDIOCONTROL,          /* bInterfaceSubClass */
+    AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+    0x00,                                 /* iInterface */
+    /* 09 byte*/
+
+    /* USB Speaker Class-specific AC Interface Descriptor */
+    SPEAKER_SIZ_INTERFACE_DESC_SIZE,   /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_CONTROL_HEADER,                 /* bDescriptorSubtype */
+    0x00,          /* 1.00 */             /* bcdADC */
+    0x01,
+    0x27,                                 /* wTotalLength = 39*/
+    0x00,
+    0x01,                                 /* bInCollection */
+    0x01,                                 /* baInterfaceNr */
+    /* 09 byte*/
+
+    /* USB Speaker Input Terminal Descriptor */
+    AUDIO_INPUT_TERMINAL_DESC_SIZE,       /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_CONTROL_INPUT_TERMINAL,         /* bDescriptorSubtype */
+    0x01,                                 /* bTerminalID */
+    0x01,                                 /* wTerminalType AUDIO_TERMINAL_USB_STREAMING   0x0101 */
+    0x01,
+    0x00,                                 /* bAssocTerminal */
+    0x01,                                 /* bNrChannels */
+    0x00,                                 /* wChannelConfig 0x0000  Mono */
+    0x00,
+    0x00,                                 /* iChannelNames */
+    0x00,                                 /* iTerminal */
+    /* 12 byte*/
+
+    /* USB Speaker Audio Feature Unit Descriptor */
+    0x09,                                 /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_CONTROL_FEATURE_UNIT,           /* bDescriptorSubtype */
+    0x02,                                 /* bUnitID */
+    0x01,                                 /* bSourceID */
+    0x01,                                 /* bControlSize */
+    AUDIO_CONTROL_MUTE,                   /* bmaControls(0) */
+    0x00,                                 /* bmaControls(1) */
+    0x00,                                 /* iTerminal */
+    /* 09 byte*/
+
+    /*USB Speaker Output Terminal Descriptor */
+    0x09,      /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_CONTROL_OUTPUT_TERMINAL,        /* bDescriptorSubtype */
+    0x03,                                 /* bTerminalID */
+    0x01,                                 /* wTerminalType  0x0301*/
+    0x03,
+    0x00,                                 /* bAssocTerminal */
+    0x02,                                 /* bSourceID */
+    0x00,                                 /* iTerminal */
+    /* 09 byte*/
+
+    /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */
+    /* Interface 1, Alternate Setting 0                                             */
+    SPEAKER_SIZ_INTERFACE_DESC_SIZE,  /* bLength */
+    USB_INTERFACE_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    0x01,                                 /* bInterfaceNumber */
+    0x00,                                 /* bAlternateSetting */
+    0x00,                                 /* bNumEndpoints */
+    USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+    AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+    AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+    0x00,                                 /* iInterface */
+    /* 09 byte*/
+
+    /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
+    /* Interface 1, Alternate Setting 1                                           */
+    SPEAKER_SIZ_INTERFACE_DESC_SIZE,  /* bLength */
+    USB_INTERFACE_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    0x01,                                 /* bInterfaceNumber */
+    0x01,                                 /* bAlternateSetting */
+    0x01,                                 /* bNumEndpoints */
+    USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */
+    AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */
+    AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */
+    0x00,                                 /* iInterface */
+    /* 09 byte*/
+
+    /* USB Speaker Audio Streaming Interface Descriptor */
+    AUDIO_STREAMING_INTERFACE_DESC_SIZE,  /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_STREAMING_GENERAL,              /* bDescriptorSubtype */
+    0x01,                                 /* bTerminalLink */
+    0x01,                                 /* bDelay */
+    0x02,                                 /* wFormatTag AUDIO_FORMAT_PCM8  0x0002*/
+    0x00,
+    /* 07 byte*/
+
+    /* USB Speaker Audio Type I Format Interface Descriptor */
+    0x0B,                                 /* bLength */
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */
+    AUDIO_STREAMING_FORMAT_TYPE,          /* bDescriptorSubtype */
+    AUDIO_FORMAT_TYPE_I,                  /* bFormatType */
+    0x01,                                 /* bNrChannels */
+    0x01,                                 /* bSubFrameSize */
+    8,                                    /* bBitResolution */
+    0x01,                                 /* bSamFreqType */
+    0xF0,                                 /* tSamFreq 22000 = 0x55F0 */
+    0x55,
+    0x00,
+    /* 11 byte*/
+
+    /* Endpoint 1 - Standard Descriptor */
+    AUDIO_STANDARD_ENDPOINT_DESC_SIZE,    /* bLength */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,         /* bDescriptorType */
+    0x01,                                 /* bEndpointAddress 1 out endpoint*/
+    USB_ENDPOINT_TYPE_ISOCHRONOUS,        /* bmAttributes */
+    0x16,                                 /* wMaxPacketSize 22 bytes*/
+    0x00,
+    0x01,                                 /* bInterval */
+    0x00,                                 /* bRefresh */
+    0x00,                                 /* bSynchAddress */
+    /* 09 byte*/
+
+    /* Endpoint - Audio Streaming Descriptor*/
+    AUDIO_STREAMING_ENDPOINT_DESC_SIZE,   /* bLength */
+    AUDIO_ENDPOINT_DESCRIPTOR_TYPE,       /* bDescriptorType */
+    AUDIO_ENDPOINT_GENERAL,               /* bDescriptor */
+    0x00,                                 /* bmAttributes */
+    0x00,                                 /* bLockDelayUnits */
+    0x00,                                 /* wLockDelay */
+    0x00,
+    /* 07 byte*/
+  };
+
+/* USB String Descriptor (optional) */
+const uint8_t Speaker_StringLangID[SPEAKER_SIZ_STRING_LANGID] =
+  {
+    0x04,
+    0x03,
+    0x09,
+    0x04
+  }
+  ; /* LangID = 0x0409: U.S. English */
+
+const uint8_t Speaker_StringVendor[SPEAKER_SIZ_STRING_VENDOR] =
+  {
+    SPEAKER_SIZ_STRING_VENDOR, /* Size of manufacturer string */
+    USB_STRING_DESCRIPTOR_TYPE,  /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t Speaker_StringProduct[SPEAKER_SIZ_STRING_PRODUCT] =
+  {
+    SPEAKER_SIZ_STRING_PRODUCT,  /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0,
+    'S', 0, 'p', 0, 'e', 0, 'a', 0, 'k', 0, 'e', 0, 'r', 0
+  };
+
+uint8_t Speaker_StringSerial[SPEAKER_SIZ_STRING_SERIAL] =
+  {
+    SPEAKER_SIZ_STRING_SERIAL,  /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0
+  };
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_istr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_istr.c
new file mode 100644
index 0000000..f5786a2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_istr.c
@@ -0,0 +1,248 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   ISTR events interrupt service routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t wIstr;  /* ISTR register last read value */
+__IO uint8_t bIntPackSOF = 0;  /* SOFs received between 2 consecutive packets */
+__IO uint32_t esof_counter =0; /* expected SOF counter */
+__IO uint32_t wCNTR=0;
+
+/* Extern variables ----------------------------------------------------------*/
+extern uint16_t In_Data_Offset;
+extern uint16_t Out_Data_Offset;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* function pointers to non-control endpoints service routines */
+void (*pEpInt_IN[7])(void) =
+  {
+    EP1_IN_Callback,
+    EP2_IN_Callback,
+    EP3_IN_Callback,
+    EP4_IN_Callback,
+    EP5_IN_Callback,
+    EP6_IN_Callback,
+    EP7_IN_Callback,
+  };
+
+void (*pEpInt_OUT[7])(void) =
+  {
+    EP1_OUT_Callback,
+    EP2_OUT_Callback,
+    EP3_OUT_Callback,
+    EP4_OUT_Callback,
+    EP5_OUT_Callback,
+    EP6_OUT_Callback,
+    EP7_OUT_Callback,
+  };
+
+
+/*******************************************************************************
+* Function Name  : USB_Istr
+* Description    : ISTR events interrupt service routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Istr(void)
+{
+    uint32_t i=0;
+ __IO uint32_t EP[8];
+  
+  wIstr = _GetISTR();
+
+#if (IMR_MSK & ISTR_CTR)
+  if (wIstr & ISTR_CTR & wInterrupt_Mask)
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    CTR_LP();
+
+#ifdef CTR_CALLBACK
+    CTR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
+#if (IMR_MSK & ISTR_RESET)
+  if (wIstr & ISTR_RESET & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_RESET);
+    Device_Property.Reset();
+#ifdef RESET_CALLBACK
+    RESET_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_DOVR)
+  if (wIstr & ISTR_DOVR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_DOVR);
+#ifdef DOVR_CALLBACK
+    DOVR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ERR)
+  if (wIstr & ISTR_ERR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ERR);
+#ifdef ERR_CALLBACK
+    ERR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_WKUP)
+  if (wIstr & ISTR_WKUP & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_WKUP);
+    Resume(RESUME_EXTERNAL);
+#ifdef WKUP_CALLBACK
+    WKUP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SUSP)
+  if (wIstr & ISTR_SUSP & wInterrupt_Mask)
+  {
+
+    /* check if SUSPEND is possible */
+    if (fSuspendEnabled)
+    {
+      Suspend();
+    }
+    else
+    {
+      /* if not possible then resume after xx ms */
+      Resume(RESUME_LATER);
+    }
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    _SetISTR((uint16_t)CLR_SUSP);
+#ifdef SUSP_CALLBACK
+    SUSP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SOF)
+  if (wIstr & ISTR_SOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_SOF);
+    bIntPackSOF++;
+
+#ifdef SOF_CALLBACK
+    SOF_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ESOF)
+  if (wIstr & ISTR_ESOF & wInterrupt_Mask)
+  {
+    /* clear ESOF flag in ISTR */
+    _SetISTR((uint16_t)CLR_ESOF);
+    
+    if ((_GetFNR()&FNR_RXDP)!=0)
+    {
+      /* increment ESOF counter */
+      esof_counter ++;
+      
+      /* test if we enter in ESOF more than 3 times with FSUSP =0 and RXDP =1=>> possible missing SUSP flag*/
+      if ((esof_counter >3)&&((_GetCNTR()&CNTR_FSUSP)==0))
+      {           
+        /* this a sequence to apply a force RESET*/
+      
+        /*Store CNTR value */
+        wCNTR = _GetCNTR(); 
+      
+        /*Store endpoints registers status */
+        for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+      
+        /*apply FRES */
+        wCNTR|=CNTR_FRES;
+        _SetCNTR(wCNTR);
+ 
+        /*clear FRES*/
+        wCNTR&=~CNTR_FRES;
+        _SetCNTR(wCNTR);
+      
+        /*poll for RESET flag in ISTR*/
+        while((_GetISTR()&ISTR_RESET) == 0);
+  
+        /* clear RESET flag in ISTR */
+        _SetISTR((uint16_t)CLR_RESET);
+   
+       /*restore Enpoints*/
+        for (i=0;i<8;i++)
+        _SetENDPOINT(i, EP[i]);
+      
+        esof_counter = 0;
+      }
+    }
+    else
+    {
+        esof_counter = 0;
+    }
+    
+    /* resume handling timing is made with ESOFs */
+    Resume(RESUME_ESOF); /* request without change of the machine state */
+
+#ifdef ESOF_CALLBACK
+    ESOF_Callback();
+#endif
+  }
+#endif
+} /* USB_Istr */
+
+/*******************************************************************************
+* Function Name  : USB_Istr
+* Description    : Start of frame callback function.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SOF_Callback(void)
+{
+  In_Data_Offset = 0;
+  Out_Data_Offset = 0;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_pwr.c
new file mode 100644
index 0000000..a2253a8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Audio_Speaker/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..8b7d80d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvopt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvopt
new file mode 100644
index 0000000..f161eaa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvopt
@@ -0,0 +1,2649 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0058NAE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06418041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0058NAE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06418041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC5000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L151xx_152xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152D-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L162xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_384 -FS08000000 -FL060000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0579U9E -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32373C_EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32373C_EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvproj
new file mode 100644
index 0000000..6c36c3e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/MDK-ARM/Composite_Example.uvproj
@@ -0,0 +1,13585 @@
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+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
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+          <Flash4></Flash4>
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+            <LinkerInputFile></LinkerInputFile>
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+        </TargetArmAds>
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+          <GroupName>User</GroupName>
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+          <Flash4></Flash4>
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+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments></TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
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+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
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+            <AdsLmap>1</AdsLmap>
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+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
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+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32F30X, USE_STM32303C_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\\STM32F30x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x8000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
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+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>stm32f37x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
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+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>hw_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\hw_config.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_desc.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_endp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_endp.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_istr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_istr.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_prop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_prop.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsmc_nand.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\fsmc_nand.c</FilePath>
+              <FileOption>
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+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
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+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
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+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>mass_mal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\mass_mal.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\src\memory.c</FilePath>
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+            <File>
+              <FileName>nand_if.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\nand_if.c</FilePath>
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+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
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+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
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+                <FileArmAds>
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+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>usb_bot.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_bot.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_scsi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_scsi.c</FilePath>
+            </File>
+            <File>
+              <FileName>scsi_data.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\scsi_data.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
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+                  <ModuleSelection>0</ModuleSelection>
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+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
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+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
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+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l152d_eval_sdio_sd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval_sdio_sd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32373c_eval_spi_sd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval_spi_sd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32303c_eval_spi_sd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval_spi_sd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/RIDE/Composite_Example.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/RIDE/Composite_Example.rprj
new file mode 100644
index 0000000..20bcdb6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/RIDE/Composite_Example.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'Composite_Example'" Path=".\Composite_Example.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="Composite_Example" >
+	<ApplicationBuild Header="Composite_Example" Extern=".\Composite_Example.rapp" Path=".\Composite_Example.rapp" OutputFile=".\STM32303-EVAL\Composite_Example.elf" Config="STM32303C_EVAL" sate="98" />
+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..8f1ba33
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,247 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210B_EVAL/stm3210b_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..2d09c3d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..a479212
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="STM32F103ZE" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.project
new file mode 100644
index 0000000..1295c9c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/.project
@@ -0,0 +1,203 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment/>
+	<projects>
+	</projects>
+	<buildSpec>
+		  <buildCommand>
+			  <name>com.tasking.arm.TskManagedBuilder</name>
+			  <arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		  <nature>org.eclipse.cdt.core.cnature</nature>
+		  <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		  <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		  <nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+    <link>
+			  <name>Doc</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>Doc/readme.txt</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>  <link>
+			  <name>STM32F10x</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/CMSIS</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/CMSIS/system_stm32f10x.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM3210E_EVAL</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM3210E_EVAL/stm3210e_eval.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/misc.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>  <link>
+			  <name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_core.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_init.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_int.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_mem.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_regs.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>  <link>
+			  <name>USB-FS-Device_Driver/usb_sil.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>  <link>
+			  <name>User</name>
+			  <type>2</type>
+			  <locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>  <link>
+			  <name>User/fsmc_nand.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>  <link>
+			  <name>User/hw_config.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>  <link>
+			  <name>User/main.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>  <link>
+			  <name>User/mass_mal.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>  <link>
+			  <name>User/memory.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>  <link>
+			  <name>User/nand_if.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>  <link>
+			  <name>User/scsi_data.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>  <link>
+			  <name>User/stm32_it.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_bot.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_desc.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_endp.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_istr.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_prop.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_pwr.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>  <link>
+			  <name>User/usb_scsi.c</name>
+			  <type>1</type>
+			  <locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link></linkedResources>
+
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..af72174
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
new file mode 100644
index 0000000..f1bb71e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 512k;
+    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                       vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                      /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..2f3a8e2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+			</storageModule>
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+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
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+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
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+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
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+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_XL.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
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+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
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+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..93a6438
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,247 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl_extsram.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
index ebc4fb7..a944802 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/stm32f10x_hd_vl_extsram.lsl
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
@@ -23,7 +23,7 @@
 
 
 #ifndef __STACK
-#  define __STACK                       2k
+#  define __STACK                       8k
 #endif
 #ifndef __HEAP
 #  define __HEAP                        2k
@@ -57,27 +57,19 @@ memory stm32f103flash
 {
     mau = 8;
     type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+    size = 0x100000;
+    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
 }
 
 memory stm32f103ram
 {
     mau = 8;
     type = ram;
-    size = 1024k;
-    map ( size = 1024k, dest_offset=0x68000000, dest=bus:ARM:local_bus);
+    size = 96k;
+    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
 }
 
 #endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
 
 
 //
@@ -95,8 +87,8 @@ section_setup ::linear
                                               no_inline
                                             )
                 {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
                         vector ( id = 2, optional, fill = "NMI_Handler" );
                         vector ( id = 3, optional, fill = "HardFault_Handler" );
                         vector ( id = 4, optional, fill = "MemManage_Handler" );
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..276c0b8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,119 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="560"/>
+									<listOptionValue builtIn="false" value="557"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<fileInfo id="com.tasking.config.arm.abs.debug.2044455393.295297643" name="usb_prop.c" rcbsApplicability="disable" resourcePath="User/usb_prop.c" toolsToInvoke="com.tasking.arm.cc.abs.debug.1657066278.669303476">
+						<tool id="com.tasking.arm.cc.abs.debug.1657066278.669303476" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug.1657066278">
+							<option id="com.tasking.arm.cc.optimize.1482032908" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.0" valueType="enumerated"/>
+							<inputType id="com.tasking.arm.cppInputType.1481381979" name="C++" superClass="com.tasking.arm.cppInputType"/>
+							<inputType id="com.tasking.arm.cpp.cInputType.1849430261" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+							<inputType id="com.tasking.arm.cc.msInputType.1490198869" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+						</tool>
+					</fileInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/.cproject
new file mode 100644
index 0000000..058c9a6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/.cproject
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32373C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f373vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F37X"/>
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="560"/>
+									<listOptionValue builtIn="false" value="549"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f37x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<fileInfo id="com.tasking.config.arm.abs.debug.2044455393.1482238769" name="usb_prop.c" rcbsApplicability="disable" resourcePath="User/usb_prop.c" toolsToInvoke="com.tasking.arm.cc.abs.debug.1657066278.1247166636">
+						<tool id="com.tasking.arm.cc.abs.debug.1657066278.1247166636" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug.1657066278">
+							<option id="com.tasking.arm.cc.optimize.1499953571" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.0" valueType="enumerated"/>
+							<inputType id="com.tasking.arm.cppInputType.2005148028" name="C++" superClass="com.tasking.arm.cppInputType"/>
+							<inputType id="com.tasking.arm.cpp.cInputType.512421559" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+							<inputType id="com.tasking.arm.cc.msInputType.341687022" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+						</tool>
+					</fileInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
new file mode 100644
index 0000000..6c766c6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32373C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32373C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..d8ba5b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..24aeee3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.cproject
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="STM32L152VB" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_md.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..c34ba34
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,237 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152_EVAL/stm32l152_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..9672c54
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,237 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..463038d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                            // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..7772f2a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.cproject
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
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+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
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+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
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+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
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+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
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+					<sourceEntries>
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+	</storageModule>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+				<buildOutputProvider>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
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+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
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+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
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+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
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+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..48e3a74
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,291 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ba973b2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:15:49 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..cbbda89
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 16:43:25 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.316348137/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.316348137/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.316348137/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.316348137/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.316348137/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
new file mode 100644
index 0000000..eec22d7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Custom_HID\TrueSTUDIO\STM3210B-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210B-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..e0aa35c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..7768c2a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:16:40 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..aa0068a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 16:43:41 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
new file mode 100644
index 0000000..09aa202
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Custom_HID\TrueSTUDIO\STM3210E-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210E-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..b543267
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
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+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
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+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
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+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
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+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..4c1cd2c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,296 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..f494c19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 16:43:56 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.189815562/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.189815562/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.189815562/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.189815562/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.189815562/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
new file mode 100644
index 0000000..b1c6965
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of 96K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..730491d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,352 @@
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+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..ed7266d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,340 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..1341ab0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:40:41 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..aa0068a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 16:43:41 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/delimiter=;
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new file mode 100644
index 0000000..c50ce5b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.cproject
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+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..b7c9e1f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..969048d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Fri Dec 14 08:51:00 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..5ce5ba5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,4 @@
+#Fri Dec 14 09:47:22 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/project/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/project/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..aa0068a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 16:43:41 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..5bd9514
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Composite_Example\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..35c7d30
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..25d858f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.cproject
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
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+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.743524191" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
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+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
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+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..c0293a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..6159162
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:18:43 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..54665d9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Custom_HID\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..1be62d5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_md Device with
+**                128KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..be2da63
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32L152D_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152D-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.743524191" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32L152D-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
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+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
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+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
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+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
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+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
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+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
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+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
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+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..3a6ee8a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,286 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152D_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152D_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/fsmc_nand.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/fsmc_nand.h
new file mode 100644
index 0000000..9bdee98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/fsmc_nand.h
@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nand.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for fsmc_nand.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FSMC_NAND_H
+#define __FSMC_NAND_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint8_t Maker_ID;
+  uint8_t Device_ID;
+  uint8_t Third_ID;
+  uint8_t Fourth_ID;
+}NAND_IDTypeDef;
+
+typedef struct 
+{
+  uint16_t Zone;
+  uint16_t Block;
+  uint16_t Page;
+} NAND_ADDRESS;
+
+/* Exported constants --------------------------------------------------------*/
+/* NAND Area definition  for STM3210E-EVAL Board RevD */
+#define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE  high */
+#define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
+
+#define DATA_AREA                  ((uint32_t)0x00000000) 
+
+/* FSMC NAND memory command */
+#define	NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define	NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+	
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
+
+#define NAND_CMD_READID            ((uint8_t)0x90)	
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/* FSMC NAND memory parameters */
+#define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
+#define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
+#define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
+#define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
+#define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
+
+/* FSMC NAND memory address computation */
+#define ADDR_1st_CYCLE(ADDR)       (uint8_t)((ADDR)& 0xFF)               /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF00) >> 8)      /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void FSMC_NAND_Init(void);
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID);
+uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite);
+uint32_t FSMC_NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead);
+uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
+uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
+uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address);
+uint32_t FSMC_NAND_Reset(void);
+uint32_t FSMC_NAND_GetStatus(void);
+uint32_t FSMC_NAND_ReadStatus(void);
+uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address);
+
+#endif /* __FSMC_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/mass_mal.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/mass_mal.h
new file mode 100644
index 0000000..4374449
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/mass_mal.h
@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file    mass_mal.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for mass_mal.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MASS_MAL_H
+#define __MASS_MAL_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define MAL_OK   0
+#define MAL_FAIL 1
+#define MAX_LUN  1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint16_t MAL_Init (uint8_t lun);
+uint16_t MAL_GetStatus (uint8_t lun);
+uint16_t MAL_Read(uint8_t lun, uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length);
+uint16_t MAL_Write(uint8_t lun, uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length);
+#endif /* __MASS_MAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/memory.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/memory.h
new file mode 100644
index 0000000..3cc19a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/memory.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    memory.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Memory management layer
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __memory_H
+#define __memory_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define TXFR_IDLE     0
+#define TXFR_ONGOING  1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Write_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length);
+void Read_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length);
+#endif /* __memory_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/platform_config.h
new file mode 100644
index 0000000..609b2fb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/platform_config.h
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+  #include "stm32l152_eval_spi_sd.h"
+ 
+#elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval_sdio_sd.h"
+  #include "stm32l152d_eval.h"
+
+#else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+  #include "stm3210b_eval_spi_sd.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval_sdio_sd.h"
+  #include "stm3210e_eval.h"
+  #include "fsmc_nand.h"
+  #include "nand_if.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+ #include "stm32373c_eval_spi_sd.h"
+
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+ #include "stm32303c_eval_spi_sd.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL)&&  !defined (USE_STM32373C_EVAL) &&  !defined (USE_STM32303C_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define USE_STM32373C_EVAL
+ #define USE_STM32303C_EVAL
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+
+#define RCC_AHBPeriph_ALLGPIO                 (RCC_AHBPeriph_GPIOA \
+                                              | RCC_AHBPeriph_GPIOB \
+                                              | RCC_AHBPeriph_GPIOC \
+                                              | RCC_AHBPeriph_GPIOD \
+                                              | RCC_AHBPeriph_GPIOE \
+                                              | RCC_AHBPeriph_GPIOF )
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+  #define ADC1_DR_Address                     ((uint32_t)0x4001244C)
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+  #define ADC1_DR_Address                     ((uint32_t)0x4001244C)
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       0
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+  #define ADC1_DR_Address                     ((uint32_t)0x40012458)
+
+#endif /* USE_STM3210B_EVAL */
+
+#if defined (USE_STM32373C_EVAL)
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+#endif
+#if defined (USE_STM32303C_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+#endif
+
+#if defined (USE_STM32L152_EVAL)
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOB
+  #define GPIO_IOAIN                          GPIOB
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_12   /* PB.12 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_18
+
+#elif defined (USE_STM32L152D_EVAL)
+  
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOF
+  #define GPIO_IOAIN                          GPIOF
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_10   /* PF.10 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_31
+
+#elif defined (USE_STM32373C_EVAL)
+  
+  #define ADC1_DR_Address                     0x4001244C
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOB
+  #define GPIO_IOAIN                          GPIOB
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_1   /* PB.1 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_9
+  #define GPIO_Mode_AIN                       GPIO_Mode_AN
+
+#elif defined (USE_STM32303C_EVAL)
+  
+  #define ADC1_DR_Address                     0x5000030C
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOC
+  #define GPIO_IOAIN                          GPIOC
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_1   /* PC.1 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_7
+  #define GPIO_Mode_AIN                       GPIO_Mode_AN
+
+#else
+  #define RCC_APB2Periph_GPIO_IOAIN           RCC_APB2Periph_GPIOC
+  #define GPIO_IOAIN                          GPIOC
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_4   /* PC.04 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_14
+
+#endif /* USE_STM32L152_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32_it.h
new file mode 100644
index 0000000..7c4b238
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32_it.h
@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void EXTI15_10_IRQHandler(void);
+
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32l1xx_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32l1xx_conf.h
new file mode 100644
index 0000000..42c3a01
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/stm32l1xx_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CONF_H
+#define __STM32L1xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_crc.h"
+#include "stm32l1xx_comp.h"
+#include "stm32l1xx_dac.h" 
+#include "stm32l1xx_dbgmcu.h"
+#include "stm32l1xx_dma.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_flash.h"
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_iwdg.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_tim.h" 
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_wwdg.h"
+#include "stm32l1xx_sdio.h"
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32L1xx_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_desc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_desc.h
new file mode 100644
index 0000000..f3f7d31
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_desc.h
@@ -0,0 +1,69 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptor Header for Custom HID Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
+#define USB_STRING_DESCRIPTOR_TYPE              0x03
+#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
+#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
+
+#define HID_DESCRIPTOR_TYPE                     0x21
+#define CUSTOMHID_SIZ_HID_DESC                  0x09
+#define CUSTOMHID_OFF_HID_DESC                  0x12
+
+#define Composite_SIZ_DEVICE_DESC               18
+#define Composite_SIZ_CONFIG_DESC               64
+#define CUSTOMHID_SIZ_REPORT_DESC               143
+#define Composite_SIZ_STRING_LANGID             4
+#define Composite_SIZ_STRING_VENDOR             38
+#define Composite_SIZ_STRING_PRODUCT            48
+#define Composite_SIZ_STRING_SERIAL             26
+
+#define STANDARD_ENDPOINT_DESC_SIZE             0x09
+
+/* Exported functions ------------------------------------------------------- */
+extern const uint8_t Composite_DeviceDescriptor[Composite_SIZ_DEVICE_DESC];
+extern const uint8_t Composite_ConfigDescriptor[Composite_SIZ_CONFIG_DESC];
+extern const uint8_t CustomHID_ReportDescriptor[CUSTOMHID_SIZ_REPORT_DESC];
+extern const uint8_t Composite_StringLangID[Composite_SIZ_STRING_LANGID];
+extern const uint8_t Composite_StringVendor[Composite_SIZ_STRING_VENDOR];
+extern const uint8_t Composite_StringProduct[Composite_SIZ_STRING_PRODUCT];
+extern uint8_t Composite_StringSerial[Composite_SIZ_STRING_SERIAL];
+
+#endif /* __USB_DESC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_istr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_istr.h
new file mode 100644
index 0000000..017dce7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_istr.h
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the peripherals header files in the user application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+ void USB_Istr(void);
+
+/* function prototypes Automatically built defining related macros */
+
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+
+#ifdef CTR_CALLBACK
+void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+void ESOF_Callback(void);
+#endif
+
+#endif /*__USB_ISTR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_prop.h
new file mode 100644
index 0000000..a43ee70
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_prop.h
@@ -0,0 +1,89 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Custom HID demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PROP_H
+#define __USB_PROP_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _HID_REQUESTS
+{
+  GET_REPORT = 1,
+  GET_IDLE,
+  GET_PROTOCOL,
+
+  SET_REPORT = 9,
+  SET_IDLE,
+  SET_PROTOCOL
+} HID_REQUESTS;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void CustomHID_init(void);
+void CustomHID_Reset(void);
+void CustomHID_SetConfiguration(void);
+void CustomHID_SetDeviceAddress (void);
+void CustomHID_Status_In (void);
+void CustomHID_Status_Out (void);
+RESULT CustomHID_Data_Setup(uint8_t);
+RESULT CustomHID_NoData_Setup(uint8_t);
+RESULT CustomHID_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *CustomHID_GetDeviceDescriptor(uint16_t );
+uint8_t *CustomHID_GetConfigDescriptor(uint16_t);
+uint8_t *CustomHID_GetStringDescriptor(uint16_t);
+RESULT CustomHID_SetProtocol(void);
+uint8_t *CustomHID_GetProtocolValue(uint16_t Length);
+RESULT CustomHID_SetProtocol(void);
+uint8_t *CustomHID_GetReportDescriptor(uint16_t Length);
+uint8_t *CustomHID_GetHIDDescriptor(uint16_t Length);
+void CustomHID_ClearFeature(void);
+
+/* MASS Storage Requests*/
+#define GET_MAX_LUN                0xFE
+#define MASS_STORAGE_RESET         0xFF
+#define LUN_DATA_LENGTH            1
+
+
+/* Exported define -----------------------------------------------------------*/
+#define CustomHID_GetConfiguration          NOP_Process
+//#define CustomHID_SetConfiguration          NOP_Process
+#define CustomHID_GetInterface              NOP_Process
+#define CustomHID_SetInterface              NOP_Process
+#define CustomHID_GetStatus                 NOP_Process
+//#define CustomHID_ClearFeature              NOP_Process
+#define CustomHID_SetEndPointFeature        NOP_Process
+#define CustomHID_SetDeviceFeature          NOP_Process
+//#define CustomHID_SetDeviceAddress          NOP_Process
+
+#define REPORT_DESCRIPTOR                  0x22
+
+#endif /* __USB_PROP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_pwr.h
new file mode 100644
index 0000000..b15860c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_pwr.h
@@ -0,0 +1,70 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+/* External variables --------------------------------------------------------*/
+extern  __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_scsi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_scsi.h
new file mode 100644
index 0000000..5c4d46f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/inc/usb_scsi.h
@@ -0,0 +1,154 @@
+/**
+  ******************************************************************************
+  * @file    usb_scsi.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to the SCSI commands
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_SCSI_H
+#define __USB_SCSI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* SCSI Commands */
+#define SCSI_FORMAT_UNIT                            0x04
+#define SCSI_INQUIRY                                0x12
+#define SCSI_MODE_SELECT6                           0x15
+#define SCSI_MODE_SELECT10                          0x55
+#define SCSI_MODE_SENSE6                            0x1A
+#define SCSI_MODE_SENSE10                           0x5A
+#define SCSI_ALLOW_MEDIUM_REMOVAL                   0x1E
+#define SCSI_READ6                                  0x08
+#define SCSI_READ10                                 0x28
+#define SCSI_READ12                                 0xA8
+#define SCSI_READ16                                 0x88
+
+#define SCSI_READ_CAPACITY10                        0x25
+#define SCSI_READ_CAPACITY16                        0x9E
+
+#define SCSI_REQUEST_SENSE                          0x03
+#define SCSI_START_STOP_UNIT                        0x1B
+#define SCSI_TEST_UNIT_READY                        0x00
+#define SCSI_WRITE6                                 0x0A
+#define SCSI_WRITE10                                0x2A
+#define SCSI_WRITE12                                0xAA
+#define SCSI_WRITE16                                0x8A
+
+#define SCSI_VERIFY10                               0x2F
+#define SCSI_VERIFY12                               0xAF
+#define SCSI_VERIFY16                               0x8F
+
+#define SCSI_SEND_DIAGNOSTIC                        0x1D
+#define SCSI_READ_FORMAT_CAPACITIES                 0x23
+
+#define NO_SENSE		                    0
+#define RECOVERED_ERROR		                    1
+#define NOT_READY		                    2
+#define MEDIUM_ERROR		                    3
+#define HARDWARE_ERROR		                    4
+#define ILLEGAL_REQUEST		                    5
+#define UNIT_ATTENTION		                    6
+#define DATA_PROTECT		                    7
+#define BLANK_CHECK		                    8
+#define VENDOR_SPECIFIC		                    9
+#define COPY_ABORTED		                    10
+#define ABORTED_COMMAND		                    11
+#define VOLUME_OVERFLOW		                    13
+#define MISCOMPARE		                    14
+
+
+#define INVALID_COMMAND                             0x20
+#define INVALID_FIELED_IN_COMMAND                   0x24
+#define PARAMETER_LIST_LENGTH_ERROR                 0x1A
+#define INVALID_FIELD_IN_PARAMETER_LIST             0x26
+#define ADDRESS_OUT_OF_RANGE                        0x21
+#define MEDIUM_NOT_PRESENT 			    0x3A
+#define MEDIUM_HAVE_CHANGED			    0x28
+
+#define READ_FORMAT_CAPACITY_DATA_LEN               0x0C
+#define READ_CAPACITY10_DATA_LEN                    0x08
+#define MODE_SENSE10_DATA_LEN                       0x08
+#define MODE_SENSE6_DATA_LEN                        0x04
+#define REQUEST_SENSE_DATA_LEN                      0x12
+#define STANDARD_INQUIRY_DATA_LEN                   0x24
+#define BLKVFY                                      0x04
+
+extern  uint8_t Page00_Inquiry_Data[];
+extern  uint8_t Standard_Inquiry_Data[];
+extern  uint8_t Standard_Inquiry_Data2[];
+extern  uint8_t Mode_Sense6_data[];
+extern  uint8_t Mode_Sense10_data[];
+extern  uint8_t Scsi_Sense_Data[];
+extern  uint8_t ReadCapacity10_Data[];
+extern  uint8_t ReadFormatCapacity_Data [];
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SCSI_Inquiry_Cmd(uint8_t lun);
+void SCSI_ReadFormatCapacity_Cmd(uint8_t lun);
+void SCSI_ReadCapacity10_Cmd(uint8_t lun);
+void SCSI_RequestSense_Cmd (uint8_t lun);
+void SCSI_Start_Stop_Unit_Cmd(uint8_t lun);
+void SCSI_ModeSense6_Cmd (uint8_t lun);
+void SCSI_ModeSense10_Cmd (uint8_t lun);
+void SCSI_Write10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr);
+void SCSI_Read10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr);
+void SCSI_Verify10_Cmd(uint8_t lun);
+
+void SCSI_Invalid_Cmd(uint8_t lun);
+void SCSI_Valid_Cmd(uint8_t lun);
+bool SCSI_Address_Management(uint8_t lun , uint8_t Cmd , uint32_t LBA , uint32_t BlockNbr);
+
+void Set_Scsi_Sense_Data(uint8_t lun , uint8_t Sens_Key, uint8_t Asc);
+void SCSI_TestUnitReady_Cmd (uint8_t lun);
+void SCSI_Format_Cmd (uint8_t lun);
+
+//#define SCSI_TestUnitReady_Cmd           SCSI_Valid_Cmd
+#define SCSI_Prevent_Removal_Cmd         SCSI_Valid_Cmd
+
+/* Invalid (Unsupported) commands */
+#define SCSI_READ_CAPACITY16_Cmd         SCSI_Invalid_Cmd
+//#define SCSI_FormatUnit_Cmd              SCSI_Invalid_Cmd
+#define SCSI_Write6_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Write16_Cmd                 SCSI_Invalid_Cmd
+#define SCSI_Write12_Cmd                 SCSI_Invalid_Cmd
+#define SCSI_Read6_Cmd                   SCSI_Invalid_Cmd
+#define SCSI_Read12_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Read16_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Send_Diagnostic_Cmd         SCSI_Invalid_Cmd
+#define SCSI_Mode_Select6_Cmd            SCSI_Invalid_Cmd
+#define SCSI_Mode_Select10_Cmd           SCSI_Invalid_Cmd
+#define SCSI_Verify12_Cmd                SCSI_Invalid_Cmd
+#define SCSI_Verify16_Cmd                SCSI_Invalid_Cmd
+
+#endif /* __USB_SCSI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/readme.txt
new file mode 100644
index 0000000..38afddb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/readme.txt
@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the Composite Example Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+This Demo provides a description of how to use the USB-FS-Device on the STM32F10xxx, 
+STM32F37xxx, STM32F30xxx and STM32L15xxx devices.
+The examples provide a composite device
+A composite device is one that has multiple interfaces controlled independently of each other.
+Using composite device, multiple functions are combined into a single device.
+In this Example the independent interfaces are : Mass Storage (MSC) and Custom HID
+
+LED1,LED2 and LED3 are reserved for Custom HID demo
+LED4 reserved for MSC, it is ON when MicroSD is Ready for write and read operations.
+
+When even one of the interface class of the device is changed, it should be handled
+differently by Windows. However, it doesn't recognize the modification. To avoid conflict on
+Windows, we suggest to assign another VID/PID to the device (idProduct = 0x5750) or
+delete device instance from device manager.
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain 
+ + \TASKING: contains preconfigured projects for TASKING toolchain  
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain           
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3. 
+
+  - STM32L152-EVAL Set-up 
+     - Jumpers JP18 and JP19 should be connected. 
+     - Jumper JP17 should be connected in position 5-6 (PB12 connector)
+     - Note that JoySitck Right and Left buttons are used for this Demo.
+	 
+  - STM32L152D-EVAL Set-up 
+	 - LCD Glass should be mounted On IO position for Potentiometer usage.
+	 - JP13 should be connected to ADC input. 
+
+  - STM32F373C_EVAL  Set-up 
+      - None. 
+
+  - STM32F303C_EVAL  Set-up 
+      - None. 
+	  
+How to use it
+=============
+ + EWARM
+    - Open the Composite_Example.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the Composite_Example.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)  
+
+ + RIDE
+    - Open the Composite_Example.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/fsmc_nand.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/fsmc_nand.c
new file mode 100644
index 0000000..ae3b79f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/fsmc_nand.c
@@ -0,0 +1,503 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nand.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file provides a set of functions needed to drive the
+*                      NAND512W3A2 memory mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nand.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define FSMC_Bank_NAND     FSMC_Bank2_NAND
+#define Bank_NAND_ADDR     Bank2_NAND_ADDR 
+#define Bank2_NAND_ADDR    ((uint32_t)0x70000000)
+
+/* Private macro -------------------------------------------------------------*/
+#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : FSMC_NAND_Init
+* Description    : Configures the FSMC and GPIOs to interface with the NAND memory.
+*                  This function must be called before any write/read operation
+*                  on the NAND.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NAND_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure; 
+  FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
+  FSMC_NAND_PCCARDTimingInitTypeDef  p;
+  
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+/* CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |  
+                                 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | 
+                                 GPIO_Pin_7;                                  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/* D4->D7 NAND pin configuration  */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+
+/* NWAIT NAND pin configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;   							 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/* INT2 NAND pin configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;   							 
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  /*-- FSMC Configuration ------------------------------------------------------*/
+  p.FSMC_SetupTime = 0x1;
+  p.FSMC_WaitSetupTime = 0x3;
+  p.FSMC_HoldSetupTime = 0x2;
+  p.FSMC_HiZSetupTime = 0x1;
+
+  FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
+  FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
+  FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
+  FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
+  FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
+
+  FSMC_NANDInit(&FSMC_NANDInitStructure);
+
+  /* FSMC NAND Bank Cmd Test */
+  FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadID
+* Description    : Reads NAND memory's ID.
+* Input          : - NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
+*                    the Manufacturer and Device ID.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
+{
+  uint32_t data = 0;
+
+  /* Send Command to the command area */ 	
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+
+   /* Sequence to read ID from NAND flash */	
+   data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
+
+   NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
+   NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
+   NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
+   NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);  
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_WriteSmallPage
+* Description    : This routine is for writing one or several 512 Bytes Page size.
+* Input          : - pBuffer: pointer on the Buffer containing data to be written   
+*                  - Address: First page address
+*                  - NumPageToWrite: Number of page to write  
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
+{
+  uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /* Page write command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);  
+
+    /* Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
+
+    /* Write data */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /* Check status for successful operation */
+    status = FSMC_NAND_GetStatus();
+    
+    if(status == NAND_READY)
+    {
+      numpagewritten++;
+
+      NumPageToWrite--;
+
+      /* Calculate Next small page Address */
+      addressstatus = FSMC_NAND_AddressIncrement(&Address);    
+    }    
+  }
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadSmallPage
+* Description    : This routine is for sequential read from one or several 
+*                  512 Bytes Page size.
+* Input          : - pBuffer: pointer on the Buffer to fill  
+*                  - Address: First page address
+*                  - NumPageToRead: Number of page to read
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
+{
+  uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {	   
+    /* Page Read command and page address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; 
+   
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); 
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; 
+
+    /* Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
+    
+    /* Get Data into Buffer */    
+    for(; index < size; index++)
+    {
+      pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+
+    numpageread++;
+    
+    NumPageToRead--;
+
+    /* Calculate page address */           			 
+    addressstatus = FSMC_NAND_AddressIncrement(&Address);
+  }
+
+  status = FSMC_NAND_GetStatus();
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_WriteSpareArea
+* Description    : This routine write the spare area information for the specified 
+*                  pages addresses.
+* Input          : - pBuffer: pointer on the Buffer containing data to be written 
+*                  - Address: First page address
+*                  - NumSpareAreaTowrite: Number of Spare Area to write
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00; 
+
+  while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /* Page write Spare area command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); 
+
+    /* Calculate the size */ 
+    size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
+
+    /* Write the data */ 
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /* Check status for successful operation */
+    status = FSMC_NAND_GetStatus();
+
+    if(status == NAND_READY)
+    {
+      numsparesreawritten++;      
+
+      NumSpareAreaTowrite--;  
+    
+      /* Calculate Next page Address */
+      addressstatus = FSMC_NAND_AddressIncrement(&Address);
+    }       
+  }
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadSpareArea
+* Description    : This routine read the spare area information from the specified
+*                  pages addresses.
+* Input          : - pBuffer: pointer on the Buffer to fill  
+*                  - Address: First page address
+*                  - NumSpareAreaToRead: Number of Spare Area to read
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
+{
+  uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {     
+    /* Page Read command and page address */     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);    
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1;
+
+    /* Data Read */
+    size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
+	
+    /* Get Data into Buffer */
+    for ( ;index < size; index++)
+    {
+      pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+    
+    numsparearearead++;
+    
+    NumSpareAreaToRead--;
+
+    /* Calculate page address */           			 
+    addressstatus = FSMC_NAND_AddressIncrement(&Address);
+  }
+
+  status = FSMC_NAND_GetStatus();
+
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_EraseBlock
+* Description    : This routine erase complete block from NAND FLASH
+* Input          : - Address: Any address into block to be erased
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*******************************************************************************/
+uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
+
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+		
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; 
+
+  return (FSMC_NAND_GetStatus());
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_Reset
+* Description    : This routine reset the NAND FLASH
+* Input          : None
+* Output         : None
+* Return         : NAND_READY
+*******************************************************************************/
+uint32_t FSMC_NAND_Reset(void)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
+
+  return (NAND_READY);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_GetStatus
+* Description    : Get the NAND operation status
+* Input          : None
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation    
+*******************************************************************************/
+uint32_t FSMC_NAND_GetStatus(void)
+{
+  uint32_t timeout = 0x1000000, status = NAND_READY;
+
+  status = FSMC_NAND_ReadStatus(); 
+
+  /* Wait for a NAND operation to complete or a TIMEOUT to occur */
+  while ((status != NAND_READY) &&( timeout != 0x00))
+  {
+     status = FSMC_NAND_ReadStatus();
+     timeout --;      
+  }
+
+  if(timeout == 0x00)
+  {          
+    status =  NAND_TIMEOUT_ERROR;      
+  } 
+
+  /* Return the operation status */
+  return (status);      
+}
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadStatus
+* Description    : Reads the NAND memory status using the Read status command 
+* Input          : None
+* Output         : None
+* Return         : The status of the NAND memory. This parameter can be:
+*                   - NAND_BUSY: when memory is busy
+*                   - NAND_READY: when memory is ready for the next operation    
+*                   - NAND_ERROR: when the previous operation generates error   
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadStatus(void)
+{
+  uint32_t data = 0x00, status = NAND_BUSY;
+
+  /* Read status operation ------------------------------------ */
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
+  data = *(__IO uint8_t *)(Bank_NAND_ADDR);
+
+  if((data & NAND_ERROR) == NAND_ERROR)
+  {
+    status = NAND_ERROR;
+  } 
+  else if((data & NAND_READY) == NAND_READY)
+  {
+    status = NAND_READY;
+  }
+  else
+  {
+    status = NAND_BUSY; 
+  }
+  
+  return (status);
+}
+
+/******************************************************************************
+* Function Name  : NAND_AddressIncrement
+* Description    : Increment the NAND memory address
+* Input          : - Address: address to be incremented.
+* Output         : None
+* Return         : The new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  Address->Page++;
+
+  if(Address->Page == NAND_BLOCK_SIZE)
+  {
+    Address->Page = 0;
+    Address->Block++;
+    
+    if(Address->Block == NAND_ZONE_SIZE)
+    {
+      Address->Block = 0;
+      Address->Zone++;
+
+      if(Address->Zone == NAND_MAX_ZONE)
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/hw_config.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/hw_config.c
new file mode 100644
index 0000000..98c213d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/hw_config.c
@@ -0,0 +1,707 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "mass_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+ErrorStatus HSEStartUpStatus;
+uint32_t ADC_ConvertedValueX = 0;
+uint32_t ADC_ConvertedValueX_1 = 0;
+__IO uint16_t  ADC1ConvertedValue = 0, ADC1ConvertedVoltage = 0, calibration_value = 0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : MAL_Config
+* Description    : MAL_layer configuration
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void MAL_Config(void)
+{
+  MAL_Init(0);
+  
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL)
+  /* Enable the FSMC Clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+  MAL_Init(1);
+#endif /* STM32F10X_HD | STM32F10X_XL */
+}
+/*******************************************************************************
+* Function Name  : Set_System
+* Description    : Configures Main system clocks & power.
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_System(void)
+{
+#if defined (STM32F37X) || defined (STM32F30X)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /*STM32L1XX_XD */
+  
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /* USB_USE_EXTERNAL_PULLUP */
+  
+  /*!< At this stage the microcontroller clock setting is already configured, 
+  this is done through SystemInit() function which is called from startup
+  file (startup_stm32xxx.s) before to branch to application main.
+  To reconfigure the default setting of SystemInit() function, refer to
+  system_stm32xxx.c file
+  */ 
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) ||  defined (STM32F37X) ||  defined (STM32F30X)
+  /* Enable the SYSCFG module clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+#endif /* STM32L1XX_XD */ 
+  
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS) && !defined(STM32F37X) && !defined(STM32F30X)
+  /* Enable USB_DISCONNECT GPIO clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE);
+  
+  /* ADCCLK = PCLK2/8 */
+  RCC_ADCCLKConfig(RCC_PCLK2_Div8);    
+#endif /* STM32L1XX_XD */
+  
+  /* Configure the used GPIOs*/
+  GPIO_Configuration();
+  
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+  
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);  
+#endif /* USB_USE_EXTERNAL_PULLUP */
+  
+#if defined(STM32F37X) || defined(STM32F30X)
+  
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+  
+  /*Set PA11,12 as IN - USB_DM,DP*/
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /*SET PA11,12 for USB: USB_DM,DP*/
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_14);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_14);
+  
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+  
+#endif
+#if defined(STM32L1XX_MD) 
+  /* Configure the LEFT button in EXTI mode */
+  STM_EVAL_PBInit(Button_LEFT, Mode_EXTI);
+  
+  /* Configure the RIGHT button in EXTI mode */
+  STM_EVAL_PBInit(Button_RIGHT, Mode_EXTI);
+#else  
+  /* Configure the KEY button in EXTI mode */
+  STM_EVAL_PBInit(Button_KEY, Mode_EXTI);
+#if !defined(STM32L1XX_HD)&& !defined(STM32L1XX_MD_PLUS) && !defined(STM32F37X) && !defined(STM32F30X) 
+  /* Configure the Tamper button in EXTI mode */
+  STM_EVAL_PBInit(Button_TAMPER, Mode_EXTI);
+#endif /* STM32L1XX_XD */
+#endif  
+  /* Additional EXTI configuration (configure both edges) */
+  EXTI_Configuration();
+  
+  /* Configure the LEDs */
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);
+  
+#if defined (STM32F30X)
+  ADC30x_Configuration();
+#else  
+  /* Configure the ADC*/
+  ADC_Configuration();
+#endif
+  /* MAL configuration */
+  MAL_Config();
+}
+
+/*******************************************************************************
+* Function Name  : Set_USBClock
+* Description    : Configures USB Clock input (48MHz).
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Set_USBClock(void)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  /* Enable USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+  
+#else
+  /* Select USBCLK source */
+  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
+  
+  /* Enable the USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : Enter_LowPowerMode.
+* Description    : Power-off system clocks and power while entering suspend mode.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Enter_LowPowerMode(void)
+{
+  /* Set the device state to suspend */
+  bDeviceState = SUSPENDED;
+}
+
+/*******************************************************************************
+* Function Name  : Leave_LowPowerMode.
+* Description    : Restores system clocks and power while exiting suspend mode.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Leave_LowPowerMode(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+  
+  /* Set the device state to the correct state */
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+  else 
+  {
+    bDeviceState = ATTACHED;
+  }
+  /*Enable SystemCoreClock*/
+  SystemInit();
+#if defined(STM32L1XX_MD)|| defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  /* Enable The HSI (16Mhz) */
+  RCC_HSICmd(ENABLE); 
+#endif
+#if defined(STM32F30X)
+  ADC30x_Configuration();
+#endif
+}
+
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config.
+* Description    : Configures the USB interrupts.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Interrupts_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure; 
+  
+  /* 2 bit for pre-emption priority, 2 bits for subpriority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);  
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#elif defined(STM32F37X)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#else
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+#endif /* STM32L1XX_XD */
+  
+  /* Enable the EXTI9_5 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the EXTI15_10 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the DMA1 Channel1 Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) 
+  NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_Init(&NVIC_InitStructure);
+  NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_Init(&NVIC_InitStructure);
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : USB_Cable_Config.
+* Description    : Software Connection/Disconnection of USB Cable.
+* Input          : NewState: new state.
+* Output         : None.
+* Return         : None
+*******************************************************************************/
+void USB_Cable_Config (FunctionalState NewState)
+{ 
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS)
+  if (NewState != DISABLE)
+  {
+    STM32L15_USB_CONNECT;
+  }
+  else
+  {
+    STM32L15_USB_DISCONNECT;
+  }  
+#else 
+  
+  if (NewState != DISABLE)
+  {
+    GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+  else
+  {
+    GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_Configuration
+* Description    : Configures the different GPIO ports.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined (STM32F37X) || defined (STM32F30X)
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT | 
+                        RCC_AHBPeriph_GPIO_IOAIN , ENABLE); 
+#else  
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT | 
+                         RCC_APB2Periph_GPIO_IOAIN , ENABLE); 
+  
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32L1XX_XD */ 
+  
+  /* Configure Potentiometer IO as analog input */
+  GPIO_InitStructure.GPIO_Pin = GPIO_IOAIN_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+  GPIO_Init(GPIO_IOAIN, &GPIO_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name : EXTI_Configuration.
+* Description   : Configure the EXTI lines for Key and Tamper push buttons.
+* Input         : None.
+* Output        : None.
+* Return value  : The direction value.
+*******************************************************************************/
+void EXTI_Configuration(void)
+{
+  EXTI_InitTypeDef EXTI_InitStructure;
+  
+#if defined (USE_STM32L152_EVAL)
+  /* Configure RIGHT EXTI line to generate an interrupt on rising & falling edges */  
+  EXTI_InitStructure.EXTI_Line = RIGHT_BUTTON_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Clear the RIGHT EXTI line pending bit */
+  EXTI_ClearITPendingBit(RIGHT_BUTTON_EXTI_LINE);
+  
+  /* Configure LEFT EXTI Line to generate an interrupt rising & falling edges */  
+  EXTI_InitStructure.EXTI_Line = LEFT_BUTTON_EXTI_LINE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Clear the LEFT EXTI line pending bit */
+  EXTI_ClearITPendingBit(LEFT_BUTTON_EXTI_LINE);
+  
+#else    
+  /* Configure Key EXTI line to generate an interrupt on rising & falling edges */  
+  EXTI_InitStructure.EXTI_Line = KEY_BUTTON_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Clear the Key EXTI line pending bit */
+  EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  
+  /* Configure Tamper EXTI Line to generate an interrupt rising & falling edges */  
+#if !defined (USE_STM32L152D_EVAL) && !defined (STM32F30X)
+  EXTI_InitStructure.EXTI_Line = TAMPER_BUTTON_EXTI_LINE;
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+  
+  /* Clear the Tamper EXTI line pending bit */
+  EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE);
+#endif 
+#endif /* USE_STM32L152_EVAL */ 
+  
+  /* Configure the EXTI line 18 connected internally to the USB IP */
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure); 
+}
+
+#if !defined (STM32F30X)
+/*******************************************************************************
+* Function Name : ADC_Configuration.
+* Description   : Configure the ADC and DMA.
+* Input         : None.
+* Output        : None.
+* Return value  : The direction value.
+*******************************************************************************/
+void ADC_Configuration(void)
+{
+  ADC_InitTypeDef       ADC_InitStructure;
+  DMA_InitTypeDef DMA_InitStructure;
+  /* Enable DMA1 clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+  
+  /* Enable ADC1 clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+  
+  /* DMA1 channel1 configuration ---------------------------------------------*/
+  DMA_DeInit(DMA1_Channel1);
+  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC_ConvertedValueX;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+  DMA_InitStructure.DMA_BufferSize = 1;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(DMA1_Channel1, &DMA_InitStructure);
+  
+  /* Enable DMA1 channel1 */
+  DMA_Cmd(DMA1_Channel1, ENABLE);
+  
+  /* Enable the DMA1 Channel1 Transfer complete interrupt */
+  DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE);
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  /* Enable the HSI for the ADC operations */
+  RCC_HSICmd(ENABLE);
+  
+  /* ADC1 configuration ------------------------------------------------------*/
+  ADC_StructInit(&ADC_InitStructure);
+  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
+  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_NbrOfConversion = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
+  
+#if defined (USE_STM32L152D_EVAL)
+  /* ADC1 regular channel31 configuration */ 
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_31, 1, ADC_SampleTime_384Cycles);
+  
+#else
+  /* ADC1 regular channel18 configuration */ 
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_18, 1, ADC_SampleTime_384Cycles);
+#endif
+  
+#if !defined (USE_STM32373C_EVAL)
+  /* Enable the request after last transfer for DMA Circular mode */
+  ADC_DMARequestAfterLastTransferCmd(ADC1, ENABLE);
+#endif
+  /* Enable ADC1 DMA */
+  ADC_DMACmd(ADC1, ENABLE);
+  
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+  
+#else
+  /* ADC1 configuration ------------------------------------------------------*/
+#if !defined (USE_STM32373C_EVAL)
+  ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
+#endif
+  
+  ADC_InitStructure.ADC_ScanConvMode = ENABLE;
+  ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
+  ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_NbrOfChannel = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
+  
+  /* ADC1 regular channel configuration */ 
+  ADC_RegularChannelConfig(ADC1, ADC_AIN_CHANNEL, 1, ADC_SampleTime_55Cycles5);
+  
+  /* Enable ADC1 DMA */
+  ADC_DMACmd(ADC1, ENABLE);
+  
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+  
+  /* Enable ADC1 reset calibration register */   
+  ADC_ResetCalibration(ADC1);
+  /* Check the end of ADC1 reset calibration register */
+  while(ADC_GetResetCalibrationStatus(ADC1));
+  /* Start ADC1 calibration */
+  ADC_StartCalibration(ADC1);
+  
+  /* Check the end of ADC1 calibration */
+  while(ADC_GetCalibrationStatus(ADC1));  
+  
+#endif /* STM32L1XX_XD */ 
+  
+}
+#endif /* STM32F30x */
+/*******************************************************************************
+* Function Name  : Get_SerialNum.
+* Description    : Create the serial number string descriptor.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Get_SerialNum(void)
+{
+  uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+  
+  Device_Serial0 = *(uint32_t*)ID1;
+  Device_Serial1 = *(uint32_t*)ID2;
+  Device_Serial2 = *(uint32_t*)ID3; 
+  
+  Device_Serial0 += Device_Serial2;
+  
+  if (Device_Serial0 != 0)
+  {
+    IntToUnicode (Device_Serial0, &Composite_StringSerial[2] , 8);
+    IntToUnicode (Device_Serial1, &Composite_StringSerial[18], 4);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : HexToChar.
+* Description    : Convert Hex 32Bits value into char.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
+{
+  uint8_t idx = 0;
+  
+  for( idx = 0 ; idx < len ; idx ++)
+  {
+    if( ((value >> 28)) < 0xA )
+    {
+      pbuf[ 2* idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2* idx] = (value >> 28) + 'A' - 10; 
+    }
+    
+    value = value << 4;
+    
+    pbuf[ 2* idx + 1] = 0;
+  }
+}
+
+/*******************************************************************************
+* Function Name : ADC30x_Configuration
+* Description   : Configure the ADC and DMA.
+* Input         : None.
+* Output        : None.
+* Return value  : The direction value.
+*******************************************************************************/
+#if defined (STM32F30X)
+
+void ADC30x_Configuration(void)
+{
+  ADC_InitTypeDef    ADC_InitStructure;
+  ADC_CommonInitTypeDef ADC_CommonInitStructure;
+  DMA_InitTypeDef  DMA_InitStructure;
+  
+  /* Enable DMA1 clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+  /* DMA1 channel1 configuration ---------------------------------------------*/
+  DMA_DeInit(DMA1_Channel1);
+  DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC_ConvertedValueX;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+  DMA_InitStructure.DMA_BufferSize = 1;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(DMA1_Channel1, &DMA_InitStructure);
+  
+  /* Enable DMA1 channel1 */
+  DMA_Cmd(DMA1_Channel1, ENABLE);
+  
+  /* Enable the DMA1 Channel1 Transfer complete interrupt */
+  DMA_ITConfig(DMA1_Channel1, DMA_IT_TC, ENABLE);
+  
+  /* Configure the ADC clock */  
+  RCC_ADCCLKConfig(RCC_ADC12PLLCLK_Div2);
+  
+  /* ADC1 Periph clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ADC12, ENABLE);
+  ADC_DeInit(ADC1);
+  ADC_StructInit(&ADC_InitStructure);
+  
+  /* Calibration procedure */
+  ADC_VoltageRegulatorCmd(ADC1, ENABLE);
+  ADC_SelectCalibrationMode(ADC1, ADC_CalibrationMode_Single);
+  ADC_StartCalibration(ADC1);
+  
+  while(ADC_GetCalibrationStatus(ADC1) != RESET );
+  calibration_value = ADC_GetCalibrationValue(ADC1);
+  
+  /* Configure the ADC1 in continuous mode */  
+  ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;                                                                    
+  ADC_CommonInitStructure.ADC_Clock = ADC_Clock_AsynClkMode;                    
+  ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;             
+  ADC_CommonInitStructure.ADC_DMAMode = ADC_DMAMode_OneShot;                  
+  ADC_CommonInitStructure.ADC_TwoSamplingDelay = 0;          
+  
+  ADC_CommonInit(ADC1, &ADC_CommonInitStructure);
+  
+  /* ADC1 DMA Enable */
+  ADC_DMACmd(ADC1, ENABLE);
+  ADC_DMAConfig(ADC1, ADC_DMAMode_Circular);
+  
+  ADC_InitStructure.ADC_ContinuousConvMode = ADC_ContinuousConvMode_Enable;
+  ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b; 
+  ADC_InitStructure.ADC_ExternalTrigConvEvent = ADC_ExternalTrigConvEvent_0;         
+  ADC_InitStructure.ADC_ExternalTrigEventEdge = ADC_ExternalTrigEventEdge_None;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_OverrunMode = ADC_OverrunMode_Disable;   
+  ADC_InitStructure.ADC_AutoInjMode = ADC_AutoInjec_Disable;  
+  ADC_InitStructure.ADC_NbrOfRegChannel = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
+  
+  /* ADC1 regular channel7 configuration */ 
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_7, 1, ADC_SampleTime_7Cycles5);
+  
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+  
+  /* wait for ADRDY */
+  while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_RDY));
+  
+  /* Start ADC1 Software Conversion */ 
+  ADC_StartConversion(ADC1);
+  
+  /* Test EOC flag */
+  while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET);
+  /* Get ADC1 converted data */
+  
+  ADC_ConvertedValueX =ADC_GetConversionValue(ADC1);
+}
+
+#endif
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/mass_mal.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/mass_mal.c
new file mode 100644
index 0000000..3b5183c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/mass_mal.c
@@ -0,0 +1,233 @@
+/**
+  ******************************************************************************
+  * @file    mass_mal.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Medium Access Layer interface
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "mass_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t Mass_Memory_Size[2];
+uint32_t Mass_Block_Size[2];
+uint32_t Mass_Block_Count[2];
+__IO uint32_t Status = 0;
+
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+SD_CardInfo mSDCardInfo;
+#endif
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : MAL_Init
+* Description    : Initializes the Media on the STM32
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Init(uint8_t lun)
+{
+  uint16_t status = MAL_OK;
+
+  switch (lun)
+  {
+    case 0:
+      Status = SD_Init();
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Init();
+      break;
+#endif
+    default:
+      return MAL_FAIL;
+  }
+  return status;
+}
+/*******************************************************************************
+* Function Name  : MAL_Write
+* Description    : Write sectors
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Write(uint8_t lun, uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length)
+{
+
+  switch (lun)
+  {
+    case 0:
+    Status = SD_WriteMultiBlocks((uint8_t*)Writebuff, Memory_Offset, Transfer_Length,1);
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+    Status = SD_WaitWriteOperation();  
+    while(SD_GetStatus() != SD_TRANSFER_OK);
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }      
+#endif /* USE_STM3210E_EVAL ||USE_STM32L152D_EVAL*/      
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Write(Memory_Offset, Writebuff, Transfer_Length);
+      break;
+#endif /* USE_STM3210E_EVAL */  
+    default:
+      return MAL_FAIL;
+  }
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : MAL_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : Buffer pointer
+*******************************************************************************/
+uint16_t MAL_Read(uint8_t lun, uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length)
+{
+
+  switch (lun)
+  {
+    case 0:
+
+      SD_ReadMultiBlocks((uint8_t*)Readbuff, Memory_Offset, Transfer_Length, 1);
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+      Status = SD_WaitReadOperation();
+      while(SD_GetStatus() != SD_TRANSFER_OK)
+      {
+      }
+      
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }
+#endif /* USE_STM3210E_EVAL */      
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Read(Memory_Offset, Readbuff, Transfer_Length);
+      ;
+      break;
+#endif
+    default:
+      return MAL_FAIL;
+  }
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : MAL_GetStatus
+* Description    : Get status
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_GetStatus (uint8_t lun)
+{
+#ifdef USE_STM3210E_EVAL
+  NAND_IDTypeDef NAND_ID;
+  uint32_t DeviceSizeMul = 0, NumberOfBlocks = 0;
+#else
+  SD_CSD SD_csd;
+  uint32_t DeviceSizeMul = 0;
+#endif /* USE_STM3210E_EVAL */
+
+#ifdef USE_STM32L152D_EVAL
+
+  uint32_t NumberOfBlocks = 0;
+#endif
+
+  if (lun == 0)
+  {
+#if defined (USE_STM3210E_EVAL)  || defined(USE_STM32L152D_EVAL)
+    if (SD_Init() == SD_OK)
+    {
+      SD_GetCardInfo(&mSDCardInfo);
+      SD_SelectDeselect((uint32_t) (mSDCardInfo.RCA << 16));
+      DeviceSizeMul = (mSDCardInfo.SD_csd.DeviceSizeMul + 2);
+
+      if(mSDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+      {
+        Mass_Block_Count[0] = (mSDCardInfo.SD_csd.DeviceSize + 1) * 1024;
+      }
+      else
+      {
+        NumberOfBlocks  = ((1 << (mSDCardInfo.SD_csd.RdBlockLen)) / 512);
+        Mass_Block_Count[0] = ((mSDCardInfo.SD_csd.DeviceSize + 1) * (1 << DeviceSizeMul) << (NumberOfBlocks/2));
+      }
+      Mass_Block_Size[0]  = 512;
+
+      Status = SD_SelectDeselect((uint32_t) (mSDCardInfo.RCA << 16)); 
+      Status = SD_EnableWideBusOperation(SDIO_BusWide_4b); 
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }
+     
+#else
+
+    uint32_t temp_block_mul = 0;
+    SD_GetCSDRegister(&SD_csd);
+    DeviceSizeMul = SD_csd.DeviceSizeMul + 2;
+    temp_block_mul = (1 << SD_csd.RdBlockLen)/ 512;
+    Mass_Block_Count[0] = ((SD_csd.DeviceSize + 1) * (1 << (DeviceSizeMul))) * temp_block_mul;
+    Mass_Block_Size[0] = 512;
+    Mass_Memory_Size[0] = (Mass_Block_Count[0] * Mass_Block_Size[0]);
+#endif /* USE_STM3210E_EVAL */
+      Mass_Memory_Size[0] = Mass_Block_Count[0] * Mass_Block_Size[0];
+      STM_EVAL_LEDOn(LED4);
+      return MAL_OK;
+
+#if defined (USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+    }
+#endif /* USE_STM3210E_EVAL */
+  }
+#ifdef USE_STM3210E_EVAL
+  else
+  {
+    FSMC_NAND_ReadID(&NAND_ID);
+    if (NAND_ID.Device_ID != 0 )
+    {
+      /* only one zone is used */
+      Mass_Block_Count[1] = NAND_ZONE_SIZE * NAND_BLOCK_SIZE * NAND_MAX_ZONE ;
+      Mass_Block_Size[1]  = NAND_PAGE_SIZE;
+      Mass_Memory_Size[1] = (Mass_Block_Count[1] * Mass_Block_Size[1]);
+      return MAL_OK;
+    }
+  }
+#endif /* USE_STM3210E_EVAL */
+  STM_EVAL_LEDOn(LED4);
+  return MAL_FAIL;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/memory.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/memory.c
new file mode 100644
index 0000000..e574c55
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/memory.c
@@ -0,0 +1,175 @@
+/**
+  ******************************************************************************
+  * @file    memory.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Memory management layer
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "memory.h"
+#include "usb_scsi.h"
+#include "usb_bot.h"
+#include "usb_regs.h"
+#include "usb_mem.h"
+#include "usb_conf.h"
+#include "hw_config.h"
+#include "mass_mal.h"
+#include "usb_lib.h"
+
+#define BULK_MAX_PACKET_SIZE 64
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t Block_Read_count = 0;
+__IO uint32_t Block_offset;
+__IO uint32_t Counter = 0;
+uint32_t  Idx;
+uint32_t Data_Buffer[64 *2]; /* 512 bytes*/
+uint8_t TransferState = TXFR_IDLE;
+/* Extern variables ----------------------------------------------------------*/
+extern uint8_t Bulk_Data_Buff[64];  /* data buffer*/
+extern uint16_t Data_Len;
+extern uint8_t Bot_State;
+extern Bulk_Only_CBW CBW;
+extern Bulk_Only_CSW CSW;
+extern uint32_t Mass_Memory_Size[2];
+extern uint32_t Mass_Block_Size[2];
+
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Read_Memory
+* Description    : Handle the Read operation from the microSD card.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Read_Memory(uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length)
+{
+  static uint32_t Offset, Length;
+
+  if (TransferState == TXFR_IDLE )
+  {
+    Offset = Memory_Offset * Mass_Block_Size[lun];
+    Length = Transfer_Length * Mass_Block_Size[lun];
+    TransferState = TXFR_ONGOING;
+  }
+
+  if (TransferState == TXFR_ONGOING )
+  {
+    if (!Block_Read_count)
+    {
+      MAL_Read(lun ,
+               Offset ,
+               Data_Buffer,
+               Mass_Block_Size[lun]);
+
+      USB_SIL_Write(EP2_IN, (uint8_t *)Data_Buffer, BULK_MAX_PACKET_SIZE);
+
+      Block_Read_count = Mass_Block_Size[lun] - BULK_MAX_PACKET_SIZE;
+      Block_offset = BULK_MAX_PACKET_SIZE;
+    }
+    else
+    {
+      USB_SIL_Write(EP2_IN, (uint8_t *)Data_Buffer + Block_offset, BULK_MAX_PACKET_SIZE);
+
+      Block_Read_count -= BULK_MAX_PACKET_SIZE;
+      Block_offset += BULK_MAX_PACKET_SIZE;
+    }
+
+    SetEPTxCount(ENDP2, BULK_MAX_PACKET_SIZE);
+    SetEPTxStatus(ENDP2, EP_TX_VALID);  
+    Offset += BULK_MAX_PACKET_SIZE;
+    Length -= BULK_MAX_PACKET_SIZE;
+
+    CSW.dDataResidue -= BULK_MAX_PACKET_SIZE;
+  }
+  if (Length == 0)
+  {
+    Block_Read_count = 0;
+    Block_offset = 0;
+    Offset = 0;
+    Bot_State = BOT_DATA_IN_LAST;
+    TransferState = TXFR_IDLE;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Write_Memory
+* Description    : Handle the Write operation to the microSD card.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Write_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length)
+{
+
+  static uint32_t W_Offset, W_Length;
+
+  uint32_t temp =  Counter + 64;
+
+  if (TransferState == TXFR_IDLE )
+  {
+    W_Offset = Memory_Offset * Mass_Block_Size[lun];
+    W_Length = Transfer_Length * Mass_Block_Size[lun];
+    TransferState = TXFR_ONGOING;
+  }
+
+  if (TransferState == TXFR_ONGOING )
+  {
+
+    for (Idx = 0 ; Counter < temp; Counter++)
+    {
+      *((uint8_t *)Data_Buffer + Counter) = Bulk_Data_Buff[Idx++];
+    }
+
+    W_Offset += Data_Len;
+    W_Length -= Data_Len;
+
+    if (!(W_Length % Mass_Block_Size[lun]))
+    {
+      Counter = 0;
+      MAL_Write(lun ,
+                W_Offset - Mass_Block_Size[lun],
+                Data_Buffer,
+                Mass_Block_Size[lun]);
+    }
+
+    CSW.dDataResidue -= Data_Len;
+    SetEPRxStatus(ENDP2, EP_RX_VALID); /* enable the next transaction*/   
+  }
+
+  if ((W_Length == 0) || (Bot_State == BOT_CSW_Send))
+  {
+    Counter = 0;
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+    TransferState = TXFR_IDLE;
+  }
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/nand_if.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/nand_if.c
new file mode 100644
index 0000000..7139219
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/nand_if.c
@@ -0,0 +1,557 @@
+/**
+  ******************************************************************************
+  * @file    nand_if.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   manage NAND operations state machine
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+#include "platform_config.h"
+
+#ifdef USE_STM3210E_EVAL
+/* Includes ------------------------------------------------------------------*/
+#include "nand_if.h"
+#include "mass_mal.h"
+#include "fsmc_nand.h"
+#include "memory.h"
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* extern variables-----------------------------------------------------------*/
+extern uint32_t SCSI_LBA;
+extern uint32_t SCSI_BlkLen;
+/* Private variables ---------------------------------------------------------*/
+uint16_t LUT[1024]; //Look Up Table Buffer
+WRITE_STATE Write_State;
+BLOCK_STATE Block_State;
+NAND_ADDRESS wAddress, fAddress;
+uint16_t  phBlock, LogAddress, Initial_Page, CurrentZone = 0;
+uint16_t  Written_Pages = 0;
+
+uint16_t LUT[1024]; //Look Up Table Buffer
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static uint16_t NAND_CleanLUT(uint8_t ZoneNbr);
+static NAND_ADDRESS NAND_GetAddress(uint32_t Address);
+static uint16_t NAND_GetFreeBlock(void);
+static uint16_t NAND_Write_Cleanup(void);
+SPARE_AREA ReadSpareArea(uint32_t address);
+static uint16_t NAND_Copy(NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint16_t PageToCopy);
+static NAND_ADDRESS NAND_ConvertPhyAddress(uint32_t Address);
+static uint16_t NAND_BuildLUT(uint8_t ZoneNbr);
+
+/*******************************************************************************
+* Function Name  : NAND_Init
+* Description    : Init NAND Interface
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Init(void)
+{
+  uint16_t Status = NAND_OK;
+
+  FSMC_NAND_Init();
+  Status = NAND_BuildLUT(0);
+  Write_State = WRITE_IDLE;
+  return Status;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Write
+* Description    : write one sector by once
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Write(uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length)
+{
+  /* check block status and calculate start and end addresses */
+  wAddress    = NAND_GetAddress(Memory_Offset / 512);
+
+  /*check Zone: if second zone is requested build second LUT*/
+  if (wAddress.Zone != CurrentZone)
+  {
+    CurrentZone = wAddress.Zone;
+    NAND_BuildLUT(CurrentZone);
+  }
+
+  phBlock     = LUT[wAddress.Block]; /* Block Index + flags */
+  LogAddress  = wAddress.Block ; /* save logical block */
+
+  /*  IDLE state  */
+  /****************/
+  if ( Write_State == WRITE_IDLE)
+  {/* Idle state */
+
+    if (phBlock & USED_BLOCK)
+    { /* USED BLOCK */
+
+      Block_State = OLD_BLOCK;
+      /* Get a free Block for swap */
+      fAddress.Block = NAND_GetFreeBlock();
+      fAddress.Zone  = wAddress.Zone;
+      Initial_Page = fAddress.Page  = wAddress.Page;
+
+      /* write the new page */
+      FSMC_NAND_WriteSmallPage((uint8_t *)Writebuff, fAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+
+      /* get physical block */
+      wAddress.Block = phBlock & 0x3FF;
+
+
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+        return NAND_OK;
+      }
+      else
+      {
+        if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+        {
+          NAND_Write_Cleanup();
+          return NAND_OK;
+        }
+        Write_State = WRITE_ONGOING;
+        return NAND_OK;
+      }
+    }
+    else
+    {/* UNUSED BLOCK */
+
+      Block_State = UNUSED_BLOCK;
+      /* write the new page */
+      wAddress.Block = phBlock & 0x3FF;
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Written_Pages = 0;
+        NAND_Write_Cleanup();
+        return NAND_OK;
+      }
+      else
+      {
+        Write_State = WRITE_ONGOING;
+        return NAND_OK;
+      }
+    }
+  }
+  /* WRITE state */
+  /***************/
+  if ( Write_State == WRITE_ONGOING)
+  {/* Idle state */
+    if (phBlock & USED_BLOCK)
+    { /* USED BLOCK */
+
+      wAddress.Block = phBlock & 0x3FF;
+      Block_State = OLD_BLOCK;
+      fAddress.Page  = wAddress.Page;
+
+      /* check if next pages are in next block */
+      if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+      {
+        /* write Last page  */
+        FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , fAddress, PAGE_TO_WRITE);
+        Written_Pages++;
+        if (Written_Pages == SCSI_BlkLen)
+        {
+          Written_Pages = 0;
+        }
+        /* Clean up and Update the LUT */
+        NAND_Write_Cleanup();
+        Write_State = WRITE_IDLE;
+        return NAND_OK;
+      }
+
+      /* write next page */
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , fAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Write_State = WRITE_IDLE;
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+      }
+
+    }
+    else
+    {/* UNUSED BLOCK */
+      wAddress.Block = phBlock & 0x3FF;
+      /* check if it is the last page in prev block */
+      if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+      {
+        /* write Last page  */
+        FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+        Written_Pages++;
+        if (Written_Pages == SCSI_BlkLen)
+        {
+          Written_Pages = 0;
+        }
+
+        /* Clean up and Update the LUT */
+        NAND_Write_Cleanup();
+        Write_State = WRITE_IDLE;
+
+
+
+        return NAND_OK;
+      }
+      /* write next page in same block */
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Write_State = WRITE_IDLE;
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+      }
+    }
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Read(uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length)
+{
+  NAND_ADDRESS phAddress;
+
+  phAddress = NAND_GetAddress(Memory_Offset / 512);
+
+  if (phAddress.Zone != CurrentZone)
+  {
+    CurrentZone = phAddress.Zone;
+    NAND_BuildLUT(CurrentZone);
+  }
+
+  if (LUT [phAddress.Block] & BAD_BLOCK)
+  {
+    return NAND_FAIL;
+  }
+  else
+  {
+    phAddress.Block = LUT [phAddress.Block] & ~ (USED_BLOCK | VALID_BLOCK);
+    FSMC_NAND_ReadSmallPage ( (uint8_t *)Readbuff , phAddress, Transfer_Length / 512);
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_CleanLUT
+* Description    : Erase old blocks & rebuild the look up table
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_CleanLUT (uint8_t ZoneNbr)
+{
+#ifdef WEAR_LEVELLING_SUPPORT
+  uint16_t BlockIdx, LUT_Item;
+#endif
+  /* Rebuild the LUT for the current zone */
+  NAND_BuildLUT (ZoneNbr);
+
+#ifdef WEAR_LEVELLING_SUPPORT
+  /* Wear Leveling : circular use of free blocks */
+  LUT_Item = LUT [BlockIdx]
+             for (BlockIdx == MAX_LOG_BLOCKS_PER_ZONE ; BlockIdx < MAX_LOG_BLOCKS_PER_ZONE + WEAR_DEPTH ; BlockIdx++)
+             {
+               LUT [BlockIdx] = LUT [BlockIdx + 1];
+             }
+             LUT [ MAX_LOG_BLOCKS_PER_ZONE + WEAR_DEPTH - 1] = LUT_Item ;
+#endif
+
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_GetAddress
+* Description    : Translate logical address into a phy one
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static NAND_ADDRESS NAND_GetAddress (uint32_t Address)
+{
+  NAND_ADDRESS Address_t;
+
+  Address_t.Page  = Address & (NAND_BLOCK_SIZE - 1);
+  Address_t.Block = Address / NAND_BLOCK_SIZE;
+  Address_t.Zone = 0;
+
+  while (Address_t.Block >= MAX_LOG_BLOCKS_PER_ZONE)
+  {
+    Address_t.Block -= MAX_LOG_BLOCKS_PER_ZONE;
+    Address_t.Zone++;
+  }
+  return Address_t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_GetFreeBlock
+* Description    : Look for a free block for data exchange
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_GetFreeBlock (void)
+{
+  return LUT[MAX_LOG_BLOCKS_PER_ZONE]& ~(USED_BLOCK | VALID_BLOCK);
+}
+
+/*******************************************************************************
+* Function Name  : ReadSpareArea
+* Description    : Check used block
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+SPARE_AREA ReadSpareArea (uint32_t address)
+{
+  SPARE_AREA t;
+  uint8_t Buffer[16];
+  NAND_ADDRESS address_s;
+  address_s = NAND_ConvertPhyAddress(address);
+  FSMC_NAND_ReadSpareArea(Buffer , address_s, 1) ;
+
+  t = *(SPARE_AREA *)Buffer;
+
+  return t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Copy
+* Description    : Copy page
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_Copy (NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint16_t PageToCopy)
+{
+  uint8_t Copybuff[512];
+  for ( ; PageToCopy > 0 ; PageToCopy-- )
+  {
+    FSMC_NAND_ReadSmallPage  ((uint8_t *)Copybuff, Address_Src , 1 );
+    FSMC_NAND_WriteSmallPage ((uint8_t *)Copybuff, Address_Dest, 1);
+    FSMC_NAND_AddressIncrement(&Address_Src);
+    FSMC_NAND_AddressIncrement(&Address_Dest);
+  }
+
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Format
+* Description    : Format the entire NAND flash
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Format (void)
+{
+  NAND_ADDRESS phAddress;
+  SPARE_AREA  SpareArea;
+  uint32_t BlockIndex;
+
+  for (BlockIndex = 0 ; BlockIndex < NAND_ZONE_SIZE * NAND_MAX_ZONE; BlockIndex++)
+  {
+    phAddress = NAND_ConvertPhyAddress(BlockIndex * NAND_BLOCK_SIZE );
+    SpareArea = ReadSpareArea(BlockIndex * NAND_BLOCK_SIZE);
+   
+    if((SpareArea.DataStatus != 0)||(SpareArea.BlockStatus != 0)){
+        FSMC_NAND_EraseBlock (phAddress);
+    }  
+  }
+  NAND_BuildLUT(0);
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Write_Cleanup
+* Description    : None
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_Write_Cleanup (void)
+{
+  uint16_t  tempSpareArea [8];
+  uint16_t  Page_Back;
+
+  if ( Block_State == OLD_BLOCK )
+  {
+    /* precopy old first pages */
+    if (Initial_Page != 0)
+    {
+      Page_Back = wAddress.Page;
+      fAddress.Page = wAddress.Page = 0;
+      NAND_Copy (wAddress, fAddress, Initial_Page);
+      wAddress.Page =  Page_Back ;
+    }
+
+    /* postcopy remaining pages */
+    if ((NAND_BLOCK_SIZE - (wAddress.Page + 1)) != 0)
+    {
+      FSMC_NAND_AddressIncrement(&wAddress);
+      fAddress.Page = wAddress.Page;
+      NAND_Copy (wAddress, fAddress, NAND_BLOCK_SIZE - wAddress.Page);
+    }
+
+    /* assign logical address to new block */
+    tempSpareArea [0] = LogAddress | USED_BLOCK ;
+    tempSpareArea [1] = 0xFFFF;
+    tempSpareArea [2] = 0xFFFF;
+
+    fAddress.Page     = 0x00;
+    FSMC_NAND_WriteSpareArea( (uint8_t *)tempSpareArea , fAddress , 1);
+
+    /* erase old block */
+    FSMC_NAND_EraseBlock(wAddress);
+    NAND_CleanLUT(wAddress.Zone);
+  }
+  else
+  {/* unused block case */
+    /* assign logical address to the new used block */
+    tempSpareArea [0] = LogAddress | USED_BLOCK ;
+    tempSpareArea [1] = 0xFFFF;
+    tempSpareArea [2] = 0xFFFF;
+
+    wAddress.Page     = 0x00;
+    FSMC_NAND_WriteSpareArea((uint8_t *)tempSpareArea , wAddress, 1);
+    NAND_CleanLUT(wAddress.Zone);
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_ConvertPhyAddress
+* Description    : None
+* Input          : physical Address
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static NAND_ADDRESS NAND_ConvertPhyAddress (uint32_t Address)
+{
+  NAND_ADDRESS Address_t;
+
+  Address_t.Page  = Address & (NAND_BLOCK_SIZE - 1);
+  Address_t.Block = Address / NAND_BLOCK_SIZE;
+  Address_t.Zone = 0;
+
+  while (Address_t.Block >= MAX_PHY_BLOCKS_PER_ZONE)
+  {
+    Address_t.Block -= MAX_PHY_BLOCKS_PER_ZONE;
+    Address_t.Zone++;
+  }
+  return Address_t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_BuildLUT
+* Description    : Build the look up table
+* Input          : None
+* Output         : None
+* Return         : Status
+* !!!! NOTE : THIS ALGORITHM IS A SUBJECT OF PATENT FOR STMICROELECTRONICS !!!!!
+*******************************************************************************/
+static uint16_t NAND_BuildLUT (uint8_t ZoneNbr)
+{
+
+  uint16_t  pBadBlock, pCurrentBlock, pFreeBlock;
+  SPARE_AREA  SpareArea;
+  /*****************************************************************************
+                                  1st step : Init.
+  *****************************************************************************/
+  /*Init the LUT (assume all blocks free) */
+  for (pCurrentBlock = 0 ; pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE ; pCurrentBlock++)
+  {
+    LUT[pCurrentBlock] = FREE_BLOCK;  /* 12th bit is set to 1 */
+  }
+
+  /* Init Pointers */
+  pBadBlock    = MAX_PHY_BLOCKS_PER_ZONE - 1;
+  pCurrentBlock = 0;
+
+  /*****************************************************************************
+                         2nd step : locate used and bad blocks
+  *****************************************************************************/
+
+  while (pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE)
+  {
+
+    SpareArea = ReadSpareArea(pCurrentBlock * NAND_BLOCK_SIZE + (ZoneNbr * NAND_BLOCK_SIZE * MAX_PHY_BLOCKS_PER_ZONE));
+
+    if ((SpareArea.DataStatus == 0) || (SpareArea.BlockStatus == 0))
+    {
+
+      LUT[pBadBlock--]    |= pCurrentBlock | (uint16_t)BAD_BLOCK ;
+      LUT[pCurrentBlock] &= (uint16_t)~FREE_BLOCK;
+      if (pBadBlock == MAX_LOG_BLOCKS_PER_ZONE)
+      {
+        return NAND_FAIL;
+      }
+    }
+    else if (SpareArea.LogicalIndex != 0xFFFF)
+    {
+
+      LUT[SpareArea.LogicalIndex & 0x3FF] |= pCurrentBlock | VALID_BLOCK | USED_BLOCK;
+      LUT[pCurrentBlock] &= (uint16_t)( ~FREE_BLOCK);
+    }
+    pCurrentBlock++ ;
+  }
+
+  /*****************************************************************************
+     3rd step : locate Free Blocks by scanning the LUT already built partially
+  *****************************************************************************/
+  pFreeBlock = 0;
+  for (pCurrentBlock = 0 ; pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE ; pCurrentBlock++ )
+  {
+
+    if ( !(LUT[pCurrentBlock]& USED_BLOCK))
+    {
+      do
+      {
+        if (LUT[pFreeBlock] & FREE_BLOCK)
+        {
+
+          LUT [pCurrentBlock] |= pFreeBlock;
+          LUT [pFreeBlock]   &= ~FREE_BLOCK;
+          break;
+        }
+        pFreeBlock++;
+      }
+      while ( pFreeBlock < MAX_PHY_BLOCKS_PER_ZONE );
+    }
+  }
+  return NAND_OK;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/scsi_data.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/scsi_data.c
new file mode 100644
index 0000000..9979d19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/scsi_data.c
@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    scsi_data.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Initialization of the SCSI data
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_scsi.h"
+#include "memory.h"
+
+
+uint8_t Page00_Inquiry_Data[] =
+  {
+    0x00, /* PERIPHERAL QUALIFIER & PERIPHERAL DEVICE TYPE*/
+    0x00,
+    0x00,
+    0x00,
+    0x00 /* Supported Pages 00*/
+  };
+uint8_t Standard_Inquiry_Data[] =
+  {
+    0x00,          /* Direct Access Device */
+    0x80,          /* RMB = 1: Removable Medium */
+    0x02,          /* Version: No conformance claim to standard */
+    0x02,
+
+    36 - 4,          /* Additional Length */
+    0x00,          /* SCCS = 1: Storage Controller Component */
+    0x00,
+    0x00,
+    /* Vendor Identification */
+    'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ',
+    /* Product Identification */
+    'S', 'D', ' ', 'F', 'l', 'a', 's', 'h', ' ',
+    'D', 'i', 's', 'k', ' ', ' ', ' ',
+    /* Product Revision Level */
+    '1', '.', '0', ' '
+  };
+uint8_t Standard_Inquiry_Data2[] =
+  {
+    0x00,          /* Direct Access Device */
+    0x80,          /* RMB = 1: Removable Medium */
+    0x02,          /* Version: No conformance claim to standard */
+    0x02,
+
+    36 - 4,          /* Additional Length */
+    0x00,          /* SCCS = 1: Storage Controller Component */
+    0x00,
+    0x00,
+    /* Vendor Identification */
+    'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ',
+    /* Product Identification */
+    'N', 'A', 'N', 'D', ' ', 'F', 'l', 'a', 's', 'h', ' ',
+    'D', 'i', 's', 'k', ' ',
+    /* Product Revision Level */
+    '1', '.', '0', ' '
+  };
+/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+uint8_t Mode_Sense6_data[] =
+  {
+    0x03,
+    0x00,
+    0x00,
+    0x00,
+  };
+
+/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+
+uint8_t Mode_Sense10_data[] =
+  {
+    0x00,
+    0x06,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00
+  };
+uint8_t Scsi_Sense_Data[] =
+  {
+    0x70, /*RespCode*/
+    0x00, /*SegmentNumber*/
+    NO_SENSE, /* Sens_Key*/
+    0x00,
+    0x00,
+    0x00,
+    0x00, /*Information*/
+    0x0A, /*AdditionalSenseLength*/
+    0x00,
+    0x00,
+    0x00,
+    0x00, /*CmdInformation*/
+    NO_SENSE, /*Asc*/
+    0x00, /*ASCQ*/
+    0x00, /*FRUC*/
+    0x00, /*TBD*/
+    0x00,
+    0x00 /*SenseKeySpecific*/
+  };
+uint8_t ReadCapacity10_Data[] =
+  {
+    /* Last Logical Block */
+    0,
+    0,
+    0,
+    0,
+
+    /* Block Length */
+    0,
+    0,
+    0,
+    0
+  };
+
+uint8_t ReadFormatCapacity_Data [] =
+  {
+    0x00,
+    0x00,
+    0x00,
+    0x08, /* Capacity List Length */
+
+    /* Block Count */
+    0,
+    0,
+    0,
+    0,
+
+    /* Block Length */
+    0x02,/* Descriptor Code: Formatted Media */
+    0,
+    0,
+    0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/stm32_it.c
new file mode 100644
index 0000000..a2ee2d8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/stm32_it.c
@@ -0,0 +1,426 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32_it.h"
+#include "usb_istr.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint8_t Send_Buffer[2];
+extern __IO uint8_t PrevXferComplete;
+extern uint32_t ADC_ConvertedValueX;
+extern uint32_t ADC_ConvertedValueX_1;
+extern __IO uint32_t TimingDelay;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+    TimingDelay--;
+}
+
+/******************************************************************************/
+/*            STM32 Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined (STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+#if defined(STM32L1XX_MD)
+/*******************************************************************************
+* Function Name  : EXTI15_10_IRQHandler
+* Description    : This function handles External lines 15 to 10 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI15_10_IRQHandler(void)
+{
+  /* Check on the RIGHT button */
+  if(EXTI_GetITStatus(RIGHT_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x05; 
+      
+      if (STM_EVAL_PBGetState(Button_RIGHT) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      
+      SetEPTxValid(ENDP1);
+      
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(RIGHT_BUTTON_EXTI_LINE);
+  }  
+
+  /* Check on the LEFT button */
+  if(EXTI_GetITStatus(LEFT_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x06; 
+      
+      if (STM_EVAL_PBGetState(Button_LEFT) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      
+      SetEPTxValid(ENDP1);
+      
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(LEFT_BUTTON_EXTI_LINE);
+  }  
+}
+#endif
+/*******************************************************************************
+* Function Name  : DMA1_Channel1_IRQHandler
+* Description    : This function handles DMA1 Channel 1 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA1_Channel1_IRQHandler(void)
+{  
+  Send_Buffer[0] = 0x07;
+  
+  if((ADC_ConvertedValueX >>4) - (ADC_ConvertedValueX_1 >>4) > 4)
+  {
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[1] = (uint8_t)(ADC_ConvertedValueX >>4);
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      SetEPTxValid(ENDP1);
+      ADC_ConvertedValueX_1 = ADC_ConvertedValueX;
+      PrevXferComplete = 0;
+    }
+  }
+  
+  DMA_ClearFlag(DMA1_FLAG_TC1);
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_IRQHandler
+* Description    : This function handles External lines interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void EXTI0_IRQHandler(void)
+#elif defined (STM32F37X)
+void EXTI2_TS_IRQHandler(void)
+#else
+void EXTI9_5_IRQHandler(void)
+#endif
+{
+  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x05; 
+#if defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+      if (!STM_EVAL_PBGetState(Button_KEY) == Bit_RESET)
+#else
+      if (STM_EVAL_PBGetState(Button_KEY) == Bit_RESET)       
+#endif      
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      SetEPTxValid(ENDP1);
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  }
+}
+#if !defined(STM32L1XX_MD) &&  !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)&& ! defined (STM32F37X) && ! defined (STM32F30X)
+/*******************************************************************************
+* Function Name  : EXTI15_10_IRQHandler
+* Description    : This function handles External lines 15 to 10 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI15_10_IRQHandler(void)
+{
+  if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x06;
+      
+      if (STM_EVAL_PBGetState(Button_TAMPER) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }
+      
+      /* Write the descriptor through the endpoint */    
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+     
+      SetEPTxValid(ENDP1);
+
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line 13 pending bit */
+    EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE);
+  }
+}
+
+#endif /*STM32L1XX_HD*/
+
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+/*******************************************************************************
+* Function Name  : SDIO_IRQHandler
+* Description    : This function handles SDIO global interrupt request.
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SDIO_IRQHandler(void)
+{ 
+  /* Process All SDIO Interrupt Sources */
+  SD_ProcessIRQSrc();
+  
+}
+
+void SD_SDIO_DMA_IRQHANDLER(void)
+{
+  /* Process DMA2 Stream3 or DMA2 Stream6 Interrupt Sources */
+  SD_ProcessDMAIRQ();
+}
+
+#endif /* STM32F10X_HD | STM32F10X_XL*/
+
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f10x.c
new file mode 100644
index 0000000..3686a2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f10x.c
@@ -0,0 +1,917 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_XX */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+           
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_XX */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+        
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+       
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f30x.c
new file mode 100644
index 0000000..31faf5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F30x devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f30x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f30x.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F30x device                          
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F30x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f30x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+  * @{
+  */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F30x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 72000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_bot.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_bot.c
new file mode 100644
index 0000000..5773bac
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_bot.c
@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file    usb_bot.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   BOT State Machine management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_scsi.h"
+#include "hw_config.h"
+#include "usb_regs.h"
+#include "usb_mem.h"
+#include "usb_conf.h"
+#include "usb_bot.h"
+#include "memory.h"
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t Bot_State;
+uint8_t Bulk_Data_Buff[64];  /* data buffer*/
+uint16_t Data_Len;
+Bulk_Only_CBW CBW;
+Bulk_Only_CSW CSW;
+uint32_t SCSI_LBA , SCSI_BlkLen;
+extern uint32_t Max_Lun;
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_In
+* Description    : Mass Storage IN transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_In (void)
+{
+  switch (Bot_State)
+  {
+    case BOT_CSW_Send:
+    case BOT_ERROR:
+      Bot_State = BOT_IDLE;
+      SetEPRxStatus(ENDP2, EP_RX_VALID);/* enable the Endpoint to receive the next cmd*/
+      if (GetEPRxStatus(EP2_OUT) == EP_RX_STALL)
+      {
+        SetEPRxStatus(EP2_OUT, EP_RX_VALID);/* enable the Endpoint to receive the next cmd*/
+      }
+      break;
+    case BOT_DATA_IN:
+      switch (CBW.CB[0])
+      {
+        case SCSI_READ10:
+          SCSI_Read10_Cmd(CBW.bLUN , SCSI_LBA , SCSI_BlkLen);
+          break;
+      }
+      break;
+    case BOT_DATA_IN_LAST:
+      Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+
+      SetEPRxStatus(ENDP2, EP_RX_VALID);
+      break;
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_Out
+* Description    : Mass Storage OUT transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_Out (void)
+{
+  uint8_t CMD;
+  CMD = CBW.CB[0];
+
+  Data_Len = USB_SIL_Read(EP2_OUT, Bulk_Data_Buff);
+
+  switch (Bot_State)
+  {
+    case BOT_IDLE:
+      CBW_Decode();
+      break;
+    case BOT_DATA_OUT:
+      if (CMD == SCSI_WRITE10)
+      {
+        SCSI_Write10_Cmd(CBW.bLUN , SCSI_LBA , SCSI_BlkLen);
+        break;
+      }
+      Bot_Abort(DIR_OUT);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_PHASE_ERROR, SEND_CSW_DISABLE);
+      break;
+    default:
+      Bot_Abort(BOTH_DIR);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_PHASE_ERROR, SEND_CSW_DISABLE);
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CBW_Decode
+* Description    : Decode the received CBW and call the related SCSI command
+*                 routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CBW_Decode(void)
+{
+  uint32_t Counter;
+
+  for (Counter = 0; Counter < Data_Len; Counter++)
+  {
+    *((uint8_t *)&CBW + Counter) = Bulk_Data_Buff[Counter];
+  }
+  CSW.dTag = CBW.dTag;
+  CSW.dDataResidue = CBW.dDataLength;
+  if (Data_Len != BOT_CBW_PACKET_LENGTH)
+  {
+    Bot_Abort(BOTH_DIR);
+    /* reset the CBW.dSignature to disable the clear feature until receiving a Mass storage reset*/
+    CBW.dSignature = 0;
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, PARAMETER_LIST_LENGTH_ERROR);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    return;
+  }
+
+  if ((CBW.CB[0] == SCSI_READ10 ) || (CBW.CB[0] == SCSI_WRITE10 ))
+  {
+    /* Calculate Logical Block Address */
+    SCSI_LBA = (CBW.CB[2] << 24) | (CBW.CB[3] << 16) | (CBW.CB[4] <<  8) | CBW.CB[5];
+    /* Calculate the Number of Blocks to transfer */
+    SCSI_BlkLen = (CBW.CB[7] <<  8) | CBW.CB[8];
+  }
+
+  if (CBW.dSignature == BOT_CBW_SIGNATURE)
+  {
+    /* Valid CBW */
+    if ((CBW.bLUN > Max_Lun) || (CBW.bCBLength < 1) || (CBW.bCBLength > 16))
+    {
+      Bot_Abort(BOTH_DIR);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    }
+    else
+    {
+      switch (CBW.CB[0])
+      {
+        case SCSI_REQUEST_SENSE:
+          SCSI_RequestSense_Cmd (CBW.bLUN);
+          break;
+        case SCSI_INQUIRY:
+          SCSI_Inquiry_Cmd(CBW.bLUN);
+          break;
+        case SCSI_START_STOP_UNIT:
+          SCSI_Start_Stop_Unit_Cmd(CBW.bLUN);
+          break;
+        case SCSI_ALLOW_MEDIUM_REMOVAL:
+          SCSI_Start_Stop_Unit_Cmd(CBW.bLUN);
+          break;
+        case SCSI_MODE_SENSE6:
+          SCSI_ModeSense6_Cmd (CBW.bLUN);
+          break;
+        case SCSI_MODE_SENSE10:
+          SCSI_ModeSense10_Cmd (CBW.bLUN);
+          break;
+        case SCSI_READ_FORMAT_CAPACITIES:
+          SCSI_ReadFormatCapacity_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ_CAPACITY10:
+          SCSI_ReadCapacity10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_TEST_UNIT_READY:
+          SCSI_TestUnitReady_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ10:
+          SCSI_Read10_Cmd(CBW.bLUN, SCSI_LBA , SCSI_BlkLen);
+          break;
+        case SCSI_WRITE10:
+          SCSI_Write10_Cmd(CBW.bLUN, SCSI_LBA , SCSI_BlkLen);
+          break;
+        case SCSI_VERIFY10:
+          SCSI_Verify10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_FORMAT_UNIT:
+          SCSI_Format_Cmd(CBW.bLUN);
+          break;
+          /*Unsupported command*/
+        case SCSI_MODE_SELECT10:
+          SCSI_Mode_Select10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_MODE_SELECT6:
+          SCSI_Mode_Select6_Cmd(CBW.bLUN);
+          break;
+
+        case SCSI_SEND_DIAGNOSTIC:
+          SCSI_Send_Diagnostic_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ6:
+          SCSI_Read6_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ12:
+          SCSI_Read12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ16:
+          SCSI_Read16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ_CAPACITY16:
+          SCSI_READ_CAPACITY16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE6:
+          SCSI_Write6_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE12:
+          SCSI_Write12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE16:
+          SCSI_Write16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_VERIFY12:
+          SCSI_Verify12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_VERIFY16:
+          SCSI_Verify16_Cmd(CBW.bLUN);
+          break;
+
+        default:
+        {
+          Bot_Abort(BOTH_DIR);
+          Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+          Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Invalid CBW */
+    Bot_Abort(BOTH_DIR);
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Transfer_Data_Request
+* Description    : Send the request response to the PC HOST.
+* Input          : uint8_t* Data_Address : point to the data to transfer.
+*                  uint16_t Data_Length : the number of Bytes to transfer.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Transfer_Data_Request(uint8_t* Data_Pointer, uint16_t Data_Len)
+{
+  USB_SIL_Write(EP2_IN, Data_Pointer, Data_Len);
+
+    SetEPTxStatus(ENDP2, EP_TX_VALID);
+    
+  Bot_State = BOT_DATA_IN_LAST;
+  CSW.dDataResidue -= Data_Len;
+  CSW.bStatus = CSW_CMD_PASSED;
+}
+
+/*******************************************************************************
+* Function Name  : Set_CSW
+* Description    : Set the SCW with the needed fields.
+* Input          : uint8_t CSW_Status this filed can be CSW_CMD_PASSED,CSW_CMD_FAILED,
+*                  or CSW_PHASE_ERROR.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Set_CSW (uint8_t CSW_Status, uint8_t Send_Permission)
+{
+  CSW.dSignature = BOT_CSW_SIGNATURE;
+  CSW.bStatus = CSW_Status;
+
+  USB_SIL_Write(EP2_IN, ((uint8_t *)& CSW), CSW_DATA_LENGTH);
+
+  Bot_State = BOT_ERROR;
+  if (Send_Permission)
+  {
+    Bot_State = BOT_CSW_Send;
+    SetEPTxStatus(ENDP2, EP_TX_VALID);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Bot_Abort
+* Description    : Stall the needed Endpoint according to the selected direction.
+* Input          : Endpoint direction IN, OUT or both directions
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Bot_Abort(uint8_t Direction)
+{
+  switch (Direction)
+  {
+    case DIR_IN :
+      SetEPTxStatus(ENDP2, EP_TX_STALL);
+      break;
+    case DIR_OUT :
+      SetEPRxStatus(ENDP2, EP_RX_STALL);
+      break;
+    case BOTH_DIR :
+      SetEPTxStatus(ENDP2, EP_TX_STALL);
+      SetEPRxStatus(ENDP2, EP_RX_STALL);
+      break;
+    default:
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_desc.c
new file mode 100644
index 0000000..5e1b127
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_desc.c
@@ -0,0 +1,299 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Custom HID Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* USB Standard Device Descriptor */
+const uint8_t Composite_DeviceDescriptor[Composite_SIZ_DEVICE_DESC] =
+  {
+    0x12,                       /*bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
+    0x00,                       /*bcdUSB */
+    0x02,
+    0x00,                       /*bDeviceClass*/
+    0x00,                       /*bDeviceSubClass*/
+    0x00,                       /*bDeviceProtocol*/
+    0x40,                       /*bMaxPacketSize40*/
+    0x83,                       /*idVendor (0x0483)*/
+    0x04, 
+    0x50,                       /*idProduct = 0x5750*/
+    0x57,
+    0x00,                       /*bcdDevice rel. 2.00*/
+    0x02,
+    1,                          /*Index of string descriptor describing
+                                              manufacturer */
+    2,                          /*Index of string descriptor describing
+                                             product*/
+    3,                          /*Index of string descriptor describing the
+                                             device serial number */
+    0x01                        /*bNumConfigurations*/
+  }
+  ; /* Composite_DeviceDescriptor */
+
+
+/* USB Configuration Descriptor */
+/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t Composite_ConfigDescriptor[Composite_SIZ_CONFIG_DESC] =
+  {
+    0x09, /* bLength: Configuration Descriptor size */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
+    Composite_SIZ_CONFIG_DESC,
+    /* wTotalLength: Bytes returned */
+    0x00,
+    0x02,         /* bNumInterfaces: 2 interfaces */
+    0x01,         /* bConfigurationValue: Configuration value */
+    0x00,         /* iConfiguration: Index of string descriptor describing
+                                 the configuration*/
+    0xC0,         /* bmAttributes: Self powered */
+    0x32,         /* MaxPower 100 mA: this current is used for detecting Vbus */
+
+    /************** Descriptor of Custom HID interface ****************/
+    /* 09 */
+    0x09,         /* bLength: Interface Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,/* bDescriptorType: Interface descriptor type */
+    0x00,         /* bInterfaceNumber: Number of Interface */
+    0x00,         /* bAlternateSetting: Alternate setting */
+    0x02,         /* bNumEndpoints */
+    0x03,         /* bInterfaceClass: HID */
+    0x00,         /* bInterfaceSubClass : 1=BOOT, 0=no boot */
+    0x00,         /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
+    0,            /* iInterface: Index of string descriptor */
+    /******************** Descriptor of Custom HID HID ********************/
+    /* 18 */
+    0x09,         /* bLength: HID Descriptor size */
+    HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
+    0x10,         /* bcdHID: HID Class Spec release number */
+    0x01,
+    0x00,         /* bCountryCode: Hardware target country */
+    0x01,         /* bNumDescriptors: Number of HID class descriptors to follow */
+    0x22,         /* bDescriptorType */
+    CUSTOMHID_SIZ_REPORT_DESC,/* wItemLength: Total length of Report descriptor */
+    0x00,
+    /******************** Descriptor of Custom HID endpoints ******************/
+    /* 27 */
+    0x07,          /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
+
+    0x81,          /* bEndpointAddress: Endpoint Address (IN) */
+    0x03,          /* bmAttributes: Interrupt endpoint */
+    0x02,          /* wMaxPacketSize: 2 Bytes max */
+    0x00,
+    0x20,          /* bInterval: Polling Interval (32 ms) */
+    /* 34 */
+    	
+    0x07,	/* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,	/* bDescriptorType: */
+			/*	Endpoint descriptor type */
+    0x01,	/* bEndpointAddress: */
+			/*	Endpoint Address (OUT) */
+    0x03,	/* bmAttributes: Interrupt endpoint */
+    0x02,	/* wMaxPacketSize: 2 Bytes max  */
+    0x00,
+    0x20,	/* bInterval: Polling Interval (20 ms) */
+    /* 41 */
+    /******************** Descriptor of Mass Storage interface ********************/
+    /* 09 */
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x01,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x02,   /* bNumEndpoints*/
+    0x08,   /* bInterfaceClass: MASS STORAGE Class */
+    0x06,   /* bInterfaceSubClass : SCSI transparent*/
+    0x50,   /* nInterfaceProtocol */
+    1,          /* iInterface: */
+    /* 18 */
+    0x07,   /*Endpoint descriptor length = 7*/
+    0x05,   /*Endpoint descriptor type */
+    0x82,   /*Endpoint address (IN, address 2) */
+    0x02,   /*Bulk endpoint type */
+    0x40,   /*Maximum packet size (64 bytes) */
+    0x00,
+    0x00,   /*Polling interval in milliseconds */
+    /* 25 */
+    0x07,   /*Endpoint descriptor length = 7 */
+    0x05,   /*Endpoint descriptor type */
+    0x02,   /*Endpoint address (OUT, address 2) */
+    0x02,   /*Bulk endpoint type */
+    0x40,   /*Maximum packet size (64 bytes) */
+    0x00,
+    0x00     /*Polling interval in milliseconds*/
+    /*32*/
+  }; /* Composite_ConfigDescriptor */
+const uint8_t CustomHID_ReportDescriptor[CUSTOMHID_SIZ_REPORT_DESC] =
+  {                    
+    0x06, 0xFF, 0x00,      /* USAGE_PAGE (Vendor Page: 0xFF00) */                       
+    0x09, 0x01,            /* USAGE (Demo Kit)               */    
+    0xa1, 0x01,            /* COLLECTION (Application)       */            
+    /* 6 */
+    
+    /* Led 1 */        
+    0x85, 0x01,            /*     REPORT_ID (1)		     */
+    0x09, 0x01,            /*     USAGE (LED 1)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x01,            /*     REPORT_ID (1)              */
+    0x09, 0x01,            /*     USAGE (LED 1)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 26 */
+    
+    /* Led 2 */
+    0x85, 0x02,            /*     REPORT_ID 2		     */
+    0x09, 0x02,            /*     USAGE (LED 2)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x02,            /*     REPORT_ID (2)              */
+    0x09, 0x02,            /*     USAGE (LED 2)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 46 */
+    
+    /* Led 3 */        
+    0x85, 0x03,            /*     REPORT_ID (3)		     */
+    0x09, 0x03,            /*     USAGE (LED 3)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x03,            /*     REPORT_ID (3)              */
+    0x09, 0x03,            /*     USAGE (LED 3)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 66 */
+    
+    /* key Push Button */  
+    0x85, 0x05,            /*     REPORT_ID (5)              */
+    0x09, 0x05,            /*     USAGE (Push Button)        */      
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */      
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */      
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */  
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */   
+    
+    0x09, 0x05,            /*     USAGE (Push Button)        */               
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */           
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */  
+         
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0x81, 0x83,            /*     INPUT (Cnst,Var,Abs,Vol)   */                    
+    0x85, 0x05,            /*     REPORT_ID (2)              */         
+                    
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0xb1, 0x83,            /*     FEATURE (Cnst,Var,Abs,Vol) */                      
+    /* 94 */
+
+    /* Tamper Push Button */  
+    0x85, 0x06,            /*     REPORT_ID (6)              */
+    0x09, 0x06,            /*     USAGE (Tamper Push Button) */      
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */      
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */      
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */  
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */   
+    
+    0x09, 0x06,            /*     USAGE (Tamper Push Button) */               
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */           
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */  
+         
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0x81, 0x83,            /*     INPUT (Cnst,Var,Abs,Vol)   */                    
+    0x85, 0x06,            /*     REPORT_ID (6)              */         
+                    
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0xb1, 0x83,            /*     FEATURE (Cnst,Var,Abs,Vol) */  
+    /* 122 */
+    
+    /* ADC IN */
+    0x85, 0x07,            /*     REPORT_ID (7)              */         
+    0x09, 0x07,            /*     USAGE (ADC IN)             */          
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */               
+    0x26, 0xff, 0x00,      /*     LOGICAL_MAXIMUM (255)      */                 
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */           
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */                    
+    0x85, 0x07,            /*     REPORT_ID (7)              */                 
+    0x09, 0x07,            /*     USAGE (ADC in)             */                     
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */                                 
+    /* 141 */
+
+    0xc0 	          /*     END_COLLECTION	             */
+  }; /* CustomHID_ReportDescriptor */
+
+/* USB String Descriptors (optional) */
+const uint8_t Composite_StringLangID[Composite_SIZ_STRING_LANGID] =
+  {
+    Composite_SIZ_STRING_LANGID,
+    USB_STRING_DESCRIPTOR_TYPE,
+    0x09,
+    0x04
+  }
+  ; /* LangID = 0x0409: U.S. English */
+
+const uint8_t Composite_StringVendor[Composite_SIZ_STRING_VENDOR] =
+  {
+    Composite_SIZ_STRING_VENDOR, /* Size of Vendor string */
+    USB_STRING_DESCRIPTOR_TYPE,  /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t Composite_StringProduct[Composite_SIZ_STRING_PRODUCT] =
+  {
+    Composite_SIZ_STRING_PRODUCT,          /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'C', 0,
+    'o', 0, 'm', 0, 'p', 0, 'o', 0, 's', 0, 'i', 0, 't', 0,
+    'e', 0,' ',0, 'M', 0, 'S', 0, 'C', 0, '+', 0, 'H', 0, 'I', 0, 'D', 0
+  };
+uint8_t Composite_StringSerial[Composite_SIZ_STRING_SERIAL] =
+  {
+    Composite_SIZ_STRING_SERIAL,           /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0,'3', 0,'2', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_endp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_endp.c
new file mode 100644
index 0000000..3344c23
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_endp.c
@@ -0,0 +1,159 @@
+/**
+  ******************************************************************************
+  * @file    usb_endp.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Endpoint routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_istr.h"
+#include "usb_bot.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t Receive_Buffer[2];
+extern __IO uint8_t PrevXferComplete;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : EP1_OUT_Callback.
+* Description    : EP1 OUT Callback Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP1_OUT_Callback(void)
+{
+  BitAction Led_State;
+
+  /* Read received data (2 bytes) */  
+  USB_SIL_Read(EP1_OUT, Receive_Buffer);
+  
+  if (Receive_Buffer[1] == 0)
+  {
+    Led_State = Bit_RESET;
+  }
+  else 
+  {
+    Led_State = Bit_SET;
+  }
+ 
+ 
+  switch (Receive_Buffer[0])
+  {
+    case 1: /* Led 1 */
+     if (Led_State != Bit_RESET)
+     {
+       STM_EVAL_LEDOn(LED1);
+     }
+     else
+     {
+       STM_EVAL_LEDOff(LED1);
+     }
+     break;
+    case 2: /* Led 2 */
+     if (Led_State != Bit_RESET)
+     {
+       STM_EVAL_LEDOn(LED2);
+     }
+     else
+     {
+       STM_EVAL_LEDOff(LED2);
+     }
+      break;
+    case 3: /* Led 3 */
+     if (Led_State != Bit_RESET)
+     {
+       STM_EVAL_LEDOn(LED3);
+     }
+     else
+     {
+       STM_EVAL_LEDOff(LED3);
+     }
+      break;
+    case 4: /* Led 4 */
+     if (Led_State != Bit_RESET)
+     {
+       STM_EVAL_LEDOn(LED4);
+     }
+     else
+     {
+       STM_EVAL_LEDOff(LED4);
+     }
+      break;
+  default:
+    STM_EVAL_LEDOff(LED1);
+    STM_EVAL_LEDOff(LED2);
+    STM_EVAL_LEDOff(LED3);
+    STM_EVAL_LEDOff(LED4); 
+    break;
+  }
+ 
+  SetEPRxStatus(ENDP1, EP_RX_VALID);
+ 
+}
+
+/*******************************************************************************
+* Function Name  : EP1_IN_Callback.
+* Description    : EP1 IN Callback Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP1_IN_Callback(void)
+{
+  PrevXferComplete = 1;
+}
+
+/*******************************************************************************
+* Function Name  : EP2_IN_Callback
+* Description    : EP2 IN Callback Routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP2_IN_Callback(void)
+{
+  Mass_Storage_In();
+}
+
+/*******************************************************************************
+* Function Name  : EP2_OUT_Callback.
+* Description    : EP2 OUT Callback Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP2_OUT_Callback(void)
+{
+  Mass_Storage_Out();
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_prop.c
new file mode 100644
index 0000000..446fa84
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_prop.c
@@ -0,0 +1,581 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processings related to Custom HID Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "hw_config.h" 
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "usb_bot.h"
+#include "memory.h"
+#include "mass_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t ProtocolValue;
+__IO uint8_t EXTI_Enable;
+__IO uint8_t Request = 0;
+uint8_t Report_Buf[2];   
+/* -------------------------------------------------------------------------- */
+/*  Structures initializations */
+/* -------------------------------------------------------------------------- */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    CustomHID_init,
+    CustomHID_Reset,
+    CustomHID_Status_In,
+    CustomHID_Status_Out,
+    CustomHID_Data_Setup,
+    CustomHID_NoData_Setup,
+    CustomHID_Get_Interface_Setting,
+    CustomHID_GetDeviceDescriptor,
+    CustomHID_GetConfigDescriptor,
+    CustomHID_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    CustomHID_GetConfiguration,
+    CustomHID_SetConfiguration,
+    CustomHID_GetInterface,
+    CustomHID_SetInterface,
+    CustomHID_GetStatus,
+    CustomHID_ClearFeature,
+    CustomHID_SetEndPointFeature,
+    CustomHID_SetDeviceFeature,
+    CustomHID_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)Composite_DeviceDescriptor,
+    Composite_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)Composite_ConfigDescriptor,
+    Composite_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR CustomHID_Report_Descriptor =
+  {
+    (uint8_t *)CustomHID_ReportDescriptor,
+    CUSTOMHID_SIZ_REPORT_DESC
+  };
+
+ONE_DESCRIPTOR CustomHID_Hid_Descriptor =
+  {
+    (uint8_t*)Composite_ConfigDescriptor + CUSTOMHID_OFF_HID_DESC,
+    CUSTOMHID_SIZ_HID_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+  {
+    {(uint8_t*)Composite_StringLangID, Composite_SIZ_STRING_LANGID},
+    {(uint8_t*)Composite_StringVendor, Composite_SIZ_STRING_VENDOR},
+    {(uint8_t*)Composite_StringProduct, Composite_SIZ_STRING_PRODUCT},
+    {(uint8_t*)Composite_StringSerial, Composite_SIZ_STRING_SERIAL}
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*CustomHID_SetReport_Feature function prototypes*/
+uint8_t *CustomHID_SetReport_Feature(uint16_t Length);
+
+extern unsigned char Bot_State;
+extern Bulk_Only_CBW CBW;
+uint32_t Max_Lun = 0; 
+
+
+/*******************************************************************************
+* Function Name  : Get_Max_Lun
+* Description    : Handle the Get Max Lun request.
+* Input          : uint16_t Length.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint8_t *Get_Max_Lun(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = LUN_DATA_LENGTH;
+    return 0;
+  }
+  else
+  {
+    return((uint8_t*)(&Max_Lun));
+  }
+}
+/*******************************************************************************
+* Function Name  : CustomHID_init.
+* Description    : Custom HID init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_init(void)
+{
+  /* Update the serial number string descriptor with the data from the unique 
+  ID*/
+  Get_SerialNum();
+    
+  pInformation->Current_Configuration = 0;
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Reset.
+* Description    : Custom HID reset routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Reset(void)
+{
+  /* Set Composite_DEVICE as not configured */
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Interface = 0;/*the default Interface*/
+  
+  /* Current Feature initialization */
+  pInformation->Current_Feature = Composite_ConfigDescriptor[7];
+ 
+  SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPRxAddr(ENDP1, ENDP1_RXADDR);
+  SetEPTxCount(ENDP1, 2);
+  SetEPRxCount(ENDP1, 2);
+  SetEPRxStatus(ENDP1, EP_RX_VALID);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  /* Initialize Endpoint 2 IN */
+  SetEPType(ENDP2, EP_BULK);
+  SetEPTxCount(ENDP1, 64);
+  SetEPTxAddr(ENDP2, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+  
+
+  /* Initialize Endpoint 2 OUT */
+  SetEPType(ENDP2, EP_BULK);
+  SetEPRxAddr(ENDP2, ENDP2_RXADDR);
+  SetEPRxCount(ENDP2, 64);
+  SetEPRxStatus(ENDP2, EP_RX_VALID);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+  CBW.dSignature = BOT_CBW_SIGNATURE;
+  Bot_State = BOT_IDLE;
+  bDeviceState = ATTACHED;
+}
+/*******************************************************************************
+* Function Name  : CustomHID_SetConfiguration.
+* Description    : Update the device state to configured and command the ADC 
+*                  conversion.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_SetConfiguration(void)
+{
+  if (pInformation->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+    
+    /* Start ADC Software Conversion */ 
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined(STM32F37X)
+    ADC_SoftwareStartConv(ADC1);
+#elif defined (STM32F30X)
+    ADC_StartConversion(ADC1);
+#else
+    ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+#endif /* STM32L1XX_XD */
+    ClearDTOG_TX(ENDP2);
+    ClearDTOG_RX(ENDP2);
+    Bot_State = BOT_IDLE; /* set the Bot state machine to the IDLE state */
+  }
+}
+/*******************************************************************************
+* Function Name  : CustomHID_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+/*******************************************************************************
+* Function Name  : CustomHID_Status_In.
+* Description    : Joystick status IN routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Status_In(void)
+{  
+  BitAction Led_State;
+  
+  if (Report_Buf[1] == 0)
+  {
+    Led_State = Bit_RESET;
+  }
+  else 
+  {
+    Led_State = Bit_SET;
+  }
+  
+  switch (Report_Buf[0])  
+  {
+    /*Change LED's status according to the host report*/
+    
+  case 1: /* Led 1 */ 
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED1);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED1);
+    }
+    break;
+  case 2:   /* Led 2 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED2);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED2);
+    }
+    break;
+  case 3:/* Led 3 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED3);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED3);
+    }
+    break;
+  case 4:/* Led 4 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED4);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED4);
+    }
+    break;
+  default:
+    STM_EVAL_LEDOff(LED1);
+    STM_EVAL_LEDOff(LED2);
+    STM_EVAL_LEDOff(LED3);
+    STM_EVAL_LEDOff(LED4); 
+    break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Status_Out
+* Description    : Joystick status OUT routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Status_Out (void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Data_Setup
+* Description    : Handle the data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+  
+  if (pInformation->USBwIndex != 0) 
+    return USB_UNSUPPORT;    
+  
+  CopyRoutine = NULL;
+  
+  if ((RequestNo == GET_DESCRIPTOR)
+      && (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+        )
+  {
+    
+    if (pInformation->USBwValue1 == REPORT_DESCRIPTOR)
+    {
+      CopyRoutine = CustomHID_GetReportDescriptor;
+    }
+    else if (pInformation->USBwValue1 == HID_DESCRIPTOR_TYPE)
+    {
+      CopyRoutine = CustomHID_GetHIDDescriptor;
+    }
+    
+  } /* End of GET_DESCRIPTOR */
+  
+  /*** GET_PROTOCOL, GET_REPORT, SET_REPORT ***/
+  else if ( (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) )
+  {         
+    switch( RequestNo )
+    {
+    case GET_PROTOCOL:
+      CopyRoutine = CustomHID_GetProtocolValue;
+      break;
+    case SET_REPORT:
+      CopyRoutine = CustomHID_SetReport_Feature;
+      Request = SET_REPORT;
+      break;
+    default:
+      break;
+    }
+  }
+  
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+  
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_SetReport_Feature
+* Description    : Set Feature request handling
+* Input          : Length.
+* Output         : None.
+* Return         : Buffer
+*******************************************************************************/
+uint8_t *CustomHID_SetReport_Feature(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 2;
+    return NULL;
+  }
+  else
+  {
+    return Report_Buf;
+  }
+}
+/*******************************************************************************
+* Function Name  : CustomHID_NoData_Setup
+* Description    : handle the no data class specific requests
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_NoData_Setup(uint8_t RequestNo)
+{
+  if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+      && (RequestNo == SET_PROTOCOL))
+  {
+    return CustomHID_SetProtocol();
+  }
+
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetConfigDescriptor.
+* Description    : Gets the configuration descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetStringDescriptor
+* Description    : Gets the string descriptors according to the needed index
+* Input          : Length
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *CustomHID_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else 
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetReportDescriptor.
+* Description    : Gets the HID report descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetReportDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &CustomHID_Report_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetHIDDescriptor.
+* Description    : Gets the HID descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetHIDDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &CustomHID_Hid_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Get_Interface_Setting.
+* Description    : tests the interface and the alternate setting according to the
+*                  supported one.
+* Input          : - Interface : interface number.
+*                  - AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT CustomHID_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_SetProtocol
+* Description    : Joystick Set Protocol request routine.
+* Input          : None.
+* Output         : None.
+* Return         : USB SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_SetProtocol(void)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  ProtocolValue = wValue0;
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetProtocolValue
+* Description    : get the protocol value
+* Input          : Length.
+* Output         : None.
+* Return         : address of the protocol value.
+*******************************************************************************/
+uint8_t *CustomHID_GetProtocolValue(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 1;
+    return NULL;
+  }
+  else
+  {
+    return (uint8_t *)(&ProtocolValue);
+  }
+}
+
+void CustomHID_ClearFeature (void)
+{
+    if (CBW.dSignature != BOT_CBW_SIGNATURE)
+    Bot_Abort(BOTH_DIR);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_pwr.c
new file mode 100644
index 0000000..a2253a8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Composite_Example/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewd
new file mode 100644
index 0000000..26ba5a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewp
new file mode 100644
index 0000000..68d30e9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.ewp
@@ -0,0 +1,6868 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xE	ST STM32F103xE</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F10X_HD</state>
+          <state>USE_STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <state>0</state>
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+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
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+          <name>IlinkProgramEntryLabelSelect</name>
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+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
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+          <state>0x11021</state>
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+          <state>1</state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <name>CrcFullSize</name>
+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
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+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
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+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      </data>
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+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
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+        <version>0</version>
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+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
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+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
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+          <state>STM32L152D-EVAL\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>STM32L152D-EVAL\Obj</state>
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+        <option>
+          <name>ListPath</name>
+          <state>STM32L152D-EVAL\List</state>
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+          <version>20</version>
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+          <state>Full formatting.</state>
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+          <version>2</version>
+          <state>1</state>
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+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
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+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>4.41A</state>
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+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xD	ST STM32L152xD</state>
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+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+          <state>1</state>
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+          <state>0</state>
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+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      <name>ICCARM</name>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
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+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32L1XX_HD</state>
+          <state>USE_STM32L152D_EVAL</state>
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+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
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+          <name>CCDebugInfo</name>
+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
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+          <state>0</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
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+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCRequirePrototypes</name>
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+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+        <option>
+          <name>PreInclude</name>
+          <state></state>
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+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL</state>
+        </option>
+        <option>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <state>3</state>
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+          <state>3</state>
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+          <name>IccLang</name>
+          <state>0</state>
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+          <name>IccCDialect</name>
+          <state>1</state>
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+          <name>IccAllowVLA</name>
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+          <state>1</state>
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+          <name>IccRTTI</name>
+          <state>1</state>
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+          <name>IccStaticDestr</name>
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+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32L152-EVAL_Custom_HID.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
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+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+      <archiveVersion>0</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
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+          <state>1</state>
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+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
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+          <name>IlinkOutputFile</name>
+          <state>Custom_HID.out</state>
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+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
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+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
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+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
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+          <name>IlinkIcfOverride</name>
+          <state>1</state>
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+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
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+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
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+          <name>IlinkExtraOptions</name>
+          <state></state>
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+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
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+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
+          <state></state>
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+          <state>0</state>
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+          <state>0</state>
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+          <state>__iar_program_start</state>
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+          <state>0x11021</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
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+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>ExePath</name>
+          <state>STM32373C_EVAL\Exe</state>
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+        <option>
+          <name>ObjPath</name>
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+          <name>ListPath</name>
+          <state>STM32373C_EVAL\List</state>
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+          <name>Input description</name>
+          <state>Full formatting.</state>
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+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
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+          <name>Output description</name>
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+          <state>1</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>4.41A</state>
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+          <name>OGLastSavedByProductVersion</name>
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+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F373xC	ST STM32F373xC</state>
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+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+          <state>1</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
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+      <name>ICCARM</name>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F37X</state>
+          <state>USE_STM32373C_EVAL</state>
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+          <name>CCPreprocFile</name>
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+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
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+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+          <name>CCDiagSuppress</name>
+          <state></state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+        <option>
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+        <option>
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+          <version>1</version>
+          <state>1111111</state>
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IProcessor</name>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
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+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCMultibyteSupport</name>
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+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
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+        <option>
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+        <option>
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+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+        <option>
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+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL</state>
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+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <state>3</state>
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+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+          <name>IccLang</name>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IccRTTI</name>
+          <state>1</state>
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+          <name>IccStaticDestr</name>
+          <state>1</state>
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+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32373C_EVAL_CustomHID.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>Custom_HID.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32f37x_flash.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM32303C_EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM32303C_EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM32303C_EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F303xC	ST STM32F303xC</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F30X</state>
+          <state>USE_STM32303C_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>0000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
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+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F30x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\iar\startup_stm32f30x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f30x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32303C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F30x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F37x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\iar\startup_stm32f37x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f37x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32373C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F37x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dac.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32l1xx.c</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_endp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.eww
new file mode 100644
index 0000000..971c371
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/Custom_HID.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\Custom_HID.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-Custom_HID</name>
+      <member>
+        <project>Custom_HID</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>Custom_HID</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>Custom_HID</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>Custom_HID</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>Custom_HID</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f37x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f37x_flash.icf
new file mode 100644
index 0000000..a743cb4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32f37x_flash.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..8b7d80d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/MDK-ARM/Custom_HID.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/MDK-ARM/Custom_HID.uvproj
new file mode 100644
index 0000000..cf43170
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/MDK-ARM/Custom_HID.uvproj
@@ -0,0 +1,12783 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>STM3210B-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>4223</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM3210B-EVAL\</OutputDirectory>
+          <OutputName>STM3210B-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210B-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x8000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>hw_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\hw_config.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_desc.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_endp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_endp.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_istr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_istr.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_prop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_prop.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32l1xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32l1xx.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>startup_stm32f10x_hd.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
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+              <FileType>2</FileType>
+              <FilePath>..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld.s</FilePath>
+              <FileOption>
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+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
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+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>STM3210E-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103ZE</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>4216</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM3210E-EVAL\</OutputDirectory>
+          <OutputName>STM3210E-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210E-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
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+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
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+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
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+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
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+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
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+            <asSyms>1</asSyms>
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+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
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+            <EndSel>0</EndSel>
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+            <RwSelD>5</RwSelD>
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+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+              <Ocm2>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
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+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <Size>0x80000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
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+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
+            </VariousControls>
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+            <VariousControls>
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+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
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+            <TextAddressRange>0x8000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
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+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
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+            </File>
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+            </File>
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+              <FilePath>..\src\stm32_it.c</FilePath>
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+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
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+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
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+              <IncludeLibraryModules></IncludeLibraryModules>
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+          <Vendor>STMicroelectronics</Vendor>
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+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
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+          <Flash4></Flash4>
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+          <GroupName>STM32373C_EVAL</GroupName>
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+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
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+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
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+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
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+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
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+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
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+                <Ropi>2</Ropi>
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+                <NoWarn>2</NoWarn>
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+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
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+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
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+      <TargetName>STM32L152-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L152VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>5249</DeviceId>
+          <RegisterFile>stm32l1xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\ST\STM32L15x\STM32L15x.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
+          <TargetStatus>
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+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM32L152-EVAL\</OutputDirectory>
+          <OutputName>STM32L152-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM32L152-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
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+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+          <SVCSIdString></SVCSIdString>
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+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
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+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
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+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
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+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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+            <RestoreToolbox>1</RestoreToolbox>
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+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
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+        <Utilities>
+          <Flash1>
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+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
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+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
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+                <StartAddress>0x8000000</StartAddress>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <Size>0x0</Size>
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+                <Size>0x20000</Size>
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+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_MD, USE_STM32L152_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL</IncludePath>
+            </VariousControls>
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+              <Define></Define>
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+            <LinkerInputFile></LinkerInputFile>
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+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
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+              <FileType>1</FileType>
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+                  <IncludeLibraryModules></IncludeLibraryModules>
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+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
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+              <FileName>hw_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\hw_config.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_desc.c</FilePath>
+            </File>
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+              <FilePath>..\readme.txt</FilePath>
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
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+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4")ESEL ELITTLE FPU2</Cpu>
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+          <StartupFile>"STARTUP\ARM\startup_MPS_CM0.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M4") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000)</FlashDriverDll>
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+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
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+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
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+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
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+            <VariousControls>
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+              <Define>USE_STDPERIPH_DRIVER, STM32F37X, USE_STM32373C_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\\STM32F37x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL</IncludePath>
+            </VariousControls>
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+              <Define></Define>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/RIDE/Custom_HID.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/RIDE/Custom_HID.rprj
new file mode 100644
index 0000000..f685752
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/RIDE/Custom_HID.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'Custom_HID'" Path=".\Custom_HID.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="Custom_HID" >
+	<ApplicationBuild Header="Custom_HID" Extern=".\Custom_HID.rapp" Path=".\Custom_HID.rapp" OutputFile=".\STM32303-EVAL\Custom_HID.elf" Config="STM32303C_EVAL" sate="98" />
+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..bda8d00
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.cproject
@@ -0,0 +1,136 @@
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+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..5155ef6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..2d09c3d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..1292232
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..1c5d0c1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..c6a41a5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
new file mode 100644
index 0000000..252b6cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL_XL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..40cd3dc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..fa6b95a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
new file mode 100644
index 0000000..80853f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32303C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32303C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
new file mode 100644
index 0000000..3ccf590
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f30x.lsl
+//
+//  Version     :  @(#)stm32f30x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F30x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F30x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       6k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+
+memory STM32F30x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE - 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM8k
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    priority = 1;
+    map ( size = 8k, dest_offset=0x10000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2 interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2 global interrupts
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB Device High Priority or CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );      // USB Device Low Priority or CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break irq and TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );        // TIM1 Update irq and TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation irqs and TIM17 global irq
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup interrupt
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break interrupt
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update interrupt
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 trigger and Comm. interrupt
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare interrupt
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4 global interrupt
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "ADC4_IRQHandler" );                 // ADC4 global interrupt
+                        vector ( id = 80, optional, fill = "COMP1_2_3_IRQHandler" );            // COMP1, COMP2 and COMP3 global interrupt
+                        vector ( id = 81, optional, fill = "COMP4_5_6_IRQHandler" );            // COMP5, COMP6 and COMP4 global interrupt
+                        vector ( id = 82, optional, fill = "COMP7_IRQHandler" );                // COMP7 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt  remap
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt  remap
+                        vector ( id = 92, optional, fill = "USBWakeUp_RMP_IRQHandler" );        // USB Wakeup Interrupt remap
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/.project
new file mode 100644
index 0000000..bcfdffd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
new file mode 100644
index 0000000..f77e8ab
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32373C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32373C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..d8ba5b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..44229ae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.cproject
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_md.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..69a8de0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..3d03fe1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.cproject
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152D-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152zd" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
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+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file (.lsl):" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_hd.lsl" valueType="string"/>
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+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
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+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
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+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
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+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
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+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..5cca315
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
new file mode 100644
index 0000000..26462e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152D-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152D-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..463038d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                            // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..1a1edfa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210B-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
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+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
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+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
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+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
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+						</toolChain>
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+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..257a59a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ba973b2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:15:49 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..e0aa35c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..2225a91
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/.cproject
@@ -0,0 +1,353 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..8390b4e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32F10X_XL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1578134158" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1314431980" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1997653104" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.586288316" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.755641127" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.377284588" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL_XL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.26443420" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.1289217812" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.144019967" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1807046025" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.704598245" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.478811538" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.864630601" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1692358135" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.820544888" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.710897842" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.160897551" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.417308276" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1343613995" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM32F103ZG\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1975801800" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.;com.atollic.truestudio.exe.debug.toolchain.gcc.486923113;com.atollic.truestudio.gcc.input.377284588">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..a60028c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,241 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..193e636
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:17:04 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..a2b5528
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Custom_HID\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
new file mode 100644
index 0000000..b1c6965
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of 96K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..5929ca9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F30x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F30x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32303C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.2061924893" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F303VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..a7816da
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,310 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..11c9ee7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
new file mode 100644
index 0000000..c0e7344
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F303VC Device with
+**                256KByte FLASH, 40KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000a000;    /* end of 40K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 40K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+  CCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+  
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section 
+  * 
+  * IMPORTANT NOTE! 
+  * If initialized variables will be placed in this section, 
+  * the startup code needs to be modified to copy the init-values.  
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+    
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.cproject
new file mode 100644
index 0000000..f6f0f6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F37x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F37x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
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+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
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+					</folderInfo>
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+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
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+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.311825581;com.atollic.truestudio.exe.debug.311825581.;com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438;com.atollic.truestudio.gcc.input.488480100">
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+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.22089575;com.atollic.truestudio.exe.debug.22089575.;com.atollic.truestudio.exe.debug.toolchain.gcc.1449748890;com.atollic.truestudio.gcc.input.408550467">
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+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..8f381a3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,315 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..734d809
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..35c7d30
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..16e969d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32L152-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
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+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32L152_EVAL"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
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+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..4e9e5a4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..5a1b32c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Custom_HID\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..0e739f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32L152D-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..bb853e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
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+					<value>true</value>
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+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
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+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152D_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152D_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/hw_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/hw_config.h
new file mode 100644
index 0000000..c01f237
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/hw_config.h
@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Set_System(void);
+void Set_USBClock(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void USB_Cable_Config (FunctionalState NewState);
+void GPIO_Configuration(void);
+void EXTI_Configuration(void);
+void ADC_Configuration(void);
+void ADC30x_Configuration(void);
+void Get_SerialNum(void);
+void TimingDelay_Decrement(void);
+void Delay(__IO uint32_t nCount);
+
+#endif  /*__HW_CONFIG_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/platform_config.h
new file mode 100644
index 0000000..d2f5b12
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/platform_config.h
@@ -0,0 +1,210 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL)&&  !defined (USE_STM32373C_EVAL) &&  !defined (USE_STM32303C_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define USE_STM32373C_EVAL
+ #define USE_STM32303C_EVAL
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+  #define ADC1_DR_Address                     ((uint32_t)0x4001244C)
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+  #define ADC1_DR_Address                     ((uint32_t)0x4001244C)
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       0
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+  #define ADC1_DR_Address                     ((uint32_t)0x40012458)
+
+#endif /* USE_STM3210B_EVAL */
+
+#if defined (USE_STM32373C_EVAL)
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+#endif
+#if defined (USE_STM32303C_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+
+#define RCC_AHBPeriph_ALLGPIO                 (RCC_AHBPeriph_GPIOA \
+                                              | RCC_AHBPeriph_GPIOB \
+                                              | RCC_AHBPeriph_GPIOC \
+                                              | RCC_AHBPeriph_GPIOD \
+                                              | RCC_AHBPeriph_GPIOE \
+                                              | RCC_AHBPeriph_GPIOF )
+#endif
+
+#if defined (USE_STM32L152_EVAL)
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOB
+  #define GPIO_IOAIN                          GPIOB
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_12   /* PB.12 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_18
+
+#elif defined (USE_STM32L152D_EVAL)
+  
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOF
+  #define GPIO_IOAIN                          GPIOF
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_10   /* PF.10 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_31
+
+#elif defined (USE_STM32373C_EVAL)
+  
+  #define ADC1_DR_Address                     0x4001244C
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOB
+  #define GPIO_IOAIN                          GPIOB
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_1   /* PB.1 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_9
+  #define GPIO_Mode_AIN                       GPIO_Mode_AN
+
+#elif defined (USE_STM32303C_EVAL)
+  
+  #define ADC1_DR_Address                      0x5000030C
+
+  #define RCC_AHBPeriph_GPIO_IOAIN            RCC_AHBPeriph_GPIOC
+  #define GPIO_IOAIN                          GPIOC
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_1   /* PC.1 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_7
+  #define GPIO_Mode_AIN                       GPIO_Mode_AN
+
+#else
+  #define RCC_APB2Periph_GPIO_IOAIN           RCC_APB2Periph_GPIOC
+  #define GPIO_IOAIN                          GPIOC
+  #define GPIO_IOAIN_PIN                      GPIO_Pin_4   /* PC.04 */
+  #define ADC_AIN_CHANNEL                     ADC_Channel_14
+
+#endif /* USE_STM32L152_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32_it.h
new file mode 100644
index 0000000..7c4b238
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32_it.h
@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void EXTI15_10_IRQHandler(void);
+
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32l1xx_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32l1xx_conf.h
new file mode 100644
index 0000000..ae4a251
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/stm32l1xx_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CONF_H
+#define __STM32L1xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_crc.h"
+#include "stm32l1xx_comp.h"
+#include "stm32l1xx_dac.h" 
+#include "stm32l1xx_dbgmcu.h"
+#include "stm32l1xx_dma.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_flash.h"
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_iwdg.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_tim.h" 
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_wwdg.h"
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32L1xx_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/usb_istr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/usb_istr.h
new file mode 100644
index 0000000..017dce7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/inc/usb_istr.h
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the peripherals header files in the user application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+ void USB_Istr(void);
+
+/* function prototypes Automatically built defining related macros */
+
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+
+#ifdef CTR_CALLBACK
+void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+void ESOF_Callback(void);
+#endif
+
+#endif /*__USB_ISTR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/readme.txt
new file mode 100644
index 0000000..b627219
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/readme.txt
@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB Custom_HID Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+This Demo provides a description of how to use the USB-FS-Device on the STM32F10xxx, 
+STM32F37xxx, STM32F30xxx and STM32L15xxx devices.
+The STM32 device is enumerated as HID compliant device, that uses the native PC 
+Host USB-FS-Device HID driver.
+
+To test the example, you need to:
+
+  1)- Start the "USB HID Demonstrator" PC applet and connect STM32 USB to PC
+  2)- The device should be detected and shown in the USB HID target box
+  3)- Press Graphic View button
+  4)- You can Select "use SET_FEATURE" or "use SET_REPORT" in order to use SET_REPORT request to send HID Report
+       for LED control
+  5)- Make sure that following report ID are configured: LED1 ID (0x1) , LED2 ID(0x2),
+       LED3 ID(0x3), LED4 ID(0x4), and BUTTON1_ID(0x5)
+  6)- Select Leds to switch on/off on the EVAL board => a SET_REPORT request will be sent
+	   
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain 
+ + \TASKING: contains preconfigured projects for TASKING toolchain  
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain           
+ + \src: contains the Demo firmware source files
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3. 
+
+  - STM32L152-EVAL Set-up 
+     - Jumpers JP18 and JP19 should be connected. 
+     - Jumper JP17 should be connected in position 5-6 (PB12 connector)
+     - Note that JoySitck Right and Left buttons are used for this Demo.
+	 
+  - STM32L152D-EVAL Set-up 
+	 - LCD Glass should be mounted On IO position for Potentiometer usage.
+	 - JP13 should be connected to ADC input. 
+
+  - STM32F373C_EVAL  Set-up 
+      - None. 
+
+  - STM32F303C_EVAL  Set-up 
+      - None. 
+	  
+How to use it
+=============
+ + EWARM
+    - Open the Custom_HID.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the Custom_HID.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)  
+
+ + RIDE
+    - Open the Custom_HID.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   		
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/main.c
new file mode 100644
index 0000000..f5590a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/main.c
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Custom HID demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+__IO uint8_t PrevXferComplete = 1;
+__IO uint32_t TimingDelay = 0;
+/* Private function prototypes -----------------------------------------------*/
+void Delay(__IO uint32_t nCount);
+
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : main.
+* Description    : main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+
+  USB_Interrupts_Config();
+
+  Set_USBClock();
+
+  USB_Init();
+
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Delay
+* Description    : Inserts a delay time.
+* Input          : nCount: specifies the delay time length.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void Delay(__IO uint32_t nCount)
+{
+  TimingDelay = nCount;
+  for(; nCount!= 0;nCount--);
+}
+
+#ifdef  USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while(1)
+  {
+  }
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/stm32_it.c
new file mode 100644
index 0000000..7614cfc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/stm32_it.c
@@ -0,0 +1,401 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32_it.h"
+#include "usb_istr.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint8_t Send_Buffer[2];
+extern __IO uint8_t PrevXferComplete;
+extern uint32_t ADC_ConvertedValueX;
+extern uint32_t ADC_ConvertedValueX_1;
+extern __IO uint32_t TimingDelay;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+    TimingDelay--;
+}
+
+/******************************************************************************/
+/*            STM32 Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined (STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+#if defined(STM32L1XX_MD)
+/*******************************************************************************
+* Function Name  : EXTI15_10_IRQHandler
+* Description    : This function handles External lines 15 to 10 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI15_10_IRQHandler(void)
+{
+  /* Check on the RIGHT button */
+  if(EXTI_GetITStatus(RIGHT_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x05; 
+      
+      if (STM_EVAL_PBGetState(Button_RIGHT) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      
+      SetEPTxValid(ENDP1);
+      
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(RIGHT_BUTTON_EXTI_LINE);
+  }  
+
+  /* Check on the LEFT button */
+  if(EXTI_GetITStatus(LEFT_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x06; 
+      
+      if (STM_EVAL_PBGetState(Button_LEFT) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      
+      SetEPTxValid(ENDP1);
+      
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(LEFT_BUTTON_EXTI_LINE);
+  }  
+}
+#endif
+/*******************************************************************************
+* Function Name  : DMA1_Channel1_IRQHandler
+* Description    : This function handles DMA1 Channel 1 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DMA1_Channel1_IRQHandler(void)
+{  
+  Send_Buffer[0] = 0x07;
+  
+  if((ADC_ConvertedValueX >>4) - (ADC_ConvertedValueX_1 >>4) > 4)
+  {
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[1] = (uint8_t)(ADC_ConvertedValueX >>4);
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      SetEPTxValid(ENDP1);
+      ADC_ConvertedValueX_1 = ADC_ConvertedValueX;
+      PrevXferComplete = 0;
+    }
+  }
+  
+  DMA_ClearFlag(DMA1_FLAG_TC1);
+}
+
+/*******************************************************************************
+* Function Name  : EXTI_IRQHandler
+* Description    : This function handles External lines interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void EXTI0_IRQHandler(void)
+#elif defined (STM32F37X)
+void EXTI2_TS_IRQHandler(void)
+#else
+void EXTI9_5_IRQHandler(void)
+#endif
+{
+  if(EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x05; 
+#if defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+      if (!STM_EVAL_PBGetState(Button_KEY) == Bit_RESET)
+#else
+      if (STM_EVAL_PBGetState(Button_KEY) == Bit_RESET)       
+#endif      
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }  
+      
+      /* Write the descriptor through the endpoint */
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+      SetEPTxValid(ENDP1);
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line  pending bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  }
+}
+#if !defined(STM32L1XX_MD) &&  !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)&& ! defined (STM32F37X) && ! defined (STM32F30X)
+/*******************************************************************************
+* Function Name  : EXTI15_10_IRQHandler
+* Description    : This function handles External lines 15 to 10 interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EXTI15_10_IRQHandler(void)
+{
+  if(EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET)
+  {  
+    if ((PrevXferComplete) && (bDeviceState == CONFIGURED))
+    {
+      Send_Buffer[0] = 0x06;
+      
+      if (STM_EVAL_PBGetState(Button_TAMPER) == Bit_RESET)
+      {
+        Send_Buffer[1] = 0x01;
+      }
+      else 
+      {
+        Send_Buffer[1] = 0x00;
+      }
+      
+      /* Write the descriptor through the endpoint */    
+      USB_SIL_Write(EP1_IN, (uint8_t*) Send_Buffer, 2);  
+     
+      SetEPTxValid(ENDP1);
+
+      PrevXferComplete = 0;
+    }
+    /* Clear the EXTI line 13 pending bit */
+    EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE);
+  }
+}
+
+#endif /*STM32L1XX_HD*/
+
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f30x.c
new file mode 100644
index 0000000..31faf5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F30x devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f30x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f30x.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F30x device                          
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F30x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f30x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+  * @{
+  */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F30x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 72000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_desc.c
new file mode 100644
index 0000000..a805f02
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_desc.c
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Custom HID Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* USB Standard Device Descriptor */
+const uint8_t CustomHID_DeviceDescriptor[CUSTOMHID_SIZ_DEVICE_DESC] =
+  {
+    0x12,                       /*bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
+    0x00,                       /*bcdUSB */
+    0x02,
+    0x00,                       /*bDeviceClass*/
+    0x00,                       /*bDeviceSubClass*/
+    0x00,                       /*bDeviceProtocol*/
+    0x40,                       /*bMaxPacketSize40*/
+    0x83,                       /*idVendor (0x0483)*/
+    0x04,
+    0x50,                       /*idProduct = 0x5750*/
+    0x57,
+    0x00,                       /*bcdDevice rel. 2.00*/
+    0x02,
+    1,                          /*Index of string descriptor describing
+                                              manufacturer */
+    2,                          /*Index of string descriptor describing
+                                             product*/
+    3,                          /*Index of string descriptor describing the
+                                             device serial number */
+    0x01                        /*bNumConfigurations*/
+  }
+  ; /* CustomHID_DeviceDescriptor */
+
+
+/* USB Configuration Descriptor */
+/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t CustomHID_ConfigDescriptor[CUSTOMHID_SIZ_CONFIG_DESC] =
+  {
+    0x09, /* bLength: Configuration Descriptor size */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
+    CUSTOMHID_SIZ_CONFIG_DESC,
+    /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,         /* bNumInterfaces: 1 interface */
+    0x01,         /* bConfigurationValue: Configuration value */
+    0x00,         /* iConfiguration: Index of string descriptor describing
+                                 the configuration*/
+    0xC0,         /* bmAttributes: Self powered */
+    0x32,         /* MaxPower 100 mA: this current is used for detecting Vbus */
+
+    /************** Descriptor of Custom HID interface ****************/
+    /* 09 */
+    0x09,         /* bLength: Interface Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,/* bDescriptorType: Interface descriptor type */
+    0x00,         /* bInterfaceNumber: Number of Interface */
+    0x00,         /* bAlternateSetting: Alternate setting */
+    0x02,         /* bNumEndpoints */
+    0x03,         /* bInterfaceClass: HID */
+    0x00,         /* bInterfaceSubClass : 1=BOOT, 0=no boot */
+    0x00,         /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
+    0,            /* iInterface: Index of string descriptor */
+    /******************** Descriptor of Custom HID HID ********************/
+    /* 18 */
+    0x09,         /* bLength: HID Descriptor size */
+    HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
+    0x10,         /* bcdHID: HID Class Spec release number */
+    0x01,
+    0x00,         /* bCountryCode: Hardware target country */
+    0x01,         /* bNumDescriptors: Number of HID class descriptors to follow */
+    0x22,         /* bDescriptorType */
+    CUSTOMHID_SIZ_REPORT_DESC,/* wItemLength: Total length of Report descriptor */
+    0x00,
+    /******************** Descriptor of Custom HID endpoints ******************/
+    /* 27 */
+    0x07,          /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
+
+    0x81,          /* bEndpointAddress: Endpoint Address (IN) */
+    0x03,          /* bmAttributes: Interrupt endpoint */
+    0x02,          /* wMaxPacketSize: 2 Bytes max */
+    0x00,
+    0x20,          /* bInterval: Polling Interval (32 ms) */
+    /* 34 */
+    	
+    0x07,	/* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,	/* bDescriptorType: */
+			/*	Endpoint descriptor type */
+    0x01,	/* bEndpointAddress: */
+			/*	Endpoint Address (OUT) */
+    0x03,	/* bmAttributes: Interrupt endpoint */
+    0x02,	/* wMaxPacketSize: 2 Bytes max  */
+    0x00,
+    0x20,	/* bInterval: Polling Interval (20 ms) */
+    /* 41 */
+  }
+  ; /* CustomHID_ConfigDescriptor */
+const uint8_t CustomHID_ReportDescriptor[CUSTOMHID_SIZ_REPORT_DESC] =
+  {                    
+    0x06, 0xFF, 0x00,      /* USAGE_PAGE (Vendor Page: 0xFF00) */                       
+    0x09, 0x01,            /* USAGE (Demo Kit)               */    
+    0xa1, 0x01,            /* COLLECTION (Application)       */            
+    /* 6 */
+    
+    /* Led 1 */        
+    0x85, 0x01,            /*     REPORT_ID (1)		     */
+    0x09, 0x01,            /*     USAGE (LED 1)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x01,            /*     REPORT_ID (1)              */
+    0x09, 0x01,            /*     USAGE (LED 1)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 26 */
+    
+    /* Led 2 */
+    0x85, 0x02,            /*     REPORT_ID 2		     */
+    0x09, 0x02,            /*     USAGE (LED 2)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x02,            /*     REPORT_ID (2)              */
+    0x09, 0x02,            /*     USAGE (LED 2)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 46 */
+    
+    /* Led 3 */        
+    0x85, 0x03,            /*     REPORT_ID (3)		     */
+    0x09, 0x03,            /*     USAGE (LED 3)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,             /*    FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x03,            /*     REPORT_ID (3)              */
+    0x09, 0x03,            /*     USAGE (LED 3)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 66 */
+    
+    /* Led 4 */
+    0x85, 0x04,            /*     REPORT_ID 4)		     */
+    0x09, 0x04,            /*     USAGE (LED 4)	             */
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */          
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */           
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */        
+    0x95, 0x01,            /*     REPORT_COUNT (1)           */       
+    0xB1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */     
+
+    0x85, 0x04,            /*     REPORT_ID (4)              */
+    0x09, 0x04,            /*     USAGE (LED 4)              */
+    0x91, 0x82,            /*     OUTPUT (Data,Var,Abs,Vol)  */
+    /* 86 */
+    
+    /* key Push Button */  
+    0x85, 0x05,            /*     REPORT_ID (5)              */
+    0x09, 0x05,            /*     USAGE (Push Button)        */      
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */      
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */      
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */  
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */   
+    
+    0x09, 0x05,            /*     USAGE (Push Button)        */               
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */           
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */  
+         
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0x81, 0x83,            /*     INPUT (Cnst,Var,Abs,Vol)   */                    
+    0x85, 0x05,            /*     REPORT_ID (2)              */         
+                    
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0xb1, 0x83,            /*     FEATURE (Cnst,Var,Abs,Vol) */                      
+    /* 114 */
+
+    /* Tamper Push Button */  
+    0x85, 0x06,            /*     REPORT_ID (6)              */
+    0x09, 0x06,            /*     USAGE (Tamper Push Button) */      
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */      
+    0x25, 0x01,            /*     LOGICAL_MAXIMUM (1)        */      
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */  
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */   
+    
+    0x09, 0x06,            /*     USAGE (Tamper Push Button) */               
+    0x75, 0x01,            /*     REPORT_SIZE (1)            */           
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */  
+         
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0x81, 0x83,            /*     INPUT (Cnst,Var,Abs,Vol)   */                    
+    0x85, 0x06,            /*     REPORT_ID (6)              */         
+                    
+    0x75, 0x07,            /*     REPORT_SIZE (7)            */           
+    0xb1, 0x83,            /*     FEATURE (Cnst,Var,Abs,Vol) */  
+    /* 142 */
+    
+    /* ADC IN */
+    0x85, 0x07,            /*     REPORT_ID (7)              */         
+    0x09, 0x07,            /*     USAGE (ADC IN)             */          
+    0x15, 0x00,            /*     LOGICAL_MINIMUM (0)        */               
+    0x26, 0xff, 0x00,      /*     LOGICAL_MAXIMUM (255)      */                 
+    0x75, 0x08,            /*     REPORT_SIZE (8)            */           
+    0x81, 0x82,            /*     INPUT (Data,Var,Abs,Vol)   */                    
+    0x85, 0x07,            /*     REPORT_ID (7)              */                 
+    0x09, 0x07,            /*     USAGE (ADC in)             */                     
+    0xb1, 0x82,            /*     FEATURE (Data,Var,Abs,Vol) */                                 
+    /* 161 */
+
+    0xc0 	          /*     END_COLLECTION	             */
+  }; /* CustomHID_ReportDescriptor */
+
+/* USB String Descriptors (optional) */
+const uint8_t CustomHID_StringLangID[CUSTOMHID_SIZ_STRING_LANGID] =
+  {
+    CUSTOMHID_SIZ_STRING_LANGID,
+    USB_STRING_DESCRIPTOR_TYPE,
+    0x09,
+    0x04
+  }
+  ; /* LangID = 0x0409: U.S. English */
+
+const uint8_t CustomHID_StringVendor[CUSTOMHID_SIZ_STRING_VENDOR] =
+  {
+    CUSTOMHID_SIZ_STRING_VENDOR, /* Size of Vendor string */
+    USB_STRING_DESCRIPTOR_TYPE,  /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t CustomHID_StringProduct[CUSTOMHID_SIZ_STRING_PRODUCT] =
+  {
+    CUSTOMHID_SIZ_STRING_PRODUCT,          /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'C', 0,
+    'u', 0, 's', 0, 't', 0, 'm', 0, ' ', 0, 'H', 0, 'I', 0,
+    'D', 0
+  };
+uint8_t CustomHID_StringSerial[CUSTOMHID_SIZ_STRING_SERIAL] =
+  {
+    CUSTOMHID_SIZ_STRING_SERIAL,           /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0,'3', 0,'2', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_istr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_istr.c
new file mode 100644
index 0000000..b2f93a4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_istr.c
@@ -0,0 +1,236 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   ISTR events interrupt service routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t wIstr;  /* ISTR register last read value */
+__IO uint8_t bIntPackSOF = 0;  /* SOFs received between 2 consecutive packets */
+__IO uint32_t esof_counter =0; /* expected SOF counter */
+__IO uint32_t wCNTR=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* function pointers to non-control endpoints service routines */
+void (*pEpInt_IN[7])(void) =
+  {
+    EP1_IN_Callback,
+    EP2_IN_Callback,
+    EP3_IN_Callback,
+    EP4_IN_Callback,
+    EP5_IN_Callback,
+    EP6_IN_Callback,
+    EP7_IN_Callback,
+  };
+
+void (*pEpInt_OUT[7])(void) =
+  {
+    EP1_OUT_Callback,
+    EP2_OUT_Callback,
+    EP3_OUT_Callback,
+    EP4_OUT_Callback,
+    EP5_OUT_Callback,
+    EP6_OUT_Callback,
+    EP7_OUT_Callback,
+  };
+
+/*******************************************************************************
+* Function Name  : USB_Istr
+* Description    : ISTR events interrupt service routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Istr(void)
+{
+    uint32_t i=0;
+ __IO uint32_t EP[8];
+  
+  wIstr = _GetISTR();
+
+#if (IMR_MSK & ISTR_CTR)
+  if (wIstr & ISTR_CTR & wInterrupt_Mask)
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    CTR_LP();
+#ifdef CTR_CALLBACK
+    CTR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
+#if (IMR_MSK & ISTR_RESET)
+  if (wIstr & ISTR_RESET & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_RESET);
+    Device_Property.Reset();
+#ifdef RESET_CALLBACK
+    RESET_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_DOVR)
+  if (wIstr & ISTR_DOVR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_DOVR);
+#ifdef DOVR_CALLBACK
+    DOVR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ERR)
+  if (wIstr & ISTR_ERR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ERR);
+#ifdef ERR_CALLBACK
+    ERR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_WKUP)
+  if (wIstr & ISTR_WKUP & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_WKUP);
+    Resume(RESUME_EXTERNAL);
+#ifdef WKUP_CALLBACK
+    WKUP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SUSP)
+  if (wIstr & ISTR_SUSP & wInterrupt_Mask)
+  {
+
+    /* check if SUSPEND is possible */
+    if (fSuspendEnabled)
+    {
+      Suspend();
+    }
+    else
+    {
+      /* if not possible then resume after xx ms */
+      Resume(RESUME_LATER);
+    }
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    _SetISTR((uint16_t)CLR_SUSP);
+#ifdef SUSP_CALLBACK
+    SUSP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SOF)
+  if (wIstr & ISTR_SOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_SOF);
+    bIntPackSOF++;
+
+#ifdef SOF_CALLBACK
+    SOF_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ESOF)
+  if (wIstr & ISTR_ESOF & wInterrupt_Mask)
+  {
+    /* clear ESOF flag in ISTR */
+    _SetISTR((uint16_t)CLR_ESOF);
+    
+    if ((_GetFNR()&FNR_RXDP)!=0)
+    {
+      /* increment ESOF counter */
+      esof_counter ++;
+      
+      /* test if we enter in ESOF more than 3 times with FSUSP =0 and RXDP =1=>> possible missing SUSP flag*/
+      if ((esof_counter >3)&&((_GetCNTR()&CNTR_FSUSP)==0))
+      {           
+        /* this a sequence to apply a force RESET*/
+      
+        /*Store CNTR value */
+        wCNTR = _GetCNTR(); 
+      
+        /*Store endpoints registers status */
+        for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+      
+        /*apply FRES */
+        wCNTR|=CNTR_FRES;
+        _SetCNTR(wCNTR);
+ 
+        /*clear FRES*/
+        wCNTR&=~CNTR_FRES;
+        _SetCNTR(wCNTR);
+      
+        /*poll for RESET flag in ISTR*/
+        while((_GetISTR()&ISTR_RESET) == 0);
+  
+        /* clear RESET flag in ISTR */
+        _SetISTR((uint16_t)CLR_RESET);
+   
+       /*restore Enpoints*/
+        for (i=0;i<8;i++)
+        _SetENDPOINT(i, EP[i]);
+      
+        esof_counter = 0;
+      }
+    }
+    else
+    {
+        esof_counter = 0;
+    }
+    
+    /* resume handling timing is made with ESOFs */
+    Resume(RESUME_ESOF); /* request without change of the machine state */
+
+#ifdef ESOF_CALLBACK
+    ESOF_Callback();
+#endif
+  }
+#endif
+} /* USB_Istr */
+
+/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_prop.c
new file mode 100644
index 0000000..c7d1716
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_prop.c
@@ -0,0 +1,534 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processings related to Custom HID Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "hw_config.h" 
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+
+
+/* Private typedef -----------------------------------------------------------*/ 
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t ProtocolValue;
+__IO uint8_t EXTI_Enable;
+__IO uint8_t Request = 0;
+uint8_t Report_Buf[2];   
+/* -------------------------------------------------------------------------- */
+/*  Structures initializations */
+/* -------------------------------------------------------------------------- */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    CustomHID_init,
+    CustomHID_Reset,
+    CustomHID_Status_In,
+    CustomHID_Status_Out,
+    CustomHID_Data_Setup,
+    CustomHID_NoData_Setup,
+    CustomHID_Get_Interface_Setting,
+    CustomHID_GetDeviceDescriptor,
+    CustomHID_GetConfigDescriptor,
+    CustomHID_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    CustomHID_GetConfiguration,
+    CustomHID_SetConfiguration,
+    CustomHID_GetInterface,
+    CustomHID_SetInterface,
+    CustomHID_GetStatus,
+    CustomHID_ClearFeature,
+    CustomHID_SetEndPointFeature,
+    CustomHID_SetDeviceFeature,
+    CustomHID_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)CustomHID_DeviceDescriptor,
+    CUSTOMHID_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)CustomHID_ConfigDescriptor,
+    CUSTOMHID_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR CustomHID_Report_Descriptor =
+  {
+    (uint8_t *)CustomHID_ReportDescriptor,
+    CUSTOMHID_SIZ_REPORT_DESC
+  };
+
+ONE_DESCRIPTOR CustomHID_Hid_Descriptor =
+  {
+    (uint8_t*)CustomHID_ConfigDescriptor + CUSTOMHID_OFF_HID_DESC,
+    CUSTOMHID_SIZ_HID_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+  {
+    {(uint8_t*)CustomHID_StringLangID, CUSTOMHID_SIZ_STRING_LANGID},
+    {(uint8_t*)CustomHID_StringVendor, CUSTOMHID_SIZ_STRING_VENDOR},
+    {(uint8_t*)CustomHID_StringProduct, CUSTOMHID_SIZ_STRING_PRODUCT},
+    {(uint8_t*)CustomHID_StringSerial, CUSTOMHID_SIZ_STRING_SERIAL}
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/*CustomHID_SetReport_Feature function prototypes*/
+uint8_t *CustomHID_SetReport_Feature(uint16_t Length);
+
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : CustomHID_init.
+* Description    : Custom HID init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_init(void)
+{
+  /* Update the serial number string descriptor with the data from the unique 
+  ID*/
+  Get_SerialNum();
+    
+  pInformation->Current_Configuration = 0;
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Reset.
+* Description    : Custom HID reset routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Reset(void)
+{
+  /* Set CustomHID_DEVICE as not configured */
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Interface = 0;/*the default Interface*/
+  
+  /* Current Feature initialization */
+  pInformation->Current_Feature = CustomHID_ConfigDescriptor[7];
+ 
+  SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPRxAddr(ENDP1, ENDP1_RXADDR);
+  SetEPTxCount(ENDP1, 2);
+  SetEPRxCount(ENDP1, 2);
+  SetEPRxStatus(ENDP1, EP_RX_VALID);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+  bDeviceState = ATTACHED;
+}
+/*******************************************************************************
+* Function Name  : CustomHID_SetConfiguration.
+* Description    : Update the device state to configured and command the ADC 
+*                  conversion.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_SetConfiguration(void)
+{
+  if (pInformation->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+    
+    /* Start ADC Software Conversion */ 
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined(STM32F37X)
+    ADC_SoftwareStartConv(ADC1);
+#elif defined (STM32F30X)
+    ADC_StartConversion(ADC1);
+#else
+    ADC_SoftwareStartConvCmd(ADC1, ENABLE);
+#endif /* STM32L1XX_XD */
+  }
+}
+/*******************************************************************************
+* Function Name  : CustomHID_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+/*******************************************************************************
+* Function Name  : CustomHID_Status_In.
+* Description    : Joystick status IN routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Status_In(void)
+{  
+  BitAction Led_State;
+  
+  if (Report_Buf[1] == 0)
+  {
+    Led_State = Bit_RESET;
+  }
+  else 
+  {
+    Led_State = Bit_SET;
+  }
+  
+  switch (Report_Buf[0])  
+  {
+    /*Change LED's status according to the host report*/
+    
+  case 1: /* Led 1 */ 
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED1);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED1);
+    }
+    break;
+  case 2:   /* Led 2 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED2);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED2);
+    }
+    break;
+  case 3:/* Led 3 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED3);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED3);
+    }
+    break;
+  case 4:/* Led 4 */    
+    if (Led_State != Bit_RESET)
+    {
+      STM_EVAL_LEDOn(LED4);
+    }
+    else
+    {
+      STM_EVAL_LEDOff(LED4);
+    }
+    break;
+  default:
+    STM_EVAL_LEDOff(LED1);
+    STM_EVAL_LEDOff(LED2);
+    STM_EVAL_LEDOff(LED3);
+    STM_EVAL_LEDOff(LED4); 
+    break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Status_Out
+* Description    : Joystick status OUT routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CustomHID_Status_Out (void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Data_Setup
+* Description    : Handle the data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+  
+  if (pInformation->USBwIndex != 0) 
+    return USB_UNSUPPORT;    
+  
+  CopyRoutine = NULL;
+  
+  if ((RequestNo == GET_DESCRIPTOR)
+      && (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+        )
+  {
+    
+    if (pInformation->USBwValue1 == REPORT_DESCRIPTOR)
+    {
+      CopyRoutine = CustomHID_GetReportDescriptor;
+    }
+    else if (pInformation->USBwValue1 == HID_DESCRIPTOR_TYPE)
+    {
+      CopyRoutine = CustomHID_GetHIDDescriptor;
+    }
+    
+  } /* End of GET_DESCRIPTOR */
+  
+  /*** GET_PROTOCOL, GET_REPORT, SET_REPORT ***/
+  else if ( (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT)) )
+  {         
+    switch( RequestNo )
+    {
+    case GET_PROTOCOL:
+      CopyRoutine = CustomHID_GetProtocolValue;
+      break;
+    case SET_REPORT:
+      CopyRoutine = CustomHID_SetReport_Feature;
+      Request = SET_REPORT;
+      break;
+    default:
+      break;
+    }
+  }
+  
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+  
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_SetReport_Feature
+* Description    : Set Feature request handling
+* Input          : Length.
+* Output         : None.
+* Return         : Buffer
+*******************************************************************************/
+uint8_t *CustomHID_SetReport_Feature(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 2;
+    return NULL;
+  }
+  else
+  {
+    return Report_Buf;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_NoData_Setup
+* Description    : handle the no data class specific requests
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_NoData_Setup(uint8_t RequestNo)
+{
+  if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+      && (RequestNo == SET_PROTOCOL))
+  {
+    return CustomHID_SetProtocol();
+  }
+
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetConfigDescriptor.
+* Description    : Gets the configuration descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetStringDescriptor
+* Description    : Gets the string descriptors according to the needed index
+* Input          : Length
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *CustomHID_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else 
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetReportDescriptor.
+* Description    : Gets the HID report descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetReportDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &CustomHID_Report_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetHIDDescriptor.
+* Description    : Gets the HID descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *CustomHID_GetHIDDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &CustomHID_Hid_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_Get_Interface_Setting.
+* Description    : tests the interface and the alternate setting according to the
+*                  supported one.
+* Input          : - Interface : interface number.
+*                  - AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT CustomHID_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_SetProtocol
+* Description    : Joystick Set Protocol request routine.
+* Input          : None.
+* Output         : None.
+* Return         : USB SUCCESS.
+*******************************************************************************/
+RESULT CustomHID_SetProtocol(void)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  ProtocolValue = wValue0;
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : CustomHID_GetProtocolValue
+* Description    : get the protocol value
+* Input          : Length.
+* Output         : None.
+* Return         : address of the protocol value.
+*******************************************************************************/
+uint8_t *CustomHID_GetProtocolValue(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 1;
+    return NULL;
+  }
+  else
+  {
+    return (uint8_t *)(&ProtocolValue);
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_pwr.c
new file mode 100644
index 0000000..a2253a8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Custom_HID/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewd
new file mode 100644
index 0000000..26ba5a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewp
new file mode 100644
index 0000000..dc50a93
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.ewp
@@ -0,0 +1,6913 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xE	ST STM32F103xE</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <state>$PROJ_DIR$\..\inc</state>
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+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
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+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
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+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <state></state>
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+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+          <state>0</state>
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+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+          <state>1</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+          <state></state>
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+          <version>0</version>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+      <name>ARM</name>
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+          <name>ObjPath</name>
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+          <state>STM32L152-EVAL\List</state>
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+          <state>Full formatting.</state>
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+          <state>1</state>
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+          <state>Full formatting.</state>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xB	ST STM32L152xB</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <version>20</version>
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+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
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+      <name>ICCARM</name>
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+          <state>STM32L1XX_MD</state>
+          <state>USE_STM32L152_EVAL</state>
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+          <name>CCPreprocComments</name>
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+          <name>CCPreprocLine</name>
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+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
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+        <option>
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+          <name>CCDiagSuppress</name>
+          <state></state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+          <version>1</version>
+          <state>1111111</state>
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+          <state>1</state>
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+        <option>
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+          <state>1</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
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+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
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+          <state>$FILE_BNAME$.o</state>
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+          <state>1</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL</state>
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+        <option>
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+          <state>.text</state>
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+          <state>3</state>
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+          <name>IccStaticDestr</name>
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+      <archiveVersion>0</archiveVersion>
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+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32L152-EVAL_DFU.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
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+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
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+      <archiveVersion>0</archiveVersion>
+      <data/>
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+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state>1</state>
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+          <name>XLinkMisraHandler</name>
+          <state>0</state>
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+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
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+          <state>DFU.out</state>
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+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
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+          <name>IlinkRawBinarySegment</name>
+          <state></state>
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+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
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+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
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+          <name>IlinkLogInitialization</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
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+          <name>IlinkLogVeneer</name>
+          <state>0</state>
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+          <name>IlinkIcfOverride</name>
+          <state>1</state>
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+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
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+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
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+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
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+          <name>IlinkExtraOptions</name>
+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
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+          <state>0</state>
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+          <state>__iar_program_start</state>
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+          <state>0x11021</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
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+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+          <name>IarchiveOverride</name>
+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+      <name>ARM</name>
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+          <name>ExePath</name>
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+          <state>STM32L152D-EVAL\List</state>
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+          <version>2</version>
+          <state>1</state>
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+          <version>0</version>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xD	ST STM32L152xD</state>
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+          <state>1</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+          <name>GFPUCoreSlave</name>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+          <name>OGUseCmsisDspLib</name>
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+        <wantNonLocal>1</wantNonLocal>
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+          <state>0</state>
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+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32L1XX_HD</state>
+          <state>USE_STM32L152D_EVAL</state>
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+          <name>CCPreprocComments</name>
+          <state>0</state>
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+          <name>CCPreprocLine</name>
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+          <name>CCListCFile</name>
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+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+          <name>CCListAssFile</name>
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+          <name>CCListAssSource</name>
+          <state>0</state>
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+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+          <name>CCDiagSuppress</name>
+          <state></state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+        <option>
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+          <state>1</state>
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+          <version>1</version>
+          <state>1111111</state>
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
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+          <state></state>
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+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCMultibyteSupport</name>
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+          <name>CCDiagWarnAreErr</name>
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+          <state>$FILE_BNAME$.o</state>
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+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+        <option>
+          <name>PreInclude</name>
+          <state></state>
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+        <option>
+          <name>CompilerMisraOverride</name>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL</state>
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+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <state>3</state>
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+          <state>3</state>
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+          <state>0</state>
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+          <name>IccRTTI</name>
+          <state>1</state>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
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+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
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+          <name>AListing</name>
+          <state>1</state>
+        </option>
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+          <name>Includes</name>
+          <state>0</state>
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+          <name>MacDefs</name>
+          <state>0</state>
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+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32L152-EVAL_DFU.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>DFU.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
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+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
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+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM32373C_EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM32373C_EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM32373C_EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>39</state>
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+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
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+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F373xC	ST STM32F373xC</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
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+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>GeneralMisraVer</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>39</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>39</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F37X</state>
+          <state>USE_STM32373C_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_xl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f10x.c</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM3210B_EVAL</name>
+      <excluded>
+        <configuration>STM3210E-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_spi_flash.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM3210E_EVAL</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_spi_flash.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F10x_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F30x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\iar\startup_stm32f30x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f30x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32303C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F30x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F37x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\iar\startup_stm32f37x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f37x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32373C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F37x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_mdp.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32l1xx.c</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash_ramfunc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\dfu_mal.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\flash_if.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\fsmc_nor.c</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\nor_if.c</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\spi_if.c</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.eww
new file mode 100644
index 0000000..77855f8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/DFU.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\DFU.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-DFU</name>
+      <member>
+        <project>DFU</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>DFU</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>DFU</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>DFU</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>DFU</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f37x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f37x_flash.icf
new file mode 100644
index 0000000..a743cb4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32f37x_flash.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..8b7d80d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/MDK-ARM/DFU.uvopt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/MDK-ARM/DFU.uvopt
new file mode 100644
index 0000000..631bf1a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/MDK-ARM/DFU.uvopt
@@ -0,0 +1,2520 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC5000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O142 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L151xx_152xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152D-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L162xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_384 -FS08000000 -FL060000)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0579U9E -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32373C_EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32373C_EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DllOpt>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/RIDE/DFU.rapp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/RIDE/DFU.rapp
new file mode 100644
index 0000000..5ac5b18
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/RIDE/DFU.rapp
@@ -0,0 +1,1542 @@
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+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210E-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210E-EVAL" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+																																			
+		</Config>
+		<Config Header="STM3210B-EVAL" >
+			<Set Header="GCC" >
+				<Section Header="Defines" >
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+																																																																																																																																																																																																																																								
+				</Section>
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+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																																																																			
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																									
+				</Section>
+				<Section Header="LIB" >
+					<Property Header="SMALLP" Value="1" Removable="1" />
+																																																																																																																																																																																																																																																																			
+				</Section>
+																																																																																																																																			
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210B-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210B-EVAL" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+																																			
+		</Config>
+		<Config Header="STM3210E-EVAL_XL" >
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F103ZGT6" />
+																																																																																								
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F10X_HD;USE_STM3210E_EVAL" Removable="1" />
+																																																																																								
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																								
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+																																			
+		</Config>
+		<Config Header="STM32L152-EVAL" >
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32L152-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32L152-EVAL" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32L152VBT6" />
+																																																																															
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32L1XX_MD; USE_STM32L152_EVAL" Removable="1" />
+																																																																															
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																															
+				</Section>
+																																																													
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																															
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																															
+				</Section>
+																																																													
+			</Set>
+																																			
+		</Config>
+		<Config Header="STM32L152D-EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																				
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32L152ZD" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+					<Property Header="OutDir" Value="STM32L152D_EVAL" Removable="1" />
+					<Property Header="ListDir" Value="STM32L152D_EVAL" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																		
+				</Section>
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32L1XX_HD; USE_STM32L152D_EVAL" Removable="1" />
+																																																				
+				</Section>
+																										
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																				
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+															
+		</Config>
+		<Config Header="STM32373C_EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																									
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F373xC" />
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+				</Section>
+																			
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32373C-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32373C-EVAL" Removable="1" />
+																									
+				</Section>
+																			
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F37X;USE_STM32373C_EVAL" Removable="1" />
+																									
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																									
+				</Section>
+																			
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+							
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+							
+				</Section>
+					
+			</Set>
+		</Config>
+		<Config Header="STM32303C_EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																									
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F303xC" />
+																									
+				</Section>
+																			
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32303C-EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32303C-EVAL" Removable="1" />
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+							
+				</Section>
+					
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F30X;USE_STM32303C_EVAL" Removable="1" />
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+				</Section>
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+					<Property Header="Optimize" Value="-Os" Removable="1" />
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+				</Section>
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+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+							
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
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+				</Section>
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+			</Set>
+		</Config>
+	</Options>
+</ApplicationBuild>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..f8af2f8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,217 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval_spi_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
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+		<link>
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+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
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+		<link>
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+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
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+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/spi_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/spi_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..2d09c3d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..1292232
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..1c5d0c1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..0a9bb62
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL_XL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_XL.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..eac63c6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,237 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_spi_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_spi_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nor.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nor.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/nor_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nor_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/spi_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/spi_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
new file mode 100644
index 0000000..1f9b805
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL_XL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/STM32F10x_XL_Bank2.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
index 72adf78..e8acf65 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK2/Settings/STM32F10x_XL_Bank2.lsl
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
@@ -29,7 +29,7 @@
 #  define __HEAP                        2k
 #endif
 #ifndef __VECTOR_TABLE_ROM_ADDR
-#  define __VECTOR_TABLE_ROM_ADDR       0x08080000
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
 #endif
 #ifndef __XVWBUF
 #define __XVWBUF                        256             /* buffer used by CrossView */
@@ -57,8 +57,8 @@ memory stm32f103flash
 {
     mau = 8;
     type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+    size = 0x100000;
+    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
 }
 
 memory stm32f103ram
@@ -70,14 +70,6 @@ memory stm32f103ram
 }
 
 #endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
 
 
 //
@@ -95,8 +87,8 @@ section_setup ::linear
                                               no_inline
                                             )
                 {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                      /* Reset Handler                           */
                         vector ( id = 2, optional, fill = "NMI_Handler" );
                         vector ( id = 3, optional, fill = "HardFault_Handler" );
                         vector ( id = 4, optional, fill = "MemManage_Handler" );
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..81df374
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
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new file mode 100644
index 0000000..5a42687
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/.cproject
@@ -0,0 +1,113 @@
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/.project
new file mode 100644
index 0000000..9eb7ee2
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/.project
@@ -0,0 +1,207 @@
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+			<name>USB-FS-Device_Driver</name>
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+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
new file mode 100644
index 0000000..f77e8ab
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32373C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32373C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..d8ba5b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..9233138
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_md.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.misc.longBranchVeneers.551239873" name="Generate long-branch veneers" superClass="com.tasking.arm.lk.misc.longBranchVeneers" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
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+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
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+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
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+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..bf4dd5a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,217 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash_ramfunc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash_ramfunc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
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new file mode 100644
index 0000000..19fb1b4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/.cproject
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..0c24151
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,222 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
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+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
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+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash_ramfunc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash_ramfunc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..77979b6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..4c39242
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210B-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1169641383" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1582707293" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..b107cf4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:36:47 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..e0aa35c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..05fa76d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.cproject
@@ -0,0 +1,353 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
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+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.project
new file mode 100644
index 0000000..7665b6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.project
@@ -0,0 +1,265 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_spi_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_spi_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nor.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/nor_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/nor_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/spi_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/spi_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..0fc623e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:37:30 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..5475c5a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..7bf2164
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,261 @@
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+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
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+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_spi_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_spi_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nor.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/nor_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/nor_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/spi_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/spi_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..2835322
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:37:55 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..e5ada8e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..5929ca9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F30x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F30x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32303C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.2061924893" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F303VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
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+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
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+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
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+				<openAction enabled="true" filePath=""/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.311825581;com.atollic.truestudio.exe.debug.311825581.;com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438;com.atollic.truestudio.gcc.input.488480100">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.22089575;com.atollic.truestudio.exe.debug.22089575.;com.atollic.truestudio.exe.debug.toolchain.gcc.1449748890;com.atollic.truestudio.gcc.input.408550467">
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
new file mode 100644
index 0000000..c0e7344
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F303VC Device with
+**                256KByte FLASH, 40KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000a000;    /* end of 40K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 40K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+  CCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+  
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section 
+  * 
+  * IMPORTANT NOTE! 
+  * If initialized variables will be placed in this section, 
+  * the startup code needs to be modified to copy the init-values.  
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+    
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.cproject
new file mode 100644
index 0000000..f6f0f6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F37x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F37x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F37X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.1266574210" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F373VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..47cfe31
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,320 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
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+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
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+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..734d809
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..35c7d30
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..46ed9a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_STM32L1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/system_STM32L1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash_ramfunc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash_ramfunc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/dfu_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/dfu_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/flash_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/flash_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..f14d2cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:38:58 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..6f7945f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..1be62d5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_md Device with
+**                128KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..4ed71c3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,362 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32L152D-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
new file mode 100644
index 0000000..674b2ff
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\TrueSTUDIO\STM32L152D-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152D-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewd
new file mode 100644
index 0000000..3472367
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>10</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewp
new file mode 100644
index 0000000..257632b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.ewp
@@ -0,0 +1,6777 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xE	ST STM32F103xE</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
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+        <option>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>GeneralMisraVer</name>
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+        </option>
+        <option>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
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+        <option>
+          <name>OGUseCmsis</name>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
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+      <name>ICCARM</name>
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+          <state>USE_STM3210E_EVAL</state>
+          <state>STM32F10X_HD</state>
+          <state>USE_STDPERIPH_DRIVER</state>
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+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
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+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</state>
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+          <state>0</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <state>0</state>
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+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
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+        <option>
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+      <archiveVersion>2</archiveVersion>
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+        <version>8</version>
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+          <state>1</state>
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+          <state></state>
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+          <state></state>
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+          <state>1</state>
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+        <option>
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+          <state>STM3210E-EVAL_SysTick.bin</state>
+        </option>
+        <option>
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+    <settings>
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+      <archiveVersion>3</archiveVersion>
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+        <extensions></extensions>
+        <cmdline></cmdline>
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+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+    <settings>
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+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+      <archiveVersion>0</archiveVersion>
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+          <name>IlinkInputFileSlave</name>
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+        <option>
+          <name>IlinkOutputFile</name>
+          <state>SysTick.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
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+          <state></state>
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+          <state></state>
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+          <name>IlinkMapFile</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
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+          <state>0</state>
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+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
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+        <option>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32f10x_flash_offset.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
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+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
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+          <state>0xFF</state>
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+          <state>0x11021</state>
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+          <name>DoCrc</name>
+          <state>0</state>
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+          <name>IlinkBE8Slave</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
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+          <name>IarchiveInputs</name>
+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
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+      <name>General</name>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>ExePath</name>
+          <state>STM3210B-EVAL\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>STM3210B-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210B-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
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+          <version>3</version>
+          <state>1</state>
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+          <name>Input description</name>
+          <state>Full formatting.</state>
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+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
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+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
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+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
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+          <name>FPU</name>
+          <version>2</version>
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+          <name>OGCoreOrChip</name>
+          <state>1</state>
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+          <state>2</state>
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+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
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+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>4.41A</state>
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+        <option>
+          <name>GeneralEnableMisra</name>
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+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xB	ST STM32F103xB</state>
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+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
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+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules98</name>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
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+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
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+        <option>
+          <name>CCDefines</name>
+          <state>USE_STM3210B_EVAL</state>
+          <state>STM32F10X_MD</state>
+          <state>USE_STDPERIPH_DRIVER</state>
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+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
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+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
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+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
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+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
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+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
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+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
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+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
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+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
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+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+        <option>
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+          <state>0</state>
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+          <name>IProcessorMode2</name>
+          <state>1</state>
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+          <name>CCOptLevel</name>
+          <state>3</state>
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+          <version>0</version>
+          <state>1</state>
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+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
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+          <name>IccLang</name>
+          <state>0</state>
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+          <name>IccCDialect</name>
+          <state>1</state>
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+        <option>
+          <name>IccAllowVLA</name>
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+          <name>IccCppDialect</name>
+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
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+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
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+          <state>1</state>
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+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+      <archiveVersion>2</archiveVersion>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <state>1</state>
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+          <state></state>
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+          <state></state>
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+          <state>$FILE_BNAME$.o</state>
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+          <name>AUserIncludes</name>
+          <state></state>
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+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
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+        <wantNonLocal>1</wantNonLocal>
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+          <version>2</version>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM3210B-EVAL_SysTick.bin</state>
+        </option>
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+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
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+      <archiveVersion>3</archiveVersion>
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+        <extensions></extensions>
+        <cmdline></cmdline>
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+      <archiveVersion>1</archiveVersion>
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+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state>1</state>
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+          <state></state>
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+          <state></state>
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+          <state></state>
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+          <name>IlinkDefines</name>
+          <state></state>
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+          <name>IlinkConfigDefines</name>
+          <state></state>
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+          <state>0</state>
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+          <name>IlinkLogModule</name>
+          <state>0</state>
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+          <name>IlinkLogSection</name>
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+          <name>IlinkLogVeneer</name>
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+          <state>1</state>
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+          <state>$PROJ_DIR$\stm32f10x_flash_offset.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <state></state>
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+          <state>1</state>
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+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+          <state></state>
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+        <version>0</version>
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+          <name>IarchiveOverride</name>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
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+          <name>OGChipSelectEditMenu</name>
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+          <state>USE_STDPERIPH_DRIVER</state>
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+          <state>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
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+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM3210E_XL_SysTick.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>SysTick.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32f10x_flash_offset.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
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+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM32L152_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM32L152_EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM32L152_EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM32L152_EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xB	ST STM32L152xB</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STM32L152_EVAL</state>
+          <state>STM32L1XX_MD</state>
+          <state>USE_STDPERIPH_DRIVER</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
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+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkStackControlFile</name>
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+        <option>
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+          <state></state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F303xC	ST STM32F303xC</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+          <name>GFPUCoreSlave</name>
+          <version>20</version>
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+          <version>20</version>
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+          <name>OGUseCmsisDspLib</name>
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+          <state>USE_STM32303C_EVAL</state>
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+        <option>
+          <name>CCListCMessages</name>
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+          <state></state>
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+          <name>CCDiagRemark</name>
+          <state></state>
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+          <name>CCDiagWarning</name>
+          <state></state>
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+          <version>1</version>
+          <state>1111111</state>
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+          <name>CCLangConformance</name>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCRequirePrototypes</name>
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+          <name>CCMultibyteSupport</name>
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+          <name>CCDiagWarnAreErr</name>
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+        <option>
+          <name>CCCompilerRuntimeInfo</name>
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+          <state>1</state>
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+        <option>
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+          <state>$FILE_BNAME$.o</state>
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+        <option>
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+          <state>1</state>
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+        <option>
+          <name>PreInclude</name>
+          <state></state>
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+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL</state>
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+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
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+          <name>CCOptLevel</name>
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+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IccRTTI</name>
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+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <group>
+    <name>Doc</name>
+    <file>
+      <name>$PROJ_DIR$\..\readme.txt</name>
+    </file>
+  </group>
+  <group>
+    <name>STM32F10x</name>
+    <excluded>
+      <configuration>STM32L152_EVAL</configuration>
+      <configuration>STM32L152D_EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_hd.s</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_xl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\src\system_stm32f10x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM3210B_EVAL</name>
+      <excluded>
+        <configuration>STM3210E-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM3210E_EVAL</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F10x_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM32L152_EVAL</configuration>
+        <configuration>STM32L152D_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F30x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152_EVAL</configuration>
+      <configuration>STM32L152D_EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\iar\startup_stm32f30x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f30x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32303C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F30x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F37x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152_EVAL</configuration>
+      <configuration>STM32L152D_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\iar\startup_stm32f37x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f37x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32373C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F37x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_mdp.s</name>
+        <excluded>
+          <configuration>STM32L152_EVAL</configuration>
+          <configuration>STM32L152D_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\src\system_stm32l1xx.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.eww
new file mode 100644
index 0000000..d162f4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/SysTick.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\SysTick.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-SysTick</name>
+      <member>
+        <project>SysTick</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>SysTick</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>SysTick</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>SysTick</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>SysTick</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32f10x_flash_offset.icf
index 1efdb2b..464f800 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/EWARM/stm32f10x_flash_offset.icf
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32f10x_flash_offset.icf
@@ -4,7 +4,7 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x08003000;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x08003000 ;
+define symbol __ICFEDIT_region_ROM_start__   = 0x08003000;
 define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
 define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
 define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32f30x_flash_offset.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32f30x_flash_offset.icf
new file mode 100644
index 0000000..48a7502
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32f30x_flash_offset.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08003000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08003000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32l1xx_flash_offset.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32l1xx_flash_offset.icf
new file mode 100644
index 0000000..80c8d4a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/EWARM/stm32l1xx_flash_offset.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08003000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08003000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/MDK-ARM/SysTick.uvproj
index 302b754..72347a2 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/Project.uvproj
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/MDK-ARM/SysTick.uvproj
@@ -7,19 +7,19 @@
 
   <Targets>
     <Target>
-      <TargetName>STM32100E-EVAL</TargetName>
+      <TargetName>STM3210B-EVAL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F100ZE</Device>
+          <Device>STM32F103VB</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>STM32F100xE_lib.SFR</RegisterFile>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>4223</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -34,8 +34,8 @@
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>ST\STM32F100xE\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F100xE\</DBRegisterFilePath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -43,14 +43,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM32100E-EVAL\</OutputDirectory>
-          <OutputName>STM32100E-EVAL</OutputName>
+          <OutputDirectory>.\STM3210B-EVAL\</OutputDirectory>
+          <OutputName>STM3210B-EVAL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM32100E-EVAL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210B-EVAL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -61,6 +61,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -100,11 +102,11 @@
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
           <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments></SimDlgDllArguments>
+          <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments></TargetDlgDllArguments>
+          <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -193,7 +195,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M3"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -264,12 +266,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
+                <Size>0x5000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <Size>0x20000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -293,8 +295,8 @@
               </OCR_RVCT3>
               <OCR_RVCT4>
                 <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <StartAddress>0x8003000</StartAddress>
+                <Size>0x1e000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -319,7 +321,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x8000</Size>
+                <Size>0x5000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -344,9 +346,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL</Define>
+              <Define>USE_STM3210B_EVAL, STM32F10X_MD, USE_STDPERIPH_DRIVER</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL;..\..\..\Utilities\STM32_EVAL\Common</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -371,7 +373,7 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
@@ -387,169 +389,14 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_fsmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_usart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_sdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_bkp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
             </File>
             <File>
-              <FileName>stm32f10x_can.c</FileName>
+              <FileName>stm32f37x_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dbgmcu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_iwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_pwr.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_rtc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_wwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>core_cm3.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_stm32f10x.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\system_stm32f10x.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>STM32_EVAL</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32_eval.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\stm32_eval.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32_eval_spi_sd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32_eval_i2c_ee.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_ee.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -558,7 +405,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -591,63 +438,29 @@
               </FileOption>
             </File>
             <File>
-              <FileName>stm32_eval_i2c_tsensor.c</FileName>
+              <FileName>main.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c</FilePath>
+              <FilePath>..\src\main.c</FilePath>
             </File>
             <File>
-              <FileName>stm32_eval_sdio_sd.c</FileName>
+              <FileName>stm32_it.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_sdio_sd.c</FilePath>
-              <FileOption>
-                <CommonProperty>
-                  <UseCPPCompiler>2</UseCPPCompiler>
-                  <RVCTCodeConst>0</RVCTCodeConst>
-                  <RVCTZI>0</RVCTZI>
-                  <RVCTOtherData>0</RVCTOtherData>
-                  <ModuleSelection>0</ModuleSelection>
-                  <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
-                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
-                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
-                  <PublicsOnly>2</PublicsOnly>
-                  <StopOnExitCode>11</StopOnExitCode>
-                  <CustomArgument></CustomArgument>
-                  <IncludeLibraryModules></IncludeLibraryModules>
-                </CommonProperty>
-                <FileArmAds>
-                  <Cads>
-                    <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
-                    <Ropi>2</Ropi>
-                    <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define></Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
+              <FilePath>..\src\stm32_it.c</FilePath>
             </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
             <File>
-              <FileName>stm32_eval_spi_flash.c</FileName>
+              <FileName>system_stm32f10x.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c</FilePath>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
             </File>
             <File>
-              <FileName>stm3210b_eval_lcd.c</FileName>
+              <FileName>system_stm32l1xx.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_lcd.c</FilePath>
+              <FilePath>..\src\system_stm32l1xx.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -689,9 +502,9 @@
               </FileOption>
             </File>
             <File>
-              <FileName>stm3210e_eval_lcd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_lcd.c</FilePath>
+              <FileName>startup_stm32f10x_hd.s</FileName>
+              <FileType>2</FileType>
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+              <FileName>startup_stm32f30x.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_xl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\arm\startup_stm32f30x.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -1316,7 +957,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -1343,10 +984,747 @@
                 </FileArmAds>
               </FileOption>
             </File>
+          </Files>
+        </Group>
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             <File>
-              <FileName>startup_stm32f10x_hd_vl.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd_vl.s</FilePath>
+              <FileName>stm32f10x_usart.c</FileName>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
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+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -1356,25 +1734,25 @@
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
     <Target>
-      <TargetName>STM3210E-EVAL_XL</TargetName>
+      <TargetName>STM3210E-EVAL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F103ZG</Device>
+          <Device>STM32F103ZE</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
           <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
-          <DeviceId>5094</DeviceId>
+          <DeviceId>4216</DeviceId>
           <RegisterFile>stm32f10x_lib.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
@@ -1399,14 +1777,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM3210E-EVAL_XL\</OutputDirectory>
-          <OutputName>STM3210E-EVAL_XL</OutputName>
+          <OutputDirectory>.\STM3210E-EVAL\</OutputDirectory>
+          <OutputName>STM3210E-EVAL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210E-EVAL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -1417,6 +1795,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -1456,11 +1836,11 @@
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
           <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+          <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+          <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -1549,7 +1929,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M3"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -1620,12 +2000,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x18000</Size>
+                <Size>0x10000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x100000</Size>
+                <Size>0x80000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -1649,8 +2029,8 @@
               </OCR_RVCT3>
               <OCR_RVCT4>
                 <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x100000</Size>
+                <StartAddress>0x8003000</StartAddress>
+                <Size>0x7e000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -1675,7 +2055,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x18000</Size>
+                <Size>0x10000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -1700,9 +2080,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL</Define>
+              <Define>USE_STM3210E_EVAL, STM32F10X_HD, USE_STDPERIPH_DRIVER</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL;..\..\..\Utilities\STM32_EVAL\Common</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -1727,7 +2107,7 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
@@ -1743,208 +2123,14 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_fsmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_usart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_sdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_bkp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dbgmcu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_iwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_pwr.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
             </File>
             <File>
-              <FileName>stm32f10x_rtc.c</FileName>
+              <FileName>stm32f37x_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_wwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>core_cm3.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_stm32f10x.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\system_stm32f10x.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>STM32_EVAL</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32_eval.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\stm32_eval.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32_eval_spi_sd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c</FilePath>
-              <FileOption>
-                <CommonProperty>
-                  <UseCPPCompiler>2</UseCPPCompiler>
-                  <RVCTCodeConst>0</RVCTCodeConst>
-                  <RVCTZI>0</RVCTZI>
-                  <RVCTOtherData>0</RVCTOtherData>
-                  <ModuleSelection>0</ModuleSelection>
-                  <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
-                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
-                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
-                  <PublicsOnly>2</PublicsOnly>
-                  <StopOnExitCode>11</StopOnExitCode>
-                  <CustomArgument></CustomArgument>
-                  <IncludeLibraryModules></IncludeLibraryModules>
-                </CommonProperty>
-                <FileArmAds>
-                  <Cads>
-                    <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
-                    <Ropi>2</Ropi>
-                    <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define></Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-            <File>
-              <FileName>stm32_eval_i2c_ee.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_ee.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -1953,7 +2139,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -1986,24 +2172,29 @@
               </FileOption>
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+              <FilePath>..\src\system_stm32f37x.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -2642,28 +2612,33 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Aads>
+                  <Cads>
                     <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <thumb>2</thumb>
-                    <SplitLS>2</SplitLS>
-                    <SwStkChk>2</SwStkChk>
-                    <NoWarn>2</NoWarn>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Aads>
+                  </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_md_vl.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_md_vl.s</FilePath>
+              <FileName>system_stm32f30x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\system_stm32f30x.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -2672,7 +2647,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -2681,33 +2656,33 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Aads>
+                  <Cads>
                     <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <thumb>2</thumb>
-                    <SplitLS>2</SplitLS>
-                    <SwStkChk>2</SwStkChk>
-                    <NoWarn>2</NoWarn>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Aads>
+                  </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_xl.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_xl.s</FilePath>
-            </File>
-            <File>
-              <FileName>startup_stm32f10x_hd_vl.s</FileName>
+              <FileName>startup_stm32f30x.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\arm\startup_stm32f30x.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -2716,7 +2691,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -2746,30 +2721,772 @@
           </Files>
         </Group>
         <Group>
+          <GroupName>STM32F10x_StdPeriph_Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32f10x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_sdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L1xx_StdPeriph_Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l1xx_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l1xx_sdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_sdio.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32F37x_StdPeriph_Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32f37x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_spi.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32F30x_StdPeriph_Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32f30x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_can.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dac.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
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+          <GroupName>STM3210B-EVAL</GroupName>
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+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
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+                <OneElfS>2</OneElfS>
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+                <uThumb>2</uThumb>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210b_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210E-EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm3210e_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
           <GroupName>Doc</GroupName>
           <Files>
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
     <Target>
-      <TargetName>STM32100B-EVAL</TargetName>
+      <TargetName>STM3210E-EVAL_XL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F100VB</Device>
+          <Device>STM32F103ZG</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128_8k -FS08000000 -FL020000)</FlashDriverDll>
-          <DeviceId>0</DeviceId>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>5094</DeviceId>
           <RegisterFile>stm32f10x_lib.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
@@ -2794,14 +3511,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM32100B-EVAL\</OutputDirectory>
-          <OutputName>STM32100B-EVAL</OutputName>
+          <OutputDirectory>.\STM3210E-EVAL_XL\</OutputDirectory>
+          <OutputName>STM3210E-EVAL_XL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM32100B-EVAL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -2812,6 +3529,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -2851,11 +3570,11 @@
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
           <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pSTM32F100B</SimDlgDllArguments>
+          <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pSTM32F100B</TargetDlgDllArguments>
+          <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -2944,7 +3663,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M3"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -3015,12 +3734,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
+                <Size>0x18000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x20000</Size>
+                <Size>0x100000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -3044,8 +3763,8 @@
               </OCR_RVCT3>
               <OCR_RVCT4>
                 <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x20000</Size>
+                <StartAddress>0x8003000</StartAddress>
+                <Size>0xfe000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -3070,7 +3789,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
+                <Size>0x18000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -3095,9 +3814,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL</Define>
+              <Define>USE_STM3210E_EVAL, STM32F10X_HD, USE_STDPERIPH_DRIVER</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -3122,7 +3841,7 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
@@ -3138,169 +3857,14 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_fsmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_usart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_sdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_bkp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
             </File>
             <File>
-              <FileName>stm32f10x_can.c</FileName>
+              <FileName>stm32f37x_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dbgmcu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_iwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_pwr.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_rtc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c</FilePath>
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                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
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+              <FileName>system_stm32f37x.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_fsmc_onenand.c</FilePath>
+              <FilePath>..\src\system_stm32f37x.c</FilePath>
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@@ -3857,7 +4337,7 @@
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@@ -3890,9 +4370,9 @@
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               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_fsmc_sram.c</FilePath>
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-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s</FilePath>
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                   <PublicsOnly>2</PublicsOnly>
@@ -3977,244 +4452,747 @@
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+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_spi.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32F30x_StdPeriph_Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
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+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32f30x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_can.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dac.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210B-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210b_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210E-EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm3210e_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -4224,26 +5202,26 @@
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
     <Target>
-      <TargetName>STM3210C-EVAL</TargetName>
+      <TargetName>STM32L152-EVAL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F107VC</Device>
+          <Device>STM32L151VB</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000)</FlashDriverDll>
-          <DeviceId>4889</DeviceId>
-          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>5246</DeviceId>
+          <RegisterFile>stm32l1xx.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -4253,13 +5231,13 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile></SFDFile>
+          <SFDFile>SFD\ST\STM32L15x\STM32L15x.sfr</SFDFile>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -4267,14 +5245,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM3210C-EVAL\</OutputDirectory>
-          <OutputName>STM3210C-EVAL</OutputName>
+          <OutputDirectory>.\STM32L152-EVAL\</OutputDirectory>
+          <OutputName>STM32L152-EVAL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM3210C-EVAL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM32L152-EVAL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -4285,6 +5263,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -4323,12 +5303,12 @@
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
-          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pSTM32F107VC</SimDlgDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
-          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pSTM32F107VC</TargetDlgDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -4387,7 +5367,7 @@
             <DriverSelection>4096</DriverSelection>
           </Flash1>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
+          <Flash3></Flash3>
           <Flash4></Flash4>
         </Utilities>
         <TargetArmAds>
@@ -4417,7 +5397,7 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M3"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
@@ -4488,12 +5468,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x4000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x40000</Size>
+                <Size>0x20000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -4517,8 +5497,8 @@
               </OCR_RVCT3>
               <OCR_RVCT4>
                 <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x40000</Size>
+                <StartAddress>0x8003000</StartAddress>
+                <Size>0x20000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -4543,7 +5523,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x4000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -4568,9 +5548,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL</Define>
+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_MD, USE_STM32L152_EVAL</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -4595,9 +5575,9 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
+            <ScatterFile>.\STM32L152-EVAL\STM32L152-EVAL.sct</ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>
@@ -4611,169 +5591,14 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_fsmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_usart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_sdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_bkp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dbgmcu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_iwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
             </File>
             <File>
-              <FileName>stm32f10x_pwr.c</FileName>
+              <FileName>stm32f37x_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_rtc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_tim.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_wwdg.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS</GroupName>
-          <Files>
-            <File>
-              <FileName>core_cm3.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_stm32f10x.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\system_stm32f10x.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>STM32_EVAL</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32_eval.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\stm32_eval.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32_eval_spi_sd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32_eval_i2c_ee.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_ee.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -4782,7 +5607,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -4815,9 +5640,24 @@
               </FileOption>
             </File>
             <File>
-              <FileName>stm32_eval_i2c_tsensor.c</FileName>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_it.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c</FilePath>
+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -4826,7 +5666,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -4859,9 +5699,14 @@
               </FileOption>
             </File>
             <File>
-              <FileName>stm32_eval_sdio_sd.c</FileName>
+              <FileName>system_stm32l1xx.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_sdio_sd.c</FilePath>
+              <FilePath>..\src\system_stm32l1xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32f10x_hd.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -4870,7 +5715,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -4879,33 +5724,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>stm32_eval_spi_flash.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c</FilePath>
+              <FileName>startup_stm32f10x_ld.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -4914,7 +5754,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -4923,33 +5763,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>stm3210b_eval_lcd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_lcd.c</FilePath>
+              <FileName>startup_stm32f10x_ld_vl.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld_vl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -4967,33 +5802,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>stm3210e_eval_lcd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_lcd.c</FilePath>
+              <FileName>startup_stm32f10x_md.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_md.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5011,33 +5841,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>stm3210e_eval_fsmc_sram.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_sram.c</FilePath>
+              <FileName>startup_stm32f10x_md_vl.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_md_vl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5046,7 +5871,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5055,33 +5880,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>stm3210e_eval_fsmc_nand.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nand.c</FilePath>
+              <FileName>startup_stm32f10x_xl.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_xl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5090,7 +5910,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5099,33 +5919,28 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Cads>
+                  <Aads>
                     <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
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                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
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-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_fsmc_nor.c</FilePath>
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+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_hd.s</FilePath>
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@@ -5134,7 +5949,7 @@
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                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
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                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
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@@ -5143,43 +5958,33 @@
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                 </CommonProperty>
                 <FileArmAds>
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+                  <Aads>
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                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
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                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
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-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c</FilePath>
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+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_md.s</FilePath>
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-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL\stm32100b_eval_lcd.c</FilePath>
+              <FileName>startup_stm32l1xx_mdp.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_mdp.s</FilePath>
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@@ -5197,33 +6002,28 @@
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                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
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                       <MiscControls></MiscControls>
                       <Define></Define>
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                       <IncludePath></IncludePath>
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-                  </Cads>
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-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100B_EVAL\stm32100b_eval_cec.c</FilePath>
+              <FileName>startup_stm32f37x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\arm\startup_stm32f37x.s</FilePath>
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@@ -5232,7 +6032,7 @@
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-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
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@@ -5241,33 +6041,28 @@
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                 </CommonProperty>
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                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
+                    <thumb>2</thumb>
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                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Cads>
+                  </Aads>
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-              <FileName>stm32100e_eval_lcd.c</FileName>
+              <FileName>system_stm32f37x.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_lcd.c</FilePath>
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@@ -5309,9 +6104,9 @@
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+              <FileName>system_stm32f30x.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_ioe.c</FilePath>
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-              <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_cec.c</FilePath>
+              <FileName>startup_stm32f30x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\arm\startup_stm32f30x.s</FilePath>
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@@ -5364,7 +6159,7 @@
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@@ -5373,33 +6168,1171 @@
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-                    <wLevel>0</wLevel>
-                    <uThumb>2</uThumb>
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                       <MiscControls></MiscControls>
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                       <IncludePath></IncludePath>
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-                  </Cads>
+                  </Aads>
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               </FileOption>
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+          </Files>
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+          <GroupName>STM32F10x_StdPeriph_Driver</GroupName>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0xc000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x60000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x60000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0xc000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_HD, USE_STM32L152D_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08003000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>.\STM32L152-EVAL\STM32L152-EVAL.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
+            </File>
             <File>
-              <FileName>stm32100e_eval_fsmc_onenand.c</FileName>
+              <FileName>stm32f37x_misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_fsmc_onenand.c</FilePath>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5408,7 +7341,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5441,9 +7374,24 @@
               </FileOption>
             </File>
             <File>
-              <FileName>stm32100e_eval_fsmc_sram.c</FileName>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_it.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32100E_EVAL\stm32100e_eval_fsmc_sram.c</FilePath>
+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5452,7 +7400,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5484,20 +7432,15 @@
                 </FileArmAds>
               </FileOption>
             </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>MDK-ARM</GroupName>
-          <Files>
             <File>
-              <FileName>startup_stm32f10x_cl.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s</FilePath>
+              <FileName>system_stm32l1xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32l1xx.c</FilePath>
             </File>
             <File>
               <FileName>startup_stm32f10x_hd.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5506,7 +7449,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5536,7 +7479,7 @@
             <File>
               <FileName>startup_stm32f10x_ld.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_ld.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5545,7 +7488,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5575,7 +7518,7 @@
             <File>
               <FileName>startup_stm32f10x_ld_vl.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_ld_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld_vl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5584,7 +7527,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5614,7 +7557,7 @@
             <File>
               <FileName>startup_stm32f10x_md.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_md.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_md.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5623,7 +7566,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5653,7 +7596,7 @@
             <File>
               <FileName>startup_stm32f10x_md_vl.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_md_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_md_vl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5662,7 +7605,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5692,7 +7635,51 @@
             <File>
               <FileName>startup_stm32f10x_xl.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_xl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_xl.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>startup_stm32l1xx_hd.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_hd.s</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32l1xx_md.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_md.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5729,9 +7716,175 @@
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_hd_vl.s</FileName>
+              <FileName>startup_stm32l1xx_mdp.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_mdp.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>startup_stm32f37x.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\arm\startup_stm32f37x.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <thumb>2</thumb>
+                    <SplitLS>2</SplitLS>
+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>system_stm32f37x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f37x.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
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+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
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+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>system_stm32f30x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\system_stm32f30x.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
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+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
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+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
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+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>startup_stm32f30x.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\arm\startup_stm32f30x.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -5740,7 +7893,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -5770,31 +7923,773 @@
           </Files>
         </Group>
         <Group>
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+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
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+              <StopOnExitCode>11</StopOnExitCode>
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+                  <Define></Define>
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+                <Ropi>2</Ropi>
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+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
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+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
+            </File>
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+              <FileName>stm32f10x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
+            </File>
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+              <FileName>stm32f10x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
+            </File>
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+              <FileName>stm32f10x_sdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
+            </File>
+          </Files>
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+          <GroupName>STM32L1xx_StdPeriph_Driver</GroupName>
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+            <File>
+              <FileName>stm32l1xx_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</FilePath>
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+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_sdio.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_usart.c</FilePath>
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+            <File>
+              <FileName>stm3210b_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210E-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210e_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
           <GroupName>Doc</GroupName>
           <Files>
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
     <Target>
-      <TargetName>STM3210E-EVAL</TargetName>
+      <TargetName>STM32373C_EVAL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F103ZE</Device>
+          <Device>STM32F373VCT6</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4")ESEL ELITTLE FPU2</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
-          <DeviceId>4216</DeviceId>
-          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <StartupFile>"STARTUP\ARM\startup_MPS_CM0.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M4") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile></RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -5809,8 +8704,8 @@
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>++ST\STM32F10x\</RegisterFilePath>
-          <DBRegisterFilePath>++ST\STM32F10x\</DBRegisterFilePath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -5818,14 +8713,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM3210E-EVAL\</OutputDirectory>
-          <OutputName>STM3210E-EVAL</OutputName>
+          <OutputDirectory>.\STM32373C_EVAL\</OutputDirectory>
+          <OutputName>STM32373C_EVAL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM3210E-EVAL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM32373C_EVAL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -5836,6 +8731,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -5875,11 +8772,11 @@
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
           <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+          <SimDlgDllArguments></SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+          <TargetDlgDllArguments></TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -5935,10 +8832,10 @@
             <RunIndependent>0</RunIndependent>
             <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
             <Capability>1</Capability>
-            <DriverSelection>4097</DriverSelection>
+            <DriverSelection>4096</DriverSelection>
           </Flash1>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3></Flash3>
+          <Flash3>"" ()</Flash3>
           <Flash4></Flash4>
         </Utilities>
         <TargetArmAds>
@@ -5968,9 +8865,9 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
@@ -5979,12 +8876,12 @@
             <hadIRAM>1</hadIRAM>
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
+            <RvdsVP>2</RvdsVP>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
             <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
+            <EndSel>1</EndSel>
             <uLtcg>0</uLtcg>
             <RoSelD>3</RoSelD>
             <RwSelD>3</RwSelD>
@@ -6039,12 +8936,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x8000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <Size>0x40000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -6069,7 +8966,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x80000</Size>
+                <Size>0x40000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -6094,7 +8991,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
+                <Size>0x8000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -6119,9 +9016,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL</Define>
+              <Define>USE_STDPERIPH_DRIVER, STM32F37X, USE_STM32373C_EVAL</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include;..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -6146,9 +9043,9 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
+            <ScatterFile>.\STM32L152-EVAL\STM32L152-EVAL.sct</ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>
@@ -6162,164 +9059,9 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_exti.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_spi.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_fsmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_usart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_sdio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_adc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_bkp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_can.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_cec.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_crc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dac.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_dbgmcu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c</FilePath>
-            </File>
-            <File>
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                   <PublicsOnly>2</PublicsOnly>
@@ -6924,14 +9406,9 @@
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-              <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s</FilePath>
-            </File>
-            <File>
-              <FileName>startup_stm32f10x_ld.s</FileName>
+              <FileName>startup_stm32f10x_xl.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_ld.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_xl.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -6940,7 +9417,7 @@
                   <RVCTOtherData>0</RVCTOtherData>
                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -6968,9 +9445,9 @@
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_ld_vl.s</FileName>
+              <FileName>startup_stm32l1xx_hd.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_ld_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_hd.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -6979,7 +9456,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -7007,9 +9484,9 @@
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_md.s</FileName>
+              <FileName>startup_stm32l1xx_md.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_md.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_md.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -7018,7 +9495,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -7046,9 +9523,9 @@
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_md_vl.s</FileName>
+              <FileName>startup_stm32l1xx_mdp.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_md_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\arm\startup_stm32l1xx_mdp.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -7057,7 +9534,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -7085,9 +9562,19 @@
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             </File>
             <File>
-              <FileName>startup_stm32f10x_xl.s</FileName>
+              <FileName>startup_stm32f37x.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_xl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\arm\startup_stm32f37x.s</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f37x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f37x.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f30x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\system_stm32f30x.c</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -7105,28 +9592,33 @@
                   <IncludeLibraryModules></IncludeLibraryModules>
                 </CommonProperty>
                 <FileArmAds>
-                  <Aads>
+                  <Cads>
                     <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
                     <Ropi>2</Ropi>
                     <Rwpi>2</Rwpi>
-                    <thumb>2</thumb>
-                    <SplitLS>2</SplitLS>
-                    <SwStkChk>2</SwStkChk>
-                    <NoWarn>2</NoWarn>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
                     <VariousControls>
                       <MiscControls></MiscControls>
                       <Define></Define>
                       <Undefine></Undefine>
                       <IncludePath></IncludePath>
                     </VariousControls>
-                  </Aads>
+                  </Cads>
                 </FileArmAds>
               </FileOption>
             </File>
             <File>
-              <FileName>startup_stm32f10x_hd_vl.s</FileName>
+              <FileName>startup_stm32f30x.s</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd_vl.s</FilePath>
+              <FilePath>..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\arm\startup_stm32f30x.s</FilePath>
               <FileOption>
                 <CommonProperty>
                   <UseCPPCompiler>2</UseCPPCompiler>
@@ -7135,7 +9627,7 @@
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                   <ModuleSelection>0</ModuleSelection>
                   <IncludeInBuild>0</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
                   <GenerateAssemblyFile>2</GenerateAssemblyFile>
                   <AssembleAssemblyFile>2</AssembleAssemblyFile>
                   <PublicsOnly>2</PublicsOnly>
@@ -7165,31 +9657,773 @@
           </Files>
         </Group>
         <Group>
+          <GroupName>STM32F10x_StdPeriph_Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
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+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32f10x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f10x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</FilePath>
+            </File>
+          </Files>
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+          <GroupName>STM32L1xx_StdPeriph_Driver</GroupName>
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+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
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+                <uThumb>2</uThumb>
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+                <Ropi>2</Ropi>
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+                  <IncludePath></IncludePath>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</FilePath>
+            </File>
+            <File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_sdio.c</FilePath>
+            </File>
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+          <GroupName>STM32F37x_StdPeriph_Driver</GroupName>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</FilePath>
+            </File>
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+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dac.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</FilePath>
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+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210B-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210b_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210E-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210e_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
           <GroupName>Doc</GroupName>
           <Files>
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
     <Target>
-      <TargetName>STM3210B-EVAL</TargetName>
+      <TargetName>STM32303C_EVAL</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
       <TargetOption>
         <TargetCommonOption>
-          <Device>STM32F103VB</Device>
+          <Device>STM32F303VC</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4")ESEL ELITTLE FPU2</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
-          <DeviceId>4223</DeviceId>
-          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <StartupFile>"STARTUP\ARM\startup_MPS_CM4.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M4") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile></RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -7204,8 +10438,8 @@
           <BinPath></BinPath>
           <IncludePath></IncludePath>
           <LibPath></LibPath>
-          <RegisterFilePath>++ST\STM32F10x\</RegisterFilePath>
-          <DBRegisterFilePath>++ST\STM32F10x\</DBRegisterFilePath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -7213,14 +10447,14 @@
             <NotGenerated>0</NotGenerated>
             <InvalidFlash>1</InvalidFlash>
           </TargetStatus>
-          <OutputDirectory>.\STM3210B-EVAL\</OutputDirectory>
-          <OutputName>STM3210B-EVAL</OutputName>
+          <OutputDirectory>.\STM32303C_EVAL\</OutputDirectory>
+          <OutputName>STM32303C_EVAL</OutputName>
           <CreateExecutable>1</CreateExecutable>
           <CreateLib>0</CreateLib>
           <CreateHexFile>0</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\STM3210B-EVAL\</ListingPath>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM32303C_EVAL\</ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
           <CreateBatchFile>0</CreateBatchFile>
@@ -7231,6 +10465,8 @@
             <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
           </BeforeCompile>
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
@@ -7270,11 +10506,11 @@
           <SimDllName>SARMCM3.DLL</SimDllName>
           <SimDllArguments></SimDllArguments>
           <SimDlgDll>DARMSTM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+          <SimDlgDllArguments></SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
           <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+          <TargetDlgDllArguments></TargetDlgDllArguments>
         </DllOption>
         <DebugOption>
           <OPTHX>
@@ -7333,7 +10569,7 @@
             <DriverSelection>4096</DriverSelection>
           </Flash1>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
+          <Flash3></Flash3>
           <Flash4></Flash4>
         </Utilities>
         <TargetArmAds>
@@ -7363,9 +10599,9 @@
             <AdsLsun>1</AdsLsun>
             <AdsLven>1</AdsLven>
             <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
+            <RvctClst>1</RvctClst>
             <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
@@ -7374,12 +10610,12 @@
             <hadIRAM>1</hadIRAM>
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
+            <RvdsVP>2</RvdsVP>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
             <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
+            <EndSel>1</EndSel>
             <uLtcg>0</uLtcg>
             <RoSelD>3</RoSelD>
             <RwSelD>3</RwSelD>
@@ -7434,12 +10670,12 @@
               <IRAM>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x5000</Size>
+                <Size>0x8000</Size>
               </IRAM>
               <IROM>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x20000</Size>
+                <Size>0x40000</Size>
               </IROM>
               <XRAM>
                 <Type>0</Type>
@@ -7464,7 +10700,7 @@
               <OCR_RVCT4>
                 <Type>1</Type>
                 <StartAddress>0x8000000</StartAddress>
-                <Size>0x20000</Size>
+                <Size>0x40000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -7489,7 +10725,7 @@
               <OCR_RVCT9>
                 <Type>0</Type>
                 <StartAddress>0x20000000</StartAddress>
-                <Size>0x5000</Size>
+                <Size>0x8000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -7514,9 +10750,9 @@
             <uThumb>0</uThumb>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL</Define>
+              <Define>USE_STDPERIPH_DRIVER, STM32F30X, USE_STM32303C_EVAL</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\Libraries\CMSIS\CM3\CoreSupport;..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL;..\..\..\Utilities\STM32_EVAL\Common</IncludePath>
+              <IncludePath>..\inc;..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include;..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc;..\..\..\..\Utilities\STM32_EVAL\Common;..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -7541,9 +10777,9 @@
             <noStLib>0</noStLib>
             <RepFail>1</RepFail>
             <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
+            <TextAddressRange>0x08003000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
+            <ScatterFile>.\STM32L152-EVAL\STM32L152-EVAL.sct</ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
             <Misc></Misc>
@@ -7557,218 +10793,9 @@
           <GroupName>User</GroupName>
           <Files>
             <File>
-              <FileName>stm32f10x_it.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\stm32f10x_it.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>StdPeriph_Driver</GroupName>
-          <Files>
-            <File>
-              <FileName>stm32f10x_rcc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32f10x_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</FilePath>
-            </File>
-            <File>
               <FileName>misc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
-            </File>
-            <File>
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+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32f37x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f37x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_spi.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32F30x_StdPeriph_Driver</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32f30x_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_can.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dac.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f30x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210B-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210b_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM3210E-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm3210e_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32L152D-EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32l152d_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32373C_EVAL</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
@@ -8682,7 +12177,7 @@
             <File>
               <FileName>readme.txt</FileName>
               <FileType>5</FileType>
-              <FilePath>.\readme.txt</FilePath>
+              <FilePath>..\readme.txt</FilePath>
             </File>
           </Files>
         </Group>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/SysTick.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/SysTick.rprj
new file mode 100644
index 0000000..0204755
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/SysTick.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'SysTick'" Path=".\SysTick.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="SysTick" >
+	<ApplicationBuild Header="SysTick" Extern=".\SysTick.rapp" Path=".\SysTick.rapp" OutputFile=".\STM32F303C_EVAL\SysTick.elf" sate="98" Config="STM32F303C_EVAL" />
+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_md_flash_offset.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_md_flash_offset.ld
new file mode 100644
index 0000000..457a3ed
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_md_flash_offset.ld
@@ -0,0 +1,242 @@
+/*
+Default linker script for STM32F10x_128_20K
+Copyright RAISONANCE S.A.S. 2008
+*/
+
+/* include the common STM32F10x sub-script */
+
+/* Common part of the linker scripts for STM32 devices*/
+
+
+/* default stack sizes. 
+
+These are used by the startup in order to allocate stacks for the different modes.
+*/
+
+__Stack_Size = 1024 ;
+
+PROVIDE ( _Stack_Size = __Stack_Size ) ;
+
+__Stack_Init = _estack  - __Stack_Size ;
+
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
+PROVIDE ( _Stack_Init = __Stack_Init ) ;
+
+/*
+There will be a link error if there is not this amount of RAM free at the end.
+*/
+_Minimum_Stack_Size = 0x100 ;
+
+
+/* include the memory spaces definitions sub-script */
+/*
+Linker subscript for STM32F10x definitions with 128K Flash and 20K RAM */
+
+/* Memory Spaces Definitions */
+
+MEMORY
+{
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+  FLASH (rx) : ORIGIN = 0x8003000, LENGTH = 128K-0x3000
+  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/* higher address of the user mode stack */
+_estack = 0x20005000;
+
+
+
+/* include the sections management sub-script for FLASH mode */
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
+    .isr_vector :
+    {
+	. = ALIGN(4);
+        KEEP(*(.isr_vector))            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+  
+    .flashtext :
+    {
+	. = ALIGN(4);
+        *(.flashtext)            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+    
+    /* the program code is stored in the .text section, which goes to Flash */
+    .text :
+    {
+	    . = ALIGN(4);
+	    
+        *(.text)                   /* remaining code */
+        *(.text.*)                   /* remaining code */
+        *(.rodata)                 /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+
+	    . = ALIGN(4);
+   	 _etext = .;
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _sidata = _etext;
+    } >FLASH
+    
+ 
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data  : AT ( _sidata )
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+        
+        *(.data)
+        *(.data.*)
+
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _edata = . ;
+    } >RAM
+    
+    
+
+    /* This is the uninitialized data section */
+    .bss :
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+        
+        *(.bss)
+        *(COMMON)
+        
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .bss secion */
+   	 _ebss = . ;
+    } >RAM
+    
+    PROVIDE ( end = _ebss );
+    PROVIDE ( _end = _ebss );
+    
+    /* This is the user stack section 
+    This is just to check that there is enough RAM left for the User mode stack
+    It should generate an error if it's full.
+     */
+    ._usrstack :
+    {
+	    . = ALIGN(4);
+        _susrstack = . ;
+        
+        . = . + _Minimum_Stack_Size ;
+        
+	    . = ALIGN(4);
+        _eusrstack = . ;
+    } >RAM
+    
+
+   
+    /* this is the FLASH Bank1 */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    .b1text :
+    {
+        *(.b1text)                   /* remaining code */
+        *(.b1rodata)                 /* read-only data (constants) */
+        *(.b1rodata*)
+    } >FLASHB1
+    
+    /* this is the EXTMEM */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    
+    /* EXTMEM Bank0 */
+    .eb0text :
+    {
+        *(.eb0text)                   /* remaining code */
+        *(.eb0rodata)                 /* read-only data (constants) */
+        *(.eb0rodata*)
+    } >EXTMEMB0
+    
+    /* EXTMEM Bank1 */
+    .eb1text :
+    {
+        *(.eb1text)                   /* remaining code */
+        *(.eb1rodata)                 /* read-only data (constants) */
+        *(.eb1rodata*)
+    } >EXTMEMB1
+    
+    /* EXTMEM Bank2 */
+    .eb2text :
+    {
+        *(.eb2text)                   /* remaining code */
+        *(.eb2rodata)                 /* read-only data (constants) */
+        *(.eb2rodata*)
+    } >EXTMEMB2
+    
+    /* EXTMEM Bank0 */
+    .eb3text :
+    {
+        *(.eb3text)                   /* remaining code */
+        *(.eb3rodata)                 /* read-only data (constants) */
+        *(.eb3rodata*)
+    } >EXTMEMB3
+    
+    
+    
+    /* after that it's only debugging information. */
+    
+    /* remove the debugging information from the standard libraries */
+    DISCARD :
+    {
+     libc.a ( * )
+     libm.a ( * )
+     libgcc.a ( * )
+     }
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_xl_flash_offset.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_xl_flash_offset.ld
new file mode 100644
index 0000000..3710a92
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f10x_xl_flash_offset.ld
@@ -0,0 +1,242 @@
+/*
+Default linker script for STM32F10x_1024_96K
+Copyright RAISONANCE S.A.S. 2008
+*/
+
+/* include the common STM32F10x sub-script */
+
+/* Common part of the linker scripts for STM32 devices*/
+
+
+/* default stack sizes. 
+
+These are used by the startup in order to allocate stacks for the different modes.
+*/
+
+__Stack_Size = 1024 ;
+
+PROVIDE ( _Stack_Size = __Stack_Size ) ;
+
+__Stack_Init = _estack  - __Stack_Size ;
+
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
+PROVIDE ( _Stack_Init = __Stack_Init ) ;
+
+/*
+There will be a link error if there is not this amount of RAM free at the end.
+*/
+_Minimum_Stack_Size = 0x100 ;
+
+
+/* include the memory spaces definitions sub-script */
+/*
+Linker subscript for STM32F10x definitions with 1024k Flash and 96K RAM */
+
+/* Memory Spaces Definitions */
+
+MEMORY
+{
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
+  FLASH (rx) : ORIGIN = 0x8003000, LENGTH = 1024K-0x3000
+  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/* higher address of the user mode stack */
+_estack = 0x20018000;
+
+
+
+/* include the sections management sub-script for FLASH mode */
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
+    .isr_vector :
+    {
+	. = ALIGN(4);
+        KEEP(*(.isr_vector))            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+  
+    .flashtext :
+    {
+	. = ALIGN(4);
+        *(.flashtext)            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+    
+    /* the program code is stored in the .text section, which goes to Flash */
+    .text :
+    {
+	    . = ALIGN(4);
+	    
+        *(.text)                   /* remaining code */
+        *(.text.*)                   /* remaining code */
+        *(.rodata)                 /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+
+	    . = ALIGN(4);
+   	 _etext = .;
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _sidata = _etext;
+    } >FLASH
+    
+ 
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data  : AT ( _sidata )
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+        
+        *(.data)
+        *(.data.*)
+
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _edata = . ;
+    } >RAM
+    
+    
+
+    /* This is the uninitialized data section */
+    .bss :
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+        
+        *(.bss)
+        *(COMMON)
+        
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .bss secion */
+   	 _ebss = . ;
+    } >RAM
+    
+    PROVIDE ( end = _ebss );
+    PROVIDE ( _end = _ebss );
+    
+    /* This is the user stack section 
+    This is just to check that there is enough RAM left for the User mode stack
+    It should generate an error if it's full.
+     */
+    ._usrstack :
+    {
+	    . = ALIGN(4);
+        _susrstack = . ;
+        
+        . = . + _Minimum_Stack_Size ;
+        
+	    . = ALIGN(4);
+        _eusrstack = . ;
+    } >RAM
+    
+
+   
+    /* this is the FLASH Bank1 */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    .b1text :
+    {
+        *(.b1text)                   /* remaining code */
+        *(.b1rodata)                 /* read-only data (constants) */
+        *(.b1rodata*)
+    } >FLASHB1
+    
+    /* this is the EXTMEM */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    
+    /* EXTMEM Bank0 */
+    .eb0text :
+    {
+        *(.eb0text)                   /* remaining code */
+        *(.eb0rodata)                 /* read-only data (constants) */
+        *(.eb0rodata*)
+    } >EXTMEMB0
+    
+    /* EXTMEM Bank1 */
+    .eb1text :
+    {
+        *(.eb1text)                   /* remaining code */
+        *(.eb1rodata)                 /* read-only data (constants) */
+        *(.eb1rodata*)
+    } >EXTMEMB1
+    
+    /* EXTMEM Bank2 */
+    .eb2text :
+    {
+        *(.eb2text)                   /* remaining code */
+        *(.eb2rodata)                 /* read-only data (constants) */
+        *(.eb2rodata*)
+    } >EXTMEMB2
+    
+    /* EXTMEM Bank0 */
+    .eb3text :
+    {
+        *(.eb3text)                   /* remaining code */
+        *(.eb3rodata)                 /* read-only data (constants) */
+        *(.eb3rodata*)
+    } >EXTMEMB3
+    
+    
+    
+    /* after that it's only debugging information. */
+    
+    /* remove the debugging information from the standard libraries */
+    DISCARD :
+    {
+     libc.a ( * )
+     libm.a ( * )
+     libgcc.a ( * )
+     }
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f37x_flash_offset.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f37x_flash_offset.ld
new file mode 100644
index 0000000..27d3b3b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/RIDE/stm32f37x_flash_offset.ld
@@ -0,0 +1,242 @@
+/*
+Default linker script for STM32F37x_256K_32K
+Copyright RAISONANCE S.A.S. 2008
+*/
+
+/* include the common STM32F37x sub-script */
+
+/* Common part of the linker scripts for STM32 devices*/
+
+
+/* default stack sizes. 
+
+These are used by the startup in order to allocate stacks for the different modes.
+*/
+
+__Stack_Size = 1024 ;
+
+PROVIDE ( _Stack_Size = __Stack_Size ) ;
+
+__Stack_Init = _estack  - __Stack_Size ;
+
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
+PROVIDE ( _Stack_Init = __Stack_Init ) ;
+
+/*
+There will be a link error if there is not this amount of RAM free at the end.
+*/
+_Minimum_Stack_Size = 0x100 ;
+
+
+/* include the memory spaces definitions sub-script */
+/*
+Linker subscript for STM32F37x definitions with 256K Flash and 32K RAM */
+
+/* Memory Spaces Definitions */
+
+MEMORY
+{
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+  FLASH (rx) : ORIGIN = 0x8003000, LENGTH = 256K-0x3000
+  FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+  EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
+}
+
+/* higher address of the user mode stack */
+_estack = 0x20008000;
+
+
+
+/* include the sections management sub-script for FLASH mode */
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
+    .isr_vector :
+    {
+	. = ALIGN(4);
+        KEEP(*(.isr_vector))            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+  
+    .flashtext :
+    {
+	. = ALIGN(4);
+        *(.flashtext)            /* Startup code */
+	. = ALIGN(4);
+    } >FLASH
+ 
+    
+    /* the program code is stored in the .text section, which goes to Flash */
+    .text :
+    {
+	    . = ALIGN(4);
+	    
+        *(.text)                   /* remaining code */
+        *(.text.*)                   /* remaining code */
+        *(.rodata)                 /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+
+	    . = ALIGN(4);
+   	 _etext = .;
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _sidata = _etext;
+    } >FLASH
+    
+ 
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data  : AT ( _sidata )
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+        
+        *(.data)
+        *(.data.*)
+
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .data secion */
+   	 _edata = . ;
+    } >RAM
+    
+    
+
+    /* This is the uninitialized data section */
+    .bss :
+    {
+	    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+        
+        *(.bss)
+        *(COMMON)
+        
+	    . = ALIGN(4);
+	    /* This is used by the startup in order to initialize the .bss secion */
+   	 _ebss = . ;
+    } >RAM
+    
+    PROVIDE ( end = _ebss );
+    PROVIDE ( _end = _ebss );
+    
+    /* This is the user stack section 
+    This is just to check that there is enough RAM left for the User mode stack
+    It should generate an error if it's full.
+     */
+    ._usrstack :
+    {
+	    . = ALIGN(4);
+        _susrstack = . ;
+        
+        . = . + _Minimum_Stack_Size ;
+        
+	    . = ALIGN(4);
+        _eusrstack = . ;
+    } >RAM
+    
+
+   
+    /* this is the FLASH Bank1 */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    .b1text :
+    {
+        *(.b1text)                   /* remaining code */
+        *(.b1rodata)                 /* read-only data (constants) */
+        *(.b1rodata*)
+    } >FLASHB1
+    
+    /* this is the EXTMEM */
+    /* the C or assembly source must explicitly place the code or data there
+    using the "section" attribute */
+    
+    /* EXTMEM Bank0 */
+    .eb0text :
+    {
+        *(.eb0text)                   /* remaining code */
+        *(.eb0rodata)                 /* read-only data (constants) */
+        *(.eb0rodata*)
+    } >EXTMEMB0
+    
+    /* EXTMEM Bank1 */
+    .eb1text :
+    {
+        *(.eb1text)                   /* remaining code */
+        *(.eb1rodata)                 /* read-only data (constants) */
+        *(.eb1rodata*)
+    } >EXTMEMB1
+    
+    /* EXTMEM Bank2 */
+    .eb2text :
+    {
+        *(.eb2text)                   /* remaining code */
+        *(.eb2rodata)                 /* read-only data (constants) */
+        *(.eb2rodata*)
+    } >EXTMEMB2
+    
+    /* EXTMEM Bank0 */
+    .eb3text :
+    {
+        *(.eb3text)                   /* remaining code */
+        *(.eb3rodata)                 /* read-only data (constants) */
+        *(.eb3rodata*)
+    } >EXTMEMB3
+    
+    
+    
+    /* after that it's only debugging information. */
+    
+    /* remove the debugging information from the standard libraries */
+    DISCARD :
+    {
+     libc.a ( * )
+     libm.a ( * )
+     libgcc.a ( * )
+     }
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..652d200
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.cproject
@@ -0,0 +1,136 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
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+									<listOptionValue builtIn="false" value="560"/>
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+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1054603186" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
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+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_md.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.outputFormat.ihex.2055967825" superClass="com.tasking.arm.lk.outputFormat.ihex" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler v4.3r1 Build 683 SN 00123456</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker v4.3r1 Build 142 SN 00123456</toolInfo>
+			</storageModule>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
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+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
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+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
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+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..04775cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
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new file mode 100644
index 0000000..f167045
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+:2032400003001860186850F002001860186810F00C000828FAD15FF000605FF0E021C1F87A
+:06326000080D02B07047EA
+:20326800F0B403460A46906810F00F0410F0100F1CBF50680443108810F0FF0F1DD01D68ED
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+:2033E80025006946FFF73CFF03B030BD08000020DFF824F0DFF824D0FFF7AEFEFFF7B4FFF7
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+:2034280000300008064901F1000252F8202001F1100131F8100052F80C3F43401360704701
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+:2034680041F21802C4F2020211B11168014301E0116881431160704704480168002908BFD3
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+:2034A800080D70470249086008680028FCD17047000000205FF000605FF44051FFF7E8BF19
+:0634C800FFF7DABF7047B8
+:0234D000FEE715
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+:0234D800FEE70D
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+:2034EC00010000000000002030310008300000000000000000000000000000000000000006
+:04000005080033F9C3
+:00000001FF
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..3c59ebf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..956503e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.outputFormat.ihex.1437528190" name="Generate Intel Hex format file" superClass="com.tasking.arm.lk.outputFormat.ihex" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker v4.3r1 Build 142 SN 00123456</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.hex b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.hex
new file mode 100644
index 0000000..a83b8d3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.hex
@@ -0,0 +1,52 @@
+:020000040800F2
+:2030000000000120F9330008CD340008D1340008D5340008D9340008DD3400081C300008B2
+:20302000203000082430000828300008E1340008E534000834300008E9340008C9340008A8
+:203040004030000844300008483000084C3000085030000854300008583000085C30000840
+:203060006030000864300008683000086C3000087030000874300008783000087C30000820
+:203080008030000884300008883000088C3000089030000894300008983000089C30000800
+:2030A000A0300008A4300008A8300008AC300008B0300008B4300008B8300008BC300008E0
+:2030C000C0300008C4300008C8300008CC300008D0300008D4300008D8300008DC300008C0
+:2030E000E0300008E4300008E8300008EC300008F0300008F4300008F8300008FC300008A0
+:203100000031000804310008083100080C3100081031000814310008183100081C31000877
+:203120002031000824310008283100082C3100080000000000A24A04001C0140001C014069
+:20314000001C0140001C0140400080000001000280000000800000008000000080000000F2
+:2031600041F20002C4F20202106841F2040350F001001060C4F2020340F20001CFF6FF014A
+:2031800018680840186041F20801C4F20201106830F0847030F480301060106830F48020EE
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+:2034F000010000000000002030310008300000000000000000000000000000000000000002
+:04000005080033F9C3
+:00000001FF
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..547d59a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E.dfu
new file mode 100644
index 0000000..935edbc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/STM3210E.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
new file mode 100644
index 0000000..1c37d81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 512k;
+    map ( size = 512k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                       vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                      /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..61ef849
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL_XL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103zg" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1715575623" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.387783740" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_XL.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.outputFormat.ihex.1083544675" name="Generate Intel Hex format file" superClass="com.tasking.arm.lk.outputFormat.ihex" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.hex b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.hex
new file mode 100644
index 0000000..dc4a397
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.hex
@@ -0,0 +1,52 @@
+:020000040800F2
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
new file mode 100644
index 0000000..252b6cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL_XL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..4d36fd1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning"/>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.lk.outputFormat.ihex.1124934211" name="Generate Intel Hex format file" superClass="com.tasking.arm.lk.outputFormat.ihex" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler v4.3r1 Build 683 SN 00123456</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker v4.3r1 Build 142 SN 00123456</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..648f319
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32303C_EVAL.hex b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32303C_EVAL.hex
new file mode 100644
index 0000000..45b8115
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32303C_EVAL.hex
@@ -0,0 +1,55 @@
+:020000040800F2
+:2030000000A000206134000835350008393500083D35000841350008453500081C3000089D
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+:04000005080034615A
+:00000001FF
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32F30.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32F30.dfu
new file mode 100644
index 0000000..b072179
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/STM32F30.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
new file mode 100644
index 0000000..642584a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f30x.lsl
+//
+//  Version     :  @(#)stm32f30x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F30x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F30x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       6k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+
+memory STM32F30x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE - 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM8k
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    priority = 1;
+    map ( size = 8k, dest_offset=0x10000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2 interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2 global interrupts
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB Device High Priority or CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );      // USB Device Low Priority or CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break irq and TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );        // TIM1 Update irq and TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation irqs and TIM17 global irq
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup interrupt
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break interrupt
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update interrupt
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 trigger and Comm. interrupt
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare interrupt
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4 global interrupt
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "ADC4_IRQHandler" );                 // ADC4 global interrupt
+                        vector ( id = 80, optional, fill = "COMP1_2_3_IRQHandler" );            // COMP1, COMP2 and COMP3 global interrupt
+                        vector ( id = 81, optional, fill = "COMP4_5_6_IRQHandler" );            // COMP5, COMP6 and COMP4 global interrupt
+                        vector ( id = 82, optional, fill = "COMP7_IRQHandler" );                // COMP7 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt  remap
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt  remap
+                        vector ( id = 92, optional, fill = "USBWakeUp_RMP_IRQHandler" );        // USB Wakeup Interrupt remap
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.cproject
new file mode 100644
index 0000000..d785589
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.cproject
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32373C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f373vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F37X"/>
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning"/>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f37x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.lk.outputFormat.ihex.1065186900" name="Generate Intel Hex format file" superClass="com.tasking.arm.lk.outputFormat.ihex" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler v4.3r1 Build 683 SN 00123456</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker v4.3r1 Build 142 SN 00123456</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.project
new file mode 100644
index 0000000..9096c12
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/.project
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32373C_EVAL.hex b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32373C_EVAL.hex
new file mode 100644
index 0000000..4cf8410
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+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32373C_EVAL.hex
@@ -0,0 +1,54 @@
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32F37.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32F37.dfu
new file mode 100644
index 0000000..8b57b97
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/STM32F37.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..38945e9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.hex b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.hex
new file mode 100644
index 0000000..8f35914
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.hex
@@ -0,0 +1,54 @@
+:020000040800F2
+:20300000004000203D340008193500081D3500082135000825350008293500081C300008AD
+:203020002030000824300008283000082D3500083135000834300008353500081535000874
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+:203080008030000884300008883000088C3000089030000894300008983000089C30000800
+:2030A000A0300008A4300008A8300008AC300008B0300008B4300008B8300008BC300008E0
+:2030C000C0300008C4300008C8300008CC300008D0300008D4300008D8300008DC300008C0
+:2030E000E0300008E4300008E8300008EC300008F0300008F4300008F8300008FC300008A0
+:203100000031000804310008083100080C3100081031000814310008183100081C31000877
+:203120002031000824310008283100082C3100083031000834310008383100083C31000857
+:203140004031000844310008483100084C310008000000000048E801000C0240000C0240A6
+:20316000000C0240000C024001000200100020000800000008000000080000000800000060
+:2031800043F60002C4F20202106843F6080350F480701060C4F202034CF20C01C8F6FF0116
+:2031A00018680840186043F60C01C4F20201106830F0011030F088501060106830F4802083
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+:20328000FBD0186830F003001860186850F003001860186810F00C000C28FAD15FF00060D3
+:2032A0005FF0E021C1F8080D02B0704730B502460B460024012010FA04F118680840884233
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+:20344000DFF824D0FFF79CFEFFF7D4FF07485FF0E021C1F8080D00200146FFF771FF00F01E
+:203460006BF87047413400080040002000300008064901F1000252F8202001F1100131F824
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+:2034C0001160704704480168002908BF70470168491E01607047C0460000002031F0604198
+:2034E00031F07F0108435FF0E021C1F8080D70470249086008680028FCD17047000000201C
+:123500005FF000605FF44051FFF7E8BF0320029070471D
+:06351400FFF7D6BF70476F
+:02351C00FEE7C8
+:02352000FEE7C4
+:02352400FEE7C0
+:02352800FEE7BC
+:02352C007047E6
+:023530007047E2
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+:02353800FEE7AC
+:20353C00010000000000002050310008300000000000000000000000000000000000000095
+:040000050800343D7E
+:00000001FF
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
new file mode 100644
index 0000000..d494039
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
new file mode 100644
index 0000000..44fb640
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
@@ -0,0 +1,151 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx_cmsis.lsl
+//
+//  Version     :  @(#)stm32l1xx_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32l1xx.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 84
+
+
+#ifndef __STACK
+#  define __STACK                       2k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        1k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32L1xx, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32l1xflash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory stm32l1xram
+{
+    mau = 8;
+    type = ram;
+    size = 16k;
+    map ( size = 16k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandle" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/vssver.scc b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/vssver.scc
new file mode 100644
index 0000000..42ae08e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152-EVAL/TASKING/vssver.scc
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..d688a4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,132 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..39e2cf2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08003000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = 372k;
+    map ( size = 372k, dest_offset=0x08003000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..53578d0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..a67aafc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:00:38 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
new file mode 100644
index 0000000..bae3840
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210B-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210B-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..baccc21
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 128K - 0x3000
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes : { *(.ARM.attributes) } > FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..faa5485
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210E-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
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+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..c34efa7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:01:09 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
new file mode 100644
index 0000000..77034d7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210E-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..54fc800
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 512K - 0x3000
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes : { *(.ARM.attributes) } > FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..874ecbc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,263 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32F10X_XL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1578134158" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1314431980" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/Common"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1997653104" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.586288316" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1370864674" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.377284588" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL_XL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.26443420" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.1289217812" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.144019967" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1807046025" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.704598245" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.478811538" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.864630601" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1692358135" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.820544888" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.710897842" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.160897551" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.417308276" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1343613995" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM32F103ZG\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.204713516" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="StdPeriph_Driver/stm32f10x_dbgmcu.c|StdPeriph_Driver/stm32f10x_can.c|StdPeriph_Driver/stm32f10x_dac.c|StdPeriph_Driver/stm32f10x_tim.c|StdPeriph_Driver/stm32f10x_pwr.c|StdPeriph_Driver/stm32f10x_bkp.c|StdPeriph_Driver/stm32f10x_cec.c|StdPeriph_Driver/stm32f10x_adc.c|StdPeriph_Driver/stm32f10x_rtc.c|StdPeriph_Driver/stm32f10x_crc.c|StdPeriph_Driver/stm32f10x_iwdg.c" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.;com.atollic.truestudio.exe.debug.toolchain.gcc.486923113;com.atollic.truestudio.gcc.input.377284588">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..3d3f2bb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..4f59879
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:01:27 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..a318eda
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..c74d3ef
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,357 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Device/ST/STM32F30x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32F30x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/STM32303C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
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+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
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+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.2061924893" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F303VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput">
+								<option id="com.atollic.truestudio.secoutput.general.convert.1230804987" name="Convert build output" superClass="com.atollic.truestudio.secoutput.general.convert" value="true" valueType="boolean"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
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+		</profile>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
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+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
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+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
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+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.311825581;com.atollic.truestudio.exe.debug.311825581.;com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438;com.atollic.truestudio.gcc.input.488480100">
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
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+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.22089575;com.atollic.truestudio.exe.debug.22089575.;com.atollic.truestudio.exe.debug.toolchain.gcc.1449748890;com.atollic.truestudio.gcc.input.408550467">
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+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
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+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
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+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
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+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM32303C-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..dae124c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,245 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..11c9ee7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..57e0178
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,12 @@
+#Wed Dec 26 09:33:09 GMT+01:00 2012
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.311825581/appendContributed=true
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
new file mode 100644
index 0000000..1a50ba4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F303VC Device with
+**                256KByte FLASH, 40KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000a000;    /* end of 40K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 256K - 0x3000
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 40K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+  CCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+  
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section 
+  * 
+  * IMPORTANT NOTE! 
+  * If initialized variables will be placed in this section, 
+  * the startup code needs to be modified to copy the init-values.  
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+    
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.cproject
new file mode 100644
index 0000000..c871fdb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.cproject
@@ -0,0 +1,355 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Device/ST/STM32F37x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32F37x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F37X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.1266574210" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F373VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..34a75db
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..4d3c6e2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 256K - 0x3000
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..ac4e08f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32L152-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1347491190" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..d0cdf7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_STM32L1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/system_STM32L1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..65faca9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:02:03 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..9c000ef
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..865fc02
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_md Device with
+**                128KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08003000, LENGTH = 128K - 0x3000
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..ada6144
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+<storageModule moduleId="org.eclipse.cdt.core.settings">
+<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+<externalSettings>
+<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+</externalSettings>
+<extensions>
+<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+</extensions>
+</storageModule>
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+<configuration artifactExtension="elf" artifactName="STM32L152D-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+</tool>
+<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Include"/>
+<listOptionValue builtIn="false" value="../../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+<listOptionValue builtIn="false" value="../../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL"/>
+<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/Common"/>
+<listOptionValue builtIn="false" value="../../../inc"/>
+<listOptionValue builtIn="false" value="../../../../../../Utilities/STM32_EVAL/STM32L152D_EVAL"/>
+</option>
+<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+</option>
+<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+</tool>
+<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152D-EVAL\stm32_flash.ld}" valueType="string"/>
+<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+</inputType>
+</tool>
+<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+<listOptionValue builtIn="false" value="STM32L1xx_HD"/>
+<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+</option>
+<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+</tool>
+<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+</tool>
+</toolChain>
+</folderInfo>
+<sourceEntries>
+<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+</sourceEntries>
+</configuration>
+</storageModule>
+<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+<storageModule moduleId="scannerConfiguration">
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+</scannerConfigBuildInfo>
+</storageModule>
+<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cconfiguration>
+</storageModule>
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+<project id="STM32L152D-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..cb881ef
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,156 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D-EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_STM32L1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/system_STM32L1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D-EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-5-PROJECT_LOC/Projects/Device_Firmware_Upgrade/binary_template/src/stm32_it.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/main.h
index d49630e..d0023a8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SysTick/TimeBase/main.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/main.h
@@ -1,31 +1,38 @@
 /**
   ******************************************************************************
-  * @file    SysTick/TimeBase/main.h 
+  * @file    main.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
+  * @version V4.0.0
+  * @date    21-January-2013
   * @brief   Header for main.c module
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
+
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __MAIN_H
 #define __MAIN_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
+
+#include "platform_config.h"
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -35,4 +42,4 @@ void TimingDelay_Decrement(void);
 
 #endif /* __MAIN_H */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/platform_config.h
new file mode 100644
index 0000000..1e54f71
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/platform_config.h
@@ -0,0 +1,80 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+#endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL) && !defined (USE_STM32373C_EVAL) && !defined (USE_STM32303C_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define USE_STM32373C_EVAL
+#define USE_STM32303C_EVAL
+#endif
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32_it.h
index 8890262..ce70454 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32_it.h
@@ -1,34 +1,37 @@
 /**
   ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h 
+  * @file    stm32_it.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
+  * @version V4.0.0
+  * @date    21-January-2013
   * @brief   This file contains the headers of the interrupt handlers.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
 
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
 
-#ifdef __cplusplus
- extern "C" {
-#endif 
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "platform_config.h"
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -45,10 +48,8 @@ void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
 
-#ifdef __cplusplus
-}
-#endif
 
-#endif /* __STM32F10x_IT_H */
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32l1xx_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32l1xx_conf.h
new file mode 100644
index 0000000..ae4a251
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/inc/stm32l1xx_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CONF_H
+#define __STM32L1xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_crc.h"
+#include "stm32l1xx_comp.h"
+#include "stm32l1xx_dac.h" 
+#include "stm32l1xx_dbgmcu.h"
+#include "stm32l1xx_dma.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_flash.h"
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_iwdg.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_tim.h" 
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_wwdg.h"
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32L1xx_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/readme.txt
new file mode 100644
index 0000000..73a9e4e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/readme.txt
@@ -0,0 +1,219 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the binary directory.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Description
+===================
+This directory contains a set of sources files that build the application to be
+loaded into Flash memory using device firmware upgrade (DFU).
+
+To build such application, some special configuration has to be preformed: 
+1. Set the program load address at 0x08003000, using your toolchain linker file
+2. Relocate the vector table at address 0x08003000, using the "NVIC_SetVectorTable"
+   function.
+ 
+The SysTick example provided within the STM32F10xxx,STM32L152xxx, STM32F30xxx and STM32F37xxx Standard 
+Peripheral examples is used as illustration. 
+   
+This example configures the SysTick to generate a time base equal to 1 ms.
+The system clock is set to 72 MHz for STM32F10xxx, STM32F30xxx  and STM32F37xxx devices and to 32MHz for 
+STM32L15xxx devices, the SysTick is clocked by the AHB clock (HCLK)
+
+A "Delay" function is implemented based on the SysTick end-of-count event.
+Four LEDs are toggled with a timing defined by the Delay function.
+
+
+Directory contents
+==================
+
+  + binary_template\EWARM: This folder contains a preconfigured project file 
+                           that produces a binary image of SysTick example to be  
+                           loaded with DFU.
+
+  + binary_template\RIDE: This folder contains a preconfigured project file 
+                          that produces a binary image of SysTick example to be 
+                          loaded with DFU.
+
+  + binary_template\MDK-ARM: This folder contains a preconfigured project file 
+                           that produces a binary image of SysTick example to be 
+                           loaded with DFU.
+
+  + binary_template\TASKING: This folder contains a preconfigured project file 
+                           that produces a binary image of SysTick example to be 
+                           loaded with DFU.
+
+ + \TrueSTUDIO: This folder contains a preconfigured project file 
+                that produces a binary image of SysTick example to be 
+                loaded with DFU.                                      
+                  
+  + binary_template\inc: contains the binary_template firmware header files 
+    - stm32f10x_conf.h    Library Configuration file for STM32F10xxx devices
+    - stm32_it.h      	  Header for stm32_it.c
+    - stm32l15xx_conf.h    Library Configuration file for STM32L15xxx devices
+    - stm32f37x_conf.h    Library Configuration file for STM32F37xxx devices
+    - stm32f30x_conf.h    Library Configuration file for STM32F30xxx devices
+    - main.h              Header for main.c
+
+  + binary_template\src: contains the binary_template firmware source files 
+    - main.c              Main program
+    - stm32_it.c      	  Interrupt handlers for STM32F10xxx,STM32L15xxx, STM32F30xxx and STM32F37xxx devices
+
+
+Hardware environment
+====================
+This example runs on STMicroelectronics STM3210B-EVAL, STM3210E-EVAL, STM32L152-EVAL,STM32F303C_EVAL 
+,STM32F373C_EVAL and STM32L152D-EVAL evaluation boards and can be easily tailored to any other hardware.
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+ + STM3210B-EVAL 
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, PC.08
+      and PC.09 pins
+ 
+ + STM3210E-EVAL
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF.07, PF.08
+      and PF.09 pins
+
+ + STM32L152-EVAL
+    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.00, PD.01, PD.02
+      and PC.12 pins
+ 
+ + STM32L152D-EVAL
+	- Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.03, PD.07, PG.14
+      and PG.15 pins
+
+ + STM32F373C_EVAL
+	- Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.0, PC.01, PC.02
+      and PC.03 pins 
+ 
+ + STM32F303C_EVAL
+	- Use LD1, LD2, LD3 and LD4 leds connected respectively to PE.08, PE.09, PE.10
+      and PE.11 pins   
+   
+How to use it
+=============
+In order to load the SysTick example with the DFU, you must do the following:
+ 
+  + EWARM
+    - Open the SysTick.eww workspace
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152-EVAL: to configure the project for STM32 Low Power Medium-density devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+   - Rebuild all files: Project->Rebuild all
+   - Go to "Utilities\Binary" and run "hextobin.bat"
+   - A binary file "SysTick.bin" will be generated under "STM3210E-EVAL\Exe" or
+     "STM3210B-EVAL\Exe" or "STM32L152-EVAL\Exe" or "STM32L152D-EVAL\Exe" or "STM32373C-EVAL\Exe" or "STM32373C-EVAL\Exe"  folder depending 
+     on configuration you selected. 
+
+  + MDK-ARM
+    - Open the SysTick.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Low Power Medium-density devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices    
+    - Rebuild all files: Project->Rebuild all target files
+    - Go to "Utilities\Binary" and run "axftobin.bat"
+    - A binary file "STM3210B-EVAL_SysTick.bin" or "STM3210E-EVAL_SysTick.bin"  
+	or "STM32L152-EVAL_SysTick.bin" or "STM32L152D-EVAL_SysTick.bin" or "STM32373C-EVAL_SysTick.bin" 
+	or "STM32303C-EVAL_SysTick.bin" will be generated under "\Obj" folder.
+       
+ + RIDE
+    - Open the SysTick.rprj project
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices     
+    - Rebuild all files: Project->build project
+    - Go to "Utilities\Binary" and run "hextobin.bat"
+    - A binary file "SysTick.bin" will be generated under "\STM3210E_EVAL" 
+	or "\STM3210B_EVAL" or "\STM32L152D_EVAL"  or "\STM32L152_EVAL" or "\STM32373C-EVAL" 
+	or "\STM32303C-EVAL" folder depending on configuration you selected.
+      
+  + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+       - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+    
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+	- STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click 
+      on Project->build project menu.
+    - Go to "Utilities\Binary" directory and run "TrueSTUDIO_elf2bin.bat"
+    - A binary file "STM32F10X_XL_SysTick.bin", 
+      "STM3210B-EVAL_SysTick.bin", "STM3210E-EVAL_SysTick.bin", 
+      "STM32L152-EVAL_SysTick.bin" will be generated under "\Debug" folder
+      "STM32L152D-EVAL_SysTick.bin" will be generated under "\Debug" folder
+      "STM32373C-EVAL_SysTick.bin" will be generated under "\Debug" folder
+      "STM32303C-EVAL_SysTick.bin" will be generated under "\Debug" folder
+
+ + The generated .bin file should be converted to the DFU format using the “DFU File
+   Manager Tool” included in the “DfuSe” PC software install. For more details on
+   how to convert a .bin file to DFU format please refer to the UM0412 user manual
+   “Getting started with DfuSe USB device firmware upgrade STMicroelectronics extension”
+   available from the STMicroelectronics microcontroller website www.st.com.
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/main.c
new file mode 100644
index 0000000..c54fe66
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/main.c
@@ -0,0 +1,161 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main program body.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __IO uint32_t TimingDelay;
+
+/* Private function prototypes -----------------------------------------------*/
+void NVIC_Configuration(void);
+void Delay(__IO uint32_t nTime);
+
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : main
+* Description    : Main program.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32xxx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32xxx.c file
+     */  
+
+  /* Configure the LEDs */
+  STM_EVAL_LEDInit(LED1);
+  STM_EVAL_LEDInit(LED2);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED4);  
+
+  /* NVIC configuration */
+  NVIC_Configuration();
+  
+  /* Setup SysTick Timer for 1 msec interrupts  */
+  if (SysTick_Config(SystemCoreClock / 1000))
+  { 
+    /* Capture error */ 
+    while (1);
+  }
+
+  while (1)
+  {
+    /* Toggle all leds */
+    STM_EVAL_LEDToggle(LED1);
+    STM_EVAL_LEDToggle(LED2);
+    STM_EVAL_LEDToggle(LED3);
+    STM_EVAL_LEDToggle(LED4);
+
+    /* Insert 500 ms delay */
+    Delay(500);
+
+    /* Toggle all leds */
+    STM_EVAL_LEDToggle(LED1);
+    STM_EVAL_LEDToggle(LED2);
+    STM_EVAL_LEDToggle(LED3);
+    STM_EVAL_LEDToggle(LED4);
+
+    /* Insert 300 ms delay */
+    Delay(300);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+  /* Set the Vector Table base location at 0x3000 */ 
+  NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x3000);
+}
+/*******************************************************************************
+* Function Name  : Delay
+* Description    : Inserts a delay time.
+* Input          : nTime: specifies the delay time length, in milliseconds.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void Delay(uint32_t nTime)
+{
+  TimingDelay = nTime;
+
+  while(TimingDelay != 0);
+}
+
+/*******************************************************************************
+* Function Name  : TimingDelay_Decrement
+* Description    : Decrements the TimingDelay variable.
+* Input          : None
+* Output         : TimingDelay
+* Return         : None
+*******************************************************************************/
+void TimingDelay_Decrement(void)
+{
+  if (TimingDelay != 0x00)
+  { 
+    TimingDelay--;
+  }
+}
+
+#ifdef USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f10x.c
new file mode 100644
index 0000000..5af97aa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f10x.c
@@ -0,0 +1,1100 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef  STM32F10X_CL
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#ifndef STM32F10X_CL      
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18;
+      
+      if (pllmull != 0x0D)
+      {
+         pllmull += 2;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13 / 2; 
+      }
+            
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        
+        if (prediv1source == 0)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F10X_CL */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+    if (HSE_VALUE <= 24000000)
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+	}
+	else
+	{
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+	}
+#endif /* STM32F10X_CL */
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }   
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+
+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+#else    
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+    
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL6); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL7); 
+#else     
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+    
+   
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/binary_template/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/dfu_mal.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/dfu_mal.h
new file mode 100644
index 0000000..9ac6c57
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/dfu_mal.h
@@ -0,0 +1,74 @@
+/**
+  ******************************************************************************
+  * @file    dfu_mal.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for dfu_mal.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __DFU_MAL_H
+#define __DFU_MAL_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "dfu_mal.h"
+#include "usb_desc.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define MAL_OK   0
+#define MAL_FAIL 1
+#define MAX_USED_MEDIA 3
+#define MAL_MASK 0xFC000000
+
+#define INTERNAL_FLASH_BASE 0x08000000
+#define SPI_FLASH_BASE      0x00000000
+#define NOR_FLASH_BASE      0x64000000
+
+#define NOR_M29W128F        0x2212
+#define NOR_M29W128G        0x2221
+#define NOR_S29GL128        0x2221
+
+/* utils macro ---------------------------------------------------------------*/
+#define _1st_BYTE(x)  (uint8_t)((x)&0xFF)             /* 1st addressing cycle */
+#define _2nd_BYTE(x)  (uint8_t)(((x)&0xFF00)>>8)      /* 2nd addressing cycle */
+#define _3rd_BYTE(x)  (uint8_t)(((x)&0xFF0000)>>16)   /* 3rd addressing cycle */
+#define _4th_BYTE(x)  (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */
+/* Exported macro ------------------------------------------------------------*/
+#define SET_POLLING_TIMING(x)   buffer[1] = _1st_BYTE(x);\
+                                buffer[2] = _2nd_BYTE(x);\
+                                buffer[3] = _3rd_BYTE(x);  
+
+/* Exported functions ------------------------------------------------------- */
+
+uint16_t MAL_Init (void);
+uint16_t MAL_Erase (uint32_t SectorAddress);
+uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength);
+uint8_t  *MAL_Read (uint32_t SectorAddress, uint32_t DataLength);
+uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer);
+
+extern uint8_t  MAL_Buffer[wTransferSize]; /* RAM Buffer for Downloaded Data */
+#endif /* __DFU_MAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/flash_if.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/flash_if.h
new file mode 100644
index 0000000..14e5556
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/flash_if.h
@@ -0,0 +1,48 @@
+/**
+  ******************************************************************************
+  * @file    flash_if.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for flash_if.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FLASH_IF_MAL_H
+#define __FLASH_IF_MAL_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+ 
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint16_t FLASH_If_Init(void);
+uint16_t FLASH_If_Erase (uint32_t SectorAddress);
+uint16_t FLASH_If_Write(uint32_t SectorAddress, uint32_t DataLength);
+uint8_t *FLASH_If_Read (uint32_t SectorAddress, uint32_t DataLength);
+
+#endif /* __FLASH_IF_MAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/fsmc_nor.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/fsmc_nor.h
new file mode 100644
index 0000000..61b5725
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/fsmc_nor.h
@@ -0,0 +1,71 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nor.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for fsmc_nor.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FSMC_NOR_H
+#define __FSMC_NOR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint16_t Manufacturer_Code;
+  uint16_t Device_Code1;
+  uint16_t Device_Code2;
+  uint16_t Device_Code3;
+}NOR_IDTypeDef;
+
+/* NOR Status */
+typedef enum
+{
+  NOR_SUCCESS = 0,
+  NOR_ONGOING,
+  NOR_ERROR,
+  NOR_TIMEOUT
+}NOR_Status;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void FSMC_NOR_Init(void);
+void FSMC_NOR_ReadID(NOR_IDTypeDef* NOR_ID);
+NOR_Status FSMC_NOR_EraseBlock(uint32_t BlockAddr);
+NOR_Status FSMC_NOR_EraseChip(void);
+NOR_Status FSMC_NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data);
+NOR_Status FSMC_NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
+NOR_Status FSMC_NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
+uint16_t FSMC_NOR_ReadHalfWord(uint32_t ReadAddr);
+void FSMC_NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
+NOR_Status FSMC_NOR_ReturnToReadMode(void);
+NOR_Status FSMC_NOR_Reset(void);
+NOR_Status FSMC_NOR_GetStatus(uint32_t Timeout);
+
+#endif /* __FSMC_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/nor_if.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/nor_if.h
new file mode 100644
index 0000000..23ebcaf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/nor_if.h
@@ -0,0 +1,47 @@
+/**
+  ******************************************************************************
+  * @file    nor_if.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for nor_if.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __NOR_IF_MAL_H
+#define __NOR_IF_MAL_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint16_t NOR_If_Init(void);
+uint16_t NOR_If_Erase(uint32_t Address);
+uint16_t NOR_If_Write(uint32_t Address, uint32_t DataLength);
+uint8_t *NOR_If_Read(uint32_t Address, uint32_t DataLength);
+
+#endif /* __NOR_IF_MAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/platform_config.h
new file mode 100644
index 0000000..d501b0f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/platform_config.h
@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #include "spi_if.h"
+ #include "nor_if.h"
+ #include "fsmc_nor.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+  #include "stm3210b_eval_spi_flash.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+  #include "stm3210e_eval_spi_flash.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL)&&  !defined (USE_STM32373C_EVAL) &&  !defined (USE_STM32303C_EVAL)
+//#define USE_STM3210B_EVAL
+//#define USE_STM3210E_EVAL
+//#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define USE_STM32373C_EVAL
+#define USE_STM32303C_EVAL
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+#elif defined (USE_STM32373C_EVAL)
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+  #define GPIO_KEY_EXTI_Line                  EXTI_Line18
+
+#elif defined (USE_STM32303C_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+  #define GPIO_KEY_EXTI_Line                  EXTI_Line18
+
+#endif /* USE_STM3210B_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32_it.h
new file mode 100644
index 0000000..f139828
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32_it.h
@@ -0,0 +1,55 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32l1xx_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32l1xx_conf.h
new file mode 100644
index 0000000..ae4a251
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/stm32l1xx_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CONF_H
+#define __STM32L1xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_crc.h"
+#include "stm32l1xx_comp.h"
+#include "stm32l1xx_dac.h" 
+#include "stm32l1xx_dbgmcu.h"
+#include "stm32l1xx_dma.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_flash.h"
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_iwdg.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_tim.h" 
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_wwdg.h"
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32L1xx_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_desc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_desc.h
new file mode 100644
index 0000000..53ff670
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_desc.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptor Header for Device Firmware Upgrade (DFU)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+#include "platform_config.h"
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define DFU_SIZ_DEVICE_DESC            18
+
+#ifdef USE_STM3210B_EVAL
+  #define DFU_SIZ_CONFIG_DESC          36
+#elif defined(USE_STM3210E_EVAL)
+  #define DFU_SIZ_CONFIG_DESC          45
+#elif defined(USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL) || defined(USE_STM32373C_EVAL) || defined(USE_STM32303C_EVAL)
+  #define DFU_SIZ_CONFIG_DESC          27
+#endif /* USE_STM3210B_EVAL */
+
+#define DFU_SIZ_STRING_LANGID           4
+#define DFU_SIZ_STRING_VENDOR           38
+#define DFU_SIZ_STRING_PRODUCT          20
+#define DFU_SIZ_STRING_SERIAL           26
+#define DFU_SIZ_STRING_INTERFACE0       98    /* Flash Bank 0 */
+
+#define DFU_SIZ_STRING_INTERFACE1       98     /* SPI Flash : M25P64*/
+#define DFU_SIZ_STRING_INTERFACE2       106    /* NOR Flash : M26M128*/
+
+extern  uint8_t DFU_DeviceDescriptor[DFU_SIZ_DEVICE_DESC];
+extern  uint8_t DFU_ConfigDescriptor[DFU_SIZ_CONFIG_DESC];
+extern  uint8_t DFU_StringLangId     [DFU_SIZ_STRING_LANGID];
+extern  uint8_t DFU_StringVendor     [DFU_SIZ_STRING_VENDOR];
+extern  uint8_t DFU_StringProduct    [DFU_SIZ_STRING_PRODUCT];
+extern  uint8_t DFU_StringSerial     [DFU_SIZ_STRING_SERIAL];
+extern  uint8_t DFU_StringInterface0 [DFU_SIZ_STRING_INTERFACE0];
+extern  uint8_t DFU_StringInterface1 [DFU_SIZ_STRING_INTERFACE1];
+extern  uint8_t DFU_StringInterface2_1 [DFU_SIZ_STRING_INTERFACE2];
+extern  uint8_t DFU_StringInterface2_2 [DFU_SIZ_STRING_INTERFACE2];
+extern  uint8_t DFU_StringInterface2_3 [DFU_SIZ_STRING_INTERFACE2];
+
+#define bMaxPacketSize0             0x40     /* bMaxPacketSize0 = 64 bytes   */
+
+#define wTransferSize               0x0400   /* wTransferSize   = 1024 bytes */
+/* bMaxPacketSize0 <= wTransferSize <= 32kbytes */
+#define wTransferSizeB0             0x00
+#define wTransferSizeB1             0x04
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+
+#endif /* __USB_DESC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_prop.h
new file mode 100644
index 0000000..ec8b2a3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_prop.h
@@ -0,0 +1,141 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to DFU demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PROP_H
+#define __USB_PROP_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void DFU_init(void);
+void DFU_Reset(void);
+void DFU_SetConfiguration(void);
+void DFU_SetDeviceAddress (void);
+void DFU_Status_In (void);
+void DFU_Status_Out (void);
+RESULT DFU_Data_Setup(uint8_t);
+RESULT DFU_NoData_Setup(uint8_t);
+RESULT DFU_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *DFU_GetDeviceDescriptor(uint16_t );
+uint8_t *DFU_GetConfigDescriptor(uint16_t);
+uint8_t *DFU_GetStringDescriptor(uint16_t);
+uint8_t *UPLOAD(uint16_t Length);
+uint8_t *DNLOAD(uint16_t Length);
+uint8_t *GETSTATE(uint16_t Length);
+uint8_t *GETSTATUS(uint16_t Length);
+void DFU_write_crc (void);
+
+/* External variables --------------------------------------------------------*/
+
+#define DFU_GetConfiguration          NOP_Process
+//#define DFU_SetConfiguration          NOP_Process
+#define DFU_GetInterface              NOP_Process
+#define DFU_SetInterface              NOP_Process
+#define DFU_GetStatus                 NOP_Process
+#define DFU_ClearFeature              NOP_Process
+#define DFU_SetEndPointFeature        NOP_Process
+#define DFU_SetDeviceFeature          NOP_Process
+//#define DFU_SetDeviceAddress          NOP_Process
+
+/*---------------------------------------------------------------------*/
+/*  DFU definitions                                                    */
+/*---------------------------------------------------------------------*/
+
+/**************************************************/
+/* DFU Requests                                   */
+/**************************************************/
+
+typedef enum _DFU_REQUESTS {
+  DFU_DNLOAD = 1,
+  DFU_UPLOAD,
+  DFU_GETSTATUS,
+  DFU_CLRSTATUS,
+  DFU_GETSTATE,
+  DFU_ABORT
+} DFU_REQUESTS;
+
+/**************************************************/
+/* DFU Requests  DFU states                       */
+/**************************************************/
+
+
+#define STATE_appIDLE                 0
+#define STATE_appDETACH               1
+#define STATE_dfuIDLE                 2
+#define STATE_dfuDNLOAD_SYNC          3
+#define STATE_dfuDNBUSY               4
+#define STATE_dfuDNLOAD_IDLE          5
+#define STATE_dfuMANIFEST_SYNC        6
+#define STATE_dfuMANIFEST             7
+#define STATE_dfuMANIFEST_WAIT_RESET  8
+#define STATE_dfuUPLOAD_IDLE          9
+#define STATE_dfuERROR                10
+
+/**************************************************/
+/* DFU Requests  DFU status                       */
+/**************************************************/
+
+#define STATUS_OK                   0x00
+#define STATUS_ERRTARGET            0x01
+#define STATUS_ERRFILE              0x02
+#define STATUS_ERRWRITE             0x03
+#define STATUS_ERRERASE             0x04
+#define STATUS_ERRCHECK_ERASED      0x05
+#define STATUS_ERRPROG              0x06
+#define STATUS_ERRVERIFY            0x07
+#define STATUS_ERRADDRESS           0x08
+#define STATUS_ERRNOTDONE           0x09
+#define STATUS_ERRFIRMWARE          0x0A
+#define STATUS_ERRVENDOR            0x0B
+#define STATUS_ERRUSBR              0x0C
+#define STATUS_ERRPOR               0x0D
+#define STATUS_ERRUNKNOWN           0x0E
+#define STATUS_ERRSTALLEDPKT        0x0F
+
+/**************************************************/
+/* DFU Requests  DFU states Manifestation State   */
+/**************************************************/
+
+#define Manifest_complete           0x00
+#define Manifest_In_Progress        0x01
+
+
+/**************************************************/
+/* Special Commands  with Download Request        */
+/**************************************************/
+
+#define CMD_GETCOMMANDS              0x00
+#define CMD_SETADDRESSPOINTER        0x21
+#define CMD_ERASE                    0x41
+
+#endif /* __USB_PROP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_pwr.h
new file mode 100644
index 0000000..3f56f16
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/inc/usb_pwr.h
@@ -0,0 +1,68 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+/* External variables --------------------------------------------------------*/
+extern  __IO uint32_t bDeviceState;             /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/readme.txt
new file mode 100644
index 0000000..25ca5c0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/readme.txt
@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB Device_Firmware_Upgrade Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+This Demo presents the implementation of a device firmware upgrade (DFU) capability
+in the STM32F10xxx, STM32F37xxx, STM32F30xxx and STM32L15xxx microcontrollers. It follows the DFU class 
+specification defined by the USB Implementers Forum for reprogramming an application 
+through USB-FS-Device. 
+The DFU principle is particularly well suited to USB-FS-Device applications that 
+need to be reprogrammed in the field.
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \binary_template: contains a set of sources files that build the application 
+                     to be loaded with DFU 
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured project for EWARM toolchain
+ + \RIDE: contains preconfigured project for RIDE toolchain
+ + \MDK-ARM: contains preconfigured project for MDK-ARM toolchain
+ + \TASKING: contains preconfigured project for TASKING toolchain  
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain          
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+Note: After each device reset, hold down the Key push-button on the STM3210B-EVAL 
+      or STM3210E-EVAL or STM32L152D-EVAL or STM32F373C-EVAL evaluation boards or the Up push button 
+      on STM32L152-EVAL evaluation board to enter the DFU mode.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+
+  - STM32L152-EVAL Set-up 
+     - None.
+     - Note that the JoyStick Up push button is used to enter DFU mode.
+ 
+  - STM32L152D-EVAL Set-up 
+     - None.
+     
+  - STM32F373C-EVAL Set-up 
+     - None.
+
+  - STM32F303C-EVAL Set-up 
+     - None.
+     
+How to use it
+=============
+ + EWARM
+    - Open the DFU.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the DFU.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)  
+
+ + RIDE
+    - Open the DFU.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+       - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/dfu_mal.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/dfu_mal.c
new file mode 100644
index 0000000..b0e8366
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/dfu_mal.c
@@ -0,0 +1,253 @@
+/**
+  ******************************************************************************
+  * @file    dfu_mal.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Generic media access Layer
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "dfu_mal.h"
+#include "usb_lib.h"
+#include "usb_type.h"
+#include "usb_desc.h"
+#include "flash_if.h"
+
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)&& !defined (USE_STM32373C_EVAL) && !defined (USE_STM32303C_EVAL)
+ #include "spi_if.h"
+
+ #include "nor_if.h"
+ #include "fsmc_nor.h"
+#endif /* STM32L1XX_MD && USE_STM32373C_EVAL*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint16_t (*pMAL_Init) (void);
+uint16_t (*pMAL_Erase) (uint32_t SectorAddress);
+uint16_t (*pMAL_Write) (uint32_t SectorAddress, uint32_t DataLength);
+uint8_t  *(*pMAL_Read)  (uint32_t SectorAddress, uint32_t DataLength);
+uint8_t  MAL_Buffer[wTransferSize]; /* RAM Buffer for Downloaded Data */
+
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)&& !defined (USE_STM32373C_EVAL) && !defined (USE_STM32303C_EVAL)
+  NOR_IDTypeDef NOR_ID;
+#endif /* STM32L1XX_XD */
+
+extern ONE_DESCRIPTOR DFU_String_Descriptor[7];
+
+/* This table holds the Typical Sector Erase and 1024 Bytes Write timings.
+   These timings will be returned to the host when it checks the device
+   status during a write or erase operation to know how much time the host
+   should wait before issuing the next get status request. 
+   These defines are set in usb_conf.h file.
+   The values of this table should be extracted from relative memories 
+   datasheet (Typical or Maximum timming value for Sector Erase and for 
+   1024 bytes Write). All timings are expressed in millisecond unit (ms).
+   Note that "Sector" refers here to the memory unit used for Erase/Write 
+   operations. It could be a sector, a page, a block, a word ...
+   If the erase operation is not supported, it is advised to set the erase
+   timing to 1 (which means 1ms: one USB frame). */
+static const uint16_t  TimingTable[5][2] =
+  { /*       Sector Erase time,            Sector Program time*/    
+    { SPI_FLASH_SECTOR_ERASE_TIME,    SPI_FLASH_SECTOR_WRITE_TIME },    /* SPI Flash */
+    { M29W128F_SECTOR_ERASE_TIME,     M29W128F_SECTOR_WRITE_TIME },     /* NOR Flash M29W128F */
+    { INTERN_FLASH_SECTOR_ERASE_TIME, INTERN_FLASH_SECTOR_WRITE_TIME }, /* Internal Flash */
+    { M29W128G_SECTOR_ERASE_TIME,     M29W128G_SECTOR_WRITE_TIME },     /* NOR Flash M29W128G */
+    { S29GL128_SECTOR_ERASE_TIME,     S29GL128_SECTOR_WRITE_TIME }      /* NOR Flash S29GL128 */
+  };
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : MAL_Init
+* Description    : Initializes the Media on the STM32
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Init(void)
+{
+
+  FLASH_If_Init(); /* Internal Flash */
+
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM3210E_EVAL)
+  SPI_If_Init();   /* SPI Flash */
+#endif /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+
+#ifdef USE_STM3210E_EVAL 
+  NOR_If_Init();  /* NOR Flash */
+  FSMC_NOR_ReadID(&NOR_ID);
+    
+  FSMC_NOR_ReturnToReadMode();
+
+  /* select the alternate descriptor following NOR ID */
+  if ((NOR_ID.Manufacturer_Code == 0x01)&&(NOR_ID.Device_Code2 == NOR_S29GL128))
+  {
+    DFU_String_Descriptor[6].Descriptor = DFU_StringInterface2_3;
+  } 
+  
+  /* select the alternate descriptor following NOR ID */
+  if  ((NOR_ID.Manufacturer_Code == 0x20)&&(NOR_ID.Device_Code2 == NOR_M29W128G))
+  {
+    DFU_String_Descriptor[6].Descriptor = DFU_StringInterface2_2;
+  }
+#endif /* USE_STM3210E_EVAL */
+
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : MAL_Erase
+* Description    : Erase sector
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Erase(uint32_t SectorAddress)
+{
+
+  switch (SectorAddress & MAL_MASK)
+  {
+    case INTERNAL_FLASH_BASE:
+      pMAL_Erase = FLASH_If_Erase;
+      break;
+      
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM3210E_EVAL)
+    case SPI_FLASH_BASE:
+      pMAL_Erase = SPI_If_Erase;
+      break;
+#endif /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+            
+#ifdef USE_STM3210E_EVAL  
+    case NOR_FLASH_BASE:
+      pMAL_Erase = NOR_If_Erase;
+      break;
+#endif /* USE_STM3210E_EVAL */
+      
+    default:
+      return MAL_FAIL;
+  }
+  return pMAL_Erase(SectorAddress);
+}
+
+/*******************************************************************************
+* Function Name  : MAL_Write
+* Description    : Write sectors
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength)
+{
+
+  switch (SectorAddress & MAL_MASK)
+  {
+    case INTERNAL_FLASH_BASE:
+      pMAL_Write = FLASH_If_Write;
+      break;
+
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM3210E_EVAL)    
+    case SPI_FLASH_BASE:
+      pMAL_Write = SPI_If_Write;
+      break;
+#endif /* USE_STM3210B_EVAL || USE_STM3210E_EVAL */      
+
+#ifdef USE_STM3210E_EVAL
+    case NOR_FLASH_BASE:
+      pMAL_Write = NOR_If_Write;
+      break;
+#endif /* USE_STM3210E_EVAL */
+    default:
+      return MAL_FAIL;
+  }
+  return pMAL_Write(SectorAddress, DataLength);
+}
+
+/*******************************************************************************
+* Function Name  : MAL_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : Buffer pointer
+*******************************************************************************/
+uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength)
+{
+
+  switch (SectorAddress & MAL_MASK)
+  {
+    case INTERNAL_FLASH_BASE:
+      pMAL_Read = FLASH_If_Read;
+      break;
+      
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM3210E_EVAL)     
+    case SPI_FLASH_BASE:
+      pMAL_Read = SPI_If_Read;
+      break;
+#endif /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+
+#ifdef USE_STM3210E_EVAL
+    case NOR_FLASH_BASE:
+      pMAL_Read = NOR_If_Read;
+      break;
+#endif /* USE_STM3210E_EVAL */
+
+    default:
+      return 0;
+  }
+  return pMAL_Read (SectorAddress, DataLength);
+}
+
+/*******************************************************************************
+* Function Name  : MAL_GetStatus
+* Description    : Get status
+* Input          : None
+* Output         : None
+* Return         : Buffer pointer
+*******************************************************************************/
+uint16_t MAL_GetStatus(uint32_t SectorAddress , uint8_t Cmd, uint8_t *buffer)
+{
+  uint8_t x = (SectorAddress  >> 26) & 0x03 ; /* 0x000000000 --> 0 */
+  /* 0x640000000 --> 1 */
+  /* 0x080000000 --> 2 */
+
+  uint8_t y = Cmd & 0x01;
+
+#if defined(USE_STM3210E_EVAL)  
+  if ((x == 1) && (NOR_ID.Device_Code2 == NOR_M29W128G)&& (NOR_ID.Manufacturer_Code == 0x20))
+  {
+    x = 3 ;
+  }
+  else if((x == 1) && (NOR_ID.Device_Code2 == NOR_S29GL128) && (NOR_ID.Manufacturer_Code == 0x01))
+  {
+    x = 4 ;
+  }  
+#endif /* USE_STM3210E_EVAL */
+  
+  SET_POLLING_TIMING(TimingTable[x][y]);  /* x: Erase/Write Timing */
+  /* y: Media              */
+  return MAL_OK;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/flash_if.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/flash_if.c
new file mode 100644
index 0000000..e6caf41
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/flash_if.c
@@ -0,0 +1,171 @@
+/**
+  ******************************************************************************
+  * @file    flash_if.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   specific media access Layer for internal flash
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "flash_if.h"
+#include "dfu_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  uint32_t tHalfPage1[128/4];
+  uint32_t tHalfPage2[128/4];
+#endif /* STM32L1XX_XD */  
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : FLASH_If_Init
+* Description    : Initializes the Media on the STM32
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t FLASH_If_Init(void)
+{
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : FLASH_If_Erase
+* Description    : Erase sector
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t FLASH_If_Erase(uint32_t SectorAddress)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  FLASH_ClearFlag(FLASH_FLAG_PGAERR | FLASH_FLAG_OPTVERR);
+  FLASH_ErasePage(SectorAddress);
+#else
+  FLASH_ErasePage(SectorAddress);
+#endif /* STM32L1XX_XD */
+  
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : FLASH_If_Write
+* Description    : Write sectors
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t FLASH_If_Write(uint32_t SectorAddress, uint32_t DataLength)
+{
+  uint32_t idx = 0;
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  __IO uint32_t* malPointer = (uint32_t *)MAL_Buffer;
+  __IO uint32_t* memPointer = (uint32_t *)SectorAddress;
+  __IO uint32_t memBuffer[32]; /* Temporary buffer holding data that will be written in a half-page space */
+  __IO uint32_t* mempBuffer = memBuffer;  
+  __IO uint32_t* tmp;
+#endif /* STM32L1XX_XD */      
+  
+  if  (DataLength & 0x3) /* Not an aligned data */
+  {
+    for (idx = DataLength; idx < ((DataLength & 0xFFFC) + 4); idx++)
+    {
+      MAL_Buffer[idx] = 0xFF;
+    }
+  } 
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) 
+  /* Reinitialize the intermediate buffer pointer */
+  mempBuffer = memBuffer;
+  
+  /* If the address is not aligned to half-page fill the first location with existing data */
+  if (((uint32_t)memPointer & 0x7F) != 0)
+  {
+    /* get the aligned address */
+    tmp = (uint32_t *)((uint32_t)memPointer & 0xFFFFFF80);
+    
+    /* Read the first part from the memory */
+    while (tmp < memPointer)
+    {
+      *(uint32_t *)(mempBuffer++) = *(uint32_t *)(tmp++);
+    }
+  }    
+  
+  while (malPointer < (uint32_t*)(MAL_Buffer + DataLength))
+  {    
+    /* Fill with the received buffer */
+    while (mempBuffer < (memBuffer + 32))
+    {
+      /* If there are still data available in the received buffer */
+      if (malPointer < ((uint32_t *)MAL_Buffer + DataLength))
+      {
+        *(uint32_t *)(mempBuffer++) = *(uint32_t *)(malPointer++);
+      }
+      else /* no more data available in the received buffer: fill remaining with dummy 0 */
+      {
+        *(uint32_t *)(mempBuffer++) = 0;
+      }
+    }
+   
+    /* Write the buffer to the memory*/    
+    FLASH_ProgramHalfPage(((uint32_t)memPointer & 0xFFFFFF80), (uint32_t *)(memBuffer));    
+    
+    /* Increment the memory pointer */ 
+    memPointer = (uint32_t *)(((uint32_t)memPointer & 0xFFFFFF80) + (32*4));
+    
+    /* Reinitialize the intermediate buffer pointer */
+    mempBuffer = memBuffer;
+  }
+  
+#else
+  
+  /* Data received are Word multiple */    
+  for (idx = 0; idx <  DataLength; idx = idx + 4)
+  {
+    FLASH_ProgramWord(SectorAddress, *(uint32_t *)(MAL_Buffer + idx));  
+    SectorAddress += 4;
+  } 
+#endif /* STM32L1XX_XD */
+ 
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : FLASH_If_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : buffer address pointer
+*******************************************************************************/
+uint8_t *FLASH_If_Read (uint32_t SectorAddress, uint32_t DataLength)
+{
+  return  (uint8_t*)(SectorAddress);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
new file mode 100644
index 0000000..cdcfcdf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/fsmc_nor.c
@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nor.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file provides a set of functions needed to drive the M29W128FL,
+  *          M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nor.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define Bank1_NOR2_ADDR       ((uint32_t)0x64000000)
+
+/* Delay definition */   
+#define BlockErase_Timeout    ((uint32_t)0x00A00000)
+#define ChipErase_Timeout     ((uint32_t)0x30000000) 
+#define Program_Timeout       ((uint32_t)0x00001400)
+
+/* Private macro -------------------------------------------------------------*/
+#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
+#define NOR_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : FSMC_NOR_Init
+* Description    : Configures the FSMC and GPIOs to interface with the NOR memory.
+*                  This function must be called before any write/read operation
+*                  on the NOR.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NOR_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+
+  /*-- GPIO Configuration ------------------------------------------------------*/
+  /* NOR Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  /* NOR Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
+                                GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;                            
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  /* NOE and NWE configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /* NE2 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  /*-- FSMC Configuration ----------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0x02;
+  p.FSMC_AddressHoldTime = 0x00;
+  p.FSMC_DataSetupTime = 0x05;
+  p.FSMC_BusTurnAroundDuration = 0x00;
+  p.FSMC_CLKDivision = 0x00;
+  p.FSMC_DataLatency = 0x00;
+  p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+  /* Enable FSMC Bank1_NOR Bank */
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_ReadID
+* Description    : Reads NOR memory's Manufacturer and Device Code.
+* Input          : - NOR_ID: pointer to a NOR_IDTypeDef structure which will hold
+*                    the Manufacturer and Device Code.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NOR_ReadID(NOR_IDTypeDef* NOR_ID)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
+
+  NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
+  NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
+  NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
+  NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
+}
+
+/*******************************************************************************
+* Function Name  : FSMC_NOR_EraseBlock
+* Description    : Erases the specified Nor memory block.
+* Input          : - BlockAddr: address of the block to erase.
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_EraseBlock(uint32_t BlockAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
+
+  return (FSMC_NOR_GetStatus(BlockErase_Timeout));
+}
+
+/*******************************************************************************
+* Function Name  : FSMC_NOR_EraseChip
+* Description    : Erases the entire chip.
+* Input          : None                      
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_EraseChip(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
+
+  return (FSMC_NOR_GetStatus(ChipErase_Timeout));
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_WriteHalfWord
+* Description    : Writes a half-word to the NOR memory. 
+* Input          : - WriteAddr : NOR memory internal address to write to.
+*                  - Data : Data to write. 
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
+  NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
+
+  return (FSMC_NOR_GetStatus(Program_Timeout));
+}
+
+/*******************************************************************************
+* Function Name  : FSMC_NOR_WriteBuffer
+* Description    : Writes a half-word buffer to the FSMC NOR memory. 
+* Input          : - pBuffer : pointer to buffer. 
+*                  - WriteAddr : NOR memory internal address from which the data 
+*                    will be written.
+*                  - NumHalfwordToWrite : number of Half words to write. 
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  NOR_Status status = NOR_ONGOING; 
+
+  do
+  {
+    /* Transfer data to the memory */
+    status = FSMC_NOR_WriteHalfWord(WriteAddr, *pBuffer++);
+    WriteAddr = WriteAddr + 2;
+    NumHalfwordToWrite--;
+  }
+  while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
+  
+  return (status); 
+}
+
+/*******************************************************************************
+* Function Name  : FSMC_NOR_ProgramBuffer
+* Description    : Writes a half-word buffer to the FSMC NOR memory. This function 
+*                  must be used only with S29GL128P NOR memory.
+* Input          : - pBuffer : pointer to buffer. 
+*                  - WriteAddr: NOR memory internal address from which the data 
+*                    will be written.
+*                  - NumHalfwordToWrite: number of Half words to write.
+*                    The maximum allowed value is 32 Half words (64 bytes).
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{       
+  uint32_t lastloadedaddress = 0x00;
+  uint32_t currentaddress = 0x00;
+  uint32_t endaddress = 0x00;
+
+  /* Initialize variables */
+  currentaddress = WriteAddr;
+  endaddress = WriteAddr + NumHalfwordToWrite - 1;
+  lastloadedaddress = WriteAddr;
+
+  /* Issue unlock command sequence */
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);  
+
+  /* Write Write Buffer Load Command */
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
+
+  /* Load Data into NOR Buffer */
+  while(currentaddress <= endaddress)
+  {
+    /* Store last loaded address & data value (for polling) */
+    lastloadedaddress = currentaddress;
+ 
+    NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
+    currentaddress += 1; 
+  }
+
+  NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
+  
+  return(FSMC_NOR_GetStatus(Program_Timeout));
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_ReadHalfWord
+* Description    : Reads a half-word from the NOR memory. 
+* Input          : - ReadAddr : NOR memory internal address to read from.
+* Output         : None
+* Return         : Half-word read from the NOR memory
+*******************************************************************************/
+uint16_t FSMC_NOR_ReadHalfWord(uint32_t ReadAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);  
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
+
+  return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
+}
+
+/*******************************************************************************
+* Function Name  : FSMC_NOR_ReadBuffer
+* Description    : Reads a block of data from the FSMC NOR memory.
+* Input          : - pBuffer : pointer to the buffer that receives the data read 
+*                    from the NOR memory.
+*                  - ReadAddr : NOR memory internal address to read from.
+*                  - NumHalfwordToRead : number of Half word to read.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
+
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /* while there is data to read */
+  {
+    /* Read a Halfword from the NOR */
+    *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
+    ReadAddr = ReadAddr + 2; 
+  }  
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_ReturnToReadMode
+* Description    : Returns the NOR memory to Read mode.
+* Input          : None
+* Output         : None
+* Return         : NOR_SUCCESS
+*******************************************************************************/
+NOR_Status FSMC_NOR_ReturnToReadMode(void)
+{
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
+
+  return (NOR_SUCCESS);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_Reset
+* Description    : Returns the NOR memory to Read mode and resets the errors in
+*                  the NOR memory Status Register.
+* Input          : None
+* Output         : None
+* Return         : NOR_SUCCESS
+*******************************************************************************/
+NOR_Status FSMC_NOR_Reset(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); 
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); 
+
+  return (NOR_SUCCESS);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NOR_GetStatus
+* Description    : Returns the NOR operation status.
+* Input          : - Timeout: NOR programming Timeout
+* Output         : None
+* Return         : NOR_Status:The returned value can be: NOR_SUCCESS, NOR_ERROR
+*                  or NOR_TIMEOUT
+*******************************************************************************/
+NOR_Status FSMC_NOR_GetStatus(uint32_t Timeout)
+{ 
+  uint16_t val1 = 0x00, val2 = 0x00;
+  NOR_Status status = NOR_ONGOING; 
+  uint32_t timeout = Timeout;
+
+  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) 
+  {
+    timeout--;
+  }
+
+  timeout = Timeout;
+  
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))   
+  {
+    timeout--;
+  }
+  
+  /* Get the NOR memory operation status -------------------------------------*/
+  while((Timeout != 0x00) && (status != NOR_SUCCESS))
+  {
+    Timeout--;
+
+	  /* Read DQ6 and DQ5 */
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+
+    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+
+    if((val1 & 0x0020) != 0x0020)
+    {
+      status = NOR_ONGOING;
+    }
+
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+    else if((val1 & 0x0020) == 0x0020)
+    {
+      return NOR_ERROR;
+    }
+  }
+
+  if(Timeout == 0x00)
+  {
+    status = NOR_TIMEOUT;
+  } 
+
+  /* Return the operation status */
+  return (status);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/spi_if.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/spi_if.c
new file mode 100644
index 0000000..8588f39
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/spi_if.c
@@ -0,0 +1,110 @@
+/**
+  ******************************************************************************
+  * @file    spi_if.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   specific media access Layer for SPI flash
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "spi_if.h"
+#include "dfu_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : SPI_If_Init
+* Description    : Initializes the Media on the STM32
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t SPI_If_Init(void)
+{
+  sFLASH_Init();
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : SPI_If_Erase
+* Description    : Erase sector
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t SPI_If_Erase(uint32_t SectorAddress)
+{
+  sFLASH_EraseSector(SectorAddress);
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : SPI_If_Write
+* Description    : Write sectors
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t SPI_If_Write(uint32_t SectorAddress, uint32_t DataLength)
+{
+  uint32_t idx, pages;
+
+  pages = (((DataLength & 0xFF00)) >> 8);
+
+  if  (DataLength & 0xFF) /* Not a 256 aligned data */
+  {
+    for ( idx = DataLength; idx < ((DataLength & 0xFF00) + 0x100) ; idx++)
+    {
+      MAL_Buffer[idx] = 0xFF;
+    }
+    pages = (((DataLength & 0xFF00)) >> 8 ) + 1;
+  }
+
+  for (idx = 0; idx < pages; idx++)
+  {
+    sFLASH_WritePage(&MAL_Buffer[idx*256], SectorAddress, 256);
+    SectorAddress += 0x100;
+  }
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : SPI_If_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : buffer address pointer
+*******************************************************************************/
+uint8_t *SPI_If_Read(uint32_t SectorAddress, uint32_t DataLength)
+{
+  sFLASH_ReadBuffer(MAL_Buffer, SectorAddress, (uint16_t)DataLength);
+  return MAL_Buffer;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f30x.c
new file mode 100644
index 0000000..31faf5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F30x devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f30x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f30x.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F30x device                          
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F30x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f30x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+  * @{
+  */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F30x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 72000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_desc.c
new file mode 100644
index 0000000..1646763
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_desc.c
@@ -0,0 +1,489 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Device Firmware Upgrade (DFU)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_desc.h"
+#include "platform_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+uint8_t DFU_DeviceDescriptor[DFU_SIZ_DEVICE_DESC] =
+  {
+    0x12,   /* bLength */
+    0x01,   /* bDescriptorType */
+    0x00,   /* bcdUSB, version 1.00 */
+    0x01,
+    0x00,   /* bDeviceClass : See interface */
+    0x00,   /* bDeviceSubClass : See interface*/
+    0x00,   /* bDeviceProtocol : See interface */
+    bMaxPacketSize0, /* bMaxPacketSize0 0x40 = 64 */
+    0x83,   /* idVendor     (0483) */
+    0x04,
+    0x11,   /* idProduct (0xDF11) DFU PiD*/
+    0xDF,
+    0x00,   /* bcdDevice*/
+    0x02,
+
+    0x01,   /* iManufacturer : index of string Manufacturer  */
+    0x02,   /* iProduct      : index of string descriptor of product*/
+    0x03,   /* iSerialNumber : index of string serial number*/
+
+    0x01    /*bNumConfigurations */
+  };
+
+#ifdef USE_STM3210B_EVAL
+uint8_t DFU_ConfigDescriptor[DFU_SIZ_CONFIG_DESC] =
+  {
+    0x09,   /* bLength: Configuration Descriptor size */
+    0x02,   /* bDescriptorType: Configuration */
+    DFU_SIZ_CONFIG_DESC, /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,   /* bNumInterfaces: 1 interface */
+    0x01,   /* bConfigurationValue: */
+    /*      Configuration value */
+    0x00,   /* iConfiguration: */
+    /*      Index of string descriptor */
+    /*      describing the configuration */
+    0xC0,   /* bmAttributes: */
+    /*      Self powered */
+    0x32,   /* MaxPower 100 mA */
+    /* 09 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 0 *********/
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x04,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 18 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 1  **********/
+
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x01,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x05,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 27 */
+
+    /******************** DFU Functional Descriptor********************/
+    0x09,   /*blength = 9 Bytes*/
+    0x21,   /* DFU Functional Descriptor*/
+    0x0B,   /*bmAttribute
+
+                                             bitCanDnload             = 1      (bit 0)
+                                             bitCanUpload             = 1      (bit 1)
+                                             bitManifestationTolerant = 0      (bit 2)
+                                             bitWillDetach            = 1      (bit 3)
+                                             Reserved                          (bit4-6)
+                                             bitAcceleratedST         = 0      (bit 7)*/
+    0xFF,   /*DetachTimeOut= 255 ms*/
+    0x00,
+    wTransferSizeB0,
+    wTransferSizeB1,          /* TransferSize = 1024 Byte*/
+    0x1A,                     /* bcdDFUVersion*/
+    0x01
+    /***********************************************************/
+    /*36*/
+
+  };
+
+#elif defined (USE_STM3210E_EVAL)
+uint8_t DFU_ConfigDescriptor[DFU_SIZ_CONFIG_DESC] =
+  {
+    0x09,   /* bLength: Configuration Descriptor size */
+    0x02,   /* bDescriptorType: Configuration */
+    DFU_SIZ_CONFIG_DESC, /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,   /* bNumInterfaces: 1 interface */
+    0x01,   /* bConfigurationValue: */
+    /*      Configuration value */
+    0x00,   /* iConfiguration: */
+    /*      Index of string descriptor */
+    /*      describing the configuration */
+    0x80,   /* bmAttributes: */
+    /*      bus powered */
+    0x20,   /* MaxPower 100 mA: this current is used for detecting Vbus */
+    /* 09 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 0 *********/
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x04,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 18 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 1  **********/
+
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x01,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x05,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 27 */    
+ 
+    /************ Descriptor of DFU interface 0 Alternate setting 2  **********/
+
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x02,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x06,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 36 */    
+
+    /******************** DFU Functional Descriptor********************/
+    0x09,   /*blength = 9 Bytes*/
+    0x21,   /* DFU Functional Descriptor*/
+    0x0B,   /*bmAttribute
+
+    bitCanDnload             = 1      (bit 0)
+    bitCanUpload             = 1      (bit 1)
+    bitManifestationTolerant = 0      (bit 2)
+    bitWillDetach            = 1      (bit 3)
+    Reserved                          (bit4-6)
+    bitAcceleratedST         = 0      (bit 7)*/
+    0xFF,   /*DetachTimeOut= 255 ms*/
+    0x00,
+    wTransferSizeB0,
+    wTransferSizeB1,          /* TransferSize = 1024 Byte*/
+    0x1A,                     /* bcdDFUVersion*/
+    0x01
+    /***********************************************************/
+    /*45*/
+
+  };
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+uint8_t DFU_ConfigDescriptor[DFU_SIZ_CONFIG_DESC] =
+  {
+    0x09,   /* bLength: Configuration Descriptor size */
+    0x02,   /* bDescriptorType: Configuration */
+    DFU_SIZ_CONFIG_DESC, /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,   /* bNumInterfaces: 1 interface */
+    0x01,   /* bConfigurationValue: */
+    /*      Configuration value */
+    0x00,   /* iConfiguration: */
+    /*      Index of string descriptor */
+    /*      describing the configuration */
+    0xC0,   /* bmAttributes: */
+    /*      bus powered */
+    0x32,   /* MaxPower 100 mA */
+    /* 09 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 0 *********/
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x04,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 18 */
+
+    /******************** DFU Functional Descriptor********************/
+    0x09,   /*blength = 9 Bytes*/
+    0x21,   /* DFU Functional Descriptor*/
+    0x0B,   /*bmAttribute
+
+                                             bitCanDnload             = 1      (bit 0)
+                                             bitCanUpload             = 1      (bit 1)
+                                             bitManifestationTolerant = 0      (bit 2)
+                                             bitWillDetach            = 1      (bit 3)
+                                             Reserved                          (bit4-6)
+                                             bitAcceleratedST         = 0      (bit 7)*/
+    0xFF,   /*DetachTimeOut= 255 ms*/
+    0x00,
+    wTransferSizeB0,
+    wTransferSizeB1,          /* TransferSize = 128 Bytes */
+    0x1A,                     /* bcdDFUVersion*/
+    0x01
+    /***********************************************************/
+    /*27*/
+
+  };
+
+#elif defined (USE_STM32373C_EVAL) || defined (USE_STM32303C_EVAL)
+uint8_t DFU_ConfigDescriptor[DFU_SIZ_CONFIG_DESC] =
+  {
+    0x09,   /* bLength: Configuration Descriptor size */
+    0x02,   /* bDescriptorType: Configuration */
+    DFU_SIZ_CONFIG_DESC, /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,   /* bNumInterfaces: 1 interface */
+    0x01,   /* bConfigurationValue: */
+    /*      Configuration value */
+    0x00,   /* iConfiguration: */
+    /*      Index of string descriptor */
+    /*      describing the configuration */
+    0xC0,   /* bmAttributes: */
+    /*      bus powered */
+    0x32,   /* MaxPower 100 mA */
+    /* 09 */
+
+    /************ Descriptor of DFU interface 0 Alternate setting 0 *********/
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x00,   /* bNumEndpoints*/
+    0xFE,   /* bInterfaceClass: Application Specific Class Code */
+    0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */
+    0x02,   /* nInterfaceProtocol: DFU mode protocol */
+    0x04,   /* iInterface: */
+    /* Index of string descriptor */
+    /* 18 */
+
+    /******************** DFU Functional Descriptor********************/
+    0x09,   /*blength = 9 Bytes*/
+    0x21,   /* DFU Functional Descriptor*/
+    0x0B,   /*bmAttribute
+
+                                             bitCanDnload             = 1      (bit 0)
+                                             bitCanUpload             = 1      (bit 1)
+                                             bitManifestationTolerant = 0      (bit 2)
+                                             bitWillDetach            = 1      (bit 3)
+                                             Reserved                          (bit4-6)
+                                             bitAcceleratedST         = 0      (bit 7)*/
+    0xFF,   /*DetachTimeOut= 255 ms*/
+    0x00,
+    wTransferSizeB0,
+    wTransferSizeB1,          /* TransferSize = 128 Bytes */
+    0x1A,                     /* bcdDFUVersion*/
+    0x01
+    /***********************************************************/
+    /*27*/
+
+  };
+
+
+#endif /* USE_STM3210B_EVAL */
+
+uint8_t DFU_StringLangId[DFU_SIZ_STRING_LANGID] =
+  {
+    DFU_SIZ_STRING_LANGID,
+    0x03,
+    0x09,
+    0x04    /* LangID = 0x0409: U.S. English */
+  };
+
+
+uint8_t DFU_StringVendor[DFU_SIZ_STRING_VENDOR] =
+  {
+    DFU_SIZ_STRING_VENDOR,
+    0x03,
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+uint8_t DFU_StringProduct[DFU_SIZ_STRING_PRODUCT] =
+  {
+    DFU_SIZ_STRING_PRODUCT,
+    0x03,
+    /* Product name: "STM32 DFU" */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'D', 0, 'F', 0, 'U', 0
+  };
+
+uint8_t DFU_StringSerial[DFU_SIZ_STRING_SERIAL] =
+  {
+    DFU_SIZ_STRING_SERIAL,
+    0x03,
+    /* Serial number */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0  
+  };
+
+#if defined (USE_STM3210B_EVAL) || defined (USE_STM32373C_EVAL) || defined (USE_STM32303C_EVAL)
+uint8_t DFU_StringInterface0[DFU_SIZ_STRING_INTERFACE0] =
+  {
+    DFU_SIZ_STRING_INTERFACE0,
+    0x03,
+    // Interface 0: "@Internal Flash   /0x08000000/12*001Ka,116*001Kg"
+    '@', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'n', 0, 'a', 0, 'l', 0,  /* 18 */
+    ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0, 'h', 0, ' ', 0, ' ', 0, /* 16 */
+
+    '/', 0, '0', 0, 'x', 0, '0', 0, '8', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, /* 22 */
+
+    '/', 0, '1', 0, '2', 0, '*', 0, '0', 0, '0', 0, '1', 0, 'K', 0, 'a', 0, /* 18 */
+    ',', 0, '1', 0, '1', 0, '6', 0, '*', 0, '0', 0, '0', 0, '1', 0, 'K', 0, 'g', 0, /* 20 */
+  };
+
+#elif defined (USE_STM3210E_EVAL)
+ #ifdef STM32F10X_XL
+uint8_t DFU_StringInterface0[DFU_SIZ_STRING_INTERFACE0] =
+  {
+    DFU_SIZ_STRING_INTERFACE0,
+    0x03,
+    // Interface 0: "@Internal Flash   /0x08000000/06*002Ka,506*002Kg"
+    '@', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'n', 0, 'a', 0, 'l', 0,  /* 18 */
+    ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0, 'h', 0, ' ', 0, ' ', 0, /* 16 */
+
+    '/', 0, '0', 0, 'x', 0, '0', 0, '8', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, /* 22 */
+
+    '/', 0, '0', 0, '6', 0, '*', 0, '0', 0, '0', 0, '2', 0, 'K', 0, 'a', 0, /* 18 */
+    ',', 0, '5', 0, '0', 0, '6', 0, '*', 0, '0', 0, '0', 0, '2', 0, 'K', 0, 'g', 0, /* 20 */
+  };
+ #else
+uint8_t DFU_StringInterface0[DFU_SIZ_STRING_INTERFACE0] =
+  {
+    DFU_SIZ_STRING_INTERFACE0,
+    0x03,
+    // Interface 0: "@Internal Flash   /0x08000000/06*002Ka,250*002Kg"
+    '@', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'n', 0, 'a', 0, 'l', 0,  /* 18 */
+    ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0, 'h', 0, ' ', 0, ' ', 0, /* 16 */
+
+    '/', 0, '0', 0, 'x', 0, '0', 0, '8', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, /* 22 */
+
+    '/', 0, '0', 0, '6', 0, '*', 0, '0', 0, '0', 0, '2', 0, 'K', 0, 'a', 0, /* 18 */
+    ',', 0, '2', 0, '5', 0, '0', 0, '*', 0, '0', 0, '0', 0, '2', 0, 'K', 0, 'g', 0, /* 20 */
+  };
+ #endif /* STM32F10X_XL */
+
+#elif defined (USE_STM32L152_EVAL)
+uint8_t DFU_StringInterface0[DFU_SIZ_STRING_INTERFACE0] =
+  {
+    DFU_SIZ_STRING_INTERFACE0,
+    0x03,
+    // Interface 0: "@Internal Flash   /0x08000000/48*256 a,464*256 g"
+    '@', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'n', 0, 'a', 0, 'l', 0,  /* 18 */
+    ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0, 'h', 0, ' ', 0, ' ', 0, /* 16 */
+
+    '/', 0, '0', 0, 'x', 0, '0', 0, '8', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, /* 22 */
+
+    '/', 0, '4', 0, '8', 0, '*', 0, '2', 0, '5', 0, '6', 0, ' ', 0, 'a', 0, /* 18 */
+    ',', 0, '4', 0, '6', 0, '4', 0, '*', 0, '2', 0, '5', 0, '6', 0, ' ', 0, 'g', 0, /* 20 */
+  
+  };
+
+
+#elif defined (USE_STM32L152D_EVAL)
+uint8_t DFU_StringInterface0[DFU_SIZ_STRING_INTERFACE0] =
+  {
+    DFU_SIZ_STRING_INTERFACE0,
+    0x03,
+    // Interface 0: "@Internal Flash   /0x08000000/48*256 a,1488*256 g"
+    '@', 0, 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'n', 0, 'a', 0, 'l', 0,  /* 18 */
+    ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0, 'h', 0, ' ', 0, ' ', 0, /* 16 */
+
+    '/', 0, '0', 0, 'x', 0, '0', 0, '8', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, /* 22 */
+
+    '/', 0, '4', 0, '8', 0, '*', 0, '2', 0, '5', 0, '6', 0, ' ', 0, 'a', 0, /* 18 */
+    ',', 0, '1', 0, '4', 0, '8', 0, '8', 0, '*', 0, '2', 0, '5', 0, '6', 0, ' ', 0, 'g', 0, /* 22 */ 
+  };
+
+#endif /* USE_STM3210B_EVAL */
+
+#if defined(USE_STM3210B_EVAL) || defined(USE_STM3210E_EVAL)
+uint8_t DFU_StringInterface1[DFU_SIZ_STRING_INTERFACE1] =
+  {
+    DFU_SIZ_STRING_INTERFACE1,
+    0x03,
+    // Interface 1: "@ SPI Flash: M25P64  /0x00000000/128*064Kg"
+    '@', 0, 'S', 0, 'P', 0, 'I', 0, ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0,
+    'h', 0, ' ', 0, ':', 0, ' ', 0, 'M', 0, '2', 0, '5', 0, 'P', 0, '6', 0, '4', 0,
+    '/', 0, '0', 0, 'x', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0,
+    '/', 0, '1', 0, '2', 0, '8', 0, '*', 0, '6', 0, '4', 0, 'K', 0, 'g', 0
+  };
+#endif /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+
+#ifdef USE_STM3210E_EVAL
+uint8_t DFU_StringInterface2_1[DFU_SIZ_STRING_INTERFACE2] =
+  {
+    DFU_SIZ_STRING_INTERFACE2,
+    0x03,
+    // Interface 1: "@ NOR Flash: M29W128 /0x64000000/256*064Kg"
+    '@', 0, 'N', 0, 'O', 0, 'R', 0, ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0,
+    'h', 0, ' ', 0, ':', 0, ' ', 0, 'M', 0, '2', 0, '9', 0, 'W', 0, '1', 0, '2', 0, '8', 0, 'F', 0,
+    '/', 0, '0', 0, 'x', 0, '6', 0, '4', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0,
+    '/', 0, '0', 0, '2', 0, '5', 0, '6', 0, '*', 0, '6', 0, '4', 0, 'K', 0, 'g', 0
+  };
+uint8_t DFU_StringInterface2_2[DFU_SIZ_STRING_INTERFACE2] =
+  {
+    DFU_SIZ_STRING_INTERFACE2,
+    0x03,
+    // Interface 1: "@ NOR Flash: M29W128 /0x64000000/128*128Kg"
+    '@', 0, 'N', 0, 'O', 0, 'R', 0, ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0,
+    'h', 0, ' ', 0, ':', 0, ' ', 0, 'M', 0, '2', 0, '9', 0, 'W', 0, '1', 0, '2', 0, '8', 0, 'G', 0,
+    '/', 0, '0', 0, 'x', 0, '6', 0, '4', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0,
+    '/', 0, '1', 0, '2', 0, '8', 0, '*', 0, '1', 0, '2', 0, '8', 0, 'K', 0, 'g', 0
+  };
+
+uint8_t DFU_StringInterface2_3[DFU_SIZ_STRING_INTERFACE2] =
+  {
+    DFU_SIZ_STRING_INTERFACE2,
+    0x03,
+    // Interface 1: "@ NOR Flash:S29GL128 /0x64000000/128*128Kg"
+    '@', 0, 'N', 0, 'O', 0, 'R', 0, ' ', 0, 'F', 0, 'l', 0, 'a', 0, 's', 0,
+    'h', 0, ' ', 0, ':', 0, ' ', 0, 'S', 0, '2', 0, '9', 0, 'G', 0, 'L', 0 , '1', 0, '2', 0, '8', 0,
+    '/', 0, '0', 0, 'x', 0, '6', 0, '4', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0,
+    '/', 0, '1', 0, '2', 0, '8', 0, '*', 0, '1', 0, '2', 0, '8', 0, 'K', 0, 'g', 0
+  };
+#endif /* USE_STM3210E_EVAL */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_prop.c
new file mode 100644
index 0000000..addfc43
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_prop.c
@@ -0,0 +1,745 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processings related to DFU demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "hw_config.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "dfu_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t wBlockNum = 0, wlength = 0;
+uint32_t Manifest_State = Manifest_complete;
+uint32_t Pointer = ApplicationAddress;  /* Base Address to Erase, Program or Read */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    DFU_init,
+    DFU_Reset,
+    DFU_Status_In,
+    DFU_Status_Out,
+    DFU_Data_Setup,
+    DFU_NoData_Setup,
+    DFU_Get_Interface_Setting,
+    DFU_GetDeviceDescriptor,
+    DFU_GetConfigDescriptor,
+    DFU_GetStringDescriptor,
+    0,                    /*DFU_EP0Buffer*/
+    bMaxPacketSize0       /*Max Packet size*/
+  };
+
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    DFU_GetConfiguration,
+    DFU_SetConfiguration,
+    DFU_GetInterface,
+    DFU_SetInterface,
+    DFU_GetStatus,
+    DFU_ClearFeature,
+    DFU_SetEndPointFeature,
+    DFU_SetDeviceFeature,
+    DFU_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)DFU_DeviceDescriptor,
+    DFU_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)DFU_ConfigDescriptor,
+    DFU_SIZ_CONFIG_DESC
+  };
+#ifdef USE_STM3210E_EVAL
+ ONE_DESCRIPTOR DFU_String_Descriptor[7] =
+#elif defined(USE_STM3210B_EVAL) 
+ ONE_DESCRIPTOR DFU_String_Descriptor[6] =
+#elif defined(USE_STM32L152_EVAL) || defined(USE_STM32L152D_EVAL) ||defined(USE_STM32373C_EVAL) ||defined(USE_STM32303C_EVAL)
+ ONE_DESCRIPTOR DFU_String_Descriptor[5] =
+#endif /* USE_STM3210E_EVAL */
+  {
+    {       (uint8_t*)DFU_StringLangId,          DFU_SIZ_STRING_LANGID       },
+    {       (uint8_t*)DFU_StringVendor,          DFU_SIZ_STRING_VENDOR       },
+    {       (uint8_t*)DFU_StringProduct,         DFU_SIZ_STRING_PRODUCT      },
+    {       (uint8_t*)DFU_StringSerial,          DFU_SIZ_STRING_SERIAL       },
+    {       (uint8_t*)DFU_StringInterface0,      DFU_SIZ_STRING_INTERFACE0   }
+#ifdef USE_STM3210B_EVAL
+    ,
+    {       (uint8_t*)DFU_StringInterface1,      DFU_SIZ_STRING_INTERFACE1   }
+#endif /* USE_STM3210B_EVAL */
+#ifdef USE_STM3210E_EVAL 
+    ,
+    {       (uint8_t*)DFU_StringInterface1,      DFU_SIZ_STRING_INTERFACE1   },
+    {       (uint8_t*)DFU_StringInterface2_1,    DFU_SIZ_STRING_INTERFACE2   }    
+#endif /* USE_STM3210E_EVAL */
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+extern  uint8_t DeviceState ;
+extern  uint8_t DeviceStatus[6];
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : DFU_init.
+* Description    : DFU init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_init(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  /* Update the serial number string descriptor with the data from the unique ID*/
+  Get_SerialNum();
+
+  pInfo->Current_Configuration = 0;
+
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  /* Enable USB interrupts */
+  USB_Interrupts_Config();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : DFU_Reset.
+* Description    : DFU reset routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_Reset(void)
+{
+  /* Set DFU_DEVICE as not configured */
+  Device_Info.Current_Configuration = 0;
+
+  /* Current Feature initialization */
+  pInformation->Current_Feature = DFU_ConfigDescriptor[7];
+
+  _SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  _SetEPType(ENDP0, EP_CONTROL);
+  _SetEPTxStatus(ENDP0, EP_TX_NAK);
+  _SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  _SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  SetEPTxCount(ENDP0, Device_Property.MaxPacketSize);
+  Clear_Status_Out(ENDP0);
+  SetEPRxValid(ENDP0);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+
+  /* Set the new control state of the device to Attached */
+  bDeviceState = ATTACHED;
+}
+/*******************************************************************************
+* Function Name  : DFU_SetConfiguration.
+* Description    : Update the device state to configured.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_SetConfiguration(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+}
+/*******************************************************************************
+* Function Name  : DFU_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+/*******************************************************************************
+* Function Name  : DFU_Status_In.
+* Description    : DFU status IN routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_Status_In(void)
+{}
+
+/*******************************************************************************
+* Function Name  : DFU_Status_Out.
+* Description    : DFU status OUT routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_Status_Out (void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+  uint32_t Addr;
+
+  if (pInfo->USBbRequest == DFU_GETSTATUS)
+  {
+    if (DeviceState == STATE_dfuDNBUSY)
+    {
+      if (wBlockNum == 0)   /* Decode the Special Command*/
+      {
+        if ((MAL_Buffer[0] ==  CMD_GETCOMMANDS) && (wlength == 1))
+        {}
+        else if  (( MAL_Buffer[0] ==  CMD_SETADDRESSPOINTER ) && (wlength == 5))
+        {
+          Pointer  = MAL_Buffer[1];
+          Pointer += MAL_Buffer[2] << 8;
+          Pointer += MAL_Buffer[3] << 16;
+          Pointer += MAL_Buffer[4] << 24;
+        }
+        else if (( MAL_Buffer[0] ==  CMD_ERASE ) && (wlength == 5))
+        {
+          Pointer  = MAL_Buffer[1];
+          Pointer += MAL_Buffer[2] << 8;
+          Pointer += MAL_Buffer[3] << 16;
+          Pointer += MAL_Buffer[4] << 24;
+          MAL_Erase(Pointer);
+        }
+      }
+
+      else if (wBlockNum > 1)  // Download Command
+      {
+        Addr = ((wBlockNum - 2) * wTransferSize) + Pointer;
+        MAL_Write(Addr, wlength);
+      }
+      wlength = 0;
+      wBlockNum = 0;
+
+      DeviceState =  STATE_dfuDNLOAD_SYNC;
+      DeviceStatus[4] = DeviceState;
+      DeviceStatus[1] = 0;
+      DeviceStatus[2] = 0;
+      DeviceStatus[3] = 0;
+      return;
+    }
+    else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/
+    {
+      DFU_write_crc();
+      return;
+    }
+  }
+  return;
+}
+
+/*******************************************************************************
+* Function Name  : DFU_Data_Setup.
+* Description    : Handle the data class specific requests.
+* Input          : RequestNb.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT DFU_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+  CopyRoutine = NULL;
+
+  if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+  {
+    if (RequestNo == DFU_UPLOAD && (DeviceState == STATE_dfuIDLE
+                                    || DeviceState == STATE_dfuUPLOAD_IDLE ))
+    {
+      CopyRoutine = UPLOAD;
+    }
+    else if (RequestNo == DFU_DNLOAD && (DeviceState == STATE_dfuIDLE
+                                         || DeviceState == STATE_dfuDNLOAD_IDLE))
+    {
+      DeviceState = STATE_dfuDNLOAD_SYNC;
+      CopyRoutine = DNLOAD;
+    }
+    else if (RequestNo == DFU_GETSTATE)
+    {
+      CopyRoutine = GETSTATE;
+    }
+    else if (RequestNo == DFU_GETSTATUS)
+    {
+      CopyRoutine = GETSTATUS;
+    }
+    else
+    {
+      return USB_UNSUPPORT;
+    }
+  }
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : DFU_NoData_Setup.
+* Description    : Handle the No data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT DFU_NoData_Setup(uint8_t RequestNo)
+{
+
+  if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+  {
+    /*DFU_NDLOAD*/
+    if (RequestNo == DFU_DNLOAD)
+    {
+      /* End of DNLOAD operation*/
+      if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE )
+      {
+        Manifest_State = Manifest_In_Progress;
+        DeviceState = STATE_dfuMANIFEST_SYNC;
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0;
+        DeviceStatus[4] = DeviceState;
+        return USB_SUCCESS;
+      }
+    }
+    /*DFU_UPLOAD*/
+    else if (RequestNo == DFU_UPLOAD)
+    {
+      DeviceState = STATE_dfuIDLE;
+      DeviceStatus[1] = 0;
+      DeviceStatus[2] = 0;
+      DeviceStatus[3] = 0;
+      DeviceStatus[4] = DeviceState;
+      return USB_SUCCESS;
+    }
+
+    /*DFU_CLRSTATUS*/
+    else if (RequestNo == DFU_CLRSTATUS)
+    {
+
+      if (DeviceState == STATE_dfuERROR)
+      {
+        DeviceState = STATE_dfuIDLE;
+        DeviceStatus[0] = STATUS_OK;/*bStatus*/
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
+        DeviceStatus[4] = DeviceState;/*bState*/
+        DeviceStatus[5] = 0;/*iString*/
+      }
+      else
+      {   /*State Error*/
+        DeviceState = STATE_dfuERROR;
+        DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
+        DeviceStatus[4] = DeviceState;/*bState*/
+        DeviceStatus[5] = 0;/*iString*/
+      }
+      return USB_SUCCESS;
+    }
+    /*DFU_ABORT*/
+    else if (RequestNo == DFU_ABORT)
+    {
+      if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC
+          || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC
+          || DeviceState == STATE_dfuUPLOAD_IDLE )
+      {
+        DeviceState = STATE_dfuIDLE;
+        DeviceStatus[0] = STATUS_OK;
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
+        DeviceStatus[4] = DeviceState;
+        DeviceStatus[5] = 0; /*iString*/
+        wBlockNum = 0;
+        wlength = 0;
+      }
+      return USB_SUCCESS;
+    }
+  }
+
+
+  return USB_UNSUPPORT;
+
+} /* End of DFU_NoData_Setup */
+
+/*******************************************************************************
+* Function Name  : DFU_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *DFU_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : DFU_GetConfigDescriptor.
+* Description    : Gets the configuration descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *DFU_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData (Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : DFU_GetStringDescriptor.
+* Description    : Gets the string descriptors according to the needed index.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *DFU_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+
+  if (wValue0 > 8)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &DFU_String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DFU_Get_Interface_Setting.
+* Description    : tests the interface and the alternate setting according to the
+*                  supported one.
+* Input          : - Interface : interface number.
+*                  - AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT DFU_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 3)
+  {
+    return USB_UNSUPPORT;   /* In this application we don't have more than 3 AlternateSettings */
+  }
+  else if (Interface > 2)
+  {
+    return USB_UNSUPPORT; /* In this application we have only 1 interfaces */
+  }
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : UPLOAD
+* Description    : Upload routine.
+* Input          : Length.
+* Output         : None.
+* Return         : Pointer to data.
+*******************************************************************************/
+uint8_t *UPLOAD(uint16_t Length)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+  uint8_t B1, B0;
+  uint16_t offset, returned;
+  uint8_t *Phy_Addr = NULL;
+  uint32_t Addr = 0;
+
+  B0 = pInfo->USBwValues.bw.bb0;
+  B1 = pInfo->USBwValues.bw.bb1;
+  wBlockNum = (uint16_t)B1;
+  wBlockNum = wBlockNum * 0x100;
+  wBlockNum += (uint16_t)B0; /* wBlockNum value updated*/
+
+  B0 = pInfo->USBwLengths.bw.bb0;
+  B1 =  pInfo->USBwLengths.bw.bb1;
+  wlength = (uint16_t)B0;
+  wlength = wlength * 0x100;
+  wlength += (uint16_t)B1; /* wlength value updated*/
+
+  offset = pInformation->Ctrl_Info.Usb_wOffset;
+
+  if (wBlockNum == 0)  /* Get Command */
+  {
+    if (wlength > 3)
+    {
+      DeviceState = STATE_dfuIDLE ;
+    }
+    else
+    {
+      DeviceState = STATE_dfuUPLOAD_IDLE;
+    }
+
+    DeviceStatus[4] = DeviceState;
+    DeviceStatus[1] = 0;
+    DeviceStatus[2] = 0;
+    DeviceStatus[3] = 0;
+
+    MAL_Buffer[0] = CMD_GETCOMMANDS;
+    MAL_Buffer[1] = CMD_SETADDRESSPOINTER;
+    MAL_Buffer[2] = CMD_ERASE;
+
+    if (Length == 0)
+    {
+      pInformation->Ctrl_Info.Usb_wLength = 3 ;
+      return NULL;
+    }
+
+    return(&MAL_Buffer[0]);
+  }
+  else if (wBlockNum > 1)
+  {
+    DeviceState = STATE_dfuUPLOAD_IDLE ;
+    DeviceStatus[4] = DeviceState;
+    DeviceStatus[1] = 0;
+    DeviceStatus[2] = 0;
+    DeviceStatus[3] = 0;
+    Addr = ((wBlockNum - 2) * wTransferSize) + Pointer;  /* Change is Accelerated*/
+
+    Phy_Addr = MAL_Read(Addr, wlength);
+    returned = wlength - offset;
+
+    if (Length == 0)
+    {
+      pInformation->Ctrl_Info.Usb_wLength = returned ;
+      return NULL;
+    }
+    return(Phy_Addr + offset);
+  }
+  else  /* unsupported wBlockNum */
+  {
+    DeviceState = STATUS_ERRSTALLEDPKT;
+    DeviceStatus[4] = DeviceState;
+    DeviceStatus[1] = 0;
+    DeviceStatus[2] = 0;
+    DeviceStatus[3] = 0;
+
+    return NULL;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : DNLOAD
+* Description    : Download routine.
+* Input          : Length.
+* Output         : None.
+* Return         : Pointer to data.
+*******************************************************************************/
+uint8_t *DNLOAD (uint16_t Length)
+{
+  DEVICE_INFO             *pInfo = &Device_Info;
+  uint8_t         B1, B0;
+  uint16_t          offset, returned;
+
+  B0 = pInfo->USBwValues.bw.bb0;
+  B1 = pInfo->USBwValues.bw.bb1;
+  wBlockNum = (uint16_t)B1;
+  wBlockNum = wBlockNum * 0x100;
+  wBlockNum += (uint16_t)B0;
+  B0 = pInfo->USBwLengths.bw.bb0;
+  B1 =  pInfo->USBwLengths.bw.bb1;
+  wlength = (uint16_t)B0;
+  wlength = wlength * 0x100;
+  wlength += (uint16_t)B1;
+
+  offset = pInfo->Ctrl_Info.Usb_wOffset;
+
+  DeviceState = STATE_dfuDNLOAD_SYNC;
+  DeviceStatus[4] = DeviceState;
+
+  returned = wlength - offset;
+
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = returned ;
+    return NULL;
+  }
+
+  return((uint8_t*)MAL_Buffer + offset);
+}
+
+/*******************************************************************************
+* Function Name  : GETSTATE.
+* Description    : Get State request routine.
+* Input          : Length.
+* Output         : None.
+* Return         : Pointer to data.
+*******************************************************************************/
+uint8_t *GETSTATE(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 1 ;
+    return NULL;
+  }
+  else
+    return(&DeviceState);
+}
+
+/*******************************************************************************
+* Function Name  : GETSTATUS.
+* Description    : Get Status request routine.
+* Input          : Length.
+* Output         : None.
+* Return         : Pointer to data.
+*******************************************************************************/
+uint8_t *GETSTATUS(uint16_t Length)
+{
+  switch (DeviceState)
+  {
+    case   STATE_dfuDNLOAD_SYNC:
+      if (wlength != 0)
+      {
+        DeviceState = STATE_dfuDNBUSY;
+        DeviceStatus[4] = DeviceState;
+        if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE))
+        {
+          MAL_GetStatus(Pointer, 0, DeviceStatus);
+        }
+        else
+        {
+          MAL_GetStatus(Pointer, 1, DeviceStatus);
+        }
+      }
+      else  /* (wlength==0)*/
+      {
+        DeviceState = STATE_dfuDNLOAD_IDLE;
+        DeviceStatus[4] = DeviceState;
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0;
+
+      }
+      break;
+    case   STATE_dfuMANIFEST_SYNC :
+      if (Manifest_State == Manifest_In_Progress)
+      {
+        DeviceState = STATE_dfuMANIFEST;
+        DeviceStatus[4] = DeviceState;
+        DeviceStatus[1] = 1;             /*bwPollTimeout = 1ms*/
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0;
+        //break;
+      }
+      else if (Manifest_State == Manifest_complete && Config_Descriptor.Descriptor[20]
+               & 0x04)
+      {
+        DeviceState = STATE_dfuIDLE;
+        DeviceStatus[4] = DeviceState;
+        DeviceStatus[1] = 0;
+        DeviceStatus[2] = 0;
+        DeviceStatus[3] = 0;
+        //break;
+      }
+      break;
+    default :
+      break;
+  }
+
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 6 ;
+    return NULL;
+  }
+  else
+    return(&(DeviceStatus[0]));
+}
+
+/*******************************************************************************
+* Function Name  : DFU_write_crc.
+* Description    : DFU Write CRC routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void DFU_write_crc(void)
+{
+  Manifest_State = Manifest_complete;
+
+  if (Config_Descriptor.Descriptor[20] & 0x04)
+  {
+    DeviceState = STATE_dfuMANIFEST_SYNC;
+    DeviceStatus[4] = DeviceState;
+    DeviceStatus[1] = 0;
+    DeviceStatus[2] = 0;
+    DeviceStatus[3] = 0;
+    return;
+  }
+  else
+  {
+    DeviceState = STATE_dfuMANIFEST_WAIT_RESET;
+    DeviceStatus[4] = DeviceState;
+    DeviceStatus[1] = 0;
+    DeviceStatus[2] = 0;
+    DeviceStatus[3] = 0;
+
+    Reset_Device();
+
+    return;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_pwr.c
new file mode 100644
index 0000000..a2253a8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Device_Firmware_Upgrade/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/JoyStickMouse.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/JoyStickMouse.ewd
new file mode 100644
index 0000000..e4dd3ce
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/JoyStickMouse.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..18520fb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/MDK-ARM/JoyStickMouse.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/MDK-ARM/JoyStickMouse.uvproj
new file mode 100644
index 0000000..87a39a2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/MDK-ARM/JoyStickMouse.uvproj
@@ -0,0 +1,12713 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>STM3210B-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>4223</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM3210B-EVAL\</OutputDirectory>
+          <OutputName>STM3210B-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210B-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x8000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32f37x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>hw_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\hw_config.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_desc.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_istr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_istr.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_prop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_prop.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_endp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_endp.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32l1xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32l1xx.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
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+                    <EnumInt>2</EnumInt>
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+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
+            <File>
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+              <FileType>2</FileType>
+              <FilePath>..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_hd.s</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
+                  <Aads>
+                    <interw>2</interw>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
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+                    <SwStkChk>2</SwStkChk>
+                    <NoWarn>2</NoWarn>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Aads>
+                </FileArmAds>
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+            <File>
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+              <FileType>2</FileType>
+              <FilePath>..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\arm\startup_stm32f10x_ld.s</FilePath>
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+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
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+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>0</IncludeInBuild>
+                  <AlwaysBuild>0</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                </CommonProperty>
+                <FileArmAds>
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+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32303c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>STM3210E-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F103ZE</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>4216</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM3210E-EVAL\</OutputDirectory>
+          <OutputName>STM3210E-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210E-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
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+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
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+            <hadIRAM2>0</hadIRAM2>
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+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
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+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
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+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+              <Ocm2>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
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+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
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+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
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+            <oTime>0</oTime>
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+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
+            </VariousControls>
+          </Cads>
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+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
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+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x8000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>User</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32f37x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</FilePath>
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+                  <IncludeLibraryModules></IncludeLibraryModules>
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+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
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+                </FileArmAds>
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+            </File>
+            <File>
+              <FileName>hw_config.c</FileName>
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+              <FilePath>..\src\hw_config.c</FilePath>
+            </File>
+            <File>
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+              <FilePath>..\src\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>usb_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\usb_desc.c</FilePath>
+            </File>
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+              <FilePath>..\src\usb_istr.c</FilePath>
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+              <FilePath>..\src\usb_prop.c</FilePath>
+            </File>
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+              <FilePath>..\src\usb_pwr.c</FilePath>
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+              <FilePath>..\src\usb_endp.c</FilePath>
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+              <FilePath>..\src\stm32_it.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32f10x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\src\system_stm32f10x.c</FilePath>
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+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
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+                      <Define></Define>
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+                      <IncludePath></IncludePath>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
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+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
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+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
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+          <Device>STM32F103ZG</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20017FFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
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+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>5094</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
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+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
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+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
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+            <HexRangeHighAddress>0</HexRangeHighAddress>
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+          <SimDlls>
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+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
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+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
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+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
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+              <Define>USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</IncludePath>
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+          <GroupName>CMSIS</GroupName>
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+                <NoWarn>2</NoWarn>
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+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>stm32373c_eval.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32303C_EVAL</GroupName>
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+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
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+                <uThumb>2</uThumb>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+                <NoWarn>2</NoWarn>
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+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L151VB</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>5246</DeviceId>
+          <RegisterFile>stm32l1xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\ST\STM32L15x\STM32L15x.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
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+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
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+          <OutputDirectory>.\STM32L152-EVAL\</OutputDirectory>
+          <OutputName>STM32L152-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
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+          <CreateHexFile>0</CreateHexFile>
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+          <ListingPath>.\STM32L152-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
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+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <nStopU2X>0</nStopU2X>
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+          <BeforeMake>
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+            <UserProg1Name></UserProg1Name>
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+          <SVCSIdString></SVCSIdString>
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+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
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+        <DebugOption>
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+            <RestoreToolbox>1</RestoreToolbox>
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+          <Target>
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+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
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+          <TargetDlls>
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+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
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+        <Utilities>
+          <Flash1>
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+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
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+          <Flash3></Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
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+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
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+                <Size>0x0</Size>
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+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_MD, USE_STM32L152_EVAL</Define>
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+            </VariousControls>
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+          <GroupName>User</GroupName>
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+              <FilePath>..\src\hw_config.c</FilePath>
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+              <FilePath>..\src\main.c</FilePath>
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+              <FilePath>..\src\usb_prop.c</FilePath>
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+                  <IncludePath></IncludePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
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+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
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+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
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+              <CustomArgument></CustomArgument>
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+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
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+          <GroupName>Doc</GroupName>
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+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
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+      <ToolsetName>ARM-ADS</ToolsetName>
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+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_md.s" ("STM32L15xx Medium density Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000)</FlashDriverDll>
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+          <RegisterFile>stm32l1xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
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+          <InfinionOptionDll></InfinionOptionDll>
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+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
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+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
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+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
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+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
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+            <InitializationFile></InitializationFile>
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+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
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+              <FilePath>..\src\usb_prop.c</FilePath>
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new file mode 100644
index 0000000..bca9a78
--- /dev/null
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new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..b921d59
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );
+                        vector(  id = 1, fill = "Reset_Handler" );                         /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..04e7bf2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL_XL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103zg" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1715575623" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.387783740" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_XL.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..c6a41a5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
new file mode 100644
index 0000000..252b6cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL_XL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
index 0271fb5..20fdd4a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/HiTOP/STM3210X-XL_BANK1/Settings/STM32F10x_XL_Bank1.lsl
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
@@ -23,7 +23,7 @@
 
 
 #ifndef __STACK
-#  define __STACK                       2k
+#  define __STACK                       8k
 #endif
 #ifndef __HEAP
 #  define __HEAP                        2k
@@ -57,8 +57,8 @@ memory stm32f103flash
 {
     mau = 8;
     type = rom;
-    size = 512k;
-    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+    size = 0x100000;
+    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
 }
 
 memory stm32f103ram
@@ -70,14 +70,6 @@ memory stm32f103ram
 }
 
 #endif /* __MEMORY */
-section_layout ::linear
-{
-	group( contiguous )
-	{
-		select ".bss.stack";
-		select "stack";
-	}
-}
 
 
 //
@@ -95,8 +87,8 @@ section_setup ::linear
                                               no_inline
                                             )
                 {
-                        vector ( id = 0, fill = "_stacklabel" ); // FIXME: "_lc_ub_stack" does not work
-                        vector ( id = 1, fill = "_START" );
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                             /* Reset Handler                           */
                         vector ( id = 2, optional, fill = "NMI_Handler" );
                         vector ( id = 3, optional, fill = "HardFault_Handler" );
                         vector ( id = 4, optional, fill = "MemManage_Handler" );
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..855ed7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.as.nowarning.1983734224" name="Suppress warnings" superClass="com.tasking.arm.as.nowarning" valueType="stringList"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..73af882
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
new file mode 100644
index 0000000..80853f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32303C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32303C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
new file mode 100644
index 0000000..3ccf590
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f30x.lsl
+//
+//  Version     :  @(#)stm32f30x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F30x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F30x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       6k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+
+memory STM32F30x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE - 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM8k
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    priority = 1;
+    map ( size = 8k, dest_offset=0x10000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2 interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2 global interrupts
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB Device High Priority or CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );      // USB Device Low Priority or CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break irq and TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );        // TIM1 Update irq and TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation irqs and TIM17 global irq
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup interrupt
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break interrupt
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update interrupt
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 trigger and Comm. interrupt
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare interrupt
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4 global interrupt
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "ADC4_IRQHandler" );                 // ADC4 global interrupt
+                        vector ( id = 80, optional, fill = "COMP1_2_3_IRQHandler" );            // COMP1, COMP2 and COMP3 global interrupt
+                        vector ( id = 81, optional, fill = "COMP4_5_6_IRQHandler" );            // COMP5, COMP6 and COMP4 global interrupt
+                        vector ( id = 82, optional, fill = "COMP7_IRQHandler" );                // COMP7 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt  remap
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt  remap
+                        vector ( id = 92, optional, fill = "USBWakeUp_RMP_IRQHandler" );        // USB Wakeup Interrupt remap
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32373C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32373C_EVAL/.cproject
new file mode 100644
index 0000000..5a42687
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32373C_EVAL/.cproject
@@ -0,0 +1,113 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32373C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f373vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F37X"/>
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f37x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..69a8de0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
new file mode 100644
index 0000000..d494039
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..3433fcf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/.cproject
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152D-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152zd" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
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+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
new file mode 100644
index 0000000..26462e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152D-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152D-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..398250d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
new file mode 100644
index 0000000..9756e14
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\JoyStickMouse\TrueSTUDIO\STM3210B-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210B-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
new file mode 100644
index 0000000..d512d7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/STM3210E-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\JoyStickMouse\TrueSTUDIO\STM3210E-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210E-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..59eddb1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32F10X_XL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1578134158" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1314431980" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT}  ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.529651997" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1684401938" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1997653104" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.586288316" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1672805933" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os " valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.377284588" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.915646075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1739994990" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1049792298" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL_XL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.731011867" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.26443420" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.1289217812" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.144019967" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1807046025" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.704598245" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.478811538" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.864630601" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1692358135" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.820544888" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.710897842" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103ZG" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.160897551" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.417308276" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1343613995" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM32F103ZG\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1493511473" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
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+					<scannerInfoProvider id="specsFile">
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+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
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+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
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+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
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+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
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+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.;com.atollic.truestudio.exe.debug.toolchain.gcc.486923113;com.atollic.truestudio.gcc.input.377284588">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..b2d3c07
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
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+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\JoyStickMouse\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
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+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
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+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
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+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
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+<listEntry value="/STM3210E-EVAL_XL"/>
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+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..5929ca9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
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+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..11c9ee7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..1148d5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,315 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..734d809
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..c721f50
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.cproject
@@ -0,0 +1,362 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32L152-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os -mlong-calls" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1760166233" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<fileInfo id="com.atollic.truestudio.exe.debug.316348137.1684888439" name="stm32l1xx_flash_ramfunc.c" rcbsApplicability="disable" resourcePath="STM32L1xx_StdPeriph_Driver/stm32l1xx_flash_ramfunc.c" toolsToInvoke="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339.693972506">
+						<tool id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339.693972506" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339">
+							<option id="com.atollic.truestudio.gcc.misc.otherflags.615224276" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os -w" valueType="string"/>
+							<inputType id="com.atollic.truestudio.gcc.input.986914590" superClass="com.atollic.truestudio.gcc.input"/>
+						</tool>
+						<tool customBuildStep="true" id="org.eclipse.cdt.managedbuilder.ui.rcbs.1814497745" name="Resource Custom Build Step">
+							<inputType id="org.eclipse.cdt.managedbuilder.ui.rcbs.inputtype.1370441703" name="Resource Custom Build Step Input Type">
+								<additionalInput kind="additionalinputdependency" paths=""/>
+							</inputType>
+							<outputType id="org.eclipse.cdt.managedbuilder.ui.rcbs.outputtype.1794455711" name="Resource Custom Build Step Output Type"/>
+						</tool>
+					</fileInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..3065c71
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+	<name>STM32L152-EVAL</name>
+	<comment></comment>
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+					<value>true</value>
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+					<value></value>
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+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
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+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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+					<value>true</value>
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+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Device_Firmware_Upgrade/readme.txt</locationURI>
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+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
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+			<name>USB-FS-Device_Driver/usb_regs.c</name>
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+		<link>
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+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
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+		</link>
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+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..f14d2cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 14:38:58 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..1be62d5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_md Device with
+**                128KByte FLASH, 16KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000;    /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x80;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..bf57519
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/STM32L152D_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/STM32L152D_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash_ramfunc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash_ramfunc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/JoyStickMouse/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/hw_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/hw_config.h
new file mode 100644
index 0000000..f23e72a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/hw_config.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define CURSOR_STEP     20
+
+#define DOWN            2
+#define LEFT            3
+#define RIGHT           4
+#define UP              5
+
+/* Exported functions ------------------------------------------------------- */
+void Set_System(void);
+void Set_USBClock(void);
+void GPIO_AINConfig(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void USB_Cable_Config (FunctionalState NewState);
+void Joystick_Send(uint8_t Keys);
+uint8_t JoyState(void);
+void Get_SerialNum(void);
+
+#endif  /*__HW_CONFIG_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/platform_config.h
new file mode 100644
index 0000000..9bb96d1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/platform_config.h
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL, USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL)&&  !defined (USE_STM32373C_EVAL) &&  !defined (USE_STM32303C_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ //#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define USE_STM32373C_EVAL
+ #define USE_STM32303C_EVAL
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+
+  #define RCC_APB2Periph_ALLGPIO              (RCC_APB2Periph_GPIOA \
+                                               | RCC_APB2Periph_GPIOB \
+                                               | RCC_APB2Periph_GPIOC \
+                                               | RCC_APB2Periph_GPIOD \
+                                               | RCC_APB2Periph_GPIOE )
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+                                                
+  #define RCC_APB2Periph_ALLGPIO              (RCC_APB2Periph_GPIOA \
+                                               | RCC_APB2Periph_GPIOB \
+                                               | RCC_APB2Periph_GPIOC \
+                                               | RCC_APB2Periph_GPIOD \
+                                               | RCC_APB2Periph_GPIOE \
+                                               | RCC_APB2Periph_GPIOF \
+                                               | RCC_APB2Periph_GPIOG )
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+                                                
+  #define RCC_AHBPeriph_ALLGPIO               (RCC_AHBPeriph_GPIOA \
+                                               | RCC_AHBPeriph_GPIOB \
+                                               | RCC_AHBPeriph_GPIOC \
+                                               | RCC_AHBPeriph_GPIOD \
+                                               | RCC_AHBPeriph_GPIOE \
+										       | RCC_AHBPeriph_GPIOF \
+                                               | RCC_AHBPeriph_GPIOH)
+#elif defined (USE_STM32373C_EVAL)
+
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+ 
+  #define GPIO_Pin_KEY                        GPIO_Pin_6   /* PE.6 */
+  #define GPIO_Pin_UP                         GPIO_Pin_10  /* PF.10 */
+  #define GPIO_Pin_DOWN                       GPIO_Pin_2  /* PF.2 */
+  #define GPIO_Pin_LEFT                       GPIO_Pin_4  /* PF.4 */
+  #define GPIO_Pin_RIGHT                      GPIO_Pin_9  /* PF.9 */
+  
+  #define RCC_AHBPeriph_GPIO_JOY_SET1        RCC_AHBPeriph_GPIOF
+
+  #define GPIO_RIGHT                          GPIOF
+  #define GPIO_LEFT                           GPIOF
+  #define GPIO_DOWN                           GPIOF
+  #define GPIO_UP                             GPIOF
+  #define GPIO_KEY                            GPIOE
+
+#elif defined (USE_STM32303C_EVAL)
+
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+
+ 
+  #define GPIO_Pin_KEY                        GPIO_Pin_6   /* PE.6 */
+  #define GPIO_Pin_UP                         GPIO_Pin_7  /* PE.7 */
+  #define GPIO_Pin_DOWN                       GPIO_Pin_5  /* PD.5 */
+  #define GPIO_Pin_LEFT                       GPIO_Pin_5  /* PB.4 */
+  #define GPIO_Pin_RIGHT                      GPIO_Pin_6  /* PD.2 */
+  
+  #define RCC_AHBPeriph_GPIO_JOY_SET1        RCC_AHBPeriph_GPIOF
+
+  #define GPIO_RIGHT                          GPIOD
+  #define GPIO_LEFT                           GPIOB
+  #define GPIO_DOWN                           GPIOD
+  #define GPIO_UP                             GPIOE
+  #define GPIO_KEY                            GPIOE
+
+                                     
+#define RCC_AHBPeriph_ALLGPIO                 (RCC_AHBPeriph_GPIOA \
+                                              | RCC_AHBPeriph_GPIOB \
+                                              | RCC_AHBPeriph_GPIOC \
+                                              | RCC_AHBPeriph_GPIOD \
+                                              | RCC_AHBPeriph_GPIOE \
+                                              | RCC_AHBPeriph_GPIOF )
+#define GPIO_KEY_EXTI_Line                  EXTI_Line18
+#endif /* USE_STM3210B_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32_it.h
new file mode 100644
index 0000000..82d81f2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32_it.h
@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void USBWakeUp_IRQHandler(void);
+
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32l1xx_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32l1xx_conf.h
new file mode 100644
index 0000000..ae4a251
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/stm32l1xx_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_CONF_H
+#define __STM32L1xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32l1xx_adc.h"
+#include "stm32l1xx_crc.h"
+#include "stm32l1xx_comp.h"
+#include "stm32l1xx_dac.h" 
+#include "stm32l1xx_dbgmcu.h"
+#include "stm32l1xx_dma.h"
+#include "stm32l1xx_exti.h"
+#include "stm32l1xx_flash.h"
+#include "stm32l1xx_gpio.h"
+#include "stm32l1xx_syscfg.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_iwdg.h"
+#include "stm32l1xx_lcd.h"
+#include "stm32l1xx_pwr.h"
+#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_rtc.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_tim.h" 
+#include "stm32l1xx_usart.h"
+#include "stm32l1xx_wwdg.h"
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32L1xx_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_conf.h
new file mode 100644
index 0000000..ff5541b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_conf.h
@@ -0,0 +1,91 @@
+/**
+  ******************************************************************************
+  * @file    usb_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Joystick Mouse demo configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CONF_H
+#define __USB_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+/*-------------------------------------------------------------*/
+/* EP_NUM */
+/* defines how many endpoints are used by the device */
+/*-------------------------------------------------------------*/
+#define EP_NUM     (2)
+
+/*-------------------------------------------------------------*/
+/* --------------   Buffer Description Table  -----------------*/
+/*-------------------------------------------------------------*/
+/* buffer table base address */
+/* buffer table base address */
+#define BTABLE_ADDRESS      (0x00)
+
+/* EP0  */
+/* rx/tx buffer base address */
+#define ENDP0_RXADDR        (0x18)
+#define ENDP0_TXADDR        (0x58)
+
+/* EP1  */
+/* tx buffer base address */
+#define ENDP1_TXADDR        (0x100)
+
+
+/*-------------------------------------------------------------*/
+/* -------------------   ISTR events  -------------------------*/
+/*-------------------------------------------------------------*/
+/* IMR_MSK */
+/* mask defining which events has to be handled */
+/* by the device application software */
+#define IMR_MSK (CNTR_CTRM  | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM  | CNTR_SOFM \
+                 | CNTR_ESOFM | CNTR_RESETM )
+
+/* CTR service routines */
+/* associated to defined endpoints */
+/* #define  EP1_IN_Callback   NOP_Process*/
+#define  EP2_IN_Callback   NOP_Process
+#define  EP3_IN_Callback   NOP_Process
+#define  EP4_IN_Callback   NOP_Process
+#define  EP5_IN_Callback   NOP_Process
+#define  EP6_IN_Callback   NOP_Process
+#define  EP7_IN_Callback   NOP_Process
+
+#define  EP1_OUT_Callback   NOP_Process
+#define  EP2_OUT_Callback   NOP_Process
+#define  EP3_OUT_Callback   NOP_Process
+#define  EP4_OUT_Callback   NOP_Process
+#define  EP5_OUT_Callback   NOP_Process
+#define  EP6_OUT_Callback   NOP_Process
+#define  EP7_OUT_Callback   NOP_Process
+
+#endif /*__USB_CONF_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_istr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_istr.h
new file mode 100644
index 0000000..d2a07f6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_istr.h
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the peripherals header files in the user application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+ void USB_Istr(void);
+
+/* function prototypes Automatically built defining related macros */
+
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+#ifdef CTR_CALLBACK
+void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+void ESOF_Callback(void);
+#endif
+
+#endif /*__USB_ISTR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_prop.h
new file mode 100644
index 0000000..f228ad2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_prop.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Joystick Mouse demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PROP_H
+#define __USB_PROP_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _HID_REQUESTS
+{
+  GET_REPORT = 1,
+  GET_IDLE,
+  GET_PROTOCOL,
+
+  SET_REPORT = 9,
+  SET_IDLE,
+  SET_PROTOCOL
+} HID_REQUESTS;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Joystick_init(void);
+void Joystick_Reset(void);
+void Joystick_SetConfiguration(void);
+void Joystick_SetDeviceAddress (void);
+void Joystick_Status_In (void);
+void Joystick_Status_Out (void);
+RESULT Joystick_Data_Setup(uint8_t);
+RESULT Joystick_NoData_Setup(uint8_t);
+RESULT Joystick_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *Joystick_GetDeviceDescriptor(uint16_t );
+uint8_t *Joystick_GetConfigDescriptor(uint16_t);
+uint8_t *Joystick_GetStringDescriptor(uint16_t);
+RESULT Joystick_SetProtocol(void);
+uint8_t *Joystick_GetProtocolValue(uint16_t Length);
+RESULT Joystick_SetProtocol(void);
+uint8_t *Joystick_GetReportDescriptor(uint16_t Length);
+uint8_t *Joystick_GetHIDDescriptor(uint16_t Length);
+
+/* Exported define -----------------------------------------------------------*/
+#define Joystick_GetConfiguration          NOP_Process
+//#define Joystick_SetConfiguration          NOP_Process
+#define Joystick_GetInterface              NOP_Process
+#define Joystick_SetInterface              NOP_Process
+#define Joystick_GetStatus                 NOP_Process
+#define Joystick_ClearFeature              NOP_Process
+#define Joystick_SetEndPointFeature        NOP_Process
+#define Joystick_SetDeviceFeature          NOP_Process
+//#define Joystick_SetDeviceAddress          NOP_Process
+
+#define REPORT_DESCRIPTOR                  0x22
+
+#endif /* __USB_PROP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_pwr.h
new file mode 100644
index 0000000..31891f1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/inc/usb_pwr.h
@@ -0,0 +1,71 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+/* External variables --------------------------------------------------------*/
+extern  __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/readme.txt
new file mode 100644
index 0000000..11b5e84
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/readme.txt
@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB JoyStickMouse Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+This Demo provides a description of how to use the USB-FS-Device on the STM32F10xxx 
+STM32L15xxx and STM32F37xxx devices.
+The STM32F10x device is enumerated as an USB-FS-Device Joystick Mouse, that uses 
+the native PC Host USB-FS-Device HID driver.
+The Joystick mounted on the STM3210B-EVAL, STM3210E-EVAL,STM32F373C_EVAL,STM32F303C_EVAL
+STM32L152-EVAL and STM32L152D-EVAL boards is used to emulate the Mouse directions.
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain
+ + \TASKING: contains preconfigured projects for TASKING toolchain
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain           
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+
+  - STM32L152-EVAL Set-up 
+     - None.
+
+  - STM32L152D-EVAL Set-up 
+     - None.
+  
+  - STM32F373C_EVAL  Set-up 
+     - None.
+
+  - STM32F303C_EVAL  Set-up 
+     - None.
+    
+How to use it
+=============
+ + EWARM
+    - Open the JoyStickMouse.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices	
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the JoyStickMouse.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)    
+
+ + RIDE
+    - Open the JoyStickMouse.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 	
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+  + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/hw_config.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/hw_config.c
new file mode 100644
index 0000000..dccf436
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/hw_config.c
@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ErrorStatus HSEStartUpStatus;
+EXTI_InitTypeDef EXTI_InitStructure;
+
+/* Extern variables ----------------------------------------------------------*/
+extern __IO uint8_t PrevXferComplete;
+
+/* Private function prototypes -----------------------------------------------*/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Set_System
+* Description    : Configures Main system clocks & power.
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_System(void)
+{
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD)&& !defined(STM32L1XX_MD_PLUS)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /*STM32L1XX_XD */
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /* USB_USE_EXTERNAL_PULLUP */
+  
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32xxx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32xxx.c file
+     */ 
+
+  /* Enable the PWR clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined(STM32F37X)|| defined(STM32F30X)
+  /* Enable the SYSCFG module clock (used for the USB disconnect feature) */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+#endif /* STM32L1XX_XD */   
+
+  /* Set all the GPIOs to AIN *************************************************/
+ #if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)&& !defined(STM32F37X) && !defined(STM32F30X)
+  GPIO_AINConfig();
+#endif /* STM32L1XX_XD */     
+
+#if  defined(STM32F37X) || defined(STM32F30X)
+  
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+
+ /*Set PA11,12 as IN - USB_DM,DP*/
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+    
+  /*SET PA11,12 for USB: USB_DM,DP*/
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_14);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_14);
+ 
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+  
+  /*Enable Joystick GPIOs clock*/
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+  /*Configure the JoyStick IOs as input floating*/
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_4 | 
+                                GPIO_Pin_9 | GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; /*PullDown is mandatory for Joystick pins*/
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+  /*Configure the JoyStick IOs as input floating*/
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_5;                  
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; /*PullDown is mandatory for Joystick pins*/
+  GPIO_Init(GPIOB, &GPIO_InitStructure); 
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;  
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;  
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+#endif /*STM32F37X && STM32F30X*/  
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS) && !defined(STM32F37X)&& !defined(STM32F30X)
+     
+  /* Enable the USB disconnect GPIO clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE);
+
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /*STM32L1XX_MD*/
+
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);  
+#endif /* USB_USE_EXTERNAL_PULLUP */
+
+  /* Joystick buttons configuration *******************************************/
+  /* Configure the Joystick buttons in GPIO mode */
+  STM_EVAL_PBInit(Button_RIGHT, Mode_GPIO);
+  STM_EVAL_PBInit(Button_LEFT, Mode_GPIO);
+  STM_EVAL_PBInit(Button_UP, Mode_GPIO);
+  STM_EVAL_PBInit(Button_DOWN, Mode_GPIO);
+
+  /* Configure the Key button in EXTI mode ************************************/
+  STM_EVAL_PBInit(Button_KEY, Mode_EXTI);
+
+  /* Configure the EXTI line 18 connected internally to the USB IP ************/
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+
+  EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+}
+
+/*******************************************************************************
+* Function Name  : Set_USBClock
+* Description    : Configures USB Clock input (48MHz).
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Set_USBClock(void)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  /* Enable USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+
+#else
+  /* Select USBCLK source */
+  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
+  
+  /* Enable the USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+#endif /* STM32L1XX_XD */
+
+}
+
+/*******************************************************************************
+* Function Name  : GPIO_AINConfig
+* Description    : Configures all IOs as AIN to reduce the power consumption.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+#ifndef STM32F37X 
+void GPIO_AINConfig(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined(STM32F30X)
+  /* Enable all GPIOs Clock*/
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ALLGPIO, ENABLE);  
+#else 
+  /* Enable all GPIOs Clock*/
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ALLGPIO, ENABLE);
+#endif /* STM32L1XX_XD */
+
+  /* Configure all GPIO port pins in Analog Input mode (floating input trigger OFF) */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
+#if defined(STM32F30X)
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
+#else
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+#endif
+  //GPIO_Init(GPIOA, &GPIO_InitStructure); // Some GPIOA pins are used for JTAG and USB
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+#if defined (USE_STM32L152_EVAL)
+  GPIO_Init(GPIOH, &GPIO_InitStructure);
+#endif /* USE_STM32L152_EVAL */  
+
+#if defined (USE_STM32L152D_EVAL)
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  GPIO_Init(GPIOH, &GPIO_InitStructure);
+#endif /* USE_STM32L152D_EVAL */ 
+  
+#if defined (USE_STM3210E_EVAL)
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+#endif /* USE_STM3210E_EVAL */
+
+}
+#endif /*STM32F37X*/
+/*******************************************************************************
+* Function Name  : Enter_LowPowerMode.
+* Description    : Power-off system clocks and power while entering suspend mode.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Enter_LowPowerMode(void)
+{
+  /* Set the device state to suspend */
+  bDeviceState = SUSPENDED;
+
+  /* Clear EXTI Line18 pending bit */
+  EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+
+  /* Request to enter STOP mode with regulator in low power mode */
+  PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_WFI);
+}
+
+/*******************************************************************************
+* Function Name  : Leave_LowPowerMode.
+* Description    : Restores system clocks and power while exiting suspend mode.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Leave_LowPowerMode(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+  
+  /* Set the device state to the correct state */
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+  else
+  {
+    bDeviceState = ATTACHED;
+  }
+  
+  /*Enable SystemCoreClock*/
+  SystemInit();
+}
+
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config.
+* Description    : Configures the USB interrupts.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Interrupts_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* 2 bit for pre-emption priority, 2 bits for subpriority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+ 
+#if defined(STM32L1XX_MD)|| defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+#elif defined(STM32F37X)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#else /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure);   
+#endif
+  /* Enable the Key EXTI line Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = KEY_BUTTON_EXTI_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : USB_Cable_Config.
+* Description    : Software Connection/Disconnection of USB Cable.
+* Input          : NewState: new state.
+* Output         : None.
+* Return         : None
+*******************************************************************************/
+void USB_Cable_Config (FunctionalState NewState)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  if (NewState != DISABLE)
+  {
+    STM32L15_USB_CONNECT;
+  }
+  else
+  {
+    STM32L15_USB_DISCONNECT;
+  }  
+   
+#else
+  if (NewState != DISABLE)
+  {
+    GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+  else
+  {
+    GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+#endif /* STM32L1XX_MD */
+}
+/*******************************************************************************
+* Function Name : JoyState.
+* Description   : Decodes the Joystick direction.
+* Input         : None.
+* Output        : None.
+* Return value  : The direction value.
+*******************************************************************************/
+uint8_t JoyState(void)
+{
+   /* "right" key is pressed */
+#if !defined(USE_STM32373C_EVAL) && !defined(USE_STM32303C_EVAL)
+   if (!STM_EVAL_PBGetState(Button_RIGHT))
+#else
+     if (STM_EVAL_PBGetState(Button_RIGHT))
+#endif
+     {
+       return JOY_RIGHT;
+     }
+   /* "left" key is pressed */
+#if !defined(USE_STM32373C_EVAL) && !defined(USE_STM32303C_EVAL)
+   if (!STM_EVAL_PBGetState(Button_LEFT))
+#else
+     if (STM_EVAL_PBGetState(Button_LEFT))
+#endif
+     {
+       return JOY_LEFT;
+     }
+   /* "up" key is pressed */
+#if !defined(USE_STM32373C_EVAL) && !defined(USE_STM32303C_EVAL)
+   if (!STM_EVAL_PBGetState(Button_UP))    
+#else
+     if (STM_EVAL_PBGetState(Button_UP))    
+#endif
+     {
+       return JOY_UP;
+     }
+   /* "down" key is pressed */
+#if !defined(USE_STM32373C_EVAL) && !defined(USE_STM32303C_EVAL)
+   if (!STM_EVAL_PBGetState(Button_DOWN))    
+#else
+     if (STM_EVAL_PBGetState(Button_DOWN))
+#endif
+     {
+       return JOY_DOWN;
+     }
+   /* No key is pressed */
+     else
+     {
+       return 0;
+     } 
+}
+
+/*******************************************************************************
+* Function Name : Joystick_Send.
+* Description   : prepares buffer to be sent containing Joystick event infos.
+* Input         : Keys: keys received from terminal.
+* Output        : None.
+* Return value  : None.
+*******************************************************************************/
+void Joystick_Send(uint8_t Keys)
+{
+  uint8_t Mouse_Buffer[4] = {0, 0, 0, 0};
+  int8_t X = 0, Y = 0;
+  
+      switch (Keys)
+  {
+    case JOY_LEFT:
+      X -= CURSOR_STEP;
+      break;
+    case JOY_RIGHT:
+
+      X += CURSOR_STEP;
+      break;
+    case JOY_UP:
+      Y -= CURSOR_STEP;
+      break;
+    case JOY_DOWN:
+      Y += CURSOR_STEP;
+      break;
+    default:
+      return;
+  }
+  /* prepare buffer to send */
+  Mouse_Buffer[1] = X;
+  Mouse_Buffer[2] = Y;
+  
+  /* Reset the control token to inform upper layer that a transfer is ongoing */
+  PrevXferComplete = 0;
+  
+  /* Copy mouse position info in ENDP1 Tx Packet Memory Area*/
+  USB_SIL_Write(EP1_IN, Mouse_Buffer, 4);
+  
+  /* Enable endpoint for transmission */
+  SetEPTxValid(ENDP1);
+
+}
+
+/*******************************************************************************
+* Function Name  : Get_SerialNum.
+* Description    : Create the serial number string descriptor.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Get_SerialNum(void)
+{
+  uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+
+  Device_Serial0 = *(uint32_t*)ID1;
+  Device_Serial1 = *(uint32_t*)ID2;
+  Device_Serial2 = *(uint32_t*)ID3;
+  
+  Device_Serial0 += Device_Serial2;
+
+  if (Device_Serial0 != 0)
+  {
+    IntToUnicode (Device_Serial0, &Joystick_StringSerial[2] , 8);
+    IntToUnicode (Device_Serial1, &Joystick_StringSerial[18], 4);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : HexToChar.
+* Description    : Convert Hex 32Bits value into char.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
+{
+  uint8_t idx = 0;
+  
+  for( idx = 0 ; idx < len ; idx ++)
+  {
+    if( ((value >> 28)) < 0xA )
+    {
+      pbuf[ 2* idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2* idx] = (value >> 28) + 'A' - 10; 
+    }
+    
+    value = value << 4;
+    
+    pbuf[ 2* idx + 1] = 0;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/main.c
new file mode 100644
index 0000000..f444671
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/main.c
@@ -0,0 +1,95 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Joystick Mouse demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint8_t PrevXferComplete = 1;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : main.
+* Description    : main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+  
+  USB_Interrupts_Config();
+  
+  Set_USBClock();
+  
+  USB_Init();
+
+  while (1)
+  {
+    
+    if (bDeviceState == CONFIGURED)
+    {
+      if ((JoyState() != 0) && (PrevXferComplete))
+      {
+        Joystick_Send(JoyState());
+      }
+    }    
+  }
+}
+
+#ifdef  USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/stm32_it.c
new file mode 100644
index 0000000..d3a0c04
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/stm32_it.c
@@ -0,0 +1,260 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_it.h"
+#include "usb_istr.h"
+#include "usb_lib.h"
+#include "usb_pwr.h"
+#include "platform_config.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32 Peripherals Interrupt Handlers                            */
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined(STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USB_FS_WKUP_IRQHandler(void)
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+#endif
+/*******************************************************************************
+* Function Name  : EXTI_IRQHandler
+* Description    : This function handles External lines  interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void EXTI0_IRQHandler(void)
+#elif defined (STM32F37X)
+void EXTI2_TS_IRQHandler(void)
+#else
+void EXTI9_5_IRQHandler(void)
+#endif
+{
+  if (EXTI_GetITStatus(KEY_BUTTON_EXTI_LINE) != RESET)
+  {
+    /* Check if the remote wakeup feature is enabled (it could be disabled 
+        by the host through ClearFeature request) */
+    if (pInformation->Current_Feature & 0x20) 
+    {      
+      pInformation->Current_Feature &= ~0x20;  
+      /* Exit low power mode and re-configure clocks */
+      Resume(RESUME_INTERNAL);
+    }
+  
+    /* Clear the EXTI line pending bit */
+    EXTI_ClearITPendingBit(KEY_BUTTON_EXTI_LINE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USBWakeUp_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USBWakeUp_IRQHandler(void)
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f10x.c
new file mode 100644
index 0000000..3686a2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f10x.c
@@ -0,0 +1,917 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_XX */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+           
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_XX */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+        
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+       
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f30x.c
new file mode 100644
index 0000000..31faf5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F30x devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f30x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f30x.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F30x device                          
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F30x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f30x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+  * @{
+  */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F30x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 72000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_desc.c
new file mode 100644
index 0000000..690639f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_desc.c
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Joystick Mouse Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/* USB Standard Device Descriptor */
+const uint8_t Joystick_DeviceDescriptor[JOYSTICK_SIZ_DEVICE_DESC] =
+  {
+    0x12,                       /*bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
+    0x00,                       /*bcdUSB */
+    0x02,
+    0x00,                       /*bDeviceClass*/
+    0x00,                       /*bDeviceSubClass*/
+    0x00,                       /*bDeviceProtocol*/
+    0x40,                       /*bMaxPacketSize 64*/
+    0x83,                       /*idVendor (0x0483)*/
+    0x04,
+    0x10,                       /*idProduct = 0x5710*/
+    0x57,
+    0x00,                       /*bcdDevice rel. 2.00*/
+    0x02,
+    1,                          /*Index of string descriptor describing
+                                                  manufacturer */
+    2,                          /*Index of string descriptor describing
+                                                 product*/
+    3,                          /*Index of string descriptor describing the
+                                                 device serial number */
+    0x01                        /*bNumConfigurations*/
+  }
+  ; /* Joystick_DeviceDescriptor */
+
+
+/* USB Configuration Descriptor */
+/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
+const uint8_t Joystick_ConfigDescriptor[JOYSTICK_SIZ_CONFIG_DESC] =
+  {
+    0x09, /* bLength: Configuration Descriptor size */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
+    JOYSTICK_SIZ_CONFIG_DESC,
+    /* wTotalLength: Bytes returned */
+    0x00,
+    0x01,         /*bNumInterfaces: 1 interface*/
+    0x01,         /*bConfigurationValue: Configuration value*/
+    0x00,         /*iConfiguration: Index of string descriptor describing
+                                     the configuration*/
+    0xE0,         /*bmAttributes: Self powered */
+    0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/
+
+    /************** Descriptor of Joystick Mouse interface ****************/
+    /* 09 */
+    0x09,         /*bLength: Interface Descriptor size*/
+    USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
+    0x00,         /*bInterfaceNumber: Number of Interface*/
+    0x00,         /*bAlternateSetting: Alternate setting*/
+    0x01,         /*bNumEndpoints*/
+    0x03,         /*bInterfaceClass: HID*/
+    0x01,         /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
+    0x02,         /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
+    0,            /*iInterface: Index of string descriptor*/
+    /******************** Descriptor of Joystick Mouse HID ********************/
+    /* 18 */
+    0x09,         /*bLength: HID Descriptor size*/
+    HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
+    0x00,         /*bcdHID: HID Class Spec release number*/
+    0x01,
+    0x00,         /*bCountryCode: Hardware target country*/
+    0x01,         /*bNumDescriptors: Number of HID class descriptors to follow*/
+    0x22,         /*bDescriptorType*/
+    JOYSTICK_SIZ_REPORT_DESC,/*wItemLength: Total length of Report descriptor*/
+    0x00,
+    /******************** Descriptor of Joystick Mouse endpoint ********************/
+    /* 27 */
+    0x07,          /*bLength: Endpoint Descriptor size*/
+    USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
+
+    0x81,          /*bEndpointAddress: Endpoint Address (IN)*/
+    0x03,          /*bmAttributes: Interrupt endpoint*/
+    0x04,          /*wMaxPacketSize: 4 Byte max */
+    0x00,
+    0x20,          /*bInterval: Polling Interval (32 ms)*/
+    /* 34 */
+  }
+  ; /* MOUSE_ConfigDescriptor */
+const uint8_t Joystick_ReportDescriptor[JOYSTICK_SIZ_REPORT_DESC] =
+  {
+    0x05,          /*Usage Page(Generic Desktop)*/
+    0x01,
+    0x09,          /*Usage(Mouse)*/
+    0x02,
+    0xA1,          /*Collection(Logical)*/
+    0x01,
+    0x09,          /*Usage(Pointer)*/
+    0x01,
+    /* 8 */
+    0xA1,          /*Collection(Linked)*/
+    0x00,
+    0x05,          /*Usage Page(Buttons)*/
+    0x09,
+    0x19,          /*Usage Minimum(1)*/
+    0x01,
+    0x29,          /*Usage Maximum(3)*/
+    0x03,
+    /* 16 */
+    0x15,          /*Logical Minimum(0)*/
+    0x00,
+    0x25,          /*Logical Maximum(1)*/
+    0x01,
+    0x95,          /*Report Count(3)*/
+    0x03,
+    0x75,          /*Report Size(1)*/
+    0x01,
+    /* 24 */
+    0x81,          /*Input(Variable)*/
+    0x02,
+    0x95,          /*Report Count(1)*/
+    0x01,
+    0x75,          /*Report Size(5)*/
+    0x05,
+    0x81,          /*Input(Constant,Array)*/
+    0x01,
+    /* 32 */
+    0x05,          /*Usage Page(Generic Desktop)*/
+    0x01,
+    0x09,          /*Usage(X axis)*/
+    0x30,
+    0x09,          /*Usage(Y axis)*/
+    0x31,
+    0x09,          /*Usage(Wheel)*/
+    0x38,
+    /* 40 */
+    0x15,          /*Logical Minimum(-127)*/
+    0x81,
+    0x25,          /*Logical Maximum(127)*/
+    0x7F,
+    0x75,          /*Report Size(8)*/
+    0x08,
+    0x95,          /*Report Count(3)*/
+    0x03,
+    /* 48 */
+    0x81,          /*Input(Variable, Relative)*/
+    0x06,
+    0xC0,          /*End Collection*/
+    0x09,
+    0x3c,
+    0x05,
+    0xff,
+    0x09,
+    /* 56 */
+    0x01,
+    0x15,
+    0x00,
+    0x25,
+    0x01,
+    0x75,
+    0x01,
+    0x95,
+    /* 64 */
+    0x02,
+    0xb1,
+    0x22,
+    0x75,
+    0x06,
+    0x95,
+    0x01,
+    0xb1,
+    /* 72 */
+    0x01,
+    0xc0
+  }
+  ; /* Joystick_ReportDescriptor */
+
+/* USB String Descriptors (optional) */
+const uint8_t Joystick_StringLangID[JOYSTICK_SIZ_STRING_LANGID] =
+  {
+    JOYSTICK_SIZ_STRING_LANGID,
+    USB_STRING_DESCRIPTOR_TYPE,
+    0x09,
+    0x04
+  }
+  ; /* LangID = 0x0409: U.S. English */
+
+const uint8_t Joystick_StringVendor[JOYSTICK_SIZ_STRING_VENDOR] =
+  {
+    JOYSTICK_SIZ_STRING_VENDOR, /* Size of Vendor string */
+    USB_STRING_DESCRIPTOR_TYPE,  /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t Joystick_StringProduct[JOYSTICK_SIZ_STRING_PRODUCT] =
+  {
+    JOYSTICK_SIZ_STRING_PRODUCT,          /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'J', 0,
+    'o', 0, 'y', 0, 's', 0, 't', 0, 'i', 0, 'c', 0, 'k', 0
+  };
+uint8_t Joystick_StringSerial[JOYSTICK_SIZ_STRING_SERIAL] =
+  {
+    JOYSTICK_SIZ_STRING_SERIAL,           /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_istr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_istr.c
new file mode 100644
index 0000000..b711fbf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_istr.c
@@ -0,0 +1,229 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   ISTR events interrupt service routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t wIstr;  /* ISTR register last read value */
+__IO uint8_t bIntPackSOF = 0;  /* SOFs received between 2 consecutive packets */
+__IO uint32_t esof_counter =0; /* expected SOF counter */
+__IO uint32_t wCNTR=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* function pointers to non-control endpoints service routines */
+void (*pEpInt_IN[7])(void) =
+  {
+    EP1_IN_Callback,
+    EP2_IN_Callback,
+    EP3_IN_Callback,
+    EP4_IN_Callback,
+    EP5_IN_Callback,
+    EP6_IN_Callback,
+    EP7_IN_Callback,
+  };
+
+void (*pEpInt_OUT[7])(void) =
+  {
+    EP1_OUT_Callback,
+    EP2_OUT_Callback,
+    EP3_OUT_Callback,
+    EP4_OUT_Callback,
+    EP5_OUT_Callback,
+    EP6_OUT_Callback,
+    EP7_OUT_Callback,
+  };
+
+/*******************************************************************************
+* Function Name  : USB_Istr
+* Description    : ISTR events interrupt service routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Istr(void)
+{
+    uint32_t i=0;
+ __IO uint32_t EP[8];
+  
+  wIstr = _GetISTR();
+#if (IMR_MSK & ISTR_CTR)
+  if (wIstr & ISTR_CTR & wInterrupt_Mask)
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    CTR_LP();
+#ifdef CTR_CALLBACK
+    CTR_Callback();
+#endif
+  }
+#endif  
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_RESET)
+  if (wIstr & ISTR_RESET & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_RESET);
+    Device_Property.Reset();
+#ifdef RESET_CALLBACK
+    RESET_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_DOVR)
+  if (wIstr & ISTR_DOVR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_DOVR);
+#ifdef DOVR_CALLBACK
+    DOVR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ERR)
+  if (wIstr & ISTR_ERR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ERR);
+#ifdef ERR_CALLBACK
+    ERR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_WKUP)
+  if (wIstr & ISTR_WKUP & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_WKUP);
+    Resume(RESUME_EXTERNAL);
+#ifdef WKUP_CALLBACK
+    WKUP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SUSP)
+  if (wIstr & ISTR_SUSP & wInterrupt_Mask)
+  {
+
+    /* check if SUSPEND is possible */
+    if (fSuspendEnabled)
+    {
+      Suspend();
+    }
+    else
+    {
+      /* if not possible then resume after xx ms */
+      Resume(RESUME_LATER);
+    }
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    _SetISTR((uint16_t)CLR_SUSP);
+#ifdef SUSP_CALLBACK
+    SUSP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SOF)
+  if (wIstr & ISTR_SOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_SOF);
+    bIntPackSOF++;
+
+#ifdef SOF_CALLBACK
+    SOF_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ESOF)
+  if (wIstr & ISTR_ESOF & wInterrupt_Mask)
+  {
+    /* clear ESOF flag in ISTR */
+    _SetISTR((uint16_t)CLR_ESOF);
+    
+    if ((_GetFNR()&FNR_RXDP)!=0)
+    {
+      /* increment ESOF counter */
+      esof_counter ++;
+      
+      /* test if we enter in ESOF more than 3 times with FSUSP =0 and RXDP =1=>> possible missing SUSP flag*/
+      if ((esof_counter >3)&&((_GetCNTR()&CNTR_FSUSP)==0))
+      {           
+        /* this a sequence to apply a force RESET*/
+      
+        /*Store CNTR value */
+        wCNTR = _GetCNTR(); 
+      
+        /*Store endpoints registers status */
+        for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+      
+        /*apply FRES */
+        wCNTR|=CNTR_FRES;
+        _SetCNTR(wCNTR);
+ 
+        /*clear FRES*/
+        wCNTR&=~CNTR_FRES;
+        _SetCNTR(wCNTR);
+      
+        /*poll for RESET flag in ISTR*/
+        while((_GetISTR()&ISTR_RESET) == 0);
+  
+        /* clear RESET flag in ISTR */
+        _SetISTR((uint16_t)CLR_RESET);
+   
+       /*restore Enpoints*/
+        for (i=0;i<8;i++)
+        _SetENDPOINT(i, EP[i]);
+      
+        esof_counter = 0;
+      }
+    }
+    else
+    {
+        esof_counter = 0;
+    }
+    
+    /* resume handling timing is made with ESOFs */
+    Resume(RESUME_ESOF); /* request without change of the machine state */
+#ifdef ESOF_CALLBACK
+    ESOF_Callback();
+#endif
+    
+  }
+#endif
+} /* USB_Istr */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_prop.c
new file mode 100644
index 0000000..a1d60cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/JoyStickMouse/src/usb_prop.c
@@ -0,0 +1,414 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Joystick Mouse Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t ProtocolValue;
+
+/* -------------------------------------------------------------------------- */
+/*  Structures initializations */
+/* -------------------------------------------------------------------------- */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    Joystick_init,
+    Joystick_Reset,
+    Joystick_Status_In,
+    Joystick_Status_Out,
+    Joystick_Data_Setup,
+    Joystick_NoData_Setup,
+    Joystick_Get_Interface_Setting,
+    Joystick_GetDeviceDescriptor,
+    Joystick_GetConfigDescriptor,
+    Joystick_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    Joystick_GetConfiguration,
+    Joystick_SetConfiguration,
+    Joystick_GetInterface,
+    Joystick_SetInterface,
+    Joystick_GetStatus,
+    Joystick_ClearFeature,
+    Joystick_SetEndPointFeature,
+    Joystick_SetDeviceFeature,
+    Joystick_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)Joystick_DeviceDescriptor,
+    JOYSTICK_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)Joystick_ConfigDescriptor,
+    JOYSTICK_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR Joystick_Report_Descriptor =
+  {
+    (uint8_t *)Joystick_ReportDescriptor,
+    JOYSTICK_SIZ_REPORT_DESC
+  };
+
+ONE_DESCRIPTOR Mouse_Hid_Descriptor =
+  {
+    (uint8_t*)Joystick_ConfigDescriptor + JOYSTICK_OFF_HID_DESC,
+    JOYSTICK_SIZ_HID_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+  {
+    {(uint8_t*)Joystick_StringLangID, JOYSTICK_SIZ_STRING_LANGID},
+    {(uint8_t*)Joystick_StringVendor, JOYSTICK_SIZ_STRING_VENDOR},
+    {(uint8_t*)Joystick_StringProduct, JOYSTICK_SIZ_STRING_PRODUCT},
+    {(uint8_t*)Joystick_StringSerial, JOYSTICK_SIZ_STRING_SERIAL}
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Joystick_init.
+* Description    : Joystick Mouse init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_init(void)
+{
+
+  /* Update the serial number string descriptor with the data from the unique
+  ID*/
+  Get_SerialNum();
+
+  pInformation->Current_Configuration = 0;
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_Reset.
+* Description    : Joystick Mouse reset routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_Reset(void)
+{
+  /* Set Joystick_DEVICE as not configured */
+  pInformation->Current_Configuration = 0;
+  pInformation->Current_Interface = 0;/*the default Interface*/
+
+  /* Current Feature initialization */
+  pInformation->Current_Feature = Joystick_ConfigDescriptor[7];
+  SetBTABLE(BTABLE_ADDRESS);
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_INTERRUPT);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxCount(ENDP1, 4);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+  bDeviceState = ATTACHED;
+}
+/*******************************************************************************
+* Function Name  : Joystick_SetConfiguration.
+* Description    : Update the device state to configured.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_SetConfiguration(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+}
+/*******************************************************************************
+* Function Name  : Joystick_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+/*******************************************************************************
+* Function Name  : Joystick_Status_In.
+* Description    : Joystick status IN routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_Status_In(void)
+{}
+
+/*******************************************************************************
+* Function Name  : Joystick_Status_Out
+* Description    : Joystick status OUT routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Joystick_Status_Out (void)
+{}
+
+/*******************************************************************************
+* Function Name  : Joystick_Data_Setup
+* Description    : Handle the data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Joystick_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t *(*CopyRoutine)(uint16_t);
+
+  CopyRoutine = NULL;
+  if ((RequestNo == GET_DESCRIPTOR)
+      && (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+      && (pInformation->USBwIndex0 == 0))
+  {
+    if (pInformation->USBwValue1 == REPORT_DESCRIPTOR)
+    {
+      CopyRoutine = Joystick_GetReportDescriptor;
+    }
+    else if (pInformation->USBwValue1 == HID_DESCRIPTOR_TYPE)
+    {
+      CopyRoutine = Joystick_GetHIDDescriptor;
+    }
+
+  } /* End of GET_DESCRIPTOR */
+
+  /*** GET_PROTOCOL ***/
+  else if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+           && RequestNo == GET_PROTOCOL)
+  {
+    CopyRoutine = Joystick_GetProtocolValue;
+  }
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_NoData_Setup
+* Description    : handle the no data class specific requests
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Joystick_NoData_Setup(uint8_t RequestNo)
+{
+  if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+      && (RequestNo == SET_PROTOCOL))
+  {
+    return Joystick_SetProtocol();
+  }
+
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *Joystick_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetConfigDescriptor.
+* Description    : Gets the configuration descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *Joystick_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetStringDescriptor
+* Description    : Gets the string descriptors according to the needed index
+* Input          : Length
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *Joystick_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetReportDescriptor.
+* Description    : Gets the HID report descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *Joystick_GetReportDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Joystick_Report_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetHIDDescriptor.
+* Description    : Gets the HID descriptor.
+* Input          : Length
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *Joystick_GetHIDDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Mouse_Hid_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_Get_Interface_Setting.
+* Description    : tests the interface and the alternate setting according to the
+*                  supported one.
+* Input          : - Interface : interface number.
+*                  - AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : USB_SUCCESS or USB_UNSUPPORT.
+*******************************************************************************/
+RESULT Joystick_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_SetProtocol
+* Description    : Joystick Set Protocol request routine.
+* Input          : None.
+* Output         : None.
+* Return         : USB SUCCESS.
+*******************************************************************************/
+RESULT Joystick_SetProtocol(void)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  ProtocolValue = wValue0;
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Joystick_GetProtocolValue
+* Description    : get the protocol value
+* Input          : Length.
+* Output         : None.
+* Return         : address of the protocol value.
+*******************************************************************************/
+uint8_t *Joystick_GetProtocolValue(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = 1;
+    return NULL;
+  }
+  else
+  {
+    return (uint8_t *)(&ProtocolValue);
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewd
new file mode 100644
index 0000000..26ba5a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
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+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
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+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
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+          <state></state>
+        </option>
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+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
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+          <state>4.41A</state>
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+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
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+        </option>
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+          <state>0</state>
+        </option>
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+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
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+          <state>1</state>
+        </option>
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+          <state>1</state>
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+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
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+          <state>1</state>
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+        <option>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
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+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
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+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
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+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
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+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
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+      <archiveVersion>2</archiveVersion>
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+        <version>0</version>
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+        <debug>1</debug>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
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+          <state>1</state>
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+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
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+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
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+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
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+          <name>IjetPowerRadio</name>
+          <state>1</state>
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+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewp
new file mode 100644
index 0000000..0c8bd18
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.ewp
@@ -0,0 +1,6934 @@
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <state>0</state>
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+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
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+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+          <state>1</state>
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+          <version>0</version>
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+        <version>0</version>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+      <name>ARM</name>
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+          <name>ListPath</name>
+          <state>STM3210B-EVAL\List</state>
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+        <option>
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+          <state>STM32F103xB	ST STM32F103xB</state>
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+          <state>1</state>
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+          <name>OGUseCmsisDspLib</name>
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+          <state></state>
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+        <option>
+          <name>CCDiagWarning</name>
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+          <state>1111111</state>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
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+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</state>
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+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+          <state>1</state>
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+          <state></state>
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+          <state>###Unitialized###</state>
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+          <state>STM32F103xG	ST STM32F103xG</state>
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+          <state></state>
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+          <state></state>
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+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</state>
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+          <state>.text</state>
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+          <state></state>
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+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
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+          <state>1</state>
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+      <archiveVersion>3</archiveVersion>
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+        <extensions></extensions>
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+      <archiveVersion>1</archiveVersion>
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+        <prebuild></prebuild>
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+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
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+          <state>0</state>
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+          <state>0</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
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+          <state>0</state>
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+          <state>1</state>
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+          <state></state>
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+          <state></state>
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+        <version>0</version>
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+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
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+          <name>Includes</name>
+          <state>0</state>
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+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32L152-EVAL_MassStorage.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>MassStorage.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
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+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM32L152D-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM32L152D-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM32L152D-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
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+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
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+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
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+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xD	ST STM32L152xD</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
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+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
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+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
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+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>GeneralMisraVer</name>
+          <state>0</state>
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+        <option>
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+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32L1XX_HD</state>
+          <state>USE_STM32L152D_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
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+          <state>1</state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <group>
+    <name>Doc</name>
+    <file>
+      <name>$PROJ_DIR$\..\readme.txt</name>
+    </file>
+  </group>
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+    <name>STM32F10x</name>
+    <excluded>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_hd.s</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_xl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f10x.c</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM3210B_EVAL</name>
+      <excluded>
+        <configuration>STM3210E-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_spi_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM3210E_EVAL</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval_sdio_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F10x_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F30x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\iar\startup_stm32f30x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f30x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32303C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval_spi_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F30x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F37x</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\iar\startup_stm32f37x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f37x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32373C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval_spi_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F37x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_mdp.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32l1xx.c</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval_spi_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval_sdio_sd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_sdio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\fsmc_nand.c</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\mass_mal.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\memory.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\nand_if.c</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM32L152-EVAL</configuration>
+        <configuration>STM32L152D-EVAL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\scsi_data.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_bot.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_endp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_scsi.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.eww
new file mode 100644
index 0000000..acdd01d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/MassStorageSimpleBuffer.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\MassStorageSimpleBuffer.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-MassStorage</name>
+      <member>
+        <project>MassStorageSimpleBuffer</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>MassStorageSimpleBuffer</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>MassStorageSimpleBuffer</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>MassStorageSimpleBuffer</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>MassStorageSimpleBuffer</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f37x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f37x_flash.icf
new file mode 100644
index 0000000..a743cb4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32f37x_flash.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..8b7d80d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvopt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvopt
new file mode 100644
index 0000000..0c4ec6b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvopt
@@ -0,0 +1,2519 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL</Key>
+          <Name>-S</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0579U9E -O2254 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L151xx_152xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O14 -O2062 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152D-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L162xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0579U9E -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32373C_EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32373C_EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvproj
new file mode 100644
index 0000000..56640a5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/MDK-ARM/MassStorageSimpleBuffer.uvproj
@@ -0,0 +1,13488 @@
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+            <Driver>BIN\UL2CM3.DLL</Driver>
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+          <Flash4></Flash4>
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+            <LinkerInputFile></LinkerInputFile>
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+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>STM32L152D-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L152ZD</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000BFFF) IROM(0x8000000-0x805FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32L1xx\startup_stm32l1xx_hd.s" ("STM32L1xx High density Startup Code")</StartupFile>
+          <FlashDriverDll>ULP2CM3(-O207 -S8 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_384 -FS08000000 -FL060000)</FlashDriverDll>
+          <DeviceId>6190</DeviceId>
+          <RegisterFile>stm32l1xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\ST\STM32L15\STM32L152xD.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32L1xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32L1xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\STM32L152D-EVAL\</OutputDirectory>
+          <OutputName>STM32L152D-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
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+            <UserProg1Name></UserProg1Name>
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+          <SVCSIdString></SVCSIdString>
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+          <RVCTZI>0</RVCTZI>
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+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
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+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
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+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
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+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
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+          <TargetDlls>
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+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
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+        <Utilities>
+          <Flash1>
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+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
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+            <RvctDeviceName></RvctDeviceName>
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+            <uocRom>0</uocRom>
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+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
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+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER, STM32L1XX_HD, USE_STM32L152D_EVAL</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL</IncludePath>
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+              <Define></Define>
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+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
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+          <GroupName>User</GroupName>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/RIDE/MassStorageSimpleBuffer.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/RIDE/MassStorageSimpleBuffer.rprj
new file mode 100644
index 0000000..1699e60
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/RIDE/MassStorageSimpleBuffer.rprj
@@ -0,0 +1,4 @@
+
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+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..3422012
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.cproject
@@ -0,0 +1,136 @@
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..bf22095
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
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+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
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+		</link>
+		<link>
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+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
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+		</link>
+		<link>
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+		</link>
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+		</link>
+		<link>
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+		</link>
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+		</link>
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+		</link>
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+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
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+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
new file mode 100644
index 0000000..930adb1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210B-EVAL/TASKING/STM32F10x_md.lsl
@@ -0,0 +1,148 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 20k;
+    map ( size = 20k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                      /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..1292232
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="false" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.project
new file mode 100644
index 0000000..94fa110
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/.project
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..1c5d0c1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..e376c18
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL_XL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
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+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
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+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
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+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
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+									<listOptionValue builtIn="false" value="STM32F10X_XL"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
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+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file (.lsl):" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_XL.lsl" valueType="string"/>
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+			</storageModule>
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+			<storageModule moduleId="com.tasking.toolInfo">
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+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
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+				<extensions>
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+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
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+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
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+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..69e7ea8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,252 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
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+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
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+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
new file mode 100644
index 0000000..252b6cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/STM3210E-EVAL_XL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL_XL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
new file mode 100644
index 0000000..a944802
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 0x100000;
+    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 96k;
+    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..2750b9d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..8353c3e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,232 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32303C_EVAL/stm32303c_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30x/STM32F30x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
new file mode 100644
index 0000000..80853f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32303C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32303C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
new file mode 100644
index 0000000..3ccf590
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f30x.lsl
+//
+//  Version     :  @(#)stm32f30x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F30x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F30x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       6k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+
+memory STM32F30x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE - 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM8k
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    priority = 1;
+    map ( size = 8k, dest_offset=0x10000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2 interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2 global interrupts
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB Device High Priority or CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );      // USB Device Low Priority or CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break irq and TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );        // TIM1 Update irq and TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation irqs and TIM17 global irq
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup interrupt
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break interrupt
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update interrupt
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 trigger and Comm. interrupt
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare interrupt
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4 global interrupt
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "ADC4_IRQHandler" );                 // ADC4 global interrupt
+                        vector ( id = 80, optional, fill = "COMP1_2_3_IRQHandler" );            // COMP1, COMP2 and COMP3 global interrupt
+                        vector ( id = 81, optional, fill = "COMP4_5_6_IRQHandler" );            // COMP5, COMP6 and COMP4 global interrupt
+                        vector ( id = 82, optional, fill = "COMP7_IRQHandler" );                // COMP7 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt  remap
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt  remap
+                        vector ( id = 92, optional, fill = "USBWakeUp_RMP_IRQHandler" );        // USB Wakeup Interrupt remap
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..44229ae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.cproject
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_MD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_md.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..f7f7450
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,237 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>stm32l152_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
new file mode 100644
index 0000000..d494039
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
new file mode 100644
index 0000000..909c5b0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
@@ -0,0 +1,151 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx_cmsis.lsl
+//
+//  Version     :  @(#)stm32l1xx_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32l1xx.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 84
+
+
+#ifndef __STACK
+#  define __STACK                       2k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        1k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32L1xx, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32l1xflash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32l1xram
+{
+    mau = 8;
+    type = ram;
+    size = 16k;
+    map ( size = 16k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandle" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..677ce43
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.cproject
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32L152D-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32l152zd" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="537"/>
+									<listOptionValue builtIn="false" value="529"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32l1xx_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..d2eee70
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,242 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
new file mode 100644
index 0000000..26462e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152D-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152D-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..77979b6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..2ef1e92
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:57:46 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
new file mode 100644
index 0000000..796c55b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210B-EVAL/STM3210B-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Mass_Storage\TrueSTUDIO\STM3210B-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM3210B-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.project
new file mode 100644
index 0000000..43c9344
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.project
@@ -0,0 +1,290 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..5c1a494
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:58:30 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..bbcbc81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,286 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval_sdio_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_fsmc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/fsmc_nand.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/fsmc_nand.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/nand_if.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/nand_if.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..20424b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Mass_Storage\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..6c1c6dc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,340 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..11c9ee7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
new file mode 100644
index 0000000..c0e7344
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32303C-EVAL/STM32F303VC_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F303VC Device with
+**                256KByte FLASH, 40KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000a000;    /* end of 40K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x200; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 40K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+  CCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+  
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section 
+  * 
+  * IMPORTANT NOTE! 
+  * If initialized variables will be placed in this section, 
+  * the startup code needs to be modified to copy the init-values.  
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+    
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.cproject
new file mode 100644
index 0000000..f6f0f6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.cproject
@@ -0,0 +1,352 @@
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+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..b4085f5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..734d809
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..35c7d30
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..3e3424c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,271 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_STM32L1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/system_STM32L1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval_spi_sd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/mass_mal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/mass_mal.c</locationURI>
+		</link>
+		<link>
+			<name>User/memory.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/memory.c</locationURI>
+		</link>
+		<link>
+			<name>User/scsi_data.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/scsi_data.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_bot.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_bot.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_scsi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Mass_Storage/src/usb_scsi.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..0ac9ecd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 15:59:01 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..5cc41ea
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Mass_Storage\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..3726f75
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32L152D-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32L1xx/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32L1xx_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32L152D_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM32L152D_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.2070040810" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1801492075" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.175735774" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1423180437" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1792104502" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.784303318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM32L152D-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.315707442" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.1911990920" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32L1xx_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.313911374" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.887021457" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1958027324" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.1399417399" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.157276368" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.2035464181" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.2081839827" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.309940778" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32L152ZD" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1010173629" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32L152D-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
new file mode 100644
index 0000000..b37a110
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Mass_Storage\TrueSTUDIO\STM32L152D-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152D-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/fsmc_nand.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/fsmc_nand.h
new file mode 100644
index 0000000..9bdee98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/fsmc_nand.h
@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nand.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for fsmc_nand.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FSMC_NAND_H
+#define __FSMC_NAND_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint8_t Maker_ID;
+  uint8_t Device_ID;
+  uint8_t Third_ID;
+  uint8_t Fourth_ID;
+}NAND_IDTypeDef;
+
+typedef struct 
+{
+  uint16_t Zone;
+  uint16_t Block;
+  uint16_t Page;
+} NAND_ADDRESS;
+
+/* Exported constants --------------------------------------------------------*/
+/* NAND Area definition  for STM3210E-EVAL Board RevD */
+#define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE  high */
+#define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
+
+#define DATA_AREA                  ((uint32_t)0x00000000) 
+
+/* FSMC NAND memory command */
+#define	NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define	NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+	
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
+
+#define NAND_CMD_READID            ((uint8_t)0x90)	
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/* FSMC NAND memory parameters */
+#define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
+#define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
+#define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
+#define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
+#define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
+
+/* FSMC NAND memory address computation */
+#define ADDR_1st_CYCLE(ADDR)       (uint8_t)((ADDR)& 0xFF)               /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF00) >> 8)      /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void FSMC_NAND_Init(void);
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID);
+uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite);
+uint32_t FSMC_NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead);
+uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
+uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
+uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address);
+uint32_t FSMC_NAND_Reset(void);
+uint32_t FSMC_NAND_GetStatus(void);
+uint32_t FSMC_NAND_ReadStatus(void);
+uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address);
+
+#endif /* __FSMC_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/hw_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/hw_config.h
new file mode 100644
index 0000000..16882c5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/hw_config.h
@@ -0,0 +1,64 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define BULK_MAX_PACKET_SIZE  0x00000040
+
+/* Exported functions ------------------------------------------------------- */
+void Set_System(void);
+void Set_USBClock(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void Led_Config(void);
+void Led_RW_ON(void);
+void Led_RW_OFF(void);
+void USB_Configured_LED(void);
+void USB_NotConfigured_LED(void);
+void USB_Cable_Config (FunctionalState NewState);
+void Get_SerialNum(void);
+void MAL_Config(void);
+#if !defined (USE_STM32L152_EVAL) 
+void USB_Disconnect_Config(void);
+#endif /* (USE_STM32L152_EVAL) */
+/* External variables --------------------------------------------------------*/
+
+#endif  /*__HW_CONFIG_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/mass_mal.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/mass_mal.h
new file mode 100644
index 0000000..4374449
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/mass_mal.h
@@ -0,0 +1,49 @@
+/**
+  ******************************************************************************
+  * @file    mass_mal.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Header for mass_mal.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MASS_MAL_H
+#define __MASS_MAL_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define MAL_OK   0
+#define MAL_FAIL 1
+#define MAX_LUN  1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+uint16_t MAL_Init (uint8_t lun);
+uint16_t MAL_GetStatus (uint8_t lun);
+uint16_t MAL_Read(uint8_t lun, uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length);
+uint16_t MAL_Write(uint8_t lun, uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length);
+#endif /* __MASS_MAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/memory.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/memory.h
new file mode 100644
index 0000000..3cc19a7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/memory.h
@@ -0,0 +1,46 @@
+/**
+  ******************************************************************************
+  * @file    memory.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Memory management layer
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __memory_H
+#define __memory_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+#define TXFR_IDLE     0
+#define TXFR_ONGOING  1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Write_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length);
+void Read_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length);
+#endif /* __memory_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/platform_config.h
new file mode 100644
index 0000000..ac73393
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/platform_config.h
@@ -0,0 +1,182 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+  #include "stm32l152_eval_spi_sd.h"
+ 
+#elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval_sdio_sd.h"
+  #include "stm32l152d_eval.h"
+
+#else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+  #include "stm3210b_eval_spi_sd.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval_sdio_sd.h"
+  #include "stm3210e_eval.h"
+  #include "fsmc_nand.h"
+  #include "nand_if.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+ #include "stm32373c_eval_spi_sd.h"
+
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+ #include "stm32303c_eval_spi_sd.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)  &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL) && !defined (USE_STM32373C_EVAL) && !defined (USE_STM32303C_EVAL)
+//#define USE_STM3210B_EVAL
+//#define USE_STM3210E_EVAL
+//#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define (USE_STM32373C_EVAL)
+#define (USE_STM32303C_EVAL)
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+#define RCC_AHBPeriph_ALLGPIO                 (RCC_AHBPeriph_GPIOA \
+                                              | RCC_AHBPeriph_GPIOB \
+                                              | RCC_AHBPeriph_GPIOC \
+                                              | RCC_AHBPeriph_GPIOD \
+                                              | RCC_AHBPeriph_GPIOE \
+                                              | RCC_AHBPeriph_GPIOF )    
+     
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+
+  #define USB_DISCONNECT                    GPIOD  
+  #define USB_DISCONNECT_PIN                GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT    RCC_APB2Periph_GPIOD
+
+#elif defined (USE_STM3210E_EVAL)
+
+  #define USB_DISCONNECT                    GPIOB  
+  #define USB_DISCONNECT_PIN                GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT    RCC_APB2Periph_GPIOB
+
+#elif defined (USE_STM32L152_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+#elif defined (USE_STM32L152D_EVAL)
+
+  #define USB_DISCONNECT                    GPIOE 
+  #define USB_DISCONNECT_PIN                GPIO_Pin_6
+  #define RCC_AHBPeriph_GPIO_DISCONNECT    RCC_AHBPeriph_GPIOE
+
+#elif defined (USE_STM32373C_EVAL)
+
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+ 
+#elif defined (USE_STM32303C_EVAL)
+
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+#endif /* USE_STM3210B_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32_it.h
index 8ff798e..fb3e1c7 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/stm32f10x_it.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32_it.h
@@ -1,30 +1,37 @@
 /**
   ******************************************************************************
-  * @file    SDIO/uSDCard/stm32f10x_it.h 
+  * @file    stm32_it.h
   * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
+  * @version V4.0.0
+  * @date    21-January-2013
   * @brief   This file contains the headers of the interrupt handlers.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
   ******************************************************************************
-  */ 
+  */
+
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "platform_config.h"
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
@@ -40,8 +47,15 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+void USB_HP_CAN1_TX_IRQHandler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
 void SDIO_IRQHandler(void);
+void SD_SDIO_DMA_IRQHANDLER(void);
+#endif /* STM32F10X_HD | STM32F10X_XL */
+					 
+#endif /* __STM32_IT_H */
 
-#endif /* __STM32F10x_IT_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_desc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_desc.h
new file mode 100644
index 0000000..47d20f6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_desc.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptor Header for Mass Storage Device
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define MASS_SIZ_DEVICE_DESC              18
+#define MASS_SIZ_CONFIG_DESC              32
+
+#define MASS_SIZ_STRING_LANGID            4
+#define MASS_SIZ_STRING_VENDOR            38
+#define MASS_SIZ_STRING_PRODUCT           38
+#define MASS_SIZ_STRING_SERIAL            26
+#define MASS_SIZ_STRING_INTERFACE         16
+
+/* Exported functions ------------------------------------------------------- */
+extern const uint8_t MASS_DeviceDescriptor[MASS_SIZ_DEVICE_DESC];
+extern const uint8_t MASS_ConfigDescriptor[MASS_SIZ_CONFIG_DESC];
+
+extern const uint8_t MASS_StringLangID[MASS_SIZ_STRING_LANGID];
+extern const uint8_t MASS_StringVendor[MASS_SIZ_STRING_VENDOR];
+extern const uint8_t MASS_StringProduct[MASS_SIZ_STRING_PRODUCT];
+extern uint8_t MASS_StringSerial[MASS_SIZ_STRING_SERIAL];
+extern const uint8_t MASS_StringInterface[MASS_SIZ_STRING_INTERFACE];
+
+#endif /* __USB_DESC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_prop.h
new file mode 100644
index 0000000..ba3e0ab
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_prop.h
@@ -0,0 +1,72 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Mass Storage Demo (Endpoint 0)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PROP_H
+#define __USB_PROP_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+#define Mass_Storage_GetConfiguration          NOP_Process
+/* #define Mass_Storage_SetConfiguration          NOP_Process*/
+#define Mass_Storage_GetInterface              NOP_Process
+#define Mass_Storage_SetInterface              NOP_Process
+#define Mass_Storage_GetStatus                 NOP_Process
+/* #define Mass_Storage_ClearFeature              NOP_Process*/
+#define Mass_Storage_SetEndPointFeature        NOP_Process
+#define Mass_Storage_SetDeviceFeature          NOP_Process
+/*#define Mass_Storage_SetDeviceAddress          NOP_Process*/
+
+/* MASS Storage Requests*/
+#define GET_MAX_LUN                0xFE
+#define MASS_STORAGE_RESET         0xFF
+#define LUN_DATA_LENGTH            1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void MASS_init(void);
+void MASS_Reset(void);
+void Mass_Storage_SetConfiguration(void);
+void Mass_Storage_ClearFeature(void);
+void Mass_Storage_SetDeviceAddress (void);
+void MASS_Status_In (void);
+void MASS_Status_Out (void);
+RESULT MASS_Data_Setup(uint8_t);
+RESULT MASS_NoData_Setup(uint8_t);
+RESULT MASS_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *MASS_GetDeviceDescriptor(uint16_t );
+uint8_t *MASS_GetConfigDescriptor(uint16_t);
+uint8_t *MASS_GetStringDescriptor(uint16_t);
+uint8_t *Get_Max_Lun(uint16_t Length);
+
+
+#endif /* __USB_PROP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_pwr.h
new file mode 100644
index 0000000..149dc04
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_pwr.h
@@ -0,0 +1,73 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+/* Includes ------------------------------------------------------------------*/
+#include "usb_core.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+
+/* External variables --------------------------------------------------------*/
+extern  __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_scsi.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_scsi.h
new file mode 100644
index 0000000..5c4d46f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/inc/usb_scsi.h
@@ -0,0 +1,154 @@
+/**
+  ******************************************************************************
+  * @file    usb_scsi.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to the SCSI commands
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_SCSI_H
+#define __USB_SCSI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* SCSI Commands */
+#define SCSI_FORMAT_UNIT                            0x04
+#define SCSI_INQUIRY                                0x12
+#define SCSI_MODE_SELECT6                           0x15
+#define SCSI_MODE_SELECT10                          0x55
+#define SCSI_MODE_SENSE6                            0x1A
+#define SCSI_MODE_SENSE10                           0x5A
+#define SCSI_ALLOW_MEDIUM_REMOVAL                   0x1E
+#define SCSI_READ6                                  0x08
+#define SCSI_READ10                                 0x28
+#define SCSI_READ12                                 0xA8
+#define SCSI_READ16                                 0x88
+
+#define SCSI_READ_CAPACITY10                        0x25
+#define SCSI_READ_CAPACITY16                        0x9E
+
+#define SCSI_REQUEST_SENSE                          0x03
+#define SCSI_START_STOP_UNIT                        0x1B
+#define SCSI_TEST_UNIT_READY                        0x00
+#define SCSI_WRITE6                                 0x0A
+#define SCSI_WRITE10                                0x2A
+#define SCSI_WRITE12                                0xAA
+#define SCSI_WRITE16                                0x8A
+
+#define SCSI_VERIFY10                               0x2F
+#define SCSI_VERIFY12                               0xAF
+#define SCSI_VERIFY16                               0x8F
+
+#define SCSI_SEND_DIAGNOSTIC                        0x1D
+#define SCSI_READ_FORMAT_CAPACITIES                 0x23
+
+#define NO_SENSE		                    0
+#define RECOVERED_ERROR		                    1
+#define NOT_READY		                    2
+#define MEDIUM_ERROR		                    3
+#define HARDWARE_ERROR		                    4
+#define ILLEGAL_REQUEST		                    5
+#define UNIT_ATTENTION		                    6
+#define DATA_PROTECT		                    7
+#define BLANK_CHECK		                    8
+#define VENDOR_SPECIFIC		                    9
+#define COPY_ABORTED		                    10
+#define ABORTED_COMMAND		                    11
+#define VOLUME_OVERFLOW		                    13
+#define MISCOMPARE		                    14
+
+
+#define INVALID_COMMAND                             0x20
+#define INVALID_FIELED_IN_COMMAND                   0x24
+#define PARAMETER_LIST_LENGTH_ERROR                 0x1A
+#define INVALID_FIELD_IN_PARAMETER_LIST             0x26
+#define ADDRESS_OUT_OF_RANGE                        0x21
+#define MEDIUM_NOT_PRESENT 			    0x3A
+#define MEDIUM_HAVE_CHANGED			    0x28
+
+#define READ_FORMAT_CAPACITY_DATA_LEN               0x0C
+#define READ_CAPACITY10_DATA_LEN                    0x08
+#define MODE_SENSE10_DATA_LEN                       0x08
+#define MODE_SENSE6_DATA_LEN                        0x04
+#define REQUEST_SENSE_DATA_LEN                      0x12
+#define STANDARD_INQUIRY_DATA_LEN                   0x24
+#define BLKVFY                                      0x04
+
+extern  uint8_t Page00_Inquiry_Data[];
+extern  uint8_t Standard_Inquiry_Data[];
+extern  uint8_t Standard_Inquiry_Data2[];
+extern  uint8_t Mode_Sense6_data[];
+extern  uint8_t Mode_Sense10_data[];
+extern  uint8_t Scsi_Sense_Data[];
+extern  uint8_t ReadCapacity10_Data[];
+extern  uint8_t ReadFormatCapacity_Data [];
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void SCSI_Inquiry_Cmd(uint8_t lun);
+void SCSI_ReadFormatCapacity_Cmd(uint8_t lun);
+void SCSI_ReadCapacity10_Cmd(uint8_t lun);
+void SCSI_RequestSense_Cmd (uint8_t lun);
+void SCSI_Start_Stop_Unit_Cmd(uint8_t lun);
+void SCSI_ModeSense6_Cmd (uint8_t lun);
+void SCSI_ModeSense10_Cmd (uint8_t lun);
+void SCSI_Write10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr);
+void SCSI_Read10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr);
+void SCSI_Verify10_Cmd(uint8_t lun);
+
+void SCSI_Invalid_Cmd(uint8_t lun);
+void SCSI_Valid_Cmd(uint8_t lun);
+bool SCSI_Address_Management(uint8_t lun , uint8_t Cmd , uint32_t LBA , uint32_t BlockNbr);
+
+void Set_Scsi_Sense_Data(uint8_t lun , uint8_t Sens_Key, uint8_t Asc);
+void SCSI_TestUnitReady_Cmd (uint8_t lun);
+void SCSI_Format_Cmd (uint8_t lun);
+
+//#define SCSI_TestUnitReady_Cmd           SCSI_Valid_Cmd
+#define SCSI_Prevent_Removal_Cmd         SCSI_Valid_Cmd
+
+/* Invalid (Unsupported) commands */
+#define SCSI_READ_CAPACITY16_Cmd         SCSI_Invalid_Cmd
+//#define SCSI_FormatUnit_Cmd              SCSI_Invalid_Cmd
+#define SCSI_Write6_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Write16_Cmd                 SCSI_Invalid_Cmd
+#define SCSI_Write12_Cmd                 SCSI_Invalid_Cmd
+#define SCSI_Read6_Cmd                   SCSI_Invalid_Cmd
+#define SCSI_Read12_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Read16_Cmd                  SCSI_Invalid_Cmd
+#define SCSI_Send_Diagnostic_Cmd         SCSI_Invalid_Cmd
+#define SCSI_Mode_Select6_Cmd            SCSI_Invalid_Cmd
+#define SCSI_Mode_Select10_Cmd           SCSI_Invalid_Cmd
+#define SCSI_Verify12_Cmd                SCSI_Invalid_Cmd
+#define SCSI_Verify16_Cmd                SCSI_Invalid_Cmd
+
+#endif /* __USB_SCSI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/readme.txt
new file mode 100644
index 0000000..944c366
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/readme.txt
@@ -0,0 +1,169 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB Mass_Storage Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+The Mass Storage Demo gives a typical example of how to use the STM32F10xxx, 
+STM32L15xxx , STM32F30xxx and STM32F37xxx USB-FS-Device peripheral to communicate 
+with the PC host using the  bulk transfer. 
+
+This demo supports the BOT (bulk only transfer) protocol and all needed SCSI
+(small computer system interface) commands, and is compatible with both Windows
+XP (SP1/SP2) and Windows 2000 (SP4).
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain
+ + \TASKING: contains preconfigured projects for TASKING toolchain
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain          
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+     - Jumper JP17 should be connected.
+     - Jumper JP20 should be not connected.
+
+  - STM32L152-EVAL Set-up 
+     - Jumper JP6 should be connected in position 1-2 (SPI2_MISO side).
+     - Jumper JP2 should be not connected.
+  
+  - STM32L152D-EVAL Set-up 
+      - LCD Glass should be mounted On IO position for MicroSD usage.
+  
+  - STM32F373C_EVAL  Set-up 
+      - None.
+
+  - STM32F303C_EVAL  Set-up 
+      - None.
+    
+How to use it
+=============
+ + EWARM
+    - Open the MassStorageSimpleBuffer.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the MassStorageSimpleBuffer.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)
+
+ + RIDE
+    - Open the MassStorageSimpleBuffer.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+  + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/fsmc_nand.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/fsmc_nand.c
new file mode 100644
index 0000000..ae3b79f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/fsmc_nand.c
@@ -0,0 +1,503 @@
+/**
+  ******************************************************************************
+  * @file    fsmc_nand.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file provides a set of functions needed to drive the
+*                      NAND512W3A2 memory mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nand.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define FSMC_Bank_NAND     FSMC_Bank2_NAND
+#define Bank_NAND_ADDR     Bank2_NAND_ADDR 
+#define Bank2_NAND_ADDR    ((uint32_t)0x70000000)
+
+/* Private macro -------------------------------------------------------------*/
+#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : FSMC_NAND_Init
+* Description    : Configures the FSMC and GPIOs to interface with the NAND memory.
+*                  This function must be called before any write/read operation
+*                  on the NAND.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NAND_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure; 
+  FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
+  FSMC_NAND_PCCARDTimingInitTypeDef  p;
+  
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+/* CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |  
+                                 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | 
+                                 GPIO_Pin_7;                                  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/* D4->D7 NAND pin configuration  */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+
+/* NWAIT NAND pin configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;   							 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/* INT2 NAND pin configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;   							 
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  /*-- FSMC Configuration ------------------------------------------------------*/
+  p.FSMC_SetupTime = 0x1;
+  p.FSMC_WaitSetupTime = 0x3;
+  p.FSMC_HoldSetupTime = 0x2;
+  p.FSMC_HiZSetupTime = 0x1;
+
+  FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
+  FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
+  FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
+  FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
+  FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
+
+  FSMC_NANDInit(&FSMC_NANDInitStructure);
+
+  /* FSMC NAND Bank Cmd Test */
+  FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadID
+* Description    : Reads NAND memory's ID.
+* Input          : - NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
+*                    the Manufacturer and Device ID.
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
+{
+  uint32_t data = 0;
+
+  /* Send Command to the command area */ 	
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+
+   /* Sequence to read ID from NAND flash */	
+   data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
+
+   NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
+   NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
+   NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
+   NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);  
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_WriteSmallPage
+* Description    : This routine is for writing one or several 512 Bytes Page size.
+* Input          : - pBuffer: pointer on the Buffer containing data to be written   
+*                  - Address: First page address
+*                  - NumPageToWrite: Number of page to write  
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
+{
+  uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /* Page write command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);  
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);  
+
+    /* Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
+
+    /* Write data */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /* Check status for successful operation */
+    status = FSMC_NAND_GetStatus();
+    
+    if(status == NAND_READY)
+    {
+      numpagewritten++;
+
+      NumPageToWrite--;
+
+      /* Calculate Next small page Address */
+      addressstatus = FSMC_NAND_AddressIncrement(&Address);    
+    }    
+  }
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadSmallPage
+* Description    : This routine is for sequential read from one or several 
+*                  512 Bytes Page size.
+* Input          : - pBuffer: pointer on the Buffer to fill  
+*                  - Address: First page address
+*                  - NumPageToRead: Number of page to read
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
+{
+  uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {	   
+    /* Page Read command and page address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A; 
+   
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); 
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1; 
+
+    /* Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
+    
+    /* Get Data into Buffer */    
+    for(; index < size; index++)
+    {
+      pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+
+    numpageread++;
+    
+    NumPageToRead--;
+
+    /* Calculate page address */           			 
+    addressstatus = FSMC_NAND_AddressIncrement(&Address);
+  }
+
+  status = FSMC_NAND_GetStatus();
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_WriteSpareArea
+* Description    : This routine write the spare area information for the specified 
+*                  pages addresses.
+* Input          : - pBuffer: pointer on the Buffer containing data to be written 
+*                  - Address: First page address
+*                  - NumSpareAreaTowrite: Number of Spare Area to write
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00; 
+
+  while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /* Page write Spare area command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS); 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS); 
+
+    /* Calculate the size */ 
+    size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
+
+    /* Write the data */ 
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /* Check status for successful operation */
+    status = FSMC_NAND_GetStatus();
+
+    if(status == NAND_READY)
+    {
+      numsparesreawritten++;      
+
+      NumSpareAreaTowrite--;  
+    
+      /* Calculate Next page Address */
+      addressstatus = FSMC_NAND_AddressIncrement(&Address);
+    }       
+  }
+  
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadSpareArea
+* Description    : This routine read the spare area information from the specified
+*                  pages addresses.
+* Input          : - pBuffer: pointer on the Buffer to fill  
+*                  - Address: First page address
+*                  - NumSpareAreaToRead: Number of Spare Area to read
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*                  And the new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
+{
+  uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {     
+    /* Page Read command and page address */     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);     
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);    
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1;
+
+    /* Data Read */
+    size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
+	
+    /* Get Data into Buffer */
+    for ( ;index < size; index++)
+    {
+      pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+    
+    numsparearearead++;
+    
+    NumSpareAreaToRead--;
+
+    /* Calculate page address */           			 
+    addressstatus = FSMC_NAND_AddressIncrement(&Address);
+  }
+
+  status = FSMC_NAND_GetStatus();
+
+  return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_EraseBlock
+* Description    : This routine erase complete block from NAND FLASH
+* Input          : - Address: Any address into block to be erased
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation 
+*******************************************************************************/
+uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
+
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+		
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; 
+
+  return (FSMC_NAND_GetStatus());
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_Reset
+* Description    : This routine reset the NAND FLASH
+* Input          : None
+* Output         : None
+* Return         : NAND_READY
+*******************************************************************************/
+uint32_t FSMC_NAND_Reset(void)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
+
+  return (NAND_READY);
+}
+
+/******************************************************************************
+* Function Name  : FSMC_NAND_GetStatus
+* Description    : Get the NAND operation status
+* Input          : None
+* Output         : None
+* Return         : New status of the NAND operation. This parameter can be:
+*                   - NAND_TIMEOUT_ERROR: when the previous operation generate 
+*                     a Timeout error
+*                   - NAND_READY: when memory is ready for the next operation    
+*******************************************************************************/
+uint32_t FSMC_NAND_GetStatus(void)
+{
+  uint32_t timeout = 0x1000000, status = NAND_READY;
+
+  status = FSMC_NAND_ReadStatus(); 
+
+  /* Wait for a NAND operation to complete or a TIMEOUT to occur */
+  while ((status != NAND_READY) &&( timeout != 0x00))
+  {
+     status = FSMC_NAND_ReadStatus();
+     timeout --;      
+  }
+
+  if(timeout == 0x00)
+  {          
+    status =  NAND_TIMEOUT_ERROR;      
+  } 
+
+  /* Return the operation status */
+  return (status);      
+}
+/******************************************************************************
+* Function Name  : FSMC_NAND_ReadStatus
+* Description    : Reads the NAND memory status using the Read status command 
+* Input          : None
+* Output         : None
+* Return         : The status of the NAND memory. This parameter can be:
+*                   - NAND_BUSY: when memory is busy
+*                   - NAND_READY: when memory is ready for the next operation    
+*                   - NAND_ERROR: when the previous operation generates error   
+*******************************************************************************/
+uint32_t FSMC_NAND_ReadStatus(void)
+{
+  uint32_t data = 0x00, status = NAND_BUSY;
+
+  /* Read status operation ------------------------------------ */
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
+  data = *(__IO uint8_t *)(Bank_NAND_ADDR);
+
+  if((data & NAND_ERROR) == NAND_ERROR)
+  {
+    status = NAND_ERROR;
+  } 
+  else if((data & NAND_READY) == NAND_READY)
+  {
+    status = NAND_READY;
+  }
+  else
+  {
+    status = NAND_BUSY; 
+  }
+  
+  return (status);
+}
+
+/******************************************************************************
+* Function Name  : NAND_AddressIncrement
+* Description    : Increment the NAND memory address
+* Input          : - Address: address to be incremented.
+* Output         : None
+* Return         : The new status of the increment address operation. It can be:
+*                  - NAND_VALID_ADDRESS: When the new address is valid address
+*                  - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  Address->Page++;
+
+  if(Address->Page == NAND_BLOCK_SIZE)
+  {
+    Address->Page = 0;
+    Address->Block++;
+    
+    if(Address->Block == NAND_ZONE_SIZE)
+    {
+      Address->Block = 0;
+      Address->Zone++;
+
+      if(Address->Zone == NAND_MAX_ZONE)
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/main.c
new file mode 100644
index 0000000..fc8d962
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/main.c
@@ -0,0 +1,86 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Mass Storage demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h" 
+#include "usb_lib.h"
+#include "usb_pwr.h"
+
+extern uint16_t MAL_Init (uint8_t lun);
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : main.
+* Description    : Main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+  Set_USBClock();
+  Led_Config();
+  USB_Interrupts_Config();
+  USB_Init();
+  while (bDeviceState != CONFIGURED);
+
+  USB_Configured_LED();
+
+  while (1)
+  {}
+}
+
+#ifdef USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/mass_mal.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/mass_mal.c
new file mode 100644
index 0000000..efce23d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/mass_mal.c
@@ -0,0 +1,233 @@
+/**
+  ******************************************************************************
+  * @file    mass_mal.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Medium Access Layer interface
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "mass_mal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint32_t Mass_Memory_Size[2];
+uint32_t Mass_Block_Size[2];
+uint32_t Mass_Block_Count[2];
+__IO uint32_t Status = 0;
+
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+SD_CardInfo mSDCardInfo;
+#endif
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : MAL_Init
+* Description    : Initializes the Media on the STM32
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Init(uint8_t lun)
+{
+  uint16_t status = MAL_OK;
+
+  switch (lun)
+  {
+    case 0:
+      Status = SD_Init();
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Init();
+      break;
+#endif
+    default:
+      return MAL_FAIL;
+  }
+  return status;
+}
+/*******************************************************************************
+* Function Name  : MAL_Write
+* Description    : Write sectors
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_Write(uint8_t lun, uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length)
+{
+
+  switch (lun)
+  {
+    case 0:
+    Status = SD_WriteMultiBlocks((uint8_t*)Writebuff, Memory_Offset, Transfer_Length,1);
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+    Status = SD_WaitWriteOperation();  
+    while(SD_GetStatus() != SD_TRANSFER_OK);
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }      
+#endif /* USE_STM3210E_EVAL ||USE_STM32L152D_EVAL*/      
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Write(Memory_Offset, Writebuff, Transfer_Length);
+      break;
+#endif /* USE_STM3210E_EVAL */  
+    default:
+      return MAL_FAIL;
+  }
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : MAL_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : Buffer pointer
+*******************************************************************************/
+uint16_t MAL_Read(uint8_t lun, uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length)
+{
+
+  switch (lun)
+  {
+    case 0:
+
+      SD_ReadMultiBlocks((uint8_t*)Readbuff, Memory_Offset, Transfer_Length, 1);
+#if defined(USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+      Status = SD_WaitReadOperation();
+      while(SD_GetStatus() != SD_TRANSFER_OK)
+      {
+      }
+      
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }
+#endif /* USE_STM3210E_EVAL */      
+      break;
+#ifdef USE_STM3210E_EVAL
+    case 1:
+      NAND_Read(Memory_Offset, Readbuff, Transfer_Length);
+      ;
+      break;
+#endif
+    default:
+      return MAL_FAIL;
+  }
+  return MAL_OK;
+}
+
+/*******************************************************************************
+* Function Name  : MAL_GetStatus
+* Description    : Get status
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+uint16_t MAL_GetStatus (uint8_t lun)
+{
+#ifdef USE_STM3210E_EVAL
+  NAND_IDTypeDef NAND_ID;
+  uint32_t DeviceSizeMul = 0, NumberOfBlocks = 0;
+#else
+  SD_CSD SD_csd;
+  uint32_t DeviceSizeMul = 0;
+#endif /* USE_STM3210E_EVAL */
+
+#ifdef USE_STM32L152D_EVAL
+
+  uint32_t NumberOfBlocks = 0;
+#endif
+
+  if (lun == 0)
+  {
+#if defined (USE_STM3210E_EVAL)  || defined(USE_STM32L152D_EVAL)
+    if (SD_Init() == SD_OK)
+    {
+      SD_GetCardInfo(&mSDCardInfo);
+      SD_SelectDeselect((uint32_t) (mSDCardInfo.RCA << 16));
+      DeviceSizeMul = (mSDCardInfo.SD_csd.DeviceSizeMul + 2);
+
+      if(mSDCardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+      {
+        Mass_Block_Count[0] = (mSDCardInfo.SD_csd.DeviceSize + 1) * 1024;
+      }
+      else
+      {
+        NumberOfBlocks  = ((1 << (mSDCardInfo.SD_csd.RdBlockLen)) / 512);
+        Mass_Block_Count[0] = ((mSDCardInfo.SD_csd.DeviceSize + 1) * (1 << DeviceSizeMul) << (NumberOfBlocks/2));
+      }
+      Mass_Block_Size[0]  = 512;
+
+      Status = SD_SelectDeselect((uint32_t) (mSDCardInfo.RCA << 16)); 
+      Status = SD_EnableWideBusOperation(SDIO_BusWide_4b); 
+      if ( Status != SD_OK )
+      {
+        return MAL_FAIL;
+      }
+     
+#else
+
+    uint32_t temp_block_mul = 0;
+    SD_GetCSDRegister(&SD_csd);
+    DeviceSizeMul = SD_csd.DeviceSizeMul + 2;
+    temp_block_mul = (1 << SD_csd.RdBlockLen)/ 512;
+    Mass_Block_Count[0] = ((SD_csd.DeviceSize + 1) * (1 << (DeviceSizeMul))) * temp_block_mul;
+    Mass_Block_Size[0] = 512;
+    Mass_Memory_Size[0] = (Mass_Block_Count[0] * Mass_Block_Size[0]);
+#endif /* USE_STM3210E_EVAL */
+      Mass_Memory_Size[0] = Mass_Block_Count[0] * Mass_Block_Size[0];
+      STM_EVAL_LEDOn(LED2);
+      return MAL_OK;
+
+#if defined (USE_STM3210E_EVAL) || defined(USE_STM32L152D_EVAL)
+    }
+#endif /* USE_STM3210E_EVAL */
+  }
+#ifdef USE_STM3210E_EVAL
+  else
+  {
+    FSMC_NAND_ReadID(&NAND_ID);
+    if (NAND_ID.Device_ID != 0 )
+    {
+      /* only one zone is used */
+      Mass_Block_Count[1] = NAND_ZONE_SIZE * NAND_BLOCK_SIZE * NAND_MAX_ZONE ;
+      Mass_Block_Size[1]  = NAND_PAGE_SIZE;
+      Mass_Memory_Size[1] = (Mass_Block_Count[1] * Mass_Block_Size[1]);
+      return MAL_OK;
+    }
+  }
+#endif /* USE_STM3210E_EVAL */
+  STM_EVAL_LEDOn(LED2);
+  return MAL_FAIL;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/memory.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/memory.c
new file mode 100644
index 0000000..919886a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/memory.c
@@ -0,0 +1,178 @@
+/**
+  ******************************************************************************
+  * @file    memory.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Memory management layer
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "memory.h"
+#include "usb_scsi.h"
+#include "usb_bot.h"
+#include "usb_regs.h"
+#include "usb_mem.h"
+#include "usb_conf.h"
+#include "hw_config.h"
+#include "mass_mal.h"
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t Block_Read_count = 0;
+__IO uint32_t Block_offset;
+__IO uint32_t Counter = 0;
+uint32_t  Idx;
+uint32_t Data_Buffer[BULK_MAX_PACKET_SIZE *2]; /* 512 bytes*/
+uint8_t TransferState = TXFR_IDLE;
+/* Extern variables ----------------------------------------------------------*/
+extern uint8_t Bulk_Data_Buff[BULK_MAX_PACKET_SIZE];  /* data buffer*/
+extern uint16_t Data_Len;
+extern uint8_t Bot_State;
+extern Bulk_Only_CBW CBW;
+extern Bulk_Only_CSW CSW;
+extern uint32_t Mass_Memory_Size[2];
+extern uint32_t Mass_Block_Size[2];
+
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Read_Memory
+* Description    : Handle the Read operation from the microSD card.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Read_Memory(uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length)
+{
+  static uint32_t Offset, Length;
+
+  if (TransferState == TXFR_IDLE )
+  {
+    Offset = Memory_Offset * Mass_Block_Size[lun];
+    Length = Transfer_Length * Mass_Block_Size[lun];
+    TransferState = TXFR_ONGOING;
+  }
+
+  if (TransferState == TXFR_ONGOING )
+  {
+    if (!Block_Read_count)
+    {
+      MAL_Read(lun ,
+               Offset ,
+               Data_Buffer,
+               Mass_Block_Size[lun]);
+
+      USB_SIL_Write(EP1_IN, (uint8_t *)Data_Buffer, BULK_MAX_PACKET_SIZE);
+
+      Block_Read_count = Mass_Block_Size[lun] - BULK_MAX_PACKET_SIZE;
+      Block_offset = BULK_MAX_PACKET_SIZE;
+    }
+    else
+    {
+      USB_SIL_Write(EP1_IN, (uint8_t *)Data_Buffer + Block_offset, BULK_MAX_PACKET_SIZE);
+
+      Block_Read_count -= BULK_MAX_PACKET_SIZE;
+      Block_offset += BULK_MAX_PACKET_SIZE;
+    }
+
+    SetEPTxCount(ENDP1, BULK_MAX_PACKET_SIZE);
+    SetEPTxStatus(ENDP1, EP_TX_VALID);  
+    Offset += BULK_MAX_PACKET_SIZE;
+    Length -= BULK_MAX_PACKET_SIZE;
+
+    CSW.dDataResidue -= BULK_MAX_PACKET_SIZE;
+    Led_RW_ON();
+  }
+  if (Length == 0)
+  {
+    Block_Read_count = 0;
+    Block_offset = 0;
+    Offset = 0;
+    Bot_State = BOT_DATA_IN_LAST;
+    TransferState = TXFR_IDLE;
+    Led_RW_OFF();
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Write_Memory
+* Description    : Handle the Write operation to the microSD card.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Write_Memory (uint8_t lun, uint32_t Memory_Offset, uint32_t Transfer_Length)
+{
+
+  static uint32_t W_Offset, W_Length;
+
+  uint32_t temp =  Counter + 64;
+
+  if (TransferState == TXFR_IDLE )
+  {
+    W_Offset = Memory_Offset * Mass_Block_Size[lun];
+    W_Length = Transfer_Length * Mass_Block_Size[lun];
+    TransferState = TXFR_ONGOING;
+  }
+
+  if (TransferState == TXFR_ONGOING )
+  {
+
+    for (Idx = 0 ; Counter < temp; Counter++)
+    {
+      *((uint8_t *)Data_Buffer + Counter) = Bulk_Data_Buff[Idx++];
+    }
+
+    W_Offset += Data_Len;
+    W_Length -= Data_Len;
+
+    if (!(W_Length % Mass_Block_Size[lun]))
+    {
+      Counter = 0;
+      MAL_Write(lun ,
+                W_Offset - Mass_Block_Size[lun],
+                Data_Buffer,
+                Mass_Block_Size[lun]);
+    }
+
+    CSW.dDataResidue -= Data_Len;
+    SetEPRxStatus(ENDP2, EP_RX_VALID); /* enable the next transaction*/   
+    Led_RW_ON();
+  }
+
+  if ((W_Length == 0) || (Bot_State == BOT_CSW_Send))
+  {
+    Counter = 0;
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+    TransferState = TXFR_IDLE;
+    Led_RW_OFF();
+  }
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/nand_if.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/nand_if.c
new file mode 100644
index 0000000..7139219
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/nand_if.c
@@ -0,0 +1,557 @@
+/**
+  ******************************************************************************
+  * @file    nand_if.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   manage NAND operations state machine
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+#include "platform_config.h"
+
+#ifdef USE_STM3210E_EVAL
+/* Includes ------------------------------------------------------------------*/
+#include "nand_if.h"
+#include "mass_mal.h"
+#include "fsmc_nand.h"
+#include "memory.h"
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* extern variables-----------------------------------------------------------*/
+extern uint32_t SCSI_LBA;
+extern uint32_t SCSI_BlkLen;
+/* Private variables ---------------------------------------------------------*/
+uint16_t LUT[1024]; //Look Up Table Buffer
+WRITE_STATE Write_State;
+BLOCK_STATE Block_State;
+NAND_ADDRESS wAddress, fAddress;
+uint16_t  phBlock, LogAddress, Initial_Page, CurrentZone = 0;
+uint16_t  Written_Pages = 0;
+
+uint16_t LUT[1024]; //Look Up Table Buffer
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static uint16_t NAND_CleanLUT(uint8_t ZoneNbr);
+static NAND_ADDRESS NAND_GetAddress(uint32_t Address);
+static uint16_t NAND_GetFreeBlock(void);
+static uint16_t NAND_Write_Cleanup(void);
+SPARE_AREA ReadSpareArea(uint32_t address);
+static uint16_t NAND_Copy(NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint16_t PageToCopy);
+static NAND_ADDRESS NAND_ConvertPhyAddress(uint32_t Address);
+static uint16_t NAND_BuildLUT(uint8_t ZoneNbr);
+
+/*******************************************************************************
+* Function Name  : NAND_Init
+* Description    : Init NAND Interface
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Init(void)
+{
+  uint16_t Status = NAND_OK;
+
+  FSMC_NAND_Init();
+  Status = NAND_BuildLUT(0);
+  Write_State = WRITE_IDLE;
+  return Status;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Write
+* Description    : write one sector by once
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Write(uint32_t Memory_Offset, uint32_t *Writebuff, uint16_t Transfer_Length)
+{
+  /* check block status and calculate start and end addresses */
+  wAddress    = NAND_GetAddress(Memory_Offset / 512);
+
+  /*check Zone: if second zone is requested build second LUT*/
+  if (wAddress.Zone != CurrentZone)
+  {
+    CurrentZone = wAddress.Zone;
+    NAND_BuildLUT(CurrentZone);
+  }
+
+  phBlock     = LUT[wAddress.Block]; /* Block Index + flags */
+  LogAddress  = wAddress.Block ; /* save logical block */
+
+  /*  IDLE state  */
+  /****************/
+  if ( Write_State == WRITE_IDLE)
+  {/* Idle state */
+
+    if (phBlock & USED_BLOCK)
+    { /* USED BLOCK */
+
+      Block_State = OLD_BLOCK;
+      /* Get a free Block for swap */
+      fAddress.Block = NAND_GetFreeBlock();
+      fAddress.Zone  = wAddress.Zone;
+      Initial_Page = fAddress.Page  = wAddress.Page;
+
+      /* write the new page */
+      FSMC_NAND_WriteSmallPage((uint8_t *)Writebuff, fAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+
+      /* get physical block */
+      wAddress.Block = phBlock & 0x3FF;
+
+
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+        return NAND_OK;
+      }
+      else
+      {
+        if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+        {
+          NAND_Write_Cleanup();
+          return NAND_OK;
+        }
+        Write_State = WRITE_ONGOING;
+        return NAND_OK;
+      }
+    }
+    else
+    {/* UNUSED BLOCK */
+
+      Block_State = UNUSED_BLOCK;
+      /* write the new page */
+      wAddress.Block = phBlock & 0x3FF;
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Written_Pages = 0;
+        NAND_Write_Cleanup();
+        return NAND_OK;
+      }
+      else
+      {
+        Write_State = WRITE_ONGOING;
+        return NAND_OK;
+      }
+    }
+  }
+  /* WRITE state */
+  /***************/
+  if ( Write_State == WRITE_ONGOING)
+  {/* Idle state */
+    if (phBlock & USED_BLOCK)
+    { /* USED BLOCK */
+
+      wAddress.Block = phBlock & 0x3FF;
+      Block_State = OLD_BLOCK;
+      fAddress.Page  = wAddress.Page;
+
+      /* check if next pages are in next block */
+      if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+      {
+        /* write Last page  */
+        FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , fAddress, PAGE_TO_WRITE);
+        Written_Pages++;
+        if (Written_Pages == SCSI_BlkLen)
+        {
+          Written_Pages = 0;
+        }
+        /* Clean up and Update the LUT */
+        NAND_Write_Cleanup();
+        Write_State = WRITE_IDLE;
+        return NAND_OK;
+      }
+
+      /* write next page */
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , fAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Write_State = WRITE_IDLE;
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+      }
+
+    }
+    else
+    {/* UNUSED BLOCK */
+      wAddress.Block = phBlock & 0x3FF;
+      /* check if it is the last page in prev block */
+      if (wAddress.Page == (NAND_BLOCK_SIZE - 1))
+      {
+        /* write Last page  */
+        FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+        Written_Pages++;
+        if (Written_Pages == SCSI_BlkLen)
+        {
+          Written_Pages = 0;
+        }
+
+        /* Clean up and Update the LUT */
+        NAND_Write_Cleanup();
+        Write_State = WRITE_IDLE;
+
+
+
+        return NAND_OK;
+      }
+      /* write next page in same block */
+      FSMC_NAND_WriteSmallPage( (uint8_t *)Writebuff , wAddress, PAGE_TO_WRITE);
+      Written_Pages++;
+      if (Written_Pages == SCSI_BlkLen)
+      {
+        Write_State = WRITE_IDLE;
+        NAND_Write_Cleanup();
+        Written_Pages = 0;
+      }
+    }
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Read
+* Description    : Read sectors
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Read(uint32_t Memory_Offset, uint32_t *Readbuff, uint16_t Transfer_Length)
+{
+  NAND_ADDRESS phAddress;
+
+  phAddress = NAND_GetAddress(Memory_Offset / 512);
+
+  if (phAddress.Zone != CurrentZone)
+  {
+    CurrentZone = phAddress.Zone;
+    NAND_BuildLUT(CurrentZone);
+  }
+
+  if (LUT [phAddress.Block] & BAD_BLOCK)
+  {
+    return NAND_FAIL;
+  }
+  else
+  {
+    phAddress.Block = LUT [phAddress.Block] & ~ (USED_BLOCK | VALID_BLOCK);
+    FSMC_NAND_ReadSmallPage ( (uint8_t *)Readbuff , phAddress, Transfer_Length / 512);
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_CleanLUT
+* Description    : Erase old blocks & rebuild the look up table
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_CleanLUT (uint8_t ZoneNbr)
+{
+#ifdef WEAR_LEVELLING_SUPPORT
+  uint16_t BlockIdx, LUT_Item;
+#endif
+  /* Rebuild the LUT for the current zone */
+  NAND_BuildLUT (ZoneNbr);
+
+#ifdef WEAR_LEVELLING_SUPPORT
+  /* Wear Leveling : circular use of free blocks */
+  LUT_Item = LUT [BlockIdx]
+             for (BlockIdx == MAX_LOG_BLOCKS_PER_ZONE ; BlockIdx < MAX_LOG_BLOCKS_PER_ZONE + WEAR_DEPTH ; BlockIdx++)
+             {
+               LUT [BlockIdx] = LUT [BlockIdx + 1];
+             }
+             LUT [ MAX_LOG_BLOCKS_PER_ZONE + WEAR_DEPTH - 1] = LUT_Item ;
+#endif
+
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_GetAddress
+* Description    : Translate logical address into a phy one
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static NAND_ADDRESS NAND_GetAddress (uint32_t Address)
+{
+  NAND_ADDRESS Address_t;
+
+  Address_t.Page  = Address & (NAND_BLOCK_SIZE - 1);
+  Address_t.Block = Address / NAND_BLOCK_SIZE;
+  Address_t.Zone = 0;
+
+  while (Address_t.Block >= MAX_LOG_BLOCKS_PER_ZONE)
+  {
+    Address_t.Block -= MAX_LOG_BLOCKS_PER_ZONE;
+    Address_t.Zone++;
+  }
+  return Address_t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_GetFreeBlock
+* Description    : Look for a free block for data exchange
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_GetFreeBlock (void)
+{
+  return LUT[MAX_LOG_BLOCKS_PER_ZONE]& ~(USED_BLOCK | VALID_BLOCK);
+}
+
+/*******************************************************************************
+* Function Name  : ReadSpareArea
+* Description    : Check used block
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+SPARE_AREA ReadSpareArea (uint32_t address)
+{
+  SPARE_AREA t;
+  uint8_t Buffer[16];
+  NAND_ADDRESS address_s;
+  address_s = NAND_ConvertPhyAddress(address);
+  FSMC_NAND_ReadSpareArea(Buffer , address_s, 1) ;
+
+  t = *(SPARE_AREA *)Buffer;
+
+  return t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Copy
+* Description    : Copy page
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_Copy (NAND_ADDRESS Address_Src, NAND_ADDRESS Address_Dest, uint16_t PageToCopy)
+{
+  uint8_t Copybuff[512];
+  for ( ; PageToCopy > 0 ; PageToCopy-- )
+  {
+    FSMC_NAND_ReadSmallPage  ((uint8_t *)Copybuff, Address_Src , 1 );
+    FSMC_NAND_WriteSmallPage ((uint8_t *)Copybuff, Address_Dest, 1);
+    FSMC_NAND_AddressIncrement(&Address_Src);
+    FSMC_NAND_AddressIncrement(&Address_Dest);
+  }
+
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Format
+* Description    : Format the entire NAND flash
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+uint16_t NAND_Format (void)
+{
+  NAND_ADDRESS phAddress;
+  SPARE_AREA  SpareArea;
+  uint32_t BlockIndex;
+
+  for (BlockIndex = 0 ; BlockIndex < NAND_ZONE_SIZE * NAND_MAX_ZONE; BlockIndex++)
+  {
+    phAddress = NAND_ConvertPhyAddress(BlockIndex * NAND_BLOCK_SIZE );
+    SpareArea = ReadSpareArea(BlockIndex * NAND_BLOCK_SIZE);
+   
+    if((SpareArea.DataStatus != 0)||(SpareArea.BlockStatus != 0)){
+        FSMC_NAND_EraseBlock (phAddress);
+    }  
+  }
+  NAND_BuildLUT(0);
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_Write_Cleanup
+* Description    : None
+* Input          : None
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static uint16_t NAND_Write_Cleanup (void)
+{
+  uint16_t  tempSpareArea [8];
+  uint16_t  Page_Back;
+
+  if ( Block_State == OLD_BLOCK )
+  {
+    /* precopy old first pages */
+    if (Initial_Page != 0)
+    {
+      Page_Back = wAddress.Page;
+      fAddress.Page = wAddress.Page = 0;
+      NAND_Copy (wAddress, fAddress, Initial_Page);
+      wAddress.Page =  Page_Back ;
+    }
+
+    /* postcopy remaining pages */
+    if ((NAND_BLOCK_SIZE - (wAddress.Page + 1)) != 0)
+    {
+      FSMC_NAND_AddressIncrement(&wAddress);
+      fAddress.Page = wAddress.Page;
+      NAND_Copy (wAddress, fAddress, NAND_BLOCK_SIZE - wAddress.Page);
+    }
+
+    /* assign logical address to new block */
+    tempSpareArea [0] = LogAddress | USED_BLOCK ;
+    tempSpareArea [1] = 0xFFFF;
+    tempSpareArea [2] = 0xFFFF;
+
+    fAddress.Page     = 0x00;
+    FSMC_NAND_WriteSpareArea( (uint8_t *)tempSpareArea , fAddress , 1);
+
+    /* erase old block */
+    FSMC_NAND_EraseBlock(wAddress);
+    NAND_CleanLUT(wAddress.Zone);
+  }
+  else
+  {/* unused block case */
+    /* assign logical address to the new used block */
+    tempSpareArea [0] = LogAddress | USED_BLOCK ;
+    tempSpareArea [1] = 0xFFFF;
+    tempSpareArea [2] = 0xFFFF;
+
+    wAddress.Page     = 0x00;
+    FSMC_NAND_WriteSpareArea((uint8_t *)tempSpareArea , wAddress, 1);
+    NAND_CleanLUT(wAddress.Zone);
+  }
+  return NAND_OK;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_ConvertPhyAddress
+* Description    : None
+* Input          : physical Address
+* Output         : None
+* Return         : Status
+*******************************************************************************/
+static NAND_ADDRESS NAND_ConvertPhyAddress (uint32_t Address)
+{
+  NAND_ADDRESS Address_t;
+
+  Address_t.Page  = Address & (NAND_BLOCK_SIZE - 1);
+  Address_t.Block = Address / NAND_BLOCK_SIZE;
+  Address_t.Zone = 0;
+
+  while (Address_t.Block >= MAX_PHY_BLOCKS_PER_ZONE)
+  {
+    Address_t.Block -= MAX_PHY_BLOCKS_PER_ZONE;
+    Address_t.Zone++;
+  }
+  return Address_t;
+}
+
+/*******************************************************************************
+* Function Name  : NAND_BuildLUT
+* Description    : Build the look up table
+* Input          : None
+* Output         : None
+* Return         : Status
+* !!!! NOTE : THIS ALGORITHM IS A SUBJECT OF PATENT FOR STMICROELECTRONICS !!!!!
+*******************************************************************************/
+static uint16_t NAND_BuildLUT (uint8_t ZoneNbr)
+{
+
+  uint16_t  pBadBlock, pCurrentBlock, pFreeBlock;
+  SPARE_AREA  SpareArea;
+  /*****************************************************************************
+                                  1st step : Init.
+  *****************************************************************************/
+  /*Init the LUT (assume all blocks free) */
+  for (pCurrentBlock = 0 ; pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE ; pCurrentBlock++)
+  {
+    LUT[pCurrentBlock] = FREE_BLOCK;  /* 12th bit is set to 1 */
+  }
+
+  /* Init Pointers */
+  pBadBlock    = MAX_PHY_BLOCKS_PER_ZONE - 1;
+  pCurrentBlock = 0;
+
+  /*****************************************************************************
+                         2nd step : locate used and bad blocks
+  *****************************************************************************/
+
+  while (pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE)
+  {
+
+    SpareArea = ReadSpareArea(pCurrentBlock * NAND_BLOCK_SIZE + (ZoneNbr * NAND_BLOCK_SIZE * MAX_PHY_BLOCKS_PER_ZONE));
+
+    if ((SpareArea.DataStatus == 0) || (SpareArea.BlockStatus == 0))
+    {
+
+      LUT[pBadBlock--]    |= pCurrentBlock | (uint16_t)BAD_BLOCK ;
+      LUT[pCurrentBlock] &= (uint16_t)~FREE_BLOCK;
+      if (pBadBlock == MAX_LOG_BLOCKS_PER_ZONE)
+      {
+        return NAND_FAIL;
+      }
+    }
+    else if (SpareArea.LogicalIndex != 0xFFFF)
+    {
+
+      LUT[SpareArea.LogicalIndex & 0x3FF] |= pCurrentBlock | VALID_BLOCK | USED_BLOCK;
+      LUT[pCurrentBlock] &= (uint16_t)( ~FREE_BLOCK);
+    }
+    pCurrentBlock++ ;
+  }
+
+  /*****************************************************************************
+     3rd step : locate Free Blocks by scanning the LUT already built partially
+  *****************************************************************************/
+  pFreeBlock = 0;
+  for (pCurrentBlock = 0 ; pCurrentBlock < MAX_PHY_BLOCKS_PER_ZONE ; pCurrentBlock++ )
+  {
+
+    if ( !(LUT[pCurrentBlock]& USED_BLOCK))
+    {
+      do
+      {
+        if (LUT[pFreeBlock] & FREE_BLOCK)
+        {
+
+          LUT [pCurrentBlock] |= pFreeBlock;
+          LUT [pFreeBlock]   &= ~FREE_BLOCK;
+          break;
+        }
+        pFreeBlock++;
+      }
+      while ( pFreeBlock < MAX_PHY_BLOCKS_PER_ZONE );
+    }
+  }
+  return NAND_OK;
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/scsi_data.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/scsi_data.c
new file mode 100644
index 0000000..9979d19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/scsi_data.c
@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    scsi_data.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Initialization of the SCSI data
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_scsi.h"
+#include "memory.h"
+
+
+uint8_t Page00_Inquiry_Data[] =
+  {
+    0x00, /* PERIPHERAL QUALIFIER & PERIPHERAL DEVICE TYPE*/
+    0x00,
+    0x00,
+    0x00,
+    0x00 /* Supported Pages 00*/
+  };
+uint8_t Standard_Inquiry_Data[] =
+  {
+    0x00,          /* Direct Access Device */
+    0x80,          /* RMB = 1: Removable Medium */
+    0x02,          /* Version: No conformance claim to standard */
+    0x02,
+
+    36 - 4,          /* Additional Length */
+    0x00,          /* SCCS = 1: Storage Controller Component */
+    0x00,
+    0x00,
+    /* Vendor Identification */
+    'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ',
+    /* Product Identification */
+    'S', 'D', ' ', 'F', 'l', 'a', 's', 'h', ' ',
+    'D', 'i', 's', 'k', ' ', ' ', ' ',
+    /* Product Revision Level */
+    '1', '.', '0', ' '
+  };
+uint8_t Standard_Inquiry_Data2[] =
+  {
+    0x00,          /* Direct Access Device */
+    0x80,          /* RMB = 1: Removable Medium */
+    0x02,          /* Version: No conformance claim to standard */
+    0x02,
+
+    36 - 4,          /* Additional Length */
+    0x00,          /* SCCS = 1: Storage Controller Component */
+    0x00,
+    0x00,
+    /* Vendor Identification */
+    'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ',
+    /* Product Identification */
+    'N', 'A', 'N', 'D', ' ', 'F', 'l', 'a', 's', 'h', ' ',
+    'D', 'i', 's', 'k', ' ',
+    /* Product Revision Level */
+    '1', '.', '0', ' '
+  };
+/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+uint8_t Mode_Sense6_data[] =
+  {
+    0x03,
+    0x00,
+    0x00,
+    0x00,
+  };
+
+/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+
+uint8_t Mode_Sense10_data[] =
+  {
+    0x00,
+    0x06,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00
+  };
+uint8_t Scsi_Sense_Data[] =
+  {
+    0x70, /*RespCode*/
+    0x00, /*SegmentNumber*/
+    NO_SENSE, /* Sens_Key*/
+    0x00,
+    0x00,
+    0x00,
+    0x00, /*Information*/
+    0x0A, /*AdditionalSenseLength*/
+    0x00,
+    0x00,
+    0x00,
+    0x00, /*CmdInformation*/
+    NO_SENSE, /*Asc*/
+    0x00, /*ASCQ*/
+    0x00, /*FRUC*/
+    0x00, /*TBD*/
+    0x00,
+    0x00 /*SenseKeySpecific*/
+  };
+uint8_t ReadCapacity10_Data[] =
+  {
+    /* Last Logical Block */
+    0,
+    0,
+    0,
+    0,
+
+    /* Block Length */
+    0,
+    0,
+    0,
+    0
+  };
+
+uint8_t ReadFormatCapacity_Data [] =
+  {
+    0x00,
+    0x00,
+    0x00,
+    0x08, /* Capacity List Length */
+
+    /* Block Count */
+    0,
+    0,
+    0,
+    0,
+
+    /* Block Length */
+    0x02,/* Descriptor Code: Formatted Media */
+    0,
+    0,
+    0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/stm32_it.c
new file mode 100644
index 0000000..7d21a9e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/stm32_it.c
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_istr.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*            STM32 Peripherals Interrupt Handlers                        */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : USB_HP_CAN1_TX_IRQHandler
+* Description    : This function handles USB High Priority or CAN TX interrupts requests
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void USB_HP_CAN1_TX_IRQHandler(void)
+{
+  CTR_HP();
+}
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined(STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+/*******************************************************************************
+* Function Name  : SDIO_IRQHandler
+* Description    : This function handles SDIO global interrupt request.
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SDIO_IRQHandler(void)
+{ 
+  /* Process All SDIO Interrupt Sources */
+  SD_ProcessIRQSrc();
+  
+}
+
+void SD_SDIO_DMA_IRQHANDLER(void)
+{
+  /* Process DMA2 Stream3 or DMA2 Stream6 Interrupt Sources */
+  SD_ProcessDMAIRQ();
+}
+
+#endif /* STM32F10X_HD | STM32F10X_XL*/
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f10x.c
new file mode 100644
index 0000000..3686a2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f10x.c
@@ -0,0 +1,917 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_XX */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+           
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_XX */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+        
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+       
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_bot.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_bot.c
new file mode 100644
index 0000000..9519a01
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_bot.c
@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file    usb_bot.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   BOT State Machine management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_scsi.h"
+#include "hw_config.h"
+#include "usb_regs.h"
+#include "usb_mem.h"
+#include "usb_conf.h"
+#include "usb_bot.h"
+#include "memory.h"
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t Bot_State;
+uint8_t Bulk_Data_Buff[BULK_MAX_PACKET_SIZE];  /* data buffer*/
+uint16_t Data_Len;
+Bulk_Only_CBW CBW;
+Bulk_Only_CSW CSW;
+uint32_t SCSI_LBA , SCSI_BlkLen;
+extern uint32_t Max_Lun;
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_In
+* Description    : Mass Storage IN transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_In (void)
+{
+  switch (Bot_State)
+  {
+    case BOT_CSW_Send:
+    case BOT_ERROR:
+      Bot_State = BOT_IDLE;
+      SetEPRxStatus(ENDP2, EP_RX_VALID);/* enable the Endpoint to receive the next cmd*/
+      if (GetEPRxStatus(EP2_OUT) == EP_RX_STALL)
+      {
+        SetEPRxStatus(EP2_OUT, EP_RX_VALID);/* enable the Endpoint to receive the next cmd*/
+      }
+      break;
+    case BOT_DATA_IN:
+      switch (CBW.CB[0])
+      {
+        case SCSI_READ10:
+          SCSI_Read10_Cmd(CBW.bLUN , SCSI_LBA , SCSI_BlkLen);
+          break;
+      }
+      break;
+    case BOT_DATA_IN_LAST:
+      Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+
+      SetEPRxStatus(ENDP2, EP_RX_VALID);
+      break;
+    default:
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_Out
+* Description    : Mass Storage OUT transfer.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_Out (void)
+{
+  uint8_t CMD;
+  CMD = CBW.CB[0];
+
+  Data_Len = USB_SIL_Read(EP2_OUT, Bulk_Data_Buff);
+
+  switch (Bot_State)
+  {
+    case BOT_IDLE:
+      CBW_Decode();
+      break;
+    case BOT_DATA_OUT:
+      if (CMD == SCSI_WRITE10)
+      {
+        SCSI_Write10_Cmd(CBW.bLUN , SCSI_LBA , SCSI_BlkLen);
+        break;
+      }
+      Bot_Abort(DIR_OUT);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_PHASE_ERROR, SEND_CSW_DISABLE);
+      break;
+    default:
+      Bot_Abort(BOTH_DIR);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_PHASE_ERROR, SEND_CSW_DISABLE);
+      break;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : CBW_Decode
+* Description    : Decode the received CBW and call the related SCSI command
+*                 routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void CBW_Decode(void)
+{
+  uint32_t Counter;
+
+  for (Counter = 0; Counter < Data_Len; Counter++)
+  {
+    *((uint8_t *)&CBW + Counter) = Bulk_Data_Buff[Counter];
+  }
+  CSW.dTag = CBW.dTag;
+  CSW.dDataResidue = CBW.dDataLength;
+  if (Data_Len != BOT_CBW_PACKET_LENGTH)
+  {
+    Bot_Abort(BOTH_DIR);
+    /* reset the CBW.dSignature to disable the clear feature until receiving a Mass storage reset*/
+    CBW.dSignature = 0;
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, PARAMETER_LIST_LENGTH_ERROR);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    return;
+  }
+
+  if ((CBW.CB[0] == SCSI_READ10 ) || (CBW.CB[0] == SCSI_WRITE10 ))
+  {
+    /* Calculate Logical Block Address */
+    SCSI_LBA = (CBW.CB[2] << 24) | (CBW.CB[3] << 16) | (CBW.CB[4] <<  8) | CBW.CB[5];
+    /* Calculate the Number of Blocks to transfer */
+    SCSI_BlkLen = (CBW.CB[7] <<  8) | CBW.CB[8];
+  }
+
+  if (CBW.dSignature == BOT_CBW_SIGNATURE)
+  {
+    /* Valid CBW */
+    if ((CBW.bLUN > Max_Lun) || (CBW.bCBLength < 1) || (CBW.bCBLength > 16))
+    {
+      Bot_Abort(BOTH_DIR);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    }
+    else
+    {
+      switch (CBW.CB[0])
+      {
+        case SCSI_REQUEST_SENSE:
+          SCSI_RequestSense_Cmd (CBW.bLUN);
+          break;
+        case SCSI_INQUIRY:
+          SCSI_Inquiry_Cmd(CBW.bLUN);
+          break;
+        case SCSI_START_STOP_UNIT:
+          SCSI_Start_Stop_Unit_Cmd(CBW.bLUN);
+          break;
+        case SCSI_ALLOW_MEDIUM_REMOVAL:
+          SCSI_Start_Stop_Unit_Cmd(CBW.bLUN);
+          break;
+        case SCSI_MODE_SENSE6:
+          SCSI_ModeSense6_Cmd (CBW.bLUN);
+          break;
+        case SCSI_MODE_SENSE10:
+          SCSI_ModeSense10_Cmd (CBW.bLUN);
+          break;
+        case SCSI_READ_FORMAT_CAPACITIES:
+          SCSI_ReadFormatCapacity_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ_CAPACITY10:
+          SCSI_ReadCapacity10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_TEST_UNIT_READY:
+          SCSI_TestUnitReady_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ10:
+          SCSI_Read10_Cmd(CBW.bLUN, SCSI_LBA , SCSI_BlkLen);
+          break;
+        case SCSI_WRITE10:
+          SCSI_Write10_Cmd(CBW.bLUN, SCSI_LBA , SCSI_BlkLen);
+          break;
+        case SCSI_VERIFY10:
+          SCSI_Verify10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_FORMAT_UNIT:
+          SCSI_Format_Cmd(CBW.bLUN);
+          break;
+          /*Unsupported command*/
+        case SCSI_MODE_SELECT10:
+          SCSI_Mode_Select10_Cmd(CBW.bLUN);
+          break;
+        case SCSI_MODE_SELECT6:
+          SCSI_Mode_Select6_Cmd(CBW.bLUN);
+          break;
+
+        case SCSI_SEND_DIAGNOSTIC:
+          SCSI_Send_Diagnostic_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ6:
+          SCSI_Read6_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ12:
+          SCSI_Read12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ16:
+          SCSI_Read16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_READ_CAPACITY16:
+          SCSI_READ_CAPACITY16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE6:
+          SCSI_Write6_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE12:
+          SCSI_Write12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_WRITE16:
+          SCSI_Write16_Cmd(CBW.bLUN);
+          break;
+        case SCSI_VERIFY12:
+          SCSI_Verify12_Cmd(CBW.bLUN);
+          break;
+        case SCSI_VERIFY16:
+          SCSI_Verify16_Cmd(CBW.bLUN);
+          break;
+
+        default:
+        {
+          Bot_Abort(BOTH_DIR);
+          Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+          Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+        }
+      }
+    }
+  }
+  else
+  {
+    /* Invalid CBW */
+    Bot_Abort(BOTH_DIR);
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Transfer_Data_Request
+* Description    : Send the request response to the PC HOST.
+* Input          : uint8_t* Data_Address : point to the data to transfer.
+*                  uint16_t Data_Length : the number of Bytes to transfer.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Transfer_Data_Request(uint8_t* Data_Pointer, uint16_t Data_Len)
+{
+  USB_SIL_Write(EP1_IN, Data_Pointer, Data_Len);
+
+    SetEPTxStatus(ENDP1, EP_TX_VALID);
+    
+  Bot_State = BOT_DATA_IN_LAST;
+  CSW.dDataResidue -= Data_Len;
+  CSW.bStatus = CSW_CMD_PASSED;
+}
+
+/*******************************************************************************
+* Function Name  : Set_CSW
+* Description    : Set the SCW with the needed fields.
+* Input          : uint8_t CSW_Status this filed can be CSW_CMD_PASSED,CSW_CMD_FAILED,
+*                  or CSW_PHASE_ERROR.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Set_CSW (uint8_t CSW_Status, uint8_t Send_Permission)
+{
+  CSW.dSignature = BOT_CSW_SIGNATURE;
+  CSW.bStatus = CSW_Status;
+
+  USB_SIL_Write(EP1_IN, ((uint8_t *)& CSW), CSW_DATA_LENGTH);
+
+  Bot_State = BOT_ERROR;
+  if (Send_Permission)
+  {
+    Bot_State = BOT_CSW_Send;
+    SetEPTxStatus(ENDP1, EP_TX_VALID);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Bot_Abort
+* Description    : Stall the needed Endpoint according to the selected direction.
+* Input          : Endpoint direction IN, OUT or both directions
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Bot_Abort(uint8_t Direction)
+{
+  switch (Direction)
+  {
+    case DIR_IN :
+      SetEPTxStatus(ENDP1, EP_TX_STALL);
+      break;
+    case DIR_OUT :
+      SetEPRxStatus(ENDP2, EP_RX_STALL);
+      break;
+    case BOTH_DIR :
+      SetEPTxStatus(ENDP1, EP_TX_STALL);
+      SetEPRxStatus(ENDP2, EP_RX_STALL);
+      break;
+    default:
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_desc.c
new file mode 100644
index 0000000..f0349d1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_desc.c
@@ -0,0 +1,147 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Mass Storage Device
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_desc.h"
+
+const uint8_t MASS_DeviceDescriptor[MASS_SIZ_DEVICE_DESC] =
+  {
+    0x12,   /* bLength  */
+    0x01,   /* bDescriptorType */
+    0x00,   /* bcdUSB, version 2.00 */
+    0x02,
+    0x00,   /* bDeviceClass : each interface define the device class */
+    0x00,   /* bDeviceSubClass */
+    0x00,   /* bDeviceProtocol */
+    0x40,   /* bMaxPacketSize0 0x40 = 64 */
+    0x83,   /* idVendor     (0483) */
+    0x04,
+    0x20,   /* idProduct */
+    0x57,
+    0x00,   /* bcdDevice 2.00*/
+    0x02,
+    1,              /* index of string Manufacturer  */
+    /**/
+    2,              /* index of string descriptor of product*/
+    /* */
+    3,              /* */
+    /* */
+    /* */
+    0x01    /*bNumConfigurations */
+  };
+const uint8_t MASS_ConfigDescriptor[MASS_SIZ_CONFIG_DESC] =
+  {
+
+    0x09,   /* bLength: Configuration Descriptor size */
+    0x02,   /* bDescriptorType: Configuration */
+    MASS_SIZ_CONFIG_DESC,
+
+    0x00,
+    0x01,   /* bNumInterfaces: 1 interface */
+    0x01,   /* bConfigurationValue: */
+    /*      Configuration value */
+    0x00,   /* iConfiguration: */
+    /*      Index of string descriptor */
+    /*      describing the configuration */
+    0xC0,   /* bmAttributes: */
+    /*      Self powered */
+    0x32,   /* MaxPower 100 mA */
+
+    /******************** Descriptor of Mass Storage interface ********************/
+    /* 09 */
+    0x09,   /* bLength: Interface Descriptor size */
+    0x04,   /* bDescriptorType: */
+    /*      Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x02,   /* bNumEndpoints*/
+    0x08,   /* bInterfaceClass: MASS STORAGE Class */
+    0x06,   /* bInterfaceSubClass : SCSI transparent*/
+    0x50,   /* nInterfaceProtocol */
+    4,          /* iInterface: */
+    /* 18 */
+    0x07,   /*Endpoint descriptor length = 7*/
+    0x05,   /*Endpoint descriptor type */
+    0x81,   /*Endpoint address (IN, address 1) */
+    0x02,   /*Bulk endpoint type */
+    0x40,   /*Maximum packet size (64 bytes) */
+    0x00,
+    0x00,   /*Polling interval in milliseconds */
+    /* 25 */
+    0x07,   /*Endpoint descriptor length = 7 */
+    0x05,   /*Endpoint descriptor type */
+    0x02,   /*Endpoint address (OUT, address 2) */
+    0x02,   /*Bulk endpoint type */
+    0x40,   /*Maximum packet size (64 bytes) */
+    0x00,
+    0x00     /*Polling interval in milliseconds*/
+    /*32*/
+  };
+const uint8_t MASS_StringLangID[MASS_SIZ_STRING_LANGID] =
+  {
+    MASS_SIZ_STRING_LANGID,
+    0x03,
+    0x09,
+    0x04
+  }
+  ;      /* LangID = 0x0409: U.S. English */
+const uint8_t MASS_StringVendor[MASS_SIZ_STRING_VENDOR] =
+  {
+    MASS_SIZ_STRING_VENDOR, /* Size of manufacturer string */
+    0x03,           /* bDescriptorType = String descriptor */
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+const uint8_t MASS_StringProduct[MASS_SIZ_STRING_PRODUCT] =
+  {
+    MASS_SIZ_STRING_PRODUCT,
+    0x03,
+    /* Product name: "STM32F10x:USB Mass Storage" */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0,
+    's', 0, ' ', 0, 'S', 0, 't', 0, 'o', 0, 'r', 0, 'a', 0, 'g', 0, 'e', 0
+
+  };
+
+uint8_t MASS_StringSerial[MASS_SIZ_STRING_SERIAL] =
+  {
+    MASS_SIZ_STRING_SERIAL,
+    0x03,
+    /* Serial number*/
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0
+  };
+const uint8_t MASS_StringInterface[MASS_SIZ_STRING_INTERFACE] =
+  {
+    MASS_SIZ_STRING_INTERFACE,
+    0x03,
+    /* Interface 0: "ST Mass" */
+    'S', 0, 'T', 0, ' ', 0, 'M', 0, 'a', 0, 's', 0, 's', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_endp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_endp.c
new file mode 100644
index 0000000..43799e3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_endp.c
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    usb_endp.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Endpoint routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_bot.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : EP1_IN_Callback
+* Description    : EP1 IN Callback Routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP1_IN_Callback(void)
+{
+  Mass_Storage_In();
+}
+
+/*******************************************************************************
+* Function Name  : EP2_OUT_Callback.
+* Description    : EP2 OUT Callback Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP2_OUT_Callback(void)
+{
+  Mass_Storage_Out();
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_prop.c
new file mode 100644
index 0000000..22eed99
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_prop.c
@@ -0,0 +1,411 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Mass Storage Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "usb_bot.h"
+#include "memory.h"
+#include "mass_mal.h"
+#include "usb_prop.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+#if defined (USE_STM3210E_EVAL)
+uint32_t Max_Lun = 1;
+#else
+uint32_t Max_Lun = 0;
+#endif
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    MASS_init,
+    MASS_Reset,
+    MASS_Status_In,
+    MASS_Status_Out,
+    MASS_Data_Setup,
+    MASS_NoData_Setup,
+    MASS_Get_Interface_Setting,
+    MASS_GetDeviceDescriptor,
+    MASS_GetConfigDescriptor,
+    MASS_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    Mass_Storage_GetConfiguration,
+    Mass_Storage_SetConfiguration,
+    Mass_Storage_GetInterface,
+    Mass_Storage_SetInterface,
+    Mass_Storage_GetStatus,
+    Mass_Storage_ClearFeature,
+    Mass_Storage_SetEndPointFeature,
+    Mass_Storage_SetDeviceFeature,
+    Mass_Storage_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)MASS_DeviceDescriptor,
+    MASS_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)MASS_ConfigDescriptor,
+    MASS_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[5] =
+  {
+    {(uint8_t*)MASS_StringLangID, MASS_SIZ_STRING_LANGID},
+    {(uint8_t*)MASS_StringVendor, MASS_SIZ_STRING_VENDOR},
+    {(uint8_t*)MASS_StringProduct, MASS_SIZ_STRING_PRODUCT},
+    {(uint8_t*)MASS_StringSerial, MASS_SIZ_STRING_SERIAL},
+    {(uint8_t*)MASS_StringInterface, MASS_SIZ_STRING_INTERFACE},
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+extern unsigned char Bot_State;
+extern Bulk_Only_CBW CBW;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : MASS_init
+* Description    : Mass Storage init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void MASS_init()
+{
+  /* Update the serial number string descriptor with the data from the unique
+  ID*/
+  Get_SerialNum();
+
+  pInformation->Current_Configuration = 0;
+
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : MASS_Reset
+* Description    : Mass Storage reset routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void MASS_Reset()
+{
+  /* Set the device as not configured */
+  Device_Info.Current_Configuration = 0;
+
+  /* Current Feature initialization */
+  pInformation->Current_Feature = MASS_ConfigDescriptor[7];
+
+  SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_NAK);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_BULK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+
+  /* Initialize Endpoint 2 */
+  SetEPType(ENDP2, EP_BULK);
+  SetEPRxAddr(ENDP2, ENDP2_RXADDR);
+  SetEPRxCount(ENDP2, Device_Property.MaxPacketSize);
+  SetEPRxStatus(ENDP2, EP_RX_VALID);
+  SetEPTxStatus(ENDP2, EP_TX_DIS);
+
+
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Set the device to response on default address */
+  SetDeviceAddress(0);
+
+  bDeviceState = ATTACHED;
+
+  CBW.dSignature = BOT_CBW_SIGNATURE;
+  Bot_State = BOT_IDLE;
+
+  USB_NotConfigured_LED();
+}
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_SetConfiguration
+* Description    : Handle the SetConfiguration request.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_SetConfiguration(void)
+{
+  if (pInformation->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+   
+    ClearDTOG_TX(ENDP1);
+    ClearDTOG_RX(ENDP2);
+
+    Bot_State = BOT_IDLE; /* set the Bot state machine to the IDLE state */
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_ClearFeature
+* Description    : Handle the ClearFeature request.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_ClearFeature(void)
+{
+  /* when the host send a CBW with invalid signature or invalid length the two
+     Endpoints (IN & OUT) shall stall until receiving a Mass Storage Reset     */
+  if (CBW.dSignature != BOT_CBW_SIGNATURE)
+    Bot_Abort(BOTH_DIR);
+}
+
+/*******************************************************************************
+* Function Name  : Mass_Storage_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Mass_Storage_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+/*******************************************************************************
+* Function Name  : MASS_Status_In
+* Description    : Mass Storage Status IN routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void MASS_Status_In(void)
+{
+  return;
+}
+
+/*******************************************************************************
+* Function Name  : MASS_Status_Out
+* Description    : Mass Storage Status OUT routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void MASS_Status_Out(void)
+{
+  return;
+}
+
+/*******************************************************************************
+* Function Name  : MASS_Data_Setup.
+* Description    : Handle the data class specific requests..
+* Input          : RequestNo.
+* Output         : None.
+* Return         : RESULT.
+*******************************************************************************/
+RESULT MASS_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t    *(*CopyRoutine)(uint16_t);
+
+  CopyRoutine = NULL;
+  if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+      && (RequestNo == GET_MAX_LUN) && (pInformation->USBwValue == 0)
+      && (pInformation->USBwIndex == 0) && (pInformation->USBwLength == 0x01))
+  {
+    CopyRoutine = Get_Max_Lun;
+  }
+  else
+  {
+    return USB_UNSUPPORT;
+  }
+
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+
+  return USB_SUCCESS;
+
+}
+
+/*******************************************************************************
+* Function Name  : MASS_NoData_Setup.
+* Description    : Handle the no data class specific requests.
+* Input          : RequestNo.
+* Output         : None.
+* Return         : RESULT.
+*******************************************************************************/
+RESULT MASS_NoData_Setup(uint8_t RequestNo)
+{
+  if ((Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+      && (RequestNo == MASS_STORAGE_RESET) && (pInformation->USBwValue == 0)
+      && (pInformation->USBwIndex == 0) && (pInformation->USBwLength == 0x00))
+  {
+    /* Initialize Endpoint 1 */
+    ClearDTOG_TX(ENDP1);
+
+    /* Initialize Endpoint 2 */
+    ClearDTOG_RX(ENDP2);
+
+    /*initialize the CBW signature to enable the clear feature*/
+    CBW.dSignature = BOT_CBW_SIGNATURE;
+    Bot_State = BOT_IDLE;
+
+    return USB_SUCCESS;
+  }
+  return USB_UNSUPPORT;
+}
+
+/*******************************************************************************
+* Function Name  : MASS_Get_Interface_Setting
+* Description    : Test the interface and the alternate setting according to the
+*                  supported one.
+* Input          : uint8_t Interface, uint8_t AlternateSetting.
+* Output         : None.
+* Return         : RESULT.
+*******************************************************************************/
+RESULT MASS_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;/* in this application we don't have AlternateSetting*/
+  }
+  else if (Interface > 0)
+  {
+    return USB_UNSUPPORT;/*in this application we have only 1 interfaces*/
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : MASS_GetDeviceDescriptor
+* Description    : Get the device descriptor.
+* Input          : uint16_t Length.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint8_t *MASS_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor );
+}
+
+/*******************************************************************************
+* Function Name  : MASS_GetConfigDescriptor
+* Description    : Get the configuration descriptor.
+* Input          : uint16_t Length.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint8_t *MASS_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor );
+}
+
+/*******************************************************************************
+* Function Name  : MASS_GetStringDescriptor
+* Description    : Get the string descriptors according to the needed index.
+* Input          : uint16_t Length.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint8_t *MASS_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+
+  if (wValue0 > 5)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Get_Max_Lun
+* Description    : Handle the Get Max Lun request.
+* Input          : uint16_t Length.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint8_t *Get_Max_Lun(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = LUN_DATA_LENGTH;
+    return 0;
+  }
+  else
+  {
+    return((uint8_t*)(&Max_Lun));
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_scsi.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_scsi.c
new file mode 100644
index 0000000..028011c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Mass_Storage/src/usb_scsi.c
@@ -0,0 +1,440 @@
+/**
+  ******************************************************************************
+  * @file    usb_scsi.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to the SCSI commands
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_scsi.h"
+#include "mass_mal.h"
+#include "usb_bot.h"
+#include "usb_regs.h"
+#include "memory.h"
+#include "platform_config.h"
+#include "usb_lib.h"
+
+#ifdef USE_STM3210E_EVAL
+ #include "nand_if.h"
+#endif /* USE_STM3210E_EVAL */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* External variables --------------------------------------------------------*/
+extern uint8_t Bulk_Data_Buff[BULK_MAX_PACKET_SIZE];  /* data buffer*/
+extern uint8_t Bot_State;
+extern Bulk_Only_CBW CBW;
+extern Bulk_Only_CSW CSW;
+extern uint32_t Mass_Memory_Size[2];
+extern uint32_t Mass_Block_Size[2];
+extern uint32_t Mass_Block_Count[2];
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : SCSI_Inquiry_Cmd
+* Description    : SCSI Inquiry Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Inquiry_Cmd(uint8_t lun)
+{
+  uint8_t* Inquiry_Data;
+  uint16_t Inquiry_Data_Length;
+
+  if (CBW.CB[1] & 0x01)/*Evpd is set*/
+  {
+    Inquiry_Data = Page00_Inquiry_Data;
+    Inquiry_Data_Length = 5;
+  }
+  else
+  {
+    if ( lun == 0)
+    {
+      Inquiry_Data = Standard_Inquiry_Data;
+    }
+    else
+    {
+      Inquiry_Data = Standard_Inquiry_Data2;
+    }
+    if (CBW.CB[4] <= STANDARD_INQUIRY_DATA_LEN)
+      Inquiry_Data_Length = CBW.CB[4];
+    else
+      Inquiry_Data_Length = STANDARD_INQUIRY_DATA_LEN;
+  }
+  Transfer_Data_Request(Inquiry_Data, Inquiry_Data_Length);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_ReadFormatCapacity_Cmd
+* Description    : SCSI ReadFormatCapacity Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_ReadFormatCapacity_Cmd(uint8_t lun)
+{
+  if (MAL_GetStatus(lun) != 0 )
+  {
+    Set_Scsi_Sense_Data(CBW.bLUN, NOT_READY, MEDIUM_NOT_PRESENT);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_ENABLE);
+    Bot_Abort(DIR_IN);
+    return;
+  }
+  ReadFormatCapacity_Data[4] = (uint8_t)(Mass_Block_Count[lun] >> 24);
+  ReadFormatCapacity_Data[5] = (uint8_t)(Mass_Block_Count[lun] >> 16);
+  ReadFormatCapacity_Data[6] = (uint8_t)(Mass_Block_Count[lun] >>  8);
+  ReadFormatCapacity_Data[7] = (uint8_t)(Mass_Block_Count[lun]);
+
+  ReadFormatCapacity_Data[9] = (uint8_t)(Mass_Block_Size[lun] >>  16);
+  ReadFormatCapacity_Data[10] = (uint8_t)(Mass_Block_Size[lun] >>  8);
+  ReadFormatCapacity_Data[11] = (uint8_t)(Mass_Block_Size[lun]);
+  Transfer_Data_Request(ReadFormatCapacity_Data, READ_FORMAT_CAPACITY_DATA_LEN);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_ReadCapacity10_Cmd
+* Description    : SCSI ReadCapacity10 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_ReadCapacity10_Cmd(uint8_t lun)
+{
+  if (MAL_GetStatus(lun))
+  {
+    Set_Scsi_Sense_Data(CBW.bLUN, NOT_READY, MEDIUM_NOT_PRESENT);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_ENABLE);
+    Bot_Abort(DIR_IN);
+    return;
+  }
+
+  ReadCapacity10_Data[0] = (uint8_t)((Mass_Block_Count[lun] - 1) >> 24);
+  ReadCapacity10_Data[1] = (uint8_t)((Mass_Block_Count[lun] - 1) >> 16);
+  ReadCapacity10_Data[2] = (uint8_t)((Mass_Block_Count[lun] - 1) >>  8);
+  ReadCapacity10_Data[3] = (uint8_t)(Mass_Block_Count[lun] - 1);
+
+  ReadCapacity10_Data[4] = (uint8_t)(Mass_Block_Size[lun] >>  24);
+  ReadCapacity10_Data[5] = (uint8_t)(Mass_Block_Size[lun] >>  16);
+  ReadCapacity10_Data[6] = (uint8_t)(Mass_Block_Size[lun] >>  8);
+  ReadCapacity10_Data[7] = (uint8_t)(Mass_Block_Size[lun]);
+  Transfer_Data_Request(ReadCapacity10_Data, READ_CAPACITY10_DATA_LEN);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_ModeSense6_Cmd
+* Description    : SCSI ModeSense6 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_ModeSense6_Cmd (uint8_t lun)
+{
+  Transfer_Data_Request(Mode_Sense6_data, MODE_SENSE6_DATA_LEN);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_ModeSense10_Cmd
+* Description    : SCSI ModeSense10 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_ModeSense10_Cmd (uint8_t lun)
+{
+  Transfer_Data_Request(Mode_Sense10_data, MODE_SENSE10_DATA_LEN);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_RequestSense_Cmd
+* Description    : SCSI RequestSense Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_RequestSense_Cmd (uint8_t lun)
+{
+  uint8_t Request_Sense_data_Length;
+
+  if (CBW.CB[4] <= REQUEST_SENSE_DATA_LEN)
+  {
+    Request_Sense_data_Length = CBW.CB[4];
+  }
+  else
+  {
+    Request_Sense_data_Length = REQUEST_SENSE_DATA_LEN;
+  }
+  Transfer_Data_Request(Scsi_Sense_Data, Request_Sense_data_Length);
+}
+
+/*******************************************************************************
+* Function Name  : Set_Scsi_Sense_Data
+* Description    : Set Scsi Sense Data routine.
+* Input          : uint8_t Sens_Key
+                   uint8_t Asc.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Set_Scsi_Sense_Data(uint8_t lun, uint8_t Sens_Key, uint8_t Asc)
+{
+  Scsi_Sense_Data[2] = Sens_Key;
+  Scsi_Sense_Data[12] = Asc;
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_Start_Stop_Unit_Cmd
+* Description    : SCSI Start_Stop_Unit Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Start_Stop_Unit_Cmd(uint8_t lun)
+{
+  Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_Read10_Cmd
+* Description    : SCSI Read10 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Read10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr)
+{
+  if (Bot_State == BOT_IDLE)
+  {
+    if (!(SCSI_Address_Management(CBW.bLUN, SCSI_READ10, LBA, BlockNbr)))/*address out of range*/
+    {
+      return;
+    }
+
+    if ((CBW.bmFlags & 0x80) != 0)
+    {
+      Bot_State = BOT_DATA_IN;
+      Read_Memory(lun, LBA , BlockNbr);
+    }
+    else
+    {
+      Bot_Abort(BOTH_DIR);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_CMD_FAILED, SEND_CSW_ENABLE);
+    }
+    return;
+  }
+  else if (Bot_State == BOT_DATA_IN)
+  {
+    Read_Memory(lun , LBA , BlockNbr);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_Write10_Cmd
+* Description    : SCSI Write10 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Write10_Cmd(uint8_t lun , uint32_t LBA , uint32_t BlockNbr)
+{
+  if (Bot_State == BOT_IDLE)
+  {
+    if (!(SCSI_Address_Management(CBW.bLUN, SCSI_WRITE10 , LBA, BlockNbr)))/*address out of range*/
+    {
+      return;
+    }
+
+    if ((CBW.bmFlags & 0x80) == 0)
+    {
+      Bot_State = BOT_DATA_OUT;
+      SetEPRxStatus(ENDP2, EP_RX_VALID);
+    }
+    else
+    {
+      Bot_Abort(DIR_IN);
+      Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+      Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    }
+    return;
+  }
+  else if (Bot_State == BOT_DATA_OUT)
+  {
+    Write_Memory(lun , LBA , BlockNbr);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_Verify10_Cmd
+* Description    : SCSI Verify10 Command routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Verify10_Cmd(uint8_t lun)
+{
+  if ((CBW.dDataLength == 0) && !(CBW.CB[1] & BLKVFY))/* BLKVFY not set*/
+  {
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+  }
+  else
+  {
+    Bot_Abort(BOTH_DIR);
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+  }
+}
+/*******************************************************************************
+* Function Name  : SCSI_Valid_Cmd
+* Description    : Valid Commands routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Valid_Cmd(uint8_t lun)
+{
+  if (CBW.dDataLength != 0)
+  {
+    Bot_Abort(BOTH_DIR);
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+  }
+  else
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+}
+/*******************************************************************************
+* Function Name  : SCSI_Valid_Cmd
+* Description    : Valid Commands routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_TestUnitReady_Cmd(uint8_t lun)
+{
+  if (MAL_GetStatus(lun))
+  {
+    Set_Scsi_Sense_Data(CBW.bLUN, NOT_READY, MEDIUM_NOT_PRESENT);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_ENABLE);
+    Bot_Abort(DIR_IN);
+    return;
+  }
+  else
+  {
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+  }
+}
+/*******************************************************************************
+* Function Name  : SCSI_Format_Cmd
+* Description    : Format Commands routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Format_Cmd(uint8_t lun)
+{
+  if (MAL_GetStatus(lun))
+  {
+    Set_Scsi_Sense_Data(CBW.bLUN, NOT_READY, MEDIUM_NOT_PRESENT);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_ENABLE);
+    Bot_Abort(DIR_IN);
+    return;
+  }
+#ifdef USE_STM3210E_EVAL
+  else
+  {
+    NAND_Format();
+    Set_CSW (CSW_CMD_PASSED, SEND_CSW_ENABLE);
+  }
+#endif
+}
+/*******************************************************************************
+* Function Name  : SCSI_Invalid_Cmd
+* Description    : Invalid Commands routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SCSI_Invalid_Cmd(uint8_t lun)
+{
+  if (CBW.dDataLength == 0)
+  {
+    Bot_Abort(DIR_IN);
+  }
+  else
+  {
+    if ((CBW.bmFlags & 0x80) != 0)
+    {
+      Bot_Abort(DIR_IN);
+    }
+    else
+    {
+      Bot_Abort(BOTH_DIR);
+    }
+  }
+  Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_COMMAND);
+  Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+}
+
+/*******************************************************************************
+* Function Name  : SCSI_Address_Management
+* Description    : Test the received address.
+* Input          : uint8_t Cmd : the command can be SCSI_READ10 or SCSI_WRITE10.
+* Output         : None.
+* Return         : Read\Write status (bool).
+*******************************************************************************/
+bool SCSI_Address_Management(uint8_t lun , uint8_t Cmd , uint32_t LBA , uint32_t BlockNbr)
+{
+  if ((LBA + BlockNbr) > Mass_Block_Count[lun] )
+  {
+    if (Cmd == SCSI_WRITE10)
+    {
+      Bot_Abort(BOTH_DIR);
+    }
+    Bot_Abort(DIR_IN);
+    Set_Scsi_Sense_Data(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    return (FALSE);
+  }
+
+  if (CBW.dDataLength != BlockNbr * Mass_Block_Size[lun])
+  {
+    if (Cmd == SCSI_WRITE10)
+    {
+      Bot_Abort(BOTH_DIR);
+    }
+    else
+    {
+      Bot_Abort(DIR_IN);
+    }
+    Set_Scsi_Sense_Data(CBW.bLUN, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
+    Set_CSW (CSW_CMD_FAILED, SEND_CSW_DISABLE);
+    return (FALSE);
+  }
+  return (TRUE);
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewd
new file mode 100644
index 0000000..26ba5a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewp
new file mode 100644
index 0000000..7f9c127
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.ewp
@@ -0,0 +1,6898 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
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+          <state>STM32F103xB	ST STM32F103xB</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+          <name>GFPUCoreSlave</name>
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+          <name>GBECoreSlave</name>
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+          <name>OGUseCmsisDspLib</name>
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+          <state>USE_STDPERIPH_DRIVER</state>
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+          <name>CCEnableRemarks</name>
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+          <state></state>
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+          <state></state>
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+          <name>CCDiagWarning</name>
+          <state></state>
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+          <name>CCDiagError</name>
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+          <version>1</version>
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+          <name>CCLangConformance</name>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
+          <name>CCRequirePrototypes</name>
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+          <name>CCMultibyteSupport</name>
+          <state>0</state>
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+          <name>CCDiagWarnAreErr</name>
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+          <name>IFpuProcessor</name>
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+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+          <state>1</state>
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+          <name>PreInclude</name>
+          <state></state>
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+          <name>CompilerMisraOverride</name>
+          <state>0</state>
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+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL</state>
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+          <state>.text</state>
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+          <name>CCOptLevel</name>
+          <state>3</state>
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+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+          <name>CCPosIndRwpi</name>
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+          <name>CCPosIndNoDynInit</name>
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+          <name>IccLang</name>
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+          <name>IccCDialect</name>
+          <state>1</state>
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+          <name>IccAllowVLA</name>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IccRTTI</name>
+          <state>1</state>
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+          <name>IccStaticDestr</name>
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+          <name>IccCmsis</name>
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+          <name>IccFloatSemantics</name>
+          <state>0</state>
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+          <state>VirtualComport_Loopback.out</state>
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+          <state>1</state>
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+        <option>
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+          <state></state>
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+          <state></state>
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+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
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+          <state></state>
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+          <state></state>
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+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
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+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
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+          <state>1</state>
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+          <state>0</state>
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+        <option>
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+          <state>0</state>
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+          <name>IlinkLogVeneer</name>
+          <state>0</state>
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+          <state>1</state>
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+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
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+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
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+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
+          <state></state>
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+          <state>__iar_program_start</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <state>0</state>
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+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+          <version>0</version>
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+          <state>0</state>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32L152xB	ST STM32L152xB</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>GBECoreSlave</name>
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+          <name>OGUseCmsisDspLib</name>
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+          <state>STM32L1XX_MD</state>
+          <state>USE_STM32L152_EVAL</state>
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+          <state></state>
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+        <option>
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+          <state></state>
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+          <state></state>
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+          <version>1</version>
+          <state>1111111</state>
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+          <state>1</state>
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+          <state></state>
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+        <option>
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+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+          <name>CCDiagWarnAreErr</name>
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+          <state>$FILE_BNAME$.o</state>
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+          <state>1</state>
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+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL</state>
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+          <state>.text</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>1</state>
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+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
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+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
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+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
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+          <name>IccCmsis</name>
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+          <name>IccFloatSemantics</name>
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+      <name>AARM</name>
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+          <name>AWarnOne</name>
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+          <name>AWarnRange1</name>
+          <state></state>
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+          <name>AWarnRange2</name>
+          <state></state>
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+          <state>80</state>
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+          <state>1</state>
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+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
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+        <option>
+          <name>ALimitErrorsCheck</name>
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+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
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+          <name>AIgnoreStdInclude</name>
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+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
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+      </data>
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+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
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+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
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+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32L152D-EVAL_VirtualComport_Loopback.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
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+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
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+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
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+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>VirtualComport_Loopback.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
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+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
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+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
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+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32l1xx_flash.icf</state>
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+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
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+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
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+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
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+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
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+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
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+          <name>IlinkExtraOptions</name>
+          <state></state>
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+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
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+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
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+          <name>IlinkAdditionalLibs</name>
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+          <state>__iar_program_start</state>
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+          <state>1</state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
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+          <name>CrcFullSize</name>
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+          <name>IlinkIElfToolPostProcess</name>
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+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
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+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
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+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <state></state>
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+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
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+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
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+          <name>ExePath</name>
+          <state>STM32373C_EVAL\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>STM32373C_EVAL\Obj</state>
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+        <option>
+          <name>ListPath</name>
+          <state>STM32373C_EVAL\List</state>
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+          <state>39</state>
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+          <version>3</version>
+          <state>1</state>
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+          <version>2</version>
+          <state>1</state>
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+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
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+        <option>
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+          <state>0</state>
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+          <state>2</state>
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+        <option>
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+          <version>0</version>
+          <state>2</state>
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+        <option>
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+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
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+          <state>4.41A</state>
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+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
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+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F373xC	ST STM32F373xC</state>
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+          <name>GenLowLevelInterface</name>
+          <state>1</state>
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+          <name>GEndianModeBE</name>
+          <state>1</state>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
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+        <option>
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+          <version>20</version>
+          <state>39</state>
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+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>39</state>
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+          <name>OGUseCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+      <name>ICCARM</name>
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+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
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+        <option>
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+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F37X</state>
+          <state>USE_STM32373C_EVAL</state>
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+        <option>
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+          <state>0</state>
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+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
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+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
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+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <group>
+    <name>Doc</name>
+    <file>
+      <name>$PROJ_DIR$\..\readme.txt</name>
+    </file>
+  </group>
+  <group>
+    <name>STM32F10x</name>
+    <excluded>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_cl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_hd.s</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_ld_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_md_vl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_xl.s</name>
+        <excluded>
+          <configuration>STM3210E-EVAL</configuration>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f10x.c</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM3210B_EVAL</name>
+      <excluded>
+        <configuration>STM3210E-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM3210C_EVAL</name>
+      <excluded>
+        <configuration>STM3210E-EVAL</configuration>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM3210E_EVAL</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL\stm3210e_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F10x_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F30X</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Source\Templates\iar\startup_stm32f30x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f30x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32303C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F30x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_syscfg.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32F37X</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Source\Templates\iar\startup_stm32f37x.s</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32f37x.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32373C_EVAL</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval_lcd.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32F37x_StdPeriph_Driver</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_adc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_can.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_dma.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_spi.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\src\stm32f37x_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_mdp.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32l1xx.c</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_endp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.eww
new file mode 100644
index 0000000..f03206a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/VirtualComport_Loopback.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\VirtualComport_Loopback.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-VCOMPort</name>
+      <member>
+        <project>CDC_LoopBack</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>CDC_LoopBack</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>CDC_LoopBack</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>CDC_LoopBack</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>CDC_LoopBack</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/stm32f30x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/stm32f30x_flash.icf
new file mode 100644
index 0000000..9d295c8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/EWARM/stm32f30x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/MDK-ARM/VirtualComport_Loopback.uvopt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/MDK-ARM/VirtualComport_Loopback.uvopt
new file mode 100644
index 0000000..72584f3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/MDK-ARM/VirtualComport_Loopback.uvopt
@@ -0,0 +1,2389 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L151xx_152xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O14 -O2062 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152D-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L162xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0579U9E -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32373C_EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32373C_EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments></SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments></TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-O14 -S0 -C0 -N00("ARM Cortex-M4") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32303C_EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32303C_EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/RIDE/VirtualComport_Loopback.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/RIDE/VirtualComport_Loopback.rprj
new file mode 100644
index 0000000..2df8f81
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/RIDE/VirtualComport_Loopback.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'VirtualComport_Loopback'" Path=".\VirtualComport_Loopback.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="VirtualComport_Loopback" >
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+</Project>
\ No newline at end of file
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new file mode 100644
index 0000000..ef33007
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.cproject
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+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..be956bf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,187 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/.project
new file mode 100644
index 0000000..f20770f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/.project
@@ -0,0 +1,197 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
new file mode 100644
index 0000000..a2ddd97
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 512k;
+    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL_XL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL_XL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM3210E-EVAL_XL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..e4cb9e8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.project
new file mode 100644
index 0000000..64d842d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/.project
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F30X/STM32F30x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
new file mode 100644
index 0000000..80853f0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32303C_EVAL/STM32303C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32303C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32303C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/.project
new file mode 100644
index 0000000..13e8e59
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32373C_EVAL/stm32373c_eval_lcd.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_lcd.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37X/STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
new file mode 100644
index 0000000..f77e8ab
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32373C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32373C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..d8ba5b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..3669bd9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,197 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
new file mode 100644
index 0000000..503c405
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
@@ -0,0 +1,151 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx_cmsis.lsl
+//
+//  Version     :  @(#)stm32l1xx_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32l1xx.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 84
+
+
+#ifndef __STACK
+#  define __STACK                       2k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        1k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32L1xx, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32l1xflash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32l1xram
+{
+    mau = 8;
+    type = ram;
+    size = 16k;
+    map ( size = 16k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" ); // FIXME: "_lc_ub_stack" does not work
+                        vector ( id = 1, fill = "Reset_Handler" );
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandle" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..5176824
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx/STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.cproject
new file mode 100644
index 0000000..02a4305
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210B-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.316348137" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.734843313" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1322668714" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.898768892" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1988110866" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F10x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STM3210B_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.601877778" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.496634270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1110536760" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="-Os " valueType="string"/>
+								<inputType id="com.atollic.truestudio.gcc.input.1633913031" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+								<option id="com.atollic.truestudio.ld.general.scriptfile.1117909711" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.296160824" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.1781072409" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
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+									<listOptionValue builtIn="false" value="STM32F10X_MD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+								<option id="com.atollic.truestudio.common_options.target.mcpu.1006608507" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F103VB" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1247154487" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.1794965867" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.950094097" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210B-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.925478812" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="scannerConfiguration">
+				<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="makefileGenerator">
+						<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..bed6a38
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..e0aa35c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210B-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103VB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20005000;    /* end of 20K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..ccb0855
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.cproject
@@ -0,0 +1,353 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
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+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM3210E-EVAL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
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+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
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+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.22089575;com.atollic.truestudio.exe.debug.22089575.;com.atollic.truestudio.exe.debug.toolchain.gcc.1449748890;com.atollic.truestudio.gcc.input.408550467">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa25d7d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:23:55 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..bfb478d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.189815562" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="STM32F10X_XL" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.189815562" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.189815562." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1571285751" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.1739352405" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM32F103ZG/Debug}" id="com.atollic.truestudio.mbs.builder1.61462586" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.371140336" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
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+								<option id="com.atollic.truestudio.common_options.target.instr_set.387750939" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.1699410786" name="Input" superClass="com.atollic.truestudio.as.input"/>
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+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX} ${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.486923113" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.1744802288" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
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+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F10x_StdPeriph_Driver/inc"/>
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+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
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+								<option id="com.atollic.truestudio.gcc.symbols.defined.1922813422" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1474007059" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.244354017" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.155448976" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.517514787" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
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+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
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+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1523226111" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
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+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1692358135" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
+					</buildOutputProvider>
+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.189815562;com.atollic.truestudio.exe.debug.189815562.;com.atollic.truestudio.exe.debug.toolchain.gcc.486923113;com.atollic.truestudio.gcc.input.377284588">
+					<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..938209b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.project
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM32F103ZG/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_xl.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_xl.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..a824e90
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:24:15 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..3b9f2f6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Virtual_COM_Port\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
new file mode 100644
index 0000000..b1c6965
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of 96K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..06577a1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,310 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..11c9ee7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F303VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/.cproject
new file mode 100644
index 0000000..f6f0f6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F37x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F37x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STM32373C_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F37X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value=" -Os" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.1266574210" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F373VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F373VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ldcc.optimization.do_garbage.631690809" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.ldcc.general.scriptfile.1826693274" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="${workspace_loc:\STM3210E-EVAL\stm32_flash.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.1826436830" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="makefileGenerator">
+				<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+			<buildOutputProvider>
+				<openAction enabled="true" filePath=""/>
+				<parser enabled="true"/>
+			</buildOutputProvider>
+			<scannerInfoProvider id="specsFile">
+				<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+				<parser enabled="true"/>
+			</scannerInfoProvider>
+		</profile>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.311825581;com.atollic.truestudio.exe.debug.311825581.;com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438;com.atollic.truestudio.gcc.input.488480100">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.22089575;com.atollic.truestudio.exe.debug.22089575.;com.atollic.truestudio.exe.debug.toolchain.gcc.1449748890;com.atollic.truestudio.gcc.input.408550467">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC"/>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="makefileGenerator">
+					<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+			<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+				<buildOutputProvider>
+					<openAction enabled="true" filePath=""/>
+					<parser enabled="true"/>
+				</buildOutputProvider>
+				<scannerInfoProvider id="specsFile">
+					<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+					<parser enabled="true"/>
+				</scannerInfoProvider>
+			</profile>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
new file mode 100644
index 0000000..734d809
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32373C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32373C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32373C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
new file mode 100644
index 0000000..35c7d30
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32373C-EVAL/STM32F373VC_FLASH.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F373VC Device with
+**                256KByte FLASH, 32KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of 32K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x100; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 32K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.cproject
new file mode 100644
index 0000000..b6d40bd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.316348137" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.project
new file mode 100644
index 0000000..cc19d22
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.project
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+	<name>STM32L152-EVAL</name>
+	<comment></comment>
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+					<value>make</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
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+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..e34e51b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:25:12 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.cproject
new file mode 100644
index 0000000..79bfbe3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.cproject
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.316348137">
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+				<externalSettings>
+					<externalSetting languages="com.atollic.truestudio.gcc.input.1633913031"/>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+					<folderInfo id="com.atollic.truestudio.exe.debug.316348137." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1057655060" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
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+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.290457456" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1"/>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.732033945" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
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+								<option id="com.atollic.truestudio.common_options.target.instr_set.424153249" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.as.input.2142008470" name="Input" superClass="com.atollic.truestudio.as.input"/>
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+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
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+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
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+								<option id="com.atollic.truestudio.gcc.symbols.defined.1107808842" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L1XX_HD"/>
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+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.172484552" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1498290489" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+						<parser enabled="true"/>
+					</scannerInfoProvider>
+				</profile>
+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
+						<parser enabled="true"/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
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+				<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+					<buildOutputProvider>
+						<openAction enabled="true" filePath=""/>
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+					<scannerInfoProvider id="specsFile">
+						<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
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+				</profile>
+				<scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.316348137;com.atollic.truestudio.exe.debug.316348137.;com.atollic.truestudio.exe.debug.toolchain.gcc.1973350339;com.atollic.truestudio.gcc.input.1633913031">
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+					<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
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+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
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+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
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+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
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+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
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+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
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+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
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+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32L152D-EVAL.com.atollic.truestudio.exe.260392079" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..819cea2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa650d6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 11:48:58 GMT+01:00 2012
+BOARD=STM32L152D-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152ZD
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
new file mode 100644
index 0000000..96ae53c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Virtual_COM_Port\TrueSTUDIO\STM32L152D-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152D-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/hw_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/hw_config.h
new file mode 100644
index 0000000..9c1f2f1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/hw_config.h
@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define MASS_MEMORY_START     0x04002000
+#define BULK_MAX_PACKET_SIZE  0x00000040
+#define LED_ON                0xF0
+#define LED_OFF               0xFF
+
+/* Exported functions ------------------------------------------------------- */
+void Set_System(void);
+void Set_USBClock(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void USB_Cable_Config (FunctionalState NewState);
+void Get_SerialNum(void);
+void LCD_Control(void);
+uint32_t CDC_Send_DATA (uint8_t *ptrBuffer, uint8_t Send_length);
+uint32_t CDC_Receive_DATA(void);
+/* External variables --------------------------------------------------------*/
+
+#endif  /*__HW_CONFIG_H*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/platform_config.h
new file mode 100644
index 0000000..02bdb83
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/platform_config.h
@@ -0,0 +1,155 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)  && !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL) &&  !defined (USE_STM32373C_EVAL) &&  !defined (USE_STM32303C_EVAL)
+//#define USE_STM3210B_EVAL
+//#define USE_STM3210E_EVAL
+//#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define (USE_STM32373C_EVAL)
+#define (USE_STM32303C_EVAL)
+#endif
+
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+ 
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+#elif defined (USE_STM32373C_EVAL)
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+
+#elif defined (USE_STM32303C_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+#endif /* USE_STM3210B_EVAL */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_conf.h
new file mode 100644
index 0000000..f1fe606
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_conf.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    usb_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Virtual COM Port Demo configuration  header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CONF_H
+#define __USB_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+
+/*-------------------------------------------------------------*/
+/* EP_NUM */
+/* defines how many endpoints are used by the device */
+/*-------------------------------------------------------------*/
+
+#define EP_NUM                          (4)
+
+/*-------------------------------------------------------------*/
+/* --------------   Buffer Description Table  -----------------*/
+/*-------------------------------------------------------------*/
+/* buffer table base address */
+/* buffer table base address */
+#define BTABLE_ADDRESS      (0x00)
+
+/* EP0  */
+/* rx/tx buffer base address */
+#define ENDP0_RXADDR        (0x40)
+#define ENDP0_TXADDR        (0x80)
+
+/* EP1  */
+/* tx buffer base address */
+#define ENDP1_TXADDR        (0xC0)
+#define ENDP2_TXADDR        (0x100)
+#define ENDP3_RXADDR        (0x110)
+
+
+/*-------------------------------------------------------------*/
+/* -------------------   ISTR events  -------------------------*/
+/*-------------------------------------------------------------*/
+/* IMR_MSK */
+/* mask defining which events has to be handled */
+/* by the device application software */
+#define IMR_MSK (CNTR_CTRM  | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM  | CNTR_SOFM \
+                 | CNTR_ESOFM | CNTR_RESETM )
+
+/*#define CTR_CALLBACK*/
+/*#define DOVR_CALLBACK*/
+/*#define ERR_CALLBACK*/
+/*#define WKUP_CALLBACK*/
+/*#define SUSP_CALLBACK*/
+/*#define RESET_CALLBACK*/
+/*#define SOF_CALLBACK*/
+/*#define ESOF_CALLBACK*/
+/* CTR service routines */
+/* associated to defined endpoints */
+/*#define  EP1_IN_Callback   NOP_Process*/
+#define  EP2_IN_Callback   NOP_Process
+#define  EP3_IN_Callback   NOP_Process
+#define  EP4_IN_Callback   NOP_Process
+#define  EP5_IN_Callback   NOP_Process
+#define  EP6_IN_Callback   NOP_Process
+#define  EP7_IN_Callback   NOP_Process
+
+#define  EP1_OUT_Callback   NOP_Process
+#define  EP2_OUT_Callback   NOP_Process
+/*#define  EP3_OUT_Callback   NOP_Process*/
+#define  EP4_OUT_Callback   NOP_Process
+#define  EP5_OUT_Callback   NOP_Process
+#define  EP6_OUT_Callback   NOP_Process
+#define  EP7_OUT_Callback   NOP_Process
+
+#endif /* __USB_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_desc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_desc.h
new file mode 100644
index 0000000..6a26870
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_desc.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptor Header for Virtual COM Port Device
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
+#define USB_STRING_DESCRIPTOR_TYPE              0x03
+#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
+#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
+
+#define VIRTUAL_COM_PORT_DATA_SIZE              64
+#define VIRTUAL_COM_PORT_INT_SIZE               8
+
+#define VIRTUAL_COM_PORT_SIZ_DEVICE_DESC        18
+#define VIRTUAL_COM_PORT_SIZ_CONFIG_DESC        67
+#define VIRTUAL_COM_PORT_SIZ_STRING_LANGID      4
+#define VIRTUAL_COM_PORT_SIZ_STRING_VENDOR      38
+#define VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT     50
+#define VIRTUAL_COM_PORT_SIZ_STRING_SERIAL      26
+
+#define STANDARD_ENDPOINT_DESC_SIZE             0x09
+
+/* Exported functions ------------------------------------------------------- */
+extern const uint8_t Virtual_Com_Port_DeviceDescriptor[VIRTUAL_COM_PORT_SIZ_DEVICE_DESC];
+extern const uint8_t Virtual_Com_Port_ConfigDescriptor[VIRTUAL_COM_PORT_SIZ_CONFIG_DESC];
+
+extern const uint8_t Virtual_Com_Port_StringLangID[VIRTUAL_COM_PORT_SIZ_STRING_LANGID];
+extern const uint8_t Virtual_Com_Port_StringVendor[VIRTUAL_COM_PORT_SIZ_STRING_VENDOR];
+extern const uint8_t Virtual_Com_Port_StringProduct[VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT];
+extern uint8_t Virtual_Com_Port_StringSerial[VIRTUAL_COM_PORT_SIZ_STRING_SERIAL];
+
+#endif /* __USB_DESC_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_istr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_istr.h
new file mode 100644
index 0000000..3e322b1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_istr.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file includes the peripherals header files in the user application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_ISTR_H
+#define __USB_ISTR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+ void USB_Istr(void);
+
+/* function prototypes Automatically built defining related macros */
+
+void EP1_IN_Callback(void);
+void EP2_IN_Callback(void);
+void EP3_IN_Callback(void);
+void EP4_IN_Callback(void);
+void EP5_IN_Callback(void);
+void EP6_IN_Callback(void);
+void EP7_IN_Callback(void);
+
+void EP1_OUT_Callback(void);
+void EP2_OUT_Callback(void);
+void EP3_OUT_Callback(void);
+void EP4_OUT_Callback(void);
+void EP5_OUT_Callback(void);
+void EP6_OUT_Callback(void);
+void EP7_OUT_Callback(void);
+
+#ifdef CTR_CALLBACK
+void CTR_Callback(void);
+#endif
+
+#ifdef DOVR_CALLBACK
+void DOVR_Callback(void);
+#endif
+
+#ifdef ERR_CALLBACK
+void ERR_Callback(void);
+#endif
+
+#ifdef WKUP_CALLBACK
+void WKUP_Callback(void);
+#endif
+
+#ifdef SUSP_CALLBACK
+void SUSP_Callback(void);
+#endif
+
+#ifdef RESET_CALLBACK
+void RESET_Callback(void);
+#endif
+
+#ifdef SOF_CALLBACK
+void SOF_Callback(void);
+#endif
+
+#ifdef ESOF_CALLBACK
+void ESOF_Callback(void);
+#endif
+#endif /*__USB_ISTR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_prop.h
new file mode 100644
index 0000000..bd81702
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/inc/usb_prop.h
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Virtual COM Port Demo (Endpoint 0)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __usb_prop_H
+#define __usb_prop_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint32_t bitrate;
+  uint8_t format;
+  uint8_t paritytype;
+  uint8_t datatype;
+}LINE_CODING;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+
+#define Virtual_Com_Port_GetConfiguration          NOP_Process
+//#define Virtual_Com_Port_SetConfiguration          NOP_Process
+#define Virtual_Com_Port_GetInterface              NOP_Process
+#define Virtual_Com_Port_SetInterface              NOP_Process
+#define Virtual_Com_Port_GetStatus                 NOP_Process
+#define Virtual_Com_Port_ClearFeature              NOP_Process
+#define Virtual_Com_Port_SetEndPointFeature        NOP_Process
+#define Virtual_Com_Port_SetDeviceFeature          NOP_Process
+//#define Virtual_Com_Port_SetDeviceAddress          NOP_Process
+
+#define SEND_ENCAPSULATED_COMMAND   0x00
+#define GET_ENCAPSULATED_RESPONSE   0x01
+#define SET_COMM_FEATURE            0x02
+#define GET_COMM_FEATURE            0x03
+#define CLEAR_COMM_FEATURE          0x04
+#define SET_LINE_CODING             0x20
+#define GET_LINE_CODING             0x21
+#define SET_CONTROL_LINE_STATE      0x22
+#define SEND_BREAK                  0x23
+
+/* Exported functions ------------------------------------------------------- */
+void Virtual_Com_Port_init(void);
+void Virtual_Com_Port_Reset(void);
+void Virtual_Com_Port_SetConfiguration(void);
+void Virtual_Com_Port_SetDeviceAddress (void);
+void Virtual_Com_Port_Status_In (void);
+void Virtual_Com_Port_Status_Out (void);
+RESULT Virtual_Com_Port_Data_Setup(uint8_t);
+RESULT Virtual_Com_Port_NoData_Setup(uint8_t);
+RESULT Virtual_Com_Port_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *Virtual_Com_Port_GetDeviceDescriptor(uint16_t );
+uint8_t *Virtual_Com_Port_GetConfigDescriptor(uint16_t);
+uint8_t *Virtual_Com_Port_GetStringDescriptor(uint16_t);
+
+uint8_t *Virtual_Com_Port_GetLineCoding(uint16_t Length);
+uint8_t *Virtual_Com_Port_SetLineCoding(uint16_t Length);
+
+#endif /* __usb_prop_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/readme.txt
new file mode 100644
index 0000000..abfa558
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/readme.txt
@@ -0,0 +1,175 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB VirtualComport_Loopback  Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+The aim of this example is to read data from and write data to USB devices using the CDC protocol. 
+It makes the USB device look like a serial port (NO serial cable connectors:You can see the data
+transferred to and from via USB instead of USB-to-USART bridge connection). 
+This example loops back the contents of a text file over usb port. To run the example, Type a message using the Pc's keyboard.
+Any data that shows in HyperTerminal is received from the device.
+This VirtualComport_Loopback Demo provides the firmware examples for the STM32F10xxx, STM32L15xxx,
+STM32F30xxx and STM32F37xxx families.
+
+- OUT transfers (receive the data from the PC to STM32):
+	When a packet is received from the PC on the OUT pipe (EP3), EP3_IN_Callback will process the receive data.
+	To receive something to the STM32 data are stored in the Receive_Buffer[] by calling CDC_Receive_DATA() 
+ 
+- IN transfers (to send the data received from the STM32 to the PC):
+	When a packet is sent from the STM32 on the IN pipe (EP1), EP1_IN_Callback will process the send data.
+	To send something to the HOST we put the data in to the Send_Buffer[] buffer and call CDC_Send_DATA() 
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain
+ + \TASKNIG: contains preconfigured projects for TASKING toolchain
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain          
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+
+  - STM32L152-EVAL Set-up 
+     - Jumper JP19 should be not connected. 
+  
+  - STM32L152D-EVAL Set-up 
+	- None	
+    
+  - STM32F373C_EVAL  Set-up 
+	- None
+
+  - STM32F303C_EVAL  Set-up 
+	- None
+
+How to use it
+=============
+ + EWARM
+    - Open the VirtualComport_Loopback.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices   
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the VirtualComport_Loopback.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5) 
+
+ + RIDE
+    - Open the VirtualComport_Loopback.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+       - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/hw_config.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/hw_config.c
new file mode 100644
index 0000000..d952ff7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/hw_config.c
@@ -0,0 +1,379 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "hw_config.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ErrorStatus HSEStartUpStatus;
+EXTI_InitTypeDef EXTI_InitStructure;
+extern __IO uint32_t packet_sent;
+extern __IO uint8_t Send_Buffer[VIRTUAL_COM_PORT_DATA_SIZE] ;
+extern __IO  uint32_t packet_receive;
+extern __IO uint8_t Receive_length;
+
+uint8_t Receive_Buffer[64];
+uint32_t Send_length;
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
+/* Extern variables ----------------------------------------------------------*/
+
+extern LINE_CODING linecoding;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : Set_System
+* Description    : Configures Main system clocks & power
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_System(void)
+{
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)
+  GPIO_InitTypeDef GPIO_InitStructure;
+#endif /* STM32L1XX_MD && STM32L1XX_XD */  
+
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /* USB_USE_EXTERNAL_PULLUP */ 
+  
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */   
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined(STM32F37X) || defined(STM32F30X)
+  /* Enable the SYSCFG module clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+#endif /* STM32L1XX_XD */ 
+   
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS) && !defined(STM32F37X) && !defined(STM32F30X)
+  /* Enable USB_DISCONNECT GPIO clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE);
+
+  /* Configure USB pull-up pin */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32L1XX_MD && STM32L1XX_XD */
+   
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);  
+#endif /* USB_USE_EXTERNAL_PULLUP */ 
+  
+#if defined(STM32F37X) || defined(STM32F30X)
+  
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+  
+  /*Set PA11,12 as IN - USB_DM,DP*/ 
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /*SET PA11,12 for USB: USB_DM,DP*/
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_14);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_14);
+  
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32F37X  && STM32F30X)*/
+ 
+   /* Configure the EXTI line 18 connected internally to the USB IP */
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure); 
+}
+
+/*******************************************************************************
+* Function Name  : Set_USBClock
+* Description    : Configures USB Clock input (48MHz)
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_USBClock(void)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+  /* Enable USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+  
+#else 
+  /* Select USBCLK source */
+  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
+  
+  /* Enable the USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : Enter_LowPowerMode
+* Description    : Power-off system clocks and power while entering suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Enter_LowPowerMode(void)
+{
+  /* Set the device state to suspend */
+  bDeviceState = SUSPENDED;
+}
+
+/*******************************************************************************
+* Function Name  : Leave_LowPowerMode
+* Description    : Restores system clocks and power while exiting suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Leave_LowPowerMode(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  /* Set the device state to the correct state */
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+  else
+  {
+    bDeviceState = ATTACHED;
+  }
+    /*Enable SystemCoreClock*/
+  SystemInit();
+}
+
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config
+* Description    : Configures the USB interrupts
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Interrupts_Config(void)
+{
+NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* 2 bit for pre-emption priority, 2 bits for subpriority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+ 
+#if defined(STM32L1XX_MD)|| defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+#elif defined(STM32F37X)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#else
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure);   
+#endif
+}
+
+/*******************************************************************************
+* Function Name  : USB_Cable_Config
+* Description    : Software Connection/Disconnection of USB Cable
+* Input          : None.
+* Return         : Status
+*******************************************************************************/
+void USB_Cable_Config (FunctionalState NewState)
+{
+#if defined(STM32L1XX_MD) || defined (STM32L1XX_HD)|| (STM32L1XX_MD_PLUS)
+  if (NewState != DISABLE)
+  {
+    STM32L15_USB_CONNECT;
+  }
+  else
+  {
+    STM32L15_USB_DISCONNECT;
+  }  
+  
+#else /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+  if (NewState != DISABLE)
+  {
+    GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+  else
+  {
+    GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : Get_SerialNum.
+* Description    : Create the serial number string descriptor.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Get_SerialNum(void)
+{
+  uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+
+  Device_Serial0 = *(uint32_t*)ID1;
+  Device_Serial1 = *(uint32_t*)ID2;
+  Device_Serial2 = *(uint32_t*)ID3;
+ 
+  Device_Serial0 += Device_Serial2;
+
+  if (Device_Serial0 != 0)
+  {
+    IntToUnicode (Device_Serial0, &Virtual_Com_Port_StringSerial[2] , 8);
+    IntToUnicode (Device_Serial1, &Virtual_Com_Port_StringSerial[18], 4);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : HexToChar.
+* Description    : Convert Hex 32Bits value into char.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
+{
+  uint8_t idx = 0;
+  
+  for( idx = 0 ; idx < len ; idx ++)
+  {
+    if( ((value >> 28)) < 0xA )
+    {
+      pbuf[ 2* idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2* idx] = (value >> 28) + 'A' - 10; 
+    }
+    
+    value = value << 4;
+    
+    pbuf[ 2* idx + 1] = 0;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Send DATA .
+* Description    : send the data received from the STM32 to the PC through USB  
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint32_t CDC_Send_DATA (uint8_t *ptrBuffer, uint8_t Send_length)
+{
+  /*if max buffer is Not reached*/
+  if(Send_length < VIRTUAL_COM_PORT_DATA_SIZE)     
+  {
+    /*Sent flag*/
+    packet_sent = 0;
+    /* send  packet to PMA*/
+    UserToPMABufferCopy((unsigned char*)ptrBuffer, ENDP1_TXADDR, Send_length);
+    SetEPTxCount(ENDP1, Send_length);
+    SetEPTxValid(ENDP1);
+  }
+  else
+  {
+    return 0;
+  } 
+  return 1;
+}
+
+/*******************************************************************************
+* Function Name  : Receive DATA .
+* Description    : receive the data from the PC to STM32 and send it through USB
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+uint32_t CDC_Receive_DATA(void)
+{ 
+  /*Receive flag*/
+  packet_receive = 0;
+  SetEPRxValid(ENDP3); 
+  return 1 ;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/main.c
new file mode 100644
index 0000000..a3a1aa8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/main.c
@@ -0,0 +1,100 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Virtual Com Port Demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+extern __IO uint8_t Receive_Buffer[64];
+extern __IO  uint32_t Receive_length ;
+extern __IO  uint32_t length ;
+uint8_t Send_Buffer[64];
+uint32_t packet_sent=1;
+uint32_t packet_receive=1;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : main.
+* Descriptioan    : Main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+  Set_USBClock();
+  USB_Interrupts_Config();
+  USB_Init();
+  
+  while (1)
+  {
+    if (bDeviceState == CONFIGURED)
+    {
+      CDC_Receive_DATA();
+      /*Check to see if we have data yet */
+      if (Receive_length  != 0)
+      {
+        if (packet_sent == 1)
+          CDC_Send_DATA ((unsigned char*)Receive_Buffer,Receive_length);
+        Receive_length = 0;
+      }
+    }
+  }
+} 
+
+#ifdef USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/stm32_it.c
new file mode 100644
index 0000000..698c8a6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/stm32_it.c
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined (STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f30x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f30x.c
new file mode 100644
index 0000000..31faf5c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f30x.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f30x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F30x devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f30x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f30x.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F30x device                          
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f30x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F30x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f30x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Defines
+  * @{
+  */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32F30x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 72000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR &= 0xF87FC00C;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+  RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_desc.c
new file mode 100644
index 0000000..ca93915
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_desc.c
@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Virtual Com Port Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* USB Standard Device Descriptor */
+const uint8_t Virtual_Com_Port_DeviceDescriptor[] =
+  {
+    0x12,   /* bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE,     /* bDescriptorType */
+    0x00,
+    0x02,   /* bcdUSB = 2.00 */
+    0x02,   /* bDeviceClass: CDC */
+    0x00,   /* bDeviceSubClass */
+    0x00,   /* bDeviceProtocol */
+    0x40,   /* bMaxPacketSize0 */
+    0x83,
+    0x04,   /* idVendor = 0x0483 */
+    0x40,
+    0x57,   /* idProduct = 0x7540 */
+    0x00,
+    0x02,   /* bcdDevice = 2.00 */
+    1,              /* Index of string descriptor describing manufacturer */
+    2,              /* Index of string descriptor describing product */
+    3,              /* Index of string descriptor describing the device's serial number */
+    0x01    /* bNumConfigurations */
+  };
+
+const uint8_t Virtual_Com_Port_ConfigDescriptor[] =
+  {
+    /*Configuration Descriptor*/
+    0x09,   /* bLength: Configuration Descriptor size */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE,      /* bDescriptorType: Configuration */
+    VIRTUAL_COM_PORT_SIZ_CONFIG_DESC,       /* wTotalLength:no of returned bytes */
+    0x00,
+    0x02,   /* bNumInterfaces: 2 interface */
+    0x01,   /* bConfigurationValue: Configuration value */
+    0x00,   /* iConfiguration: Index of string descriptor describing the configuration */
+    0xC0,   /* bmAttributes: self powered */
+    0x32,   /* MaxPower 0 mA */
+    /*Interface Descriptor*/
+    0x09,   /* bLength: Interface Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,  /* bDescriptorType: Interface */
+    /* Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x01,   /* bNumEndpoints: One endpoints used */
+    0x02,   /* bInterfaceClass: Communication Interface Class */
+    0x02,   /* bInterfaceSubClass: Abstract Control Model */
+    0x01,   /* bInterfaceProtocol: Common AT commands */
+    0x00,   /* iInterface: */
+    /*Header Functional Descriptor*/
+    0x05,   /* bLength: Endpoint Descriptor size */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x00,   /* bDescriptorSubtype: Header Func Desc */
+    0x10,   /* bcdCDC: spec release number */
+    0x01,
+    /*Call Management Functional Descriptor*/
+    0x05,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x01,   /* bDescriptorSubtype: Call Management Func Desc */
+    0x00,   /* bmCapabilities: D0+D1 */
+    0x01,   /* bDataInterface: 1 */
+    /*ACM Functional Descriptor*/
+    0x04,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x02,   /* bDescriptorSubtype: Abstract Control Management desc */
+    0x02,   /* bmCapabilities */
+    /*Union Functional Descriptor*/
+    0x05,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x06,   /* bDescriptorSubtype: Union func desc */
+    0x00,   /* bMasterInterface: Communication class interface */
+    0x01,   /* bSlaveInterface0: Data Class Interface */
+    /*Endpoint 2 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x82,   /* bEndpointAddress: (IN2) */
+    0x03,   /* bmAttributes: Interrupt */
+    VIRTUAL_COM_PORT_INT_SIZE,      /* wMaxPacketSize: */
+    0x00,
+    0xFF,   /* bInterval: */
+    /*Data class interface descriptor*/
+    0x09,   /* bLength: Endpoint Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,  /* bDescriptorType: */
+    0x01,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x02,   /* bNumEndpoints: Two endpoints used */
+    0x0A,   /* bInterfaceClass: CDC */
+    0x00,   /* bInterfaceSubClass: */
+    0x00,   /* bInterfaceProtocol: */
+    0x00,   /* iInterface: */
+    /*Endpoint 3 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x03,   /* bEndpointAddress: (OUT3) */
+    0x02,   /* bmAttributes: Bulk */
+    VIRTUAL_COM_PORT_DATA_SIZE,             /* wMaxPacketSize: */
+    0x00,
+    0x00,   /* bInterval: ignore for Bulk transfer */
+    /*Endpoint 1 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x81,   /* bEndpointAddress: (IN1) */
+    0x02,   /* bmAttributes: Bulk */
+    VIRTUAL_COM_PORT_DATA_SIZE,             /* wMaxPacketSize: */
+    0x00,
+    0x00    /* bInterval */
+  };
+
+/* USB String Descriptors */
+const uint8_t Virtual_Com_Port_StringLangID[VIRTUAL_COM_PORT_SIZ_STRING_LANGID] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_LANGID,
+    USB_STRING_DESCRIPTOR_TYPE,
+    0x09,
+    0x04 /* LangID = 0x0409: U.S. English */
+  };
+
+const uint8_t Virtual_Com_Port_StringVendor[VIRTUAL_COM_PORT_SIZ_STRING_VENDOR] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_VENDOR,     /* Size of Vendor string */
+    USB_STRING_DESCRIPTOR_TYPE,             /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t Virtual_Com_Port_StringProduct[VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT,          /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    /* Product name: "STM32 Virtual COM Port" */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'V', 0, 'i', 0,
+    'r', 0, 't', 0, 'u', 0, 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0,
+    'M', 0, ' ', 0, 'P', 0, 'o', 0, 'r', 0, 't', 0, ' ', 0, ' ', 0
+  };
+
+uint8_t Virtual_Com_Port_StringSerial[VIRTUAL_COM_PORT_SIZ_STRING_SERIAL] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_SERIAL,           /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,                   /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_endp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_endp.c
new file mode 100644
index 0000000..ee2c603
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_endp.c
@@ -0,0 +1,78 @@
+/**
+  ******************************************************************************
+  * @file    usb_endp.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Endpoint routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_mem.h"
+#include "hw_config.h"
+#include "usb_istr.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Interval between sending IN packets in frame number (1 frame = 1ms) */
+#define VCOMPORT_IN_FRAME_INTERVAL             5
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern __IO uint32_t packet_sent;
+extern __IO uint32_t packet_receive;
+extern __IO uint8_t Receive_Buffer[64];
+uint32_t Receive_length;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : EP1_IN_Callback
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+
+void EP1_IN_Callback (void)
+{
+  packet_sent = 1;
+}
+
+/*******************************************************************************
+* Function Name  : EP3_OUT_Callback
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP3_OUT_Callback(void)
+{
+  packet_receive = 1;
+  Receive_length = GetEPRxCount(ENDP3);
+  PMAToUserBufferCopy((unsigned char*)Receive_Buffer, ENDP3_RXADDR, Receive_length);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_prop.c
new file mode 100644
index 0000000..c8176c5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_prop.c
@@ -0,0 +1,414 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Virtual Com Port Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t Request = 0;
+
+LINE_CODING linecoding =
+  {
+    115200, /* baud rate*/
+    0x00,   /* stop bits-1*/
+    0x00,   /* parity - none*/
+    0x08    /* no. of bits 8*/
+  };
+
+/* -------------------------------------------------------------------------- */
+/*  Structures initializations */
+/* -------------------------------------------------------------------------- */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    Virtual_Com_Port_init,
+    Virtual_Com_Port_Reset,
+    Virtual_Com_Port_Status_In,
+    Virtual_Com_Port_Status_Out,
+    Virtual_Com_Port_Data_Setup,
+    Virtual_Com_Port_NoData_Setup,
+    Virtual_Com_Port_Get_Interface_Setting,
+    Virtual_Com_Port_GetDeviceDescriptor,
+    Virtual_Com_Port_GetConfigDescriptor,
+    Virtual_Com_Port_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    Virtual_Com_Port_GetConfiguration,
+    Virtual_Com_Port_SetConfiguration,
+    Virtual_Com_Port_GetInterface,
+    Virtual_Com_Port_SetInterface,
+    Virtual_Com_Port_GetStatus,
+    Virtual_Com_Port_ClearFeature,
+    Virtual_Com_Port_SetEndPointFeature,
+    Virtual_Com_Port_SetDeviceFeature,
+    Virtual_Com_Port_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)Virtual_Com_Port_DeviceDescriptor,
+    VIRTUAL_COM_PORT_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)Virtual_Com_Port_ConfigDescriptor,
+    VIRTUAL_COM_PORT_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+  {
+    {(uint8_t*)Virtual_Com_Port_StringLangID, VIRTUAL_COM_PORT_SIZ_STRING_LANGID},
+    {(uint8_t*)Virtual_Com_Port_StringVendor, VIRTUAL_COM_PORT_SIZ_STRING_VENDOR},
+    {(uint8_t*)Virtual_Com_Port_StringProduct, VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT},
+    {(uint8_t*)Virtual_Com_Port_StringSerial, VIRTUAL_COM_PORT_SIZ_STRING_SERIAL}
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_init.
+* Description    : Virtual COM Port Mouse init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_init(void)
+{
+
+  /* Update the serial number string descriptor with the data from the unique
+  ID*/
+  Get_SerialNum();
+
+  pInformation->Current_Configuration = 0;
+
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Reset
+* Description    : Virtual_Com_Port Mouse reset routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Reset(void)
+{
+  /* Set Virtual_Com_Port DEVICE as not configured */
+  pInformation->Current_Configuration = 0;
+
+  /* Current Feature initialization */
+  pInformation->Current_Feature = Virtual_Com_Port_ConfigDescriptor[7];
+
+  /* Set Virtual_Com_Port DEVICE with the default Interface*/
+  pInformation->Current_Interface = 0;
+
+  SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_BULK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+
+  /* Initialize Endpoint 2 */
+  SetEPType(ENDP2, EP_INTERRUPT);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPRxStatus(ENDP2, EP_RX_DIS);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+
+  /* Initialize Endpoint 3 */
+  SetEPType(ENDP3, EP_BULK);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, VIRTUAL_COM_PORT_DATA_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+  
+  bDeviceState = ATTACHED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetConfiguration.
+* Description    : Update the device state to configured.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_SetConfiguration(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Status_In.
+* Description    : Virtual COM Port Status In Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Status_In(void)
+{
+  if (Request == SET_LINE_CODING)
+  {
+    Request = 0;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Status_Out
+* Description    : Virtual COM Port Status OUT Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Status_Out(void)
+{}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Data_Setup
+* Description    : handle the data class specific requests
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Virtual_Com_Port_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t    *(*CopyRoutine)(uint16_t);
+
+  CopyRoutine = NULL;
+
+  if (RequestNo == GET_LINE_CODING)
+  {
+    if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+    {
+      CopyRoutine = Virtual_Com_Port_GetLineCoding;
+    }
+  }
+  else if (RequestNo == SET_LINE_CODING)
+  {
+    if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+    {
+      CopyRoutine = Virtual_Com_Port_SetLineCoding;
+    }
+    Request = SET_LINE_CODING;
+  }
+
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_NoData_Setup.
+* Description    : handle the no data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Virtual_Com_Port_NoData_Setup(uint8_t RequestNo)
+{
+
+  if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+  {
+    if (RequestNo == SET_COMM_FEATURE)
+    {
+      return USB_SUCCESS;
+    }
+    else if (RequestNo == SET_CONTROL_LINE_STATE)
+    {
+      return USB_SUCCESS;
+    }
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetConfigDescriptor.
+* Description    : get the configuration descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetStringDescriptor
+* Description    : Gets the string descriptors according to the needed index
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Get_Interface_Setting.
+* Description    : test the interface and the alternate setting according to the
+*                  supported one.
+* Input1         : uint8_t: Interface : interface number.
+* Input2         : uint8_t: AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+RESULT Virtual_Com_Port_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 1)
+  {
+    return USB_UNSUPPORT;
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetLineCoding.
+* Description    : send the linecoding structure to the PC host.
+* Input          : Length.
+* Output         : None.
+* Return         : Linecoding structure base address.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetLineCoding(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(linecoding);
+    return NULL;
+  }
+  return(uint8_t *)&linecoding;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetLineCoding.
+* Description    : Set the linecoding structure fields.
+* Input          : Length.
+* Output         : None.
+* Return         : Linecoding structure base address.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_SetLineCoding(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(linecoding);
+    return NULL;
+  }
+  return(uint8_t *)&linecoding;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_pwr.c
new file mode 100644
index 0000000..38b8915
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/VirtualComport_Loopback/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+              
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewd b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewd
new file mode 100644
index 0000000..26f0adf
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewd
@@ -0,0 +1,8092 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xE.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxE.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210B-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F103xG.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F10xxG.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xB.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32L152D-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32L152xD.ddf</state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L16xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F3xxx.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+  <configuration>
+    <name>STM32303C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>C-SPY</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>23</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCVariant</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>MemOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MemFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RunToEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RunToName</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCDDFArgumentProducer</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCDownloadSuppressDownload</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDownloadVerifyAll</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OCDynDriverList</name>
+          <state>STLINK_ID</state>
+        </option>
+        <option>
+          <name>OCLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>OCDownloadAttachToProgram</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>UseFlashLoader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CLowLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacFile2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CDevice</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>FlashLoadersV3</name>
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F30x.board</state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesSuppressCheck3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesPath3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OverrideDefFlashBoard</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesOffset1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesOffset3</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OCImagesUse1</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCImagesUse3</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDeviceConfigMacroFile</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ARMSIM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCSimDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCSimEnablePSP</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspOverrideConfig</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCSimPspConfigFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ANGEL_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCAngelHeartbeat</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommunication</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CAngelCommBaud</name>
+          <version>0</version>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CAngelCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ANGELTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoAngelLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AngelLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>GDBSERVER_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARROM_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRomLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CRomCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRomCommBaud</name>
+          <version>0</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IJET_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCIarProbeConfigFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetResetList</name>
+          <version>0</version>
+          <state>9</state>
+        </option>
+        <option>
+          <name>IjetHWResetDuration</name>
+          <state>300</state>
+        </option>
+        <option>
+          <name>IjetHWResetDelay</name>
+          <state>200</state>
+        </option>
+        <option>
+          <name>IjetPowerFromProbe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetPowerRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IjetDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>IjetInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTargetEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetJtagSpeedList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetProtocolRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetSwoPin</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>IjetSwoPrescalerList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetRestoreBreakpointsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IjetUpdateBreakpointsEdit</name>
+          <state>_call_main</state>
+        </option>
+        <option>
+          <name>RDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchCHKERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CatchDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>JLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>14</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>JLinkSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCJLinkDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCJLinkHWResetDelay</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JLinkInitialSpeed</name>
+          <state>32</state>
+        </option>
+        <option>
+          <name>CCDoJlinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCScanChainNonARMDevices</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkIRLength</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkCommRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>CCJLinkSpeedRadioV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCUSBDevice</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkResetList</name>
+          <version>6</version>
+          <state>7</state>
+        </option>
+        <option>
+          <name>CCJLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCORERESET</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchMMERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchNOCPERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchCHRERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchSTATERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchBUSERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchINTERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchHARDERR</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCatchDummy</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkScriptFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCJLinkUsbSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCTcpIpAlt</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJLinkTcpIpSerialNo</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCJLinkTraceSourceDummy</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>LMIFTDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>LmiftdiSpeed</name>
+          <state>500</state>
+        </option>
+        <option>
+          <name>CCLmiftdiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiftdiLogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLmiFtdiInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>MACRAIGOR_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>3</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>jtag</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TCPIP</name>
+          <state>aaa.bbb.ccc.ddd</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>DoEmuMultiTarget</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>EmuMultiTarget</name>
+          <state>0@ARM7TDMI</state>
+        </option>
+        <option>
+          <name>EmuHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CEmuCommBaud</name>
+          <version>0</version>
+          <state>4</state>
+        </option>
+        <option>
+          <name>CEmuCommPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>jtago</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>UnusedAddr</name>
+          <state>0x00800000</state>
+        </option>
+        <option>
+          <name>CCMacraigorHWResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCJTagBreakpointRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagDoUpdateBreakpoints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJTagUpdateBreakpoints</name>
+          <state>main</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMacraigorInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>PEMICRO_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCPEMicroAttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroInterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroResetDelay</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPEMicroJtagSpeed</name>
+          <state>#UNINITIALIZED#</state>
+        </option>
+        <option>
+          <name>CCJPEMicroShowSettings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>DoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCPEMicroUSBDevice</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPEMicroSerialPort</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCPEMicroTCPIP</name>
+          <state>10.0.0.1</state>
+        </option>
+        <option>
+          <name>CCPEMicroCommCmdLineProducer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDI_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDIDriverDll</name>
+          <state>Browse to your RDI driver</state>
+        </option>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>RDIJTAGJET_ID</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CRDILogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CRDILogFileEdit</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>CCRDIHWReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchReset</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchUndef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchSWI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchPrefetch</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchIRQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRDICatchFIQ</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>JTAGjetConfigure</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>STLINK_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>2</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceRadio</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCSTLinkInterfaceCmdLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSTLinkResetList</name>
+          <version>1</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCpuClockEdit</name>
+          <state>72.0</state>
+        </option>
+        <option>
+          <name>CCSwoClockAuto</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSwoClockEdit</name>
+          <state>2000</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>THIRDPARTY_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CThirdPartyDriverDll</name>
+          <state>Browse to your third-party driver</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CThirdPartyLogFileEditB</name>
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>
+        </option>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XDS100_ID</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OCDriverInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OCXDS100AttachSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>TIPackageOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TIPackage</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCXds100InterfaceList</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BoardFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <debuggerPlugins>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+    </debuggerPlugins>
+  </configuration>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewp
new file mode 100644
index 0000000..24ff4a0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.ewp
@@ -0,0 +1,6860 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>STM3210E-EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xE	ST STM32F103xE</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F10X_HD</state>
+          <state>USE_STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
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+          <version>1</version>
+          <state>1111111</state>
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+        <option>
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+          <state>1</state>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
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+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
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+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
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+          <state>$FILE_BNAME$.o</state>
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+          <state>100</state>
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+          <state>0</state>
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+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
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+        <wantNonLocal>1</wantNonLocal>
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+          <version>2</version>
+          <state>2</state>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM3210E-EVAL_VirtualCOMPort.bin</state>
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+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
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+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
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+      <archiveVersion>3</archiveVersion>
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+        <extensions></extensions>
+        <cmdline></cmdline>
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+      <archiveVersion>1</archiveVersion>
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+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+          <state>1</state>
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+          <name>IlinkConfigDefines</name>
+          <state></state>
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+          <state>1</state>
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+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>0</state>
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+          <name>IlinkLogAutoLibSelect</name>
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+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
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+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+          <name>IlinkOptInline</name>
+          <state>0</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
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+          <state>1</state>
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+          <state>0</state>
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+          <state></state>
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+          <state></state>
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+          <version>0</version>
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+        <version>0</version>
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+          <name>IarchiveOverride</name>
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+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
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+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
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+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
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+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM3210B-EVAL_VirtualCOMPort.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>VirtualCOMPort.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\stm32f10x_flash.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
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+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM3210E-EVAL_XL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM3210E-EVAL_XL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM3210E-EVAL_XL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM3210E-EVAL_XL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.40.1.53794</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F103xG	ST STM32F103xG</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F10X_XL</state>
+          <state>USE_STM3210E_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>STM32373C_EVAL</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>STM32373C_EVAL\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>STM32373C_EVAL\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>STM32373C_EVAL\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>4.41A</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.1.4445</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>STM32F373xC	ST STM32F373xC</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>39</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state>USE_STDPERIPH_DRIVER</state>
+          <state>STM32F37X</state>
+          <state>USE_STM32373C_EVAL</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>1111111</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL</state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
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+        <option>
+          <name>Includes</name>
+          <state>0</state>
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+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
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+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
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+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
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+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
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+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
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+        <option>
+          <name>AXRef</name>
+          <state>0</state>
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+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
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+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
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+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
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+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
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+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
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+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>STM32373C_EVAL_VirtualCOMPort.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
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+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>VirtualCOMPort.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
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+          <state>$PROJ_DIR$\stm32f37x_flash.icf</state>
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+          <state></state>
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+          <state>1</state>
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+          <state>1</state>
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+          <state>1</state>
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+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+          <state>1</state>
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+          <state>0</state>
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+          <state>1</state>
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+          <state></state>
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+        <option>
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+          <state>###Unitialized###</state>
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+          <state>STM32F303xC	ST STM32F303xC</state>
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+          <state></state>
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+          <state></state>
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+          <state></state>
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+          <state>1111111</state>
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+          <name>CCSignedPlainChar</name>
+          <state>1</state>
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+        <option>
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+          <state>$PROJ_DIR$\..\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\Common</state>
+          <state>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL</state>
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+          <state>.text</state>
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+          <configuration>STM32303C_EVAL</configuration>
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+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\iar\startup_stm32f10x_xl.s</name>
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+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM32373C_EVAL</configuration>
+          <configuration>STM32303C_EVAL</configuration>
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+        <configuration>STM3210E-EVAL_XL</configuration>
+        <configuration>STM32373C_EVAL</configuration>
+        <configuration>STM32303C_EVAL</configuration>
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+      <file>
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+      <file>
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+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
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+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</name>
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+      <file>
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+      <file>
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+      <file>
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+      <file>
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+      <file>
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+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\src\stm32f30x_usart.c</name>
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+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32L152-EVAL</configuration>
+      <configuration>STM32L152D-EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
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+      <file>
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+      <file>
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+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</name>
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+      <file>
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+      <file>
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+      <file>
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+      <file>
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+      <file>
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+    <name>STM32L1xx</name>
+    <excluded>
+      <configuration>STM3210E-EVAL</configuration>
+      <configuration>STM3210B-EVAL</configuration>
+      <configuration>STM3210E-EVAL_XL</configuration>
+      <configuration>STM32373C_EVAL</configuration>
+      <configuration>STM32303C_EVAL</configuration>
+    </excluded>
+    <group>
+      <name>CMSIS</name>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_hd.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_md.s</name>
+        <excluded>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Source\Templates\iar\startup_stm32l1xx_mdp.s</name>
+        <excluded>
+          <configuration>STM32L152-EVAL</configuration>
+          <configuration>STM32L152D-EVAL</configuration>
+        </excluded>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\src\system_stm32l1xx.c</name>
+        <excluded>
+          <configuration>STM3210B-EVAL</configuration>
+          <configuration>STM3210E-EVAL_XL</configuration>
+        </excluded>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152_EVAL</name>
+      <excluded>
+        <configuration>STM32L152D-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL\stm32l152_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L152D_EVAL</name>
+      <excluded>
+        <configuration>STM32L152-EVAL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL\stm32l152d_eval.c</name>
+      </file>
+    </group>
+    <group>
+      <name>STM32L1xx_StdPeriph_Driver</name>
+      <excluded>
+        <configuration>STM3210B-EVAL</configuration>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </excluded>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_i2c.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_pwr.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>
+      </file>
+      <file>
+        <name>$PROJ_DIR$\..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_usart.c</name>
+      </file>
+    </group>
+  </group>
+  <group>
+    <name>USB-FS-Device_Driver</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_core.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_int.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_regs.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\..\Libraries\STM32_USB-FS-Device_Driver\src\usb_sil.c</name>
+    </file>
+  </group>
+  <group>
+    <name>User</name>
+    <file>
+      <name>$PROJ_DIR$\..\src\hw_config.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\main.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\stm32_it.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_desc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_endp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_istr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_prop.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\src\usb_pwr.c</name>
+    </file>
+  </group>
+</project>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.eww b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.eww
new file mode 100644
index 0000000..f65e377
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/VirtualCOMPort.eww
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\VirtualCOMPort.ewp</path>
+  </project>
+  <batchBuild>
+    <batchDefinition>
+      <name>USB-Package-VCOMPort</name>
+      <member>
+        <project>VirtualCOMPort</project>
+        <configuration>STM3210B-EVAL</configuration>
+      </member>
+      <member>
+        <project>VirtualCOMPort</project>
+        <configuration>STM3210C-EVAL</configuration>
+      </member>
+      <member>
+        <project>VirtualCOMPort</project>
+        <configuration>STM3210E-EVAL</configuration>
+      </member>
+      <member>
+        <project>VirtualCOMPort</project>
+        <configuration>STM3210E-EVAL_XL</configuration>
+      </member>
+      <member>
+        <project>VirtualCOMPort</project>
+        <configuration>STM32L152-EVAL</configuration>
+      </member>
+    </batchDefinition>
+  </batchBuild>
+</workspace>
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f10x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f10x_flash.icf
new file mode 100644
index 0000000..6721a0d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f10x_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f37x_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f37x_flash.icf
new file mode 100644
index 0000000..a743cb4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32f37x_flash.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32l1xx_flash.icf b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32l1xx_flash.icf
new file mode 100644
index 0000000..8b7d80d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/EWARM/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0805FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvopt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvopt
new file mode 100644
index 0000000..0c4b8ae
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvopt
@@ -0,0 +1,2403 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>STM3210B-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210B-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103VB</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103VB</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM3210E-EVAL_XL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM3210E-EVAL_XL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F103ZG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F103ZG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UM0015BJE -O2190 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06416041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32L151xx_152xx_DS.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-U-O14 -O2062 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32L15x_128 -FS08000000 -FL020000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>STM32L152D-EVAL</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\STM32L152D-EVAL\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
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+        <uProt>0</uProt>
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+      <LintExecutable></LintExecutable>
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+    <ToolsetName>ARM-ADS</ToolsetName>
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+        <TabStop>8</TabStop>
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+        <SimDllName>SARMCM3.DLL</SimDllName>
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+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments></SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
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+        <tDlgPa></tDlgPa>
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+        <pMon>BIN\UL2CM3.DLL</pMon>
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+      <TargetDriverDllRegistry>
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+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
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+        </SetRegEntry>
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+      <FilenameWithoutPath>stm32l152d_eval.c</FilenameWithoutPath>
+    </File>
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+    <GroupName>STM32373C_EVAL</GroupName>
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+    </File>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvproj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvproj
new file mode 100644
index 0000000..ee49c4d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/MDK-ARM/VirtualCOMPort.uvproj
@@ -0,0 +1,12678 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
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+      <TargetName>STM3210B-EVAL</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
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+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)</FlashDriverDll>
+          <DeviceId>4223</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
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+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
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+          </TargetStatus>
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+          <OutputName>STM3210B-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
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+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\STM3210B-EVAL\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
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+          </BeforeCompile>
+          <BeforeMake>
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+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
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+            <Driver>BIN\UL2CM3.DLL</Driver>
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+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
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+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL\stm32373c_eval.c</FilePath>
+            </File>
+          </Files>
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+          <GroupName>STM32303C_EVAL</GroupName>
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+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>0</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+            </CommonProperty>
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+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
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+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL\stm32303c_eval.c</FilePath>
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+        <Group>
+          <GroupName>Doc</GroupName>
+          <Files>
+            <File>
+              <FileName>readme.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\readme.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
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+          <Device>STM32F103ZE</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)</FlashDriverDll>
+          <DeviceId>4216</DeviceId>
+          <RegisterFile>stm32f10x_lib.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F10x\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F10x\</DBRegisterFilePath>
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+            <NotGenerated>0</NotGenerated>
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+          <OutputName>STM3210E-EVAL</OutputName>
+          <CreateExecutable>1</CreateExecutable>
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+          <CreateHexFile>0</CreateHexFile>
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+          <HexFormatSelection>1</HexFormatSelection>
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+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
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+            <nStopU2X>0</nStopU2X>
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+          <IncludeLibraryModules></IncludeLibraryModules>
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+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F103ZE</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F103ZE</TargetDlgDllArguments>
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+        <DebugOption>
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+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
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+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
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+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
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+          <TargetDlls>
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+            <InitializationFile></InitializationFile>
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+        <Utilities>
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+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
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+            <RvctDeviceName></RvctDeviceName>
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+              <FilePath>..\src\hw_config.c</FilePath>
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+              <FilePath>..\src\main.c</FilePath>
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+              <FileName>usb_desc.c</FileName>
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+              <FilePath>..\src\usb_istr.c</FilePath>
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+              <FileName>usb_prop.c</FileName>
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+              <FilePath>..\src\usb_prop.c</FilePath>
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+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M4")ESEL ELITTLE FPU2</Cpu>
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+          <FlashDriverDll>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M4") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000)</FlashDriverDll>
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+          <Flash4></Flash4>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rapp b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rapp
new file mode 100644
index 0000000..765e056
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rapp
@@ -0,0 +1,1427 @@
+
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+		<Config Header="STM3210B_EVAL" >
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																																						
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																																						
+				</Section>
+																																																																																																																																																																																																																																																																																						
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STM3210B_EVAL;VECT_TAB_FLASH" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																													
+				</Section>
+																																																																																																																																																																																																																																																																															
+			</Set>
+																																																																																																																																																																																														
+		</Config>
+		<Config Header="STM3210E_EVAL" >
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STM3210E_EVAL;VECT_TAB_FLASH" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																													
+				</Section>
+																																																																																																																																																																																																																																																																															
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																																						
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																																						
+				</Section>
+				<Section Header="LIB" >
+					<Property Header="SMALLP" Value="1" Removable="1" />
+																																																																																																																																																																																																																																																																																																																																																				
+				</Section>
+																																																																																																																																																																																																																																																																								
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F103ZET6" />
+																																																																																																																																																																																																																																																																																																																																																																						
+				</Section>
+																																																																																																																																																																																																																																																																																						
+			</Set>
+																																																																																																																																																																																									
+		</Config>
+		<Config Header="STM3210E-EVAL" >
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F103ZET6" />
+																																																																																																																																																																																																																																																																																																																									
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																																																																																																																									
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																															
+				</Section>
+				<Section Header="LIB" >
+					<Property Header="SMALLP" Value="1" Removable="1" />
+																																																																																																																																																																																																																																																																																																																									
+				</Section>
+																																																																																																																																																																													
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F10X_HD;USE_STM3210E_EVAL" Removable="1" />
+																																																																																																																																																																																																																																																																																														
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																																																																																																																																											
+				</Section>
+																																																																																																																																																	
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210E-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210E-EVAL" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+																																													
+		</Config>
+		<Config Header="STM3210B-EVAL" >
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="STM32F10X_MD;USE_STDPERIPH_DRIVER;USE_STM3210B_EVAL" Removable="1" />
+																																																																																																																																																																																																																																																																																					
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																																																																												
+				</Section>
+				<Section Header="WARNINGS" >
+					<Property Header="CONSWARNINGS" Value="" Removable="1" />
+					<Property Header="SWITCHWARNINGS" Value="" Removable="1" />
+					<Property Header="SHADOWARNINGS" Value="" Removable="1" />
+					<Property Header="UNUSEDWARNINGS" Value="" Removable="1" />
+																																																																																																																																																																																		
+				</Section>
+																																																																																																
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																																																																																																																
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																																																																																																																						
+				</Section>
+				<Section Header="LIB" >
+					<Property Header="SMALLP" Value="1" Removable="1" />
+																																																																																																																																																																																																																																																																																																																
+				</Section>
+																																																																																																																																																																						
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210B-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210B-EVAL" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+																																													
+		</Config>
+		<Config Header="STM3210E-EVAL_XL" >
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM3210E-EVAL_XL" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F103ZGT6" />
+																																																																																																																												
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F10X_HD;USE_STM3210E_EVAL" Removable="1" />
+																																																																																																																												
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																																																																												
+				</Section>
+																																																																																																
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																												
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																																												
+				</Section>
+																																																																																																
+			</Set>
+																																													
+		</Config>
+		<Config Header="STM32L152-EVAL" >
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32L152-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32L152-EVAL" Removable="1" />
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Include;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152_EVAL" Removable="1" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="Target" >
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32L152VBT6" />
+																																																																																																	
+				</Section>
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																																								
+				</Section>
+																																																																				
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32L1XX_MD; USE_STM32L152_EVAL" Removable="1" />
+																																																																																																	
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																
+				</Section>
+												
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																																																	
+				</Section>
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																																																	
+				</Section>
+																																																																											
+			</Set>
+					
+		</Config>
+		<Config Header="STM32L152D-EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																																						
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32L152ZD" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32L1xx\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32L1xx_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32L152D_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+					<Property Header="OutDir" Value="STM32L152D_EVAL" Removable="1" />
+					<Property Header="ListDir" Value="STM32L152D_EVAL" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER; STM32L1XX_HD; USE_STM32L152D_EVAL" Removable="1" />
+																																																																						
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																																						
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="SCRIPTFILES" Value="Yes" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																																						
+				</Section>
+																																																						
+			</Set>
+																																			
+		</Config>
+		<Config Header="STM32373C_EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																													
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F373xC" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F37x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F37x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32373C_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32373-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32373-EVAL" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F37X;USE_STM32373C_EVAL" Removable="1" />
+																																																				
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																				
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="File" Value="" Removable="1" />
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+																									
+		</Config>
+		<Config Header="STM32F373C_EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																				
+				</Section>
+																																								
+			</Set>
+																									
+		</Config>
+		<Config Header="STM32303C_EVAL" >
+			<Set Header="Target" >
+				<Section Header="ToolSetARM" >
+					<Property Header="BuildToolSetARM" Value="ARM\GNU.config" />
+																																																				
+				</Section>
+				<Section Header="ProcessorARM" >
+					<Property Header="Processor" Value="STM32F303xC" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="ApplicationBuild" >
+				<Section Header="Directories" >
+					<Property Header="OutDir" Value="$(ApplicationDir)\STM32303-EVAL" Removable="1" />
+					<Property Header="ListDir" Value="$(ApplicationDir)\STM32303-EVAL" Removable="1" />
+					<Property Header="IncDir" Value="..\inc;..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include;..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc;..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc;..\..\..\Utilities\STM32_EVAL;..\..\..\Utilities\STM32_EVAL\Common;..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL;..\..\..\Libraries\CMSIS\Include" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="GCC" >
+				<Section Header="Defines" >
+					<Property Header="Defines" Value="USE_STDPERIPH_DRIVER;STM32F30X;USE_STM32303C_EVAL" Removable="1" />
+																																																				
+				</Section>
+				<Section Header="OPTIMIZE" >
+					<Property Header="Optimize" Value="-Os" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+			<Set Header="LD" >
+				<Section Header="Startup" >
+					<Property Header="DEFAULTSTARTUP" Value="No" Removable="1" />
+					<Property Header="File" Value="" Removable="1" />
+																																																				
+				</Section>
+				<Section Header="Scripts" >
+					<Property Header="StarterKitLimit" Value="No" Removable="1" />
+																																																				
+				</Section>
+																																								
+			</Set>
+																									
+		</Config>
+			
+	</Options>
+</ApplicationBuild>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rprj b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rprj
new file mode 100644
index 0000000..b8fcd58
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/RIDE/VirtualCOMPort.rprj
@@ -0,0 +1,4 @@
+
+<Project Header="Project 'VirtualCOMPort'" Path=".\VirtualCOMPort.rprj" Project="Yes" OutputFile="" sate="96" ActiveApp="VirtualCOMPort" >
+	<ApplicationBuild Header="VirtualCOMPort" Extern=".\VirtualCOMPort.rapp" Path=".\VirtualCOMPort.rapp" OutputFile=".\STM32303-EVAL\VirtualCOMPort.elf" Config="STM32303C_EVAL" sate="98" />
+</Project>
\ No newline at end of file
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/.project
new file mode 100644
index 0000000..5155ef6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/.project
@@ -0,0 +1,202 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
new file mode 100644
index 0000000..37a6b98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210B-EVAL/STM3210B-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210B-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210B-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210B-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210B-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..d6acb59
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.cproject
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210E-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103ze" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;..\..\..\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\CMSIS\Device\ST\STM32F10x\Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\Common&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;..\..\..\..\..\Utilities\STM32_EVAL\STM3210E_EVAL&quot;"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
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+									<listOptionValue builtIn="false" value="560"/>
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+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/STM32F10x_hd.lsl" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+		<cconfiguration id="com.tasking.config.arm.abs.release.1258418627">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.release.1258418627" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM3210B-EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.release.1258418627" name="Release" parent="com.tasking.config.arm.abs.release">
+					<folderInfo id="com.tasking.config.arm.abs.release.1258418627." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.release.1519878930" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.release">
+							<option id="com.tasking.arm.pluginVersion.753991160" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.116421631" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1935071203" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f103vb" valueType="string"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.release.1267471898" name="Release" osList="" superClass="com.tasking.arm.platform.abs.release"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Release}" id="com.tasking.arm.builder.abs.debug.1660652434" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.release.1575251102" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.release">
+								<option id="com.tasking.arm.cc.pr36858.667949791" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<inputType id="com.tasking.arm.cppInputType.2091871615" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.1848464199" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.1535867854" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.release.1696180280" name="Assembler" superClass="com.tasking.arm.as.abs.release">
+								<inputType id="com.tasking.arm.asmInputType.696605406" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.release.412256846" name="Linker" superClass="com.tasking.arm.lk.abs.release">
+								<inputType id="com.tasking.arm.lkObjInputType.244725194" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.407770682" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.project
new file mode 100644
index 0000000..3119c37
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
new file mode 100644
index 0000000..547d59a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/STM3210E-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM3210E-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM3210E-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
new file mode 100644
index 0000000..629bfcb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL/TASKING/STM32F10x_hd.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 512k;
+    map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 64k;
+    map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector( id = 2, optional, fill = "NMI_Handler" );  /* 2 Non Maskable Interrupt                */
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN_RX1_IRQHandler" );              // CAN RX1
+                        vector ( id = 38, optional, fill = "CAN_SCE_IRQHandler" );              // CAN SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/.project
new file mode 100644
index 0000000..c6a41a5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL_XL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM3210x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
new file mode 100644
index 0000000..a944802
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM3210E-EVAL_XL/TASKING/STM32F10x_XL.lsl
@@ -0,0 +1,165 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f103_cmsis.lsl
+//
+//  Version     :  @(#)stm32f103_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32f103.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 76
+
+
+#ifndef __STACK
+#  define __STACK                       8k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32F10x, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32f103flash
+{
+    mau = 8;
+    type = rom;
+    size = 0x100000;
+    map ( size = 0x100000, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32f103ram
+{
+    mau = 8;
+    type = ram;
+    size = 96k;
+    map ( size = 96k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                                                       /* Reset Handler                           */
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_IRQHandler" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );        // USB High Priority or CAN1 TX
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );       // USB LowPriority or CAN1 RX0
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );              // CAN1 SCE
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM9_IRQHandler" );             // TIM1 Break
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM10_IRQHandler" );              // TIM1 Update
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM11_IRQHandler" );         // TIM1 Trigger and Commutation
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup from suspend
+                        vector ( id = 59, optional, fill = "TIM8_BRK_TIM12_IRQHandler" );             // TIM8 Break
+                        vector ( id = 60, optional, fill = "TIM8_UP_TIM13_IRQHandler" );              // TIM8 Update
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_TIM14_IRQHandler" );         // TIM8 Trigger and Commutation
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3
+                        vector ( id = 64, optional, fill = "FSMC_IRQHandler" );                 // FSMC
+                        vector ( id = 65, optional, fill = "SDIO_IRQHandler" );                 // SDIO
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5
+                        vector ( id = 70, optional, fill = "TIM6_IRQHandler" );                 // TIM6
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel1
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel2
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel3
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" );      // DMA2 Channel4 and DMA2 Channel5
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.cproject
new file mode 100644
index 0000000..2750b9d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.cproject
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.tasking.config.arm.abs.debug.2044455393">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.arm.abs.debug.2044455393" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="abs" artifactName="STM32303C_EVAL" buildArtefactType="com.tasking.arm.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.arm.buildArtefactType.elf" cleanCommand="&quot;${PRODDIR}/bin/rm&quot; -rf" description="" id="com.tasking.config.arm.abs.debug.2044455393" name="Debug" parent="com.tasking.config.arm.abs.debug">
+					<folderInfo id="com.tasking.config.arm.abs.debug.2044455393." name="/" resourcePath="">
+						<toolChain id="com.tasking.arm.abs.debug.315882766" name="TASKING VX-toolset for ARM" superClass="com.tasking.arm.abs.debug">
+							<option id="com.tasking.arm.pluginVersion.306560835" name="Plugin version" superClass="com.tasking.arm.pluginVersion" value="1.88.0.0" valueType="string"/>
+							<option id="com.tasking.arm.prodDir.527888595" name="Product directory:" superClass="com.tasking.arm.prodDir" value="${eclipse_home}/.." valueType="string"/>
+							<option id="com.tasking.arm.cpu.1659227005" name="Processor:" superClass="com.tasking.arm.cpu" value="stm32f303vc" valueType="string"/>
+							<option id="com.tasking.arm.globalOptions.endianness.847552914" name="Endianness:" superClass="com.tasking.arm.globalOptions.endianness" value="com.tasking.arm.globalOptions.endianness.little" valueType="enumerated"/>
+							<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF" id="com.tasking.arm.platform.abs.debug.2077143327" name="Debug" osList="" superClass="com.tasking.arm.platform.abs.debug"/>
+							<builder buildPath="${workspace_loc:/STM3210B-EVAL/Debug}" id="com.tasking.arm.builder.abs.debug.1207760117" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING ARM Makefile generator" parallelBuildOn="true" parallelizationNumber="-1" superClass="com.tasking.arm.builder.abs.debug"/>
+							<tool id="com.tasking.arm.cc.abs.debug.1657066278" name="C/C++ Compiler" superClass="com.tasking.arm.cc.abs.debug">
+								<option id="com.tasking.arm.cc.pr36858.1629322841" name="workaround for PR36858" superClass="com.tasking.arm.cc.pr36858" value="true" valueType="string"/>
+								<option id="com.tasking.arm.cc.includePaths.449008655" name="Include paths" superClass="com.tasking.arm.cc.includePaths" valueType="includePath">
+									<listOptionValue builtIn="false" value="..\..\.\..\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\CMSIS\Device\ST\STM32F30x\Include"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32_USB-FS-Device_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Libraries\STM32F30x_StdPeriph_Driver\inc"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\Common"/>
+									<listOptionValue builtIn="false" value="..\..\.\..\..\..\Utilities\STM32_EVAL\STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.definedSymbols.2139466164" name="Defined symbols" superClass="com.tasking.arm.cc.definedSymbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.tasking.arm.cc.optimize.1365289574" name="Optimization level:" superClass="com.tasking.arm.cc.optimize" value="com.tasking.arm.cc.optimize.3" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.tradeoff.1958267302" name="Trade-off between speed and size:" superClass="com.tasking.arm.cc.tradeoff" value="com.tasking.arm.cc.tradeoff.4" valueType="enumerated"/>
+								<option id="com.tasking.arm.cc.globalTypeChecking.1184544748" name="Perform global type checking on C code" superClass="com.tasking.arm.cc.globalTypeChecking" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.nowarning.398961799" name="Suppress C compiler warnings" superClass="com.tasking.arm.cc.nowarning" valueType="stringList">
+									<listOptionValue builtIn="false" value="588"/>
+									<listOptionValue builtIn="false" value="549"/>
+									<listOptionValue builtIn="false" value="557"/>
+									<listOptionValue builtIn="false" value="508"/>
+									<listOptionValue builtIn="false" value="560"/>
+								</option>
+								<option id="com.tasking.arm.cc.defaultHeaderFile.1126538551" name="Include CMSIS device register definition header file" superClass="com.tasking.arm.cc.defaultHeaderFile" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.cmsisIncludePaths.1232400927" name="Add CMSIS include paths" superClass="com.tasking.arm.cc.cmsisIncludePaths" value="true" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.codeGeneration.useFpu.1037423562" name="Use FPU" superClass="com.tasking.arm.cc.codeGeneration.useFpu" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.cc.additionalOptions.2089822954" name="Additional options:" superClass="com.tasking.arm.cc.additionalOptions" value="" valueType="string"/>
+								<option id="com.tasking.arm.cc.codeGeneration.Thumb.51606921" name="Use Thumb instruction set" superClass="com.tasking.arm.cc.codeGeneration.Thumb" value="true" valueType="boolean"/>
+								<inputType id="com.tasking.arm.cppInputType.78394475" name="C++" superClass="com.tasking.arm.cppInputType"/>
+								<inputType id="com.tasking.arm.cpp.cInputType.609856589" name="C" superClass="com.tasking.arm.cpp.cInputType"/>
+								<inputType id="com.tasking.arm.cc.msInputType.765887363" name="MS" superClass="com.tasking.arm.cc.msInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.as.abs.debug.1696826359" name="Assembler" superClass="com.tasking.arm.as.abs.debug">
+								<option id="com.tasking.arm.as.nowarnings.1345499014" name="Suppress all warnings" superClass="com.tasking.arm.as.nowarnings" value="false" valueType="boolean"/>
+								<option id="com.tasking.arm.as.definedSymbols.1925183717" name="Defined symbols" superClass="com.tasking.arm.as.definedSymbols"/>
+								<option id="com.tasking.arm.as.includePaths.762676103" name="Include paths" superClass="com.tasking.arm.as.includePaths"/>
+								<option id="com.tasking.arm.as.additionalOptions.1602992317" name="Additional options:" superClass="com.tasking.arm.as.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.asmInputType.1662245119" name="ASM" superClass="com.tasking.arm.asmInputType"/>
+							</tool>
+							<tool id="com.tasking.arm.lk.abs.debug.666839530" name="Linker" superClass="com.tasking.arm.lk.abs.debug">
+								<option id="com.tasking.arm.lk.lslFile.578724675" name="Linker script file:" superClass="com.tasking.arm.lk.lslFile" value="../TASKING/stm32f30x.lsl" valueType="string"/>
+								<option id="com.tasking.arm.lk.library.1866270609" name="Libraries" superClass="com.tasking.arm.lk.library"/>
+								<option id="com.tasking.arm.lk.libraryDirectory.122337355" name="Library search path" superClass="com.tasking.arm.lk.libraryDirectory"/>
+								<option id="com.tasking.arm.lk.additionalOptions.2095335915" name="Additional options:" superClass="com.tasking.arm.lk.additionalOptions" value="" valueType="string"/>
+								<inputType id="com.tasking.arm.lkObjInputType.1921927729" name="OBJ" superClass="com.tasking.arm.lkObjInputType"/>
+								<inputType id="com.tasking.arm.lkLibInputType.1525417255" name="LIB" superClass="com.tasking.arm.lkLibInputType"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="com.tasking.toolInfo">
+				<toolInfo>TASKING VX-toolset for ARM Cortex: object linker (TRIAL VERS v4.3r1 Build 142</toolInfo>
+				<toolInfo>TASKING program builder v4.3r1 Build 068</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: assembler v4.3r1 Build 148</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: control program v4.3r1 Build 120</toolInfo>
+				<toolInfo>TASKING VX-toolset for ARM Cortex: C compiler (TRIAL VERSION v4.3r1 Build 683</toolInfo>
+			</storageModule>
+			<storageModule addStartupFiles="false" moduleId="com.tasking.processor" updateRefProjects="true"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210B-EVAL.com.tasking.arm.target.abs.491846486" name="TASKING ARM Application" projectType="com.tasking.arm.target.abs"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.release.1258418627;com.tasking.config.arm.abs.release.1258418627.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.tasking.config.arm.abs.debug.2044455393;com.tasking.config.arm.abs.debug.2044455393.">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.arm.TskARMScannerInfo"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.arm.clanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.arm.cpplanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.arm.cpplanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/STM3210B-EVAL"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.launch
new file mode 100644
index 0000000..4635ffb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+  <booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+  <stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+  <booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+  <stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+  <stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+  <stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+  <stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+  <stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+  <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+  <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+  <booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+    <listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+  <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+    <listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
new file mode 100644
index 0000000..3ccf590
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32303C_EVAL/TASKING/stm32f30x.lsl
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f30x.lsl
+//
+//  Version     :  @(#)stm32f30x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F30x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F30x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       6k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+
+memory STM32F30x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE - 8k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F30x_SRAM8k
+{
+    mau = 8;
+    type = ram;
+    size = 8k;
+    priority = 1;
+    map ( size = 8k, dest_offset=0x10000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2 interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" );               // ADC1 and ADC2 global interrupts
+                        vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" );       // USB Device High Priority or CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" );      // USB Device Low Priority or CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM1_BRK_TIM15_IRQHandler" );       // TIM1 Break irq and TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM1_UP_TIM16_IRQHandler" );        // TIM1 Update irq and TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM1_TRG_COM_TIM17_IRQHandler" );   // TIM1 Trigger and Commutation irqs and TIM17 global irq
+                        vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" );              // TIM1 Capture Compare
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup interrupt
+                        vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" );             // TIM8 Break interrupt
+                        vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" );              // TIM8 Update interrupt
+                        vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" );         // TIM8 trigger and Comm. interrupt
+                        vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" );              // TIM8 Capture Compare interrupt
+                        vector ( id = 63, optional, fill = "ADC3_IRQHandler" );                 // ADC3 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 68, optional, fill = "UART4_IRQHandler" );                // UART4 global interrupt
+                        vector ( id = 69, optional, fill = "UART5_IRQHandler" );                // UART5 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC_IRQHandler" );             // TIM6 glbl irq, DAC1 and DAC2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "ADC4_IRQHandler" );                 // ADC4 global interrupt
+                        vector ( id = 80, optional, fill = "COMP1_2_3_IRQHandler" );            // COMP1, COMP2 and COMP3 global interrupt
+                        vector ( id = 81, optional, fill = "COMP4_5_6_IRQHandler" );            // COMP5, COMP6 and COMP4 global interrupt
+                        vector ( id = 82, optional, fill = "COMP7_IRQHandler" );                // COMP7 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt  remap
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt  remap
+                        vector ( id = 92, optional, fill = "USBWakeUp_RMP_IRQHandler" );        // USB Wakeup Interrupt remap
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/.project
new file mode 100644
index 0000000..23f3d84
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/.project
@@ -0,0 +1,197 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C_EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>PARENT-1-PROJECT_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x/STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
new file mode 100644
index 0000000..6c766c6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/STM32373C_EVAL.launch
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32373C-Eval board"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32f10x.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32373C_EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32373C_EVAL"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32373C_EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
new file mode 100644
index 0000000..d8ba5b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32373C_EVAL/TASKING/stm32f37x.lsl
@@ -0,0 +1,200 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32f37x.lsl
+//
+//  Version     :  @(#)stm32f37x.lsl    1.1 12/07/27
+//
+//  Description :  LSL file for the STMicroelectronics STM32F37x
+//
+//  Copyright 2012 Altium BV     
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32F37x, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMSIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 98
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x20000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  256k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   32k
+#endif
+
+memory STM32F37x_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32F37x_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    priority = 2;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Define the vector table for CMSIS
+//
+#ifdef __CMSIS_VECTORS
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );                      // NMI Handler
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );                // Hard Fault Handler
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );                // MPU Fault Handler
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );                 // Bus Fault Handler
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );               // Usage Fault Handler
+                        vector ( id = 11, optional, fill = "SVC_Handler" );                     // SVCall Handler
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );                // Debug Monitor Handler
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );                  // PendSV Handler
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );                 // SysTick Handler
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper amd TimeStanp through EXTI
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC Wakeup through the EXTI line
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash global interrupt
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC global interrupt
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0 interrupt
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1 interrupt
+                        vector ( id = 24, optional, fill = "EXTI2_TS_IRQHandler" );                // EXTI2_TS_IRQHandler interrupt
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3 interrupt
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4 interrupt
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );        // DMA1 Channel 1 global interrupt
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );        // DMA1 Channel 2 global interrupt
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );        // DMA1 Channel 3 global interrupt
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );        // DMA1 Channel 4 global interrupt
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );        // DMA1 Channel 5 global interrupt
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );        // DMA1 Channel 6 global interrupt
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );        // DMA1 Channel 7 global interrupt
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );                 // ADC1 interrupts
+                        vector ( id = 35, optional, fill = "CAN1_TX_IRQHandler" );              // CAN1 TX interrupts
+                        vector ( id = 36, optional, fill = "CAN1_RX0_IRQHandler" );             // CAN1 RX0 interrupts
+                        vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" );             // CAN1 RX1 interrupt
+                        vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" );             // CAN1 SCE interrupt
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5 interrupts
+                        vector ( id = 40, optional, fill = "TIM15_IRQHandler" );                // TIM15 global interrupt
+                        vector ( id = 41, optional, fill = "TIM16_IRQHandler" );                // TIM16 global interrupt
+                        vector ( id = 42, optional, fill = "TIM17_IRQHandler" );                // TIM17 global interrupt
+                        vector ( id = 43, optional, fill = "TIM118_DAC2_IRQHandler" );          // TIM18 global Interrupt and DAC2 underrun Interrupt
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2 global interrupt
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3 global interrupt
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4 global interrupt
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1 global interrupt
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2 global interrupt
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1 global interrupt
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2 global interrupt
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3 global interrupt
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10 interrupts
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );            // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "CEC_IRQHandler" );                  // CEC interrupt
+                        vector ( id = 59, optional, fill = "TIM12_IRQHandler" );                // TIM12 global interrupt
+                        vector ( id = 60, optional, fill = "TIM13_IRQHandler" );                // TIM13 global interrupt
+                        vector ( id = 61, optional, fill = "TIM14_IRQHandler" );                // TIM14 global interrupt
+                        vector ( id = 66, optional, fill = "TIM5_IRQHandler" );                 // TIM5 global interrupt
+                        vector ( id = 67, optional, fill = "SPI3_IRQHandler" );                 // SPI3 global interrupt
+                        vector ( id = 70, optional, fill = "TIM6_DAC1_IRQHandler" );            // TIM6 glbl irq, DAC1 CH1 & CH2 underrun err irqs
+                        vector ( id = 71, optional, fill = "TIM7_IRQHandler" );                 // TIM7 global interrupt
+                        vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" );        // DMA2 Channel 1 global interrupt
+                        vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" );        // DMA2 Channel 2 global interrupt
+                        vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" );        // DMA2 Channel 3 global interrupt
+                        vector ( id = 75, optional, fill = "DMA2_Channel4_IRQHandler" );        // DMA2 Channel 4 global interrupt
+                        vector ( id = 76, optional, fill = "DMA2_Channel5_IRQHandler" );        // DMA2 Channel 5 global interrupt
+                        vector ( id = 77, optional, fill = "SDADC1_IRQHandler" );               // ADC Sigma Delta 1 global Interrupt
+                        vector ( id = 78, optional, fill = "SDADC2_IRQHandler" );               // ADC Sigma Delta 2 global Interrupt
+                        vector ( id = 79, optional, fill = "SDADC3_IRQHandler" );               // ADC Sigma Delta 3 global Interrupt
+                        vector ( id = 80, optional, fill = "COMP_IRQHandler" );                 // COMP1 and COMP2 global interrupt
+                        vector ( id = 90, optional, fill = "USB_HP_IRQHandler" );               // USB High Priority global Interrupt
+                        vector ( id = 91, optional, fill = "USB_LP_IRQHandler" );               // USB Low Priority global Interrupt
+                        vector ( id = 92, optional, fill = "USBWakeUp_IRQHandler" );            // USB Wakeup Interrupt
+                        vector ( id = 94, optional, fill = "TIM19_IRQHandler" );                // TIM19 global Interrupt
+                        vector ( id = 97, optional, fill = "FPU_IRQHandler" );                  // Floating point Interrupt
+                }
+}
+#endif /* __CMSIS_VECTORS */
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/.project
new file mode 100644
index 0000000..69a8de0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/.project
@@ -0,0 +1,207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152_EVAL/stm32l152_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
new file mode 100644
index 0000000..d494039
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/STM32L152-EVAL.launch
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="J-Link over USB (JTAG)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="dijlinkarm"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="JTAG"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
new file mode 100644
index 0000000..909c5b0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152-EVAL/TASKING/stm32l1xx_md.lsl
@@ -0,0 +1,151 @@
+////////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx_cmsis.lsl
+//
+//  Version     :  @(#)stm32l1xx_cmsis.lsl      1.2  09/06/04
+//
+//  Description :  LSL file for the STMicroelectronics STM32F103, CMSIS version
+//
+//  Copyright 2009 Altium BV     
+//
+//  NOTE:
+//      This file is derived from cm3.lsl and stm32l1xx.lsl.
+//      It is assumed that the user works with the ARMv7M architecture.
+//      Other architectures will not work with this lsl file.
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// We do not want the vectors as defined in arm_arch.lsl
+//
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                 84
+
+
+#ifndef __STACK
+#  define __STACK                       2k
+#endif
+#ifndef __HEAP
+#  define __HEAP                        1k
+#endif
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+#ifndef __XVWBUF
+#define __XVWBUF                        256             /* buffer used by CrossView */
+#endif
+
+#include <arm_arch.lsl>
+
+////////////////////////////////////////////////////////////////////////////
+//
+// In the STM32L1xx, 3 different boot modes can be selected
+// - User Flash memory is selected as boot space
+// - SystemMemory is selected as boot space
+// - Embedded SRAM is selected as boot space
+//
+// This aliases the physical memory associated with each boot mode to Block
+// 000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+// the related memory (Flash memory or SRAM) is still accessible at its
+// original memory space.
+//
+// If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+memory stm32l1xflash
+{
+    mau = 8;
+    type = rom;
+    size = 128k;
+    map ( size = 128k, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory stm32l1xram
+{
+    mau = 8;
+    type = ram;
+    size = 16k;
+    map ( size = 16k, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandle" );               // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );                  // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..5cca315
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/.project
@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.tasking.arm.TskManagedBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.tasking.arm.target</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>WORKSPACE_LOC/.metadata/Link</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32l1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32l1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_sdio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
new file mode 100644
index 0000000..26462e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/STM32L152D-EVAL.launch
@@ -0,0 +1,48 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.tasking.cdt.launch.localCLaunch">
+<booleanAttribute key="com.tasking.debug.cdt.core.BREAK_ON_EXIT" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.CACHE_TARGET_ACCESS" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.COMMUNICATION" value="ST-LINK over USB (SWD)"/>
+<stringAttribute key="com.tasking.debug.cdt.core.CONFIGURATION" value="Default"/>
+<stringAttribute key="com.tasking.debug.cdt.core.DILOGCALLBACK_LOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.DOWNLOAD" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.FSS_ROOT" value="${project_loc}\${build_config}"/>
+<stringAttribute key="com.tasking.debug.cdt.core.GDILOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.GOTO_MAIN" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.HISTORY_BUFFER_ENABLED" value="false"/>
+<stringAttribute key="com.tasking.debug.cdt.core.MSGLOG_FILE_NAME" value=""/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PROGRAM_FLASH" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.PSM_ENABLED" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.RESET_TARGET" value="true"/>
+<stringAttribute key="com.tasking.debug.cdt.core.TARGET" value="STMicroelectronics STM32L152D-EVAL"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.TARGET_POLLING" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.USE_MDF_FILE" value="false"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.VERIFY" value="true"/>
+<booleanAttribute key="com.tasking.debug.cdt.core.linkToProject" value="true"/>
+<stringAttribute key="debugger_configuration.debug_instrument_module" value="distlink"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_mirror_address" value="0x0"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_monitor" value="fstm32l1xx.sre"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_sector_buffer_size" value="4096"/>
+<stringAttribute key="debugger_configuration.gdi.flash.flash_workspace" value="0x20000000"/>
+<stringAttribute key="debugger_configuration.gdi.resource.hwdiarm.protocol" value="SWD"/>
+<stringAttribute key="debugger_configuration.general.kdi_orti_file" value=""/>
+<stringAttribute key="debugger_configuration.general.ksm_sharedlib" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="com.tasking.debug.cdt.core.CDebugger"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_REGISTER_BOOKKEEPING" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.launch.ENABLE_VARIABLE_BOOKKEEPING" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${project_loc}\${build_config}\STM32L152D-EVAL.abs"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
new file mode 100644
index 0000000..77979b6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TASKING/STM32L152D-EVAL/TASKING/stm32l1xx_hd.lsl
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////////
+//
+//  File        :  stm32l1xx.lsl
+//
+//  Version     :  @(#)stm32l1xx.lsl    1.5  11/06/30
+//
+//  Description :  LSL file for the STMicroelectronics STM32L1xx
+//
+//  Copyright 2010-2011 Altium BV
+//  
+//  Macros specific to control this LSL file
+//
+//  __MEMORY            Define this macro to suppress definition of on-chip 
+//                      memory. Must be defined when you want to define on-chip
+//                      in your project's LSL file.
+//  __FLASH_SIZE        Specifies the size of flash memory to be allocated
+//  __SRAM_SIZE         Specifies the size of the SRAM memory to be allocated
+//  __EEPROM_SIZE       Specifies the size of the EEPROM memory to be allocated
+//  __NO_DEFAULT_AUTO_VECTORS
+//                      When enabled the interrupt vector table will not be 
+//                      generated
+//  __VECTOR_TABLE_RAM_COPY
+//                      Define this macro to enable copying the vector table 
+//                      at startup from ROM to RAM.
+//  __VECTOR_TABLE_ROM_ADDR
+//                      Specify the vector table address in ROM
+//  __VECTOR_TABLE_RAM_ADDR
+//                      Specify the vector table address in RAM when the the
+//                      it is copied from ROM to RAM (__VECTOR_TABLE_RAM_COPY)
+//
+//  See arm_arch.lsl for more available macros.
+//
+//  Notes:
+//  In the STM32L1xx, 3 different boot modes can be selected
+//  - User Flash memory is selected as boot space
+//  - SystemMemory is selected as boot space
+//  - Embedded SRAM is selected as boot space
+//
+//  This aliases the physical memory associated with each boot mode to Block
+//  000 (0x00000000 boot memory). Even when aliased in the boot memory space,
+//  the related memory (Flash memory or SRAM) is still accessible at its
+//  original memory space.
+//
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __NO_DEFAULT_AUTO_VECTORS
+// Suppress the vectors as defined arm_arch.lsl, because we define our 
+// own vectors for CMIS
+#define __CMSIS_VECTORS                 1
+#define __NO_DEFAULT_AUTO_VECTORS       1
+#define __NR_OF_VECTORS                73
+#endif
+
+#ifndef __VECTOR_TABLE_ROM_ADDR
+#  define __VECTOR_TABLE_ROM_ADDR       0x08000000
+#endif
+
+#ifndef __VECTOR_TABLE_RAM_ADDR
+#  define __VECTOR_TABLE_RAM_ADDR       0x00000000
+#endif
+
+
+#ifndef __STACK
+#  define __STACK                       4k
+#endif
+
+#ifndef __HEAP
+#  define __HEAP                        2k
+#endif
+
+#include <arm_arch.lsl>
+
+//
+//  If no memory is defined yet use the following memory settings
+//
+#ifndef __MEMORY
+
+// Specify default size for Flash and SRAM
+#ifndef __FLASH_SIZE
+#  define __FLASH_SIZE  384k
+#endif
+#ifndef __SRAM_SIZE
+#  define __SRAM_SIZE   48k
+#endif
+#ifndef __EEPROM_SIZE
+#  define __EEPROM_SIZE 4k
+#endif
+
+memory STM32L1xx_Flash
+{
+    mau = 8;
+    type = rom;
+    size = __FLASH_SIZE;
+    map ( size = __FLASH_SIZE, dest_offset=0x08000000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_EEPROM
+{
+    mau = 8;
+    type = reserved rom;
+    size = __EEPROM_SIZE;
+    map ( size = __EEPROM_SIZE, dest_offset=0x08080000, dest=bus:ARM:local_bus);
+}
+
+memory STM32L1xx_SRAM
+{
+    mau = 8;
+    type = ram;
+    size = __SRAM_SIZE;
+    map ( size = __SRAM_SIZE, dest_offset=0x20000000, dest=bus:ARM:local_bus);
+}
+
+#endif /* __MEMORY */
+
+
+//
+// Custom vector table defines interrupts according to CMSIS standard
+//
+# if defined(__CPU_ARMV7M__)
+section_setup ::linear
+{
+                // vector table with handler addresses
+                vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_RUN_ADDR,
+                                              template = ".text.handler_address",
+                                              template_symbol = "_lc_vector_handler",
+                                              vector_prefix = "_vector_",
+                                              __VECTOR_TABLE_COPY_ATTRIBUTE 
+                                              fill = loop,
+                                              no_inline
+                                            )
+                {
+                        vector ( id = 0, fill = "_lc_ub_stack" );                               // Top of Stack
+                        vector ( id = 1, fill = "Reset_Handler" );                              // Reset Handler
+                        vector ( id = 2, optional, fill = "NMI_Handler" );
+                        vector ( id = 3, optional, fill = "HardFault_Handler" );
+                        vector ( id = 4, optional, fill = "MemManage_Handler" );
+                        vector ( id = 5, optional, fill = "BusFault_Handler" );
+                        vector ( id = 6, optional, fill = "UsageFault_Handler" );
+                        vector ( id = 11, optional, fill = "SVC_Handler" );
+                        vector ( id = 12, optional, fill = "DebugMon_Handler" );
+                        vector ( id = 14, optional, fill = "PendSV_Handler" );
+                        vector ( id = 15, optional, fill = "SysTick_Handler" );
+
+                        // External Interrupts :
+                        vector ( id = 16, optional, fill = "WWDG_IRQHandler" );                 // Window Watchdog
+                        vector ( id = 17, optional, fill = "PVD_IRQHandler" );                  // PVD through EXTI Line detect
+                        vector ( id = 18, optional, fill = "TAMPER_STAMP_IRQHandler" );         // Tamper
+                        vector ( id = 19, optional, fill = "RTC_WKUP_IRQHandler" );             // RTC
+                        vector ( id = 20, optional, fill = "FLASH_IRQHandler" );                // Flash
+                        vector ( id = 21, optional, fill = "RCC_IRQHandler" );                  // RCC
+                        vector ( id = 22, optional, fill = "EXTI0_IRQHandler" );                // EXTI Line 0
+                        vector ( id = 23, optional, fill = "EXTI1_IRQHandler" );                // EXTI Line 1
+                        vector ( id = 24, optional, fill = "EXTI2_IRQHandler" );                // EXTI Line 2
+                        vector ( id = 25, optional, fill = "EXTI3_IRQHandler" );                // EXTI Line 3
+                        vector ( id = 26, optional, fill = "EXTI4_IRQHandler" );                // EXTI Line 4
+                        vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" );          // DMA Channel 1
+                        vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" );          // DMA Channel 2
+                        vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" );          // DMA Channel 3
+                        vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" );          // DMA Channel 4
+                        vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" );          // DMA Channel 5
+                        vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" );          // DMA Channel 6
+                        vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" );          // DMA Channel 7
+                        vector ( id = 34, optional, fill = "ADC1_IRQHandler" );               // ADC1_IRQHandler
+                        vector ( id = 35, optional, fill = "USB_HP_IRQHandler" );              //  USB_HP_IRQHandler
+                        vector ( id = 36, optional, fill = "USB_LP_IRQHandler" );             // USB_LP_IRQHandler
+                        vector ( id = 37, optional, fill = "DAC_IRQHandler" );              // CAN1 RX1
+                        vector ( id = 38, optional, fill = "COMP_IRQHandler" );              // COMP_IRQHandler
+                        vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" );              // EXTI Line 9..5
+                        vector ( id = 40, optional, fill = "LCD_IRQHandler" );             // LCD_IRQHandler
+                        vector ( id = 41, optional, fill = "TIM9_IRQHandler" );              // TIM9_IRQHandler
+                        vector ( id = 42, optional, fill = "TIM10_IRQHandler" );         // TIM10_IRQHandler
+                        vector ( id = 43, optional, fill = "TIM11_IRQHandler" );              // TIM11_IRQHandler
+                        vector ( id = 44, optional, fill = "TIM2_IRQHandler" );                 // TIM2
+                        vector ( id = 45, optional, fill = "TIM3_IRQHandler" );                 // TIM3
+                        vector ( id = 46, optional, fill = "TIM4_IRQHandler" );                 // TIM4
+                        vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" );              // I2C1 Event
+                        vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" );              // I2C1 Error
+                        vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" );              // I2C2 Event
+                        vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" );              // I2C2 Error
+                        vector ( id = 51, optional, fill = "SPI1_IRQHandler" );                 // SPI1
+                        vector ( id = 52, optional, fill = "SPI2_IRQHandler" );                 // SPI2
+                        vector ( id = 53, optional, fill = "USART1_IRQHandler" );               // USART1
+                        vector ( id = 54, optional, fill = "USART2_IRQHandler" );               // USART2
+                        vector ( id = 55, optional, fill = "USART3_IRQHandler" );               // USART3
+                        vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" );            // EXTI Line 15..10
+                        vector ( id = 57, optional, fill = "RTC_Alarm_IRQHandler" );             // RTC Alarm through EXTI Line
+                        vector ( id = 58, optional, fill = "USB_FS_WKUP_IRQHandler" );          // USB_FS_WKUP_IRQHandler
+                        vector ( id = 59, optional, fill = "TIM6_IRQHandler" );                 // TIM6_IRQHandler
+                        vector ( id = 60, optional, fill = "TIM7_IRQHandler" );                 // TIM7_IRQHandler
+                        vector ( id = 61, optional, fill = "SDIO_IRQHandler" );                 // SDIO_IRQHandler
+                        vector ( id = 62, optional, fill = "TIM5_IRQHandler" );                 //TIM5_IRQHandler
+                        vector ( id = 63, optional, fill = "SPI3_IRQHandler" );                 //SPI3_IRQHandler
+                        vector ( id = 64, optional, fill = "UART4_IRQHandler" );                //UART4_IRQHandler
+                        vector ( id = 65, optional, fill = "UART5_IRQHandler" );                //UART5_IRQHandler
+                        vector ( id = 66, optional, fill = "DMA2_Channel1_IRQHandler" );        //DMA2_Channel1_IRQHandler
+                        vector ( id = 67, optional, fill = "DMA2_Channel2_IRQHandler" );        //DMA2_Channel2_IRQHandler
+                        vector ( id = 68, optional, fill = "DMA2_Channel3_IRQHandler" );        //DMA2_Channel3_IRQHandler
+                        vector ( id = 69, optional, fill = "DMA2_Channel4_IRQHandler" );        //DMA2_Channel4_IRQHandler
+                        vector ( id = 70, optional, fill = "DMA2_Channel5_IRQHandler" );        //DMA2_Channel5_IRQHandler
+                        vector ( id = 71, optional, fill = "AES_IRQHandler" );                  //AES_IRQHandler
+                        vector ( id = 72, optional, fill = "COMP_ACQ_IRQHandler" );             //Comparator Channel Acquisition
+                                              
+                }
+}
+# endif
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.project
new file mode 100644
index 0000000..153ec17
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.project
@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210B-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210B_EVAL/stm3210b_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_md.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..f6eb6e4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210B-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:23:19 GMT+01:00 2012
+BOARD=STM3210B-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.cproject
new file mode 100644
index 0000000..ccb0855
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.cproject
@@ -0,0 +1,353 @@
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+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="makefileGenerator">
+							<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/${specs_file}&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'g++ -E -P -v -dD &quot;${plugin_state_location}/specs.cpp&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+					<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
+						<buildOutputProvider>
+							<openAction enabled="true" filePath=""/>
+							<parser enabled="true"/>
+						</buildOutputProvider>
+						<scannerInfoProvider id="specsFile">
+							<runAction arguments="-c 'gcc -E -P -v -dD &quot;${plugin_state_location}/specs.c&quot;'" command="sh" useDefault="true"/>
+							<parser enabled="true"/>
+						</scannerInfoProvider>
+					</profile>
+				</scannerConfigBuildInfo>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM3210E-EVAL.com.atollic.truestudio.exe.1347824761" name="Executable" projectType="com.atollic.truestudio.exe"/>
+	</storageModule>
+</cproject>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.project
new file mode 100644
index 0000000..d448e26
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.project
@@ -0,0 +1,230 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM3210E-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f10x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/system_stm32f10x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM3210E_EVAL/stm3210e_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F10x_StdPeriph_Driver/stm32f10x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f10x_hd.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F10x/Source/Templates/TrueSTUDIO/startup_stm32f10x_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..fa25d7d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:23:55 GMT+01:00 2012
+BOARD=STM3210E-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZE
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..8320534
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20010000;    /* end of 64K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 64K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
new file mode 100644
index 0000000..bfb478d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.cproject
@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.189815562">
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+			<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="STM32F103ZG.com.atollic.truestudio.exe.973923606" name="Executable" projectType="com.atollic.truestudio.exe"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..a824e90
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:24:15 GMT+01:00 2012
+BOARD=STM3210E-EVAL_XL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F103ZG
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
new file mode 100644
index 0000000..3b9f2f6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/STM32F10X_XL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Virtual_COM_Port\TrueSTUDIO\STM3210E-EVAL_XL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32F10X_XL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM3210E-EVAL_XL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM3210E-EVAL_XL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
new file mode 100644
index 0000000..b1c6965
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM3210E-EVAL_XL/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F103ZG Device with
+**                1MByte FLASH, 96KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20018000;    /* end of 96K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1M
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 96K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.cproject b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.cproject
new file mode 100644
index 0000000..5929ca9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.cproject
@@ -0,0 +1,352 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.atollic.truestudio.exe.debug.311825581">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.311825581" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.311825581" name="Debug" parent="com.atollic.truestudio.exe.debug" postbuildStep="" prebuildStep="">
+					<folderInfo id="com.atollic.truestudio.exe.debug.311825581." name="/" resourcePath="">
+						<toolChain id="com.atollic.truestudio.exe.debug.toolchain.1420439189" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.151927203" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>
+							<builder buildPath="${workspace_loc:/STM3210E-EVAL/Debug}" id="com.atollic.truestudio.mbs.builder1.1914283841" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+								</outputEntries>
+							</builder>
+							<tool command="arm-atollic-eabi-gcc -c" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.as.1164707273" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">
+								<option id="com.atollic.truestudio.common_options.target.endianess.106420962" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.568212416" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1812317909" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.as.general.incpath.521871915" name="Include path" superClass="com.atollic.truestudio.as.general.incpath"/>
+								<inputType id="com.atollic.truestudio.as.input.305266555" name="Input" superClass="com.atollic.truestudio.as.input"/>
+							</tool>
+							<tool commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG}${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="com.atollic.truestudio.exe.debug.toolchain.gcc.1123980438" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">
+								<option id="com.atollic.truestudio.gcc.directories.select.439682285" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/CMSIS/Device/ST/STM32F30x/Include"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32_USB-FS-Device_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Libraries/STM32F30x_StdPeriph_Driver/inc"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/Common"/>
+									<listOptionValue builtIn="false" value="../../../../../Utilities/STM32_EVAL/STM32303C_EVAL"/>
+									<listOptionValue builtIn="false" value="../../../inc"/>
+								</option>
+								<option id="com.atollic.truestudio.gcc.symbols.defined.2128372492" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32F30X"/>
+									<listOptionValue builtIn="false" value="USE_STM32303C_EVAL"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.492059125" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.1329265125" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1481983578" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1725101992" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.optimization.prep_data.1467069942" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gcc.misc.otherflags.1729058625" name="Other options" superClass="com.atollic.truestudio.gcc.misc.otherflags" value="" valueType="string"/>
+								<option id="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level.2061924893" name="Optimization Level" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.optimization.level" value="com.atollic.truestudio.gcc.optimization.level.0s" valueType="enumerated"/>
+								<inputType id="com.atollic.truestudio.gcc.input.488480100" superClass="com.atollic.truestudio.gcc.input"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ld.1761649334" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">
+								<option id="com.atollic.truestudio.common_options.target.endianess.1518303750" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.75478988" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.258687522" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.ld.general.scriptfile.168624971" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../STM32F303VC_FLASH.ld" valueType="string"/>
+								<option id="com.atollic.truestudio.ld.optimization.do_garbage.1748822620" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>
+								<inputType id="com.atollic.truestudio.ld.input.700384899" name="Input" superClass="com.atollic.truestudio.ld.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.527336926" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">
+								<option id="com.atollic.truestudio.gpp.symbols.defined.926135890" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="stringList">
+									<listOptionValue builtIn="false" value="USE_STM3210E_EVAL"/>
+									<listOptionValue builtIn="false" value="STM32F10X_HD"/>
+									<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
+								</option>
+								<option id="com.atollic.truestudio.common_options.target.endianess.559070467" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.808997326" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1981448318" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.gpp.optimization.prep_garbage.926671416" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_rtti.411635994" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>
+								<option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.263523013" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>
+							</tool>
+							<tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.1992835162" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">
+								<option id="com.atollic.truestudio.common_options.target.endianess.82127981" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>
+								<option id="com.atollic.truestudio.common_options.target.mcpu.39484667" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="STM32F303VC" valueType="enumerated"/>
+								<option id="com.atollic.truestudio.common_options.target.instr_set.1432065453" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>
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diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.project
new file mode 100644
index 0000000..03e51a0
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.project
@@ -0,0 +1,310 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32303C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f30x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f30x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32303C_EVAL/stm32303c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_opamp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_opamp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f30x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F30x_StdPeriph_Driver/src/stm32f30x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f30x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..01cdaca
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,21 @@
+<<<<<<< .mine
+#Thu Dec 13 17:37:51 GMT+01:00 2012
+BOARD=STM32303C-EVAL
+=======
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+>>>>>>> .r415
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+<<<<<<< .mine
+MCU=STM32F303VC
+=======
+MCU=STM32F373VC
+>>>>>>> .r415
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
new file mode 100644
index 0000000..53aeace
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32303C-EVAL/STM32303C-EVAL.elf.launch
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Start the executable&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="72"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="72000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#9;&#9;&#13;&#10;&#13;&#10;# Enable Debug connection in low power modes (DBGMCU-&gt;CR)&#13;&#10;set *0xE0042004 = (*0xE0042004) | 0x7&#13;&#10;&#13;&#10;# The executable starts automatically"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="E:\SVN\STM32_USB-FS-Device_Lib\Projects\Custom_HID\TrueSTUDIO\STM32303C-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32303C-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32303C-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32303C-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.project
new file mode 100644
index 0000000..1d811d4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.project
@@ -0,0 +1,315 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32373C-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?children?</key>
+					<value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
+				</dictionary>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210E-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_stm32f37x.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src/system_stm32f37x.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Custom_HID/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32373C_EVAL/stm32373c_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_adc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_adc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_can.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_can.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_cec.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_cec.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_comp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_comp.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_crc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_crc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dac.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dac.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dbgmcu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dbgmcu.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_dma.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_dma.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_i2c.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_i2c.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_iwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_iwdg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_pwr.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_rtc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_rtc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_sdadc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_sdadc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_spi.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_spi.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_tim.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_tim.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32F37x_StdPeriph_Driver/stm32f37x_wwdg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32F37x_StdPeriph_Driver/src/stm32f37x_wwdg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_stm32f37x.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32F37x/Source/Templates/TrueSTUDIO/startup_stm32f37x.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..ab00129
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32373C-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Thu Dec 13 17:34:36 GMT+01:00 2012
+BOARD=STM32373C-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32F373VC
+MCU_VENDOR=STMicroelectronics
+MODEL=Pro
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=ARM\u00AE
+VERSION=3.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
new file mode 100644
index 0000000..e34e51b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/.settings/com.atollic.truestudio.debug.hardware_device.prefs
@@ -0,0 +1,12 @@
+#Mon Mar 19 16:25:12 GMT+01:00 2012
+BOARD=STM32L152-EVAL
+CODE_LOCATION=FLASH
+ENDIAN=Little-endian
+MCU=STM32L152VB
+MCU_VENDOR=STMicroelectronics
+MODEL=Lite
+PROBE=ST-LINK
+PROJECT_FORMAT_VERSION=2
+TARGET=STMicroelectronics\u00AE STM32\u2122
+VERSION=2.3.0
+eclipse.preferences.version=1
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
new file mode 100644
index 0000000..f63f161
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152-EVAL/STM32L152-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Virtual_COM_Port\TrueSTUDIO\STM32L152-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/.project b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/.project
new file mode 100644
index 0000000..6dbdfd4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/.project
@@ -0,0 +1,231 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>STM32L152D-EVAL</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/STM3210B-EVAL/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>CMSIS</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Doc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>CMSIS/system_STM32L1xx.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/system_STM32L1xx.c</locationURI>
+		</link>
+		<link>
+			<name>Doc/readme.txt</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>STM32L152D_EVAL/stm32l152d_eval.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_exti.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_exti.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_flash.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_flash.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_gpio.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_gpio.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_rcc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_rcc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/STM32L1xx_usart.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/STM32L1xx_usart.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/misc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/misc.c</locationURI>
+		</link>
+		<link>
+			<name>STM32L1xx_StdPeriph_Driver/stm32l1xx_syscfg.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c</locationURI>
+		</link>
+		<link>
+			<name>TrueSTUDIO/startup_STM32L1xx_md.s</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/CMSIS/Device/ST/STM32L1xx/Source/Templates/TrueSTUDIO/startup_STM32L1xx_hd.s</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_core.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_core.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_init.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_init.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_int.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_int.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_mem.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_regs.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_regs.c</locationURI>
+		</link>
+		<link>
+			<name>USB-FS-Device_Driver/usb_sil.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Libraries/STM32_USB-FS-Device_Driver/src/usb_sil.c</locationURI>
+		</link>
+		<link>
+			<name>User/hw_config.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/hw_config.c</locationURI>
+		</link>
+		<link>
+			<name>User/main.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/main.c</locationURI>
+		</link>
+		<link>
+			<name>User/stm32_it.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/stm32_it.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_desc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_desc.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_endp.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_endp.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_istr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_istr.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_prop.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_prop.c</locationURI>
+		</link>
+		<link>
+			<name>User/usb_pwr.c</name>
+			<type>1</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Projects/Virtual_COM_Port/src/usb_pwr.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
new file mode 100644
index 0000000..96ae53c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/STM32L152D-EVAL.elf.launch
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
+<stringAttribute key="com.atollic.hardwaredebug.launch.analyzeCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Start the executable.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.enable_swv" value="false"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.formatVersion" value="2"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.initCommands" value=""/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.ipAddress" value="localhost"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.jtagDevice" value="ST-LINK"/>
+<intAttribute key="com.atollic.hardwaredebug.launch.portNumber" value="61234"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.remoteCommand" value="target extended-remote"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.runCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.serverParam" value="-p 61234 -l 1 -d"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.startServer" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swd_mode" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_port" value="61235"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_div" value="8"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.swv_trace_hclk" value="8000000"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.swv_wait_for_sync" value="true"/>
+<booleanAttribute key="com.atollic.hardwaredebug.launch.useRemoteTarget" value="true"/>
+<stringAttribute key="com.atollic.hardwaredebug.launch.verifyCommands" value="# Set flash parallelism mode to 32, 16, or 8 bit when using STM32 F2/F4 microcontrollers&#13;&#10;# Uncomment next line, 2=32 bit, 1=16 bit and 0=8 bit parallelism mode&#13;&#10;#monitor flash set_parallelism_mode 2&#13;&#10;&#13;&#10;# Load the program executable&#13;&#10;load&#13;&#10;&#13;&#10;# Set a breakpoint at main().&#13;&#10;tbreak main&#13;&#10;&#13;&#10;# Reset to known state&#13;&#10;monitor reset&#13;&#10;&#13;&#10;# Run to the breakpoint.&#13;&#10;continue"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.enable_logging" value="false"/>
+<stringAttribute key="com.atollic.hardwaredebug.stlink.log_file" value="C:\VSS\BARRACUDA\INTRODUCTION PACKAGE\FIRMWARE\STM32_USB-FS-Device_Lib\Project\Virtual_COM_Port\TrueSTUDIO\STM32L152D-EVAL\Debug\st-link_gdbserver_log.txt"/>
+<booleanAttribute key="com.atollic.hardwaredebug.stlink.verify_flash" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${TOOLCHAIN_PATH}/arm-atollic-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;globalVariableList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList/&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/STM32L152D-EVAL.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="STM32L152D-EVAL"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/STM32L152D-EVAL"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
new file mode 100644
index 0000000..0d8b7b3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/TrueSTUDIO/STM32L152D-EVAL/stm32_flash.ld
@@ -0,0 +1,171 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for stm32l1xx_hd Device with
+**                384KByte FLASH, 48KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2000BFF8; 
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x800;  /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 384K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/hw_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/hw_config.h
new file mode 100644
index 0000000..ed8b783
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/hw_config.h
@@ -0,0 +1,64 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HW_CONFIG_H
+#define __HW_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+#include "usb_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define MASS_MEMORY_START     0x04002000
+#define BULK_MAX_PACKET_SIZE  0x00000040
+#define LED_ON                0xF0
+#define LED_OFF               0xFF
+
+#define USART_RX_DATA_SIZE   2048
+/* Exported functions ------------------------------------------------------- */
+void Set_System(void);
+void Set_USBClock(void);
+void Enter_LowPowerMode(void);
+void Leave_LowPowerMode(void);
+void USB_Interrupts_Config(void);
+void USB_Cable_Config (FunctionalState NewState);
+void USART_Config_Default(void);
+bool USART_Config(void);
+void USB_To_USART_Send_Data(uint8_t* data_buffer, uint8_t Nb_bytes);
+void USART_To_USB_Send_Data(void);
+void Handle_USBAsynchXfer (void);
+void Get_SerialNum(void);
+
+/* External variables --------------------------------------------------------*/
+
+#endif  /*__HW_CONFIG_H*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/platform_config.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/platform_config.h
new file mode 100644
index 0000000..68d9c6f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/platform_config.h
@@ -0,0 +1,161 @@
+/**
+  ******************************************************************************
+  * @file    platform_config.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Evaluation board specific configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __PLATFORM_CONFIG_H
+#define __PLATFORM_CONFIG_H
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+ #include "stm32l1xx.h"
+ #if defined (USE_STM32L152_EVAL)
+  #include "stm32l152_eval.h"
+ #elif defined (USE_STM32L152D_EVAL)
+  #include "stm32l152d_eval.h"
+ #else
+  #error "Missing define: USE_STM32L152_EVAL or USE_STM32L152D_EVAL"
+ #endif /* USE_STM32L152_EVAL */
+#elif defined (STM32F10X_MD) || defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #include "stm32f10x.h"
+ #if defined (USE_STM3210B_EVAL)
+  #include "stm3210b_eval.h"
+ #elif defined (USE_STM3210E_EVAL)
+  #include "stm3210e_eval.h"
+ #else
+  #error "Missing define: USE_STM3210B_EVAL or USE_STM3210E_EVAL"
+ #endif /* USE_STM3210B_EVAL */
+#elif defined (USE_STM32373C_EVAL)
+ #include "stm32f37x.h"
+ #include "stm32373c_eval.h"
+#elif defined (USE_STM32303C_EVAL)
+ #include "stm32f30x.h"
+ #include "stm32303c_eval.h"
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line corresponding to the STMicroelectronics evaluation board
+   used to run the example */
+#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)  && !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32L152D_EVAL) &&  !defined (USE_STM32373C_EVAL) && !defined (USE_STM32303C_EVAL)
+//#define USE_STM3210B_EVAL
+//#define USE_STM3210E_EVAL
+//#define USE_STM32L152_EVAL
+//#define USE_STM32L152D_EVAL
+//#define (USE_STM32373C_EVAL)
+#define (USE_STM32303C_EVAL)
+#endif
+
+/*Unique Devices IDs register set*/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+
+#define         ID1          (0x1FF80050)
+#define         ID2          (0x1FF80054)
+#define         ID3          (0x1FF80064)
+
+#elif defined (STM32F37X) || defined(STM32F30X)
+
+#define         ID1          (0x1FFFF7AC)
+#define         ID2          (0x1FFFF7B0)
+#define         ID3          (0x1FFFF7B4)
+
+#else /*STM32F1x*/
+
+#define         ID1          (0x1FFFF7E8)
+#define         ID2          (0x1FFFF7EC)
+#define         ID3          (0x1FFFF7F0)
+
+#endif
+
+/* Define the STM32F10x hardware depending on the used evaluation board */
+#ifdef USE_STM3210B_EVAL
+  #define USB_DISCONNECT                      GPIOD  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_9
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOD
+  #define EVAL_COM1_IRQHandler                USART1_IRQHandler 
+
+#elif defined (USE_STM3210E_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_14
+  #define RCC_APB2Periph_GPIO_DISCONNECT      RCC_APB2Periph_GPIOB
+  #define EVAL_COM1_IRQHandler                USART1_IRQHandler 
+ 
+
+#elif defined (USE_STM32L152_EVAL) || defined (USE_STM32L152D_EVAL)
+ /* 
+   For STM32L15xx devices it is possible to use the internal USB pullup
+   controlled by register SYSCFG_PMC (refer to RM0038 reference manual for
+   more details).
+   It is also possible to use external pullup (and disable the internal pullup)
+   by setting the define USB_USE_EXTERNAL_PULLUP in file platform_config.h
+   and configuring the right pin to be used for the external pull up configuration.
+   To have more details on how to use an external pull up, please refer to 
+   STM3210E-EVAL evaluation board manuals.
+   */
+ /* Uncomment the following define to use an external pull up instead of the 
+    integrated STM32L15xx internal pull up. In this case make sure to set up
+    correctly the external required hardware and the GPIO defines below.*/
+/* #define USB_USE_EXTERNAL_PULLUP */
+
+ #if !defined(USB_USE_EXTERNAL_PULLUP)
+  #define STM32L15_USB_CONNECT                SYSCFG_USBPuCmd(ENABLE)
+  #define STM32L15_USB_DISCONNECT             SYSCFG_USBPuCmd(DISABLE)
+
+ #elif defined(USB_USE_EXTERNAL_PULLUP)
+  /* PA0 is chosen just as illustrating example, you should modify the defines
+    below according to your hardware configuration. */ 
+  #define USB_DISCONNECT                      GPIOA
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_0
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOA
+  #define STM32L15_USB_CONNECT                GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+  #define STM32L15_USB_DISCONNECT             GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN)
+ #endif /* USB_USE_EXTERNAL_PULLUP */
+
+#elif defined (USE_STM32373C_EVAL)
+  #define USB_DISCONNECT                      GPIOC  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_5
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOC
+
+#elif defined (USE_STM32303C_EVAL)
+  #define USB_DISCONNECT                      GPIOB  
+  #define USB_DISCONNECT_PIN                  GPIO_Pin_8
+  #define RCC_AHBPeriph_GPIO_DISCONNECT       RCC_AHBPeriph_GPIOB
+#endif /* USE_STM3210B_EVAL */
+
+#if defined (USE_STM32L152_EVAL) || (USE_STM32373C_EVAL)
+ #define EVAL_COM1_IRQHandler                USART2_IRQHandler
+#elif defined (USE_STM32L152D_EVAL) || (USE_STM32303C_EVAL)
+ #define EVAL_COM1_IRQHandler              USART1_IRQHandler
+#endif
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __PLATFORM_CONFIG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32_it.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32_it.h
new file mode 100644
index 0000000..a6f3368
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32_it.h
@@ -0,0 +1,59 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_IT_H
+#define __STM32_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "platform_config.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USB_LP_CAN1_RX0_IRQHandler(void);
+
+#if defined (USE_STM32L152_EVAL) || (USE_STM32373C_EVAL)
+void USART2_IRQHandler(void);
+#else
+void USART1_IRQHandler(void);
+#endif /* USE_STM32L152_EVAL */
+#endif /* __STM32_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f10x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..e08299d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f10x_conf.h
@@ -0,0 +1,85 @@
+/**
+  ******************************************************************************
+  * @file    stm32f10x_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h" 
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h"   /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/*******************************************************************************
+* Macro Name     : assert_param
+* Description    : The assert_param macro is used for function's parameters check.
+* Input          : - expr: If expr is false, it calls assert_failed function
+*                    which reports the name of the source file and the source
+*                    line number of the call that failed. 
+*                    If expr is true, it returns no value.
+* Return         : None
+*******************************************************************************/ 
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f30x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f30x_conf.h
new file mode 100644
index 0000000..e716105
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f30x_conf.h
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32f30x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30X_CONF_H
+#define __STM32F30X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f30x_adc.h"
+#include "stm32f30x_can.h"
+#include "stm32f30x_crc.h"
+#include "stm32f30x_comp.h"
+#include "stm32f30x_dac.h"
+#include "stm32f30x_dbgmcu.h"
+#include "stm32f30x_dma.h"
+#include "stm32f30x_exti.h"
+#include "stm32f30x_flash.h"
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_syscfg.h"
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_iwdg.h"
+#include "stm32f30x_opamp.h"
+#include "stm32f30x_pwr.h"
+#include "stm32f30x_rcc.h"
+#include "stm32f30x_rtc.h"
+#include "stm32f30x_spi.h"
+#include "stm32f30x_tim.h"
+#include "stm32f30x_usart.h"
+#include "stm32f30x_wwdg.h"
+#include "stm32f30x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F30X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f37x_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f37x_conf.h
new file mode 100644
index 0000000..3d39101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/stm32f37x_conf.h
@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32f37x_conf.h 
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F37X_CONF_H
+#define __STM32F37X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "stm32f37x_adc.h"
+#include "stm32f37x_can.h"
+#include "stm32f37x_cec.h"
+#include "stm32f37x_crc.h"
+#include "stm32f37x_comp.h"
+#include "stm32f37x_dac.h"
+#include "stm32f37x_dbgmcu.h"
+#include "stm32f37x_dma.h"
+#include "stm32f37x_exti.h"
+#include "stm32f37x_flash.h"
+#include "stm32f37x_gpio.h"
+#include "stm32f37x_syscfg.h"
+#include "stm32f37x_i2c.h"
+#include "stm32f37x_iwdg.h"
+#include "stm32f37x_pwr.h"
+#include "stm32f37x_rcc.h"
+#include "stm32f37x_rtc.h"
+#include "stm32f37x_sdadc.h"
+#include "stm32f37x_spi.h"
+#include "stm32f37x_tim.h"
+#include "stm32f37x_usart.h"
+#include "stm32f37x_wwdg.h"
+#include "stm32f37x_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function which reports 
+  *         the name of the source file and the source line number of the call 
+  *         that failed. If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F37X_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_conf.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_conf.h
new file mode 100644
index 0000000..bdb9bb2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_conf.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    usb_conf.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Virtual COM Port Demo configuration  header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CONF_H
+#define __USB_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+
+/*-------------------------------------------------------------*/
+/* EP_NUM */
+/* defines how many endpoints are used by the device */
+/*-------------------------------------------------------------*/
+
+#define EP_NUM                          (4)
+
+/*-------------------------------------------------------------*/
+/* --------------   Buffer Description Table  -----------------*/
+/*-------------------------------------------------------------*/
+/* buffer table base address */
+/* buffer table base address */
+#define BTABLE_ADDRESS      (0x00)
+
+/* EP0  */
+/* rx/tx buffer base address */
+#define ENDP0_RXADDR        (0x40)
+#define ENDP0_TXADDR        (0x80)
+
+/* EP1  */
+/* tx buffer base address */
+#define ENDP1_TXADDR        (0xC0)
+#define ENDP2_TXADDR        (0x100)
+#define ENDP3_RXADDR        (0x110)
+
+
+/*-------------------------------------------------------------*/
+/* -------------------   ISTR events  -------------------------*/
+/*-------------------------------------------------------------*/
+/* IMR_MSK */
+/* mask defining which events has to be handled */
+/* by the device application software */
+#define IMR_MSK (CNTR_CTRM  | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM  | CNTR_SOFM \
+                 | CNTR_ESOFM | CNTR_RESETM )
+
+/*#define CTR_CALLBACK*/
+/*#define DOVR_CALLBACK*/
+/*#define ERR_CALLBACK*/
+/*#define WKUP_CALLBACK*/
+/*#define SUSP_CALLBACK*/
+/*#define RESET_CALLBACK*/
+#define SOF_CALLBACK
+/*#define ESOF_CALLBACK*/
+/* CTR service routines */
+/* associated to defined endpoints */
+/*#define  EP1_IN_Callback   NOP_Process*/
+#define  EP2_IN_Callback   NOP_Process
+#define  EP3_IN_Callback   NOP_Process
+#define  EP4_IN_Callback   NOP_Process
+#define  EP5_IN_Callback   NOP_Process
+#define  EP6_IN_Callback   NOP_Process
+#define  EP7_IN_Callback   NOP_Process
+
+#define  EP1_OUT_Callback   NOP_Process
+#define  EP2_OUT_Callback   NOP_Process
+/*#define  EP3_OUT_Callback   NOP_Process*/
+#define  EP4_OUT_Callback   NOP_Process
+#define  EP5_OUT_Callback   NOP_Process
+#define  EP6_OUT_Callback   NOP_Process
+#define  EP7_OUT_Callback   NOP_Process
+
+#endif /* __USB_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_desc.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_desc.h
new file mode 100644
index 0000000..6a26870
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_desc.h
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptor Header for Virtual COM Port Device
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
+#define USB_STRING_DESCRIPTOR_TYPE              0x03
+#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
+#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
+
+#define VIRTUAL_COM_PORT_DATA_SIZE              64
+#define VIRTUAL_COM_PORT_INT_SIZE               8
+
+#define VIRTUAL_COM_PORT_SIZ_DEVICE_DESC        18
+#define VIRTUAL_COM_PORT_SIZ_CONFIG_DESC        67
+#define VIRTUAL_COM_PORT_SIZ_STRING_LANGID      4
+#define VIRTUAL_COM_PORT_SIZ_STRING_VENDOR      38
+#define VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT     50
+#define VIRTUAL_COM_PORT_SIZ_STRING_SERIAL      26
+
+#define STANDARD_ENDPOINT_DESC_SIZE             0x09
+
+/* Exported functions ------------------------------------------------------- */
+extern const uint8_t Virtual_Com_Port_DeviceDescriptor[VIRTUAL_COM_PORT_SIZ_DEVICE_DESC];
+extern const uint8_t Virtual_Com_Port_ConfigDescriptor[VIRTUAL_COM_PORT_SIZ_CONFIG_DESC];
+
+extern const uint8_t Virtual_Com_Port_StringLangID[VIRTUAL_COM_PORT_SIZ_STRING_LANGID];
+extern const uint8_t Virtual_Com_Port_StringVendor[VIRTUAL_COM_PORT_SIZ_STRING_VENDOR];
+extern const uint8_t Virtual_Com_Port_StringProduct[VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT];
+extern uint8_t Virtual_Com_Port_StringSerial[VIRTUAL_COM_PORT_SIZ_STRING_SERIAL];
+
+#endif /* __USB_DESC_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_prop.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_prop.h
new file mode 100644
index 0000000..bd81702
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_prop.h
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Virtual COM Port Demo (Endpoint 0)
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __usb_prop_H
+#define __usb_prop_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint32_t bitrate;
+  uint8_t format;
+  uint8_t paritytype;
+  uint8_t datatype;
+}LINE_CODING;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported define -----------------------------------------------------------*/
+
+#define Virtual_Com_Port_GetConfiguration          NOP_Process
+//#define Virtual_Com_Port_SetConfiguration          NOP_Process
+#define Virtual_Com_Port_GetInterface              NOP_Process
+#define Virtual_Com_Port_SetInterface              NOP_Process
+#define Virtual_Com_Port_GetStatus                 NOP_Process
+#define Virtual_Com_Port_ClearFeature              NOP_Process
+#define Virtual_Com_Port_SetEndPointFeature        NOP_Process
+#define Virtual_Com_Port_SetDeviceFeature          NOP_Process
+//#define Virtual_Com_Port_SetDeviceAddress          NOP_Process
+
+#define SEND_ENCAPSULATED_COMMAND   0x00
+#define GET_ENCAPSULATED_RESPONSE   0x01
+#define SET_COMM_FEATURE            0x02
+#define GET_COMM_FEATURE            0x03
+#define CLEAR_COMM_FEATURE          0x04
+#define SET_LINE_CODING             0x20
+#define GET_LINE_CODING             0x21
+#define SET_CONTROL_LINE_STATE      0x22
+#define SEND_BREAK                  0x23
+
+/* Exported functions ------------------------------------------------------- */
+void Virtual_Com_Port_init(void);
+void Virtual_Com_Port_Reset(void);
+void Virtual_Com_Port_SetConfiguration(void);
+void Virtual_Com_Port_SetDeviceAddress (void);
+void Virtual_Com_Port_Status_In (void);
+void Virtual_Com_Port_Status_Out (void);
+RESULT Virtual_Com_Port_Data_Setup(uint8_t);
+RESULT Virtual_Com_Port_NoData_Setup(uint8_t);
+RESULT Virtual_Com_Port_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting);
+uint8_t *Virtual_Com_Port_GetDeviceDescriptor(uint16_t );
+uint8_t *Virtual_Com_Port_GetConfigDescriptor(uint16_t);
+uint8_t *Virtual_Com_Port_GetStringDescriptor(uint16_t);
+
+uint8_t *Virtual_Com_Port_GetLineCoding(uint16_t Length);
+uint8_t *Virtual_Com_Port_SetLineCoding(uint16_t Length);
+
+#endif /* __usb_prop_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_pwr.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_pwr.h
new file mode 100644
index 0000000..15255b2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/inc/usb_pwr.h
@@ -0,0 +1,72 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.h
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management header
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_PWR_H
+#define __USB_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RESUME_STATE
+{
+  RESUME_EXTERNAL,
+  RESUME_INTERNAL,
+  RESUME_LATER,
+  RESUME_WAIT,
+  RESUME_START,
+  RESUME_ON,
+  RESUME_OFF,
+  RESUME_ESOF
+} RESUME_STATE;
+
+typedef enum _DEVICE_STATE
+{
+  UNCONNECTED,
+  ATTACHED,
+  POWERED,
+  SUSPENDED,
+  ADDRESSED,
+  CONFIGURED
+} DEVICE_STATE;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void Suspend(void);
+void Resume_Init(void);
+void Resume(RESUME_STATE eResumeSetVal);
+RESULT PowerOn(void);
+RESULT PowerOff(void);
+
+/* External variables --------------------------------------------------------*/
+extern  __IO uint32_t bDeviceState; /* USB device status */
+extern __IO bool fSuspendEnabled;  /* true when suspend is possible */
+
+#endif  /*__USB_PWR_H*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/readme.txt b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/readme.txt
new file mode 100644
index 0000000..7f7e18a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/readme.txt
@@ -0,0 +1,215 @@
+/**
+  ******************************************************************************
+  * @file    readme.txt
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Description of the USB Virtual_COM_Port Demo.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+Example description
+===================
+In modern PCs, USB is the standard communication port for almost all peripherals. 
+However many industrial software applications still use the classic COM Port (UART).
+The Virtual COM Port Demo provides a simple solution to bypass this problem; it
+uses the USB-FS-Device as a COM port by affecting the legacy PC application designed for
+COM Port communication.
+This Virtual COM Port Demo provides the firmware examples for the STM32F10xxx,STM32L15xxx,
+STM32F30xxx and STM32F37xxx families.
+
+Note that with this demo only the following configuration are supported:
+-> 7bit data with parity (Even or Odd).
+-> 8bit data with and without parity.
+
+This demo is using two different methods for the IN and OUT transfers in order 
+to manage the data rate difference between USB and USART buses:
+
+ - OUT transfers (from Host to Device):
+     When a packet is received from the host on the OUT pipe (EP3), the Endpoint
+     callback function is called when the transfer is complete and all the received
+     data are then sent through USART peripheral in polling mode. This allows all
+     incoming OUT packets to be NAKed till the current packet is completely transferred
+     through the USART interface.
+ 
+ - IN transfers (from Device to Host):
+     For IN data, a large circular buffer is used. USART and USB respectively write
+     and read to/from this buffer independently.
+     USART RXNE interrupt is used to write data into the buffer. This interrupt 
+     has the highest priority, which allows to avoid overrun and data loss conditions.
+     USB IN endpoint (EP1) is written with the received data into the SOF interrupt 
+     callback. 
+     Into this callback, a frame counter counts the number of passed frames since 
+     the last time IN endpoint was written. This allows to write IN endpoint at
+     separated frames when enough data are present in the data buffer. 
+     To modify the number of frame between IN write operations, modify the value 
+     of the define "VCOMPORT_IN_FRAME_INTERVAL" in "usb_endp.c" file.
+     To allow high data rate performance, SOF interrupt is managed with highest 
+     priority (thus SOF interrupt is checked before all other interrupts).     
+
+
+More details about this Demo implementation is given in the User manual 
+"UM0424 STM32F10xxx USB development kit", available for download from the ST
+microcontrollers website: www.st.com/stm32
+
+
+Directory contents
+==================
+ + \inc: contains the Demo firmware header files
+ + \EWARM: contains preconfigured projects for EWARM toolchain
+ + \RIDE: contains preconfigured projects for RIDE toolchain
+ + \MDK-ARM: contains preconfigured projects for MDK-ARM toolchain
+ + \TASKNIG: contains preconfigured projects for TASKING toolchain
+ + \TrueSTUDIO: contains preconfigured projects for TrueSTUDIO toolchain          
+ + \src: contains the Demo firmware source files
+
+
+Hardware environment
+====================
+This example runs these STMicroelectronics evaluation boards and can be easily tailored to any other hardware: 
+
+- STM3210B-EVAL
+- STM3210E-EVAL
+- STM32L152-EVAL
+- STM32F373C_EVAL
+- STM32F303C_EVAL
+- STM32L152D-EVAL
+
+To select the STMicroelectronics evaluation board used to run the example, uncomment
+the corresponding line in platform_config.h file.
+
+  - STM3210B-EVAL Set-up 
+     - Jumper JP1 (USB disconnect) should be connected in position 2-3.
+     - Connect a null-modem female/female RS232 cable between the DB9 connector 
+      CN6 and Host (PC) serial port.
+
+  - STM3210E-EVAL Set-up 
+     - Jumper JP14 (USB disconnect) should be connected in position 2-3.
+     - Connect a null-modem female/female RS232 cable between the DB9 connector
+      CN12 and Host (PC) serial port. 
+
+  - STM32L152-EVAL Set-up 
+     - Jumper JP19 should be not connected.
+     - Jumper JP5 should be connected in 2-3 position (RS232)
+     - Connect a null-modem female/female RS232 cable between the DB9 connector
+       CN2 and Host (PC) serial port.
+     - The signal Bootloader_RESET (shared with CTS signal) HENSE USART cable with 
+      RX,TX and GND lines ONLY is mandatory
+  
+  - STM32L152D-EVAL Set-up 
+	- Jumper JP4 should be connected in 2-3 position (RS232)
+	- Connect a null-modem female/female RS232 cable between the DB9 connector	
+      CN1 and Host (PC) serial port.
+	- In STM32L152D-EVAL RevB CTS pin is connected directly (without jumper) to MCU Reset: HENSE USART cable with 
+      RX,TX and GND lines ONLY is mandatory. When using EVAL Rev A Put JP3 to position 2-3	
+    
+  - STM32F373C_EVAL  Set-up 
+	- Jumper JP6 should be connected in 2-3 position (RS232)
+        - Jumper JP7 should be connected in 1-2 position.
+        - Connect a null-modem female/female RS232 cable between the DB9 connector
+          CN12 and Host (PC) serial port.
+
+  - STM32F303C_EVAL  Set-up 
+	- Jumper JP13 should be connected in 2-3 position (RS232)
+        - Connect a null-modem female/female RS232 cable between the DB9 connector
+          CN8 and Host (PC) serial port.
+
+How to use it
+=============
+ + EWARM
+    - Open the VirtualCOMPort.eww workspace.
+    - In the workspace toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices     
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the VirtualCOMPort.Uv2 project
+    - In the build toolbar select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices 
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5) 
+
+ + RIDE
+    - Open the VirtualCOMPort.rprj project.
+    - In the configuration toolbar(Project->properties) select the project config:
+        - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all files: Project->build project
+    - Load project image: Debug->start(ctrl+D)
+    - Run program: Debug->Run(ctrl+F9)
+
+ + TASKING
+    - Open TASKING toolchain.
+      - Click on File->Import, select General->'Existing Projects into Workspace' 
+        and then click "Next". 
+      - Browse to TASKING workspace directory and select the project: 
+       - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to configure the project for STM32 High-density devices
+        - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
+        - STM32L152-EVAL: to configure the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+        window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+        Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project:  
+        - STM3210B-EVAL: to load the project for STM32 Medium-density devices
+        - STM3210E-EVAL: to load the project for STM32 High-density devices
+        - STM3210E_EVAL_XL: to load the project for STM32 XL-density devices
+        - STM32L152_EVAL: to load the project for STM32 Medium-Density Low-Power devices
+        - STM32L152D-EVAL: to configure the project for STM32 High-Density Low-Power devices
+        - STM32373C-EVAL:  to configure the project for STM32F37xxx devices
+        - STM32303C-EVAL:  to configure the project for STM32F30xxx devices  
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE******
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/hw_config.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/hw_config.c
new file mode 100644
index 0000000..5f58e7f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/hw_config.c
@@ -0,0 +1,561 @@
+/**
+  ******************************************************************************
+  * @file    hw_config.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Hardware Configuration & Setup
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "hw_config.h"
+#include "usb_pwr.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+ErrorStatus HSEStartUpStatus;
+USART_InitTypeDef USART_InitStructure;
+EXTI_InitTypeDef EXTI_InitStructure;
+uint8_t  USART_Rx_Buffer [USART_RX_DATA_SIZE]; 
+uint32_t USART_Rx_ptr_in = 0;
+uint32_t USART_Rx_ptr_out = 0;
+uint32_t USART_Rx_length  = 0;
+
+uint8_t  USB_Tx_State = 0;
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
+/* Extern variables ----------------------------------------------------------*/
+
+extern LINE_CODING linecoding;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : Set_System
+* Description    : Configures Main system clocks & power
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_System(void)
+{
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS)
+  GPIO_InitTypeDef GPIO_InitStructure;
+#endif /* STM32L1XX_MD && STM32L1XX_XD */  
+
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  GPIO_InitTypeDef  GPIO_InitStructure;
+#endif /* USB_USE_EXTERNAL_PULLUP */ 
+  
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f10x_xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+       system_stm32f10x.c file
+     */   
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS) || defined(STM32F37X) || defined(STM32F30X)
+  /* Enable the SYSCFG module clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+#endif /* STM32L1XX_XD */ 
+   
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_HD) && !defined(STM32L1XX_MD_PLUS) && !defined(STM32F37X) && !defined(STM32F30X)
+  /* Enable USB_DISCONNECT GPIO clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_DISCONNECT, ENABLE);
+
+  /* Configure USB pull-up pin */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32L1XX_MD && STM32L1XX_XD */
+   
+#if defined(USB_USE_EXTERNAL_PULLUP)
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);  
+#endif /* USB_USE_EXTERNAL_PULLUP */ 
+  
+#if defined(STM32F37X) || defined(STM32F30X)
+  
+  /* Enable the USB disconnect GPIO clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIO_DISCONNECT, ENABLE);
+  
+  /*Set PA11,12 as IN - USB_DM,DP*/
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /*SET PA11,12 for USB: USB_DM,DP*/
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_14);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_14);
+  
+  /* USB_DISCONNECT used as USB pull-up */
+  GPIO_InitStructure.GPIO_Pin = USB_DISCONNECT_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(USB_DISCONNECT, &GPIO_InitStructure);
+#endif /* STM32F37X && STM32F30X */ 
+  
+  /* Configure the EXTI line 18 connected internally to the USB IP */
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18; 
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : Set_USBClock
+* Description    : Configures USB Clock input (48MHz)
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Set_USBClock(void)
+{
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MD_PLUS) 
+  /* Enable USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+  
+#else 
+  /* Select USBCLK source */
+  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5);
+  
+  /* Enable the USB clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  : Enter_LowPowerMode
+* Description    : Power-off system clocks and power while entering suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Enter_LowPowerMode(void)
+{
+  /* Set the device state to suspend */
+  bDeviceState = SUSPENDED;
+}
+
+/*******************************************************************************
+* Function Name  : Leave_LowPowerMode
+* Description    : Restores system clocks and power while exiting suspend mode
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void Leave_LowPowerMode(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  /* Set the device state to the correct state */
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+  else
+  {
+    bDeviceState = ATTACHED;
+  }
+  /*Enable SystemCoreClock*/
+  SystemInit();
+}
+
+/*******************************************************************************
+* Function Name  : USB_Interrupts_Config
+* Description    : Configures the USB interrupts
+* Input          : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Interrupts_Config(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure; 
+  
+  /* 2 bit for pre-emption priority, 2 bits for subpriority */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);  
+  
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+    /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#elif defined(STM32F37X)
+  /* Enable the USB interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+#else
+  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+    /* Enable the USB Wake-up interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = USBWakeUp_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_Init(&NVIC_InitStructure);
+#endif /* STM32L1XX_XD */
+
+  /* Enable USART Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = EVAL_COM1_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_Init(&NVIC_InitStructure);
+}
+
+/*******************************************************************************
+* Function Name  : USB_Cable_Config
+* Description    : Software Connection/Disconnection of USB Cable
+* Input          : None.
+* Return         : Status
+*******************************************************************************/
+void USB_Cable_Config (FunctionalState NewState)
+{
+#if defined(STM32L1XX_MD) || defined (STM32L1XX_HD)|| (STM32L1XX_MD_PLUS)
+  if (NewState != DISABLE)
+  {
+    STM32L15_USB_CONNECT;
+  }
+  else
+  {
+    STM32L15_USB_DISCONNECT;
+  }  
+  
+#else /* USE_STM3210B_EVAL or USE_STM3210E_EVAL */
+  if (NewState != DISABLE)
+  {
+    GPIO_ResetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+  else
+  {
+    GPIO_SetBits(USB_DISCONNECT, USB_DISCONNECT_PIN);
+  }
+#endif /* STM32L1XX_MD */
+}
+
+/*******************************************************************************
+* Function Name  :  USART_Config_Default.
+* Description    :  configure the EVAL_COM1 with default values.
+* Input          :  None.
+* Return         :  None.
+*******************************************************************************/
+void USART_Config_Default(void)
+{
+  /* EVAL_COM1 default configuration */
+  /* EVAL_COM1 configured as follow:
+        - BaudRate = 9600 baud  
+        - Word Length = 8 Bits
+        - One Stop Bit
+        - Parity Odd
+        - Hardware flow control disabled
+        - Receive and transmit enabled
+  */
+  USART_InitStructure.USART_BaudRate = 9600;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_Odd;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+  /* Configure and enable the USART */
+  STM_EVAL_COMInit(COM1, &USART_InitStructure);
+
+  /* Enable the USART Receive interrupt */
+  USART_ITConfig(EVAL_COM1, USART_IT_RXNE, ENABLE);
+}
+
+/*******************************************************************************
+* Function Name  :  USART_Config.
+* Description    :  Configure the EVAL_COM1 according to the line coding structure.
+* Input          :  None.
+* Return         :  Configuration status
+                    TRUE : configuration done with success
+                    FALSE : configuration aborted.
+*******************************************************************************/
+bool USART_Config(void)
+{
+
+  /* set the Stop bit*/
+  switch (linecoding.format)
+  {
+    case 0:
+      USART_InitStructure.USART_StopBits = USART_StopBits_1;
+      break;
+    case 1:
+      USART_InitStructure.USART_StopBits = USART_StopBits_1_5;
+      break;
+    case 2:
+      USART_InitStructure.USART_StopBits = USART_StopBits_2;
+      break;
+    default :
+    {
+      USART_Config_Default();
+      return (FALSE);
+    }
+  }
+
+  /* set the parity bit*/
+  switch (linecoding.paritytype)
+  {
+    case 0:
+      USART_InitStructure.USART_Parity = USART_Parity_No;
+      break;
+    case 1:
+      USART_InitStructure.USART_Parity = USART_Parity_Even;
+      break;
+    case 2:
+      USART_InitStructure.USART_Parity = USART_Parity_Odd;
+      break;
+    default :
+    {
+      USART_Config_Default();
+      return (FALSE);
+    }
+  }
+
+  /*set the data type : only 8bits and 9bits is supported */
+  switch (linecoding.datatype)
+  {
+    case 0x07:
+      /* With this configuration a parity (Even or Odd) should be set */
+      USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+      break;
+    case 0x08:
+      if (USART_InitStructure.USART_Parity == USART_Parity_No)
+      {
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+      }
+      else 
+      {
+        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
+      }
+      
+      break;
+    default :
+    {
+      USART_Config_Default();
+      return (FALSE);
+    }
+  }
+
+  USART_InitStructure.USART_BaudRate = linecoding.bitrate;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ 
+  /* Configure and enable the USART */
+  STM_EVAL_COMInit(COM1, &USART_InitStructure);
+
+  return (TRUE);
+}
+
+/*******************************************************************************
+* Function Name  : USB_To_USART_Send_Data.
+* Description    : send the received data from USB to the UART 0.
+* Input          : data_buffer: data address.
+                   Nb_bytes: number of bytes to send.
+* Return         : none.
+*******************************************************************************/
+void USB_To_USART_Send_Data(uint8_t* data_buffer, uint8_t Nb_bytes)
+{
+  
+  uint32_t i;
+  
+  for (i = 0; i < Nb_bytes; i++)
+  {
+    USART_SendData(EVAL_COM1, *(data_buffer + i));
+    while(USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TXE) == RESET); 
+  }  
+}
+
+/*******************************************************************************
+* Function Name  : Handle_USBAsynchXfer.
+* Description    : send data to USB.
+* Input          : None.
+* Return         : none.
+*******************************************************************************/
+void Handle_USBAsynchXfer (void)
+{
+  
+  uint16_t USB_Tx_ptr;
+  uint16_t USB_Tx_length;
+  
+  if(USB_Tx_State != 1)
+  {
+    if (USART_Rx_ptr_out == USART_RX_DATA_SIZE)
+    {
+      USART_Rx_ptr_out = 0;
+    }
+    
+    if(USART_Rx_ptr_out == USART_Rx_ptr_in) 
+    {
+      USB_Tx_State = 0; 
+      return;
+    }
+    
+    if(USART_Rx_ptr_out > USART_Rx_ptr_in) /* rollback */
+    { 
+      USART_Rx_length = USART_RX_DATA_SIZE - USART_Rx_ptr_out;
+    }
+    else 
+    {
+      USART_Rx_length = USART_Rx_ptr_in - USART_Rx_ptr_out;
+    }
+    
+    if (USART_Rx_length > VIRTUAL_COM_PORT_DATA_SIZE)
+    {
+      USB_Tx_ptr = USART_Rx_ptr_out;
+      USB_Tx_length = VIRTUAL_COM_PORT_DATA_SIZE;
+      
+      USART_Rx_ptr_out += VIRTUAL_COM_PORT_DATA_SIZE;	
+      USART_Rx_length -= VIRTUAL_COM_PORT_DATA_SIZE;	
+    }
+    else
+    {
+      USB_Tx_ptr = USART_Rx_ptr_out;
+      USB_Tx_length = USART_Rx_length;
+      
+      USART_Rx_ptr_out += USART_Rx_length;
+      USART_Rx_length = 0;
+    }
+    USB_Tx_State = 1; 
+    UserToPMABufferCopy(&USART_Rx_Buffer[USB_Tx_ptr], ENDP1_TXADDR, USB_Tx_length);
+    SetEPTxCount(ENDP1, USB_Tx_length);
+    SetEPTxValid(ENDP1); 
+  }  
+  
+}
+/*******************************************************************************
+* Function Name  : UART_To_USB_Send_Data.
+* Description    : send the received data from UART 0 to USB.
+* Input          : None.
+* Return         : none.
+*******************************************************************************/
+void USART_To_USB_Send_Data(void)
+{
+  
+  if (linecoding.datatype == 7)
+  {
+    USART_Rx_Buffer[USART_Rx_ptr_in] = USART_ReceiveData(EVAL_COM1) & 0x7F;
+  }
+  else if (linecoding.datatype == 8)
+  {
+    USART_Rx_Buffer[USART_Rx_ptr_in] = USART_ReceiveData(EVAL_COM1);
+  }
+  
+  USART_Rx_ptr_in++;
+  
+  /* To avoid buffer overflow */
+  if(USART_Rx_ptr_in == USART_RX_DATA_SIZE)
+  {
+    USART_Rx_ptr_in = 0;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Get_SerialNum.
+* Description    : Create the serial number string descriptor.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Get_SerialNum(void)
+{
+  uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
+
+  Device_Serial0 = *(uint32_t*)ID1;
+  Device_Serial1 = *(uint32_t*)ID2;
+  Device_Serial2 = *(uint32_t*)ID3;  
+
+  Device_Serial0 += Device_Serial2;
+
+  if (Device_Serial0 != 0)
+  {
+    IntToUnicode (Device_Serial0, &Virtual_Com_Port_StringSerial[2] , 8);
+    IntToUnicode (Device_Serial1, &Virtual_Com_Port_StringSerial[18], 4);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : HexToChar.
+* Description    : Convert Hex 32Bits value into char.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
+{
+  uint8_t idx = 0;
+  
+  for( idx = 0 ; idx < len ; idx ++)
+  {
+    if( ((value >> 28)) < 0xA )
+    {
+      pbuf[ 2* idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2* idx] = (value >> 28) + 'A' - 10; 
+    }
+    
+    value = value << 4;
+    
+    pbuf[ 2* idx + 1] = 0;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/main.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/main.c
new file mode 100644
index 0000000..0476650
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/main.c
@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    main.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Virtual Com Port Demo main file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : main.
+* Description    : Main routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+int main(void)
+{
+  Set_System();
+  Set_USBClock();
+  USB_Interrupts_Config();
+  USB_Init();
+  
+  while (1)
+  {
+  }
+}
+#ifdef USE_FULL_ASSERT
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert_param error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert_param error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {}
+}
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/stm32_it.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/stm32_it.c
new file mode 100644
index 0000000..1c081f4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/stm32_it.c
@@ -0,0 +1,236 @@
+/**
+  ******************************************************************************
+  * @file    stm32_it.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and peripherals
+  *          interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "stm32_it.h"
+#include "usb_lib.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/******************************************************************************/
+/*            Cortex-M Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : NMI_Handler
+* Description    : This function handles NMI exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NMI_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : HardFault_Handler
+* Description    : This function handles Hard Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : MemManage_Handler
+* Description    : This function handles Memory Manage exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : BusFault_Handler
+* Description    : This function handles Bus Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : UsageFault_Handler
+* Description    : This function handles Usage Fault exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/*******************************************************************************
+* Function Name  : SVC_Handler
+* Description    : This function handles SVCall exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SVC_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : DebugMon_Handler
+* Description    : This function handles Debug Monitor exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void DebugMon_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : PendSV_Handler
+* Description    : This function handles PendSVC exception.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void PendSV_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : SysTick_Handler
+* Description    : This function handles SysTick Handler.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void SysTick_Handler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name  : USB_IRQHandler
+* Description    : This function handles USB Low Priority interrupts
+*                  requests.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)|| defined (STM32F37X)
+void USB_LP_IRQHandler(void)
+#else
+void USB_LP_CAN1_RX0_IRQHandler(void)
+#endif
+{
+  USB_Istr();
+}
+
+/*******************************************************************************
+* Function Name  : EVAL_COM1_IRQHandler
+* Description    : This function handles EVAL_COM1 global interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void EVAL_COM1_IRQHandler(void)
+{
+  if (USART_GetITStatus(EVAL_COM1, USART_IT_RXNE) != RESET)
+  {
+    /* Send the received data to the PC Host*/
+    USART_To_USB_Send_Data();
+  }
+
+  /* If overrun condition occurs, clear the ORE flag and recover communication */
+  if (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_ORE) != RESET)
+  {
+    (void)USART_ReceiveData(EVAL_COM1);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : USB_FS_WKUP_IRQHandler
+* Description    : This function handles USB WakeUp interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+
+#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD)|| defined(STM32L1XX_MD_PLUS)
+void USB_FS_WKUP_IRQHandler(void)
+#else
+void USBWakeUp_IRQHandler(void)
+#endif
+{
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/******************************************************************************/
+/*                 STM32 Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32xxx.s).                                            */
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name  : PPP_IRQHandler
+* Description    : This function handles PPP interrupt request.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f10x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f10x.c
new file mode 100644
index 0000000..3686a2f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f10x.c
@@ -0,0 +1,917 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f10x_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F10x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f10x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+   frequency (after reset the HSI is used as SYSCLK source)
+   
+   IMPORTANT NOTE:
+   ============== 
+   1. After each device reset the HSI is used as System clock source.
+
+   2. Please make sure that the selected System clock doesn't exceed your device's
+      maximum frequency.
+      
+   3. If none of the define below is enabled, the HSI is used as System clock
+    source.
+
+   4. The System clock configuration functions provided within this file assume that:
+        - For Low, Medium and High density Value line devices an external 8MHz 
+          crystal is used to drive the System clock.
+        - For Low, Medium and High density devices an external 8MHz crystal is
+          used to drive the System clock.
+        - For Connectivity line devices an external 25MHz crystal is used to drive
+          the System clock.
+     If you are using different crystal you have to adapt those functions accordingly.
+    */
+    
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz  24000000
+#else
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000 */ 
+/* #define SYSCLK_FREQ_36MHz  36000000 */
+/* #define SYSCLK_FREQ_48MHz  48000000 */
+/* #define SYSCLK_FREQ_56MHz  56000000 */
+#define SYSCLK_FREQ_72MHz  72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+  static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_XX */
+    
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+           
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+  SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */ 
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+  required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114;
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
+  RCC->APB2ENR = 0x000001E0;
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BB;  
+  GPIOD->CRH = 0xBBBBBBBB;
+
+  GPIOE->CRL = 0xB44444BB;  
+  GPIOE->CRH = 0xBBBBBBBB;
+
+  GPIOF->CRL = 0x44BBBBBB;  
+  GPIOF->CRH = 0xBBBB4444;
+
+  GPIOG->CRL = 0x44BBBBBB;  
+  GPIOG->CRH = 0x44444B44;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4] = 0x00001011;
+  FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }  
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 0 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
+#endif
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else    
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_XX */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo36(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+        
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 1 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+       
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
+  *         and PCLK1 prescalers. 
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock 
+         configuration. User can add here some code to deal with this error */
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f37x.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f37x.c
new file mode 100644
index 0000000..943f188
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32f37x.c
@@ -0,0 +1,380 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f37x.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F37x devices,
+  *          and is generated by the clock configuration tool  
+  *          STM32f37x_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f37x.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f37x.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can
+  *    add some code to deal with this issue inside the SetSysClock() function.      
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" defined
+  *    in "stm32f37x.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         Supported STM32F37x device                          
+  *=============================================================================
+ *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 72000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 72000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *----------------------------------------------------------------------------
+  *        PLLMUL                                 | 9
+  *-----------------------------------------------------------------------------
+  *        PREDIV                                 | 1
+  *-----------------------------------------------------------------------------
+  *        USB Clock                              | ENABLE
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 2
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32F37x_System
+  * @{
+  */  
+  
+/** @addtogroup STM32F37x_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f37x.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */  
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 72000000;
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F37x_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontrollers system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{ 
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+   
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, SDADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x00FF0000;
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+  /* Reset PREDIV1[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+  /* Reset USARTSW[1:0], I2CSW and CECSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0F8C;
+  
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+  
+/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+  
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect. 
+  *             
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f37x.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f37x.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.  
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+        /* HSE oscillator clock selected as PREDIV1 clock entry */
+        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+      }      
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).             
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer and set Flash Latency */
+    FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+ 
+     /* HCLK = SYSCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+       
+     /* PCLK2 = HCLK / 1 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+     
+     /* PCLK1 = HCLK / 2 */
+     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /* PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32l1xx.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32l1xx.c
new file mode 100644
index 0000000..1be659d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/system_stm32l1xx.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32L1xx Ultra
+  *          Low Power devices, and is generated by the clock configuration
+  *          tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l1xx_xx.s" file.
+  *                        
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.   
+  *      
+  * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.    
+  *    
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and MSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  * 
+  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+  *    in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  * 
+  * 5. This file configures the system clock as follows:  
+  *=============================================================================
+  *                         System Clock Configuration
+  *=============================================================================
+  *        System Clock source          | PLL(HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK                       | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        HCLK                         | 32000000 Hz
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler               | 1
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency                | 8000000 Hz
+  *-----------------------------------------------------------------------------
+  *        PLL DIV                      | 3
+  *-----------------------------------------------------------------------------
+  *        PLL MUL                      | 12
+  *-----------------------------------------------------------------------------
+  *        VDD                          | 3.3 V
+  *-----------------------------------------------------------------------------
+  *        Vcore                        | 1.8 V (Range 1)
+  *-----------------------------------------------------------------------------
+  *        Flash Latency                | 1 WS
+  *-----------------------------------------------------------------------------
+  *        SDIO clock (SDIOCLK)         | 48000000 Hz
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB clock  | Disabled
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM32L152D_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+  
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+  * @{
+  */
+uint32_t SystemCoreClock    = 32000000;
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t)0x88FFC00C;
+  
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+  /*!< Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+    
+  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+    case 0x04:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x08:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0C:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18)];
+      plldiv = (plldiv >> 22) + 1;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+      SystemCoreClock = (32768 * (1 << (msirange + 1)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash 
+  *         settings.
+  * @note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+    /* Flash 1 wait state */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
+    
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+  
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+  
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+    {
+    }
+        
+    /* HCLK = SYSCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+  
+    /* PCLK2 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK /1*/
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+    
+    /*  PLL configuration */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+                                        RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+    {
+    }
+  }
+  else
+  {
+    /* If HSE fails to start-up, the application will have wrong clock
+       configuration. User can add here some code to deal with this error */
+  }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in SystemInit() function before jump to main.
+  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
+ | PD15 <-> FSMC_D1  |--------------------+ 
+ +-------------------+
+*/
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHBENR   = 0x000080D8;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CC00CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A0A;
+  /* Configure PDx pins speed to 40 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0F0F;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 40 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC00F;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 40 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x00000C00;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00200AAA;
+  /* Configure PGx pins speed to 40 MHz */ 
+  GPIOG->OSPEEDR = 0x00300FFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHBENR    = 0x400080D8;
+
+  /* Configure and enable Bank1_SRAM3 */
+  FSMC_Bank1->BTCR[4]  = 0x00001011;
+  FSMC_Bank1->BTCR[5]  = 0x00000300;
+  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+  Bank1_SRAM3 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 3;
+  p.FSMC_BusTurnAroundDuration = 0;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_desc.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_desc.c
new file mode 100644
index 0000000..ca93915
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_desc.c
@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    usb_desc.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Descriptors for Virtual Com Port Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+
+/* USB Standard Device Descriptor */
+const uint8_t Virtual_Com_Port_DeviceDescriptor[] =
+  {
+    0x12,   /* bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE,     /* bDescriptorType */
+    0x00,
+    0x02,   /* bcdUSB = 2.00 */
+    0x02,   /* bDeviceClass: CDC */
+    0x00,   /* bDeviceSubClass */
+    0x00,   /* bDeviceProtocol */
+    0x40,   /* bMaxPacketSize0 */
+    0x83,
+    0x04,   /* idVendor = 0x0483 */
+    0x40,
+    0x57,   /* idProduct = 0x7540 */
+    0x00,
+    0x02,   /* bcdDevice = 2.00 */
+    1,              /* Index of string descriptor describing manufacturer */
+    2,              /* Index of string descriptor describing product */
+    3,              /* Index of string descriptor describing the device's serial number */
+    0x01    /* bNumConfigurations */
+  };
+
+const uint8_t Virtual_Com_Port_ConfigDescriptor[] =
+  {
+    /*Configuration Descriptor*/
+    0x09,   /* bLength: Configuration Descriptor size */
+    USB_CONFIGURATION_DESCRIPTOR_TYPE,      /* bDescriptorType: Configuration */
+    VIRTUAL_COM_PORT_SIZ_CONFIG_DESC,       /* wTotalLength:no of returned bytes */
+    0x00,
+    0x02,   /* bNumInterfaces: 2 interface */
+    0x01,   /* bConfigurationValue: Configuration value */
+    0x00,   /* iConfiguration: Index of string descriptor describing the configuration */
+    0xC0,   /* bmAttributes: self powered */
+    0x32,   /* MaxPower 0 mA */
+    /*Interface Descriptor*/
+    0x09,   /* bLength: Interface Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,  /* bDescriptorType: Interface */
+    /* Interface descriptor type */
+    0x00,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x01,   /* bNumEndpoints: One endpoints used */
+    0x02,   /* bInterfaceClass: Communication Interface Class */
+    0x02,   /* bInterfaceSubClass: Abstract Control Model */
+    0x01,   /* bInterfaceProtocol: Common AT commands */
+    0x00,   /* iInterface: */
+    /*Header Functional Descriptor*/
+    0x05,   /* bLength: Endpoint Descriptor size */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x00,   /* bDescriptorSubtype: Header Func Desc */
+    0x10,   /* bcdCDC: spec release number */
+    0x01,
+    /*Call Management Functional Descriptor*/
+    0x05,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x01,   /* bDescriptorSubtype: Call Management Func Desc */
+    0x00,   /* bmCapabilities: D0+D1 */
+    0x01,   /* bDataInterface: 1 */
+    /*ACM Functional Descriptor*/
+    0x04,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x02,   /* bDescriptorSubtype: Abstract Control Management desc */
+    0x02,   /* bmCapabilities */
+    /*Union Functional Descriptor*/
+    0x05,   /* bFunctionLength */
+    0x24,   /* bDescriptorType: CS_INTERFACE */
+    0x06,   /* bDescriptorSubtype: Union func desc */
+    0x00,   /* bMasterInterface: Communication class interface */
+    0x01,   /* bSlaveInterface0: Data Class Interface */
+    /*Endpoint 2 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x82,   /* bEndpointAddress: (IN2) */
+    0x03,   /* bmAttributes: Interrupt */
+    VIRTUAL_COM_PORT_INT_SIZE,      /* wMaxPacketSize: */
+    0x00,
+    0xFF,   /* bInterval: */
+    /*Data class interface descriptor*/
+    0x09,   /* bLength: Endpoint Descriptor size */
+    USB_INTERFACE_DESCRIPTOR_TYPE,  /* bDescriptorType: */
+    0x01,   /* bInterfaceNumber: Number of Interface */
+    0x00,   /* bAlternateSetting: Alternate setting */
+    0x02,   /* bNumEndpoints: Two endpoints used */
+    0x0A,   /* bInterfaceClass: CDC */
+    0x00,   /* bInterfaceSubClass: */
+    0x00,   /* bInterfaceProtocol: */
+    0x00,   /* iInterface: */
+    /*Endpoint 3 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x03,   /* bEndpointAddress: (OUT3) */
+    0x02,   /* bmAttributes: Bulk */
+    VIRTUAL_COM_PORT_DATA_SIZE,             /* wMaxPacketSize: */
+    0x00,
+    0x00,   /* bInterval: ignore for Bulk transfer */
+    /*Endpoint 1 Descriptor*/
+    0x07,   /* bLength: Endpoint Descriptor size */
+    USB_ENDPOINT_DESCRIPTOR_TYPE,   /* bDescriptorType: Endpoint */
+    0x81,   /* bEndpointAddress: (IN1) */
+    0x02,   /* bmAttributes: Bulk */
+    VIRTUAL_COM_PORT_DATA_SIZE,             /* wMaxPacketSize: */
+    0x00,
+    0x00    /* bInterval */
+  };
+
+/* USB String Descriptors */
+const uint8_t Virtual_Com_Port_StringLangID[VIRTUAL_COM_PORT_SIZ_STRING_LANGID] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_LANGID,
+    USB_STRING_DESCRIPTOR_TYPE,
+    0x09,
+    0x04 /* LangID = 0x0409: U.S. English */
+  };
+
+const uint8_t Virtual_Com_Port_StringVendor[VIRTUAL_COM_PORT_SIZ_STRING_VENDOR] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_VENDOR,     /* Size of Vendor string */
+    USB_STRING_DESCRIPTOR_TYPE,             /* bDescriptorType*/
+    /* Manufacturer: "STMicroelectronics" */
+    'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+    'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+    'c', 0, 's', 0
+  };
+
+const uint8_t Virtual_Com_Port_StringProduct[VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT,          /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,        /* bDescriptorType */
+    /* Product name: "STM32 Virtual COM Port" */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0, ' ', 0, 'V', 0, 'i', 0,
+    'r', 0, 't', 0, 'u', 0, 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0,
+    'M', 0, ' ', 0, 'P', 0, 'o', 0, 'r', 0, 't', 0, ' ', 0, ' ', 0
+  };
+
+uint8_t Virtual_Com_Port_StringSerial[VIRTUAL_COM_PORT_SIZ_STRING_SERIAL] =
+  {
+    VIRTUAL_COM_PORT_SIZ_STRING_SERIAL,           /* bLength */
+    USB_STRING_DESCRIPTOR_TYPE,                   /* bDescriptorType */
+    'S', 0, 'T', 0, 'M', 0, '3', 0, '2', 0
+  };
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_endp.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_endp.c
new file mode 100644
index 0000000..b662cfe
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_endp.c
@@ -0,0 +1,144 @@
+/**
+  ******************************************************************************
+  * @file    usb_endp.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Endpoint routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_desc.h"
+#include "usb_mem.h"
+#include "hw_config.h"
+#include "usb_istr.h"
+#include "usb_pwr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Interval between sending IN packets in frame number (1 frame = 1ms) */
+#define VCOMPORT_IN_FRAME_INTERVAL             5
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t USB_Rx_Buffer[VIRTUAL_COM_PORT_DATA_SIZE];
+extern  uint8_t USART_Rx_Buffer[];
+extern uint32_t USART_Rx_ptr_out;
+extern uint32_t USART_Rx_length;
+extern uint8_t  USB_Tx_State;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : EP1_IN_Callback
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP1_IN_Callback (void)
+{
+  uint16_t USB_Tx_ptr;
+  uint16_t USB_Tx_length;
+  
+  if (USB_Tx_State == 1)
+  {
+    if (USART_Rx_length == 0) 
+    {
+      USB_Tx_State = 0;
+    }
+    else 
+    {
+      if (USART_Rx_length > VIRTUAL_COM_PORT_DATA_SIZE){
+        USB_Tx_ptr = USART_Rx_ptr_out;
+        USB_Tx_length = VIRTUAL_COM_PORT_DATA_SIZE;
+        
+        USART_Rx_ptr_out += VIRTUAL_COM_PORT_DATA_SIZE;
+        USART_Rx_length -= VIRTUAL_COM_PORT_DATA_SIZE;    
+      }
+      else 
+      {
+        USB_Tx_ptr = USART_Rx_ptr_out;
+        USB_Tx_length = USART_Rx_length;
+        
+        USART_Rx_ptr_out += USART_Rx_length;
+        USART_Rx_length = 0;
+      }
+      UserToPMABufferCopy(&USART_Rx_Buffer[USB_Tx_ptr], ENDP1_TXADDR, USB_Tx_length);
+      SetEPTxCount(ENDP1, USB_Tx_length);
+      SetEPTxValid(ENDP1); 
+    }
+  }
+}
+
+/*******************************************************************************
+* Function Name  : EP3_OUT_Callback
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void EP3_OUT_Callback(void)
+{
+  uint16_t USB_Rx_Cnt;
+  
+  /* Get the received data buffer and update the counter */
+  USB_Rx_Cnt = USB_SIL_Read(EP3_OUT, USB_Rx_Buffer);
+  
+  /* USB data will be immediately processed, this allow next USB traffic being 
+  NAKed till the end of the USART Xfer */
+  
+  USB_To_USART_Send_Data(USB_Rx_Buffer, USB_Rx_Cnt);
+ 
+  /* Enable the receive of data on EP3 */
+  SetEPRxValid(ENDP3);
+}
+
+
+/*******************************************************************************
+* Function Name  : SOF_Callback / INTR_SOFINTR_Callback
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void SOF_Callback(void)
+{
+  static uint32_t FrameCount = 0;
+  
+  if(bDeviceState == CONFIGURED)
+  {
+    if (FrameCount++ == VCOMPORT_IN_FRAME_INTERVAL)
+    {
+      /* Reset the frame counter */
+      FrameCount = 0;
+      
+      /* Check the data to be sent through IN pipe */
+      Handle_USBAsynchXfer();
+    }
+  }  
+}
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_istr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_istr.c
new file mode 100644
index 0000000..41166a9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_istr.c
@@ -0,0 +1,233 @@
+/**
+  ******************************************************************************
+  * @file    usb_istr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   ISTR events interrupt service routines
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_prop.h"
+#include "usb_pwr.h"
+#include "usb_istr.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t wIstr;  /* ISTR register last read value */
+__IO uint8_t bIntPackSOF = 0;  /* SOFs received between 2 consecutive packets */
+__IO uint32_t esof_counter =0; /* expected SOF counter */
+__IO uint32_t wCNTR=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* function pointers to non-control endpoints service routines */
+void (*pEpInt_IN[7])(void) =
+  {
+    EP1_IN_Callback,
+    EP2_IN_Callback,
+    EP3_IN_Callback,
+    EP4_IN_Callback,
+    EP5_IN_Callback,
+    EP6_IN_Callback,
+    EP7_IN_Callback,
+  };
+
+void (*pEpInt_OUT[7])(void) =
+  {
+    EP1_OUT_Callback,
+    EP2_OUT_Callback,
+    EP3_OUT_Callback,
+    EP4_OUT_Callback,
+    EP5_OUT_Callback,
+    EP6_OUT_Callback,
+    EP7_OUT_Callback,
+  };
+
+/*******************************************************************************
+* Function Name  : USB_Istr
+* Description    : ISTR events interrupt service routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void USB_Istr(void)
+{
+    uint32_t i=0;
+ __IO uint32_t EP[8];
+  
+  wIstr = _GetISTR();
+
+#if (IMR_MSK & ISTR_SOF)
+  if (wIstr & ISTR_SOF & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_SOF);
+    bIntPackSOF++;
+
+#ifdef SOF_CALLBACK
+    SOF_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
+  
+#if (IMR_MSK & ISTR_CTR)
+  if (wIstr & ISTR_CTR & wInterrupt_Mask)
+  {
+    /* servicing of the endpoint correct transfer interrupt */
+    /* clear of the CTR flag into the sub */
+    CTR_LP();
+#ifdef CTR_CALLBACK
+    CTR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/  
+#if (IMR_MSK & ISTR_RESET)
+  if (wIstr & ISTR_RESET & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_RESET);
+    Device_Property.Reset();
+#ifdef RESET_CALLBACK
+    RESET_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_DOVR)
+  if (wIstr & ISTR_DOVR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_DOVR);
+#ifdef DOVR_CALLBACK
+    DOVR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_ERR)
+  if (wIstr & ISTR_ERR & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_ERR);
+#ifdef ERR_CALLBACK
+    ERR_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_WKUP)
+  if (wIstr & ISTR_WKUP & wInterrupt_Mask)
+  {
+    _SetISTR((uint16_t)CLR_WKUP);
+    Resume(RESUME_EXTERNAL);
+#ifdef WKUP_CALLBACK
+    WKUP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+#if (IMR_MSK & ISTR_SUSP)
+  if (wIstr & ISTR_SUSP & wInterrupt_Mask)
+  {
+
+    /* check if SUSPEND is possible */
+    if (fSuspendEnabled)
+    {
+      Suspend();
+    }
+    else
+    {
+      /* if not possible then resume after xx ms */
+      Resume(RESUME_LATER);
+    }
+    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+    _SetISTR((uint16_t)CLR_SUSP);
+#ifdef SUSP_CALLBACK
+    SUSP_Callback();
+#endif
+  }
+#endif
+  /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
+
+#if (IMR_MSK & ISTR_ESOF)
+  if (wIstr & ISTR_ESOF & wInterrupt_Mask)
+  {
+    /* clear ESOF flag in ISTR */
+    _SetISTR((uint16_t)CLR_ESOF);
+    
+    if ((_GetFNR()&FNR_RXDP)!=0)
+    {
+      /* increment ESOF counter */
+      esof_counter ++;
+      
+      /* test if we enter in ESOF more than 3 times with FSUSP =0 and RXDP =1=>> possible missing SUSP flag*/
+      if ((esof_counter >3)&&((_GetCNTR()&CNTR_FSUSP)==0))
+      {           
+        /* this a sequence to apply a force RESET*/
+      
+        /*Store CNTR value */
+        wCNTR = _GetCNTR(); 
+      
+        /*Store endpoints registers status */
+        for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+      
+        /*apply FRES */
+        wCNTR|=CNTR_FRES;
+        _SetCNTR(wCNTR);
+ 
+        /*clear FRES*/
+        wCNTR&=~CNTR_FRES;
+        _SetCNTR(wCNTR);
+      
+        /*poll for RESET flag in ISTR*/
+        while((_GetISTR()&ISTR_RESET) == 0);
+  
+        /* clear RESET flag in ISTR */
+        _SetISTR((uint16_t)CLR_RESET);
+   
+       /*restore Enpoints*/
+        for (i=0;i<8;i++)
+        _SetENDPOINT(i, EP[i]);
+      
+        esof_counter = 0;
+      }
+    }
+    else
+    {
+        esof_counter = 0;
+    }
+    
+    /* resume handling timing is made with ESOFs */
+    Resume(RESUME_ESOF); /* request without change of the machine state */
+
+#ifdef ESOF_CALLBACK
+    ESOF_Callback();
+#endif
+  }
+#endif
+} /* USB_Istr */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_prop.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_prop.c
new file mode 100644
index 0000000..6a59c1a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_prop.c
@@ -0,0 +1,418 @@
+/**
+  ******************************************************************************
+  * @file    usb_prop.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   All processing related to Virtual Com Port Demo
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_prop.h"
+#include "usb_desc.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint8_t Request = 0;
+
+LINE_CODING linecoding =
+  {
+    115200, /* baud rate*/
+    0x00,   /* stop bits-1*/
+    0x00,   /* parity - none*/
+    0x08    /* no. of bits 8*/
+  };
+
+/* -------------------------------------------------------------------------- */
+/*  Structures initializations */
+/* -------------------------------------------------------------------------- */
+
+DEVICE Device_Table =
+  {
+    EP_NUM,
+    1
+  };
+
+DEVICE_PROP Device_Property =
+  {
+    Virtual_Com_Port_init,
+    Virtual_Com_Port_Reset,
+    Virtual_Com_Port_Status_In,
+    Virtual_Com_Port_Status_Out,
+    Virtual_Com_Port_Data_Setup,
+    Virtual_Com_Port_NoData_Setup,
+    Virtual_Com_Port_Get_Interface_Setting,
+    Virtual_Com_Port_GetDeviceDescriptor,
+    Virtual_Com_Port_GetConfigDescriptor,
+    Virtual_Com_Port_GetStringDescriptor,
+    0,
+    0x40 /*MAX PACKET SIZE*/
+  };
+
+USER_STANDARD_REQUESTS User_Standard_Requests =
+  {
+    Virtual_Com_Port_GetConfiguration,
+    Virtual_Com_Port_SetConfiguration,
+    Virtual_Com_Port_GetInterface,
+    Virtual_Com_Port_SetInterface,
+    Virtual_Com_Port_GetStatus,
+    Virtual_Com_Port_ClearFeature,
+    Virtual_Com_Port_SetEndPointFeature,
+    Virtual_Com_Port_SetDeviceFeature,
+    Virtual_Com_Port_SetDeviceAddress
+  };
+
+ONE_DESCRIPTOR Device_Descriptor =
+  {
+    (uint8_t*)Virtual_Com_Port_DeviceDescriptor,
+    VIRTUAL_COM_PORT_SIZ_DEVICE_DESC
+  };
+
+ONE_DESCRIPTOR Config_Descriptor =
+  {
+    (uint8_t*)Virtual_Com_Port_ConfigDescriptor,
+    VIRTUAL_COM_PORT_SIZ_CONFIG_DESC
+  };
+
+ONE_DESCRIPTOR String_Descriptor[4] =
+  {
+    {(uint8_t*)Virtual_Com_Port_StringLangID, VIRTUAL_COM_PORT_SIZ_STRING_LANGID},
+    {(uint8_t*)Virtual_Com_Port_StringVendor, VIRTUAL_COM_PORT_SIZ_STRING_VENDOR},
+    {(uint8_t*)Virtual_Com_Port_StringProduct, VIRTUAL_COM_PORT_SIZ_STRING_PRODUCT},
+    {(uint8_t*)Virtual_Com_Port_StringSerial, VIRTUAL_COM_PORT_SIZ_STRING_SERIAL}
+  };
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_init.
+* Description    : Virtual COM Port Mouse init routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_init(void)
+{
+
+  /* Update the serial number string descriptor with the data from the unique
+  ID*/
+  Get_SerialNum();
+
+  pInformation->Current_Configuration = 0;
+
+  /* Connect the device */
+  PowerOn();
+
+  /* Perform basic device initialization operations */
+  USB_SIL_Init();
+
+  /* configure the USART to the default settings */
+  USART_Config_Default();
+
+  bDeviceState = UNCONNECTED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Reset
+* Description    : Virtual_Com_Port Mouse reset routine
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Reset(void)
+{
+  /* Set Virtual_Com_Port DEVICE as not configured */
+  pInformation->Current_Configuration = 0;
+
+  /* Current Feature initialization */
+  pInformation->Current_Feature = Virtual_Com_Port_ConfigDescriptor[7];
+
+  /* Set Virtual_Com_Port DEVICE with the default Interface*/
+  pInformation->Current_Interface = 0;
+
+  SetBTABLE(BTABLE_ADDRESS);
+
+  /* Initialize Endpoint 0 */
+  SetEPType(ENDP0, EP_CONTROL);
+  SetEPTxStatus(ENDP0, EP_TX_STALL);
+  SetEPRxAddr(ENDP0, ENDP0_RXADDR);
+  SetEPTxAddr(ENDP0, ENDP0_TXADDR);
+  Clear_Status_Out(ENDP0);
+  SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+  SetEPRxValid(ENDP0);
+
+  /* Initialize Endpoint 1 */
+  SetEPType(ENDP1, EP_BULK);
+  SetEPTxAddr(ENDP1, ENDP1_TXADDR);
+  SetEPTxStatus(ENDP1, EP_TX_NAK);
+  SetEPRxStatus(ENDP1, EP_RX_DIS);
+
+  /* Initialize Endpoint 2 */
+  SetEPType(ENDP2, EP_INTERRUPT);
+  SetEPTxAddr(ENDP2, ENDP2_TXADDR);
+  SetEPRxStatus(ENDP2, EP_RX_DIS);
+  SetEPTxStatus(ENDP2, EP_TX_NAK);
+
+  /* Initialize Endpoint 3 */
+  SetEPType(ENDP3, EP_BULK);
+  SetEPRxAddr(ENDP3, ENDP3_RXADDR);
+  SetEPRxCount(ENDP3, VIRTUAL_COM_PORT_DATA_SIZE);
+  SetEPRxStatus(ENDP3, EP_RX_VALID);
+  SetEPTxStatus(ENDP3, EP_TX_DIS);
+
+  /* Set this device to response on default address */
+  SetDeviceAddress(0);
+  
+  bDeviceState = ATTACHED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetConfiguration.
+* Description    : Update the device state to configured.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_SetConfiguration(void)
+{
+  DEVICE_INFO *pInfo = &Device_Info;
+
+  if (pInfo->Current_Configuration != 0)
+  {
+    /* Device configured */
+    bDeviceState = CONFIGURED;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetConfiguration.
+* Description    : Update the device state to addressed.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_SetDeviceAddress (void)
+{
+  bDeviceState = ADDRESSED;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Status_In.
+* Description    : Virtual COM Port Status In Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Status_In(void)
+{
+  if (Request == SET_LINE_CODING)
+  {
+    USART_Config();
+    Request = 0;
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Status_Out
+* Description    : Virtual COM Port Status OUT Routine.
+* Input          : None.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Virtual_Com_Port_Status_Out(void)
+{}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Data_Setup
+* Description    : handle the data class specific requests
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Virtual_Com_Port_Data_Setup(uint8_t RequestNo)
+{
+  uint8_t    *(*CopyRoutine)(uint16_t);
+
+  CopyRoutine = NULL;
+
+  if (RequestNo == GET_LINE_CODING)
+  {
+    if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+    {
+      CopyRoutine = Virtual_Com_Port_GetLineCoding;
+    }
+  }
+  else if (RequestNo == SET_LINE_CODING)
+  {
+    if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+    {
+      CopyRoutine = Virtual_Com_Port_SetLineCoding;
+    }
+    Request = SET_LINE_CODING;
+  }
+
+  if (CopyRoutine == NULL)
+  {
+    return USB_UNSUPPORT;
+  }
+
+  pInformation->Ctrl_Info.CopyData = CopyRoutine;
+  pInformation->Ctrl_Info.Usb_wOffset = 0;
+  (*CopyRoutine)(0);
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_NoData_Setup.
+* Description    : handle the no data class specific requests.
+* Input          : Request Nb.
+* Output         : None.
+* Return         : USB_UNSUPPORT or USB_SUCCESS.
+*******************************************************************************/
+RESULT Virtual_Com_Port_NoData_Setup(uint8_t RequestNo)
+{
+
+  if (Type_Recipient == (CLASS_REQUEST | INTERFACE_RECIPIENT))
+  {
+    if (RequestNo == SET_COMM_FEATURE)
+    {
+      return USB_SUCCESS;
+    }
+    else if (RequestNo == SET_CONTROL_LINE_STATE)
+    {
+      return USB_SUCCESS;
+    }
+  }
+
+  return USB_UNSUPPORT;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetDeviceDescriptor.
+* Description    : Gets the device descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the device descriptor.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetDeviceDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Device_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetConfigDescriptor.
+* Description    : get the configuration descriptor.
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the configuration descriptor.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetConfigDescriptor(uint16_t Length)
+{
+  return Standard_GetDescriptorData(Length, &Config_Descriptor);
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetStringDescriptor
+* Description    : Gets the string descriptors according to the needed index
+* Input          : Length.
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetStringDescriptor(uint16_t Length)
+{
+  uint8_t wValue0 = pInformation->USBwValue0;
+  if (wValue0 > 4)
+  {
+    return NULL;
+  }
+  else
+  {
+    return Standard_GetDescriptorData(Length, &String_Descriptor[wValue0]);
+  }
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_Get_Interface_Setting.
+* Description    : test the interface and the alternate setting according to the
+*                  supported one.
+* Input1         : uint8_t: Interface : interface number.
+* Input2         : uint8_t: AlternateSetting : Alternate Setting number.
+* Output         : None.
+* Return         : The address of the string descriptors.
+*******************************************************************************/
+RESULT Virtual_Com_Port_Get_Interface_Setting(uint8_t Interface, uint8_t AlternateSetting)
+{
+  if (AlternateSetting > 0)
+  {
+    return USB_UNSUPPORT;
+  }
+  else if (Interface > 1)
+  {
+    return USB_UNSUPPORT;
+  }
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_GetLineCoding.
+* Description    : send the linecoding structure to the PC host.
+* Input          : Length.
+* Output         : None.
+* Return         : Linecoding structure base address.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_GetLineCoding(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(linecoding);
+    return NULL;
+  }
+  return(uint8_t *)&linecoding;
+}
+
+/*******************************************************************************
+* Function Name  : Virtual_Com_Port_SetLineCoding.
+* Description    : Set the linecoding structure fields.
+* Input          : Length.
+* Output         : None.
+* Return         : Linecoding structure base address.
+*******************************************************************************/
+uint8_t *Virtual_Com_Port_SetLineCoding(uint16_t Length)
+{
+  if (Length == 0)
+  {
+    pInformation->Ctrl_Info.Usb_wLength = sizeof(linecoding);
+    return NULL;
+  }
+  return(uint8_t *)&linecoding;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_pwr.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_pwr.c
new file mode 100644
index 0000000..a2253a8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Projects/Virtual_COM_Port/src/usb_pwr.c
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    usb_pwr.c
+  * @author  MCD Application Team
+  * @version V4.0.0
+  * @date    21-January-2013
+  * @brief   Connection/disconnection & power management
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+#include "usb_conf.h"
+#include "usb_pwr.h"
+#include "hw_config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t bDeviceState = UNCONNECTED; /* USB device status */
+__IO bool fSuspendEnabled = TRUE;  /* true when suspend is possible */
+__IO uint32_t EP[8];
+
+struct
+{
+  __IO RESUME_STATE eState;
+  __IO uint8_t bESOFcnt;
+}
+ResumeS;
+
+__IO uint32_t remotewakeupon=0;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Extern function prototypes ------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name  : PowerOn
+* Description    :
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOn(void)
+{
+  uint16_t wRegVal;
+
+  /*** cable plugged-in ? ***/
+  USB_Cable_Config(ENABLE);
+
+  /*** CNTR_PWDN = 0 ***/
+  wRegVal = CNTR_FRES;
+  _SetCNTR(wRegVal);
+
+  /*** CNTR_FRES = 0 ***/
+  wInterrupt_Mask = 0;
+  _SetCNTR(wInterrupt_Mask);
+  /*** Clear pending interrupts ***/
+  _SetISTR(0);
+  /*** Set interrupt mask ***/
+  wInterrupt_Mask = CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM;
+  _SetCNTR(wInterrupt_Mask);
+  
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : PowerOff
+* Description    : handles switch-off conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+RESULT PowerOff()
+{
+  /* disable all interrupts and force USB reset */
+  _SetCNTR(CNTR_FRES);
+  /* clear interrupt status register */
+  _SetISTR(0);
+  /* Disable the Pull-Up*/
+  USB_Cable_Config(DISABLE);
+  /* switch-off device */
+  _SetCNTR(CNTR_FRES + CNTR_PDWN);
+  /* sw variables reset */
+  /* ... */
+
+  return USB_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name  : Suspend
+* Description    : sets suspend mode operating conditions
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Suspend(void)
+{
+	uint32_t i =0;
+	uint16_t wCNTR;
+	uint32_t tmpreg = 0;
+  __IO uint32_t savePWR_CR=0;
+	/* suspend preparation */
+	/* ... */
+	
+	/*Store CNTR value */
+	wCNTR = _GetCNTR();  
+
+    /* This a sequence to apply a force RESET to handle a robustness case */
+    
+	/*Store endpoints registers status */
+    for (i=0;i<8;i++) EP[i] = _GetENDPOINT(i);
+	
+	/* unmask RESET flag */
+	wCNTR|=CNTR_RESETM;
+	_SetCNTR(wCNTR);
+	
+	/*apply FRES */
+	wCNTR|=CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*clear FRES*/
+	wCNTR&=~CNTR_FRES;
+	_SetCNTR(wCNTR);
+	
+	/*poll for RESET flag in ISTR*/
+	while((_GetISTR()&ISTR_RESET) == 0);
+	
+	/* clear RESET flag in ISTR */
+	_SetISTR((uint16_t)CLR_RESET);
+	
+	/*restore Enpoints*/
+	for (i=0;i<8;i++)
+	_SetENDPOINT(i, EP[i]);
+	
+	/* Now it is safe to enter macrocell in suspend mode */
+	wCNTR |= CNTR_FSUSP;
+	_SetCNTR(wCNTR);
+	
+	/* force low-power mode in the macrocell */
+	wCNTR = _GetCNTR();
+	wCNTR |= CNTR_LPMODE;
+	_SetCNTR(wCNTR);
+	
+	/*prepare entry in low power mode (STOP mode)*/
+	/* Select the regulator state in STOP mode*/
+	savePWR_CR = PWR->CR;
+	tmpreg = PWR->CR;
+	/* Clear PDDS and LPDS bits */
+	tmpreg &= ((uint32_t)0xFFFFFFFC);
+	/* Set LPDS bit according to PWR_Regulator value */
+	tmpreg |= PWR_Regulator_LowPower;
+	/* Store the new value */
+	PWR->CR = tmpreg;
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+        SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#else
+        SCB->SCR |= SCB_SCR_SLEEPDEEP;       
+#endif
+	
+	/* enter system in STOP mode, only when wakeup flag in not set */
+	if((_GetISTR()&ISTR_WKUP)==0)
+	{
+		__WFI();
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 
+#endif
+	}
+	else
+	{
+		/* Clear Wakeup flag */
+		_SetISTR(CLR_WKUP);
+		/* clear FSUSP to abort entry in suspend mode  */
+        wCNTR = _GetCNTR();
+        wCNTR&=~CNTR_FSUSP;
+        _SetCNTR(wCNTR);
+		
+		/*restore sleep mode configuration */ 
+		/* restore Power regulator config in sleep mode*/
+		PWR->CR = savePWR_CR;
+		
+		/* Reset SLEEPDEEP bit of Cortex System Control Register */
+#if defined (STM32F30X) || defined (STM32F37X)		
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#else
+                SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+#endif
+    }
+}
+
+/*******************************************************************************
+* Function Name  : Resume_Init
+* Description    : Handles wake-up restoring normal operations
+* Input          : None.
+* Output         : None.
+* Return         : USB_SUCCESS.
+*******************************************************************************/
+void Resume_Init(void)
+{
+  uint16_t wCNTR;
+  
+  /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
+  /* restart the clocks */
+  /* ...  */
+
+  /* CNTR_LPMODE = 0 */
+  wCNTR = _GetCNTR();
+  wCNTR &= (~CNTR_LPMODE);
+  _SetCNTR(wCNTR);    
+  
+  /* restore full power */
+  /* ... on connected devices */
+  Leave_LowPowerMode();
+
+  /* reset FSUSP bit */
+  _SetCNTR(IMR_MSK);
+
+  /* reverse suspend preparation */
+  /* ... */ 
+
+}
+
+/*******************************************************************************
+* Function Name  : Resume
+* Description    : This is the state machine handling resume operations and
+*                 timing sequence. The control is based on the Resume structure
+*                 variables and on the ESOF interrupt calling this subroutine
+*                 without changing machine state.
+* Input          : a state machine value (RESUME_STATE)
+*                  RESUME_ESOF doesn't change ResumeS.eState allowing
+*                  decrementing of the ESOF counter in different states.
+* Output         : None.
+* Return         : None.
+*******************************************************************************/
+void Resume(RESUME_STATE eResumeSetVal)
+{
+  uint16_t wCNTR;
+
+  if (eResumeSetVal != RESUME_ESOF)
+    ResumeS.eState = eResumeSetVal;
+  switch (ResumeS.eState)
+  {
+    case RESUME_EXTERNAL:
+      if (remotewakeupon ==0)
+      {
+        Resume_Init();
+        ResumeS.eState = RESUME_OFF;
+      }
+      else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
+      {
+        ResumeS.eState = RESUME_ON;
+      }
+      break;
+    case RESUME_INTERNAL:
+      Resume_Init();
+      ResumeS.eState = RESUME_START;
+      remotewakeupon = 1;
+      break;
+    case RESUME_LATER:
+      ResumeS.bESOFcnt = 2;
+      ResumeS.eState = RESUME_WAIT;
+      break;
+    case RESUME_WAIT:
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+        ResumeS.eState = RESUME_START;
+      break;
+    case RESUME_START:
+      wCNTR = _GetCNTR();
+      wCNTR |= CNTR_RESUME;
+      _SetCNTR(wCNTR);
+      ResumeS.eState = RESUME_ON;
+      ResumeS.bESOFcnt = 10;
+      break;
+    case RESUME_ON:    
+      ResumeS.bESOFcnt--;
+      if (ResumeS.bESOFcnt == 0)
+      {
+        wCNTR = _GetCNTR();
+        wCNTR &= (~CNTR_RESUME);
+        _SetCNTR(wCNTR);
+        ResumeS.eState = RESUME_OFF;
+        remotewakeupon = 0;
+      }
+      break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+      ResumeS.eState = RESUME_OFF;
+      break;
+  }
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/TrueSTUDIO_elf2bin.bat b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/TrueSTUDIO_elf2bin.bat
new file mode 100644
index 0000000..b3e3fe8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/TrueSTUDIO_elf2bin.bat
@@ -0,0 +1,10 @@
+@echo off
+
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210C-EVAL\Debug\STM3210C-EVAL.elf  ("arm-elf-objcopy.exe" -O binary ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210C-EVAL\Debug\STM3210C-EVAL.elf" ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210C-EVAL\Debug\STM3210C-EVAL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210B-EVAL\Debug\STM3210B-EVAL.elf  ("arm-elf-objcopy.exe" -O binary ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210B-EVAL\Debug\STM3210B-EVAL.elf" ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210B-EVAL\Debug\STM3210B-EVAL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL\Debug\STM3210E-EVAL.elf  ("arm-elf-objcopy.exe" -O binary ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL\Debug\STM3210E-EVAL.elf" ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL\Debug\STM3210E-EVAL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL_XL\Debug\STM32F10X_XL.elf    ("arm-elf-objcopy.exe" -O binary ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL_XL\Debug\STM32F10X_XL.elf" ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM3210E-EVAL_XL\Debug\STM32F10X_XL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM32L152-EVAL\Debug\STM32L152-EVAL.elf  ("arm-elf-objcopy.exe" -O binary ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM32L152-EVAL\Debug\STM32L152-EVAL.elf" ".\..\..\Project\Device_Firmware_Upgrade\binary_template\TrueSTUDIO\STM32L152-EVAL\Debug\STM32L152-EVAL_SysTick.bin")
+
+pause
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/arm-elf-objcopy.exe b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/arm-elf-objcopy.exe
new file mode 100644
index 0000000..46553ff
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/arm-elf-objcopy.exe
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/axftobin.bat b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/axftobin.bat
new file mode 100644
index 0000000..4a3becc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/axftobin.bat
@@ -0,0 +1,6 @@
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL_XL\STM3210E-EVAL_XL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL_XL\STM3210E-EVAL_XL.axf" --bin --output ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL_XL\STM3210E-EVAL_XL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210B-EVAL\STM3210B-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210B-EVAL\STM3210B-EVAL.axf" --bin --output ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210B-EVAL\STM3210B-EVAL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL\STM3210E-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL\STM3210E-EVAL.axf" --bin --output ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210E-EVAL\STM3210E-EVAL_SysTick.bin") 
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210C-EVAL\STM3210C-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210C-EVAL\STM3210C-EVAL.axf" --bin --output ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM3210C-EVAL\STM3210C-EVAL_SysTick.bin")
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM32L152-EVAL\STM32L152-EVAL.axf (C:\Keil\ARM\BIN40\fromelf.exe ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM32L152-EVAL\STM32L152-EVAL.axf" --bin --output ".\..\..\Project\Device_Firmware_Upgrade\binary_template\MDK-ARM\STM32L152-EVAL\STM32L152-EVAL_SysTick.bin")
+pause
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/cygwin1.dll b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/cygwin1.dll
new file mode 100644
index 0000000..984dd61
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/cygwin1.dll
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/hextobin.bat b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/hextobin.bat
new file mode 100644
index 0000000..cee45c5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/Binary/hextobin.bat
@@ -0,0 +1,12 @@
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210E-EVAL\SysTick.hex (hex2bin.exe  .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210E-EVAL\SysTick.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210B-EVAL\SysTick.hex (hex2bin.exe  .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210B-EVAL\SysTick.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210C-EVAL\SysTick.hex (hex2bin.exe  .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210C-EVAL\SysTick.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210E-EVAL_XL\SysTick.hex (hex2bin.exe  .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM3210E-EVAL_XL\SysTick.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM32L152-EVAL\SysTick.hex (hex2bin.exe  .\..\..\Project\Device_Firmware_Upgrade\binary_template\RIDE\STM32L152-EVAL\SysTick.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210B-EVAL\Project.hex  (hex2bin.exe   .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210B-EVAL\Project.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210C-EVAL\Project.hex  (hex2bin.exe   .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210C-EVAL\Project.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210E-EVAL\Project.hex  (hex2bin.exe   .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210E-EVAL\Project.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210E-EVAL_XL\Project.hex (hex2bin.exe .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM3210E-EVAL_XL\Project.hex)
+if exist .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM32L152-EVAL\Project.hex  (hex2bin.exe   .\..\..\Project\Device_Firmware_Upgrade\binary_template\HiTOP\STM32L152-EVAL\Project.hex)
+
+pause
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_AudioSpeaker.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_AudioSpeaker.dfu
new file mode 100644
index 0000000..b6f599c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_AudioSpeaker.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_JoystickMouse.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_JoystickMouse.dfu
new file mode 100644
index 0000000..0fd3c5f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_JoystickMouse.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..580081e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..c3fba6d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210B-EVAL_VirtualComport_Loopback.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_AudioSpeaker.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_AudioSpeaker.dfu
new file mode 100644
index 0000000..3081a9c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_AudioSpeaker.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_Composite_Example.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_Composite_Example.dfu
new file mode 100644
index 0000000..9ccfa8c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_Composite_Example.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_MassStorage.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_MassStorage.dfu
new file mode 100644
index 0000000..b649ba8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_MassStorage.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_AudioSpeaker.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_AudioSpeaker.dfu
new file mode 100644
index 0000000..3081a9c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_AudioSpeaker.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_Composite_Example.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_Composite_Example.dfu
new file mode 100644
index 0000000..d0c4284
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_Composite_Example.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_JoyStickMouse.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_JoyStickMouse.dfu
new file mode 100644
index 0000000..f161c91
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_JoyStickMouse.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_MassStorage.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_MassStorage.dfu
new file mode 100644
index 0000000..b649ba8
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_MassStorage.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..597cd0e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..1f85bfb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM3210E-EVAL_XL_VirtualComport_Loopback.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_CustomHID.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_CustomHID.dfu
new file mode 100644
index 0000000..4dcc9a2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_CustomHID.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_MassStorage.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_MassStorage.dfu
new file mode 100644
index 0000000..c927ebc
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_MassStorage.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..e14ff75
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..fec8ef3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32303C-EVAL_VirtualComport_Loopback.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_CustomHID.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_CustomHID.dfu
new file mode 100644
index 0000000..5658101
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_CustomHID.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_JoyStickMouse.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_JoyStickMouse.dfu
new file mode 100644
index 0000000..103f4c3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_JoyStickMouse.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_MassStorage.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_MassStorage.dfu
new file mode 100644
index 0000000..29d81fa
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_MassStorage.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..4c546b7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..5b13017
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32373C-EVAL_VirtualComport_Loopback.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_AudioSpeaker.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_AudioSpeaker.dfu
new file mode 100644
index 0000000..6b19155
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_AudioSpeaker.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Composite_Example.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Composite_Example.dfu
new file mode 100644
index 0000000..6ffb73a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Composite_Example.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Custom_HID.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Custom_HID.dfu
new file mode 100644
index 0000000..eea820e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_Custom_HID.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_MassStorage.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_MassStorage.dfu
new file mode 100644
index 0000000..23ca6b6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_MassStorage.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..194e9e1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..6638545
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152-EVAL_VirtualComport_Loopback.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_Composite_Example.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_Composite_Example.dfu
new file mode 100644
index 0000000..52a647e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_Composite_Example.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_JoyStickMouse.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_JoyStickMouse.dfu
new file mode 100644
index 0000000..6c7ba98
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_JoyStickMouse.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualCOMPort.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualCOMPort.dfu
new file mode 100644
index 0000000..ba6f42c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualCOMPort.dfu
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualComport_Loopback.dfu b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualComport_Loopback.dfu
new file mode 100644
index 0000000..16e64cd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/DFU_images/STM32L152D-EVAL_VirtualComport_Loopback.dfu
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/fonts.c
index 04c5560..80cce42 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/fonts.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/fonts.c
@@ -2,23 +2,29 @@
   ******************************************************************************
   * @file    fonts.c
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
+  * @version V5.0.2
+  * @date    05-March-2012
   * @brief   This file provides text fonts for STM32xx-EVAL's LCD driver. 
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
 /* Includes ------------------------------------------------------------------*/
 #include "fonts.h"
 
@@ -35,7 +41,7 @@
   */
 
 /** @addtogroup FONTS
-  * @brief      This file includes the Fonts driver of STM32-EVAL boards.
+  * @brief      This file includes the Fonts driver of STM32xx-EVAL boards.
   * @{
   */  
 
@@ -994,4 +1000,4 @@ sFONT Font8x8 = {
 /**
   * @}
   */  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.c
new file mode 100644
index 0000000..203a17d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.c
@@ -0,0 +1,528 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log.c
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    05-March-2012
+  * @brief   This file provides all the LCD Log firmware functions.
+  *          
+  *          The LCD Log module allows to automatically set a header and footer
+  *          on any application using the LCD display and allows to dump user,
+  *          debug and error messages by using the following macros: LCD_ErrLog(),
+  *          LCD_UsrLog() and LCD_DbgLog().
+  *         
+  *          It supports also the scroll feature by embedding an internal software
+  *          cache for display. This feature allows to dump message sequentially
+  *          on the display even if the number of displayed lines is bigger than
+  *          the total number of line allowed by the display.
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include  "lcd_log.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+* @{
+*/
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @defgroup LCD_LOG 
+* @brief LCD Log LCD_Application module
+* @{
+*/ 
+
+/** @defgroup LCD_LOG_Private_Types
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Defines
+* @{
+*/ 
+
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Macros
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Variables
+* @{
+*/ 
+
+LCD_LOG_line LCD_CacheBuffer [LCD_CACHE_DEPTH]; 
+uint16_t LCD_LineColor;
+uint16_t LCD_CacheBuffer_xptr;
+uint16_t LCD_CacheBuffer_yptr_top;
+uint16_t LCD_CacheBuffer_yptr_bottom;
+
+uint16_t LCD_CacheBuffer_yptr_top_bak;
+uint16_t LCD_CacheBuffer_yptr_bottom_bak;
+
+FunctionalState LCD_CacheBuffer_yptr_invert;
+FunctionalState LCD_ScrollActive;
+FunctionalState LCD_Lock;
+FunctionalState LCD_Scrolled;
+uint16_t LCD_ScrollBackStep;
+
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_FunctionPrototypes
+* @{
+*/ 
+static void LCD_LOG_UpdateDisplay (void);
+/**
+* @}
+*/ 
+
+
+/** @defgroup LCD_LOG_Private_Functions
+* @{
+*/ 
+
+
+/**
+* @brief  Init the LCD Log module 
+* @param  None
+* @retval None
+*/
+
+void LCD_LOG_Init ( void)
+{
+  /* Deinit LCD cache */
+  LCD_LOG_DeInit();
+  /* Clear the LCD */
+  LCD_Clear(Black);  
+}
+
+/**
+* @brief DeInitializes the LCD Log module. 
+* @param  None
+* @retval None
+*/
+void LCD_LOG_DeInit(void)
+{
+  LCD_LineColor = LCD_LOG_DEFAULT_COLOR;
+  LCD_CacheBuffer_xptr = 0;
+  LCD_CacheBuffer_yptr_top = 0;
+  LCD_CacheBuffer_yptr_bottom = 0;
+  
+  LCD_CacheBuffer_yptr_top_bak = 0;
+  LCD_CacheBuffer_yptr_bottom_bak = 0;
+  
+  LCD_CacheBuffer_yptr_invert= ENABLE;
+  LCD_ScrollActive = DISABLE;
+  LCD_Lock = DISABLE;
+  LCD_Scrolled = DISABLE;
+  LCD_ScrollBackStep = 0;
+}
+
+/**
+* @brief  Display the application header (title) on the LCD screen 
+* @param  Title :  pointer to the string to be displayed
+* @retval None
+*/
+void LCD_LOG_SetHeader (uint8_t *Title)
+{
+  sFONT *cFont;
+  uint32_t size = 0 , idx; 
+  uint8_t  *ptr = Title;
+  uint8_t  tmp[27];
+  
+  /* center the header */
+  while (*ptr++) size ++ ;
+
+  /* truncate extra text */
+  if(size > 26)
+  {
+     size = 26;
+  }
+  
+  for (idx = 0 ; idx < 27 ; idx ++)
+  { 
+    tmp[idx] = ' '; 
+  }
+
+  for (idx = 0 ; idx < size ; idx ++)
+  { 
+    tmp[idx + (27 - size)/2] = Title[idx];
+  }
+  
+  /* Clear the LCD */
+  LCD_Clear(Black);
+    
+  /* Set the LCD Font */
+  LCD_SetFont (&Font12x12);
+
+  cFont = LCD_GetFont();  
+  /* Set the LCD Text Color */
+  LCD_SetTextColor(White);
+  LCD_SetBackColor(Blue);
+  LCD_ClearLine(0);
+  LCD_DisplayStringLine(cFont->Height, tmp);
+  LCD_ClearLine(2 * cFont->Height);
+
+  LCD_SetBackColor(Black);
+  LCD_SetFont (&Font8x12);
+}
+
+/**
+* @brief  Display the application footer (status) on the LCD screen 
+* @param  Status :  pointer to the string to be displayed
+* @retval None
+*/
+void LCD_LOG_SetFooter(uint8_t *Status)
+{
+  sFONT *cFont;
+  uint8_t  tmp[40], i;
+  LCD_SetBackColor(Blue);
+  cFont = LCD_GetFont();
+  
+  for (i= 0; i< (320/cFont->Width)-1 ; i++)
+  {
+    tmp[i] = ' ';
+  }
+  
+  tmp[(320/cFont->Width)-1] = 0;
+  LCD_DisplayStringLine(LCD_PIXEL_HEIGHT - cFont->Height, tmp);
+  LCD_DisplayStringLine(LCD_PIXEL_HEIGHT - cFont->Height, Status);
+  LCD_SetBackColor(Black);  
+}
+
+/**
+* @brief  Clear the Text Zone 
+* @param  None 
+* @retval None
+*/
+void LCD_LOG_ClearTextZone(void)
+{
+  uint8_t i=0;
+  sFONT *cFont = LCD_GetFont();
+  
+  for (i= 0 ; i < YWINDOW_SIZE; i++)
+  {
+    LCD_ClearLine((i + YWINDOW_MIN) * cFont->Height);
+  }
+  
+  LCD_LOG_DeInit();
+}
+
+/**
+* @brief  Redirect the printf to the lcd 
+* @param  c: character to be displayed
+* @param  f: output file pointer
+* @retval None
+*/
+PUTCHAR_PROTOTYPE
+{
+  
+  sFONT *cFont = LCD_GetFont();
+  uint32_t idx;
+  
+  if(LCD_Lock == DISABLE)
+  {
+    if((LCD_ScrollActive == ENABLE)||(LCD_ScrollActive == ENABLE))
+    {
+      LCD_CacheBuffer_yptr_bottom = LCD_CacheBuffer_yptr_bottom_bak;
+      LCD_CacheBuffer_yptr_top    = LCD_CacheBuffer_yptr_top_bak;
+      LCD_ScrollActive = DISABLE;
+      LCD_Scrolled = DISABLE;
+      LCD_ScrollBackStep = 0;
+      
+    }
+    
+    if(( LCD_CacheBuffer_xptr < LCD_PIXEL_WIDTH /cFont->Width ) &&  ( ch != '\n'))
+    {
+      LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch;
+    }   
+    else 
+    {
+      if(LCD_CacheBuffer_yptr_top >= LCD_CacheBuffer_yptr_bottom)
+      {
+        
+        if(LCD_CacheBuffer_yptr_invert == DISABLE)
+        {
+          LCD_CacheBuffer_yptr_top++;
+          
+          if(LCD_CacheBuffer_yptr_top == LCD_CACHE_DEPTH)
+          {
+            LCD_CacheBuffer_yptr_top = 0;  
+          }
+        }
+        else
+        {
+          LCD_CacheBuffer_yptr_invert= DISABLE;
+        }
+      }
+      
+      for(idx = LCD_CacheBuffer_xptr ; idx < LCD_PIXEL_WIDTH /cFont->Width; idx++)
+      {
+        LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = ' ';
+      }   
+      LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].color = LCD_LineColor;  
+      
+      LCD_CacheBuffer_xptr = 0;
+      
+      LCD_LOG_UpdateDisplay (); 
+      
+      LCD_CacheBuffer_yptr_bottom ++; 
+      
+      if (LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH) 
+      {
+        LCD_CacheBuffer_yptr_bottom = 0;
+        LCD_CacheBuffer_yptr_top = 1;    
+        LCD_CacheBuffer_yptr_invert = ENABLE;
+      }
+      
+      if( ch != '\n')
+      {
+        LCD_CacheBuffer[LCD_CacheBuffer_yptr_bottom].line[LCD_CacheBuffer_xptr++] = (uint16_t)ch;
+      }
+      
+    }
+  }
+  return ch;
+}
+  
+/**
+* @brief  Update the text area display
+* @param  None
+* @retval None
+*/
+static void LCD_LOG_UpdateDisplay (void)
+{
+  uint8_t cnt = 0 ;
+  uint16_t length = 0 ;
+  uint16_t ptr = 0, index = 0;
+  
+  sFONT *cFont = LCD_GetFont();
+  
+  if((LCD_CacheBuffer_yptr_bottom  < (YWINDOW_SIZE -1)) && 
+     (LCD_CacheBuffer_yptr_bottom  >= LCD_CacheBuffer_yptr_top))
+  {
+    LCD_SetTextColor(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].color);
+    LCD_DisplayStringLine ((YWINDOW_MIN + LCD_CacheBuffer_yptr_bottom) * cFont->Height,
+                           (uint8_t *)(LCD_CacheBuffer[cnt + LCD_CacheBuffer_yptr_bottom].line));
+  }
+  else
+  {
+    
+    if(LCD_CacheBuffer_yptr_bottom < LCD_CacheBuffer_yptr_top)
+    {
+      /* Virtual length for rolling */
+      length = LCD_CACHE_DEPTH + LCD_CacheBuffer_yptr_bottom ;
+    }
+    else
+    {
+      length = LCD_CacheBuffer_yptr_bottom;
+    }
+    
+    ptr = length - YWINDOW_SIZE + 1;
+    
+    for  (cnt = 0 ; cnt < YWINDOW_SIZE ; cnt ++)
+    {
+      
+      index = (cnt + ptr )% LCD_CACHE_DEPTH ;
+      
+      LCD_SetTextColor(LCD_CacheBuffer[index].color);
+      LCD_DisplayStringLine ((cnt + YWINDOW_MIN) * cFont->Height, 
+                             (uint8_t *)(LCD_CacheBuffer[index].line));
+      
+    }
+  }
+  
+}
+
+#ifdef LCD_SCROLL_ENABLED
+/**
+* @brief  Display previous text frame
+* @param  None
+* @retval Status
+*/
+ErrorStatus LCD_LOG_ScrollBack (void)
+{
+    
+  if(LCD_ScrollActive == DISABLE)
+  {
+    
+    LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom;
+    LCD_CacheBuffer_yptr_top_bak    = LCD_CacheBuffer_yptr_top;
+    
+    
+    if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+    {
+      
+      if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <=  YWINDOW_SIZE)
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+    }
+    LCD_ScrollActive = ENABLE;
+    
+    if((LCD_CacheBuffer_yptr_bottom  > LCD_CacheBuffer_yptr_top)&&
+       (LCD_Scrolled == DISABLE ))
+    {
+      LCD_CacheBuffer_yptr_bottom--;
+      LCD_Scrolled = ENABLE;
+    }
+    
+  }
+  
+  if(LCD_ScrollActive == ENABLE)
+  {
+    LCD_Lock = ENABLE;
+    
+    if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+    {
+      
+      if((LCD_CacheBuffer_yptr_bottom  - LCD_CacheBuffer_yptr_top) <  YWINDOW_SIZE )
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+      
+      LCD_CacheBuffer_yptr_bottom --;
+    }
+    else if(LCD_CacheBuffer_yptr_bottom <= LCD_CacheBuffer_yptr_top)
+    {
+      
+      if((LCD_CACHE_DEPTH  - LCD_CacheBuffer_yptr_top + LCD_CacheBuffer_yptr_bottom) < YWINDOW_SIZE)
+      {
+        LCD_Lock = DISABLE;
+        return ERROR;
+      }
+      LCD_CacheBuffer_yptr_bottom --;
+      
+      if(LCD_CacheBuffer_yptr_bottom == 0xFFFF)
+      {
+        LCD_CacheBuffer_yptr_bottom = LCD_CACHE_DEPTH - 2;
+      }
+    }
+    LCD_ScrollBackStep++;
+    LCD_LOG_UpdateDisplay();
+    LCD_Lock = DISABLE;
+  }
+  return SUCCESS;
+}
+
+/**
+* @brief  Display next text frame
+* @param  None
+* @retval Status
+*/
+ErrorStatus LCD_LOG_ScrollForward (void)
+{
+  
+  if(LCD_ScrollBackStep != 0)
+  {
+    if(LCD_ScrollActive == DISABLE)
+    {
+      
+      LCD_CacheBuffer_yptr_bottom_bak = LCD_CacheBuffer_yptr_bottom;
+      LCD_CacheBuffer_yptr_top_bak    = LCD_CacheBuffer_yptr_top;
+      
+      if(LCD_CacheBuffer_yptr_bottom > LCD_CacheBuffer_yptr_top) 
+      {
+        
+        if ((LCD_CacheBuffer_yptr_bottom - LCD_CacheBuffer_yptr_top) <=  YWINDOW_SIZE)
+        {
+          LCD_Lock = DISABLE;
+          return ERROR;
+        }
+      }
+      LCD_ScrollActive = ENABLE;
+      
+      if((LCD_CacheBuffer_yptr_bottom  > LCD_CacheBuffer_yptr_top)&&
+         (LCD_Scrolled == DISABLE ))
+      {
+        LCD_CacheBuffer_yptr_bottom--;
+        LCD_Scrolled = ENABLE;
+      }
+      
+    }
+    
+    if(LCD_ScrollActive == ENABLE)
+    {
+      LCD_Lock = ENABLE;
+      LCD_ScrollBackStep--;
+      
+      if(++LCD_CacheBuffer_yptr_bottom == LCD_CACHE_DEPTH)
+      {
+        LCD_CacheBuffer_yptr_bottom = 0;
+      }
+      
+      LCD_LOG_UpdateDisplay();
+      LCD_Lock = DISABLE;
+      
+    }  
+    return SUCCESS;
+  }
+  else // LCD_ScrollBackStep == 0 
+  {
+    LCD_Lock = DISABLE;
+    return ERROR;
+  }  
+}
+#endif /* LCD_SCROLL_ENABLED */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.h
new file mode 100644
index 0000000..a7ec668
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log.h
@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    05-March-2012
+  * @brief   header for the lcd_log.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef  __LCD_LOG_H__
+#define  __LCD_LOG_H__
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "lcd_log_conf.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+
+/** @addtogroup LCD_LOG
+  * @{
+  */
+  
+/** @defgroup LCD_LOG
+  * @brief 
+  * @{
+  */ 
+
+
+/** @defgroup LCD_LOG_Exported_Defines
+  * @{
+  */ 
+#ifdef __GNUC__
+/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
+   set to 'Yes') calls __io_putchar() */
+#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
+#else
+#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+/** These value can be changed by user */
+
+#ifdef LCD_SCROLL_ENABLED
+ #define     LCD_CACHE_DEPTH     (YWINDOW_SIZE + CACHE_SIZE)
+#else
+ #define     LCD_CACHE_DEPTH     YWINDOW_SIZE
+#endif
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Types
+  * @{
+  */ 
+typedef struct _LCD_LOG_line
+{
+  uint8_t  line[XWINDOW_MAX];
+  uint16_t color;
+
+}LCD_LOG_line;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Macros
+  * @{
+  */ 
+#define  LCD_ErrLog(...)    LCD_LineColor = Red;\
+                            printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            LCD_LineColor = LCD_LOG_DEFAULT_COLOR
+
+#define  LCD_UsrLog(...)    LCD_LineColor = LCD_LOG_DEFAULT_COLOR;\
+                            printf(__VA_ARGS__);\
+
+
+#define  LCD_DbgLog(...)    LCD_LineColor = Cyan;\
+                            printf(__VA_ARGS__);\
+                            LCD_LineColor = LCD_LOG_DEFAULT_COLOR
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_Variables
+  * @{
+  */ 
+extern uint16_t LCD_LineColor;
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_Exported_FunctionsPrototype
+  * @{
+  */ 
+void LCD_LOG_Init(void);
+void LCD_LOG_DeInit(void);
+void LCD_LOG_SetHeader(uint8_t *Title);
+void LCD_LOG_SetFooter(uint8_t *Status);
+void LCD_LOG_ClearTextZone(void);
+#ifdef LCD_SCROLL_ENABLED
+ ErrorStatus LCD_LOG_ScrollBack(void);
+ ErrorStatus LCD_LOG_ScrollForward(void);
+#endif
+/**
+  * @}
+  */ 
+
+
+#endif /* __LCD_LOG_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h
new file mode 100644
index 0000000..c242be1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/lcd_log_conf_template.h
@@ -0,0 +1,113 @@
+/**
+  ******************************************************************************
+  * @file    lcd_log_conf_template.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    05-March-2012
+  * @brief   lcd_log configuration template file.
+  *          This file should be copied to the application folder and modified 
+  *          as follows:
+  *            - Rename it to 'lcd_log_conf.h'.
+  *            - Update the name of the LCD header file depending on the EVAL board
+  *              you are using (see line32 below).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef  __LCD_LOG_CONF_H__
+#define  __LCD_LOG_CONF_H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32xxx_eval_lcd.h" /* replace 'stm32xxx' with your EVAL board name, ex: stm3210c_eval_lcd.h */
+#include <stdio.h>
+
+/** @addtogroup LCD_LOG
+  * @{
+  */
+  
+/** @defgroup LCD_LOG
+  * @brief This file is the 
+  * @{
+  */ 
+
+
+/** @defgroup LCD_LOG_CONF_Exported_Defines
+  * @{
+  */ 
+/* Comment the line below to disable the scroll back and forward features */
+#define LCD_SCROLL_ENABLED
+
+/* Define the LCD default text color */
+#define LCD_LOG_DEFAULT_COLOR    LCD_COLOR_WHITE
+
+/* Define the display window settings */
+#define YWINDOW_MIN              3
+#define YWINDOW_SIZE             12
+#define XWINDOW_MAX              50
+
+/* Define the cache depth */
+#define CACHE_SIZE               50
+
+/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup LCD_LOG_Exported_Macros
+  * @{
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_CONF_Exported_Variables
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+#endif /* __LCD_LOG_H__ */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/stm32_eval_legacy.h
index d30caff..4910509 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/Common/stm32_eval_legacy.h
@@ -1,27 +1,33 @@
 /**
   ******************************************************************************
-  * @file    stm32_eval.h
+  * @file    stm32_eval_legacy.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   Header file for stm32_eval.c module.
+  * @version V5.0.2
+  * @date    05-March-2012
+  * @brief   This file contains defines legacy for STM32 EVAL drivers.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
   */ 
   
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_H
-#define __STM32_EVAL_H
+#ifndef __STM32_EVAL_LEGACY_H
+#define __STM32_EVAL_LEGACY_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -29,150 +35,15 @@
 
 /* Includes ------------------------------------------------------------------*/
 
-/** @addtogroup Utilities
-  * @{
-  */ 
-  
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_Abstraction_Layer
-  * @{
-  */
-  
-/** @defgroup STM32_EVAL_HARDWARE_RESOURCES
-  * @{
-  */
-
-/**
-@code  
- The table below gives an overview of the hardware resources supported by each 
- STM32 EVAL board.
-     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))
-     - IOE: IO Expander on I2C
-     - sFLASH: serial SPI FLASH (M25Pxxx)
-     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)
-     - TSENSOR: Temperature Sensor (LM75)
-     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) 
-  =================================================================================================================+
-    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |
-  =================================================================================================================+
-   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |
-  -----------------------------------------------------------------------------------------------------------------+
-   STM32100E-EVAL  |  4  |    8     |     2     | YES (FSMC)| YES  |  YES   | YES |   YES   |    YES   |    NO     |
-  =================================================================================================================+
-@endcode
-*/
-
-/**
-  * @}
-  */
-  
-/** @defgroup STM32_EVAL_Exported_Types
-  * @{
-  */
-typedef enum 
-{
-  LED1 = 0,
-  LED2 = 1,
-  LED3 = 2,
-  LED4 = 3
-} Led_TypeDef;
-
-typedef enum 
-{  
-  BUTTON_WAKEUP = 0,
-  BUTTON_TAMPER = 1,
-  BUTTON_KEY = 2,
-  BUTTON_RIGHT = 3,
-  BUTTON_LEFT = 4,
-  BUTTON_UP = 5,
-  BUTTON_DOWN = 6,
-  BUTTON_SEL = 7
-} Button_TypeDef;
-
-typedef enum 
-{  
-  BUTTON_MODE_GPIO = 0,
-  BUTTON_MODE_EXTI = 1
-} ButtonMode_TypeDef;
-
-typedef enum 
-{ 
-  JOY_NONE = 0,
-  JOY_SEL = 1,
-  JOY_DOWN = 2,
-  JOY_LEFT = 3,
-  JOY_RIGHT = 4,
-  JOY_UP = 5
-} JOYState_TypeDef
-;
-
-typedef enum 
-{
-  COM1 = 0,
-  COM2 = 1
-} COM_TypeDef;   
-/**
-  * @}
-  */ 
-  
-/** @defgroup STM32_EVAL_Exported_Constants
-  * @{
-  */
-
-/** 
-  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation
-  *   board used in your application.
-  *   
-  *  Tip: To avoid modifying this file each time you need to switch between these
-  *       boards, you can define the board in your toolchain compiler preprocessor.    
-  */ 
-#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\
-   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- //#define USE_STM32L152_EVAL
- //#define USE_STM32100E_EVAL
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* STM322xG_EVAL Defines Legacy */ 
+#ifdef USE_STM3220F_EVAL       
+  #define USE_STM322xG_EVAL
 #endif
+#define STM3220F_LCD_Init       STM322xG_LCD_Init
 
-#ifdef USE_STM32100B_EVAL
- #include "stm32f10x.h"
- #include "stm32100b_eval/stm32100b_eval.h"
-#elif defined USE_STM3210B_EVAL
- #include "stm32f10x.h"
- #include "stm3210b_eval/stm3210b_eval.h" 
-#elif defined USE_STM3210E_EVAL
- #include "stm32f10x.h"
- #include "stm3210e_eval/stm3210e_eval.h"
-#elif defined USE_STM3210C_EVAL
- #include "stm32f10x.h"
- #include "stm3210c_eval/stm3210c_eval.h"
-#elif defined USE_STM32L152_EVAL
- #include "stm32l1xx.h"
- #include "stm32l152_eval/stm32l152_eval.h" 
-#elif defined USE_STM32100E_EVAL
- #include "stm32f10x.h"
- #include "stm32100e_eval/stm32100e_eval.h"
-#else 
- #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
-#endif                      
-
-
-/** 
-  * @brief  STM32 Button Defines Legacy  
-  */ 
+/* Button Defines Legacy */ 
 #define Button_WAKEUP        BUTTON_WAKEUP
 #define Button_TAMPER        BUTTON_TAMPER
 #define Button_KEY           BUTTON_KEY
@@ -187,9 +58,7 @@ typedef enum
 #define JOY_CENTER           JOY_SEL
 #define JOY_State_TypeDef    JOYState_TypeDef 
 
-/** 
-  * @brief  LCD Defines Legacy  
-  */ 
+/* LCD Defines Legacy */ 
 #define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK
 #define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT
 #define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK
@@ -327,42 +196,13 @@ typedef enum
 #define Horizontal          LCD_DIR_HORIZONTAL
 #define Vertical            LCD_DIR_VERTICAL
 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup STM32_EVAL_Exported_Functions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* __STM32_EVAL_LEGACY_H */
 
-#endif /* __STM32_EVAL_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/Release_Notes.html
index 430a05b..8d612a4 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Release_Notes.html
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/Release_Notes.html
@@ -13,7 +13,7 @@
   <link rel="File-List" href="Library_files/filelist.xml">
 
   
-  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32 Standard Peripherals Library Utilities</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM3210B_EVAL Evaluation Board Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
 
 
   
@@ -86,16 +86,16 @@ div.Section1
         <tbody>
           <tr>
             <td style="vertical-align: top;">
-            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
             </td>
           </tr>
           <tr style="">
             <td style="padding: 1.5pt;">
             <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32 Standard Peripherals Library Utilities (Utilities)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+Notes for STM3210B_EVAL Evaluation Board Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
             <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
-2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
             </td>
           </tr>
         </tbody>
@@ -107,15 +107,41 @@ Notes for STM32 Standard Peripherals Library Utilities (Utilities)</span><span s
             <td style="padding: 0cm;" valign="top">
             <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
             <ol style="margin-top: 0cm;" start="1" type="1">
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32 Standard Peripherals Library Utilities
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM3210B_EVAL&nbsp;Evaluation Board Drivers
 update History</a><o:p></o:p></span></li>
               <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
             </ol>
             <span style="font-family: &quot;Times New Roman&quot;;">
             </span>
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32
-Standard
-Peripherals Library Utilities update History</span></h2><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.5.0 / 07-March-2011<o:p></o:p></span></h3>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM3210B_EVAL Evaluation Board Drivers update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V5.0.1 / 05-March-2012<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files:&nbsp;license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 176px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V5.0.0 / 03-February-2012<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the&nbsp;new license agreement</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update STM32 Evaluation Board Drivers architecture and folder organization,&nbsp;<span style="font-weight: bold; font-style: italic;">full&nbsp;API compatibility maintained vs. V4.6.2</span></span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">All the HW&nbsp;drivers required for each board are&nbsp;provided within this board folder</span><span style="font-size: 10pt; font-family: Verdana;">. The concerned drivers are:</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_i2c_ee.c\.h:</span>&nbsp;I2C M24Cxx EEPROM memory driver</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_i2c_tsensor.c\.h:</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">I2C </span><span style="font-size: 10pt; font-family: Verdana;">LM75 temperature sensor driver</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_spi_flash.c\.h:</span> SPI M25Pxxx FLASH memory driver</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_sdio_sd.c\.h:</span> SDIO SD Card memory driver</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval_spi_sd.c\.h:</span>&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">SPI SD Card memory driver&nbsp;</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">These drivers were&nbsp;moved from </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\Common</span> to </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\STM32XXX_EVAL</span> folder(s)</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\Common&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;">folder contains only drivers for the fonts and log module used by the LCD driver</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32_eval.c\.h</span> files removed, <span style="font-style: italic; text-decoration: underline;">as consequence you need to perform the following update on your project configuration&nbsp; (based on EVAL drivers V4.6.2):</span></span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">In the&nbsp;project files, add your EVAL board driver source&nbsp;file&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">"stm3210b_eval.c"</span>&nbsp;instead of <span style="font-style: italic;">"stm32_eval.c"</span></span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Include your EVAL board driver header file&nbsp;<span style="font-style: italic;">#include "stm3210b_eval.h"</span>&nbsp;instead of <span style="font-style: italic;">#include "stm32_eval.h"</span></span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">If
+you are&nbsp;using the EVAL board's LCD, you need to add the include of
+the LCD header file&nbsp;#include "stm3210b_eval_lcd.h"</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">If
+you are using the LCD log module, after copying it to the application
+folder you have to edit it and update the name of the LCD header file. For more details, refer to the <span style="font-style: italic;">lcd_log_conf_template.h</span> driver description.</span></li></ul></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm3210b_eval_lcd.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Remove &#8220;static&#8221; from&nbsp;<span style="font-style: italic;">TextColor</span> and&nbsp;<span style="font-style: italic;">BackColor</span> variables declaration (need to be changed from other application modules)&nbsp;</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.6.2 /&nbsp;22-July-2011<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM3210C_EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm3210c_eval_lcd.c: update to support new LCD AM240320D5TOQW01H (controller ILI9325)</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">STM322xG-EVAL</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm322xg_eval.h: fix value of the SDIO clock divider (<span style="font-style: italic;">SDIO_TRANSFER_CLK_DIV</span> constant) to 2 instead of 0</span></li></ul><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm322xg_eval_lcd.c: increase FSMC<span style="font-style: italic;"> AddressSetupTime</span> value from 1 to 3 to be compliant with some&nbsp;LCD access timing</span></li></ul><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm322xg_eval_audio_codec.c: update <span style="font-style: italic;">Codec_CtrlInterface_Init(</span>) and <span style="font-style: italic;">Codec_GPIO_Init(</span>) functions to not reconfigure the I2C peripheral if it's&nbsp;already </span><span style="font-size: 10pt; font-family: Verdana;">enabled and </span><span style="font-size: 10pt; font-family: Verdana;">configured&nbsp;(to
+avoid configuring the I2C twice when using both&nbsp;Audio codec and IO
+Expander drivers in the same application).<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.6.1 / 18-April-2011<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">some</span><span style="font-size: 10pt; font-family: Verdana;"> <span style="font-weight: bold; font-style: italic;">STM322xG_EVAL</span> drivers (no change on the API) to fix&nbsp;warnings wit<span style="font-weight: bold; font-style: italic;"></span>h TASKING C compiler.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Change the Release Notes name to <span style="font-weight: bold; font-style: italic;">STM32 Evaluation Board Drivers </span><br></span></li><li style="font-style: italic;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm322xg_eval.c</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">SD_LowLevel_Init(): change&nbsp;SDIO pins speed configuration to&nbsp;"GPIO_Speed_25MHz"</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.6.0 / 11-March-2011<o:p></o:p></span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Official version supporting <span style="font-weight: bold; font-style: italic;">STM322xG_EVAL</span> evaluation board RevB (for <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices).</span></li><li style="font-style: italic;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Common</span></li><ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add
+new LCD log utility drivers: The LCD Log module allows to automatically
+set a header and footer on any application using the LCD display and
+allows to dump user, debug and error messages by using the following
+macros: LCD_ErrLog(),&nbsp;&nbsp;&nbsp; LCD_UsrLog() and LCD_DbgLog().</span></li></ul></ul><div style="margin-left: 40px;"><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline; font-style: italic;">Note</span><span style="font-style: italic;">:</span> the <span style="font-style: italic;">STM322xG_EVAL</span> board RevA was wrongly named <span style="font-style: italic;">STM3220F_EVAL</span></span><br></div><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.5.0 / 07-March-2011<o:p></o:p></span></h3>
             <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
 Changes<o:p></o:p></span></u></b></p>
 
@@ -293,25 +319,18 @@ drivers for STM3210E-EVAL board: stm3210e_eval_fsmc_sram.h/.c, </span><span styl
 and </span><span style="font-size: 10pt; font-family: Verdana;">stm3210e_eval_fsmc_nand.h/.c.</span></li>
               </ul>
             </ul>
-            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-
-            <b><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS.</span></b>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
+required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
+the License for the specific language governing permissions and
+limitations under the License.</span><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
             
             <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
             <hr align="center" size="2" width="100%"></span></div>
             <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;">&nbsp;Microcontrollers
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
             </td>
           </tr>
         </tbody>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c
index d2adb8c..338f921 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.c
@@ -1,33 +1,36 @@
 /**
   ******************************************************************************
-  * @file    stm32100e_eval.c
+  * @file    stm3210b_eval.c
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
+  * @version V5.0.1
+  * @date    05-March-2012
   * @brief   This file provides
   *            - set of firmware functions to manage Leds, push-button and COM ports
-  *            - low level initialization functions for SD card (on SDIO), SPI serial
+  *            - low level initialization functions for SD card (on SPI), SPI serial
   *              flash (sFLASH) and temperature sensor (LM75)
-  *          available on STM32100E-EVAL evaluation board from STMicroelectronics.  
+  *          available on STM3210B-EVAL evaluation board from STMicroelectronics.    
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
   */ 
   
 /* Includes ------------------------------------------------------------------*/
-#include "stm32100e_eval.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_dma.h"
+#include "stm3210b_eval.h"
 
 /** @addtogroup Utilities
   * @{
@@ -37,19 +40,19 @@
   * @{
   */ 
 
-/** @addtogroup STM32100E_EVAL
+/** @addtogroup STM3210B_EVAL
   * @{
   */ 
       
-/** @defgroup STM32100E_EVAL_LOW_LEVEL 
+/** @defgroup STM3210B_EVAL_LOW_LEVEL 
   * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) 
-  *        and temperature sensor (LM75) available on STM32100E-EVAL evaluation 
+  *        COM ports, SD card on SPI, serial flash (sFLASH), serial EEPROM (sEE) 
+  *        and temperature sensor (LM75) available on STM3210B-EVAL evaluation
   *        board from STMicroelectronics.
   * @{
   */ 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_TypesDefinitions
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_TypesDefinitions
   * @{
   */ 
 /**
@@ -57,7 +60,7 @@
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Defines
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Defines
   * @{
   */ 
 /**
@@ -65,7 +68,7 @@
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Macros
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Macros
   * @{
   */ 
 /**
@@ -73,7 +76,7 @@
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Variables
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Variables
   * @{
   */ 
 GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
@@ -146,14 +149,13 @@ const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
 
 const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
 
-DMA_InitTypeDef   sEEDMA_InitStructure;
 
 /**
   * @}
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_FunctionPrototypes
   * @{
   */ 
 
@@ -162,7 +164,7 @@ DMA_InitTypeDef   sEEDMA_InitStructure;
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Private_Functions
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Private_Functions
   * @{
   */ 
 
@@ -218,7 +220,7 @@ void STM_EVAL_LEDOn(Led_TypeDef Led)
   */
 void STM_EVAL_LEDOff(Led_TypeDef Led)
 {
-  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];    
+  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];  
 }
 
 /**
@@ -336,13 +338,14 @@ void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
   /* Enable GPIO clock */
   RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
 
-  /* Enable UART clock */
   if (COM == COM1)
   {
     RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
   }
   else
   {
+    /* Enable the USART2 Pins Software Remapping */
+    GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
     RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
   }
 
@@ -352,6 +355,7 @@ void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
   GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
 
+
   /* Configure USART Rx as input floating */
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
   GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
@@ -377,7 +381,7 @@ void SD_LowLevel_DeInit(void)
   SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
   
   /*!< SD_SPI Periph clock disable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE);
+  RCC_APB2PeriphClockCmd(SD_SPI_CLK, DISABLE); 
   
   /*!< Configure SD_SPI pins: SCK */
   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
@@ -417,7 +421,8 @@ void SD_LowLevel_Init(void)
                          SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
 
   /*!< SD_SPI Periph clock enable */
-  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE);
+  RCC_APB2PeriphClockCmd(SD_SPI_CLK, ENABLE); 
+
   
   /*!< Configure SD_SPI pins: SCK */
   GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
@@ -431,6 +436,7 @@ void SD_LowLevel_Init(void)
 
   /*!< Configure SD_SPI pins: MISO */
   GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
   GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
   
   /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
@@ -450,7 +456,7 @@ void SD_LowLevel_Init(void)
   SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
   SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
   SPI_InitStructure.SPI_CRCPolynomial = 7;
   SPI_Init(SD_SPI, &SPI_InitStructure);
@@ -459,149 +465,6 @@ void SD_LowLevel_Init(void)
 }
 
 /**
-  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DeInit(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure; 
-  NVIC_InitTypeDef NVIC_InitStructure;    
-   
-  /* sEE_I2C Peripheral Disable */
-  I2C_Cmd(sEE_I2C, DISABLE);
- 
-  /* sEE_I2C DeInit */
-  I2C_DeInit(sEE_I2C);
-
-  /*!< sEE_I2C Periph clock disable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
-  
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);   
-  
-  /* Disable and Deinitialize the DMA channels */
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
-  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-}
-
-/**
-  * @brief  Initializes peripherals used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_Init(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  NVIC_InitTypeDef NVIC_InitStructure;  
-    
-  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
-  RCC_APB2PeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
-
-  /*!< sEE_I2C Periph clock enable */
-  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
-    
-  /*!< GPIO configuration */  
-  /*!< Configure sEE_I2C pins: SCL */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
-  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
-
-  /*!< Configure sEE_I2C pins: SDA */
-  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
-  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); 
-
-  /* Configure and enable I2C DMA TX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-
-  /* Configure and enable I2C DMA RX Channel interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
-  NVIC_Init(&NVIC_InitStructure);  
-  
-  /*!< I2C DMA TX and RX channels configuration */
-  /* Enable the DMA clock */
-  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
-
-  /* I2C TX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
-  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
-  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
-  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
-  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
-  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
-  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  
-  /* I2C RX DMA Channel configuration */
-  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
-  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
-  
-  /* Enable the DMA Channels Interrupts */
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
-  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
-}
-
-/**
-  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
-  * @param  None
-  * @retval None
-  */
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
-{ 
-  /* Initialize the DMA with the new parameters */
-  if (Direction == sEE_DIRECTION_TX)
-  {
-    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
-    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
-  }
-  else
-  { 
-    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
-    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
-    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
-    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
-    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
-  }
-}
-
-/**
   * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
   * @param  None
   * @retval None
@@ -707,7 +570,7 @@ void LM75_LowLevel_DeInit(void)
 }
 
 /**
-  * @brief  Initializes the LM75_I2C..
+  * @brief  Initializes the LM75_I2C.
   * @param  None
   * @retval None
   */
@@ -738,11 +601,12 @@ void LM75_LowLevel_Init(void)
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
   GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
 }
-
+  
 /**
   * @}
   */ 
 
+
 /**
   * @}
   */ 
@@ -750,13 +614,13 @@ void LM75_LowLevel_Init(void)
 /**
   * @}
   */
-
+ 
 /**
   * @}
-  */    
+  */  
 
 /**
   * @}
-  */ 
+  */  
     
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h
new file mode 100644
index 0000000..0a43b80
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval.h
@@ -0,0 +1,403 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval.h
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file contains definitions for STM3210B_EVAL's Leds, push-buttons
+  *          COM ports, SD Card (on SPI), sFLASH (on SPI) and Temperature sensor 
+  *          LM75 (on I2C) hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210B_EVAL_H
+#define __STM3210B_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+#include "stm32_eval_legacy.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+    
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL
+  * @{
+  */
+  
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_WAKEUP = 0,
+  BUTTON_TAMPER = 1,
+  BUTTON_KEY = 2,
+  BUTTON_RIGHT = 3,
+  BUTTON_LEFT = 4,
+  BUTTON_UP = 5,
+  BUTTON_DOWN = 6,
+  BUTTON_SEL = 7
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;
+
+/**
+  * @}
+  */
+
+
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief  Define for STM3210B_EVAL board  
+  */ 
+#if !defined (USE_STM3210B_EVAL)
+ #define USE_STM3210B_EVAL
+#endif
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+#define LED1_PIN                         GPIO_Pin_6
+#define LED1_GPIO_PORT                   GPIOC
+#define LED1_GPIO_CLK                    RCC_APB2Periph_GPIOC  
+  
+#define LED2_PIN                         GPIO_Pin_7
+#define LED2_GPIO_PORT                   GPIOC
+#define LED2_GPIO_CLK                    RCC_APB2Periph_GPIOC  
+
+#define LED3_PIN                         GPIO_Pin_8  
+#define LED3_GPIO_PORT                   GPIOC
+#define LED3_GPIO_CLK                    RCC_APB2Periph_GPIOC  
+  
+#define LED4_PIN                         GPIO_Pin_9
+#define LED4_GPIO_PORT                   GPIOC
+#define LED4_GPIO_CLK                    RCC_APB2Periph_GPIOC  
+
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          8
+
+/**
+ * @brief Wakeup push-button
+ */
+#define WAKEUP_BUTTON_PIN                GPIO_Pin_0
+#define WAKEUP_BUTTON_GPIO_PORT          GPIOA
+#define WAKEUP_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOA
+#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line0
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOA
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource0
+#define WAKEUP_BUTTON_EXTI_IRQn          EXTI0_IRQn 
+/**
+ * @brief Tamper push-button
+ */
+#define TAMPER_BUTTON_PIN                GPIO_Pin_13
+#define TAMPER_BUTTON_GPIO_PORT          GPIOC
+#define TAMPER_BUTTON_GPIO_CLK           RCC_APB2Periph_GPIOC
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   GPIO_PortSourceGPIOC
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    GPIO_PinSource13
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn 
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_9
+#define KEY_BUTTON_GPIO_PORT             GPIOB
+#define KEY_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOB
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line9
+#define KEY_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOB
+#define KEY_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource9
+#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_0
+#define RIGHT_BUTTON_GPIO_PORT           GPIOE
+#define RIGHT_BUTTON_GPIO_CLK            RCC_APB2Periph_GPIOE
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line0
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    GPIO_PortSourceGPIOE
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     GPIO_PinSource0
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI0_IRQn
+/**
+ * @brief Joystick Left push-button
+ */
+#define LEFT_BUTTON_PIN                  GPIO_Pin_1
+#define LEFT_BUTTON_GPIO_PORT            GPIOE
+#define LEFT_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOE
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line1
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOE
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource1
+#define LEFT_BUTTON_EXTI_IRQn            EXTI1_IRQn  
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_8
+#define UP_BUTTON_GPIO_PORT              GPIOD
+#define UP_BUTTON_GPIO_CLK               RCC_APB2Periph_GPIOD
+#define UP_BUTTON_EXTI_LINE              EXTI_Line8
+#define UP_BUTTON_EXTI_PORT_SOURCE       GPIO_PortSourceGPIOD
+#define UP_BUTTON_EXTI_PIN_SOURCE        GPIO_PinSource8
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  
+/**
+ * @brief Joystick Down push-button
+ */  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_14
+#define DOWN_BUTTON_GPIO_PORT            GPIOD
+#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line14
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource14
+#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+/**
+ * @brief Joystick Sel push-button
+ */
+#define SEL_BUTTON_PIN                   GPIO_Pin_12
+#define SEL_BUTTON_GPIO_PORT             GPIOD
+#define SEL_BUTTON_GPIO_CLK              RCC_APB2Periph_GPIOD
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line12
+#define SEL_BUTTON_EXTI_PORT_SOURCE      GPIO_PortSourceGPIOD
+#define SEL_BUTTON_EXTI_PIN_SOURCE       GPIO_PinSource12
+#define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn   
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             2
+
+/**
+ * @brief Definition for COM port1, connected to USART1
+ */ 
+#define EVAL_COM1                        USART1
+#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_9
+#define EVAL_COM1_TX_GPIO_PORT           GPIOA
+#define EVAL_COM1_TX_GPIO_CLK            RCC_APB2Periph_GPIOA
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_10
+#define EVAL_COM1_RX_GPIO_PORT           GPIOA
+#define EVAL_COM1_RX_GPIO_CLK            RCC_APB2Periph_GPIOA
+#define EVAL_COM1_IRQn                   USART1_IRQn
+
+/**
+ * @brief Definition for COM port2, connected to USART2 (USART2 pins remapped on GPIOD)
+ */ 
+#define EVAL_COM2                        USART2
+#define EVAL_COM2_CLK                    RCC_APB1Periph_USART2
+#define EVAL_COM2_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM2_TX_GPIO_PORT           GPIOD
+#define EVAL_COM2_TX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM2_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM2_RX_GPIO_PORT           GPIOD
+#define EVAL_COM2_RX_GPIO_CLK            RCC_APB2Periph_GPIOD
+#define EVAL_COM2_IRQn                   USART2_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_SD_SPI
+  * @{
+  */
+/**
+  * @brief  SD SPI Interface pins
+  */
+#define SD_SPI                           SPI1
+#define SD_SPI_CLK                       RCC_APB2Periph_SPI1
+#define SD_SPI_SCK_PIN                   GPIO_Pin_5                  /* PA.05 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOA                       /* GPIOA */
+#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOA
+#define SD_SPI_MISO_PIN                  GPIO_Pin_6                  /* PA.06 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOA                       /* GPIOA */
+#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOA
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_7                  /* PA.07 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOA                       /* GPIOA */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOA
+#define SD_CS_PIN                        GPIO_Pin_12                 /* PC.12 */
+#define SD_CS_GPIO_PORT                  GPIOC                       /* GPIOC */
+#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOC
+#define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOE
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_M25P_FLASH_SPI
+  * @{
+  */
+/**
+  * @brief  M25P FLASH SPI Interface pins
+  */  
+#define sFLASH_SPI                       SPI1
+#define sFLASH_SPI_CLK                   RCC_APB2Periph_SPI1
+#define sFLASH_SPI_SCK_PIN               GPIO_Pin_5                  /* PA.05 */
+#define sFLASH_SPI_SCK_GPIO_PORT         GPIOA                       /* GPIOA */
+#define sFLASH_SPI_SCK_GPIO_CLK          RCC_APB2Periph_GPIOA
+#define sFLASH_SPI_MISO_PIN              GPIO_Pin_6                  /* PA.06 */
+#define sFLASH_SPI_MISO_GPIO_PORT        GPIOA                       /* GPIOA */
+#define sFLASH_SPI_MISO_GPIO_CLK         RCC_APB2Periph_GPIOA
+#define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
+#define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
+#define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
+#define sFLASH_CS_PIN                    GPIO_Pin_4                  /* PA.04 */
+#define sFLASH_CS_GPIO_PORT              GPIOA                       /* GPIOA */
+#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOA 
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM3210B_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  LM75 Temperature Sensor I2C Interface pins
+  */  
+#define LM75_I2C                         I2C1
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
+#define LM75_I2C_DR                      ((uint32_t)0x40005410)
+
+#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
+#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
+#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
+#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7 
+
+/**
+  * @}
+  */
+    
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */ 
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void sFLASH_LowLevel_DeInit(void);
+void sFLASH_LowLevel_Init(void); 
+void LM75_LowLevel_DeInit(void);
+void LM75_LowLevel_Init(void); 
+ 
+/**
+  * @}
+  */ 
+    
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __STM3210B_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */    
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.c
new file mode 100644
index 0000000..b10d513
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.c
@@ -0,0 +1,982 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_i2c_tsensor.c
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file provides a set of functions needed to manage the I2C LM75 
+  *          temperature sensor mounted on STM3210B-EVAL board. 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this sensor. The needed STM32 hardware resources (I2C and 
+  *          GPIO) are defined in stm3210b_eval.h file, and the initialization is 
+  *          performed in LM75_LowLevel_Init() function declared in stm3210b_eval.c 
+  *          file.
+  *            
+  *          Note:
+  *          -----    
+  *          This driver uses the DMA method to send and receive data on I2C bus,
+  *          which allows higher efficiency and reliability  of the communication.
+  *                 
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          LM75_LowLevel_Init() function.
+  *
+  *     +-----------------------------------------------------------------+
+  *     |                        Pin assignment                           |                 
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32 I2C Pins                       |   STLM75  |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | LM75_I2C_SDA_PIN/ SDA                 |   SDA     |    1        |
+  *     | LM75_I2C_SCL_PIN/ SCL                 |   SCL     |    2        |
+  *     | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT  |   OS/INT  |    3        |
+  *     | .                                     |   GND     |    4  (0V)  |
+  *     | .                                     |   GND     |    5  (0V)  |
+  *     | .                                     |   GND     |    6  (0V)  |
+  *     | .                                     |   GND     |    7  (0V)  |
+  *     | .                                     |   VDD     |    8  (3.3V)|
+  *     +---------------------------------------+-----------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval_i2c_tsensor.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_I2C_TSENSOR
+  * @brief      This file includes the LM75 Temperature Sensor driver of 
+  *             STM3210B-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Defines
+  * @{
+  */ 
+#define LM75_SD_SET                0x01 /*!< Set SD bit in the configuration register */
+#define LM75_SD_RESET              0xFE /*!< Reset SD bit in the configuration register */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Variables
+  * @{
+  */ 
+  
+__IO uint32_t  LM75_Timeout = LM75_LONG_TIMEOUT; 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Function_Prototypes
+  * @{
+  */ 
+static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData);
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_DeInit(void)
+{
+  LM75_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_Init(void)
+{
+  I2C_InitTypeDef   I2C_InitStructure;
+  
+  LM75_LowLevel_Init();
+  
+  I2C_DeInit(LM75_I2C);
+
+  /*!< LM75_I2C Init */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = LM75_I2C_SPEED;
+  I2C_Init(LM75_I2C, &I2C_InitStructure);
+
+  /*!< Enable SMBus Alert interrupt */
+  I2C_ITConfig(LM75_I2C, I2C_IT_ERR, ENABLE);
+
+  /*!< LM75_I2C Init */
+  I2C_Cmd(LM75_I2C, ENABLE);
+}
+
+
+/**
+  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
+  * @param  None
+  * @retval None
+  */
+
+static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+  
+  RCC_AHBPeriphClockCmd(LM75_DMA_CLK, ENABLE);
+  
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = LM75_I2C_DR;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
+   /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  
+  /* If using DMA for Reception */
+  if (Direction == LM75_DMA_RX)
+  {
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = NumData;
+    
+    DMA_DeInit(LM75_DMA_RX_CHANNEL);
+    
+    DMA_Init(LM75_DMA_RX_CHANNEL, &DMA_InitStructure);
+  }
+   /* If using DMA for Transmission */
+  else if (Direction == LM75_DMA_TX)
+  { 
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = NumData;
+    
+    DMA_DeInit(LM75_DMA_TX_CHANNEL);
+    
+    DMA_Init(LM75_DMA_TX_CHANNEL, &DMA_InitStructure);
+  }
+}
+
+
+/**
+  * @brief  Checks the LM75 status.
+  * @param  None
+  * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS).
+  */
+ErrorStatus LM75_GetStatus(void)
+{
+  uint32_t I2C_TimeOut = I2C_TIMEOUT;
+
+  /*!< Clear the LM75_I2C AF flag */
+  I2C_ClearFlag(LM75_I2C, I2C_FLAG_AF);
+
+  /*!< Enable LM75_I2C acknowledgement if it is already disabled by other function */
+  I2C_AcknowledgeConfig(LM75_I2C, ENABLE);
+
+  /*---------------------------- Transmission Phase ---------------------------*/
+
+  /*!< Send LM75_I2C START condition */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+
+  /*!< Test on LM75_I2C EV5 and clear it */
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) && I2C_TimeOut)  /*!< EV5 */
+  {
+    I2C_TimeOut--;
+  }
+  if (I2C_TimeOut == 0)
+  {
+    return ERROR;
+  }
+  
+  I2C_TimeOut = I2C_TIMEOUT;
+
+  /*!< Send STLM75 slave address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+
+  while ((!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && I2C_TimeOut)/* EV6 */
+  {
+    I2C_TimeOut--;
+  }
+
+  if ((I2C_GetFlagStatus(LM75_I2C, I2C_FLAG_AF) != 0x00) || (I2C_TimeOut == 0))
+  {
+    return ERROR;
+  }
+  else
+  {
+    return SUCCESS;
+  }
+}
+/**
+  * @brief  Read the specified register from the LM75.
+  * @param  RegName: specifies the LM75 register to be read.
+  *              This member can be one of the following values:  
+  *                  - LM75_REG_TEMP: temperature register
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @retval LM75 register value.
+  */
+uint16_t LM75_ReadReg(uint8_t RegName)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint16_t tmp = 0;    
+  
+   /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, RegName);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
+  tmp |= LM75_BufferRX[1];
+  
+  /* return a Reg value */
+  return (uint16_t)tmp;  
+}
+
+/**
+  * @brief  Write to the specified register of the LM75.
+  * @param  RegName: specifies the LM75 register to be written.
+  *              This member can be one of the following values:    
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @param  RegValue: value to be written to LM75 register.  
+  * @retval None
+  */
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue)
+{   
+  uint8_t LM75_BufferTX[2] ={0,0};
+  LM75_BufferTX[0] = (uint8_t)(RegValue >> 8);
+  LM75_BufferTX[1] = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)LM75_BufferTX, 2);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, RegName);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
+  
+  return LM75_OK;
+}
+
+/**
+  * @brief  Read Temperature register of LM75: double temperature value.
+  * @param  None
+  * @retval LM75 measured temperature value.
+  */
+uint16_t LM75_ReadTemp(void)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint16_t tmp = 0;
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_TEMP);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
+  tmp |= LM75_BufferRX[1];    
+  
+  /*!< Return Temperature value */
+  return (uint16_t)(tmp >> 7);
+}
+
+/**
+  * @brief  Read the configuration register from the LM75.
+  * @param  None
+  * @retval LM75 configuration register value.
+  */
+uint8_t LM75_ReadConfReg(void)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0}; 
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Return Temperature value */
+  return (uint8_t)LM75_BufferRX[0];
+}
+
+/**
+  * @brief  Write to the configuration register of the LM75.
+  * @param  RegValue: sepecifies the value to be written to LM75 configuration 
+  *         register.
+  * @retval None
+  */
+uint8_t LM75_WriteConfReg(uint8_t RegValue)
+{   
+  uint8_t LM75_BufferTX = 0;  
+  LM75_BufferTX = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
+  
+  return LM75_OK;
+  
+}
+
+/**
+  * @brief  Enables or disables the LM75.
+  * @param  NewState: specifies the LM75 new status. This parameter can be ENABLE
+  *         or DISABLE.  
+  * @retval None
+  */
+uint8_t LM75_ShutDown(FunctionalState NewState)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint8_t LM75_BufferTX = 0;
+  __IO uint8_t RegValue = 0;    
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Get received data */
+  RegValue = (uint8_t)LM75_BufferRX[0];
+  
+  /*---------------------------- Transmission Phase ---------------------------*/
+  
+  /*!< Enable or disable SD bit */
+  if (NewState != DISABLE)
+  {
+    /*!< Enable LM75 */
+    LM75_BufferTX = RegValue & LM75_SD_RESET;
+  }
+  else
+  {
+    /*!< Disable LM75 */
+    LM75_BufferTX = RegValue | LM75_SD_SET;
+  }  
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
+  
+  return LM75_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.h
new file mode 100644
index 0000000..5f76937
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_i2c_tsensor.h
@@ -0,0 +1,179 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_i2c_tsensor.h
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210b_eval_i2c_tsensor firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210B_EVAL_I2C_TSENSOR_H
+#define __STM3210B_EVAL_I2C_TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_I2C_TSENSOR
+  * @{
+  */  
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Exported_Types
+  * @{
+  */
+   
+ /** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  LM75_DMA_TX = 0,
+  LM75_DMA_RX = 1
+}LM75_DMADirection_TypeDef;
+
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  LM75_OK = 0,
+  LM75_FAIL
+}LM75_Status_TypDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Exported_Constants
+  * @{
+  */ 
+    
+/* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback(). 
+   If This Callback is enabled, it should be implemented by user in main function .
+   LM75_TimeoutUserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_TIMEOUT_USER_CALLBACK */    
+    
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define LM75_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define LM75_LONG_TIMEOUT         ((uint32_t)(10 * LM75_FLAG_TIMEOUT))    
+    
+
+/**
+  * @brief  Block Size
+  */
+#define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
+#define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
+#define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
+#define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
+#define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
+#define LM75_ADDR           0x90   /*!< LM75 address */
+#define LM75_I2C_SPEED      100000 /*!< I2C Speed */
+  
+   
+
+/**
+  * @}
+  */
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_I2C_TSENSOR_Exported_Functions
+  * @{
+  */ 
+void LM75_DeInit(void);
+void LM75_Init(void);
+ErrorStatus LM75_GetStatus(void);
+uint16_t LM75_ReadTemp(void);
+uint16_t LM75_ReadReg(uint8_t RegName);
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t LM75_ReadConfReg(void);
+uint8_t LM75_WriteConfReg(uint8_t RegValue);
+uint8_t LM75_ShutDown(FunctionalState NewState);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t LM75_TIMEOUT_UserCallback(void);
+#else
+ #define LM75_TIMEOUT_UserCallback()  LM75_FAIL
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210B_EVAL_I2C_TSENSOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
new file mode 100644
index 0000000..b30f9ef
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.c
@@ -0,0 +1,1884 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_lcd.c
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
+  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
+  *          Liquid Crystal Display Module of STM3210B-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval_lcd.h"
+#include "../Common/fonts.c"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+    
+/** @defgroup STM3210B_EVAL_LCD 
+  * @briefThis file includes the LCD driver for AM-240320LTNQW00H (LCD_HX8312),
+  *          AM-240320L8TNQW00H (LCD_ILI9320), AM-240320LDTNQW00H (LCD_SPFD5408B)
+  *          Liquid Crystal Display Module of STM3210B-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Defines
+  * @{
+  */ 
+#define LCD_ILI9320        0x9320
+#define LCD_HX8312         0x8312
+#define LCD_SPFD5408       0x5408
+#define START_BYTE         0x70
+#define SET_INDEX          0x00
+#define READ_STATUS        0x01
+#define LCD_WRITE_REG      0x02
+#define LCD_READ_REG       0x03
+#define MAX_POLY_CORNERS   200
+#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
+#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Macros
+  * @{
+  */
+#define ABS(X)  ((X) > 0 ? (X) : -(X))   
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Variables
+  * @{
+  */ 
+static sFONT *LCD_Currentfonts;
+/* Global variables to set the written text color */
+__IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
+static __IO uint32_t LCDType = LCD_ILI9320;
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Function_Prototypes
+  * @{
+  */ 
+#ifndef USE_Delay
+static void delay(vu32 nCount);
+#endif /* USE_Delay*/
+
+static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue);
+static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue);
+static void PutPixel(int16_t x, int16_t y);
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_LCD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the LCD.
+  * @param  None
+  * @retval None
+  */
+void LCD_DeInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /*!< LCD Display Off */
+  LCD_DisplayOff();
+
+  /*!< LCD_SPI disable */
+  SPI_Cmd(LCD_SPI, DISABLE);
+  
+  /*!< LCD_SPI DeInit */
+  SPI_I2S_DeInit(LCD_SPI);
+   
+  /*!< Disable SPI clock  */
+  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
+    
+  /* Configure NCS in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Configure NWR(RNW), RS in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
+  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
+  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Configure SPI pins: SCK, MISO and MOSI */
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Setups the LCD.
+  * @param  None
+  * @retval None
+  */
+void LCD_Setup(void)
+{ 
+/* Configure the LCD Control pins --------------------------------------------*/
+  LCD_CtrlLinesConfig();
+  
+/* Configure the LCD_SPI interface ----------------------------------------------*/
+  LCD_SPIConfig();
+  if(LCDType == LCD_ILI9320)
+  {
+    _delay_(5); /* Delay 50 ms */
+    /* Start Initial Sequence ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
+    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
+    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
+    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
+    /* Power On sequence -----------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
+    _delay_(5);                /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
+    _delay_(5);                /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
+    /* Adjust the Gamma Curve ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0006);
+    LCD_WriteReg(LCD_REG_49, 0x0101);
+    LCD_WriteReg(LCD_REG_50, 0x0003);
+    LCD_WriteReg(LCD_REG_53, 0x0106);
+    LCD_WriteReg(LCD_REG_54, 0x0b02);
+    LCD_WriteReg(LCD_REG_55, 0x0302);
+    LCD_WriteReg(LCD_REG_56, 0x0707);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0600);
+    LCD_WriteReg(LCD_REG_61, 0x020b);
+  
+    /* Set GRAM area ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
+    /* Partial Display Control -----------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+    /* Panel Control ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+  }
+  else if(LCDType == LCD_SPFD5408)
+  {   
+    /* Start Initial Sequence --------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
+    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
+    /* Power On sequence -------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */  
+    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                 /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    _delay_(5);                  /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
+    _delay_(5);                 /* Delay 50 ms */ 
+    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
+    _delay_(5);                 /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
+    /* Adjust the Gamma Curve --------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0007);
+    LCD_WriteReg(LCD_REG_49, 0x0302);
+    LCD_WriteReg(LCD_REG_50, 0x0105);
+    LCD_WriteReg(LCD_REG_53, 0x0206);
+    LCD_WriteReg(LCD_REG_54, 0x0808);
+    LCD_WriteReg(LCD_REG_55, 0x0206);
+    LCD_WriteReg(LCD_REG_56, 0x0504);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0105);
+    LCD_WriteReg(LCD_REG_61, 0x0808);
+    /* Set GRAM area -----------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
+    /* Partial Display Control -------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+    /* Panel Control -----------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+    /* Set GRAM write direction and BGR = 1
+       I/D=01 (Horizontal : increment, Vertical : decrement)
+       AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
+  }
+  else if(LCDType == LCD_HX8312)
+  {
+    /* Enable the LCD Oscillator ---------------------------------------------*/
+    LCD_WriteReg(LCD_REG_1, 0x10);
+    LCD_WriteReg(LCD_REG_0, 0xA0);
+    LCD_WriteReg(LCD_REG_3, 0x01);
+    _delay_(1); /* Delay 10 ms */
+    LCD_WriteReg(LCD_REG_3, 0x00);
+    LCD_WriteReg(LCD_REG_43, 0x04);
+  
+    LCD_WriteReg(LCD_REG_40, 0x18);
+    LCD_WriteReg(LCD_REG_26, 0x05);
+    LCD_WriteReg(LCD_REG_37, 0x05);
+    LCD_WriteReg(LCD_REG_25, 0x00);
+    
+    /* LCD Power On ----------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_28, 0x73);
+    LCD_WriteReg(LCD_REG_36, 0x74);
+    LCD_WriteReg(LCD_REG_30, 0x01);
+    LCD_WriteReg(LCD_REG_24, 0xC1);
+    _delay_(1); /* Delay 10 ms */
+    LCD_WriteReg(LCD_REG_24, 0xE1);
+    LCD_WriteReg(LCD_REG_24, 0xF1);
+    _delay_(6); /* Delay 60 ms */
+    LCD_WriteReg(LCD_REG_24, 0xF5);
+    _delay_(6); /* Delay 60 ms */
+    LCD_WriteReg(LCD_REG_27, 0x09);
+    _delay_(1); /* Delay 10 ms */
+    LCD_WriteReg(LCD_REG_31, 0x11);
+    LCD_WriteReg(LCD_REG_32, 0x0E);
+    LCD_WriteReg(LCD_REG_30, 0x81);
+    _delay_(1); /* Delay 10 ms */
+    
+    /* Chip Set --------------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_157, 0x00);
+    LCD_WriteReg(LCD_REG_192, 0x00);
+   
+    LCD_WriteReg(LCD_REG_14, 0x00);
+    LCD_WriteReg(LCD_REG_15, 0x00);
+    LCD_WriteReg(LCD_REG_16, 0x00);
+    LCD_WriteReg(LCD_REG_17, 0x00);
+    LCD_WriteReg(LCD_REG_18, 0x00);
+    LCD_WriteReg(LCD_REG_19, 0x00);
+    LCD_WriteReg(LCD_REG_20, 0x00);
+    LCD_WriteReg(LCD_REG_21, 0x00);
+    LCD_WriteReg(LCD_REG_22, 0x00);
+    LCD_WriteReg(LCD_REG_23, 0x00);
+   
+    LCD_WriteReg(LCD_REG_52, 0x01);
+    LCD_WriteReg(LCD_REG_53, 0x00);
+    LCD_WriteReg(LCD_REG_75, 0x00);
+    LCD_WriteReg(LCD_REG_76, 0x00);
+    LCD_WriteReg(LCD_REG_78, 0x00);
+    LCD_WriteReg(LCD_REG_79, 0x00);
+    LCD_WriteReg(LCD_REG_80, 0x00);
+  
+    LCD_WriteReg(LCD_REG_60, 0x00);
+    LCD_WriteReg(LCD_REG_61, 0x00);
+    LCD_WriteReg(LCD_REG_62, 0x01);
+    LCD_WriteReg(LCD_REG_63, 0x3F);
+    LCD_WriteReg(LCD_REG_64, 0x02);
+    LCD_WriteReg(LCD_REG_65, 0x02);
+    LCD_WriteReg(LCD_REG_66, 0x00);
+    LCD_WriteReg(LCD_REG_67, 0x00);
+    LCD_WriteReg(LCD_REG_68, 0x00);
+    LCD_WriteReg(LCD_REG_69, 0x00);
+    LCD_WriteReg(LCD_REG_70, 0xEF);
+    LCD_WriteReg(LCD_REG_71, 0x00);
+    LCD_WriteReg(LCD_REG_72, 0x00);
+    LCD_WriteReg(LCD_REG_73, 0x01);
+    LCD_WriteReg(LCD_REG_74, 0x3F);
+  
+    LCD_WriteReg(LCD_REG_29, 0x08);  /* R29:Gate scan direction setting */
+  
+    LCD_WriteReg(LCD_REG_134, 0x00);
+    LCD_WriteReg(LCD_REG_135, 0x30);
+    LCD_WriteReg(LCD_REG_136, 0x02);
+    LCD_WriteReg(LCD_REG_137, 0x05);
+  
+    LCD_WriteReg(LCD_REG_141, 0x01);  /* R141:Register set-up mode for one line clock */
+    LCD_WriteReg(LCD_REG_139, 0x20);  /* R139:One line SYSCLK number in one-line */
+    LCD_WriteReg(LCD_REG_51, 0x01);  /* R51:N line inversion setting */
+    LCD_WriteReg(LCD_REG_55, 0x01);  /* R55:Scanning method setting */
+    LCD_WriteReg(LCD_REG_118, 0x00);
+   
+    /* Gamma Set -------------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_143, 0x10);
+    LCD_WriteReg(LCD_REG_144, 0x67);
+    LCD_WriteReg(LCD_REG_145, 0x07);
+    LCD_WriteReg(LCD_REG_146, 0x65);
+    LCD_WriteReg(LCD_REG_147, 0x07);
+    LCD_WriteReg(LCD_REG_148, 0x01);
+    LCD_WriteReg(LCD_REG_149, 0x76);
+    LCD_WriteReg(LCD_REG_150, 0x56);
+    LCD_WriteReg(LCD_REG_151, 0x00);
+    LCD_WriteReg(LCD_REG_152, 0x06);
+    LCD_WriteReg(LCD_REG_153, 0x03);
+    LCD_WriteReg(LCD_REG_154, 0x00);
+  
+    /* Display On ------------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_1, 0x50);
+    LCD_WriteReg(LCD_REG_5, 0x04);
+    LCD_WriteReg(LCD_REG_0, 0x80);
+    LCD_WriteReg(LCD_REG_59, 0x01);
+    _delay_(4);  /* Delay 40 ms */
+    LCD_WriteReg(LCD_REG_0, 0x20);
+  }  
+}
+
+
+/**
+  * @brief  Initializes the LCD.
+  * @param  None
+  * @retval None
+  */
+void STM3210B_LCD_Init(void)
+{
+  /* Setups the LCD */
+  LCD_Setup();
+  /* Try to read new LCD controller ID 0x9320 */
+  if (LCD_ReadReg(LCD_REG_0) == LCD_ILI9320)
+  {
+    LCDType = LCD_ILI9320;
+  }
+  else
+  {
+    LCDType = LCD_SPFD5408;
+    /* Setups the LCD */
+    LCD_Setup();
+    /* Try to read new LCD controller ID 0x5408 */
+    if (LCD_ReadReg(LCD_REG_0) != LCD_SPFD5408)
+    {
+      LCDType = LCD_HX8312;
+      /* Setups the LCD */
+      LCD_Setup();
+    }
+  }
+  LCD_SetFont(&LCD_DEFAULT_FONT);
+}
+
+/**
+  * @brief  Sets the LCD Text and Background colors.
+  * @param  _TextColor: specifies the Text Color.
+  * @param  _BackColor: specifies the Background Color.
+  * @retval None
+  */
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
+{
+  TextColor = _TextColor; 
+  BackColor = _BackColor;
+}
+
+/**
+  * @brief  Gets the LCD Text and Background colors.
+  * @param  _TextColor: pointer to the variable that will contain the Text 
+            Color.
+  * @param  _BackColor: pointer to the variable that will contain the Background 
+            Color.
+  * @retval None
+  */
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)
+{
+  *_TextColor = TextColor; *_BackColor = BackColor;
+}
+
+/**
+  * @brief  Sets the Text color.
+  * @param  Color: specifies the Text color code RGB(5-6-5).
+  * @retval None
+  */
+void LCD_SetTextColor(__IO uint16_t Color)
+{
+  TextColor = Color;
+}
+
+
+/**
+  * @brief  Sets the Background color.
+  * @param  Color: specifies the Background color code RGB(5-6-5).
+  * @retval None
+  */
+void LCD_SetBackColor(__IO uint16_t Color)
+{
+  BackColor = Color;
+}
+
+/**
+  * @brief  Sets the Text Font.
+  * @param  fonts: specifies the font to be used.
+  * @retval None
+  */
+void LCD_SetFont(sFONT *fonts)
+{
+  LCD_Currentfonts = fonts;
+}
+
+/**
+  * @brief  Gets the Text Font.
+  * @param  None.
+  * @retval the used font.
+  */
+sFONT *LCD_GetFont(void)
+{
+  return LCD_Currentfonts;
+}
+
+/**
+  * @brief  Clears the selected line.
+  * @param  Line: the Line to be cleared.
+  *   This parameter can be one of the following values:
+  *     @arg Linex: where x can be 0..n
+  * @retval None
+  */
+void LCD_ClearLine(uint8_t Line)
+{
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
+  /* Send the string character by character on lCD */
+  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
+  {
+    /* Display one character on LCD */
+    LCD_DisplayChar(Line, refcolumn, ' ');
+    /* Decrement the column position by 16 */
+    refcolumn -= LCD_Currentfonts->Width;
+  }
+}
+
+
+/**
+  * @brief  Clears the hole LCD.
+  * @param  Color: the color of the background.
+  * @retval None
+  */
+void LCD_Clear(uint16_t Color)
+{
+  uint32_t index = 0;
+  
+  LCD_SetCursor(0x00, 0x013F); 
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  }
+  for(index = 0; index < 76800; index++)
+  {
+    LCD_WriteRAM(Color);
+  }
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
+  }  
+}
+
+
+/**
+  * @brief  Sets the cursor position.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position. 
+  * @retval None
+  */
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_WriteReg(LCD_REG_32, Xpos);
+    LCD_WriteReg(LCD_REG_33, Ypos);
+  }
+  else if(LCDType == LCD_HX8312)
+  {
+    LCD_WriteReg(LCD_REG_66, Xpos);
+    LCD_WriteReg(LCD_REG_67, ((Ypos & 0x100)>> 8));
+    LCD_WriteReg(LCD_REG_68, (Ypos & 0xFF));
+  }
+}
+
+
+/**
+  * @brief  Draws a character on LCD.
+  * @param  Xpos: the Line where to display the character shape.
+  * @param  Ypos: start column address.
+  * @param  c: pointer to the character data.
+  * @retval None
+  */
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
+{
+  uint32_t index = 0, i = 0;
+  uint8_t Xaddress = 0;
+   
+  Xaddress = Xpos;
+  
+  LCD_SetCursor(Xaddress, Ypos);
+  
+  for(index = 0; index < LCD_Currentfonts->Height; index++)
+  {
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+    }
+    for(i = 0; i < LCD_Currentfonts->Width; i++)
+    {
+      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
+        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))
+
+      {
+        LCD_WriteRAM(BackColor);
+      }
+      else
+      {
+        LCD_WriteRAM(TextColor);
+      }
+    }
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+    }  
+    Xaddress++;
+    LCD_SetCursor(Xaddress, Ypos);
+  }
+}
+
+
+/**
+  * @brief  Displays one character (16dots width, 24dots height).
+  * @param  Line: the Line where to display the character shape .
+  *   This parameter can be one of the following values:
+  *     @arg Linex: where x can be 0..9
+  * @param  Column: start column address.
+  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
+  * @retval None
+  */
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
+{
+  Ascii -= 32;
+  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
+}
+
+
+/**
+  * @brief  Displays a maximum of 20 char on the LCD.
+  * @param  Line: the Line where to display the character shape .
+  *   This parameter can be one of the following values:
+  *     @arg Linex: where x can be 0..9
+  * @param  *ptr: pointer to string to display on LCD.
+  * @retval None
+  */
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
+{
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
+
+  /* Send the string character by character on lCD */
+  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
+  {
+    /* Display one character on LCD */
+    LCD_DisplayChar(Line, refcolumn, *ptr);
+    /* Decrement the column position by 16 */
+    refcolumn -= LCD_Currentfonts->Width;
+    /* Point on the next character */
+    ptr++;
+  }
+}
+
+
+/**
+  * @brief  Sets a display window
+  * @param  Xpos: specifies the X buttom left position.
+  * @param  Ypos: specifies the Y buttom left position.
+  * @param  Height: display window height.
+  * @param  Width: display window width.
+  * @retval None
+  */
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Horizontal GRAM Start Address */
+    if(Xpos >= Height)
+    {
+      LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
+    }
+    else
+    {
+      LCD_WriteReg(LCD_REG_80, 0);
+    }
+    /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_81, Xpos);
+    /* Vertical GRAM Start Address */
+    if(Ypos >= Width)
+    {
+      LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
+    }  
+    else
+    {
+      LCD_WriteReg(LCD_REG_82, 0);
+    }
+    /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_83, Ypos);
+  }
+  else if(LCDType == LCD_HX8312)
+  {  
+    LCD_WriteReg(LCD_REG_1, 0xD0);
+    LCD_WriteReg(LCD_REG_5, 0x14);
+  
+    LCD_WriteReg(LCD_REG_69, (Xpos - Height + 1));
+    LCD_WriteReg(LCD_REG_70, Xpos);
+ 
+    LCD_WriteReg(LCD_REG_71, (((Ypos - Width + 1) & 0x100)>> 8));
+    LCD_WriteReg(LCD_REG_72, ((Ypos - Width + 1) & 0xFF));
+    LCD_WriteReg(LCD_REG_73, ((Ypos & 0x100)>> 8));
+    LCD_WriteReg(LCD_REG_74, (Ypos & 0xFF));
+  }
+  LCD_SetCursor(Xpos, Ypos);
+}
+
+
+/**
+  * @brief  Disables LCD Window mode.
+  * @param  None
+  * @retval None
+  */
+void LCD_WindowModeDisable(void)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_SetDisplayWindow(239, 0x13F, 240, 320);
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+  }
+  else if(LCDType == LCD_HX8312)
+  {
+    LCD_WriteReg(LCD_REG_1, 0x50);
+    LCD_WriteReg(LCD_REG_5, 0x04); 
+  }
+    
+}
+
+
+/**
+  * @brief  Displays a line.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Length: line length.
+  * @param  Direction: line direction.
+  *   This parameter can be one of the following values: Vertical or Horizontal.
+  * @retval None
+  */
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
+{
+  uint32_t i = 0;
+  
+  LCD_SetCursor(Xpos, Ypos);
+  if(Direction == LCD_DIR_HORIZONTAL)
+  { 
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+    }
+    for(i = 0; i < Length; i++)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+    }
+  }
+  else
+  {
+   for(i = 0; i < Length; i++)
+    {
+      if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+      {
+        LCD_WriteRAMWord(TextColor);
+      }
+      else  if(LCDType == LCD_HX8312)
+      {
+        LCD_WriteRAM(TextColor);
+      }
+      Xpos++;
+      LCD_SetCursor(Xpos, Ypos);
+    }
+  }
+}
+
+
+/**
+  * @brief  Displays a rectangle.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Height: display rectangle height.
+  * @param  Width: display rectangle width.
+  * @retval None
+  */
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+{
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
+  
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
+}
+
+
+/**
+  * @brief  Displays a circle.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Radius
+  * @retval None
+  */
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
+{
+  int32_t  D;/* Decision Variable */ 
+  uint32_t  CurX;/* Current X Value */
+  uint32_t  CurY;/* Current Y Value */ 
+  
+  D = 3 - (Radius << 1);
+  CurX = 0;
+  CurY = Radius;
+  
+  while (CurX <= CurY)
+  {
+    LCD_SetCursor(Xpos + CurX, Ypos + CurY);
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos - CurX, Ypos + CurY);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos - CurX, Ypos - CurY);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos + CurY, Ypos + CurX);
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos + CurY, Ypos - CurX);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos - CurY, Ypos + CurX);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    LCD_SetCursor(Xpos - CurY, Ypos - CurX);
+
+    if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+    {
+      LCD_WriteRAMWord(TextColor);
+    }
+    else if(LCDType == LCD_HX8312)
+    {
+      LCD_WriteRAM(TextColor);
+    }
+    if (D < 0)
+    { 
+      D += (CurX << 2) + 6;
+    }
+    else
+    {
+      D += ((CurX - CurY) << 2) + 10;
+      CurY--;
+    }
+    CurX++;
+  }
+}
+
+
+/**
+  * @brief  Displays a monocolor picture.
+  * @param  Pict: pointer to the picture array.
+  * @retval None
+  */
+void LCD_DrawMonoPict(const uint32_t *Pict)
+{
+  uint32_t index = 0, i = 0;
+  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
+
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  }
+
+  for(index = 0; index < 2400; index++)
+  {
+    for(i = 0; i < 32; i++)
+    {
+      if((Pict[index] & (1 << i)) == 0x00)
+      {
+        LCD_WriteRAM(BackColor);
+      }
+      else
+      {
+        LCD_WriteRAM(TextColor);
+      }
+    }
+  }
+
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+  }
+}
+
+#ifdef USE_LCD_DrawBMP 
+/**
+  * @brief  Displays a bitmap picture loaded in the SPI Flash.
+  * @param  BmpAddress: Bmp picture address in the SPI Flash.
+  * @retval None
+  */
+void LCD_DrawBMP(uint32_t BmpAddress)
+{
+  uint32_t i = 0, size = 0;
+  /* Read bitmap size */
+  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
+  /* get bitmap data address offset */
+  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
+  
+  size = (size - i)/2;
+  sFLASH_StartReadSequence(BmpAddress + i);
+  /* Disable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, DISABLE);
+  /* SPI in 16-bit mode */
+  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
+  /* Enable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, ENABLE);
+  
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1008);
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  }
+  
+  /* Read bitmap data from SPI Flash and send them to LCD */
+  for(i = 0; i < size; i++)
+  {
+    LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
+  }
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+  }
+
+  /* Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+  /* Disable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, DISABLE);
+  /* SPI in 8-bit mode */
+  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
+  /* Enable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, ENABLE);
+
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
+    /* AM = 1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+  }
+}
+#endif /* USE_LCD_DrawBMP */
+ 
+/**
+  * @brief  Displays a full rectangle.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Height: rectangle height.
+  * @param  Width: rectangle width.
+  * @retval None
+  */
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
+{
+  LCD_SetTextColor(TextColor);
+
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
+  
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
+
+  Width -= 2;
+  Height--;
+  Ypos--;
+
+  LCD_SetTextColor(BackColor);
+
+  while(Height--)
+  {
+    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);    
+  }
+
+  LCD_SetTextColor(TextColor);
+}
+
+/**
+  * @brief  Displays a full circle.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Radius
+  * @retval None
+  */
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
+{
+  int32_t  D;    /* Decision Variable */ 
+  uint32_t  CurX;/* Current X Value */
+  uint32_t  CurY;/* Current Y Value */ 
+  
+  D = 3 - (Radius << 1);
+
+  CurX = 0;
+  CurY = Radius;
+  
+  LCD_SetTextColor(BackColor);
+
+  while (CurX <= CurY)
+  {
+    if(CurY > 0) 
+    {
+      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
+      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);
+    }
+
+    if(CurX > 0) 
+    {
+      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
+      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);
+    }
+    if (D < 0)
+    { 
+      D += (CurX << 2) + 6;
+    }
+    else
+    {
+      D += ((CurX - CurY) << 2) + 10;
+      CurY--;
+    }
+    CurX++;
+  }
+
+  LCD_SetTextColor(TextColor);
+  LCD_DrawCircle(Xpos, Ypos, Radius);
+}
+
+/**
+  * @brief  Displays an uni line (between two points).
+  * @param  x1: specifies the point 1 x position.
+  * @param  y1: specifies the point 1 y position.
+  * @param  x2: specifies the point 2 x position.
+  * @param  y2: specifies the point 2 y position.
+  * @retval None
+  */
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
+{
+  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, 
+  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0, 
+  curpixel = 0;
+  
+  deltax = ABS(x2 - x1);        /* The difference between the x's */
+  deltay = ABS(y2 - y1);        /* The difference between the y's */
+  x = x1;                       /* Start x off at the first pixel */
+  y = y1;                       /* Start y off at the first pixel */
+  
+  if (x2 >= x1)                 /* The x-values are increasing */
+  {
+    xinc1 = 1;
+    xinc2 = 1;
+  }
+  else                          /* The x-values are decreasing */
+  {
+    xinc1 = -1;
+    xinc2 = -1;
+  }
+  
+  if (y2 >= y1)                 /* The y-values are increasing */
+  {
+    yinc1 = 1;
+    yinc2 = 1;
+  }
+  else                          /* The y-values are decreasing */
+  {
+    yinc1 = -1;
+    yinc2 = -1;
+  }
+  
+  if (deltax >= deltay)         /* There is at least one x-value for every y-value */
+  {
+    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */
+    yinc2 = 0;                  /* Don't change the y for every iteration */
+    den = deltax;
+    num = deltax / 2;
+    numadd = deltay;
+    numpixels = deltax;         /* There are more x-values than y-values */
+  }
+  else                          /* There is at least one y-value for every x-value */
+  {
+    xinc2 = 0;                  /* Don't change the x for every iteration */
+    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */
+    den = deltay;
+    num = deltay / 2;
+    numadd = deltax;
+    numpixels = deltay;         /* There are more y-values than x-values */
+  }
+  
+  for (curpixel = 0; curpixel <= numpixels; curpixel++)
+  {
+    PutPixel(x, y);             /* Draw the current pixel */
+    num += numadd;              /* Increase the numerator by the top of the fraction */
+    if (num >= den)             /* Check if numerator >= denominator */
+    {
+      num -= den;               /* Calculate the new numerator value */
+      x += xinc1;               /* Change the x as appropriate */
+      y += yinc1;               /* Change the y as appropriate */
+    }
+    x += xinc2;                 /* Change the x as appropriate */
+    y += yinc2;                 /* Change the y as appropriate */
+  }
+}
+
+/**
+  * @brief  Displays an polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @retval None
+  */
+void LCD_PolyLine(pPoint Points, uint16_t PointCount)
+{
+  int16_t X = 0, Y = 0;
+
+  if(PointCount < 2)
+  {
+    return;
+  }
+
+  while(--PointCount)
+  {
+    X = Points->X;
+    Y = Points->Y;
+    Points++;
+    LCD_DrawUniLine(X, Y, Points->X, Points->Y);
+  }
+}
+
+/**
+  * @brief  Displays an relative polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @param  Closed: specifies if the draw is closed or not.
+  *           1: closed, 0 : not closed.
+  * @retval None
+  */
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)
+{
+  int16_t X = 0, Y = 0;
+  pPoint First = Points;
+
+  if(PointCount < 2)
+  {
+    return;
+  }  
+  X = Points->X;
+  Y = Points->Y;
+  while(--PointCount)
+  {
+    Points++;
+    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);
+    X = X + Points->X;
+    Y = Y + Points->Y;
+  }
+  if(Closed)
+  {
+    LCD_DrawUniLine(First->X, First->Y, X, Y);
+  }  
+}
+
+/**
+  * @brief  Displays a closed polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @retval None
+  */
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)
+{
+  LCD_PolyLine(Points, PointCount);
+  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);
+}
+
+/**
+  * @brief  Displays a relative polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @retval None
+  */
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)
+{
+  LCD_PolyLineRelativeClosed(Points, PointCount, 0);
+}
+
+/**
+  * @brief  Displays a closed relative polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @retval None
+  */
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
+{
+  LCD_PolyLineRelativeClosed(Points, PointCount, 1);
+}
+
+
+/**
+  * @brief  Displays a  full polyline (between many points).
+  * @param  Points: pointer to the points array.
+  * @param  PointCount: Number of points.
+  * @retval None
+  */
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
+{
+  /*  public-domain code by Darel Rex Finley, 2007 */
+  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,
+  j = 0, swap = 0;
+  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;
+
+  IMAGE_LEFT = IMAGE_RIGHT = Points->X;
+  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;
+
+  for(i = 1; i < PointCount; i++)
+  {
+    pixelX = POLY_X(i);
+    if(pixelX < IMAGE_LEFT)
+    {
+      IMAGE_LEFT = pixelX;
+    }
+    if(pixelX > IMAGE_RIGHT)
+    {
+      IMAGE_RIGHT = pixelX;
+    }
+    
+    pixelY = POLY_Y(i);
+    if(pixelY < IMAGE_TOP)
+    { 
+      IMAGE_TOP = pixelY;
+    }
+    if(pixelY > IMAGE_BOTTOM)
+    {
+      IMAGE_BOTTOM = pixelY;
+    }
+  }
+  
+  LCD_SetTextColor(BackColor);  
+
+  /*  Loop through the rows of the image. */
+  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++) 
+  {  
+    /* Build a list of nodes. */
+    nodes = 0; j = PointCount-1;
+
+    for (i = 0; i < PointCount; i++) 
+    {
+      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
+      {
+        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
+      }
+      j = i; 
+    }
+  
+    /* Sort the nodes, via a simple "Bubble" sort. */
+    i = 0;
+    while (i < nodes-1) 
+    {
+      if (nodeX[i]>nodeX[i+1]) 
+      {
+        swap = nodeX[i]; 
+        nodeX[i] = nodeX[i+1]; 
+        nodeX[i+1] = swap; 
+        if(i)
+        {
+          i--; 
+        }
+      }
+      else 
+      {
+        i++;
+      }
+    }
+  
+    /*  Fill the pixels between node pairs. */
+    for (i = 0; i < nodes; i+=2) 
+    {
+      if(nodeX[i] >= IMAGE_RIGHT) 
+      {
+        break;
+      }
+      if(nodeX[i+1] > IMAGE_LEFT) 
+      {
+        if (nodeX[i] < IMAGE_LEFT)
+        {
+          nodeX[i]=IMAGE_LEFT;
+        }
+        if(nodeX[i+1] > IMAGE_RIGHT)
+        {
+          nodeX[i+1] = IMAGE_RIGHT;
+        }
+        LCD_SetTextColor(BackColor);
+        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);
+        LCD_SetTextColor(TextColor);
+        PutPixel(pixelY, nodeX[i+1]);
+        PutPixel(pixelY, nodeX[i]);
+        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */
+      }
+    }
+  } 
+
+  /* draw the edges */
+  LCD_SetTextColor(TextColor);
+}
+
+/**
+  * @brief  Reset LCD control line(/CS) and Send Start-Byte
+  * @param  Start_Byte: the Start-Byte to be sent
+  * @retval None
+  */
+void LCD_nCS_StartByte(uint8_t Start_Byte)
+{
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
+
+  SPI_I2S_SendData(LCD_SPI, Start_Byte);
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+}
+
+
+/**
+  * @brief  Writes index to select the LCD register.
+  * @param  LCD_Reg: address of the selected register.
+  * @retval None
+  */
+void LCD_WriteRegIndex(uint8_t LCD_Reg)
+{
+  /* Reset LCD control line(/CS) and Send Start-Byte */
+  LCD_nCS_StartByte(START_BYTE | SET_INDEX);
+
+  /* Write 16-bit Reg Index (High Byte is 0) */
+  SPI_I2S_SendData(LCD_SPI, 0x00);
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  SPI_I2S_SendData(LCD_SPI, LCD_Reg);
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Writes to the selected LCD ILI9320 register.
+  * @param  LCD_Reg: address of the selected register.
+  * @param  LCD_RegValue: value to write to the selected register.
+  * @retval None
+  */
+static void LCD_WriteRegILI9320(uint8_t LCD_Reg, uint16_t LCD_RegValue)
+{
+  /* Write 16-bit Index (then Write Reg) */
+  LCD_WriteRegIndex(LCD_Reg);
+
+  /* Write 16-bit Reg */
+  /* Reset LCD control line(/CS) and Send Start-Byte */
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
+
+  SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Reads the selected LCD Register.
+  * @param  LCD_Reg: address of the selected register.
+  * @retval LCD Register Value.
+  */
+uint16_t LCD_ReadReg(uint8_t LCD_Reg)
+{
+  uint16_t tmp = 0;
+  uint8_t i = 0;
+  
+  /* LCD_SPI prescaler: 4 */
+  LCD_SPI->CR1 &= 0xFFC7;
+  LCD_SPI->CR1 |= 0x0008;
+  /* Write 16-bit Index (then Read Reg) */
+  LCD_WriteRegIndex(LCD_Reg);
+  /* Read 16-bit Reg */
+  /* Reset LCD control line(/CS) and Send Start-Byte */
+  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
+  
+  for(i = 0; i < 5; i++)
+  {
+    SPI_I2S_SendData(LCD_SPI, 0xFF);
+    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+    {
+    }
+    /* One byte of invalid dummy data read after the start byte */
+    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+    {    
+    }
+    SPI_I2S_ReceiveData(LCD_SPI); 
+  }
+
+  SPI_I2S_SendData(LCD_SPI, 0xFF);
+
+  /* Read upper byte */
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  /* Read lower byte */
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  tmp = SPI_I2S_ReceiveData(LCD_SPI);
+  
+  
+  SPI_I2S_SendData(LCD_SPI, 0xFF);
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+
+  /* Read lower byte */
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+
+  tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+
+  /* LCD_SPI prescaler: 2 */
+  LCD_SPI->CR1 &= 0xFFC7;
+
+  return tmp;
+}
+
+
+/**
+  * @brief  Prepare to write to the LCD RAM.
+  * @param  None
+  * @retval None
+  */
+void LCD_WriteRAM_Prepare(void)
+{
+  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
+
+  /* Reset LCD control line(/CS) and Send Start-Byte */
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
+}
+
+
+/**
+  * @brief  Writes 1 word to the LCD RAM.
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
+  * @retval None
+  */
+void LCD_WriteRAMWord(uint16_t RGB_Code)
+{
+
+  LCD_WriteRAM_Prepare();
+
+  LCD_WriteRAM(RGB_Code);
+
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Writes to the selected LCD HX8312 register.
+  * @param  LCD_Reg: address of the selected register.
+  * @param  LCD_RegValue: value to write to the selected register.
+  * @retval None
+  */
+static void LCD_WriteRegHX8312(uint8_t LCD_Reg, uint8_t LCD_RegValue)
+{
+  uint16_t tmp = 0;
+  
+  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
+  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_RESET);
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
+  
+  tmp = LCD_Reg << 8;
+  tmp |= LCD_RegValue;
+   
+  SPI_I2S_SendData(LCD_SPI, tmp);
+
+  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  {
+  }
+  
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Writes to the selected LCD register.
+  * @param  LCD_Reg: address of the selected register.
+  * @param  LCD_RegValue: value to write to the selected register.
+  * @retval None
+  */
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_WriteRegILI9320(LCD_Reg, LCD_RegValue);
+  }
+  else if(LCDType == LCD_HX8312)
+  {
+    LCD_WriteRegHX8312(LCD_Reg, ((uint8_t)LCD_RegValue));
+  }
+}
+
+
+/**
+  * @brief  Writes to the LCD RAM.
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
+  * @retval None
+  */
+void LCD_WriteRAM(uint16_t RGB_Code)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
+    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+    {
+    }
+    SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
+    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+    {
+    }
+  }
+
+  if(LCDType == LCD_HX8312)
+  {
+    LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_RESET);
+    LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
+    SPI_I2S_SendData(LCD_SPI, RGB_Code);
+
+    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+    {
+    }
+  
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+  }
+}
+
+
+/**
+  * @brief  Power on the LCD.
+  * @param  None
+  * @retval None
+  */
+void LCD_PowerOn(void)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Power On sequence ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);               /* Dis-charge capacitor power voltage (200ms) */
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
+    _delay_(5);                /* delay 50 ms */
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
+    _delay_(5);                /* delay 50 ms */
+    LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
+  }
+  else if(LCDType == LCD_HX8312)
+  {  
+    /* Power On Set */
+    LCD_WriteReg(LCD_REG_28, 0x73);
+    LCD_WriteReg(LCD_REG_36, 0x74);
+    LCD_WriteReg(LCD_REG_30, 0x01);
+    LCD_WriteReg(LCD_REG_24, 0xC1);
+    _delay_(1); /* Delay 10 ms */
+    LCD_WriteReg(LCD_REG_24, 0xE1);
+    LCD_WriteReg(LCD_REG_24, 0xF1);
+    _delay_(6); /* Delay 60 ms */
+    LCD_WriteReg(LCD_REG_24, 0xF5);
+    _delay_(6); /* Delay 60 ms */
+    LCD_WriteReg(LCD_REG_27, 0x09);
+    _delay_(1); /* Delay 10 ms */
+    LCD_WriteReg(LCD_REG_31, 0x11);
+    LCD_WriteReg(LCD_REG_32, 0x0E);
+    LCD_WriteReg(LCD_REG_30, 0x81);
+    _delay_(1); /* Delay 10 ms */
+  }
+}
+
+
+/**
+  * @brief  Enables the Display.
+  * @param  None
+  * @retval None
+  */
+void LCD_DisplayOn(void)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Display On */
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+  }
+  else if(LCDType == LCD_HX8312)
+  {  
+    LCD_WriteReg(LCD_REG_1, 0x50);
+    LCD_WriteReg(LCD_REG_5, 0x04);
+    /* Display On */
+    LCD_WriteReg(LCD_REG_0, 0x80);
+    LCD_WriteReg(LCD_REG_59, 0x01);
+    _delay_(4); /* Delay 40 ms */
+    LCD_WriteReg(LCD_REG_0, 0x20);
+  }  
+}
+
+
+/**
+  * @brief  Disables the Display.
+  * @param  None
+  * @retval None
+  */
+void LCD_DisplayOff(void)
+{
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Display Off */
+    LCD_WriteReg(LCD_REG_7, 0x0);
+  }
+  else if(LCDType == LCD_HX8312)
+  { 
+    /* Display Off */
+    LCD_WriteReg(LCD_REG_0, 0xA0);
+    _delay_(4);  /* Delay 40 ms */
+    LCD_WriteReg(LCD_REG_59, 0x00);
+  } 
+}
+
+
+/**
+  * @brief  Configures LCD control lines in Output Push-Pull mode.
+  * @param  None
+  * @retval None
+  */
+void LCD_CtrlLinesConfig(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK | LCD_NWR_GPIO_CLK | LCD_RS_GPIO_CLK, ENABLE);
+
+  /* Configure NCS in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Configure NWR(RNW), RS in Output Push-Pull mode */
+  GPIO_InitStructure.GPIO_Pin = LCD_RS_PIN;
+  GPIO_Init(LCD_RS_GPIO_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = LCD_NWR_PIN;
+  GPIO_Init(LCD_NWR_GPIO_PORT, &GPIO_InitStructure);
+  
+  LCD_CtrlLinesWrite(LCD_NWR_GPIO_PORT, LCD_NWR_PIN, Bit_SET);
+  LCD_CtrlLinesWrite(LCD_RS_GPIO_PORT, LCD_RS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Sets or reset LCD control lines.
+  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
+  * @param  CtrlPins: the Control line.
+  *   This parameter can be:
+  *     @arg LCD_NCS_PIN: Chip Select pin
+  *     @arg LCD_NWR_PIN: Read/Write Selection pin
+  *     @arg LCD_RS_PIN: Register/RAM Selection pin
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *   This parameter can be:
+  *     @arg Bit_RESET: to clear the port pin
+  *     @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
+{
+  /* Set or Reset the control line */
+  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
+}
+
+/**
+  * @brief  Configures the LCD_SPI interface.
+  * @param  None
+  * @retval None
+  */
+void LCD_SPIConfig(void)
+{
+  SPI_InitTypeDef    SPI_InitStructure;
+  GPIO_InitTypeDef   GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
+
+  /* Enable SPI clock  */
+  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
+
+  /* Configure SPI pins: SCK, MISO and MOSI */
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  SPI_I2S_DeInit(LCD_SPI);
+  
+  /* SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+    SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  }
+  else if(LCDType == LCD_HX8312)
+  {
+    SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
+    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+  }
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+
+  SPI_Init(LCD_SPI, &SPI_InitStructure);
+
+  /* SPI enable */
+  SPI_Cmd(LCD_SPI, ENABLE);
+}
+
+/**
+  * @brief  Displays a pixel.
+  * @param  x: pixel x.
+  * @param  y: pixel y.  
+  * @retval None
+  */
+static void PutPixel(int16_t x, int16_t y)
+{ 
+  if(x < 0 || x > 239 || y < 0 || y > 319)
+  {
+    return;  
+  }
+  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(vu32 nCount)
+{
+  vu32 index = 0; 
+  for(index = (100000 * nCount); index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
index 0584c8a..a733849 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_lcd.h
@@ -1,34 +1,41 @@
 /**
   ******************************************************************************
-  * @file    stm3210c_eval_lcd.h
+  * @file    stm3210b_eval_lcd.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the lcd firmware driver.
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210b_eval_lcd firmware driver.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210C_EVAL_LCD_H
-#define __STM3210C_EVAL_LCD_H
+#ifndef __STM3210B_EVAL_LCD_H
+#define __STM3210B_EVAL_LCD_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "stm3210b_eval.h"
 #include "../Common/fonts.h"
 
 /** @addtogroup Utilities
@@ -39,16 +46,16 @@
   * @{
   */ 
 
-/** @addtogroup STM3210C_EVAL
+/** @addtogroup STM3210B_EVAL
   * @{
   */
     
-/** @addtogroup STM3210C_EVAL_LCD
+/** @addtogroup STM3210B_EVAL_LCD
   * @{
   */ 
 
 
-/** @defgroup STM3210C_EVAL_LCD_Exported_Types
+/** @defgroup STM3210B_EVAL_LCD_Exported_Types
   * @{
   */
 typedef struct 
@@ -60,14 +67,16 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM3210C_EVAL_LCD_Exported_Constants
+
+
+/** @defgroup STM3210B_EVAL_LCD_Exported_Constants
   * @{
   */ 
 
 /**
  * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
  *        display a bitmap picture on the LCD. This function assumes that the bitmap
- *        file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however
+ *        file is loaded in the SPI Flash (mounted on STM3210B-EVAL board), however
  *        user can tailor it according to his application hardware requirement.     
  */
 /*#define USE_LCD_DrawBMP*/
@@ -86,7 +95,8 @@ typedef struct
                                    (with 10ms time base), using SysTick for example */
 #else
   #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif 
+#endif                                     
+
 
 /** 
   * @brief  LCD Control pins  
@@ -94,21 +104,27 @@ typedef struct
 #define LCD_NCS_PIN             GPIO_Pin_2                  
 #define LCD_NCS_GPIO_PORT       GPIOB                       
 #define LCD_NCS_GPIO_CLK        RCC_APB2Periph_GPIOB  
+#define LCD_NWR_PIN             GPIO_Pin_15
+#define LCD_NWR_GPIO_PORT       GPIOD
+#define LCD_NWR_GPIO_CLK        RCC_APB2Periph_GPIOD
+#define LCD_RS_PIN              GPIO_Pin_7                     
+#define LCD_RS_GPIO_PORT        GPIOD
+#define LCD_RS_GPIO_CLK         RCC_APB2Periph_GPIOD 
 
 /** 
   * @brief  LCD SPI Interface pins 
   */ 
-#define LCD_SPI			            SPI3
-#define LCD_SPI_CLK		          RCC_APB1Periph_SPI3
-#define LCD_SPI_SCK_PIN         GPIO_Pin_10                 
-#define LCD_SPI_SCK_GPIO_PORT   GPIOC                       
-#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOC  
-#define LCD_SPI_MISO_PIN        GPIO_Pin_11                 
-#define LCD_SPI_MISO_GPIO_PORT  GPIOC                       
-#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOC  
-#define LCD_SPI_MOSI_PIN        GPIO_Pin_12                 
-#define LCD_SPI_MOSI_GPIO_PORT  GPIOC                       
-#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOC       
+#define LCD_SPI			            SPI2
+#define LCD_SPI_CLK		          RCC_APB1Periph_SPI2
+#define LCD_SPI_SCK_PIN         GPIO_Pin_13                 
+#define LCD_SPI_SCK_GPIO_PORT   GPIOB                       
+#define LCD_SPI_SCK_GPIO_CLK    RCC_APB2Periph_GPIOB  
+#define LCD_SPI_MISO_PIN        GPIO_Pin_14                 
+#define LCD_SPI_MISO_GPIO_PORT  GPIOB                       
+#define LCD_SPI_MISO_GPIO_CLK   RCC_APB2Periph_GPIOB  
+#define LCD_SPI_MOSI_PIN        GPIO_Pin_15                 
+#define LCD_SPI_MOSI_GPIO_PORT  GPIOB                       
+#define LCD_SPI_MOSI_GPIO_CLK   RCC_APB2Periph_GPIOB 
 
 /** 
   * @brief  LCD Registers  
@@ -220,7 +236,11 @@ typedef struct
 #define LCD_REG_157           0x9D
 #define LCD_REG_192           0xC0
 #define LCD_REG_193           0xC1
+#define LCD_REG_227           0xE3
 #define LCD_REG_229           0xE5
+#define LCD_REG_231           0xE7
+#define LCD_REG_239           0xEF
+
 
 /** 
   * @brief  LCD color  
@@ -238,7 +258,7 @@ typedef struct
 
 /** 
   * @brief  LCD Lines depending on the chosen fonts.  
-  */ 
+  */
 #define LCD_LINE_0               LINE(0)
 #define LCD_LINE_1               LINE(1)
 #define LCD_LINE_2               LINE(2)
@@ -291,7 +311,7 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM3210C_EVAL_LCD_Exported_Macros
+/** @defgroup STM3210B_EVAL_LCD_Exported_Macros
   * @{
   */
 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))   
@@ -299,14 +319,16 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM3210C_EVAL_LCD_Exported_Functions
+
+
+/** @defgroup STM3210B_EVAL_LCD_Exported_Functions
   * @{
-  */
-void LCD_DeInit(void);   
+  */ 
+void LCD_DeInit(void);
 void LCD_Setup(void);
-void STM3210C_LCD_Init(void);
+void STM3210B_LCD_Init(void);
 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); 
 void LCD_SetTextColor(__IO uint16_t Color);
 void LCD_SetBackColor(__IO uint16_t Color);
 void LCD_ClearLine(uint8_t Line);
@@ -323,10 +345,7 @@ void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Directio
 void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
 void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
 void LCD_DrawMonoPict(const uint32_t *Pict);
-#ifdef USE_LCD_DrawBMP
-//void LCD_DrawBMP(uint32_t BmpAddress);
-void LCD_DrawBMP(const uint16_t *BmpAddress);
-#endif 
+void LCD_DrawBMP(uint32_t BmpAddress);
 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
 void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
 void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
@@ -351,14 +370,16 @@ void LCD_CtrlLinesConfig(void);
 void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
 void LCD_SPIConfig(void);
 
+/**
+  * @}
+  */ 
+  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM3210C_EVAL_LCD_H */
-/**
-  * @}
-  */ 
+#endif /* __STM3210B_EVAL_LCD_H */
+
 
 /**
   * @}
@@ -366,7 +387,7 @@ void LCD_SPIConfig(void);
 
 /**
   * @}
-  */
+  */ 
 
 /**
   * @}
@@ -374,6 +395,6 @@ void LCD_SPIConfig(void);
 
 /**
   * @}
-  */ 
-     
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+  */   
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.c
new file mode 100644
index 0000000..bb827e2
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.c
@@ -0,0 +1,546 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_spi_flash.c
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file provides a set of functions needed to manage the SPI M25Pxxx
+  *          FLASH memory mounted on STM3210B-EVAL board. 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32 hardware resources (SPI and 
+  *          GPIO) are defined in stm3210b_eval.h file, and the initialization is 
+  *          performed in sFLASH_LowLevel_Init() function declared in stm3210b_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          sFLASH_LowLevel_Init() function.
+  *            
+  *          +-----------------------------------------------------------+
+  *          |                     Pin assignment                        |
+  *          +-----------------------------+---------------+-------------+
+  *          |  STM32 SPI Pins             |     sFLASH    |    Pin      |
+  *          +-----------------------------+---------------+-------------+
+  *          | sFLASH_CS_PIN               | ChipSelect(/S)|    1        |
+  *          | sFLASH_SPI_MISO_PIN / MISO  |   DataOut(Q)  |    2        |
+  *          |                             |   VCC         |    3 (3.3 V)|
+  *          |                             |   GND         |    4 (0 V)  |
+  *          | sFLASH_SPI_MOSI_PIN / MOSI  |   DataIn(D)   |    5        |
+  *          | sFLASH_SPI_SCK_PIN / SCLK   |   Clock(C)    |    6        |
+  *          |                             |    VCC        |    7 (3.3 V)|
+  *          |                             |    VCC        |    8 (3.3 V)|  
+  *          +-----------------------------+---------------+-------------+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval_spi_flash.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_SPI_FLASH
+  * @brief      This file includes the M25Pxxx SPI FLASH driver of STM3210B-EVAL board.
+  * @{
+  */  
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Defines
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_DeInit(void)
+{
+  sFLASH_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the peripherals used by the SPI FLASH driver.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_Init(void)
+{
+  SPI_InitTypeDef  SPI_InitStructure;
+
+  sFLASH_LowLevel_Init();
+    
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+
+  /*!< SPI configuration */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+#else
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
+#endif
+
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(sFLASH_SPI, &SPI_InitStructure);
+
+  /*!< Enable the sFLASH_SPI  */
+  SPI_Cmd(sFLASH_SPI, ENABLE);
+}
+
+/**
+  * @brief  Erases the specified FLASH sector.
+  * @param  SectorAddr: address of the sector to erase.
+  * @retval None
+  */
+void sFLASH_EraseSector(uint32_t SectorAddr)
+{
+  /*!< Send write enable instruction */
+  sFLASH_WriteEnable();
+
+  /*!< Sector Erase */
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+  /*!< Send Sector Erase instruction */
+  sFLASH_SendByte(sFLASH_CMD_SE);
+  /*!< Send SectorAddr high nibble address byte */
+  sFLASH_SendByte((SectorAddr & 0xFF0000) >> 16);
+  /*!< Send SectorAddr medium nibble address byte */
+  sFLASH_SendByte((SectorAddr & 0xFF00) >> 8);
+  /*!< Send SectorAddr low nibble address byte */
+  sFLASH_SendByte(SectorAddr & 0xFF);
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+
+  /*!< Wait the end of Flash writing */
+  sFLASH_WaitForWriteEnd();
+}
+
+/**
+  * @brief  Erases the entire FLASH.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_EraseBulk(void)
+{
+  /*!< Send write enable instruction */
+  sFLASH_WriteEnable();
+
+  /*!< Bulk Erase */
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+  /*!< Send Bulk Erase instruction  */
+  sFLASH_SendByte(sFLASH_CMD_BE);
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+
+  /*!< Wait the end of Flash writing */
+  sFLASH_WaitForWriteEnd();
+}
+
+/**
+  * @brief  Writes more than one byte to the FLASH with a single WRITE cycle 
+  *         (Page WRITE sequence).
+  * @note   The number of byte can't exceed the FLASH page size.
+  * @param  pBuffer: pointer to the buffer  containing the data to be written
+  *         to the FLASH.
+  * @param  WriteAddr: FLASH's internal address to write to.
+  * @param  NumByteToWrite: number of bytes to write to the FLASH, must be equal
+  *         or less than "sFLASH_PAGESIZE" value.
+  * @retval None
+  */
+void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
+{
+  /*!< Enable the write access to the FLASH */
+  sFLASH_WriteEnable();
+
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+  /*!< Send "Write to Memory " instruction */
+  sFLASH_SendByte(sFLASH_CMD_WRITE);
+  /*!< Send WriteAddr high nibble address byte to write to */
+  sFLASH_SendByte((WriteAddr & 0xFF0000) >> 16);
+  /*!< Send WriteAddr medium nibble address byte to write to */
+  sFLASH_SendByte((WriteAddr & 0xFF00) >> 8);
+  /*!< Send WriteAddr low nibble address byte to write to */
+  sFLASH_SendByte(WriteAddr & 0xFF);
+
+  /*!< while there is data to be written on the FLASH */
+  while (NumByteToWrite--)
+  {
+    /*!< Send the current byte */
+    sFLASH_SendByte(*pBuffer);
+    /*!< Point on the next byte to be written */
+    pBuffer++;
+  }
+
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+
+  /*!< Wait the end of Flash writing */
+  sFLASH_WaitForWriteEnd();
+}
+
+/**
+  * @brief  Writes block of data to the FLASH. In this function, the number of
+  *         WRITE cycles are reduced, using Page WRITE sequence.
+  * @param  pBuffer: pointer to the buffer  containing the data to be written
+  *         to the FLASH.
+  * @param  WriteAddr: FLASH's internal address to write to.
+  * @param  NumByteToWrite: number of bytes to write to the FLASH.
+  * @retval None
+  */
+void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
+{
+  uint8_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
+
+  Addr = WriteAddr % sFLASH_SPI_PAGESIZE;
+  count = sFLASH_SPI_PAGESIZE - Addr;
+  NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
+  NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
+
+  if (Addr == 0) /*!< WriteAddr is sFLASH_PAGESIZE aligned  */
+  {
+    if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
+    {
+      sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
+    }
+    else /*!< NumByteToWrite > sFLASH_PAGESIZE */
+    {
+      while (NumOfPage--)
+      {
+        sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
+        WriteAddr +=  sFLASH_SPI_PAGESIZE;
+        pBuffer += sFLASH_SPI_PAGESIZE;
+      }
+
+      sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
+    }
+  }
+  else /*!< WriteAddr is not sFLASH_PAGESIZE aligned  */
+  {
+    if (NumOfPage == 0) /*!< NumByteToWrite < sFLASH_PAGESIZE */
+    {
+      if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sFLASH_PAGESIZE */
+      {
+        temp = NumOfSingle - count;
+
+        sFLASH_WritePage(pBuffer, WriteAddr, count);
+        WriteAddr +=  count;
+        pBuffer += count;
+
+        sFLASH_WritePage(pBuffer, WriteAddr, temp);
+      }
+      else
+      {
+        sFLASH_WritePage(pBuffer, WriteAddr, NumByteToWrite);
+      }
+    }
+    else /*!< NumByteToWrite > sFLASH_PAGESIZE */
+    {
+      NumByteToWrite -= count;
+      NumOfPage =  NumByteToWrite / sFLASH_SPI_PAGESIZE;
+      NumOfSingle = NumByteToWrite % sFLASH_SPI_PAGESIZE;
+
+      sFLASH_WritePage(pBuffer, WriteAddr, count);
+      WriteAddr +=  count;
+      pBuffer += count;
+
+      while (NumOfPage--)
+      {
+        sFLASH_WritePage(pBuffer, WriteAddr, sFLASH_SPI_PAGESIZE);
+        WriteAddr +=  sFLASH_SPI_PAGESIZE;
+        pBuffer += sFLASH_SPI_PAGESIZE;
+      }
+
+      if (NumOfSingle != 0)
+      {
+        sFLASH_WritePage(pBuffer, WriteAddr, NumOfSingle);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Reads a block of data from the FLASH.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the FLASH.
+  * @param  ReadAddr: FLASH's internal address to read from.
+  * @param  NumByteToRead: number of bytes to read from the FLASH.
+  * @retval None
+  */
+void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead)
+{
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+
+  /*!< Send "Read from Memory " instruction */
+  sFLASH_SendByte(sFLASH_CMD_READ);
+
+  /*!< Send ReadAddr high nibble address byte to read from */
+  sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
+  /*!< Send ReadAddr medium nibble address byte to read from */
+  sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
+  /*!< Send ReadAddr low nibble address byte to read from */
+  sFLASH_SendByte(ReadAddr & 0xFF);
+
+  while (NumByteToRead--) /*!< while there is data to be read */
+  {
+    /*!< Read a byte from the FLASH */
+    *pBuffer = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
+    /*!< Point to the next location where the byte read will be saved */
+    pBuffer++;
+  }
+
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+}
+
+/**
+  * @brief  Reads FLASH identification.
+  * @param  None
+  * @retval FLASH identification
+  */
+uint32_t sFLASH_ReadID(void)
+{
+  uint32_t Temp = 0, Temp0 = 0, Temp1 = 0, Temp2 = 0;
+
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+
+  /*!< Send "RDID " instruction */
+  sFLASH_SendByte(0x9F);
+
+  /*!< Read a byte from the FLASH */
+  Temp0 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
+
+  /*!< Read a byte from the FLASH */
+  Temp1 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
+
+  /*!< Read a byte from the FLASH */
+  Temp2 = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
+
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+
+  Temp = (Temp0 << 16) | (Temp1 << 8) | Temp2;
+
+  return Temp;
+}
+
+/**
+  * @brief  Initiates a read data byte (READ) sequence from the Flash.
+  *   This is done by driving the /CS line low to select the device, then the READ
+  *   instruction is transmitted followed by 3 bytes address. This function exit
+  *   and keep the /CS line low, so the Flash still being selected. With this
+  *   technique the whole content of the Flash is read with a single READ instruction.
+  * @param  ReadAddr: FLASH's internal address to read from.
+  * @retval None
+  */
+void sFLASH_StartReadSequence(uint32_t ReadAddr)
+{
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+
+  /*!< Send "Read from Memory " instruction */
+  sFLASH_SendByte(sFLASH_CMD_READ);
+
+  /*!< Send the 24-bit address of the address to read from -------------------*/
+  /*!< Send ReadAddr high nibble address byte */
+  sFLASH_SendByte((ReadAddr & 0xFF0000) >> 16);
+  /*!< Send ReadAddr medium nibble address byte */
+  sFLASH_SendByte((ReadAddr& 0xFF00) >> 8);
+  /*!< Send ReadAddr low nibble address byte */
+  sFLASH_SendByte(ReadAddr & 0xFF);
+}
+
+/**
+  * @brief  Reads a byte from the SPI Flash.
+  * @note   This function must be used only if the Start_Read_Sequence function
+  *         has been previously called.
+  * @param  None
+  * @retval Byte Read from the SPI Flash.
+  */
+uint8_t sFLASH_ReadByte(void)
+{
+  return (sFLASH_SendByte(sFLASH_DUMMY_BYTE));
+}
+
+/**
+  * @brief  Sends a byte through the SPI interface and return the byte received
+  *         from the SPI bus.
+  * @param  byte: byte to send.
+  * @retval The value of the received byte.
+  */
+uint8_t sFLASH_SendByte(uint8_t byte)
+{
+  /*!< Loop while DR register in not emplty */
+  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
+
+  /*!< Send byte through the SPI1 peripheral */
+  SPI_I2S_SendData(sFLASH_SPI, byte);
+
+  /*!< Wait to receive a byte */
+  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
+
+  /*!< Return the byte read from the SPI bus */
+  return SPI_I2S_ReceiveData(sFLASH_SPI);
+}
+
+/**
+  * @brief  Sends a Half Word through the SPI interface and return the Half Word
+  *         received from the SPI bus.
+  * @param  HalfWord: Half Word to send.
+  * @retval The value of the received Half Word.
+  */
+uint16_t sFLASH_SendHalfWord(uint16_t HalfWord)
+{
+  /*!< Loop while DR register in not emplty */
+  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_TXE) == RESET);
+
+  /*!< Send Half Word through the sFLASH peripheral */
+  SPI_I2S_SendData(sFLASH_SPI, HalfWord);
+
+  /*!< Wait to receive a Half Word */
+  while (SPI_I2S_GetFlagStatus(sFLASH_SPI, SPI_I2S_FLAG_RXNE) == RESET);
+
+  /*!< Return the Half Word read from the SPI bus */
+  return SPI_I2S_ReceiveData(sFLASH_SPI);
+}
+
+/**
+  * @brief  Enables the write access to the FLASH.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_WriteEnable(void)
+{
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+
+  /*!< Send "Write Enable" instruction */
+  sFLASH_SendByte(sFLASH_CMD_WREN);
+
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+}
+
+/**
+  * @brief  Polls the status of the Write In Progress (WIP) flag in the FLASH's
+  *         status register and loop until write opertaion has completed.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_WaitForWriteEnd(void)
+{
+  uint8_t flashstatus = 0;
+
+  /*!< Select the FLASH: Chip Select low */
+  sFLASH_CS_LOW();
+
+  /*!< Send "Read Status Register" instruction */
+  sFLASH_SendByte(sFLASH_CMD_RDSR);
+
+  /*!< Loop as long as the memory is busy with a write cycle */
+  do
+  {
+    /*!< Send a dummy byte to generate the clock needed by the FLASH
+    and put the value of the status register in FLASH_Status variable */
+    flashstatus = sFLASH_SendByte(sFLASH_DUMMY_BYTE);
+
+  }
+  while ((flashstatus & sFLASH_WIP_FLAG) == SET); /* Write in progress */
+
+  /*!< Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.h
new file mode 100644
index 0000000..ef3a4cb
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_flash.h
@@ -0,0 +1,157 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_spi_flash.h
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210b_eval_spi_flash firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210B_EVAL_SPI_FLASH_H
+#define __STM3210B_EVAL_SPI_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_SPI_FLASH
+  * @{
+  */  
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Exported_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Exported_Constants
+  * @{
+  */
+/**
+  * @brief  M25P SPI Flash supported commands
+  */  
+#define sFLASH_CMD_WRITE          0x02  /*!< Write to Memory instruction */
+#define sFLASH_CMD_WRSR           0x01  /*!< Write Status Register instruction */
+#define sFLASH_CMD_WREN           0x06  /*!< Write enable instruction */
+#define sFLASH_CMD_READ           0x03  /*!< Read from Memory instruction */
+#define sFLASH_CMD_RDSR           0x05  /*!< Read Status Register instruction  */
+#define sFLASH_CMD_RDID           0x9F  /*!< Read identification */
+#define sFLASH_CMD_SE             0xD8  /*!< Sector Erase instruction */
+#define sFLASH_CMD_BE             0xC7  /*!< Bulk Erase instruction */
+
+#define sFLASH_WIP_FLAG           0x01  /*!< Write In Progress (WIP) flag */
+
+#define sFLASH_DUMMY_BYTE         0xA5
+#define sFLASH_SPI_PAGESIZE       0x100
+
+#define sFLASH_M25P128_ID         0x202018
+#define sFLASH_M25P64_ID          0x202017
+  
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Exported_Macros
+  * @{
+  */
+/**
+  * @brief  Select sFLASH: Chip Select pin low
+  */
+#define sFLASH_CS_LOW()       GPIO_ResetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)
+/**
+  * @brief  Deselect sFLASH: Chip Select pin high
+  */
+#define sFLASH_CS_HIGH()      GPIO_SetBits(sFLASH_CS_GPIO_PORT, sFLASH_CS_PIN)   
+/**
+  * @}
+  */ 
+  
+
+
+/** @defgroup STM3210B_EVAL_SPI_FLASH_Exported_Functions
+  * @{
+  */
+/**
+  * @brief  High layer functions
+  */
+void sFLASH_DeInit(void);
+void sFLASH_Init(void);
+void sFLASH_EraseSector(uint32_t SectorAddr);
+void sFLASH_EraseBulk(void);
+void sFLASH_WritePage(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
+void sFLASH_WriteBuffer(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
+void sFLASH_ReadBuffer(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t NumByteToRead);
+uint32_t sFLASH_ReadID(void);
+void sFLASH_StartReadSequence(uint32_t ReadAddr);
+
+/**
+  * @brief  Low layer functions
+  */
+uint8_t sFLASH_ReadByte(void);
+uint8_t sFLASH_SendByte(uint8_t byte);
+uint16_t sFLASH_SendHalfWord(uint16_t HalfWord);
+void sFLASH_WriteEnable(void);
+void sFLASH_WaitForWriteEnd(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210B_EVAL_SPI_FLASH_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c
new file mode 100644
index 0000000..a672b69
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.c
@@ -0,0 +1,911 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_spi_sd.c
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file provides a set of functions needed to manage the SPI SD 
+  *          Card memory mounted on STM3210B-EVAL board. 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32 hardware resources (SPI and 
+  *          GPIO) are defined in stm3210b_eval.h file, and the initialization is 
+  *          performed in SD_LowLevel_Init() function declared in stm3210b_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SD_LowLevel_Init() function.
+  *
+  *          ===================================================================
+  *          Note: 
+  *           - This driver doesn't support SD High Capacity cards.
+  *          ===================================================================
+  *
+  *          +-------------------------------------------------------+
+  *          |                     Pin assignment                    |
+  *          +-------------------------+---------------+-------------+
+  *          |  STM32 SPI Pins         |     SD        |    Pin      |
+  *          +-------------------------+---------------+-------------+
+  *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |
+  *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |
+  *          |                         |   GND         |    3 (0 V)  |
+  *          |                         |   VDD         |    4 (3.3 V)|
+  *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |
+  *          |                         |   GND         |    6 (0 V)  |
+  *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |
+  *          +-------------------------+---------------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval_spi_sd.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_SPI_SD
+  * @brief      This file includes the SD card driver of STM32-EVAL boards.
+  * @{
+  */ 
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Function_Prototypes
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the SD/SD communication.
+  * @param  None
+  * @retval None
+  */
+void SD_DeInit(void)
+{
+  SD_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the SD/SD communication.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_Init(void)
+{
+  uint32_t i = 0;
+
+  /*!< Initialize SD_SPI */
+  SD_LowLevel_Init(); 
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF, 10 times with CS high */
+  /*!< Rise CS and MOSI for 80 clocks cycles */
+  for (i = 0; i <= 9; i++)
+  {
+    /*!< Send dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+  }
+  /*------------Put SD in SPI mode--------------*/
+  /*!< SD initialized and set to SPI mode properly */
+  return (SD_GoIdleState());
+}
+
+/**
+ * @brief  Detect if SD card is correctly plugged in the memory slot.
+ * @param  None
+ * @retval Return if SD is detected or not
+ */
+uint8_t SD_Detect(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  /*!< Check GPIO to detect SD */
+  if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN)
+  {
+    status = SD_NOT_PRESENT;
+  }
+  return status;
+}
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD 
+  *         card information.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
+{
+  SD_Error status = SD_RESPONSE_FAILURE;
+
+  status = SD_GetCSDRegister(&(cardinfo->SD_csd));
+  status = SD_GetCIDRegister(&(cardinfo->SD_cid));
+  cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
+  cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
+  cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
+  cardinfo->CardCapacity *= cardinfo->CardBlockSize;
+
+  /*!< Returns the reponse */
+  return status;
+}
+
+/**
+  * @brief  Reads a block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+  SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Save the received data */
+        *pBuffer = SD_ReadByte();
+       
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Reads multiple block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be read.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+    SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return  SD_RESPONSE_FAILURE;
+    }
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Read the pointed data */
+        *pBuffer = SD_ReadByte();
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Set next read address*/
+      Offset += 512;
+      /*!< get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes a block on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */
+  SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Send a dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(0xFE);
+
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes many blocks on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be written.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */
+    SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return SD_RESPONSE_FAILURE;
+    }
+    /*!< Send dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE);
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Set next write address */
+    Offset += 512;
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CSD card register.
+  *         Reading the contents of the CSD register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_csd: pointer on an SCD register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CSD_Tab[16];
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Send CMD9 (CSD register) or CMD10(CSD register) */
+  SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF);
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      for (i = 0; i < 16; i++)
+      {
+        /*!< Store CSD register value on CSD_Tab */
+        CSD_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
+  SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
+  SD_csd->Reserved1 = CSD_Tab[0] & 0x03;
+
+  /*!< Byte 1 */
+  SD_csd->TAAC = CSD_Tab[1];
+
+  /*!< Byte 2 */
+  SD_csd->NSAC = CSD_Tab[2];
+
+  /*!< Byte 3 */
+  SD_csd->MaxBusClkFrec = CSD_Tab[3];
+
+  /*!< Byte 4 */
+  SD_csd->CardComdClasses = CSD_Tab[4] << 4;
+
+  /*!< Byte 5 */
+  SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
+  SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
+
+  /*!< Byte 6 */
+  SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
+  SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
+  SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
+  SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
+  SD_csd->Reserved2 = 0; /*!< Reserved */
+
+  SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
+
+  /*!< Byte 7 */
+  SD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
+
+  /*!< Byte 8 */
+  SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
+
+  SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
+  SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
+
+  /*!< Byte 9 */
+  SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
+  SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
+  SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
+  /*!< Byte 10 */
+  SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
+    
+  SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6;
+  SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1;
+
+  /*!< Byte 11 */
+  SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7;
+  SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F);
+
+  /*!< Byte 12 */
+  SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
+  SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
+  SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
+  SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
+
+  /*!< Byte 13 */
+  SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6;
+  SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
+  SD_csd->Reserved3 = 0;
+  SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
+
+  /*!< Byte 14 */
+  SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
+  SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
+  SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
+  SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
+  SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
+  SD_csd->ECC = (CSD_Tab[14] & 0x03);
+
+  /*!< Byte 15 */
+  SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1;
+  SD_csd->Reserved4 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CID card register.
+  *         Reading the contents of the CID register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_cid: pointer on an CID register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CID_Tab[16];
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD10 (CID register) */
+  SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF);
+  
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Store CID register value on CID_Tab */
+      for (i = 0; i < 16; i++)
+      {
+        CID_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_cid->ManufacturerID = CID_Tab[0];
+
+  /*!< Byte 1 */
+  SD_cid->OEM_AppliID = CID_Tab[1] << 8;
+
+  /*!< Byte 2 */
+  SD_cid->OEM_AppliID |= CID_Tab[2];
+
+  /*!< Byte 3 */
+  SD_cid->ProdName1 = CID_Tab[3] << 24;
+
+  /*!< Byte 4 */
+  SD_cid->ProdName1 |= CID_Tab[4] << 16;
+
+  /*!< Byte 5 */
+  SD_cid->ProdName1 |= CID_Tab[5] << 8;
+
+  /*!< Byte 6 */
+  SD_cid->ProdName1 |= CID_Tab[6];
+
+  /*!< Byte 7 */
+  SD_cid->ProdName2 = CID_Tab[7];
+
+  /*!< Byte 8 */
+  SD_cid->ProdRev = CID_Tab[8];
+
+  /*!< Byte 9 */
+  SD_cid->ProdSN = CID_Tab[9] << 24;
+
+  /*!< Byte 10 */
+  SD_cid->ProdSN |= CID_Tab[10] << 16;
+
+  /*!< Byte 11 */
+  SD_cid->ProdSN |= CID_Tab[11] << 8;
+
+  /*!< Byte 12 */
+  SD_cid->ProdSN |= CID_Tab[12];
+
+  /*!< Byte 13 */
+  SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
+  SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
+
+  /*!< Byte 14 */
+  SD_cid->ManufactDate |= CID_Tab[14];
+
+  /*!< Byte 15 */
+  SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;
+  SD_cid->Reserved2 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Send 5 bytes command to the SD card.
+  * @param  Cmd: The user expected command to send to SD card.
+  * @param  Arg: The command argument.
+  * @param  Crc: The CRC.
+  * @retval None
+  */
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
+{
+  uint32_t i = 0x00;
+  
+  uint8_t Frame[6];
+  
+  Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
+  
+  Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
+  
+  Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
+  
+  Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
+  
+  Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
+  
+  Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
+  
+  for (i = 0; i < 6; i++)
+  {
+    SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
+  }
+}
+
+/**
+  * @brief  Get SD card data response.
+  * @param  None
+  * @retval The SD status: Read data response xxx0<status>1
+  *         - status 010: Data accecpted
+  *         - status 101: Data rejected due to a crc error
+  *         - status 110: Data rejected due to a Write error.
+  *         - status 111: Data rejected due to other error.
+  */
+uint8_t SD_GetDataResponse(void)
+{
+  uint32_t i = 0;
+  uint8_t response, rvalue;
+
+  while (i <= 64)
+  {
+    /*!< Read resonse */
+    response = SD_ReadByte();
+    /*!< Mask unused bits */
+    response &= 0x1F;
+    switch (response)
+    {
+      case SD_DATA_OK:
+      {
+        rvalue = SD_DATA_OK;
+        break;
+      }
+      case SD_DATA_CRC_ERROR:
+        return SD_DATA_CRC_ERROR;
+      case SD_DATA_WRITE_ERROR:
+        return SD_DATA_WRITE_ERROR;
+      default:
+      {
+        rvalue = SD_DATA_OTHER_ERROR;
+        break;
+      }
+    }
+    /*!< Exit loop in case of data ok */
+    if (rvalue == SD_DATA_OK)
+      break;
+    /*!< Increment loop counter */
+    i++;
+  }
+
+  /*!< Wait null data */
+  while (SD_ReadByte() == 0);
+
+  /*!< Return response */
+  return response;
+}
+
+/**
+  * @brief  Returns the SD response.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetResponse(uint8_t Response)
+{
+  uint32_t Count = 0xFFF;
+
+  /*!< Check if response is got or a timeout is happen */
+  while ((SD_ReadByte() != Response) && Count)
+  {
+    Count--;
+  }
+  if (Count == 0)
+  {
+    /*!< After time out */
+    return SD_RESPONSE_FAILURE;
+  }
+  else
+  {
+    /*!< Right response got */
+    return SD_RESPONSE_NO_ERROR;
+  }
+}
+
+/**
+  * @brief  Returns the SD status.
+  * @param  None
+  * @retval The SD status.
+  */
+uint16_t SD_GetStatus(void)
+{
+  uint16_t Status = 0;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */
+  SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF);
+
+  Status = SD_ReadByte();
+  Status |= (uint16_t)(SD_ReadByte() << 8);
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  return Status;
+}
+
+/**
+  * @brief  Put SD in Idle state.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GoIdleState(void)
+{
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
+  SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
+  
+  /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
+  if (SD_GetResponse(SD_IN_IDLE_STATE))
+  {
+    /*!< No Idle State Response: return response failue */
+    return SD_RESPONSE_FAILURE;
+  }
+  /*----------Activates the card initialization process-----------*/
+  do
+  {
+    /*!< SD chip select high */
+    SD_CS_HIGH();
+    
+    /*!< Send Dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    
+    /*!< SD chip select low */
+    SD_CS_LOW();
+    
+    /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
+    SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
+    /*!< Wait for no error Response (R1 Format) equal to 0x00 */
+  }
+  while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
+  
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  return SD_RESPONSE_NO_ERROR;
+}
+
+/**
+  * @brief  Write a byte on the SD.
+  * @param  Data: byte to send.
+  * @retval None
+  */
+uint8_t SD_WriteByte(uint8_t Data)
+{
+  /*!< Wait until the transmit buffer is empty */
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  
+  /*!< Send the byte */
+  SPI_I2S_SendData(SD_SPI, Data);
+  
+  /*!< Wait to receive a byte*/
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  
+  /*!< Return the byte read from the SPI bus */ 
+  return (uint8_t)SPI_I2S_ReceiveData(SD_SPI);
+}
+
+/**
+  * @brief  Read a byte from the SD.
+  * @param  None
+  * @retval The received byte.
+  */
+uint8_t SD_ReadByte(void)
+{
+  uint8_t Data = 0;
+  
+  /*!< Wait until the transmit buffer is empty */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  /*!< Send the byte */
+  SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE);
+
+  /*!< Wait until a data is received */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  /*!< Get the received data */
+  Data = (uint8_t)SPI_I2S_ReceiveData(SD_SPI);
+
+  /*!< Return the shifted data */
+  return Data;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.h
new file mode 100644
index 0000000..3e9829b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210B_EVAL/stm3210b_eval_spi_sd.h
@@ -0,0 +1,286 @@
+/**
+  ******************************************************************************
+  * @file    stm3210b_eval_spi_sd.h
+  * @author  MCD Application Team
+  * @version V5.0.1
+  * @date    05-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210b_eval_spi_sd firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210B_EVAL_SPI_SD_H
+#define __STM3210B_EVAL_SPI_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210b_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210B_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210B_EVAL_SPI_SD
+  * @{
+  */  
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Exported_Types
+  * @{
+  */ 
+
+typedef enum
+{
+/**
+  * @brief  SD reponses and error flags
+  */
+  SD_RESPONSE_NO_ERROR      = (0x00),
+  SD_IN_IDLE_STATE          = (0x01),
+  SD_ERASE_RESET            = (0x02),
+  SD_ILLEGAL_COMMAND        = (0x04),
+  SD_COM_CRC_ERROR          = (0x08),
+  SD_ERASE_SEQUENCE_ERROR   = (0x10),
+  SD_ADDRESS_ERROR          = (0x20),
+  SD_PARAMETER_ERROR        = (0x40),
+  SD_RESPONSE_FAILURE       = (0xFF),
+
+/**
+  * @brief  Data response error
+  */
+  SD_DATA_OK                = (0x05),
+  SD_DATA_CRC_ERROR         = (0x0B),
+  SD_DATA_WRITE_ERROR       = (0x0D),
+  SD_DATA_OTHER_ERROR       = (0xFF)
+} SD_Error;
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210B_EVAL_SPI_SD_Exported_Constants
+  * @{
+  */ 
+    
+/**
+  * @brief  Block Size
+  */
+#define SD_BLOCK_SIZE    0x200
+
+/**
+  * @brief  Dummy byte
+  */
+#define SD_DUMMY_BYTE   0xFF
+
+/**
+  * @brief  Start Data tokens:
+  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is 
+  *         on the data/command line)  
+  */
+#define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
+#define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
+#define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
+#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
+#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT        ((uint8_t)0x01)
+#define SD_NOT_PRESENT    ((uint8_t)0x00)
+
+
+/**
+  * @brief  Commands: CMDxx = CMD-number | 0x40
+  */
+#define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
+#define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
+#define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
+#define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
+#define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
+#define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
+#define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
+#define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
+#define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
+#define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
+#define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
+#define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
+#define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
+#define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
+#define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
+#define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
+#define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
+#define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
+#define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
+#define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
+#define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
+#define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
+#define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210B_EVAL_SPI_SD_Exported_Macros
+  * @{
+  */
+/** 
+  * @brief  Select SD Card: ChipSelect pin low   
+  */  
+#define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/** 
+  * @brief  Deselect SD Card: ChipSelect pin high   
+  */ 
+#define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210B_EVAL_SPI_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);  
+SD_Error SD_Init(void);
+uint8_t SD_Detect(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
+
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
+SD_Error SD_GetResponse(uint8_t Response);
+uint8_t SD_GetDataResponse(void);
+SD_Error SD_GoIdleState(void);
+uint16_t SD_GetStatus(void);
+
+uint8_t SD_WriteByte(uint8_t byte);
+uint8_t SD_ReadByte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210B_EVAL_SPI_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */    
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
new file mode 100644
index 0000000..e7495f7
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.c
@@ -0,0 +1,677 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval.c
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file provides
+  *            - set of firmware functions to manage Leds, push-button and COM ports
+  *            - low level initialization functions for SD card (on SDIO), SPI serial
+  *              flash (sFLASH) and temperature sensor (LM75)
+  *          available on STM3210E-EVAL evaluation board from STMicroelectronics.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_dma.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */ 
+      
+/** @defgroup STM3210E_EVAL_LOW_LEVEL 
+  * @brief This file provides firmware functions to manage Leds, push-buttons, 
+  *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) 
+  *        and temperature sensor (LM75) available on STM3210E-EVAL evaluation 
+  *        board from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
+                                 LED4_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+                                 LED4_GPIO_CLK};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT, 
+                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
+
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN, 
+                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
+                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
+                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
+
+const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,
+                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
+
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
+                                            TAMPER_BUTTON_EXTI_LINE, 
+                                            KEY_BUTTON_EXTI_LINE,
+                                            RIGHT_BUTTON_EXTI_LINE,
+                                            LEFT_BUTTON_EXTI_LINE,
+                                            UP_BUTTON_EXTI_LINE,
+                                            DOWN_BUTTON_EXTI_LINE,
+                                            SEL_BUTTON_EXTI_LINE};
+
+const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,
+                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, 
+                                              KEY_BUTTON_EXTI_PORT_SOURCE,
+                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
+                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
+                                              UP_BUTTON_EXTI_PORT_SOURCE,
+                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
+                                              SEL_BUTTON_EXTI_PORT_SOURCE};
+								 
+const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,
+                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, 
+                                             KEY_BUTTON_EXTI_PIN_SOURCE,
+                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
+                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
+                                             UP_BUTTON_EXTI_PIN_SOURCE,
+                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
+                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
+
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn, 
+                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
+                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
+                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
+
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
+
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
+ 
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
+ 
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
+
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
+ 
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
+
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
+
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4
+  * @retval None
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Enable the GPIO_LED Clock */
+  RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];     
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];    
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button
+  *     @arg BUTTON_TAMPER: Tamper Push Button  
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button
+  * @param  Button_Mode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                     generation capability  
+  * @retval None
+  */
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* Enable the BUTTON Clock */
+  RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
+
+  /* Configure Button pin as input floating */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+
+  if (Button_Mode == BUTTON_MODE_EXTI)
+  {
+    /* Connect Button EXTI Line to Button GPIO Pin */
+    GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+
+    /* Configure Button EXTI line */
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+
+    if(Button != BUTTON_WAKEUP)
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+    }
+    else
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
+    }
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+    EXTI_Init(&EXTI_InitStructure);
+
+    /* Enable and set Button EXTI Interrupt to the lowest priority */
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+    NVIC_Init(&NVIC_InitStructure); 
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter can be one of following parameters:    
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button
+  *     @arg BUTTON_TAMPER: Tamper Push Button  
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    
+  * @retval The Button GPIO pin value.
+  */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+/**
+  * @brief  Configures COM port.
+  * @param  COM: Specifies the COM port to be configured.
+  *   This parameter can be one of following parameters:    
+  *     @arg COM1
+  *     @arg COM2  
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
+  *   contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_APB2PeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
+
+  /* Enable UART clock */
+  if (COM == COM1)
+  {
+    RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
+  }
+  else
+  {
+    RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+  }
+
+  /* Configure USART Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
+
+  /* Configure USART Rx as input floating */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
+
+  /* USART configuration */
+  USART_Init(COM_USART[COM], USART_InitStruct);
+    
+  /* Enable USART */
+  USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+  * @brief  DeInitializes the SDIO interface.
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /*!< Disable SDIO Clock */
+  SDIO_ClockCmd(DISABLE);
+  
+  /*!< Set Power State to OFF */
+  SDIO_SetPowerState(SDIO_PowerState_OFF);
+
+  /*!< DeInitializes the SDIO peripheral */
+  SDIO_DeInit();
+  
+  /*!< Disable the SDIO AHB Clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, DISABLE);
+
+  /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /*!< Configure PD.02 CMD line */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< GPIOC and GPIOD Periph clock enable */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);
+
+  /*!< Configure PC.08, PC.09, PC.10, PC.11, PC.12 pin: D0, D1, D2, D3, CLK pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /*!< Configure PD.02 CMD line */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+  
+  /*!< Enable the SDIO AHB Clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_SDIO, ENABLE);
+
+  /*!< Enable the DMA2 Clock */
+  RCC_AHBPeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE);
+}
+
+/**
+  * @brief  Configures the DMA2 Channel4 for SDIO Tx request.
+  * @param  BufferSRC: pointer to the source buffer
+  * @param  BufferSize: buffer size
+  * @retval None
+  */
+void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
+{
+
+  DMA_InitTypeDef DMA_InitStructure;
+
+  DMA_ClearFlag(SD_SDIO_DMA_FLAG_TC | SD_SDIO_DMA_FLAG_TE | SD_SDIO_DMA_FLAG_HT | SD_SDIO_DMA_FLAG_GL);
+
+  /*!< DMA2 Channel4 disable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, DISABLE);
+
+  /*!< SDIO DMA CHANNEL Config */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(SD_SDIO_DMA_CHANNEL, &DMA_InitStructure);
+
+  DMA_ITConfig(SD_SDIO_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+
+  /*!< SDIO DMA CHANNEL enable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, ENABLE);  
+}
+
+/**
+  * @brief  Configures the DMA2 Channel4 for SDIO Rx request.
+  * @param  BufferDST: pointer to the destination buffer
+  * @param  BufferSize: buffer size
+  * @retval None
+  */
+void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+
+  DMA_ClearFlag(SD_SDIO_DMA_FLAG_TC | SD_SDIO_DMA_FLAG_TE | SD_SDIO_DMA_FLAG_HT | SD_SDIO_DMA_FLAG_GL);
+
+  /*!< SDIO DMA CHANNEL disable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, DISABLE);
+
+  /*!< SDIO DMA CHANNEL Config */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(SD_SDIO_DMA_CHANNEL, &DMA_InitStructure);
+
+  DMA_ITConfig(SD_SDIO_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+
+  /*!< SDIO DMA CHANNEL enable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, ENABLE);  
+}
+
+/**
+  * @brief  Returns the DMA End Of Transfer Status.
+  * @param  None
+  * @retval DMA SDIO Channel Status.
+  */
+uint32_t SD_DMAEndOfTransferStatus(void)
+{
+  return (uint32_t)DMA_GetFlagStatus(DMA2_FLAG_TC4);
+}
+
+/**
+  * @brief  DeInitializes the peripherals used by the SPI FLASH driver.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /*!< Disable the sFLASH_SPI  */
+  SPI_Cmd(sFLASH_SPI, DISABLE);
+  
+  /*!< DeInitializes the sFLASH_SPI */
+  SPI_I2S_DeInit(sFLASH_SPI);
+  
+  /*!< sFLASH_SPI Periph clock disable */
+  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, DISABLE);
+  
+  /*!< Configure sFLASH_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sFLASH_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
+  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sFLASH_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
+  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
+  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the peripherals used by the SPI FLASH driver.
+  * @param  None
+  * @retval None
+  */
+void sFLASH_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /*!< sFLASH_SPI_CS_GPIO, sFLASH_SPI_MOSI_GPIO, sFLASH_SPI_MISO_GPIO 
+       and sFLASH_SPI_SCK_GPIO Periph clock enable */
+  RCC_APB2PeriphClockCmd(sFLASH_CS_GPIO_CLK | sFLASH_SPI_MOSI_GPIO_CLK | sFLASH_SPI_MISO_GPIO_CLK |
+                         sFLASH_SPI_SCK_GPIO_CLK, ENABLE);
+
+  /*!< sFLASH_SPI Periph clock enable */
+  RCC_APB2PeriphClockCmd(sFLASH_SPI_CLK, ENABLE);
+  
+  /*!< Configure sFLASH_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(sFLASH_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sFLASH_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MOSI_PIN;
+  GPIO_Init(sFLASH_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sFLASH_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_SPI_MISO_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
+  GPIO_Init(sFLASH_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+  
+  /*!< Configure sFLASH_CS_PIN pin: sFLASH Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sFLASH_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(sFLASH_CS_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< Disable LM75_I2C */
+  I2C_Cmd(LM75_I2C, DISABLE);
+  /*!< DeInitializes the LM75_I2C */
+  I2C_DeInit(LM75_I2C);
+  
+  /*!< LM75_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
+    
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the LM75_I2C..
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< LM75_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
+    
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
+  RCC_APB2PeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
+                         LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
+  
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure); 
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
index fc6bff2..1f9fbe0 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval.h
@@ -1,36 +1,43 @@
 /**
   ******************************************************************************
-  * @file    stm32100e_eval.h
+  * @file    stm3210e_eval.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains definitions for STM32100E_EVAL's Leds, push-buttons
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file contains definitions for STM3210E_EVAL's Leds, push-buttons
   *          COM ports, sFLASH (on SPI) and Temperature Sensor LM75 (on I2C)
   *          hardware resources.  
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
   */ 
   
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_H
-#define __STM32100E_EVAL_H
+#ifndef __STM3210E_EVAL_H
+#define __STM3210E_EVAL_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif 
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
+#include "stm32f10x.h"
+#include "stm32_eval_legacy.h"
 
 /** @addtogroup Utilities
   * @{
@@ -40,25 +47,74 @@
   * @{
   */  
   
-/** @addtogroup STM32100E_EVAL
+/** @addtogroup STM3210E_EVAL
   * @{
   */ 
 
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL
   * @{
   */ 
   
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Types
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Types
   * @{
   */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_WAKEUP = 0,
+  BUTTON_TAMPER = 1,
+  BUTTON_KEY = 2,
+  BUTTON_RIGHT = 3,
+  BUTTON_LEFT = 4,
+  BUTTON_UP = 5,
+  BUTTON_DOWN = 6,
+  BUTTON_SEL = 7
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;
 /**
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Constants
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Constants
   * @{
   */ 
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_LED
+/** 
+  * @brief  Define for STM3210E_EVAL board  
+  */ 
+#if !defined (USE_STM3210E_EVAL)
+ #define USE_STM3210E_EVAL
+#endif
+
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_LED
   * @{
   */
 #define LEDn                             4
@@ -83,7 +139,7 @@
   * @}
   */
   
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_BUTTON
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_BUTTON
   * @{
   */  
 #define BUTTONn                          8
@@ -151,13 +207,13 @@
 /**
  * @brief Joystick Down push-button
  */   
-#define DOWN_BUTTON_PIN                  GPIO_Pin_11
-#define DOWN_BUTTON_GPIO_PORT            GPIOG
-#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOG
-#define DOWN_BUTTON_EXTI_LINE            EXTI_Line11
-#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOG
-#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource11
-#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_3
+#define DOWN_BUTTON_GPIO_PORT            GPIOD
+#define DOWN_BUTTON_GPIO_CLK             RCC_APB2Periph_GPIOD
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line3
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     GPIO_PortSourceGPIOD
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      GPIO_PinSource3
+#define DOWN_BUTTON_EXTI_IRQn            EXTI3_IRQn  
 /**
  * @brief Joystick Sel push-button
  */  
@@ -172,7 +228,7 @@
   * @}
   */ 
 
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_COM
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_COM
   * @{
   */
 #define COMn                             2
@@ -207,81 +263,42 @@
   * @}
   */ 
 
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_SD_FLASH
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_SD_FLASH
   * @{
   */
 /**
-  * @brief  SD SPI Interface pins
-  */
-#define SD_SPI                           SPI2
-#define SD_SPI_CLK                       RCC_APB1Periph_SPI2
-#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PC.13 */
-#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
-#define SD_SPI_SCK_GPIO_CLK              RCC_APB2Periph_GPIOB
-#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PC.14 */
-#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
-#define SD_SPI_MISO_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
-#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
-#define SD_SPI_MOSI_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define SD_CS_PIN                        GPIO_Pin_6                  /* PG.06 */
-#define SD_CS_GPIO_PORT                  GPIOG                       /* GPIOG */
-#define SD_CS_GPIO_CLK                   RCC_APB2Periph_GPIOG
+  * @brief  SD FLASH SDIO Interface
+  */ 
+
 #define SD_DETECT_PIN                    GPIO_Pin_11                 /* PF.11 */
 #define SD_DETECT_GPIO_PORT              GPIOF                       /* GPIOF */
 #define SD_DETECT_GPIO_CLK               RCC_APB2Periph_GPIOF
 
-/**
-  * @}
+#define SDIO_FIFO_ADDRESS                ((uint32_t)0x40018080)
+/** 
+  * @brief  SDIO Intialization Frequency (400KHz max)
   */
-
-/** @addtogroup STM3210C_EVAL_LOW_LEVEL_I2C_EE
-  * @{
+#define SDIO_INIT_CLK_DIV                ((uint8_t)0xB2)
+/** 
+  * @brief  SDIO Data Transfer Frequency (25MHz max) 
   */
-/**
-  * @brief  I2C EEPROM Interface pins
-  */  
-#define sEE_I2C                          I2C2
-#define sEE_I2C_CLK                      RCC_APB1Periph_I2C2
-#define sEE_I2C_SCL_PIN                  GPIO_Pin_10                 /* PB.10 */
-#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SCL_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_I2C_SDA_PIN                  GPIO_Pin_11                  /* PB.11 */
-#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
-#define sEE_I2C_SDA_GPIO_CLK             RCC_APB2Periph_GPIOB
-#define sEE_M24C64_32
-
-#define sEE_I2C_DMA                      DMA1   
-#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel4
-#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel5 
-#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC4   
-#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL4 
-#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC5 
-#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL5    
-#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
-#define sEE_I2C_DR_Address               ((uint32_t)0x40005810)
-#define sEE_USE_DMA
-   
-#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel4_IRQn
-#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel5_IRQn
-#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel4_IRQHandler
-#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel5_IRQHandler  
-#define sEE_I2C_DMA_PREPRIO              0
-#define sEE_I2C_DMA_SUBPRIO              0
- 
-#define sEE_DIRECTION_TX                 0
-#define sEE_DIRECTION_RX                 1 
-
-/* Time constant for the delay caclulation allowing to have a millisecond 
-   incrementing counter. This value should be equal to (System Clock / 1000).
-   ie. if system clock = 24MHz then sEE_TIME_CONST should be 24. */
-#define sEE_TIME_CONST          24 
+#define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x01)
+
+#define SD_SDIO_DMA                      DMA2
+#define SD_SDIO_DMA_CLK                  RCC_AHBPeriph_DMA2
+#define SD_SDIO_DMA_CHANNEL              DMA2_Channel4
+#define SD_SDIO_DMA_FLAG_TC              DMA2_FLAG_TC4
+#define SD_SDIO_DMA_FLAG_TE              DMA2_FLAG_TE4
+#define SD_SDIO_DMA_FLAG_HT              DMA2_FLAG_HT4
+#define SD_SDIO_DMA_FLAG_GL              DMA2_FLAG_GL4
+#define SD_SDIO_DMA_IRQn                 DMA2_Channel4_5_IRQn
+#define SD_SDIO_DMA_IRQHANDLER           DMA2_Channel4_5_IRQHandler
 
 /**
   * @}
   */ 
   
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_M25P_FLASH_SPI
   * @{
   */
 /**
@@ -298,40 +315,38 @@
 #define sFLASH_SPI_MOSI_PIN              GPIO_Pin_7                  /* PA.07 */
 #define sFLASH_SPI_MOSI_GPIO_PORT        GPIOA                       /* GPIOA */
 #define sFLASH_SPI_MOSI_GPIO_CLK         RCC_APB2Periph_GPIOA
-#define sFLASH_CS_PIN                    GPIO_Pin_6                  /* PE.06 */
-#define sFLASH_CS_GPIO_PORT              GPIOE                       /* GPIOE */
-#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOE
+#define sFLASH_CS_PIN                    GPIO_Pin_2                  /* PB.02 */
+#define sFLASH_CS_GPIO_PORT              GPIOB                       /* GPIOB */
+#define sFLASH_CS_GPIO_CLK               RCC_APB2Periph_GPIOB
 
 /**
   * @}
   */
 
-
-/** @addtogroup STM32100E_EVAL_LOW_LEVEL_TSENSOR_I2C
+/** @addtogroup STM3210E_EVAL_LOW_LEVEL_TSENSOR_I2C
   * @{
   */
 /**
   * @brief  LM75 Temperature Sensor I2C Interface pins
   */  
-#define LM75_I2C                         I2C2
-#define LM75_I2C_CLK                     RCC_APB1Periph_I2C2
-#define LM75_I2C_SCL_PIN                 GPIO_Pin_10                 /* PB.10 */
+#define LM75_I2C                         I2C1
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
 #define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
 #define LM75_I2C_SCL_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SDA_PIN                 GPIO_Pin_11                 /* PB.11 */
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
 #define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
 #define LM75_I2C_SDA_GPIO_CLK            RCC_APB2Periph_GPIOB
-#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_12                 /* PB.12 */
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
 #define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
 #define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_APB2Periph_GPIOB
-#define LM75_I2C_DR                      ((uint32_t)0x40005810)
+#define LM75_I2C_DR                      ((uint32_t)0x40005410)
 
 #define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
-#define LM75_DMA_TX_CHANNEL              DMA1_Channel4
-#define LM75_DMA_RX_CHANNEL              DMA1_Channel5
-#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC4
-#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC5   
-   
+#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
+#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
+#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
 /**
   * @}
   */
@@ -340,14 +355,14 @@
   * @}
   */
   
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Macros
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Macros
   * @{
   */ 
 /**
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LOW_LEVEL_Exported_Functions
+/** @defgroup STM3210E_EVAL_LOW_LEVEL_Exported_Functions
   * @{
   */ 
 void STM_EVAL_LEDInit(Led_TypeDef Led);
@@ -359,9 +374,8 @@ uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
 void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
 void SD_LowLevel_DeInit(void);
 void SD_LowLevel_Init(void); 
-void sEE_LowLevel_DeInit(void);
-void sEE_LowLevel_Init(void);
-void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction); 
+void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
+void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
 void sFLASH_LowLevel_DeInit(void);
 void sFLASH_LowLevel_Init(void); 
 void LM75_LowLevel_DeInit(void);
@@ -373,7 +387,7 @@ void LM75_LowLevel_Init(void);
 }
 #endif
   
-#endif /* __STM32100E_EVAL_H */
+#endif /* __STM3210E_EVAL_H */
 /**
   * @}
   */ 
@@ -390,4 +404,4 @@ void LM75_LowLevel_Init(void);
   * @}
   */
   
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
new file mode 100644
index 0000000..8d19219
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.c
@@ -0,0 +1,552 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_nand.c
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file provides a set of functions needed to drive the
+  *          NAND512W3A2 memory mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval_fsmc_nand.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_NAND
+  * @brief      This file provides a set of functions needed to drive the
+  *             NAND512W3A2 memory mounted on STM3210E-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Defines
+  * @{
+  */ 
+/** 
+  * @brief  FSMC Bank 2 
+  */
+#define FSMC_Bank_NAND     FSMC_Bank2_NAND
+#define Bank_NAND_ADDR     Bank2_NAND_ADDR 
+#define Bank2_NAND_ADDR    ((uint32_t)0x70000000)     
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Macros
+  * @{
+  */
+#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)  
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the NAND memory.
+  *         This function must be called before any write/read operation on the 
+  *         NAND.
+  * @param  None
+  * @retval None
+  */
+void NAND_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure; 
+  FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
+  FSMC_NAND_PCCARDTimingInitTypeDef  p;
+  
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+  
+/*-- GPIO Configuration ------------------------------------------------------*/
+/*!< CLE, ALE, D0->D3, NOE, NWE and NCE2  NAND pin configuration  */
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |  
+                                 GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | 
+                                 GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/*!< D4->D7 NAND pin configuration  */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+
+/*!< NWAIT NAND pin configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+
+  GPIO_Init(GPIOD, &GPIO_InitStructure); 
+
+/*!< INT2 NAND pin configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  /*-- FSMC Configuration ------------------------------------------------------*/
+  p.FSMC_SetupTime = 0x0;
+  p.FSMC_WaitSetupTime = 0x2;
+  p.FSMC_HoldSetupTime = 0x1;
+  p.FSMC_HiZSetupTime = 0x0;
+
+  FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
+  FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
+  FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
+  FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
+  FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
+  FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
+
+  FSMC_NANDInit(&FSMC_NANDInitStructure);
+
+  /*!< FSMC NAND Bank Cmd Test */
+  FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
+}
+
+/**
+  * @brief  Reads NAND memory's ID.
+  * @param  NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
+  *         the Manufacturer and Device ID.  
+  * @retval None
+  */
+void NAND_ReadID(NAND_IDTypeDef* NAND_ID)
+{
+  uint32_t data = 0;
+
+  /*!< Send Command to the command area */
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+
+   /*!< Sequence to read ID from NAND flash */
+   data = *(__IO uint32_t *)(Bank_NAND_ADDR | DATA_AREA);
+
+   NAND_ID->Maker_ID   = ADDR_1st_CYCLE (data);
+   NAND_ID->Device_ID  = ADDR_2nd_CYCLE (data);
+   NAND_ID->Third_ID   = ADDR_3rd_CYCLE (data);
+   NAND_ID->Fourth_ID  = ADDR_4th_CYCLE (data);
+}
+
+/**
+  * @brief  This routine is for writing one or several 512 Bytes Page size.
+  * @param  pBuffer: pointer on the Buffer containing data to be written 
+  * @param  Address: First page address
+  * @param  NumPageToWrite: Number of page to write  
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation 
+  *                And the new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address  
+  */
+uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite)
+{
+  uint32_t index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /*!< Page write command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+    /*!< Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
+
+    /*!< Write data */
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /*!< Check status for successful operation */
+    status = NAND_GetStatus();
+    
+    if(status == NAND_READY)
+    {
+      numpagewritten++;
+
+      NumPageToWrite--;
+
+      /*!< Calculate Next small page Address */
+      addressstatus = NAND_AddressIncrement(&Address);
+    }
+  }
+  
+  return (status | addressstatus);
+}
+
+/**
+  * @brief  This routine is for sequential read from one or several 512 Bytes Page size.
+  * @param  pBuffer: pointer on the Buffer to fill
+  * @param  Address: First page address
+  * @param  NumPageToRead: Number of page to read  
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation 
+  *                And the new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t NAND_ReadSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead)
+{
+  uint32_t index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {
+    /*!< Page Read command and page address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+   
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+    
+    /*!< Calculate the size */
+    size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
+    
+    /*!< Get Data into Buffer */    
+    for(; index < size; index++)
+    {
+      pBuffer[index]= *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+
+    numpageread++;
+    
+    NumPageToRead--;
+
+    /*!< Calculate page address */
+    addressstatus = NAND_AddressIncrement(&Address);
+  }
+
+  status = NAND_GetStatus();
+  
+  return (status | addressstatus);
+}
+
+/**
+  * @brief  This routine write the spare area information for the specified
+  *         pages addresses.  
+  * @param  pBuffer: pointer on the Buffer containing data to be written 
+  * @param  Address: First page address
+  * @param  NumSpareAreaTowrite: Number of Spare Area to write
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation 
+  *                And the new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00; 
+
+  while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+  {
+    /*!< Page write Spare area command and address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+    /*!< Calculate the size */ 
+    size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
+
+    /*!< Write the data */ 
+    for(; index < size; index++)
+    {
+      *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+    }
+    
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+    /*!< Check status for successful operation */
+    status = NAND_GetStatus();
+
+    if(status == NAND_READY)
+    {
+      numsparesreawritten++;
+
+      NumSpareAreaTowrite--;
+    
+      /*!< Calculate Next page Address */
+      addressstatus = NAND_AddressIncrement(&Address);
+    }
+  }
+  
+  return (status | addressstatus);
+}
+
+/**
+  * @brief  This routine read the spare area information from the specified
+  *         pages addresses.  
+  * @param  pBuffer: pointer on the Buffer to fill 
+  * @param  Address: First page address
+  * @param  NumSpareAreaToRead: Number of Spare Area to read
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation 
+  *                And the new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address
+  */
+uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead)
+{
+  uint32_t numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
+  uint32_t status = NAND_READY, size = 0x00;
+
+  while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+  {     
+    /*!< Page Read command and page address */
+    *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00; 
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+    *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+    /*!< Data Read */
+    size = NAND_SPARE_AREA_SIZE +  (NAND_SPARE_AREA_SIZE * numsparearearead);
+
+    /*!< Get Data into Buffer */
+    for ( ;index < size; index++)
+    {
+      pBuffer[index] = *(__IO uint8_t *)(Bank_NAND_ADDR | DATA_AREA);
+    }
+    
+    numsparearearead++;
+    
+    NumSpareAreaToRead--;
+
+    /*!< Calculate page address */
+    addressstatus = NAND_AddressIncrement(&Address);
+  }
+
+  status = NAND_GetStatus();
+
+  return (status | addressstatus);
+}
+
+/**
+  * @brief  This routine erase complete block from NAND FLASH
+  * @param  Address: Any address into block to be erased
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate 
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation 
+  */
+uint32_t NAND_EraseBlock(NAND_ADDRESS Address)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
+
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+  *(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1; 
+
+  return (NAND_GetStatus());
+}
+
+/**
+  * @brief  This routine reset the NAND FLASH.
+  * @param  None
+  * @retval NAND_READY
+  */
+uint32_t NAND_Reset(void)
+{
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
+
+  return (NAND_READY);
+}
+
+/**
+  * @brief  Get the NAND operation status.
+  * @param  None
+  * @retval New status of the NAND operation. This parameter can be:
+  *              - NAND_TIMEOUT_ERROR: when the previous operation generate
+  *                a Timeout error
+  *              - NAND_READY: when memory is ready for the next operation
+  */
+uint32_t NAND_GetStatus(void)
+{
+  uint32_t timeout = 0x1000000, status = NAND_READY;
+
+  status = NAND_ReadStatus();
+
+  /*!< Wait for a NAND operation to complete or a TIMEOUT to occur */
+  while ((status != NAND_READY) &&( timeout != 0x00))
+  {
+     status = NAND_ReadStatus();
+     timeout --;
+  }
+
+  if(timeout == 0x00)
+  {
+    status =  NAND_TIMEOUT_ERROR;
+  }
+
+  /*!< Return the operation status */
+  return (status);
+}
+  
+/**
+  * @brief  Reads the NAND memory status using the Read status command. 
+  * @param  None
+  * @retval The status of the NAND memory. This parameter can be:
+  *              - NAND_BUSY: when memory is busy
+  *              - NAND_READY: when memory is ready for the next operation
+  *              - NAND_ERROR: when the previous operation gererates error
+  */
+uint32_t NAND_ReadStatus(void)
+{
+  uint32_t data = 0x00, status = NAND_BUSY;
+
+  /*!< Read status operation ------------------------------------ */
+  *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
+  data = *(__IO uint8_t *)(Bank_NAND_ADDR);
+
+  if((data & NAND_ERROR) == NAND_ERROR)
+  {
+    status = NAND_ERROR;
+  } 
+  else if((data & NAND_READY) == NAND_READY)
+  {
+    status = NAND_READY;
+  }
+  else
+  {
+    status = NAND_BUSY; 
+  }
+  
+  return (status);
+}
+
+/**
+  * @brief  Increment the NAND memory address. 
+  * @param  Address: address to be incremented.
+  * @retval The new status of the increment address operation. It can be:
+  *              - NAND_VALID_ADDRESS: When the new address is valid address
+  *              - NAND_INVALID_ADDRESS: When the new address is invalid address   
+  */
+uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address)
+{
+  uint32_t status = NAND_VALID_ADDRESS;
+ 
+  Address->Page++;
+
+  if(Address->Page == NAND_BLOCK_SIZE)
+  {
+    Address->Page = 0;
+    Address->Block++;
+    
+    if(Address->Block == NAND_ZONE_SIZE)
+    {
+      Address->Block = 0;
+      Address->Zone++;
+
+      if(Address->Zone == NAND_MAX_ZONE)
+      {
+        status = NAND_INVALID_ADDRESS;
+      }
+    }
+  } 
+  
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h
new file mode 100644
index 0000000..4c6cdf9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nand.h
@@ -0,0 +1,183 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_nand.h
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210e_eval_fsmc_nand firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+   
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210E_EVAL_FSMC_NAND_H
+#define __STM3210E_EVAL_FSMC_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_NAND
+  * @{
+  */  
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Types
+  * @{
+  */
+typedef struct
+{
+  uint8_t Maker_ID;
+  uint8_t Device_ID;
+  uint8_t Third_ID;
+  uint8_t Fourth_ID;
+}NAND_IDTypeDef;
+
+typedef struct 
+{
+  uint16_t Zone;
+  uint16_t Block;
+  uint16_t Page;
+} NAND_ADDRESS;  
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Constants
+  * @{
+  */
+/** 
+  * @brief  NAND Area definition  for STM3210E-EVAL Board RevD  
+  */  
+#define CMD_AREA                   (uint32_t)(1<<16)  /* A16 = CLE  high */
+#define ADDR_AREA                  (uint32_t)(1<<17)  /* A17 = ALE high */
+
+#define DATA_AREA                  ((uint32_t)0x00000000) 
+
+/** 
+  * @brief  FSMC NAND memory command  
+  */  
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)
+
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/** 
+  * @brief  NAND memory status  
+  */  
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
+#define NAND_BUSY                  ((uint32_t)0x00000000)
+#define NAND_ERROR                 ((uint32_t)0x00000001)
+#define NAND_READY                 ((uint32_t)0x00000040)
+
+/** 
+  * @brief  FSMC NAND memory parameters  
+  */  
+#define NAND_PAGE_SIZE             ((uint16_t)0x0200) /* 512 bytes per page w/o Spare Area */
+#define NAND_BLOCK_SIZE            ((uint16_t)0x0020) /* 32x512 bytes pages per block */
+#define NAND_ZONE_SIZE             ((uint16_t)0x0400) /* 1024 Block per zone */
+#define NAND_SPARE_AREA_SIZE       ((uint16_t)0x0010) /* last 16 bytes as spare area */
+#define NAND_MAX_ZONE              ((uint16_t)0x0004) /* 4 zones of 1024 block */
+
+/** 
+  * @brief  FSMC NAND memory address computation  
+  */  
+#define ADDR_1st_CYCLE(ADDR)       (uint8_t)((ADDR)& 0xFF)               /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF00) >> 8)      /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(ADDR)       (uint8_t)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */   
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NAND_Exported_Functions
+  * @{
+  */ 
+void NAND_Init(void);
+void NAND_ReadID(NAND_IDTypeDef* NAND_ID);
+uint32_t NAND_WriteSmallPage(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToWrite);
+uint32_t NAND_ReadSmallPage (uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumPageToRead);
+uint32_t NAND_WriteSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaTowrite);
+uint32_t NAND_ReadSpareArea(uint8_t *pBuffer, NAND_ADDRESS Address, uint32_t NumSpareAreaToRead);
+uint32_t NAND_EraseBlock(NAND_ADDRESS Address);
+uint32_t NAND_Reset(void);
+uint32_t NAND_GetStatus(void);
+uint32_t NAND_ReadStatus(void);
+uint32_t NAND_AddressIncrement(NAND_ADDRESS* Address);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210E_EVAL_FSMC_NAND_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
new file mode 100644
index 0000000..45a788a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.c
@@ -0,0 +1,484 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_nor.c
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file provides a set of functions needed to drive the M29W128FL, 
+  *          M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval_fsmc_nor.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_NOR
+  * @brief      This file provides a set of functions needed to drive the M29W128FL, 
+  *             M29W128GL and S29GL128P NOR memories mounted on STM3210E-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Defines
+  * @{
+  */ 
+/** 
+  * @brief  FSMC Bank 1 NOR/SRAM2  
+  */
+#define Bank1_NOR2_ADDR       ((uint32_t)0x64000000)
+
+/* Delay definition */   
+#define BlockErase_Timeout    ((uint32_t)0x00A00000)
+#define ChipErase_Timeout     ((uint32_t)0x30000000) 
+#define Program_Timeout       ((uint32_t)0x00001400)     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Macros
+  * @{
+  */
+#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
+#define NOR_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))  
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroupSTM3210E_EVAL_FSMC_NOR_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the NOR memory.
+  *         This function must be called before any write/read operation
+  *         on the NOR.
+  * @param  None
+  * @retval None
+  */
+void NOR_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | 
+                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+
+  /*-- GPIO Configuration ------------------------------------------------------*/
+  /*!< NOR Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  /*!< NOR Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
+                                GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  /*!< NOE and NWE configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /*!< NE2 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+  /*!< Configure PD6 for NOR memory Ready/Busy signal */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  
+  /*-- FSMC Configuration ----------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0x02;
+  p.FSMC_AddressHoldTime = 0x00;
+  p.FSMC_DataSetupTime = 0x05;
+  p.FSMC_BusTurnAroundDuration = 0x00;
+  p.FSMC_CLKDivision = 0x00;
+  p.FSMC_DataLatency = 0x00;
+  p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+  /*!< Enable FSMC Bank1_NOR Bank */
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
+}
+
+/**
+  * @brief  Reads NOR memory's Manufacturer and Device Code.
+  * @param  NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the 
+  *         Manufacturer and Device Code.  
+  * @retval None
+  */
+void NOR_ReadID(NOR_IDTypeDef* NOR_ID)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
+
+  NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
+  NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
+  NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
+  NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
+}
+
+/**
+  * @brief  Erases the specified Nor memory block.
+  * @param  BlockAddr: address of the block to erase.
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_EraseBlock(uint32_t BlockAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
+
+  return (NOR_GetStatus(BlockErase_Timeout));
+}
+
+/**
+  * @brief  Erases the entire chip.
+  * @param  None                      
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_EraseChip(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
+
+  return (NOR_GetStatus(ChipErase_Timeout));
+}
+
+/**
+  * @brief  Writes a half-word to the NOR memory.
+  * @param  WriteAddr: NOR memory internal address to write to.
+  * @param  Data: Data to write. 
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
+  NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
+
+  return (NOR_GetStatus(Program_Timeout));
+}
+
+/**
+  * @brief  Writes a half-word buffer to the FSMC NOR memory. 
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: NOR memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of Half words to write. 
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  NOR_Status status = NOR_ONGOING; 
+
+  do
+  {
+    /*!< Transfer data to the memory */
+    status = NOR_WriteHalfWord(WriteAddr, *pBuffer++);
+    WriteAddr = WriteAddr + 2;
+    NumHalfwordToWrite--;
+  }
+  while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
+  
+  return (status); 
+}
+
+/**
+  * @brief  Writes a half-word buffer to the FSMC NOR memory.
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: NOR memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of Half words to write.
+  *         The maximum allowed value is 32 Half words (64 bytes).
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  uint32_t lastloadedaddress = 0x00;
+  uint32_t currentaddress = 0x00;
+  uint32_t endaddress = 0x00;
+
+  /*!< Initialize variables */
+  currentaddress = WriteAddr;
+  endaddress = WriteAddr + NumHalfwordToWrite - 1;
+  lastloadedaddress = WriteAddr;
+
+  /*!< Issue unlock command sequence */
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);  
+
+  /*!< Write Write Buffer Load Command */
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
+
+  /*!< Load Data into NOR Buffer */
+  while(currentaddress <= endaddress)
+  {
+    /*!< Store last loaded address & data value (for polling) */
+    lastloadedaddress = currentaddress;
+ 
+    NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
+    currentaddress += 1; 
+  }
+
+  NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
+  
+  return(NOR_GetStatus(Program_Timeout));
+}
+
+/**
+  * @brief  Reads a half-word from the NOR memory. 
+  * @param  ReadAddr: NOR memory internal address to read from.
+  * @retval Half-word read from the NOR memory
+  */
+uint16_t NOR_ReadHalfWord(uint32_t ReadAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);  
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
+
+  return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
+}
+
+/**
+  * @brief  Reads a block of data from the FSMC NOR memory.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         NOR memory.
+  * @param  ReadAddr: NOR memory internal address to read from.
+  * @param  NumHalfwordToRead : number of Half word to read.
+  * @retval None
+  */
+void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
+
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */
+  {
+    /*!< Read a Halfword from the NOR */
+    *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
+    ReadAddr = ReadAddr + 2; 
+  }  
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode.
+  * @param  None
+  * @retval NOR_SUCCESS
+  */
+NOR_Status NOR_ReturnToReadMode(void)
+{
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
+
+  return (NOR_SUCCESS);
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode and resets the errors in the NOR 
+  *         memory Status Register.  
+  * @param  None
+  * @retval NOR_SUCCESS
+  */
+NOR_Status NOR_Reset(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); 
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); 
+
+  return (NOR_SUCCESS);
+}
+
+/**
+  * @brief  Returns the NOR operation status.
+  * @param  Timeout: NOR progamming Timeout
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_GetStatus(uint32_t Timeout)
+{ 
+  uint16_t val1 = 0x00, val2 = 0x00;
+  NOR_Status status = NOR_ONGOING; 
+  uint32_t timeout = Timeout;
+
+  /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) 
+  {
+    timeout--;
+  }
+
+  timeout = Timeout;
+  
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))   
+  {
+    timeout--;
+  }
+  
+  /*!< Get the NOR memory operation status -----------------------------------*/
+  while((Timeout != 0x00) && (status != NOR_SUCCESS))
+  {
+    Timeout--;
+
+    /*!< Read DQ6 and DQ5 */
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+
+    /*!< If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+
+    if((val1 & 0x0020) != 0x0020)
+    {
+      status = NOR_ONGOING;
+    }
+
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+    else if((val1 & 0x0020) == 0x0020)
+    {
+      return NOR_ERROR;
+    }
+  }
+
+  if(Timeout == 0x00)
+  {
+    status = NOR_TIMEOUT;
+  } 
+
+  /*!< Return the operation status */
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
new file mode 100644
index 0000000..707e5e3
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_fsmc_nor.h
@@ -0,0 +1,134 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_fsmc_nor.h
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm3210e_eval_fsmc_nor firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210E_EVAL_FSMC_NOR_H
+#define __STM3210E_EVAL_FSMC_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_FSMC_NOR
+  * @{
+  */  
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Types
+  * @{
+  */
+typedef struct
+{
+  uint16_t Manufacturer_Code;
+  uint16_t Device_Code1;
+  uint16_t Device_Code2;
+  uint16_t Device_Code3;
+}NOR_IDTypeDef;
+
+/* NOR Status */
+typedef enum
+{
+  NOR_SUCCESS = 0,
+  NOR_ONGOING,
+  NOR_ERROR,
+  NOR_TIMEOUT
+}NOR_Status;  
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Constants
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_FSMC_NOR_Exported_Functions
+  * @{
+  */ 
+void NOR_Init(void);
+void NOR_ReadID(NOR_IDTypeDef* NOR_ID);
+NOR_Status NOR_EraseBlock(uint32_t BlockAddr);
+NOR_Status NOR_EraseChip(void);
+NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data);
+NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
+NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite);
+uint16_t NOR_ReadHalfWord(uint32_t ReadAddr);
+void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead);
+NOR_Status NOR_ReturnToReadMode(void);
+NOR_Status NOR_Reset(void);
+NOR_Status NOR_GetStatus(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210E_EVAL_FSMC_NOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c
new file mode 100644
index 0000000..1e1de17
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.c
@@ -0,0 +1,2816 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_sdio_sd.c
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file provides a set of functions needed to manage the SDIO SD 
+  *          Card memory mounted on STM3210E-EVAL evaluation board. 
+  *          
+  *            
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                   How to use this driver
+  *          ===================================================================
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32 hardware resources (SDIO and 
+  *          GPIO) are defined in stm3210e_eval.h file, and the initialization is 
+  *          performed in SD_LowLevel_Init() function declared in stm3210e_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SD_LowLevel_Init() function.
+  *
+  *          A - SD Card Initialization and configuration
+  *          ============================================    
+  *            - To initialize the SD Card, use the SD_Init() function.  It 
+  *              Initializes the SD Card and put it into StandBy State (Ready 
+  *              for data transfer). This function provide the following operations:
+  *
+  *              1 - Apply the SD Card initialization process at 400KHz and check
+  *                  the SD Card type (Standard Capacity or High Capacity). You 
+  *                  can change or adapt this frequency by adjusting the 
+  *                  "SDIO_INIT_CLK_DIV" define inside the stm3210e_eval.h file. 
+  *                  The SD Card frequency (SDIO_CK) is computed as follows:
+  *
+  *                     +---------------------------------------------+
+  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
+  *                     +---------------------------------------------+
+  *
+  *                  In initialization mode and according to the SD Card standard, 
+  *                  make sure that the SDIO_CK frequency don't exceed 400KHz.
+  *
+  *              2 - Get the SD CID and CSD data. All these information are
+  *                  managed by the SDCardInfo structure. This structure provide
+  *                  also ready computed SD Card capacity and Block size.   
+  *
+  *              3 - Configure the SD Card Data transfer frequency. By Default,
+  *                  the card transfer frequency is set to 24MHz. You can change
+  *                  or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" 
+  *                  define inside the stm3210e_eval.h file.
+  *                  The SD Card frequency (SDIO_CK) is computed as follows:
+  *
+  *                     +---------------------------------------------+
+  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
+  *                     +---------------------------------------------+
+  *
+  *                  In transfer mode and according to the SD Card standard, 
+  *                  make sure that the SDIO_CK frequency don't exceed 25MHz
+  *                  and 50MHz in High-speed mode switch.
+  *                  To be able to use a frequency higher than 24MHz, you should
+  *                  use the SDIO peripheral in bypass mode. Refer to the 
+  *                  corresponding reference manual for more details.
+  *
+  *              4 -  Select the corresponding SD Card according to the address
+  *                   read with the step 2.
+  *
+  *              5 -  Configure the SD Card in wide bus mode: 4-bits data.
+  *
+  *          B - SD Card Read operation
+  *          ========================== 
+  *           - You can read SD card by using two function: SD_ReadBlock() and
+  *             SD_ReadMultiBlocks() functions. These functions support only
+  *             512-byte block length.
+  *           - The SD_ReadBlock() function read only one block (512-byte). This
+  *             function can transfer the data using DMA controller or using 
+  *             polling mode. To select between DMA or polling mode refer to 
+  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm3210e_eval_sdio_sd.h
+  *             file and uncomment the corresponding line. By default the SD DMA
+  *             mode is selected          
+  *           - The SD_ReadMultiBlocks() function read only mutli blocks (multiple 
+  *             of 512-byte). 
+  *           - Any read operation should be followed by two functions to check
+  *             if the DMA Controller and SD Card status.
+  *              - SD_ReadWaitOperation(): this function insure that the DMA
+  *                controller has finished all data transfer.
+  *              - SD_GetStatus(): to check that the SD Card has finished the 
+  *                data transfer and it is ready for data.
+  *
+  *           - The DMA transfer is finished by the SDIO Data End interrupt. 
+  *             User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler()
+  *             and SD_ProcessDMAIRQ() function inside the DMA2_Channel4_5_IRQHandler().
+  *             Don't forget to enable the SDIO_IRQn and DMA2_Channel4_5_IRQn 
+  *             interrupts using the NVIC controller.
+  *
+  *          C - SD Card Write operation
+  *          =========================== 
+  *           - You can write SD card by using two function: SD_WriteBlock() and
+  *             SD_WriteMultiBlocks() functions. These functions support only
+  *             512-byte block length.   
+  *           - The SD_WriteBlock() function write only one block (512-byte). This
+  *             function can transfer the data using DMA controller or using 
+  *             polling mode. To select between DMA or polling mode refer to 
+  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm3210e_eval_sdio_sd.h
+  *             file and uncomment the corresponding line. By default the SD DMA
+  *             mode is selected          
+  *           - The SD_WriteMultiBlocks() function write only mutli blocks (multiple 
+  *             of 512-byte). 
+  *           - Any write operation should be followed by two functions to check
+  *             if the DMA Controller and SD Card status.
+  *              - SD_ReadWaitOperation(): this function insure that the DMA
+  *                controller has finished all data transfer.
+  *              - SD_GetStatus(): to check that the SD Card has finished the 
+  *                data transfer and it is ready for data.
+  *
+  *           - The DMA transfer is finished by the SDIO Data End interrupt. 
+  *             User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler()
+  *             and SD_ProcessDMAIRQ() function inside the DMA2_Channel4_5_IRQHandler().
+  *             Don't forget to enable the SDIO_IRQn and DMA2_Channel4_5_IRQn 
+  *             interrupts using the NVIC controller.
+  *
+  *
+  *          D - SD card status
+  *          ================== 
+  *           - At any time, you can check the SD Card status and get the SD card
+  *             state by using the SD_GetStatus() function. This function checks
+  *             first if the SD card is still connected and then get the internal
+  *             SD Card transfer state.     
+  *           - You can also get the SD card SD Status register by using the 
+  *             SD_SendSDStatus() function.
+  *
+  *          E - Programming Model (Selecting DMA for SDIO data Transfer)
+  *          ============================================================ 
+  *             Status = SD_Init(); // Initialization Step as described in section A
+  *
+  *             // SDIO Interrupt ENABLE
+  *             NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
+  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  *             NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  *             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  *             NVIC_Init(&NVIC_InitStructure);
+  *             // DMA2 Channel4 Interrupt ENABLE
+  *             NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn;
+  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  *             NVIC_Init(&NVIC_InitStructure);
+  *               
+  *             // Write operation as described in Section C
+  *             Status = SD_WriteBlock(buffer, address, 512);
+  *             Status = SD_WaitWriteOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
+  *             Status = SD_WaitWriteOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             // Read operation as described in Section B
+  *             Status = SD_ReadBlock(buffer, address, 512);
+  *             Status = SD_WaitReadOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
+  *             Status = SD_WaitReadOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             - Add the SDIO and DMA2 Channel4 IRQ Handlers:   
+  *                 void SDIO_IRQHandler(void)
+  *                 {
+  *                   SD_ProcessIRQ();  
+  *                 }   
+  *                 void SD_SDIO_DMA_IRQHANDLER(void)
+  *                 {
+  *                   SD_ProcessDMAIRQ();  
+  *                 }     
+  *
+  *          F - Programming Model (Selecting Polling for SDIO data Transfer)
+  *          ================================================================
+  *            //Only SD Card Single Block operation are managed.   
+  *            Status = SD_Init(); // Initialization Step as described in section
+  *               
+  *            // Write operation as described in Section C
+  *            Status = SD_WriteBlock(buffer, address, 512);
+  *
+  *            // Read operation as described in Section B
+  *            Status = SD_ReadBlock(buffer, address, 512);
+  *                 
+  *          STM32 SDIO Pin assignment
+  *          =========================
+  *          +-----------------------------------------------------------+
+  *          |                     Pin assignment                        |
+  *          +-----------------------------+---------------+-------------+
+  *          |  STM32 SDIO Pins            |     SD        |    Pin      |
+  *          +-----------------------------+---------------+-------------+
+  *          |      SDIO D2                |   D2          |    1        |
+  *          |      SDIO D3                |   D3          |    2        |
+  *          |      SDIO CMD               |   CMD         |    3        |
+  *          |                             |   VCC         |    4 (3.3 V)|
+  *          |      SDIO CLK               |   CLK         |    5        |
+  *          |                             |   GND         |    6 (0 V)  |
+  *          |      SDIO D0                |   D0          |    7        |
+  *          |      SDIO D1                |   D1          |    8        |
+  *          +-----------------------------+---------------+-------------+
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval_sdio_sd.h"
+
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_SDIO_SD
+  * @brief      This file provides all the SD Card driver firmware functions.
+  * @{
+  */ 
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Defines
+  * @{
+  */ 
+
+/** 
+  * @brief  SDIO Static flags, TimeOut, FIFO Address  
+  */
+#define NULL 0
+#define SDIO_STATIC_FLAGS               ((uint32_t)0x000005FF)
+#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
+
+/** 
+  * @brief  Mask for errors Card Status R1 (OCR Register) 
+  */
+#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
+#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
+#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
+#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
+#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
+#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
+#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
+#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
+
+#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
+#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
+#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
+#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
+
+#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
+#define SD_ALLZERO                      ((uint32_t)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
+#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
+
+#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
+#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
+#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
+#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
+#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
+#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
+
+#define SD_HALFFIFO                     ((uint32_t)0x00000008)
+#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Command Class Supported 
+  */
+#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
+#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
+#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Following commands are SD Card Specific commands.
+  *         SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SDIO_SEND_IF_COND               ((uint32_t)0x00000008)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Variables
+  * @{
+  */
+
+static uint32_t CardType =  SDIO_STD_CAPACITY_SD_CARD_V1_1;
+static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0;
+static uint8_t SDSTATUS_Tab[16];
+__IO uint32_t StopCondition = 0;
+__IO SD_Error TransferError = SD_OK;
+__IO uint32_t TransferEnd = 0, DMAEndOfTransfer = 0;
+SD_CardInfo SDCardInfo;
+
+SDIO_InitTypeDef SDIO_InitStructure;
+SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+SDIO_DataInitTypeDef SDIO_DataInitStructure;
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Function_Prototypes
+  * @{
+  */
+static SD_Error CmdError(void);
+static SD_Error CmdResp1Error(uint8_t cmd);
+static SD_Error CmdResp7Error(void);
+static SD_Error CmdResp3Error(void);
+static SD_Error CmdResp2Error(void);
+static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca);
+static SD_Error SDEnWideBus(FunctionalState NewState);
+static SD_Error IsCardProgramming(uint8_t *pstatus);
+static SD_Error FindSCR(uint16_t rca, uint32_t *pscr);
+uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes);
+  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Private_Functions
+  * @{
+  */  
+
+/**
+  * @brief  DeInitializes the SDIO interface.
+  * @param  None
+  * @retval None
+  */
+void SD_DeInit(void)
+{ 
+  SD_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for data 
+  *         transfer).
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_Init(void)
+{
+  __IO SD_Error errorstatus = SD_OK;
+  
+  /* SDIO Peripheral Low Level Init */
+  SD_LowLevel_Init();
+
+  SDIO_DeInit();
+
+  errorstatus = SD_PowerON();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  errorstatus = SD_InitializeCards();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  /*!< Configure the SDIO peripheral */
+  /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */
+  SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
+  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+  SDIO_Init(&SDIO_InitStructure);
+
+  /*----------------- Read CSD/CID MSD registers ------------------*/
+  errorstatus = SD_GetCardInfo(&SDCardInfo);
+
+  if (errorstatus == SD_OK)
+  {
+    /*----------------- Select Card --------------------------------*/
+    errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16));
+  }
+
+  if (errorstatus == SD_OK)
+  {
+    errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b);
+  }  
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Gets the cuurent sd card data transfer status.
+  * @param  None
+  * @retval SDTransferState: Data Transfer state.
+  *   This value can be: 
+  *        - SD_TRANSFER_OK: No data transfer is acting
+  *        - SD_TRANSFER_BUSY: Data transfer is acting
+  */
+SDTransferState SD_GetStatus(void)
+{
+  SDCardState cardstate =  SD_CARD_TRANSFER;
+
+  cardstate = SD_GetState();
+  
+  if (cardstate == SD_CARD_TRANSFER)
+  {
+    return(SD_TRANSFER_OK);
+  }
+  else if(cardstate == SD_CARD_ERROR)
+  {
+    return (SD_TRANSFER_ERROR);
+  }
+  else
+  {
+    return(SD_TRANSFER_BUSY);
+  }
+}
+
+/**
+  * @brief  Returns the current card's state.
+  * @param  None
+  * @retval SDCardState: SD Card Error or SD Card Current State.
+  */
+SDCardState SD_GetState(void)
+{
+  uint32_t resp1 = 0;
+  
+  if(SD_Detect()== SD_PRESENT)
+  {
+    if (SD_SendStatus(&resp1) != SD_OK)
+    {
+      return SD_CARD_ERROR;
+    }
+    else
+    {
+      return (SDCardState)((resp1 >> 9) & 0x0F);
+    }
+  }
+  else
+  {
+    return SD_CARD_ERROR;
+  }
+}
+
+/**
+ * @brief  Detect if SD card is correctly plugged in the memory slot.
+ * @param  None
+ * @retval Return if SD is detected or not
+ */
+uint8_t SD_Detect(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  /*!< Check GPIO to detect SD */
+  if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET)
+  {
+    status = SD_NOT_PRESENT;
+  }
+  return status;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures 
+  *   clock controls.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_PowerON(void)
+{
+  __IO SD_Error errorstatus = SD_OK;
+  uint32_t response = 0, count = 0, validvoltage = 0;
+  uint32_t SDType = SD_STD_CAPACITY;
+
+  /*!< Power ON Sequence -----------------------------------------------------*/
+  /*!< Configure the SDIO peripheral */
+  /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */
+  /*!< SDIO_CK for initialization should not exceed 400 KHz */  
+  SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV;
+  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+  SDIO_Init(&SDIO_InitStructure);
+
+  /*!< Set Power State to ON */
+  SDIO_SetPowerState(SDIO_PowerState_ON);
+
+  /*!< Enable SDIO Clock */
+  SDIO_ClockCmd(ENABLE);
+
+  /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/
+  /*!< No CMD response required */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdError();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/
+  /*!< Send CMD8 to verify SD card interface operating condition */
+  /*!< Argument: - [31:12]: Reserved (shall be set to '0')
+               - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+               - [7:0]: Check Pattern (recommended 0xAA) */
+  /*!< CMD Response: R7 */
+  SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp7Error();
+
+  if (errorstatus == SD_OK)
+  {
+    CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */
+    SDType = SD_HIGH_CAPACITY;
+  }
+  else
+  {
+    /*!< CMD55 */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+    errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+  }
+  /*!< CMD55 */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  /*!< If errorstatus is Command TimeOut, it is a MMC card */
+  /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  if (errorstatus == SD_OK)
+  {
+    /*!< SD CARD */
+    /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+    while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
+    {
+
+      /*!< SEND CMD55 APP_CMD with RCA as 0 */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+      SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp3Error();
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      response = SDIO_GetResponse(SDIO_RESP1);
+      validvoltage = (((response >> 31) == 1) ? 1 : 0);
+      count++;
+    }
+    if (count >= SD_MAX_VOLT_TRIAL)
+    {
+      errorstatus = SD_INVALID_VOLTRANGE;
+      return(errorstatus);
+    }
+
+    if (response &= SD_HIGH_CAPACITY)
+    {
+      CardType = SDIO_HIGH_CAPACITY_SD_CARD;
+    }
+
+  }/*!< else MMC Card */
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Turns the SDIO output signals off.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_PowerOFF(void)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Set Power State to OFF */
+  SDIO_SetPowerState(SDIO_PowerState_OFF);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Intialises all cards or single card as the case may be Card(s) come 
+  *         into standby state.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_InitializeCards(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint16_t rca = 0x01;
+
+  if (SDIO_GetPowerState() == SDIO_PowerState_OFF)
+  {
+    errorstatus = SD_REQUEST_NOT_APPLICABLE;
+    return(errorstatus);
+  }
+
+  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
+  {
+    /*!< Send CMD2 ALL_SEND_CID */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp2Error();
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+
+    CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
+    CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
+    CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
+    CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) ||  (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) ||  (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType)
+      ||  (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    /*!< Send CMD3 SET_REL_ADDR with argument 0 */
+    /*!< SD Card publishes its RCA. */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca);
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+  }
+
+  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
+  {
+    RCA = rca;
+
+    /*!< Send CMD9 SEND_CSD with argument as card's RCA */
+    SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16);
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp2Error();
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+
+    CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
+    CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
+    CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
+    CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+
+  errorstatus = SD_OK; /*!< All cards get intialized */
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD card 
+  *         information.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
+{
+  SD_Error errorstatus = SD_OK;
+  uint8_t tmp = 0;
+
+  cardinfo->CardType = (uint8_t)CardType;
+  cardinfo->RCA = (uint16_t)RCA;
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6;
+  cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2;
+  cardinfo->SD_csd.Reserved1 = tmp & 0x03;
+
+  /*!< Byte 1 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.TAAC = tmp;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.NSAC = tmp;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF);
+  cardinfo->SD_csd.MaxBusClkFrec = tmp;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.CardComdClasses = tmp << 4;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4;
+  cardinfo->SD_csd.RdBlockLen = tmp & 0x0F;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4;
+  cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */
+
+  if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0))
+  {
+    cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
+
+    /*!< Byte 7 */
+    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
+    cardinfo->SD_csd.DeviceSize |= (tmp) << 2;
+
+    /*!< Byte 8 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
+    cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
+
+    cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
+    cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
+
+    /*!< Byte 9 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
+    cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
+    cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
+    cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
+    /*!< Byte 10 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
+    cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
+    
+    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
+    cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
+    cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
+    cardinfo->CardCapacity *= cardinfo->CardBlockSize;
+  }
+  else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    /*!< Byte 7 */
+    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
+    cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
+
+    /*!< Byte 8 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
+
+    cardinfo->SD_csd.DeviceSize |= (tmp << 8);
+
+    /*!< Byte 9 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
+
+    cardinfo->SD_csd.DeviceSize |= (tmp);
+
+    /*!< Byte 10 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
+    
+    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024;
+    cardinfo->CardBlockSize = 512;    
+  }
+
+
+  cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF);
+  cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
+  cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
+  cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
+  cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.Reserved3 = 0;
+  cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
+
+  /*!< Byte 14 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
+  cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
+  cardinfo->SD_csd.ECC = (tmp & 0x03);
+
+  /*!< Byte 15 */
+  tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF);
+  cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
+  cardinfo->SD_csd.Reserved4 = 1;
+
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ManufacturerID = tmp;
+
+  /*!< Byte 1 */
+  tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.OEM_AppliID = tmp << 8;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8);
+  cardinfo->SD_cid.OEM_AppliID |= tmp;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)(CID_Tab[0] & 0x000000FF);
+  cardinfo->SD_cid.ProdName1 = tmp << 24;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdName1 |= tmp << 16;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.ProdName1 |= tmp << 8;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ProdName1 |= tmp;
+
+  /*!< Byte 7 */
+  tmp = (uint8_t)(CID_Tab[1] & 0x000000FF);
+  cardinfo->SD_cid.ProdName2 = tmp;
+
+  /*!< Byte 8 */
+  tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdRev = tmp;
+
+  /*!< Byte 9 */
+  tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.ProdSN = tmp << 24;
+
+  /*!< Byte 10 */
+  tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ProdSN |= tmp << 16;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(CID_Tab[2] & 0x000000FF);
+  cardinfo->SD_cid.ProdSN |= tmp << 8;
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdSN |= tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
+  cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
+
+  /*!< Byte 14 */
+  tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ManufactDate |= tmp;
+
+  /*!< Byte 15 */
+  tmp = (uint8_t)(CID_Tab[3] & 0x000000FF);
+  cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
+  cardinfo->SD_cid.Reserved2 = 1;
+  
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
+  *         card.
+  * @param  WideMode: Specifies the SD card wide bus mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
+  *     @arg SDIO_BusWide_4b: 4-bit data transfer
+  *     @arg SDIO_BusWide_1b: 1-bit data transfer
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  uint8_t tmp = 0;
+
+  errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab);
+
+  if (errorstatus  != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6);
+  cardstatus->DAT_BUS_WIDTH = tmp;
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5);
+  cardstatus->SECURED_MODE = tmp;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF));
+  cardstatus->SD_CARD_TYPE = tmp << 8;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF));
+  cardstatus->SD_CARD_TYPE |= tmp;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8;
+
+  /*!< Byte 7 */
+  tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp;
+
+  /*!< Byte 8 */
+  tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF));
+  cardstatus->SPEED_CLASS = tmp;
+
+  /*!< Byte 9 */
+  tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF));
+  cardstatus->PERFORMANCE_MOVE = tmp;
+
+  /*!< Byte 10 */
+  tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4);
+  cardstatus->AU_SIZE = tmp;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF);
+  cardstatus->ERASE_SIZE = tmp << 8;
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF);
+  cardstatus->ERASE_SIZE |= tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2);
+  cardstatus->ERASE_TIMEOUT = tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3));
+  cardstatus->ERASE_OFFSET = tmp;
+ 
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
+  *         card.
+  * @param  WideMode: Specifies the SD card wide bus mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
+  *     @arg SDIO_BusWide_4b: 4-bit data transfer
+  *     @arg SDIO_BusWide_1b: 1-bit data transfer
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< MMC Card doesn't support this feature */
+  if (SDIO_MULTIMEDIA_CARD == CardType)
+  {
+    errorstatus = SD_UNSUPPORTED_FEATURE;
+    return(errorstatus);
+  }
+  else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    if (SDIO_BusWide_8b == WideMode)
+    {
+      errorstatus = SD_UNSUPPORTED_FEATURE;
+      return(errorstatus);
+    }
+    else if (SDIO_BusWide_4b == WideMode)
+    {
+      errorstatus = SDEnWideBus(ENABLE);
+
+      if (SD_OK == errorstatus)
+      {
+        /*!< Configure the SDIO peripheral */
+        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
+        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
+        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+        SDIO_Init(&SDIO_InitStructure);
+      }
+    }
+    else
+    {
+      errorstatus = SDEnWideBus(DISABLE);
+
+      if (SD_OK == errorstatus)
+      {
+        /*!< Configure the SDIO peripheral */
+        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
+        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+        SDIO_Init(&SDIO_InitStructure);
+      }
+    }
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Selects od Deselects the corresponding card.
+  * @param  addr: Address of the Card to be selected.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SelectDeselect(uint32_t addr)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Send CMD7 SDIO_SEL_DESEL_CARD */
+  SDIO_CmdInitStructure.SDIO_Argument =  addr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to read one block from a specified address in a card. The Data
+  *         transfer can be managed by DMA mode or Polling mode. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.            
+  * @param  readbuff: pointer to the buffer that will contain the received data
+  * @param  ReadAddr: Address from where data are to be read.  
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize)
+{
+  SD_Error errorstatus = SD_OK;
+#if defined (SD_POLLING_MODE) 
+  uint32_t count = 0, *tempbuff = (uint32_t *)readbuff;
+#endif
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 0;
+  
+  SDIO->DCTRL = 0x0;
+
+  
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+  
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send CMD17 READ_SINGLE_BLOCK */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+#if defined (SD_POLLING_MODE)  
+  /*!< In case of single block transfer, no need of stop transfer at all.*/
+  /*!< Polling mode */
+  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
+    {
+      for (count = 0; count < 8; count++)
+      {
+        *(tempbuff + count) = SDIO_ReadData();
+      }
+      tempbuff += 8;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+  count = SD_DATATIMEOUT;
+  while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
+  {
+    *tempbuff = SDIO_ReadData();
+    tempbuff++;
+    count--;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+#elif defined (SD_DMA_MODE)
+    SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+    SDIO_DMACmd(ENABLE);
+    SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize);
+#endif
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to read blocks from a specified address  in a card.  The Data
+  *         transfer can be managed by DMA mode or Polling mode. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.   
+  * @param  readbuff: pointer to the buffer that will contain the received data.
+  * @param  ReadAddr: Address from where data are to be read.
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @param  NumberOfBlocks: number of blocks to be read.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SD_Error errorstatus = SD_OK;
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 1;
+	
+  SDIO->DCTRL = 0x0;
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+
+  /*!< Set Block Size for Card */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+    
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send CMD18 READ_MULT_BLOCK with argument data address */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SDIO_DMACmd(ENABLE);
+  SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize));
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  *         This function should be called after SDIO_ReadMultiBlocks() function
+  *         to insure that all data sent by the card are already transferred by 
+  *         the DMA controller.
+  * @param  None.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WaitReadOperation(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0))
+  {
+    timeout--;
+  }
+  
+  DMAEndOfTransfer = 0x00;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0))
+  {
+    timeout--;  
+  }
+
+  if (StopCondition == 1)
+  {
+    errorstatus = SD_StopTransfer();
+  }
+  
+  if ((timeout == 0) && (errorstatus == SD_OK))
+  {
+    errorstatus = SD_DATA_TIMEOUT;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  if (TransferError != SD_OK)
+  {
+    return(TransferError);
+  }
+  else
+  {
+    return(errorstatus);  
+  }
+}
+
+/**
+  * @brief  Allows to write one block starting from a specified address in a card.
+  *         The Data transfer can be managed by DMA mode or Polling mode.
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.      
+  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
+  * @param  WriteAddr: Address from where data are to be read.   
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize)
+{
+  SD_Error errorstatus = SD_OK;
+
+#if defined (SD_POLLING_MODE)
+  uint32_t bytestransferred = 0, count = 0, restwords = 0;
+  uint32_t *tempbuff = (uint32_t *)writebuff;
+#endif
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 0;
+  
+  SDIO->DCTRL = 0x0;
+
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+    
+  /*!< Send CMD24 WRITE_SINGLE_BLOCK */
+  SDIO_CmdInitStructure.SDIO_Argument = WriteAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< In case of single data block transfer no need of stop command at all */
+#if defined (SD_POLLING_MODE) 
+  while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET)
+    {
+      if ((512 - bytestransferred) < 32)
+      {
+        restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 -  bytestransferred) / 4 + 1);
+        for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4)
+        {
+          SDIO_WriteData(*tempbuff);
+        }
+      }
+      else
+      {
+        for (count = 0; count < 8; count++)
+        {
+          SDIO_WriteData(*(tempbuff + count));
+        }
+        tempbuff += 8;
+        bytestransferred += 32;
+      }
+    }
+  }
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_TXUNDERR);
+    errorstatus = SD_TX_UNDERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+#elif defined (SD_DMA_MODE)
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize);
+  SDIO_DMACmd(ENABLE);
+#endif
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to write blocks starting from a specified address in a card.
+  *         The Data transfer can be managed by DMA mode only. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.     
+  * @param  WriteAddr: Address from where data are to be read.
+  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @param  NumberOfBlocks: number of blocks to be written.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SD_Error errorstatus = SD_OK;
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 1;
+  
+  SDIO->DCTRL = 0x0;
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+  
+  /*!< To improve performance */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16);
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+  /*!< To improve performance */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+
+  /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SDIO_DMACmd(ENABLE);
+  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize));
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  *         This function should be called after SDIO_WriteBlock() and
+  *         SDIO_WriteMultiBlocks() function to insure that all data sent by the 
+  *         card are already transferred by the DMA controller.        
+  * @param  None.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WaitWriteOperation(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0))
+  {
+    timeout--;
+  }
+  
+  DMAEndOfTransfer = 0x00;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0))
+  {
+    timeout--;  
+  }
+
+  if (StopCondition == 1)
+  {
+    errorstatus = SD_StopTransfer();
+  }
+  
+  if ((timeout == 0) && (errorstatus == SD_OK))
+  {
+    errorstatus = SD_DATA_TIMEOUT;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+  
+  if (TransferError != SD_OK)
+  {
+    return(TransferError);
+  }
+  else
+  {
+    return(errorstatus);
+  }
+}
+
+/**
+  * @brief  Gets the cuurent data transfer state.
+  * @param  None
+  * @retval SDTransferState: Data Transfer state.
+  *   This value can be: 
+  *        - SD_TRANSFER_OK: No data transfer is acting
+  *        - SD_TRANSFER_BUSY: Data transfer is acting
+  */
+SDTransferState SD_GetTransferState(void)
+{
+  if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT))
+  {
+    return(SD_TRANSFER_BUSY);
+  }
+  else
+  {
+    return(SD_TRANSFER_OK);
+  }
+}
+
+/**
+  * @brief  Aborts an ongoing data transfer.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_StopTransfer(void)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Send CMD12 STOP_TRANSMISSION  */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to erase memory area specified for the given card.
+  * @param  startaddr: the start address.
+  * @param  endaddr: the end address.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t delay = 0;
+  __IO uint32_t maxdelay = 0;
+  uint8_t cardstate = 0;
+
+  /*!< Check if the card coomnd class supports erase command */
+  if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0)
+  {
+    errorstatus = SD_REQUEST_NOT_APPLICABLE;
+    return(errorstatus);
+  }
+
+  maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2);
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    startaddr /= 512;
+    endaddr /= 512;
+  }
+  
+  /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+    SDIO_CmdInitStructure.SDIO_Argument = startaddr;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START);
+    if (errorstatus != SD_OK)
+    {
+      return(errorstatus);
+    }
+
+    /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+    SDIO_CmdInitStructure.SDIO_Argument = endaddr;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END);
+    if (errorstatus != SD_OK)
+    {
+      return(errorstatus);
+    }
+  }
+
+  /*!< Send CMD38 ERASE */
+  SDIO_CmdInitStructure.SDIO_Argument = 0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_ERASE);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  for (delay = 0; delay < maxdelay; delay++)
+  {}
+
+  /*!< Wait till the card is in programming state */
+  errorstatus = IsCardProgramming(&cardstate);
+  delay = SD_DATATIMEOUT;
+  while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate)))
+  {
+    errorstatus = IsCardProgramming(&cardstate);
+    delay--;
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  pcardstatus: pointer to the buffer that will contain the SD card 
+  *         status (Card Status register).
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SendStatus(uint32_t *pcardstatus)
+{
+  SD_Error errorstatus = SD_OK;
+
+  if (pcardstatus == NULL)
+  {
+    errorstatus = SD_INVALID_PARAMETER;
+    return(errorstatus);
+  }
+
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  *pcardstatus = SDIO_GetResponse(SDIO_RESP1);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns the current SD card's status.
+  * @param  psdstatus: pointer to the buffer that will contain the SD card status 
+  *         (SD Status register).
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SendSDStatus(uint32_t *psdstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t count = 0;
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  /*!< Set block size for card if it is not equal to current block size for card. */
+  SDIO_CmdInitStructure.SDIO_Argument = 64;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< CMD55 */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = 64;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send ACMD13 SD_APP_STAUS  with argument as card's RCA.*/
+  SDIO_CmdInitStructure.SDIO_Argument = 0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
+    {
+      for (count = 0; count < 8; count++)
+      {
+        *(psdstatus + count) = SDIO_ReadData();
+      }
+      psdstatus += 8;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+
+  count = SD_DATATIMEOUT;
+  while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
+  {
+    *psdstatus = SDIO_ReadData();
+    psdstatus++;
+    count--;
+  }
+  /*!< Clear all the static status flags*/
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to process all the interrupts that are high.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ProcessIRQSrc(void)
+{ 
+  if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET)
+  {
+    TransferError = SD_OK;
+    SDIO_ClearITPendingBit(SDIO_IT_DATAEND);
+    TransferEnd = 1;
+  }  
+  else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL);
+    TransferError = SD_DATA_CRC_FAIL;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT);
+    TransferError = SD_DATA_TIMEOUT;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_RXOVERR);
+    TransferError = SD_RX_OVERRUN;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR);
+    TransferError = SD_TX_UNDERRUN;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_STBITERR);
+    TransferError = SD_START_BIT_ERR;
+  }
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |
+                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |
+                SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE);
+  return(TransferError);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  * @param  None.
+  * @retval None.
+  */
+void SD_ProcessDMAIRQ(void)
+{
+  if(DMA2->ISR & DMA2_FLAG_TC4)
+  {
+    DMAEndOfTransfer = 0x01;
+    DMA_ClearFlag(DMA2_FLAG_TC4 | DMA2_FLAG_TE4 | DMA2_FLAG_HT4 | DMA2_FLAG_GL4);
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdError(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */
+
+  while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET))
+  {
+    timeout--;
+  }
+
+  if (timeout == 0)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp7Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t timeout = SDIO_CMD0TIMEOUT;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0))
+  {
+    timeout--;
+    status = SDIO->STA;
+  }
+
+  if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT))
+  {
+    /*!< Card is not V2.0 complient or card does not support the set voltage range */
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+
+  if (status & SDIO_FLAG_CMDREND)
+  {
+    /*!< Card is SD V2.0 compliant */
+    errorstatus = SD_OK;
+    SDIO_ClearFlag(SDIO_FLAG_CMDREND);
+    return(errorstatus);
+  }
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  cmd: The sent command index.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp1Error(uint8_t cmd)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t response_r1;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Check response received is of desired command */
+  if (SDIO_GetCommandResponse() != cmd)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  /*!< We have received response, retrieve it for analysis  */
+  response_r1 = SDIO_GetResponse(SDIO_RESP1);
+
+  if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return(errorstatus);
+  }
+
+  if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+
+  if (response_r1 & SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+
+  if (response_r1 & SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+
+  if (response_r1 & SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+
+  if (response_r1 & SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+
+  if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+
+  if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (response_r1 & SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+
+  if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+
+  if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+
+  if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+
+  if (response_r1 & SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+
+  if (response_r1 & SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+
+  if (response_r1 & SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+
+  if (response_r1 & SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp3Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp2Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  cmd: The sent command index.
+  * @param  prca: pointer to the variable that will contain the SD card relative 
+  *         address RCA. 
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t response_r1;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Check response received is of desired command */
+  if (SDIO_GetCommandResponse() != cmd)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  /*!< We have received response, retrieve it.  */
+  response_r1 = SDIO_GetResponse(SDIO_RESP1);
+
+  if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)))
+  {
+    *prca = (uint16_t) (response_r1 >> 16);
+    return(errorstatus);
+  }
+
+  if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (response_r1 & SD_R6_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (response_r1 & SD_R6_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables or disables the SDIO wide bus mode.
+  * @param  NewState: new state of the SDIO wide bus mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error SDEnWideBus(FunctionalState NewState)
+{
+  SD_Error errorstatus = SD_OK;
+
+  uint32_t scr[2] = {0, 0};
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  /*!< Get SCR Register */
+  errorstatus = FindSCR((uint16_t)RCA, scr);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< If wide bus operation to be enabled */
+  if (NewState == ENABLE)
+  {
+    /*!< If requested card supports wide bus operation */
+    if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+    {
+      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
+      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x2;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+      return(errorstatus);
+    }
+    else
+    {
+      errorstatus = SD_REQUEST_NOT_APPLICABLE;
+      return(errorstatus);
+    }
+  }   /*!< If wide bus operation to be disabled */
+  else
+  {
+    /*!< If requested card supports 1 bit mode operation */
+    if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+    {
+      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
+      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      return(errorstatus);
+    }
+    else
+    {
+      errorstatus = SD_REQUEST_NOT_APPLICABLE;
+      return(errorstatus);
+    }
+  }
+}
+
+/**
+  * @brief  Checks if the SD card is in programming state.
+  * @param  pstatus: pointer to the variable that will contain the SD card state.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error IsCardProgramming(uint8_t *pstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  __IO uint32_t respR1 = 0, status = 0;
+
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  status = SDIO->STA;
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  status = (uint32_t)SDIO_GetCommandResponse();
+
+  /*!< Check response received is of desired command */
+  if (status != SD_CMD_SEND_STATUS)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+
+  /*!< We have received response, retrieve it for analysis  */
+  respR1 = SDIO_GetResponse(SDIO_RESP1);
+
+  /*!< Find out card status */
+  *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F);
+
+  if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return(errorstatus);
+  }
+
+  if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+
+  if (respR1 & SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+
+  if (respR1 & SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+
+  if (respR1 & SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+
+  if (respR1 & SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+
+  if (respR1 & SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+
+  if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+
+  if (respR1 & SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  if (respR1 & SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (respR1 & SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+
+  if (respR1 & SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+
+  if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (respR1 & SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+
+  if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+
+  if (respR1 & SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+
+  if (respR1 & SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+
+  if (respR1 & SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+
+  if (respR1 & SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+
+  if (respR1 & SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Find the SD card SCR register value.
+  * @param  rca: selected card address.
+  * @param  pscr: pointer to the buffer that will contain the SCR value.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error FindSCR(uint16_t rca, uint32_t *pscr)
+{
+  uint32_t index = 0;
+  SD_Error errorstatus = SD_OK;
+  uint32_t tempscr[2] = {0, 0};
+
+  /*!< Set Block Size To 8 Bytes */
+  /*!< Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = 8;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+
+  /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
+    {
+      *(tempscr + index) = SDIO_ReadData();
+      index++;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
+
+  *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Converts the number of bytes in power of two and returns the power.
+  * @param  NumberOfBytes: number of bytes.
+  * @retval None
+  */
+uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes)
+{
+  uint8_t count = 0;
+
+  while (NumberOfBytes != 1)
+  {
+    NumberOfBytes >>= 1;
+    count++;
+  }
+  return(count);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.h
new file mode 100644
index 0000000..e3e2252
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_sdio_sd.h
@@ -0,0 +1,406 @@
+/**
+  ******************************************************************************
+  * @file    stm3210e_eval_sdio_sd.h
+  * @author  MCD Application Team
+  * @version V5.1.0
+  * @date    18-January-2013
+  * @brief   This file contains all the functions prototypes for the SD Card 
+  *          stm3210e_eval_sdio_sd driver firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210E_EVAL_SDIO_SD_H
+#define __STM3210E_EVAL_SDIO_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210e_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM3210E_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM3210E_EVAL_SDIO_SD
+  * @{
+  */  
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Exported_Types
+  * @{
+  */ 
+typedef enum
+{
+/** 
+  * @brief  SDIO specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
+  SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
+  SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
+  SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
+  SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
+  SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
+  SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
+  SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
+  SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
+  SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
+  SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
+  SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
+  SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
+  SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
+  SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18), /*!< Internal card controller error */
+  SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
+  SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
+  SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
+  SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
+  SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
+  SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR, 
+  SD_NOT_CONFIGURED,
+  SD_REQUEST_PENDING, 
+  SD_REQUEST_NOT_APPLICABLE, 
+  SD_INVALID_PARAMETER,  
+  SD_UNSUPPORTED_FEATURE,  
+  SD_UNSUPPORTED_HW,  
+  SD_ERROR,  
+  SD_OK = 0 
+} SD_Error;
+
+/** 
+  * @brief  SDIO Transfer state  
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK  = 0,
+  SD_TRANSFER_BUSY = 1,
+  SD_TRANSFER_ERROR
+} SDTransferState;
+
+/** 
+  * @brief  SD Card States 
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
+}SDCardState;
+
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card Status 
+  */
+typedef struct
+{
+  __IO uint8_t DAT_BUS_WIDTH;
+  __IO uint8_t SECURED_MODE;
+  __IO uint16_t SD_CARD_TYPE;
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;
+  __IO uint8_t SPEED_CLASS;
+  __IO uint8_t PERFORMANCE_MOVE;
+  __IO uint8_t AU_SIZE;
+  __IO uint16_t ERASE_SIZE;
+  __IO uint8_t ERASE_TIMEOUT;
+  __IO uint8_t ERASE_OFFSET;
+} SD_CardStatus;
+
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint64_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+  uint16_t RCA;
+  uint8_t CardType;
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM3210E_EVAL_SDIO_SD_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief SDIO Commands  Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)
+#define SD_CMD_SEND_CID                            ((uint8_t)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
+#define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
+                                                                  block to be erased. (For SD card only) */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For SD card only) */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
+                                                                  (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE                               ((uint8_t)38)
+#define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
+#define SD_CMD_APP_CMD                             ((uint8_t)55)
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)
+#define SD_CMD_NO_CMD                              ((uint8_t)64)
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
+#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
+  
+/* Uncomment the following line to select the SDIO Data transfer mode */  
+#if !defined (SD_DMA_MODE) && !defined (SD_POLLING_MODE)
+#define SD_DMA_MODE                                ((uint32_t)0x00000000)
+/*#define SD_POLLING_MODE                            ((uint32_t)0x00000002)*/
+#endif
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT                                 ((uint8_t)0x01)
+#define SD_NOT_PRESENT                             ((uint8_t)0x00)
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM3210E_EVAL_SDIO_SD_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM3210E_EVAL_SDIO_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);
+SD_Error SD_Init(void);
+SDTransferState SD_GetStatus(void);
+SDCardState SD_GetState(void);
+uint8_t SD_Detect(void);
+SD_Error SD_PowerON(void);
+SD_Error SD_PowerOFF(void);
+SD_Error SD_InitializeCards(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
+SD_Error SD_SelectDeselect(uint32_t addr);
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SDTransferState SD_GetTransferState(void);
+SD_Error SD_StopTransfer(void);
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
+SD_Error SD_SendStatus(uint32_t *pcardstatus);
+SD_Error SD_SendSDStatus(uint32_t *psdstatus);
+SD_Error SD_ProcessIRQSrc(void);
+void SD_ProcessDMAIRQ(void);
+SD_Error SD_WaitReadOperation(void);
+SD_Error SD_WaitWriteOperation(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210E_EVAL_SDIO_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c
new file mode 100644
index 0000000..37cba19
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.c
@@ -0,0 +1,762 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides: a set of firmware functions to manage Leds,
+  *          push-button and COM ports
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */   
+    
+/** @defgroup STM32303C_EVAL_LOW_LEVEL 
+  * @brief This file provides firmware functions to manage Leds, push-buttons, 
+  *        COM ports, SD card on SPI and temperature sensor (TS751) available on 
+  *        STM32303C-EVAL evaluation board from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
+                                 LED4_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+                                 LED4_GPIO_CLK};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT, 
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
+
+const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN, LEFT_BUTTON_PIN, 
+                                      UP_BUTTON_PIN, DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
+
+const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK, 
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
+
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE,
+                                            RIGHT_BUTTON_EXTI_LINE,
+                                            LEFT_BUTTON_EXTI_LINE,
+                                            UP_BUTTON_EXTI_LINE,
+                                            DOWN_BUTTON_EXTI_LINE,
+                                            SEL_BUTTON_EXTI_LINE};
+
+const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE,
+                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
+                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
+                                              UP_BUTTON_EXTI_PORT_SOURCE,
+                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
+                                              SEL_BUTTON_EXTI_PORT_SOURCE};
+								 
+const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE,
+                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
+                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
+                                             UP_BUTTON_EXTI_PIN_SOURCE,
+                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
+                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
+
+const uint8_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, 
+                                       RIGHT_BUTTON_EXTI_IRQn, LEFT_BUTTON_EXTI_IRQn, 
+                                       UP_BUTTON_EXTI_IRQn, DOWN_BUTTON_EXTI_IRQn, 
+                                       SEL_BUTTON_EXTI_IRQn};
+
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; 
+
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
+ 
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
+
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
+
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
+ 
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
+
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
+
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
+ 
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE};
+
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE};
+ 
+const uint8_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF};
+ 
+const uint8_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF};
+
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4
+  * @retval None
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Enable the GPIO_LED Clock */
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter can be one of following parameters: 
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button
+  * @param  Button_Mode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                     generation capability  
+  * @retval None
+  */
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* There is no Wakeup button on STM32303C_EVAL-EVAL, the Button value should
+     be greater than 0. */
+  if(Button > 0)
+  {
+    Button = (Button_TypeDef) (Button - 1);
+    
+    /* Enable the BUTTON Clock */
+    RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+    /* Configure Button pin as input */
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+    GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+    GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+
+    if (Button_Mode == BUTTON_MODE_EXTI)
+    {
+      /* Connect Button EXTI Line to Button GPIO Pin */
+      SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+
+      /* Configure Button EXTI line */
+      EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    
+      if(Button != BUTTON_KEY) 
+      {
+        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
+      }
+      else
+      {
+        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+      }
+      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+      EXTI_Init(&EXTI_InitStructure);
+
+      /* Enable and set Button EXTI Interrupt to the lowest priority */
+      NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+      NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+      NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+      NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+      NVIC_Init(&NVIC_InitStructure); 
+    }
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter can be one of following parameters:
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button     
+  * @retval - When Button > 0, the Button GPIO pin value is returned.
+  *         - When Button = 0 , error code (0xFF) is returned.   
+  */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+  /* There is no Wakeup button on STM32303C_EVAL-EVAL, the Button value should
+     be greater than 0. */
+  if(Button > 0)
+  {
+    Button = (Button_TypeDef) (Button - 1);
+    return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+  }
+  else
+  {
+    return 0xFF; /* Error Code */
+  }
+}
+
+/**
+  * @brief  Configures COM port.
+  * @param  COM: Specifies the COM port to be configured.
+  *   This parameter can be one of following parameters:    
+  *     @arg COM1  
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
+  *   contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
+
+  /* Enable USART clock */
+  RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
+
+  /* Connect PXx to USARTx_Tx */
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
+
+  /* Connect PXx to USARTx_Rx */
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
+  
+  /* Configure USART Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
+    
+  /* Configure USART Rx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
+
+  /* USART configuration */
+  USART_Init(COM_USART[COM], USART_InitStruct);
+    
+  /* Enable USART */
+  USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+  * @brief  DeInitializes the SPI interface.
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  SPI_Cmd(SD_SPI, DISABLE); /* SD_SPI disable */
+  SPI_I2S_DeInit(SD_SPI);   /* DeInitializes the SD_SPI */
+  
+  /* SD_SPI Periph clock disable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); 
+
+  /*Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  SPI_InitTypeDef   SPI_InitStructure;
+
+  /* SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
+       and SD_SPI_SCK_GPIO Periph clock enable */
+  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
+                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
+
+  /* SD_SPI Periph clock enable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); 
+
+  /* Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PXx to SD_SPI_SCK */
+  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
+
+  /* Connect PXx to SD_SPI_MISO */
+  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); 
+
+  /* Connect PXx to SD_SPI_MOSI */
+  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  
+  
+  /* SD_SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(SD_SPI, &SPI_InitStructure);
+  
+  SPI_RxFIFOThresholdConfig(SD_SPI, SPI_RxFIFOThreshold_QF);
+  
+  SPI_Cmd(SD_SPI, ENABLE); /* SD_SPI enable */
+}
+
+/**
+  * @brief  DeInitializes the TS751_I2C.
+  * @param  None
+  * @retval None
+  */
+void TS751_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /* Disable TS751_I2C */
+  I2C_Cmd(TS751_I2C, DISABLE);
+  
+  /* DeInitializes the TS751_I2C */
+  I2C_DeInit(TS751_I2C);
+  
+  /* TS751_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(TS751_I2C_CLK, DISABLE);
+    
+  /* Configure TS751_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(TS751_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure TS751_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SDA_PIN;
+  GPIO_Init(TS751_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure TS751_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SMBUSALERT_PIN;
+  GPIO_Init(TS751_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the TS751_I2C..
+  * @param  None
+  * @retval None
+  */
+void TS751_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /* TS751_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(TS751_I2C_CLK, ENABLE);
+    
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+  
+  /* TS751_I2C_SCL_GPIO_CLK, TS751_I2C_SDA_GPIO_CLK 
+       and TS751_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(TS751_I2C_SCL_GPIO_CLK | TS751_I2C_SDA_GPIO_CLK |
+                        TS751_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
+  
+  /* Connect PXx to I2C_SCL */
+  GPIO_PinAFConfig(TS751_I2C_SCL_GPIO_PORT, TS751_I2C_SCL_SOURCE, TS751_I2C_SCL_AF);
+
+  /* Connect PXx to I2C_SDA */
+  GPIO_PinAFConfig(TS751_I2C_SDA_GPIO_PORT, TS751_I2C_SDA_SOURCE, TS751_I2C_SDA_AF); 
+
+  /* Connect PXx to I2C_SMBUSALER */
+  GPIO_PinAFConfig(TS751_I2C_SMBUSALERT_GPIO_PORT, TS751_I2C_SMBUSALERT_SOURCE, TS751_I2C_SMBUSALERT_AF);
+    
+  /* Configure TS751_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(TS751_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure TS751_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SDA_PIN;
+  GPIO_Init(TS751_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure TS751_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = TS751_I2C_SMBUSALERT_PIN;
+  GPIO_Init(TS751_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_I2C_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure; 
+   
+  /* sEE_I2C Peripheral Disable */
+  I2C_Cmd(sEE_I2C, DISABLE);
+ 
+  /* sEE_I2C DeInit */
+  I2C_DeInit(sEE_I2C);
+
+  /* sEE_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
+    
+  /* GPIO configuration */  
+  /* Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_I2C_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+    
+  /* sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
+  
+  /* sEE_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
+  
+  /* Connect PXx to I2C_SCL*/
+  GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
+  
+  /* Connect PXx to I2C_SDA*/
+  GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);
+  
+  /* GPIO configuration */  
+  /* Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);     
+}
+
+/**
+  * @brief  DeInitializes the SPI interface.
+  * @param  None
+  * @retval None
+  */
+void sEE_SPI_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  SPI_Cmd(sEE_SPI, DISABLE); /* sEE_SPI disable */
+  SPI_I2S_DeInit(sEE_SPI);   /* DeInitializes the sEE_SPI */
+  
+  /* sEE_SPI Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_SPI_CLK, DISABLE); 
+
+  /* Configure sEE_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MISO_PIN;
+  GPIO_Init(sEE_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MOSI_PIN;
+  GPIO_Init(sEE_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE_CS_PIN pin: sEE Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_CS_PIN;
+  GPIO_Init(sEE_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SPI interface for EEPROM
+  * @param  None
+  * @retval None
+  */
+void sEE_SPI_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  SPI_InitTypeDef   SPI_InitStructure;
+
+  /* sEE_CS_GPIO, sEE_MOSI_GPIO, sEE_MISO_GPIO and sEE_SCK_GPIO 
+       Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_SPI_CS_GPIO_CLK | sEE_SPI_MOSI_GPIO_CLK | sEE_SPI_MISO_GPIO_CLK |
+                        sEE_SPI_SCK_GPIO_CLK , ENABLE);
+
+  /* sEE Periph clock enable */
+  RCC_APB1PeriphClockCmd(sEE_SPI_CLK, ENABLE); 
+
+  /* Configure sEE pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(sEE_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MISO_PIN;
+  GPIO_Init(sEE_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MOSI_PIN;
+  GPIO_Init(sEE_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure sEE_CS_PIN pin: sEE Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(sEE_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PXx to sEE_SCK */
+  GPIO_PinAFConfig(sEE_SPI_SCK_GPIO_PORT, sEE_SPI_SCK_SOURCE, sEE_SPI_SCK_AF);
+
+  /* Connect PXx to sEE_MISO */
+  GPIO_PinAFConfig(sEE_SPI_MISO_GPIO_PORT, sEE_SPI_MISO_SOURCE, sEE_SPI_MISO_AF); 
+
+  /* Connect PXx to sEE_MOSI */
+  GPIO_PinAFConfig(sEE_SPI_MOSI_GPIO_PORT, sEE_SPI_MOSI_SOURCE, sEE_SPI_MOSI_AF);  
+  
+  /* sEE SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
+
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(sEE_SPI, &SPI_InitStructure);
+
+  SPI_RxFIFOThresholdConfig(sEE_SPI, SPI_RxFIFOThreshold_QF);
+
+  SPI_Cmd(sEE_SPI, ENABLE); /* sEE_SPI enable */
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.h
new file mode 100644
index 0000000..82a2749
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval.h
@@ -0,0 +1,442 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains definitions for STM32303C_EVAL's Leds, push-buttons
+  *          and COM ports hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32303C_EVAL_H
+#define __STM32303C_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+#include "stm32_eval_legacy.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */
+      
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{
+  BUTTON_NONE = 0,
+  BUTTON_KEY = 1,
+  BUTTON_RIGHT = 2,
+  BUTTON_LEFT = 3,
+  BUTTON_UP = 4,
+  BUTTON_DOWN = 5,
+  BUTTON_SEL = 6
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;   
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief  Define for STM32303C_EVAL board  
+  */ 
+#if !defined (USE_STM32303C_EVAL)
+ #define USE_STM32303C_EVAL
+#endif
+
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_8
+#define LED1_GPIO_PORT                   GPIOE
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOE
+  
+#define LED2_PIN                         GPIO_Pin_9
+#define LED2_GPIO_PORT                   GPIOE
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOE
+  
+#define LED3_PIN                         GPIO_Pin_10
+#define LED3_GPIO_PORT                   GPIOE
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOE
+  
+#define LED4_PIN                         GPIO_Pin_11
+#define LED4_GPIO_PORT                   GPIOE
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOE
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          6
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_6
+#define KEY_BUTTON_GPIO_PORT             GPIOE
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line6
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource6
+#define KEY_BUTTON_EXTI_IRQn             EXTI9_5_IRQn
+
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_6
+#define RIGHT_BUTTON_GPIO_PORT           GPIOD
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line6
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOD
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource6
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI9_5_IRQn
+
+/**
+ * @brief Joystick Left push-button
+ */
+#define LEFT_BUTTON_PIN                  GPIO_Pin_5
+#define LEFT_BUTTON_GPIO_PORT            GPIOB
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line5
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOB
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource5
+#define LEFT_BUTTON_EXTI_IRQn            EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_7
+#define UP_BUTTON_GPIO_PORT              GPIOE
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define UP_BUTTON_EXTI_LINE              EXTI_Line7
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource7
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Down push-button
+ */  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_5
+#define DOWN_BUTTON_GPIO_PORT            GPIOD
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOD
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line5
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOD
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource5
+#define DOWN_BUTTON_EXTI_IRQn            EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Sel push-button
+ */
+#define SEL_BUTTON_PIN                   GPIO_Pin_13
+#define SEL_BUTTON_GPIO_PORT             GPIOC
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOC
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line13
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOC
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource13
+#define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn 
+
+/**
+  * @}
+  */ 
+
+
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             1
+
+/**
+ * @brief Definition for COM port1, connected to USART1
+ */ 
+#define EVAL_COM1                        USART1
+#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
+
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_4
+#define EVAL_COM1_TX_GPIO_PORT           GPIOC
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource4
+#define EVAL_COM1_TX_AF                  GPIO_AF_7
+
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_1
+#define EVAL_COM1_RX_GPIO_PORT           GPIOE
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOE
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource1
+#define EVAL_COM1_RX_AF                  GPIO_AF_7
+
+#define EVAL_COM1_CTS_PIN                GPIO_Pin_11
+#define EVAL_COM1_CTS_GPIO_PORT          GPIOA
+#define EVAL_COM1_CTS_GPIO_CLK           RCC_AHBPeriph_GPIOA
+#define EVAL_COM1_CTS_SOURCE             GPIO_PinSource11
+#define EVAL_COM1_CTS_AF                 GPIO_AF_7
+
+#define EVAL_COM1_RTS_PIN                GPIO_Pin_12
+#define EVAL_COM1_RTS_GPIO_PORT          GPIOA
+#define EVAL_COM1_RTS_GPIO_CLK           RCC_AHBPeriph_GPIOA
+#define EVAL_COM1_RTS_SOURCE             GPIO_PinSource12
+#define EVAL_COM1_RTS_AF                 GPIO_AF_7
+   
+#define EVAL_COM1_IRQn                   USART1_IRQn
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_SD_SPI
+  * @{
+  */
+/**
+  * @brief  SD SPI Interface pins
+  */
+#define SD_SPI                           SPI2
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI2
+
+#define SD_SPI_SCK_PIN                   GPIO_Pin_9                  /* PF.09 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOF                       /* GPIOF */
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOF
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource9
+#define SD_SPI_SCK_AF                    GPIO_AF_5
+
+#define SD_SPI_MISO_PIN                  GPIO_Pin_14                  /* PB.14 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource14
+#define SD_SPI_MISO_AF                   GPIO_AF_5
+
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                  /* PB.15 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource15
+#define SD_SPI_MOSI_AF                   GPIO_AF_5
+
+#define SD_CS_PIN                        GPIO_Pin_15                  /* PE.15 */
+#define SD_CS_GPIO_PORT                  GPIOE                       /* GPIOE */
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOF
+
+   
+#define SD_DETECT_PIN                    GPIO_Pin_6                 /* PC.06 */
+#define SD_DETECT_EXTI_LINE              EXTI_Line6
+#define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource6
+#define SD_DETECT_GPIO_PORT              GPIOC                       /* GPIOC */
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOC
+#define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOC
+#define SD_DETECT_EXTI_IRQn              EXTI9_5_IRQn
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_sEE_SPI
+  * @{
+  */
+/**
+  * @brief  sEE SPI Interface pins
+  */
+#define sEE_SPI                          SPI2
+#define sEE_SPI_CLK                      RCC_APB1Periph_SPI2
+   
+#define sEE_SPI_SCK_PIN                  GPIO_Pin_9                   /* PF.09 */
+#define sEE_SPI_SCK_GPIO_PORT            GPIOF                        /* GPIOF */
+#define sEE_SPI_SCK_GPIO_CLK             RCC_AHBPeriph_GPIOF
+#define sEE_SPI_SCK_SOURCE               GPIO_PinSource9
+#define sEE_SPI_SCK_AF                   GPIO_AF_5
+
+#define sEE_SPI_MISO_PIN                 GPIO_Pin_14                  /* PB.14 */
+#define sEE_SPI_MISO_GPIO_PORT           GPIOB                        /* GPIOB */
+#define sEE_SPI_MISO_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define sEE_SPI_MISO_SOURCE              GPIO_PinSource14
+#define sEE_SPI_MISO_AF                  GPIO_AF_5
+
+#define sEE_SPI_MOSI_PIN                 GPIO_Pin_15                  /* PB.15 */
+#define sEE_SPI_MOSI_GPIO_PORT           GPIOB                        /* GPIOB */
+#define sEE_SPI_MOSI_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define sEE_SPI_MOSI_SOURCE              GPIO_PinSource15
+#define sEE_SPI_MOSI_AF                  GPIO_AF_5
+
+#define sEE_SPI_CS_PIN                   GPIO_Pin_7                  /* PD.07 */
+#define sEE_SPI_CS_GPIO_PORT             GPIOD                       /* GPIOD */
+#define sEE_SPI_CS_GPIO_CLK              RCC_AHBPeriph_GPIOD
+
+/**
+  * @brief  sEE SPI Interface Type
+  */
+#define sEE_M95M01 
+
+/**
+  * @}
+  */
+  
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  TS751 Temperature Sensor I2C Interface pins
+  */
+#define TS751_I2C                        I2C2
+#define TS751_I2C_CLK                    RCC_APB1Periph_I2C2
+
+#define TS751_I2C_SCL_PIN                GPIO_Pin_6                  /* PF.06 */
+#define TS751_I2C_SCL_GPIO_PORT          GPIOF                       /* GPIOF */
+#define TS751_I2C_SCL_GPIO_CLK           RCC_AHBPeriph_GPIOF
+#define TS751_I2C_SCL_SOURCE             GPIO_PinSource6
+#define TS751_I2C_SCL_AF                 GPIO_AF_4
+
+#define TS751_I2C_SDA_PIN                GPIO_Pin_10                  /* PA.10 */
+#define TS751_I2C_SDA_GPIO_PORT          GPIOA                       /* GPIOA */
+#define TS751_I2C_SDA_GPIO_CLK           RCC_AHBPeriph_GPIOA
+#define TS751_I2C_SDA_SOURCE             GPIO_PinSource10
+#define TS751_I2C_SDA_AF                 GPIO_AF_4
+
+#define TS751_I2C_SMBUSALERT_PIN         GPIO_Pin_8                  /* PA.08 */
+#define TS751_I2C_SMBUSALERT_GPIO_PORT   GPIOA                       /* GPIOA */
+#define TS751_I2C_SMBUSALERT_GPIO_CLK    RCC_AHBPeriph_GPIOA
+#define TS751_I2C_SMBUSALERT_SOURCE      GPIO_PinSource8
+#define TS751_I2C_SMBUSALERT_AF          GPIO_AF_4
+
+/**
+  * @}
+  */
+   
+/** @addtogroup STM32303C_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+#define sEE_I2C                          I2C2
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C2
+   
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PF.06 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOF                       /* GPIOF */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOF
+#define sEE_I2C_SCL_SOURCE               GPIO_PinSource6
+#define sEE_I2C_SCL_AF                   GPIO_AF_4
+
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_10                  /* PA.10 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOA                       /* GPIOA */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOA
+#define sEE_I2C_SDA_SOURCE               GPIO_PinSource10
+#define sEE_I2C_SDA_AF                   GPIO_AF_4
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32303C_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void TS751_LowLevel_DeInit(void);
+void TS751_LowLevel_Init(void);
+void sEE_SPI_LowLevel_DeInit(void);
+void sEE_SPI_LowLevel_Init(void);
+void sEE_I2C_LowLevel_DeInit(void);
+void sEE_I2C_LowLevel_Init(void); 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32303C_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.c
new file mode 100644
index 0000000..9d0991d
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.c
@@ -0,0 +1,1597 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_audio_codec.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file includes the low layer driver for CS42L52 Audio Codec
+  *          available on STM32303C_EVAL evaluation board(MB1019).  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*==============================================================================================================================
+                                             User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver supports STM32F30x devices on STM32303C_EVAL (MB1019) Evaluation boards.
+
+   - Configure the options in file stm32303c_eval_audio_codec.h in the section CONFIGURATION.
+      Refer to the sections 2 and 3 to have more details on the possible configurations.
+
+   - Call the function EVAL_AUDIO_Init(
+                                    OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, 
+                                                 OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or 
+                                                 OUTPUT_DEVICE_BOTH)
+                                    Volume: initial volume to be set (0 is min (mute), 100 is max (100%)
+                                    AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...)
+                                     this parameter is relative to the audio file/stream type.
+                                   )
+      This function configures all the hardware required for the audio application (codec, I2C, I2S, 
+      GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK.
+      if the returned value is different from 0 or the function is stuck then the communication with
+      the codec has failed (try to un-plug the power or reset device in this case).
+      + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream.
+      + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream.
+      + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented 
+         into the audio jack on the evaluation board). When the Headphone is connected it is used
+         as output. When the headphone is disconnected from the audio jack, the output is
+         automatically switched to Speaker.
+      + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream
+         at the same time.
+
+   - Call the function EVAL_AUDIO_Play(
+                                  pBuffer: pointer to the audio data file address
+                                  Size: size of the buffer to be sent in Bytes
+                                 )
+      to start playing (for the first time) from the audio file/stream.
+
+   - Call the function EVAL_AUDIO_PauseResume(
+                                         Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or 
+                                               any value different from 0) to resume playing.
+                                         )
+       Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called
+          for resume (it is not allowed to call EVAL_AUDIO_Play() in this case).
+       Note. This function should be called only when the audio file is played or paused (not stopped).
+
+   - For each mode, you may need to implement the relative callback functions into your code.
+      The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in 
+      the stm32303c_eval_audio_codec.h file. (refer to the example for more details on the callbacks implementations)
+
+   - To Stop playing, to modify the volume level or to mute, use the functions
+       EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute().
+
+   - The driver API and the callback functions are at the end of the stm32303c_eval_audio_codec.h file.
+ 
+
+ Driver architecture:
+ --------------------
+ This driver is composed of three main layers:
+   o High Audio Layer: consists of the function API exported in the stm32303c_eval_audio_codec.h file
+     (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...)
+   o Codec Control layer: consists of the functions API controlling the audio codec (CS42L52) and 
+     included as local functions in file stm32303c_eval_audio_codec.c (Codec_Init(), Codec_Play() ...)
+   o Media Access Layer (MAL): which consists of functions allowing to access the media containing/
+     providing the audio file/stream. These functions are also included as local functions into
+     the stm32303c_eval_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...)
+  Each set of functions (layer) may be implemented independently of the others and customized when 
+  needed.    
+
+2. Modes description:
+---------------------
+     + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location.
+     + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a 
+        memory location or from a device at real time (double buffer could be used).
+
+3. DMA interrupts description:
+------------------------------
+     + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has finished the transfer.
+     + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has reached the half of the buffer transfer (generally, it is useful 
+        to load the first half of buffer while DMA is loading from the second half).
+     + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer.
+
+4. Known Limitations:
+---------------------
+   1- When using the Speaker, if the audio file quality is not high enough, the speaker output
+      may produce high and uncomfortable noise level. To avoid this issue, to use speaker
+      output properly, try to increase audio file sampling rate (typically higher than 48KHz).
+      This operation will lead to larger file size.
+   2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some
+      user interrupt routines (in this case, interrupts could be disabled just before the start of 
+      communication then re-enabled when it is over). Note that this communication is only done at
+      the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is 
+      performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is 
+      required with the audio codec.
+  3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, 
+     File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.
+  4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice 
+     on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing).
+  5- Supports only 16-bit audio data size.
+===============================================================================================================================*/
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval_audio_codec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32303C_EVAL_AUDIO_CODEC
+  * @brief       This file includes the low layer driver for CS42L52 Audio Codec
+  *              available on STM32303C_EVAL evaluation board(MB1019).
+  * @{
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Defines
+  * @{
+  */ 
+
+/* Mask for the bit EN of the I2S CFGR register */
+#define I2S_ENABLE_MASK                 0x0400
+
+/* Delay for the Codec to be correctly reset */
+#define CODEC_RESET_DELAY               0x4FFF
+
+/* Codec audio Standards */
+#ifdef I2S_STANDARD_PHILLIPS
+ #define  CODEC_STANDARD                0x04
+ #define I2S_STANDARD                   I2S_Standard_Phillips         
+#elif defined(I2S_STANDARD_MSB)
+ #define  CODEC_STANDARD                0x00
+ #define I2S_STANDARD                   I2S_Standard_MSB    
+#elif defined(I2S_STANDARD_LSB)
+ #define  CODEC_STANDARD                0x08
+ #define I2S_STANDARD                   I2S_Standard_LSB    
+#else 
+ #error "Error: No audio communication standard selected !"
+#endif /* I2S_STANDARD */
+
+/* The 7 bits Codec address (sent through I2C interface) */
+#define CODEC_ADDRESS                   0x94  /* b1001010. */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Variables
+  * @{
+  */
+/* This structure is declared global because it is handled by two different functions */
+DMA_InitTypeDef DMA_InitStructure; 
+DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure;
+
+uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */
+uint32_t AudioRemSize   = 0xFFFF; /* This variable holds the remaining data in audio file */
+uint16_t *CurrentPos;             /* This variable holds the current position of audio pointer */
+
+__IO uint32_t  CODECTimeout = CODEC_LONG_TIMEOUT;   
+__IO uint8_t OutputDev = 0;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Private_Functions
+  * @{
+  */ 
+
+/*----------------------------------------------------------------------------
+                           Audio Codec functions 
+  ----------------------------------------------------------------------------*/
+/* High Layer codec functions */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+static uint32_t Codec_DeInit(void);
+static uint32_t Codec_Play(void);
+static uint32_t Codec_PauseResume(uint32_t Cmd);
+static uint32_t Codec_Stop(uint32_t Cmd);
+static uint32_t Codec_VolumeCtrl(uint8_t Volume);
+static uint32_t Codec_Mute(uint32_t Cmd);
+/* Low layer codec functions */
+static void     Codec_CtrlInterface_Init(void);
+static void     Codec_CtrlInterface_DeInit(void);
+static void     Codec_AudioInterface_Init(uint32_t AudioFreq);
+static void     Codec_AudioInterface_DeInit(void);
+uint32_t Codec_ReadRegister(uint8_t RegisterAddr);
+static void     Codec_GPIO_Init(void);
+static void     Codec_GPIO_Recorder_Init(void);
+static void     Codec_GPIO_DeInit(void);
+static void     Delay(__IO uint32_t nCount);
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                   MAL (Media Access Layer) functions 
+  ----------------------------------------------------------------------------*/
+/* Peripherals configuration functions */
+static void     Audio_MAL_Init(void);
+static void     Audio_MAL_DeInit(void);
+static void     Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr);
+static void     Audio_MAL_Stop(void);
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief  Configure the audio peripherals.
+  * @param  OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{    
+  /* Perform low layer Codec initialization */
+  if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0)
+  {
+    return 1;                
+  }
+  else
+  {    
+    /* I2S data transfer preparation:
+    Prepare the Media to be used for the audio transfer from memory to I2S peripheral */
+    Audio_MAL_Init();
+    
+    /* Return 0 when all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Deinitializes all the resources used by the codec (those initialized
+  *         by EVAL_AUDIO_Init() function). 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_DeInit(void)
+{ 
+  /* DeInitialize Codec */  
+  Codec_DeInit();  
+  
+  /* DeInitialize the Media layer */
+  Audio_MAL_DeInit();
+  
+  return 0;
+}
+
+/**
+  * @brief  Starts playing audio stream from a data buffer for a determined size. 
+  * @param  pBuffer: Pointer to the buffer 
+  * @param  Size: Number of audio data BYTES.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size)
+{
+  /* Set the total number of data to be played (count in half-word) */
+  AudioTotalSize = Size/2;
+
+  /* Call the audio Codec Play function */
+  Codec_Play();
+  
+  /* Update the Media layer and enable it for play */  
+  Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2)));
+  
+  /* Update the remaining number of data to be played */
+  AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize);
+  
+  /* Update the current audio pointer position */
+  CurrentPos = pBuffer + DMA_MAX(AudioTotalSize);
+  
+  return 0;
+}
+
+/**
+  * @brief  This function Pauses or Resumes the audio file stream. In case
+  *         of using DMA, the DMA Pause feature is used. In all cases the I2S 
+  *         peripheral is disabled. 
+  * 
+  * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only
+  *          this function should be called for resume (use of EVAL_AUDIO_Play() 
+  *          function for resume could lead to unexpected behavior).
+  * 
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd)
+{    
+  /* Call the Audio Codec Pause/Resume function */
+  if (Codec_PauseResume(Cmd) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call the Media layer pause/resume function */
+    Audio_MAL_PauseResume(Cmd, 0);
+    
+    /* Return 0 if all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Stops audio playing and Power down the Audio Codec. 
+  * @param  Option: could be one of the following parameters 
+  *           - CODEC_PDWN_SW: for software power off (by writing registers). 
+  *                            Then no need to reconfigure the Codec after power on.
+  *           - CODEC_PDWN_HW: completely shut down the codec (physically). 
+  *                            Then need to reconfigure the Codec after power on.  
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Stop(uint32_t Option)
+{
+  /* Call Audio Codec Stop function */
+  if (Codec_Stop(Option) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call Media layer Stop function */
+    Audio_MAL_Stop();
+    
+    /* Update the remaining data number */
+    AudioRemSize = AudioTotalSize;    
+    
+    /* Return 0 when all operations are correctly done */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Controls the current audio volume level. 
+  * @param  Volume: Volume level to be set in percentage from 0% to 100% (0 for 
+  *         Mute and 100 for Max volume level).
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume)
+{
+  /* Call the codec volume control function with converted volume value */
+  return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume)));
+}
+
+/**
+  * @brief  Enables or disables the MUTE mode by software 
+  * @param  Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to 
+  *         unmute the codec and restore previous volume level.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Mute(uint32_t Cmd)
+{ 
+  /* Call the Codec Mute function */
+  return (Codec_Mute(Cmd));
+}
+
+/**
+  * @brief  This function handles main Media layer interrupt. 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+void Audio_MAL_IRQHandler(void)
+{    
+#ifndef AUDIO_MAL_MODE_NORMAL
+  uint16_t *pAddr = (uint16_t *)CurrentPos;
+  uint32_t Size = AudioRemSize;
+#endif /* AUDIO_MAL_MODE_NORMAL */
+  
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+  /* Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TC) != RESET)
+  {     
+ #ifdef AUDIO_MAL_MODE_NORMAL
+    /* Check if the end of file has been reached */
+    if (AudioRemSize > 0)
+    {      
+      /* Wait the DMA Channel to be effectively disabled */
+      while (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TC) != SET)
+      {}
+      
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);  
+      
+      /* Re-Configure the buffer address and size */
+      DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) CurrentPos;
+      DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize));
+      
+      /* Configure the DMA Channel with the new parameters */
+      DMA_Init(AUDIO_MAL_DMA_CHANNEL , &DMA_InitStructure);
+      
+      /* Enable the I2S DMA Channel */
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL , ENABLE);    
+      
+      /* Update the current pointer position */
+      CurrentPos += DMA_MAX(AudioRemSize);        
+      
+      /* Update the remaining number of data to be played */
+      AudioRemSize -= DMA_MAX(AudioRemSize);    
+    }
+    else
+    {
+      /* Disable the I2S DMA Channel */
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL , DISABLE);   
+      
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);       
+      
+      /* Manage the remaining file size and new address offset: This function 
+      should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+      EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0);       
+    }
+    
+ #elif defined(AUDIO_MAL_MODE_CIRCULAR)
+    /* Manage the remaining file size and new address offset: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_TransferComplete_CallBack(pAddr, Size);    
+    
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC);
+ #endif /* AUDIO_MAL_MODE_NORMAL */  
+  }
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+
+#ifdef AUDIO_MAL_DMA_IT_HT_EN  
+  /* Half Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_HT) != RESET)
+  {
+    /* Manage the remaining file size and new address offset: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size);    
+   
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_HT);    
+  }
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+  
+#ifdef AUDIO_MAL_DMA_IT_TE_EN  
+  /* FIFO Error interrupt */
+  if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_TE) != RESET) || \
+     (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_FE) != RESET) || \
+     (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_DME) != RESET))
+    
+  {
+    /* Manage the error generated on DMA FIFO: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr);    
+    
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_TE | AUDIO_MAL_DMA_FLAG_FE | \
+                                        AUDIO_MAL_DMA_FLAG_DME);
+  }  
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+}
+
+/*============================================================================
+                CS42L52 Audio Codec Control Functions
+  ============================================================================*/
+/**
+  * @brief  Initializes the audio codec and all related interfaces (control 
+  *         interface: I2C and audio interface: I2S)
+  * @param  OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{
+  uint32_t counter = 0; 
+
+  /* Configure the Codec related IOs */
+  Codec_GPIO_Init();   
+
+  /* Initialize the Control interface of the Audio Codec */
+  Codec_CtrlInterface_Init();     
+  
+  /* Keep Codec powered OFF */
+  counter += Codec_WriteRegister(0x02, 0x9E/*0x01*/);  
+
+  switch (OutputDevice)
+  {
+    case OUTPUT_DEVICE_SPEAKER:
+      counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+      OutputDev = 0xFA;
+      break;
+      
+    case OUTPUT_DEVICE_HEADPHONE:
+      counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+      OutputDev = 0xAF;
+      break;
+      
+    case OUTPUT_DEVICE_BOTH:
+      counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+      OutputDev = 0xAA;
+      break;
+      
+    case OUTPUT_DEVICE_AUTO:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+      
+    default:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+  }
+  
+  /* Clock configuration: Auto detection */  
+  counter += Codec_WriteRegister(0x05, 0x80);
+  /* Set the Slave Mode and the audio Standard */  
+  counter += Codec_WriteRegister(0x06, 0x03/*CODEC_STANDARD*/);  
+  /* Interface Control 2: SCLK is Re-timed signal from MCLK*/
+  counter +=Codec_WriteRegister(0x07, 0x00); 
+  /* ADCA and PGAA Select: no input selected*/
+  counter +=Codec_WriteRegister(0x08, 0x00);
+  /* ADCB and PGAB Select: no input selected*/
+  counter +=Codec_WriteRegister(0x09, 0x00); 
+  /*Play Back Control 1: headphone gain is 0.4, PCM not inverted, Master not mute*/
+  counter +=Codec_WriteRegister(0x0D, 0x10);/* CS42L52 has different config than CS42L52*/ 
+  /* Miscellaneous Controls: Passthrough Analog & Passthrough Mute off, Soft Ramp on @0x0E*/
+  counter +=Codec_WriteRegister(0x0E, 0x02);  
+  /* Play Back Control 2: Headphone Mute off, speaker mute off, mono enabled */
+  counter +=Codec_WriteRegister(0x0F, 0x32); 
+  /* PCM A Volume: PCM Mute disabled, Volume is 0db(default) */
+  counter +=Codec_WriteRegister(0x1A, 0x00);
+  /* PCM B Volume: PCM Mute disabled, Volume is 0db(default) */
+  counter +=Codec_WriteRegister(0x1B, 0x00); 
+  /* Headphone A Volume: Headphone Volume is -6db */
+  counter +=Codec_WriteRegister(0x22, (u8)(0-12));
+  /* Headphone B Volume: Headphone Volume is -6db */
+  counter +=Codec_WriteRegister(0x23, (u8)(0-12));    
+  /* Speaker A Volume: Speaker Volume is 0db (default) */
+  counter +=Codec_WriteRegister(0x24, 0x00);
+  /* Speaker B Volume: Speaker Volume is 0db (default) */
+  counter +=Codec_WriteRegister(0x25, 0x00);
+  /* Charge Pump Frequency: 5 (default) */
+  counter +=Codec_WriteRegister(0x34, 5<<4);
+  /* Power Control 1: power up */
+  counter += Codec_WriteRegister(0x02, 0x00); 
+  counter += Codec_WriteRegister(0x20, 0xff); 
+  counter += Codec_WriteRegister(0x21, 0xff); 
+
+  /* Configure the I2S peripheral */
+  Codec_AudioInterface_Init(AudioFreq);  
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Initializes the audio codec and all related interfaces (control 
+  *         interface: I2C and audio interface: I2S)
+  * @param  OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t Codec_Record_Init(void)
+{
+  uint32_t counter = 0; 
+
+  /* Configure the Codec related IOs */
+  Codec_GPIO_Recorder_Init();   
+  
+  /* Initialize the Control interface of the Audio Codec */
+  Codec_CtrlInterface_Init();     
+  
+  /* Mono Record @ MIC1+ with Bias */
+  /* Power Control 2[@03h]: MICB Off, MIC A & Bias On */
+  counter += Codec_WriteRegister(0x03, 0x04);
+  /* Power Control 3[@04h]: headphone A/B Off, speaker A & B Off */
+  counter += Codec_WriteRegister(0x04, 0xFF);
+  /* Clocking Control: auto sample rate(Fs) */
+  counter += Codec_WriteRegister(0x05, 0x80);
+  /* Interface Control 1: slave, LeftJustified, 16-bit data */
+  counter += Codec_WriteRegister(0x06, 0x03);
+  /* Interface Control 2: SCLK is Re-timed signal from MCLK, BIAS: 0.5*VA */
+  counter += Codec_WriteRegister(0x07, 0x00);
+  /* ADCA and PGAA Select: MICx selected */
+  counter += Codec_WriteRegister(0x08, 0x90);
+  /* ADCB and PGAB Select: MICx selected */
+  counter += Codec_WriteRegister(0x09, 0x90);
+  /* Misc ADC Control: SDOUT Signal Source is ADC_or_DSP */
+  counter += Codec_WriteRegister(0x0C, 0x00);
+  /* Play Back Control 1: headphone gain is 0.4, PCM not inverted, Master not mute */
+  counter += Codec_WriteRegister(0x0D, 0x00);
+  /* Miscellaneous Controls: Passthrough Analog & Passthrough Mute off, Soft Ramp on @0x0E */
+  counter += Codec_WriteRegister(0x0E, 0x02);
+  /* Play Back Control 2: Headphone Mute on, speaker mute off, mono enabled */
+  counter += Codec_WriteRegister(0x0F, 0xC2);
+  /* MICA Amp Control: select MIC 2x, Single-Ended, Gain=16db */
+  counter += Codec_WriteRegister(0x10, 0x2E);
+  /* MICB Amp Control: select MIC 2x, Single-Ended, Gain=16db */
+  counter += Codec_WriteRegister(0x11, 0x40);
+  /* MICB Amp Control: try with Differential, Gain=16db */
+  counter += Codec_WriteRegister(0x11, 0x20);
+  /* PGA Volume ALC Control: Gain=0db */
+  counter += Codec_WriteRegister(0x12, 0x00);
+  /* PGA Volume ALC Control: Gain=0db */
+  counter += Codec_WriteRegister(0x13, 0x00); 
+  counter += Codec_WriteRegister(0x34, 5<<4);
+  
+  counter += Codec_WriteRegister(0x02, 0x14);
+  
+  /* Return communication control value */
+  return counter;  
+    
+}
+
+/**
+  * @brief  Restore the audio codec state to default state and free all used 
+  *         resources.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_DeInit(void)
+{
+  uint32_t counter = 0; 
+  uint16_t i = 0;
+  uint8_t tmp = 0; 
+  
+  /* Enable Master Playback Mute @0x0D */
+  counter += Codec_WriteRegister(0x02, 0x03);
+  /* Power down CS42L52 @0x03 */
+  counter += Codec_WriteRegister(0x03, 0x07);
+  /* Power down CS42L52 @0x04 */
+  counter += Codec_WriteRegister(0x04, 0xFF);
+  /* config interface @0x06 */
+  counter += Codec_WriteRegister(0x06, 0x03);  
+  /* Disable Analog (Soft Ramp & Zero Cross) and HighPassFilter @0x0A */
+  counter += Codec_WriteRegister(0x0A, 0x00);
+  /* Digital Soft Ramp on & Zero Cross off @0x0E */
+  counter += Codec_WriteRegister(0x0E, 0x02);
+  /* Headphone Mute, Speaker Mute @0x0F */
+  counter += Codec_WriteRegister(0x0F, 0xF2);  
+  /* PCM A Volume: Mute @0x1A */
+  counter += Codec_WriteRegister(0x1A, 0x80);
+  /* PCM B Volume: Mute @0x1B */
+  counter += Codec_WriteRegister(0x1B, 0x80);
+  /* Limiter Attack Rate: 0x00 @0x29 */
+  counter += Codec_WriteRegister(0x29, 0x00);
+  
+  i = 0;
+  do{
+  // Power down CS42L52 @0x02
+  counter += Codec_WriteRegister(0x02, 0x9F);
+  tmp = Codec_ReadRegister(0x02);
+  i++;
+  }
+  while (((tmp & 0x01) == 0) && (i < 10));
+   
+  Delay(CODEC_RESET_DELAY);
+  
+  /* Deinitialize all use GPIOs */
+  Codec_GPIO_DeInit();
+  
+  /* Deinitialize the Codec audio interface (I2S) */
+  Codec_AudioInterface_DeInit(); 
+  /* Disable the Codec control interface */
+  Codec_CtrlInterface_DeInit();
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Start the audio Codec play feature.
+  * @note   For this codec no Play options are required.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Play(void)
+{
+  /* 
+     No actions required on Codec level for play command
+     */  
+
+  /* Return communication control value */
+  return 0;  
+}
+
+/**
+  * @brief  Pauses and resumes playing on the audio codec.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_PauseResume(uint32_t Cmd)
+{
+  uint32_t counter = 0;   
+  
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  { 
+    /* Mute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_ON);
+
+    /* Put the Codec in Power save mode */    
+    counter += Codec_WriteRegister(0x02, 0x01); 
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Unmute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_OFF);
+    
+    counter += Codec_WriteRegister(0x04, OutputDev);
+    
+    /* Exit the Power save mode */
+    counter += Codec_WriteRegister(0x02, 0x9E); 
+
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Stops audio Codec playing. It powers down the codec.
+  * @param  CodecPdwnMode: selects the  power down mode.
+  *          - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this 
+  *                           mode the codec keeps the previous initialization
+  *                           (no need to re-Initialize the codec registers).
+  *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
+  *                           mode, the codec is set to default configuration 
+  *                           (user should re-Initialize the codec in order to 
+  *                            play again the audio stream).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Stop(uint32_t CodecPdwnMode)
+{
+  uint32_t counter = 0;   
+
+  /* Mute the output first */
+  Codec_Mute(AUDIO_MUTE_ON);
+  
+  if (CodecPdwnMode == CODEC_PDWN_SW)
+  {    
+    /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
+    counter += Codec_WriteRegister(0x02, 0x9F);
+  }
+  else /* CODEC_PDWN_HW */
+  { 
+    /* Power down the components */
+    counter += Codec_WriteRegister(0x02, 0x9F);
+
+    /* Wait at least 100us */
+    Delay(0xFFF);
+  }  
+  return counter;    
+}
+
+/**
+  * @brief  Sets higher or lower the codec volume level.
+  * @param  Volume: a byte value from 0 to 255 (refer to codec registers 
+  *         description for more details).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_VolumeCtrl(uint8_t Volume)
+{
+  uint32_t counter = 0;
+  
+  if (Volume > 0xE6)
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume - 0xE7); 
+    counter += Codec_WriteRegister(0x21, Volume - 0xE7);     
+  }
+  else
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume + 0x19); 
+    counter += Codec_WriteRegister(0x21, Volume + 0x19); 
+  }
+
+  return counter;  
+}
+
+/**
+  * @brief  Enables or disables the mute feature on the audio codec.
+  * @param  Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
+  *             mute mode.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Mute(uint32_t Cmd)
+{
+  uint32_t counter = 0;  
+  
+  /* Set the Mute mode */
+  if (Cmd == AUDIO_MUTE_ON)
+  {
+    counter += Codec_WriteRegister(0x04, 0xFF);
+    counter += Codec_WriteRegister(0x0F, 0xF0);
+  }
+  else /* AUDIO_MUTE_OFF Disable the Mute */
+  {
+    counter += Codec_WriteRegister(0x04, 0x05);
+    counter += Codec_WriteRegister(0x0F, 0x02);
+  }
+  
+  return counter; 
+}
+
+/**
+  * @brief  Switch dynamically (while audio file is played) the output target 
+  *         (speaker or headphone).
+  * @note   This function modifies a global variable of the audio codec driver: OutputDev.
+  * @param  Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
+  *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t Codec_SwitchOutput(uint8_t Output)
+{
+  uint8_t counter = 0;
+  
+  switch (Output) 
+  {
+    case OUTPUT_DEVICE_SPEAKER:
+      counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+      OutputDev = 0xFA;
+      break;
+      
+    case OUTPUT_DEVICE_HEADPHONE:
+      counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+      OutputDev = 0xAF;
+      break;
+      
+    case OUTPUT_DEVICE_BOTH:
+      counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+      OutputDev = 0xAA;
+      break;
+      
+    case OUTPUT_DEVICE_AUTO:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+      
+    default:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;
+  }
+  
+  return counter;
+}
+
+/**
+  * @brief  Writes a Byte to a given register into the audio codec through the 
+            control interface (I2C)
+  * @param  RegisterAddr: The address (location) of the register to be written.
+  * @param  RegisterValue: the Byte value to be written into destination register.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t result = 0;
+  
+  /* Test on BUSY Flag */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_BUSY) != RESET) 
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 2, I2C_AutoEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;  
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterAddr );
+    
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }  
+  
+  /* Write data to TXDR */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterValue);
+  
+  /* Wait until STOPF flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(CODEC_I2C, I2C_ICR_STOPCF);
+
+#ifdef VERIFY_WRITTENDATA
+  /* Verify that the data has been correctly written */  
+  result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1;
+#endif /* VERIFY_WRITTENDATA */
+
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return result;
+}
+
+/**
+  * @brief  Reads and returns the value of an audio codec register through the
+  *         control interface (I2C).
+  * @param  RegisterAddr: Address of the register to be read.
+  * @retval Value of the register to be read or dummy value if the communication
+  *         fails.
+  */
+uint32_t Codec_ReadRegister(uint8_t RegisterAddr)
+{
+   uint32_t result = 0;
+  
+  /* Test on BUSY Flag */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterAddr);
+  
+  /* Wait until TC flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }  
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_RXNE) == RESET)  
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Read data from RXDR */
+  result = I2C_ReceiveData(CODEC_I2C);  
+  
+  /* Wait until STOPF flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_STOPF) == RESET) 
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(CODEC_I2C, I2C_ICR_STOPCF);
+
+  /* Return the byte read from Codec */
+  return result;
+}
+
+/**
+  * @brief  Initializes the Audio Codec control interface (I2C).
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_Init(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+  
+  /* Enable the CODEC_I2C peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE);
+  
+  /* CODEC_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Disable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = CODEC_I2C_TIMING;
+  
+  /* Enable the I2C peripheral */  
+  I2C_Init(CODEC_I2C, &I2C_InitStructure);
+  I2C_Cmd(CODEC_I2C, ENABLE);
+   
+}
+
+/**
+  * @brief  Restore the Audio Codec control interface to its default state.
+  *         This function doesn't de-initialize the I2C because the I2C peripheral
+  *         may be used by other modules.
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_DeInit(void)
+{
+  /* Disable the I2C peripheral */ /* This step is not done here because 
+     the I2C interface can be used by other modules */
+   /*I2C_DeInit(CODEC_I2C); */
+}
+
+/**
+  * @brief  Initializes the Audio Codec audio interface (I2S)
+  * @note   This function assumes that the I2S input clock (through PLL_R in 
+  *         Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
+  *         is already configured and ready to be used.    
+  * @param  AudioFreq: Audio frequency to be configured for the I2S peripheral. 
+  * @retval None
+  */
+static void Codec_AudioInterface_Init(uint32_t AudioFreq)
+{
+  I2S_InitTypeDef I2S_InitStructure;
+
+  /* Enable the CODEC_I2S peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
+  
+  /* Deinitialize SPI3_I2S3 peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+   
+  /* CODEC_I2S peripheral configuration */
+  SPI_I2S_DeInit(CODEC_I2S);
+  I2S_InitStructure.I2S_AudioFreq = AudioFreq;
+  I2S_InitStructure.I2S_Standard = I2S_Standard_MSB;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+#ifdef CODEC_MCLK_ENABLED
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
+#elif defined(CODEC_MCLK_DISABLED)
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+#else
+ #error "No selection for the MCLK output has been defined !"
+#endif /* CODEC_MCLK_ENABLED */
+
+  /* Initialize the I2S peripheral with the structure above */
+  I2S_Init(CODEC_I2S, &I2S_InitStructure);
+
+  /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function 
+       or by user functions if DMA mode not enabled */ 
+}
+
+/**
+  * @brief  Restores the Audio Codec audio interface to its default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_AudioInterface_DeInit(void)
+{
+  /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+  
+  /* Deinitialize the CODEC_I2S peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+  
+  /* Disable the CODEC_I2S peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, DISABLE); 
+}
+
+/**
+  * @brief Initializes IOs used by the Audio Codec (on the control and audio 
+  *        interfaces).
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  NVIC_InitTypeDef  NVIC_InitStructure;
+  I2S_InitTypeDef I2S_InitStructure;
+  
+  /* Enable I2S and I2C GPIO clocks */
+  RCC_AHBPeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE);
+  
+  /* Connect pins to I2C peripheral */
+  GPIO_PinAFConfig(CODEC_I2C_SCL_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2C_SDA_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF);
+  
+  /* CODEC_I2C SCL and SDA pins configuration ----------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SDA_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(CODEC_I2C_SDA_GPIO, &GPIO_InitStructure);     
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN ;
+  GPIO_Init(CODEC_I2C_SCL_GPIO, &GPIO_InitStructure); 
+     
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DIN_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DOUT_PINSRC, CODEC_I2S_GPIO_AF);
+  
+  /* CODEC_I2S pins configuration: WS, SCK, DIN and DOUT pins -------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_DIN_PIN | CODEC_I2S_DOUT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);
+
+ #ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins configuration: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);   
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_MCK_GPIO_AF); 
+ #endif /* CODEC_MCLK_ENABLED */  
+  
+  /* SPI3/I2S3 IRQ Channel configuration */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
+  
+  NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+    
+  /* Deinitialize SPI3_I2S3 peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+  /* I2S3 configuration ---------------------------------------//
+   SPI3_I2S3 - configured as follow:
+        - Work as Master & (transmiter) Rx
+        - 16bit data
+        - (Disable) Output MCLK
+        - Audio sample rate: 11kHz(have to use 8k/24k for CS42L52 ?)
+        - Default clock polarity: low level */
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+  I2S_InitStructure.I2S_Standard = I2S_Standard_MSB;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
+  I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_32k;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_Init(CODEC_I2S, &I2S_InitStructure);
+  /* Disable the I2S3 TXE Interrupt */
+  SPI_I2S_ITConfig(CODEC_I2S, SPI_I2S_IT_TXE, DISABLE); 
+  /* Enable the SPI3/I2S3 peripheral */
+  I2S_Cmd(CODEC_I2S, ENABLE);
+
+}
+
+/**
+  * @brief Initializes IOs used by the Audio Codec (on the control and audio 
+  *        interfaces).
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_Recorder_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+  I2S_InitTypeDef I2S_InitStructure;
+  
+  /* Enable I2S and I2C GPIO clocks */
+  RCC_AHBPeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE);
+  
+  /* Connect pins to I2C peripheral */
+  GPIO_PinAFConfig(CODEC_I2C_SCL_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2C_SDA_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF);
+  
+  /* CODEC_I2C SCL and SDA pins configuration ----------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SDA_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(CODEC_I2C_SDA_GPIO, &GPIO_InitStructure);     
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN ;
+  GPIO_Init(CODEC_I2C_SCL_GPIO, &GPIO_InitStructure); 
+  
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DIN_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DOUT_PINSRC, CODEC_I2S_GPIO_AF);
+  
+  /* CODEC_I2S pins configuration: WS, SCK, DIN and DOUT pins -------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_DIN_PIN | CODEC_I2S_DOUT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);
+  
+ #ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins configuration: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);   
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_MCK_GPIO_AF); 
+ #endif /* CODEC_MCLK_ENABLED */   
+  
+  
+  /* SPI3/I2S3 IRQ Channel configuration */
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
+
+  NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+    
+  /* Deinitialize SPI3_I2S3 peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+  /* I2S3 configuration ---------------------------------------//
+   SPI3_I2S3 - configured as follow:
+        - Work as Master & (transmiter) Rx
+        - 16bit data
+        - (Disable) Output MCLK
+        - Audio sample rate: 11kHz(have to use 8k/24k for CS42L52)
+        - Default clock polarity: low level */
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+  I2S_InitStructure.I2S_Standard = I2S_Standard_MSB;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
+  I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_8k;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_Init(CODEC_I2S, &I2S_InitStructure);
+  /* configure Full Duplex */
+  I2S_FullDuplexConfig(I2S3ext, &I2S_InitStructure);
+  /* Disable the I2S3 TXE Interrupt */
+  SPI_I2S_ITConfig(CODEC_I2S, SPI_I2S_IT_TXE, DISABLE); 
+  /* Enable the SPI3/I2S3 peripheral */
+  I2S_Cmd(CODEC_I2S, ENABLE);
+  I2S_Cmd(I2S3ext, ENABLE);
+}
+
+/**
+  * @brief  Restores the IOs used by the Audio Codec interface to their default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_DeInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Deinitialize all the GPIOs used by the driver (EXCEPT the I2C IOs since 
+     they are used by the IOExpander as well) */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_DIN_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);     
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);
+
+#ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins deinitialization: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; 
+  GPIO_Init(CODEC_I2S_MCK_WS_GPIO, &GPIO_InitStructure);   
+  /* Disconnect pins from I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_MCK_PINSRC, 0x00); 
+#endif /* CODEC_MCLK_ENABLED */ 
+  
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_DOUT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+  
+  /* Disconnect pins from I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_WS_GPIO, CODEC_I2S_WS_PINSRC, 0x00);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, 0x00);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DIN_PINSRC, 0x00);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_DOUT_PINSRC, 0x00);
+}
+
+/**
+  * @brief  Inserts a delay time (not accurate timing).
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+void Delay( __IO uint32_t nCount)
+{
+  for (; nCount != 0; nCount--);
+}
+
+#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
+/**
+  * @brief  Basic management of the timeout situation.
+  * @param  None
+  * @retval None
+  */
+uint32_t Codec_TIMEOUT_UserCallback(void)
+{
+  /* The following code allows I2C error recovery and return to normal communication
+     if the error source doesn’t still exist (ie. hardware issue..) */
+  I2C_InitTypeDef I2C_InitStructure;
+
+  
+  /* LCD_ErrLog("> I2C Timeout error occurred\n"); */  
+  I2C_GenerateSTOP(CODEC_I2C, ENABLE);
+  /* Generated a Software reset */
+  I2C_SoftwareResetCmd(CODEC_I2C);
+  
+  /* CODEC_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Disable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = CODEC_I2C_TIMING;
+  
+  /* Enable the I2C peripheral */  
+  I2C_Init(CODEC_I2C, &I2C_InitStructure);
+  I2C_Cmd(CODEC_I2C, ENABLE);
+
+  /* At this stage the I2C error should be recovered and device can communicate
+     again (except if the error source still exist).
+     User can implement mechanism (ex. test on max trial number) to manage situation
+     when the I2C can't recover from current error. */
+
+  /* LCD_UsrLog("> I2C error recovered.\n"); */
+
+  return 0;
+}
+#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
+
+/*============================================================================
+                Audio MAL Interface Control Functions
+  ============================================================================*/
+
+/**
+  * @brief  Initializes and prepares the Media to perform audio data transfer 
+  *         from Media to the I2S peripheral.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Init(void)  
+{   
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;
+#endif
+  
+  /* Enable the DMA clock */
+  RCC_AHBPeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE); 
+    
+  /* Configure the DMA Channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+  /* Set the parameters to be configured */
+ 
+  DMA_InitStructure.DMA_PeripheralBaseAddr = CODEC_I2S_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;      /* This field will be configured in play function */
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;      /* This field will be configured in play function */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
+  DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; 
+#ifdef AUDIO_MAL_MODE_NORMAL
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+#elif defined(AUDIO_MAL_MODE_CIRCULAR)
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+#else
+  #error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
+#endif /* AUDIO_MAL_MODE_NORMAL */  
+  DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);  
+
+  /* Enable the selected DMA interrupts (selected in "stm32_eval_audio_codec.h" defines) */
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+#ifdef AUDIO_MAL_DMA_IT_HT_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_HT, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+#ifdef AUDIO_MAL_DMA_IT_TE_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+  
+  /* Enable the I2S DMA request */
+  SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+  
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  /* I2S DMA IRQ Channel configuration */
+  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+#endif 
+}
+
+/**
+  * @brief  Restore default state of the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_DeInit(void)  
+{   
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;  
+  
+  /* Deinitialize the NVIC interrupt for the I2S DMA Channel */
+  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
+  NVIC_Init(&NVIC_InitStructure);  
+#endif 
+  
+  /* Disable the DMA before the deinit */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  
+  /* Dinitialize the DMA Channel */
+  DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+  
+  /* The DMA clock is not disabled */
+}
+
+/**
+  * @brief  Starts playing audio stream from the audio Media.
+  * @param  None
+  * @retval None
+  */
+void Audio_MAL_Play(uint32_t Addr, uint32_t Size)
+{   
+  /* Configure the buffer address and size */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Addr;
+  DMA_InitStructure.DMA_BufferSize = (uint32_t)Size/2;
+  
+  /* Configure the DMA Channel with the new parameters */
+  DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);
+  
+  /* Enable the I2S DMA Channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+}
+
+/**
+  * @brief  Pauses or Resumes the audio stream playing from the Media.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *              from 0) to resume. 
+  * @param  Addr: Address from/at which the audio stream should resume/pause.
+  * @retval None
+  */
+static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr)
+{
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  {   
+    /* Disable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE);
+
+    /* Pause the I2S DMA Channel 
+        Note. For the STM32F30x devices, the DMA implements a pause feature, 
+              by disabling the channel, all configuration is preserved and data 
+              transfer is paused till the next enable of the channel.*/
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);  
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Enable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+  
+    /* Resume the I2S DMA Channel 
+        Note. For the STM32F30x devices, the DMA implements a pause feature, 
+              by disabling the channel, all configuration is preserved and data 
+              transfer is paused till the next enable of the channel.*/
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+    
+    /* If the I2S peripheral is still not enabled, enable it */
+    if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
+    {
+      I2S_Cmd(CODEC_I2S, ENABLE);
+    }    
+  }  
+}
+
+/**
+  * @brief  Stops audio stream playing on the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Stop(void)
+{   
+  /* Stop the Transfer on the I2S side: Stop and disable the DMA channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+
+  /* Clear all the DMA flags for the next transfer */
+  DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC|AUDIO_MAL_DMA_FLAG_HT|AUDIO_MAL_DMA_FLAG_TE);
+  
+  /* The I2S DMA requests are not disabled here. */
+  
+  /* In all modes, disable the I2S peripheral */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.h
new file mode 100644
index 0000000..0e0f44c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_audio_codec.h
@@ -0,0 +1,302 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_audio_codec.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32303c_eval_audio_codec.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32303C_EVAL_AUDIOCODEC_H
+#define __STM32303C_EVAL_AUDIOCODEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL_AUDIO_CODEC
+  * @{
+  */  
+
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Exported_Types
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Exported_Constants
+  * @{
+  */
+
+/*----------------------------------------------------------------------------
+             CONFIGURATION: Audio Codec Driver Configuration parameters
+  ----------------------------------------------------------------------------*/
+/* Audio Transfer mode (DMA, Interrupt or Polling) */
+#define AUDIO_MAL_MODE_NORMAL         /* Uncomment this line to enable the audio 
+                                         Transfer using DMA */
+/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio 
+                                         Transfer using DMA */
+
+/* For the DMA modes select the interrupt that will be used */
+#define AUDIO_MAL_DMA_IT_TC_EN   /* Uncomment this line to enable DMA Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_HT_EN */  /* Uncomment this line to enable DMA Half Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_TE_EN */  /* Uncomment this line to enable DMA Transfer Error interrupt */
+
+/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
+#define EVAL_AUDIO_IRQ_PREPRIO           0   /* Select the preemption priority level(0 is the highest) */
+#define EVAL_AUDIO_IRQ_SUBRIO            0   /* Select the sub-priority level (0 is the highest) */
+
+/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() 
+   function implemented in stm32303c_eval_audio_codec.c file.
+   Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                    OPTIONAL Configuration defines parameters
+  ----------------------------------------------------------------------------*/
+/* I2C clock speed configuration (in Hz) 
+  WARNING: 
+   Make sure that this define is not already declared in other files (ie. 
+  stm32303c_eval.h file). It can be used in parallel by other modules. */
+
+/* I2C TIMING Register define when I2C clock source is SYSCLK */
+/* set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define CODEC_I2C_TIMING          0xC062121F
+
+/* Uncomment defines below to select standard for audio communication between 
+  Codec and I2S peripheral */
+#define I2S_STANDARD_PHILLIPS
+/* #define I2S_STANDARD_MSB */
+/* #define I2S_STANDARD_LSB */
+
+/* Uncomment the defines below to select if the Master clock mode should be 
+  enabled or not */
+#define CODEC_MCLK_ENABLED
+/* #define CODEC_MCLK_DISABLED */
+
+/* Uncomment this line to enable verifying data sent to codec after each write 
+  operation */
+#define VERIFY_WRITTENDATA
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                    Hardware Configuration defines parameters
+  ----------------------------------------------------------------------------*/
+/* Audio Reset Pin definition */
+#define AUDIO_RESET_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define AUDIO_RESET_PIN                GPIO_Pin_11
+#define AUDIO_RESET_GPIO               GPIOD
+
+/* I2S peripheral configuration defines */
+#define CODEC_I2S                      SPI3
+#define CODEC_I2S_CLK                  RCC_APB1Periph_SPI3
+#define CODEC_I2S_ADDRESS              0x40003C0C
+#define CODEC_I2S_GPIO_AF              GPIO_AF_6
+#define CODEC_I2S_MCK_GPIO_AF          GPIO_AF_5
+#define CODEC_I2S_IRQ                  SPI3_IRQn
+#define CODEC_I2S_GPIO_CLOCK           (RCC_AHBPeriph_GPIOA)|(RCC_AHBPeriph_GPIOC)
+#define CODEC_I2S_WS_PIN               GPIO_Pin_4
+#define CODEC_I2S_SCK_PIN              GPIO_Pin_10
+#define CODEC_I2S_DOUT_PIN             GPIO_Pin_11
+#define CODEC_I2S_DIN_PIN              GPIO_Pin_12
+#define CODEC_I2S_MCK_PIN              GPIO_Pin_9
+#define CODEC_I2S_WS_PINSRC            GPIO_PinSource4
+#define CODEC_I2S_SCK_PINSRC           GPIO_PinSource10
+#define CODEC_I2S_DOUT_PINSRC          GPIO_PinSource11
+#define CODEC_I2S_DIN_PINSRC           GPIO_PinSource12
+#define CODEC_I2S_MCK_PINSRC           GPIO_PinSource9
+#define CODEC_I2S_GPIO                 GPIOC
+#define CODEC_I2S_MCK_WS_GPIO          GPIOA
+#define Audio_I2S_IRQHandler           SPI3_IRQHandler
+
+ /* I2S DMA Channel definitions */
+#define AUDIO_MAL_DMA_CLOCK            RCC_AHBPeriph_DMA2
+#define AUDIO_MAL_DMA_CHANNEL          DMA2_Channel2
+#define AUDIO_MAL_DMA_IRQ              DMA2_Channel2_IRQn
+#define AUDIO_MAL_DMA_FLAG_TC          DMA2_FLAG_TC2
+#define AUDIO_MAL_DMA_FLAG_HT          DMA2_FLAG_HT2
+#define AUDIO_MAL_DMA_FLAG_TE          DMA2_FLAG_TE2
+
+#define Audio_MAL_IRQHandler           DMA2_Channel2_IRQHandler
+#define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord
+#define AUDIO_MAL_DMA_MEM_DATA_SIZE    DMA_MemoryDataSize_HalfWord
+#define DMA_MAX_SZE                    0xFFFF
+
+/* I2C peripheral configuration defines (control interface of the audio codec) */
+#define CODEC_I2C                      I2C2
+#define CODEC_I2C_CLK                  RCC_APB1Periph_I2C2
+#define CODEC_I2C_GPIO_CLOCK           (RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOF)
+#define CODEC_I2C_GPIO_AF              GPIO_AF_4
+#define CODEC_I2C_SCL_GPIO             GPIOF
+#define CODEC_I2C_SDA_GPIO             GPIOA
+#define CODEC_I2C_SCL_PIN              GPIO_Pin_6
+#define CODEC_I2C_SDA_PIN              GPIO_Pin_10
+#define CODEC_I2S_SCL_PINSRC           GPIO_PinSource6
+#define CODEC_I2S_SDA_PINSRC           GPIO_PinSource10
+
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define CODEC_FLAG_TIMEOUT             ((uint32_t)0x1000)
+#define CODEC_LONG_TIMEOUT             ((uint32_t)(300 * CODEC_FLAG_TIMEOUT))
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                        Audio Codec User defines
+  ----------------------------------------------------------------------------*/
+/* Codec output DEVICE */
+#define OUTPUT_DEVICE_SPEAKER         1
+#define OUTPUT_DEVICE_HEADPHONE       2
+#define OUTPUT_DEVICE_BOTH            3
+#define OUTPUT_DEVICE_AUTO            4
+
+/* Volume Levels values */
+#define DEFAULT_VOLMIN                0x00
+#define DEFAULT_VOLMAX                0xFF
+#define DEFAULT_VOLSTEP               0x04
+
+#define AUDIO_PAUSE                   0
+#define AUDIO_RESUME                  1
+
+/* Codec POWER DOWN modes */
+#define CODEC_PDWN_HW                 1
+#define CODEC_PDWN_SW                 2
+
+/* MUTE commands */
+#define AUDIO_MUTE_ON                 1
+#define AUDIO_MUTE_OFF                0
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Exported_Macros
+  * @{
+  */ 
+#define VOLUME_CONVERT(x)    ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100)))
+#define DMA_MAX(x)           (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_AUDIO_CODEC_Exported_Functions
+  * @{
+  */ 
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+uint32_t EVAL_AUDIO_DeInit(void);
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size);
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd);
+uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode);
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume);
+uint32_t EVAL_AUDIO_Mute(uint32_t Command);
+
+uint32_t Codec_SwitchOutput(uint8_t Output);
+uint32_t Codec_Record_Init(void);
+uint32_t Codec_ReadRegister(uint8_t RegisterAddr);
+
+uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue);
+
+
+
+/* User Callbacks: user has to implement these functions in his code if
+  they are needed. -----------------------------------------------------------*/
+
+/* This function is called when the requested data has been completely transferred.
+   In Normal mode (when  the define AUDIO_MAL_MODE_NORMAL is enabled) this function
+   is called at the end of the whole audio file.
+   In circular mode (when  the define AUDIO_MAL_MODE_CIRCULAR is enabled) this 
+   function is called at the end of the current buffer transmission. */
+void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when half of the requested buffer has been transferred 
+   This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR 
+   define is enabled)*/
+void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when an Interrupt due to transfer error on or peripheral
+   error occurs. */
+void EVAL_AUDIO_Error_CallBack(void* pData);
+
+/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...) on the Codec control interface (I2C).
+   You can use the default timeout callback implementation by uncommenting the 
+   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32303c_eval_audio_codec.h file.
+   Typically the user implementation of this callback should reset I2C peripheral
+   and re-initialize communication or in worst case reset all the application. */
+uint32_t Codec_TIMEOUT_UserCallback(void);
+void Audio_MAL_IRQHandler(void);
+void Audio_MAL_Play(uint32_t Addr, uint32_t Size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32303C_EVAL_AUDIOCODEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.c
new file mode 100644
index 0000000..fe89465
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.c
@@ -0,0 +1,717 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_i2c_ee.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides a set of functions needed to manage an I2C M24LR64 
+  *          and M24M01 EEPROM memory.
+  *                       
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32F30x hardware resources (I2C and 
+  *          GPIO) are defined in stm32303c_eval.h file, and the initialization is 
+  *          performed in sEE_LowLevel_Init() function declared in stm32303c_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          sEE_LowLevel_Init() function. 
+  *        
+  *          @note In this driver, basic read and write functions (sEE_ReadBuffer() 
+  *                and sEE_WritePage()) use Polling mode to perform the data transfer 
+  *                to/from EEPROM memory.
+  *            
+  *     +-----------------------------------------------------------------+
+  *     |               Pin assignment for M24M01 EEPROM                  |                 
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32F30x I2C Pins                   |   sEE     |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | .                                     |   NC      |    1        |
+  *     | .                                     |   E1(VDD) |    2 (3.3V) |
+  *     | .                                     |   E2(GND) |    3  (0V)  |
+  *     | .                                     |   VSS     |    4  (0V)  |
+  *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
+  *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
+  *     | .                                     |   /WC(VSS)|    7 (0V)   |
+  *     | .                                     |   VDD     |    8 (3.3V) |
+  *     +---------------------------------------+-----------+-------------+
+  *     +-----------------------------------------------------------------+
+  *     |               Pin assignment for M24LR64 EEPROM                 |
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32F30x I2C Pins                   |   sEE     |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | .                                     |   E0(GND) |    1  (0V)  |
+  *     | .                                     |   AC0     |    2        |
+  *     | .                                     |   AC1     |    3        |
+  *     | .                                     |   VSS     |    4  (0V)  |
+  *     | sEE_I2C_SDA_PIN/ SDA                  |   SDA     |    5        |
+  *     | sEE_I2C_SCL_PIN/ SCL                  |   SCL     |    6        |
+  *     | .                                     |   E1(GND) |    7  (0V)  |
+  *     | .                                     |   VDD     |    8 (3.3V) |
+  *     +---------------------------------------+-----------+-------------+    *  
+  *
+  *  *    *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval_i2c_ee.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL_I2C_EE
+  * @brief      This file includes the I2C EEPROM driver of STM32303C-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Defines
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Variables
+  * @{
+  */
+__IO uint16_t  sEEAddress = 0;   
+__IO uint32_t  sEETimeout = sEE_LONG_TIMEOUT;
+__IO uint16_t  sEEDataNum;
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_DeInit(void)
+{
+  sEE_I2C_LowLevel_DeInit(); 
+}
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_Init(void)
+{ 
+  I2C_InitTypeDef  I2C_InitStructure;
+  
+  sEE_I2C_LowLevel_Init();
+  
+  /*!< I2C configuration */
+  /* sEE_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = sEE_I2C_TIMING;
+  
+  /* Apply sEE_I2C configuration after enabling it */
+  I2C_Init(sEE_I2C, &I2C_InitStructure);
+  
+  /* sEE_I2C Peripheral Enable */
+  I2C_Cmd(sEE_I2C, ENABLE);
+  
+  /*!< Select the EEPROM address */
+  sEEAddress = sEE_HW_ADDRESS;      
+}
+
+/**
+  * @brief  Reads a block of data from the EEPROM.
+  * @param  pBuffer : pointer to the buffer that receives the data read from 
+  *         the EEPROM.
+  * @param  ReadAddr : EEPROM's internal address to start reading from.
+  * @param  NumByteToRead : pointer to the variable holding number of bytes to 
+  *         be read from the EEPROM.
+  *
+  * @retval sEE_OK (0) if operation is correctly performed, else return value 
+  *         different from sEE_OK (0) or the timeout user callback.
+  */
+uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
+{  
+  uint32_t NumbOfSingle = 0, Count = 0, DataNum = 0, StartCom = 0;
+  
+  /* Get number of reload cycles */
+  Count = (*NumByteToRead) / 255;  
+  NumbOfSingle = (*NumByteToRead) % 255;
+  
+#ifdef sEE_M24C08
+  
+  /* Configure slave address, nbytes, reload and generate start */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send memory address */
+  I2C_SendData(sEE_I2C, (uint8_t)ReadAddr);
+  
+#elif defined(sEE_M24M01) || defined(sEE_M24C64_32) || defined (sEE_M24LR64) 
+  
+  /* Configure slave address, nbytes, reload and generate start */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, 2, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send MSB of memory address */
+  I2C_SendData(sEE_I2C, (uint8_t)((ReadAddr & 0xFF00) >> 8));
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LSB of memory address  */
+  I2C_SendData(sEE_I2C, (uint8_t)(ReadAddr & 0x00FF));
+  
+#endif /*!< sEE_M24C08 */ 
+  
+  /* Wait until TC flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }  
+  
+  /* If number of Reload cycles is not equal to 0 */
+  if (Count != 0)
+  {
+    /* Starting communication */
+    StartCom = 1;
+    
+    /* Wait until all reload cycles are performed */
+    while( Count != 0)
+    { 
+      /* If a read transfer is performed */
+      if (StartCom == 0)      
+      {
+        /* Wait until TCR flag is set */
+        sEETimeout = sEE_LONG_TIMEOUT; 
+        while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TCR) == RESET)
+        {
+          if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+        }
+      }      
+      
+      /* if remains one read cycle */
+      if ((Count == 1) && (NumbOfSingle == 0))
+      {
+        /* if starting communication */
+        if (StartCom != 0)
+        {
+          /* Configure slave address, end mode and start condition */
+          I2C_TransferHandling(sEE_I2C, sEEAddress, 255, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+        }
+        else
+        {
+          /* Configure slave address, end mode */
+          I2C_TransferHandling(sEE_I2C, sEEAddress, 255, I2C_AutoEnd_Mode, I2C_No_StartStop);          
+        }
+      }
+      else 
+      {
+        /* if starting communication */
+        if (StartCom != 0)
+        {
+          /* Configure slave address, end mode and start condition */
+          I2C_TransferHandling(sEE_I2C, sEEAddress, 255, I2C_Reload_Mode, I2C_Generate_Start_Read);
+        }
+        else
+        {
+          /* Configure slave address, end mode */
+          I2C_TransferHandling(sEE_I2C, sEEAddress, 255, I2C_Reload_Mode, I2C_No_StartStop);          
+        } 
+      }
+      
+      /* Update local variable */
+      StartCom = 0;      
+      DataNum = 0;
+      
+      /* Wait until all data are received */
+      while (DataNum != 255)
+      {        
+        /* Wait until RXNE flag is set */
+        sEETimeout = sEE_LONG_TIMEOUT;
+        while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_RXNE) == RESET)
+        {
+          if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+        }
+        
+        /* Read data from RXDR */
+        pBuffer[DataNum]= I2C_ReceiveData(sEE_I2C);
+        
+        /* Update number of received data */
+        DataNum++;
+        (*NumByteToRead)--;
+      }      
+      /* Update Pointer of received buffer */ 
+      pBuffer += DataNum;  
+      
+      /* update number of reload cycle */
+      Count--;
+    }
+    
+    /* If number of single data is not equal to 0 */
+    if (NumbOfSingle != 0)
+    {            
+      /* Wait until TCR flag is set */
+      sEETimeout = sEE_LONG_TIMEOUT;   
+      while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TCR) == RESET)
+      {
+        if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+      }
+      
+      /* Update CR2 : set Nbytes and end mode */
+      I2C_TransferHandling(sEE_I2C, sEEAddress, (uint8_t)(NumbOfSingle), I2C_AutoEnd_Mode, I2C_No_StartStop);
+      
+      /* Reset local variable */
+      DataNum = 0;
+      
+      /* Wait until all data are received */
+      while (DataNum != NumbOfSingle)
+      {        
+        /* Wait until RXNE flag is set */
+        sEETimeout = sEE_LONG_TIMEOUT;
+        while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_RXNE) == RESET)
+        {
+          if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+        }
+        
+        /* Read data from RXDR */
+        pBuffer[DataNum]= I2C_ReceiveData(sEE_I2C);
+        
+        /* Update number of received data */
+        DataNum++;
+        (*NumByteToRead)--;
+      } 
+    }
+  }
+  else
+  {
+    /* Update CR2 : set Slave Address , set read request, generate Start and set end mode */
+    I2C_TransferHandling(sEE_I2C, sEEAddress, (uint32_t)(NumbOfSingle), I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+    
+    /* Reset local variable */
+    DataNum = 0;
+    
+    /* Wait until all data are received */
+    while (DataNum != NumbOfSingle)
+    {
+      /* Wait until RXNE flag is set */
+      sEETimeout = sEE_LONG_TIMEOUT; 
+      while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_RXNE) == RESET)
+      {
+        if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+      }
+      
+      /* Read data from RXDR */
+      pBuffer[DataNum]= I2C_ReceiveData(sEE_I2C);
+      
+      /* Update number of received data */
+      DataNum++;
+      (*NumByteToRead)--;
+    }    
+  }  
+  
+  /* Wait until STOPF flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(sEE_I2C, I2C_ICR_STOPCF);
+  
+  /* If all operations OK, return sEE_OK (0) */
+  return sEE_OK;
+}
+
+/**
+  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
+  *
+  * @note   The number of bytes (combined to write start address) must not 
+  *         cross the EEPROM page boundary. This function can only write into
+  *         the boundaries of an EEPROM page.
+  *         This function doesn't check on boundaries condition (in this driver 
+  *         the function sEE_WriteBuffer() which calls sEE_WritePage() is 
+  *         responsible of checking on Page boundaries).
+  * 
+  * @param  pBuffer : pointer to the buffer containing the data to be written to 
+  *         the EEPROM.
+  * @param  WriteAddr : EEPROM's internal address to write to.
+  * @param  NumByteToWrite : pointer to the variable holding number of bytes to 
+  *         be written into the EEPROM.
+  *
+  * @retval sEE_OK (0) if operation is correctly performed, else return value 
+  *         different from sEE_OK (0) or the timeout user callback.
+  */
+uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite)
+{   
+  uint32_t DataNum = 0;
+  
+#ifdef sEE_M24C08
+  
+  /* Configure slave address, nbytes, reload and generate start */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, 1, I2C_Reload_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send memory address */
+  I2C_SendData(sEE_I2C, (uint8_t)WriteAddr);
+  
+#elif defined(sEE_M24M01) || defined(sEE_M24C64_32) || defined (sEE_M24LR64)
+  
+  /* Configure slave address, nbytes, reload and generate start */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, 2, I2C_Reload_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send MSB of memory address */
+  I2C_SendData(sEE_I2C, (uint8_t)((WriteAddr & 0xFF00) >> 8));  
+  
+  /* Wait until TXIS flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LSB of memory address  */
+  I2C_SendData(sEE_I2C, (uint8_t)(WriteAddr & 0x00FF));
+  
+#endif /*!< sEE_M24C08 */
+  
+  /* Wait until TCR flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TCR) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }
+  
+  /* Update CR2 : set Slave Address , set write request, generate Start and set end mode */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, (uint8_t)(*NumByteToWrite), I2C_AutoEnd_Mode, I2C_No_StartStop);
+  
+  while (DataNum != (*NumByteToWrite))
+  {      
+    /* Wait until TXIS flag is set */
+    sEETimeout = sEE_LONG_TIMEOUT;
+    while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_TXIS) == RESET)
+    {
+      if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+    }  
+    
+    /* Write data to TXDR */
+    I2C_SendData(sEE_I2C, (uint8_t)(pBuffer[DataNum]));
+    
+    /* Update number of transmitted data */
+    DataNum++;   
+  }  
+  
+  /* Wait until STOPF flag is set */
+  sEETimeout = sEE_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(sEE_I2C, I2C_ICR_STOPCF);
+  
+  /* If all operations OK, return sEE_OK (0) */
+  return sEE_OK;
+}
+
+/**
+  * @brief  Writes buffer of data to the I2C EEPROM.
+  * @param  pBuffer : pointer to the buffer  containing the data to be written 
+  *         to the EEPROM.
+  * @param  WriteAddr : EEPROM's internal address to write to.
+  * @param  NumByteToWrite : number of bytes to write to the EEPROM.
+  * @retval None
+  */
+void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
+{
+  uint16_t NumOfPage = 0, NumOfSingle = 0, count = 0;
+  uint16_t Addr = 0;
+  
+  Addr = WriteAddr % sEE_PAGESIZE;
+  count = sEE_PAGESIZE - Addr;
+  NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
+  NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
+  
+  /*!< If WriteAddr is sEE_PAGESIZE aligned  */
+  if(Addr == 0) 
+  {
+    /*!< If NumByteToWrite < sEE_PAGESIZE */
+    if(NumOfPage == 0) 
+    {
+      /* Store the number of data to be written */
+      sEEDataNum = NumOfSingle;
+      /* Start writing data */
+      sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+      sEE_WaitEepromStandbyState();
+    }
+    /*!< If NumByteToWrite > sEE_PAGESIZE */
+    else  
+    {
+      while(NumOfPage--)
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = sEE_PAGESIZE;        
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
+        sEE_WaitEepromStandbyState();
+        WriteAddr +=  sEE_PAGESIZE;
+        pBuffer += sEE_PAGESIZE;
+      }
+      
+      if(NumOfSingle!=0)
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = NumOfSingle;          
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+        sEE_WaitEepromStandbyState();
+      }
+    }
+  }
+  /*!< If WriteAddr is not sEE_PAGESIZE aligned  */
+  else 
+  {
+    /*!< If NumByteToWrite < sEE_PAGESIZE */
+    if(NumOfPage== 0) 
+    {
+      /*!< If the number of data to be written is more than the remaining space 
+      in the current page: */
+      if (NumByteToWrite > count)
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = count;        
+        /*!< Write the data contained in same page */
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+        sEE_WaitEepromStandbyState();      
+        
+        /* Store the number of data to be written */
+        sEEDataNum = (NumByteToWrite - count);          
+        /*!< Write the remaining data in the following page */
+        sEE_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&sEEDataNum));
+        sEE_WaitEepromStandbyState();        
+      }      
+      else      
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = NumOfSingle;         
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+        sEE_WaitEepromStandbyState();        
+      }     
+    }
+    /*!< If NumByteToWrite > sEE_PAGESIZE */
+    else
+    {
+      NumByteToWrite -= count;
+      NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
+      NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
+      
+      if(count != 0)
+      {  
+        /* Store the number of data to be written */
+        sEEDataNum = count;         
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+        sEE_WaitEepromStandbyState();
+        WriteAddr += count;
+        pBuffer += count;
+      } 
+      
+      while(NumOfPage--)
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = sEE_PAGESIZE;          
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum));
+        sEETimeout = sEE_LONG_TIMEOUT;
+        sEE_WaitEepromStandbyState();
+        WriteAddr +=  sEE_PAGESIZE;
+        pBuffer += sEE_PAGESIZE;  
+      }
+      if(NumOfSingle != 0)
+      {
+        /* Store the number of data to be written */
+        sEEDataNum = NumOfSingle;           
+        sEE_WritePage(pBuffer, WriteAddr, (uint8_t*)(&sEEDataNum)); 
+        sEE_WaitEepromStandbyState();
+      }
+    }
+  }  
+}
+
+/**
+  * @brief  Wait for EEPROM Standby state.
+  * 
+  * @note  This function allows to wait and check that EEPROM has finished the 
+  *        last operation. It is mostly used after Write operation: after receiving
+  *        the buffer to be written, the EEPROM may need additional time to actually
+  *        perform the write operation. During this time, it doesn't answer to
+  *        I2C packets addressed to it. Once the write operation is complete
+  *        the EEPROM responds to its address.
+  * 
+  * @param  None
+  *
+  * @retval sEE_OK (0) if operation is correctly performed, else return value 
+  *         different from sEE_OK (0) or the timeout user callback.
+  */
+uint32_t sEE_WaitEepromStandbyState(void)      
+{
+  __IO uint32_t sEETrials = 0;
+  
+  /* Keep looping till the slave acknowledge his address or maximum number 
+  of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
+  in stm32303c_eval_i2c_ee.h file) */
+  
+  /* Configure CR2 register : set Slave Address and end mode */
+  I2C_TransferHandling(sEE_I2C, sEEAddress, 0, I2C_AutoEnd_Mode, I2C_No_StartStop);  
+  
+  do
+  { 
+    /* Initialize sEETimeout */
+    sEETimeout = sEE_FLAG_TIMEOUT;
+    
+    /* Clear NACKF */
+    I2C_ClearFlag(sEE_I2C, I2C_ICR_NACKCF | I2C_ICR_STOPCF);
+    
+    /* Generate start */
+    I2C_GenerateSTART(sEE_I2C, ENABLE);
+    
+    /* Wait until timeout elapsed */
+    while (sEETimeout-- != 0); 
+    
+    /* Check if the maximum allowed numbe of trials has bee reached */
+    if (sEETrials++ == sEE_MAX_TRIALS_NUMBER)
+    {
+      /* If the maximum number of trials has been reached, exit the function */
+      return sEE_TIMEOUT_UserCallback();
+    }
+  }
+  while(I2C_GetFlagStatus(sEE_I2C, I2C_ISR_NACKF) != RESET);
+  
+  /* Clear STOPF */
+  I2C_ClearFlag(sEE_I2C, I2C_ICR_STOPCF);
+  
+  /* Return sEE_OK if device is ready */
+  return sEE_OK;
+}
+
+#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
+/**
+  * @brief  Basic management of the timeout situation.
+  * @param  None.
+  * @retval None.
+  */
+uint32_t sEE_TIMEOUT_UserCallback(void)
+{
+ return 0;
+}
+#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.h
new file mode 100644
index 0000000..00a799a
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_ee.h
@@ -0,0 +1,206 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_i2c_ee.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for 
+  *          the stm32303c_eval_i2c_ee.c firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32303C_EVAL_I2C_EE_H
+#define __STM32303C_EVAL_I2C_EE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL_I2C_EE
+  * @{
+  */  
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Exported_Types
+  * @{
+  */ 
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32303C_EVAL_I2C_EE_Exported_Constants
+  * @{
+  */
+
+/* Select which EEPROM will be used with this driver */
+#define sEE_M24LR64 
+/* #define sEE_M24M01 */ 
+   
+/* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() 
+   function implemented in stm32303c_eval_i2c_ee.c file.
+   sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+   
+#if !defined (sEE_M24C08) && !defined (sEE_M24C64_32) && !defined (sEE_M24LR64) && !defined (sEE_M24M01)
+/* Use the defines below the choose the EEPROM type */
+#define sEE_M24M01  /* Support the device: M24M01. */
+/* #define sEE_M24C08*/  /* Support the device: M24C08. */
+/* note: Could support: M24C01, M24C02, M24C04 and M24C16 if the blocks and 
+   HW address are correctly defined*/
+/*#define sEE_M24C64_32*/  /* Support the devices: M24C32 and M24C64 */
+/*#define sEE_M24LR64*/ /*Support the devices: M24LR64 */
+#endif
+
+#ifdef sEE_M24C64_32
+/* For M24C32 and M24C64 devices, E0,E1 and E2 pins are all used for device 
+  address selection (ne need for additional address lines). According to the 
+  Harware connection on the board. */
+
+ #define sEE_HW_ADDRESS         0xA0   /* E0 = E1 = E2 = 0 */ 
+
+#elif defined (sEE_M24C08)
+/* The M24C08W contains 4 blocks (128byte each) with the adresses below: E2 = 0 
+   EEPROM Addresses defines */
+ #define sEE_HW_ADDRESS     0xA0   /* E2 = 0 */ 
+ /*#define sEE_HW_ADDRESS     0xA2*/ /* E2 = 0 */  
+ /*#define sEE_HW_ADDRESS     0xA4*/ /* E2 = 0 */
+ /*#define sEE_HW_ADDRESS     0xA6*/ /* E2 = 0 */
+
+#elif defined (sEE_M24LR64)
+ #define sEE_HW_ADDRESS         0xA0
+
+#elif defined (sEE_M24M01)
+/* The sEE_M24M01 contains 2 blocks (64Kbytes each) with the adresses below 
+   EEPROM Addresses defines */
+ #define sEE_HW_ADDRESS     0xA4      /* Block 1 : E1= 1; E2 = 0; A16 = 0 */
+ /*#define sEE_HW_ADDRESS     0xA6*/  /* Block 2 : E1= 1; E2 = 0; A16 = 1 */
+
+#endif /* sEE_M24C64_32 */
+
+/* I2C TIMING Register define when I2C clock source is SYSCLK */
+/* I2C TIMING is calculated in case of the I2C Clock source is the SYSCLK = 72 MHz */
+/* When using sEE_M24M01 set TIMING to 0x00C4092A to reach 1 MHz speed (Rise time = 26ns, Fall time = 2ns) */
+/* When using sEE_M24LR64 set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define sEE_I2C_TIMING             0xC062121F
+   
+
+#if defined (sEE_M24C08)
+ #define sEE_PAGESIZE           16
+#elif defined (sEE_M24C64_32)
+ #define sEE_PAGESIZE           32
+#elif defined (sEE_M24LR64)
+ #define sEE_PAGESIZE           4
+#elif defined (sEE_M24M01)
+ #define sEE_PAGESIZE           128   
+#endif
+   
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define sEE_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
+
+/* Maximum number of trials for sEE_WaitEepromStandbyState() function */
+#define sEE_MAX_TRIALS_NUMBER     300
+      
+#define sEE_OK                    0
+#define sEE_FAIL                  1   
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32303C_EVAL_I2C_EE_Exported_Macros
+  * @{
+  */    
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_EE_Exported_Functions
+  * @{
+  */ 
+void     sEE_DeInit(void);
+void     sEE_Init(void);
+uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
+uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite);
+void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
+uint32_t sEE_WaitEepromStandbyState(void);
+
+/* USER Callbacks: These are functions for which prototypes only are declared in
+   EEPROM driver and that should be implemented into user applicaiton. */  
+/* sEE_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...).
+   You can use the default timeout callback implementation by uncommenting the 
+   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32303c_eval_i2c_ee.h file.
+   Typically the user implementation of this callback should reset I2C peripheral
+   and re-initialize communication or in worst case reset all the application. */
+uint32_t sEE_TIMEOUT_UserCallback(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32303C_EVAL_I2C_EE_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.c
new file mode 100644
index 0000000..54476df
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.c
@@ -0,0 +1,754 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_i2c_tsensor.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file provides a set of functions needed to manage the I2C TS751 
+  *          temperature sensor mounted on STM32303C-EVAL board . 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this sensor. The needed STM323F30x hardware resources (I2C and 
+  *          GPIO) are defined in stm32303c_eval.h file, and the initialization is 
+  *          performed in TS751_LowLevel_Init() function declared in stm32303c_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          TS751_LowLevel_Init() function.
+  *
+  *     +--------------------------------------------------------------------+
+  *     |                        Pin assignment                              |                 
+  *     +---------------------------------------+-----------+----------------+
+  *     |  STM32F30x I2C Pins                   |   STTS751     |   Pin      |
+  *     +---------------------------------------+-----------+----------------+
+  *     | TS751_I2C_SDA_PIN/ SDA                 |   Addr/Therm |    1       |
+  *     | TS751_I2C_SCL_PIN/ SCL                 |   GND        |    2 (0V)  |
+  *     | TS751_I2C_SMBUSALERT_PIN/ SMBUS ALERT  |   VDD        |    3 (3.3V)|
+  *     | Addr/Therm pin                         |   SCL        |    4       |
+  *     | .                                      |   SMBUS ALERT|    5       |
+  *     | .                                      |   SDA        |    6       |
+  *     +---------------------------------------+-----------+----------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval_i2c_tsensor.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL_I2C_TSENSOR
+  * @brief      This file includes the TS751 Temperature Sensor driver of 
+  *             STM32303C-EVAL boards.
+  * @{
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Defines
+  * @{
+  */ 
+#define TS751_SD_SET                0x01 /*!< Set SD bit in the configuration register */
+#define TS751_SD_RESET              0xFE /*!< Reset SD bit in the configuration register */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Variables
+  * @{
+  */ 
+  
+__IO uint32_t  TS751_Timeout = TS751_LONG_TIMEOUT; 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Function_Prototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the TS751_I2C.
+  * @param  None
+  * @retval None
+  */
+void TS751_DeInit(void)
+{
+  TS751_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the TS751_I2C.
+  * @param  None
+  * @retval None
+  */
+void TS751_Init(void)
+{  
+  I2C_InitTypeDef  I2C_InitStructure;
+  
+  TS751_LowLevel_Init();
+  
+  /* TS751_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = TS751_I2C_TIMING;
+  
+  /* Apply TS751_I2C configuration after enabling it */
+  I2C_Init(TS751_I2C, &I2C_InitStructure);
+  
+  /* TS751_I2C Peripheral Enable */
+  I2C_Cmd(TS751_I2C, ENABLE);
+}
+
+/**
+  * @brief  Checks the TS751 status.
+  * @param  None
+  * @retval ErrorStatus: TS751 Status (ERROR or SUCCESS).
+  */
+ErrorStatus TS751_GetStatus(void)
+{
+  uint32_t I2C_TimeOut = I2C_TIMEOUT;
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 0, I2C_AutoEnd_Mode, I2C_No_StartStop);
+  
+  /* Clear NACKF and STOPF */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_NACKCF | I2C_ICR_STOPCF);
+  
+  /* Generate start */
+  I2C_GenerateSTART(TS751_I2C, ENABLE);  
+  
+  /* Wait until timeout elapsed */
+  while ((I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET) && (I2C_TimeOut-- != 0)); 
+  
+  /* Check if Temp sensor is ready for use */
+  if ((I2C_GetFlagStatus(TS751_I2C, I2C_ISR_NACKF) != RESET) || (I2C_TimeOut == 0))
+  {      
+    /* Clear NACKF and STOPF */
+    I2C_ClearFlag(TS751_I2C, I2C_ICR_NACKCF | I2C_ICR_STOPCF);
+    
+    return ERROR;
+  }
+  else
+  {
+    /* Clear STOPF */
+    I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+    
+    return SUCCESS;
+  }    
+}
+
+/**
+  * @brief  Read the specified register from the TS751.
+  * @param  RegName: specifies the TS751 register to be read.
+  *              This member can be one of the following values:  
+  *                  - TS751_REG_TEMP: temperature register
+  *                  - TS751_REG_TOS: Over-limit temperature register
+  *                  - TS751_REG_THYS: Hysteresis temperature register
+  * @retval TS751 register value.
+  */
+uint8_t TS751_ReadReg(uint8_t RegName)
+{   
+  uint8_t TS751_BufferRX[1] ={0}; 
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)RegName);
+  
+  /* Wait until TC flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)    
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Read data from RXDR */
+  TS751_BufferRX[0]= I2C_ReceiveData(TS751_I2C);
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)   
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  /* return a Reg value */
+  return TS751_BufferRX[0];  
+}
+
+/**
+  * @brief  Write to the specified register of the TS751.
+  * @param  RegName: specifies the TS751 register to be written.
+  *              This member can be one of the following values:    
+  *                  - TS751_REG_TOS: Over-limit temperature register
+  *                  - TS751_REG_THYS: Hysteresis temperature register
+  * @param  RegValue: value to be written to TS751 register.  
+  * @retval None
+  */
+uint8_t TS751_WriteReg(uint8_t RegName, uint16_t RegValue)
+{  
+  uint8_t TS751_BufferTX[1] ={0};
+  
+  TS751_BufferTX[0] = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_Reload_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)   
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)RegName);
+  
+  /* Wait until TCR flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TCR) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_No_StartStop);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Write data to TXDR */
+  I2C_SendData(TS751_I2C, (TS751_BufferTX[0]));
+  
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  return TS751_OK;
+}
+/**
+  * @brief  Read Temperature register of TS751: double temperature value.
+  * @param  None
+  * @retval TS751 measured temperature value.
+  */
+uint8_t TS751_AlerteResponseAddressRead(void)
+{   
+  uint8_t TS751_BufferRX[1] ={0};
+  
+  /**************** Read Alerte Response Address ***********************/
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  /* Configure slave address, nbytes, reload, end mode and start generation */
+  I2C_TransferHandling(TS751_I2C, 0x18, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read); 
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;    
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Read data from RXDR */
+  TS751_BufferRX[0]= I2C_ReceiveData(TS751_I2C); 
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF | I2C_ICR_NACKCF);
+  
+  /* return ARA value */
+  return TS751_BufferRX[0]; 
+}
+  
+
+/**
+  * @brief  Read Temperature register of TS751: double temperature value.
+  * @param  None
+  * @retval TS751 measured temperature value.
+  */
+uint16_t TS751_ReadTemp(void)
+{   
+  uint8_t TS751_BufferRX[2] ={0,0};
+  uint16_t tmp = 0;
+  
+  /**************** Read Temperature value high Register ***********************/
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write); 
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_TEMPH); 
+  /* Wait until TC flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }   
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read); 
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;    
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Read data from RXDR */
+  TS751_BufferRX[0]= I2C_ReceiveData(TS751_I2C); 
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  
+  /****************** Read Temperature value low Register ************************/  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write); 
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_TEMPL);
+  
+  /* Wait until TC flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }   
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;    
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Read data from RXDR */
+  TS751_BufferRX[1]= I2C_ReceiveData(TS751_I2C);  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  } 
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  /*************************** Store Data ******************************/
+  /*!< Store TS751_I2C received data */
+  tmp = (uint16_t)(TS751_BufferRX[0] << 8);
+  tmp |= TS751_BufferRX[1];      
+  /*!< Return Temperature value */
+  return (uint16_t)(tmp >> 4);
+}
+
+/**
+  * @brief  Read the configuration register from the TS751.
+  * @param  None
+  * @retval TS751 configuration register value.
+  */
+uint8_t TS751_ReadConfReg(void)
+{   
+  uint8_t TS751_BufferRX[1] ={0}; 
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_CONF);
+  
+  /* Wait until TC flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)  
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Read data from RXDR */
+  TS751_BufferRX[0]= I2C_ReceiveData(TS751_I2C);  
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET) 
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  /*!< Return Register value */
+  return (uint8_t)TS751_BufferRX[0];
+}
+
+/**
+  * @brief  Write to the configuration register of the TS751.
+  * @param  RegValue: specifies the value to be written to TS751 configuration 
+  *         register.
+  * @retval None
+  */
+uint8_t TS751_WriteConfReg(uint8_t RegValue)
+{   
+  uint8_t TS751_BufferTX = 0;  
+  
+  TS751_BufferTX = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET) 
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_Reload_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_CONF);
+  
+  /* Wait until TCR flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TCR) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_No_StartStop);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Write data to TXDR */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_BufferTX);
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+    
+  return TS751_OK;  
+}
+
+/**
+  * @brief  Enables or disables the TS751.
+  * @param  NewState: specifies the TS751 new status. This parameter can be ENABLE
+  *         or DISABLE.  
+  * @retval None
+  */
+uint8_t TS751_ShutDown(FunctionalState NewState)
+{   
+  uint8_t TS751_BufferRX[2] ={0,0};
+  uint8_t TS751_BufferTX = 0;
+  __IO uint8_t RegValue = 0;    
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_CONF);
+  
+  /* Wait until TC flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;   
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_RXNE) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Read data from RXDR */
+  TS751_BufferRX[0]= I2C_ReceiveData(TS751_I2C); 
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  /*!< Get received data */
+  RegValue = (uint8_t)TS751_BufferRX[0];
+  
+  /*---------------------------- Transmission Phase ---------------------------*/
+  
+  /*!< Enable or disable SD bit */
+  if (NewState != DISABLE)
+  {
+    /*!< Enable TS751 */
+    TS751_BufferTX = RegValue & TS751_SD_RESET;
+  }
+  else
+  {
+    /*!< Disable TS751 */
+    TS751_BufferTX = RegValue | TS751_SD_SET;
+  }  
+  
+  /* Test on BUSY Flag */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_Reload_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_REG_CONF);
+  
+  /* Wait until TCR flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TCR) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(TS751_I2C, TS751_ADDR, 1, I2C_AutoEnd_Mode, I2C_No_StartStop);
+  
+  /* Wait until TXIS flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }  
+  
+  /* Write data to TXDR */
+  I2C_SendData(TS751_I2C, (uint8_t)TS751_BufferTX);
+  
+  /* Wait until STOPF flag is set */
+  TS751_Timeout = TS751_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(TS751_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((TS751_Timeout--) == 0) return TS751_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(TS751_I2C, I2C_ICR_STOPCF);
+  
+  return TS751_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.h
new file mode 100644
index 0000000..af5ff97
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32303C_EVAL/stm32303c_eval_i2c_tsensor.h
@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    stm32303c_eval_i2c_tsensor.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    23-October-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32303c_eval_i2c_tsensor.c firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32303C_EVAL_I2C_TSENSOR_H
+#define __STM32303C_EVAL_I2C_TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32303c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL
+  * @{
+  */ 
+
+/** @addtogroup Common
+  * @{
+  */
+  
+/** @addtogroup STM32303C_EVAL_I2C_TSENSOR
+  * @{
+  */  
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Exported_Types
+  * @{
+  */
+   
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  TS751_OK = 0,
+  TS751_FAIL
+}TS751_Status_TypDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Exported_Constants
+  * @{
+  */ 
+    
+/* Uncomment the following line to use Timeout_User_Callback TS751_TimeoutUserCallback(). 
+   If This Callback is enabled, it should be implemented by user in main function .
+   TS751_TimeoutUserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/*#define USE_TIMEOUT_USER_CALLBACK*/
+    
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define TS751_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define TS751_LONG_TIMEOUT         ((uint32_t)(10 * TS751_FLAG_TIMEOUT))    
+    
+
+/**
+  * @brief  Block Size
+  */
+#define TS751_REG_TEMPH      0x00  /*!< Temperature Register of TS751 */
+#define TS751_REG_TEMPL      0x02  /*!< Temperature Register of TS751 */
+#define TS751_REG_CONF       0x03  /*!< Configuration Register of TS751 */
+#define TS751_REG_THYS       0x21  /*!< Temperature Register of TS751 */
+#define TS751_REG_TOS        0x20  /*!< Over-temp Shutdown threshold Register of TS751 */
+#define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
+#define TS751_ADDR           0x90   /*!< TS751 address */
+
+
+/* I2C TIMING Register define when I2C clock source is SYSCLK */
+/* I2C TIMING is calculated in case of the I2C Clock source is the SYSCLK = 72 MHz */
+/* set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define TS751_I2C_TIMING              0xC062121F
+  
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32303C_EVAL_I2C_TSENSOR_Exported_Functions
+  * @{
+  */ 
+void TS751_DeInit(void);
+void TS751_Init(void);
+ErrorStatus TS751_GetStatus(void);
+uint8_t TS751_AlerteResponseAddressRead(void);
+uint16_t TS751_ReadTemp(void);
+uint8_t TS751_ReadReg(uint8_t RegName);
+uint8_t TS751_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t TS751_ReadConfReg(void);
+uint8_t TS751_WriteConfReg(uint8_t RegValue);
+uint8_t TS751_ShutDown(FunctionalState NewState);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with TS751. Only protoype
+  *         of this function is decalred in TS751 driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and TS751.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t TS751_TIMEOUT_UserCallback(void);
+#else
+ #define TS751_TIMEOUT_UserCallback()  TS751_FAIL
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32303C_EVAL_I2C_TSENSOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c
new file mode 100644
index 0000000..62b6a04
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.c
@@ -0,0 +1,677 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides a set of firmware functions to manage Leds, 
+  *          push-button and COM ports
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */   
+    
+/** @defgroup STM32373C_EVAL_LOW_LEVEL 
+  * @brief This file provides firmware functions to manage Leds, push-buttons, 
+  *        COM ports, SD card on SPI and temperature sensor (LM75) available on 
+  *        STM32373C-EVAL evaluation board from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
+                                 LED4_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+                                 LED4_GPIO_CLK};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {TAMPER_BUTTON_GPIO_PORT, KEY_BUTTON_GPIO_PORT,
+                                      RIGHT_BUTTON_GPIO_PORT, LEFT_BUTTON_GPIO_PORT,
+                                      UP_BUTTON_GPIO_PORT, DOWN_BUTTON_GPIO_PORT,
+                                      SEL_BUTTON_GPIO_PORT}; 
+
+const uint16_t BUTTON_PIN[BUTTONn] = {TAMPER_BUTTON_PIN, KEY_BUTTON_PIN,
+                                      RIGHT_BUTTON_PIN, LEFT_BUTTON_PIN,
+                                      UP_BUTTON_PIN, DOWN_BUTTON_PIN,
+                                      SEL_BUTTON_PIN}; 
+
+const uint32_t BUTTON_CLK[BUTTONn] = {TAMPER_BUTTON_GPIO_CLK, KEY_BUTTON_GPIO_CLK,
+                                      RIGHT_BUTTON_GPIO_CLK, LEFT_BUTTON_GPIO_CLK,
+                                      UP_BUTTON_GPIO_CLK, DOWN_BUTTON_GPIO_CLK,
+                                      SEL_BUTTON_GPIO_CLK};
+
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {TAMPER_BUTTON_EXTI_LINE,
+                                            KEY_BUTTON_EXTI_LINE,
+                                            RIGHT_BUTTON_EXTI_LINE,
+                                            LEFT_BUTTON_EXTI_LINE,
+                                            UP_BUTTON_EXTI_LINE,
+                                            DOWN_BUTTON_EXTI_LINE,
+                                            SEL_BUTTON_EXTI_LINE};
+
+const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {TAMPER_BUTTON_EXTI_PORT_SOURCE,
+                                              KEY_BUTTON_EXTI_PORT_SOURCE,
+                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,
+                                              LEFT_BUTTON_EXTI_PORT_SOURCE,
+                                              UP_BUTTON_EXTI_PORT_SOURCE,
+                                              DOWN_BUTTON_EXTI_PORT_SOURCE,
+                                              SEL_BUTTON_EXTI_PORT_SOURCE};
+								 
+const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {TAMPER_BUTTON_EXTI_PIN_SOURCE,
+                                             KEY_BUTTON_EXTI_PIN_SOURCE,
+                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,
+                                             LEFT_BUTTON_EXTI_PIN_SOURCE,
+                                             UP_BUTTON_EXTI_PIN_SOURCE,
+                                             DOWN_BUTTON_EXTI_PIN_SOURCE,
+                                             SEL_BUTTON_EXTI_PIN_SOURCE}; 
+                                             
+const uint8_t BUTTON_IRQn[BUTTONn] = {TAMPER_BUTTON_EXTI_IRQn, KEY_BUTTON_EXTI_IRQn,
+                                       RIGHT_BUTTON_EXTI_IRQn, LEFT_BUTTON_EXTI_IRQn,
+                                       UP_BUTTON_EXTI_IRQn, DOWN_BUTTON_EXTI_IRQn,
+                                       SEL_BUTTON_EXTI_IRQn};                                       
+                                       
+
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; 
+
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
+ 
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
+
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
+
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
+ 
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
+
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
+
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
+ 
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE};
+
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE};
+ 
+const uint8_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF};
+ 
+const uint8_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF};
+
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4
+  * @retval None
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Enable the GPIO_LED Clock */
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter can be one of following parameters: 
+  *     @arg BUTTON_TAMPER: Tamper Push Button  
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button
+  * @param  Button_Mode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                     generation capability  
+  * @retval None
+  */
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* There is no Wakeup button on STM32373C_EVAL, the Button value should
+     be greater than 0. */
+  if(Button > 0)
+  {
+    Button = (Button_TypeDef) (Button - 1);
+    
+    /* Enable the BUTTON Clock */
+    RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+    /* Configure Button pin as input */
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+    GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+    GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+
+    if (Button_Mode == BUTTON_MODE_EXTI)
+    {
+      /* Connect Button EXTI Line to Button GPIO Pin */
+      SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+
+      /* Configure Button EXTI line */
+      EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+      EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    
+      if(Button != BUTTON_KEY) 
+      {
+        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
+      }
+      else
+      {
+        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+      }
+      EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+      EXTI_Init(&EXTI_InitStructure);
+
+      /* Enable and set Button EXTI Interrupt to the lowest priority */
+      NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+      NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+      NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+      NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+      NVIC_Init(&NVIC_InitStructure); 
+    }
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter can be one of following parameters:
+  *     @arg BUTTON_TAMPER: Tamper Push Button   
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    
+  * @retval - When Button > 0, the Button GPIO pin value is returned.
+  *         - When Button = 0 , error code (0xFF) is returned.   
+  */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+  /* There is no Wakeup button on STM32373C_EVAL-EVAL, the Button value should
+     be greater than 0. */
+  if(Button > 0)
+  {
+    Button = (Button_TypeDef) (Button - 1);
+    return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+  }
+  else
+  {
+    return 0xFF; /* Error Code */
+  }
+}
+
+/**
+  * @brief  Configures COM port.
+  * @param  COM: Specifies the COM port to be configured.
+  *   This parameter can be one of following parameters:    
+  *     @arg COM1
+  *     @arg COM2  
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
+  *   contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
+
+  /* Enable USART clock */
+  RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+
+  /* Connect PXx to USARTx_Tx */
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
+
+  /* Connect PXx to USARTx_Rx */
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
+  
+  /* Configure USART Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
+    
+  /* Configure USART Rx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
+
+  /* USART configuration */
+  USART_Init(COM_USART[COM], USART_InitStruct);
+    
+  /* Enable USART */
+  USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+  * @brief  DeInitializes the SPI interface.
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
+  SPI_I2S_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
+  
+  /*!< SD_SPI Periph clock disable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); 
+
+  /*!< Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  SPI_InitTypeDef   SPI_InitStructure;
+
+  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
+       and SD_SPI_SCK_GPIO Periph clock enable */
+  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
+                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
+
+  /*!< SD_SPI Periph clock enable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); 
+
+  /*!< Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PXx to SD_SPI_SCK */
+  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
+
+  /* Connect PXx to SD_SPI_MISO */
+  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); 
+
+  /* Connect PXx to SD_SPI_MOSI */
+  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  
+  
+  /*!< SD_SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(SD_SPI, &SPI_InitStructure);
+  
+  SPI_RxFIFOThresholdConfig(SD_SPI, SPI_RxFIFOThreshold_QF);
+  
+  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
+}
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< Disable LM75_I2C */
+  I2C_Cmd(LM75_I2C, DISABLE);
+  
+  /*!< DeInitializes the LM75_I2C */
+  I2C_DeInit(LM75_I2C);
+  
+  /*!< LM75_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
+    
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+
+/**
+  * @brief  Initializes the LM75_I2C..
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< LM75_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
+    
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+  
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
+                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
+  
+  /* Connect PXx to I2C_SCL */
+  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
+
+  /* Connect PXx to I2C_SDA */
+  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); 
+
+  /* Connect PXx to I2C_SMBUSALER */
+  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);
+    
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_I2C_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure; 
+   
+  /* sEE_I2C Peripheral Disable */
+  I2C_Cmd(sEE_I2C, DISABLE);
+ 
+  /* sEE_I2C DeInit */
+  I2C_DeInit(sEE_I2C);
+
+  /*!< sEE_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
+    
+  /* Disable the I2C fast mode plus driving capability */
+  SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, DISABLE);
+  
+  /*!< GPIO configuration */  
+  /*!< Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_I2C_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+  
+  /* Enable the I2C fast mode plus driving capability */
+  SYSCFG_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus_I2C2, ENABLE);
+  
+  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
+  
+  /*!< sEE_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
+  
+  /* Connect PXx to I2C_SCL*/
+  GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
+  
+  /* Connect PXx to I2C_SDA*/
+  GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);
+  
+  /*!< GPIO configuration */  
+  /*!< Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+  
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);     
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.h
new file mode 100644
index 0000000..335482b
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval.h
@@ -0,0 +1,409 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains definitions for STM32373C_EVAL's Leds, push-buttons
+  *          and COM ports hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_H
+#define __STM32373C_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+#include "stm32_eval_legacy.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+      
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_WAKEUP = 0,
+  BUTTON_TAMPER = 1,
+  BUTTON_KEY = 2,
+  BUTTON_RIGHT = 3,
+  BUTTON_LEFT = 4,
+  BUTTON_UP = 5,
+  BUTTON_DOWN = 6,
+  BUTTON_SEL = 7
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief  Define for STM32373C_EVAL board  
+  */ 
+#if !defined (USE_STM32373C_EVAL)
+ #define USE_STM32373C_EVAL
+#endif
+
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_0
+#define LED1_GPIO_PORT                   GPIOC
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOC
+  
+#define LED2_PIN                         GPIO_Pin_1
+#define LED2_GPIO_PORT                   GPIOC
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOC
+  
+#define LED3_PIN                         GPIO_Pin_2
+#define LED3_GPIO_PORT                   GPIOC
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOC
+  
+#define LED4_PIN                         GPIO_Pin_3
+#define LED4_GPIO_PORT                   GPIOC
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOC
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          7
+
+/**
+ * @brief Tamper push-button
+ */
+#define TAMPER_BUTTON_PIN                GPIO_Pin_0
+#define TAMPER_BUTTON_GPIO_PORT          GPIOA
+#define TAMPER_BUTTON_GPIO_CLK           RCC_AHBPeriph_GPIOA
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line0
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOA
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource0
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI0_IRQn
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_2
+#define KEY_BUTTON_GPIO_PORT             GPIOA
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOA
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line2
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOA
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource2
+#define KEY_BUTTON_EXTI_IRQn             EXTI2_TS_IRQn
+
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_9
+#define RIGHT_BUTTON_GPIO_PORT           GPIOF
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOF
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line9
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOF
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource9
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI9_5_IRQn
+
+/**
+ * @brief Joystick Left push-button
+ */
+#define LEFT_BUTTON_PIN                  GPIO_Pin_4
+#define LEFT_BUTTON_GPIO_PORT            GPIOF
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOF
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line4
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOF
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource4
+#define LEFT_BUTTON_EXTI_IRQn            EXTI4_IRQn  
+
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_10
+#define UP_BUTTON_GPIO_PORT              GPIOF
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOF
+#define UP_BUTTON_EXTI_LINE              EXTI_Line10
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOF
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource10
+#define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Down push-button
+ */  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_2
+#define DOWN_BUTTON_GPIO_PORT            GPIOF
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOF
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line2
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOF
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource2
+#define DOWN_BUTTON_EXTI_IRQn            EXTI2_TS_IRQn  
+
+/**
+ * @brief Joystick Sel push-button
+ */
+#define SEL_BUTTON_PIN                   GPIO_Pin_6
+#define SEL_BUTTON_GPIO_PORT             GPIOE
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line6
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource6
+#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn 
+
+/**
+  * @}
+  */ 
+
+
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             1
+
+/**
+ * @brief Definition for COM port1, connected to USART2
+ */ 
+#define EVAL_COM1                        USART2
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
+
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource5
+#define EVAL_COM1_TX_AF                  GPIO_AF_7
+
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource6
+#define EVAL_COM1_RX_AF                  GPIO_AF_7
+
+#define EVAL_COM1_CTS_PIN                GPIO_Pin_3
+#define EVAL_COM1_CTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_CTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_CTS_SOURCE             GPIO_PinSource3
+#define EVAL_COM1_CTS_AF                 GPIO_AF_7
+
+#define EVAL_COM1_RTS_PIN                GPIO_Pin_4
+#define EVAL_COM1_RTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_RTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RTS_SOURCE             GPIO_PinSource4
+#define EVAL_COM1_RTS_AF                 GPIO_AF_7
+   
+#define EVAL_COM1_IRQn                   USART2_IRQn
+   
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_SD_SPI
+  * @{
+  */
+/**
+  * @brief  SD SPI Interface pins
+  */
+#define SD_SPI                           SPI3
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI3
+#define SD_SPI_SCK_PIN                   GPIO_Pin_10                  /* PC.10 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOC                        /* GPIOC */
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOC
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource10
+#define SD_SPI_SCK_AF                    GPIO_AF_6
+
+#define SD_SPI_MISO_PIN                  GPIO_Pin_11                  /* PC.11 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOC                        /* GPIOC */
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOC
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource11
+#define SD_SPI_MISO_AF                   GPIO_AF_6
+
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_12                  /* PC.12 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOC                        /* GPIOC */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOC
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource12
+#define SD_SPI_MOSI_AF                   GPIO_AF_6
+
+#define SD_CS_PIN                        GPIO_Pin_2                  /* PE.02 */
+#define SD_CS_GPIO_PORT                  GPIOE                       /* GPIOE */
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOE
+
+   
+#define SD_DETECT_PIN                    GPIO_Pin_3                  /* PE.03  */
+#define SD_DETECT_EXTI_LINE              EXTI_Line3
+#define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource3
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define SD_DETECT_EXTI_IRQn              EXTI3_IRQn
+
+/**
+  * @}
+  */
+  
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  LM75 Temperature Sensor I2C Interface pins
+  */
+#define LM75_I2C                         I2C2
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C2
+   
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_9                  /* PA.09 */
+#define LM75_I2C_SCL_GPIO_PORT           GPIOA                       /* GPIOA */
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOA
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource9
+#define LM75_I2C_SCL_AF                  GPIO_AF_4
+   
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_10                 /* PA.10 */
+#define LM75_I2C_SDA_GPIO_PORT           GPIOA                       /* GPIOA */
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOA
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource10
+#define LM75_I2C_SDA_AF                  GPIO_AF_4
+   
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_8                  /* PA.08 */
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOA                       /* GPIOA */
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOA
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource8
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_4
+/**
+  * @}
+  */
+   
+/** @addtogroup STM32373C_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */   
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+#define sEE_I2C                          I2C2
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C2
+   
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_9                  /* PA.09 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOA                       /* GPIOA */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOA
+#define sEE_I2C_SCL_SOURCE               GPIO_PinSource9
+#define sEE_I2C_SCL_AF                   GPIO_AF_4
+
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_10                 /* PA.10 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOA                       /* GPIOA */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOA
+#define sEE_I2C_SDA_SOURCE               GPIO_PinSource10
+#define sEE_I2C_SDA_AF                   GPIO_AF_4
+
+/**
+  * @}
+  */   
+   
+/** @defgroup STM32373C_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void LM75_LowLevel_DeInit(void);
+void LM75_LowLevel_Init(void);
+void sEE_I2C_LowLevel_DeInit(void);
+void sEE_I2C_LowLevel_Init(void); 
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32373C_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.c
new file mode 100644
index 0000000..351a4b5
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.c
@@ -0,0 +1,1405 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_audio_codec.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file includes the low layer driver for CS43L22 Audio Codec
+  *          available on STM32373C_EVAL evaluation board(MB988).  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*==============================================================================================================================
+                                             User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver supports STM32F37x devices on STM32373C_EVAL (MB988) Evaluation boards.
+
+   - Configure the options in file stm32373c_eval_audio_codec.h in the section CONFIGURATION.
+      Refer to the sections 2 and 3 to have more details on the possible configurations.
+
+   - Call the function EVAL_AUDIO_Init(
+                                    OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, 
+                                                 OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or 
+                                                 OUTPUT_DEVICE_BOTH)
+                                    Volume: initial volume to be set (0 is min (mute), 100 is max (100%)
+                                    AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...)
+                                     this parameter is relative to the audio file/stream type.
+                                   )
+      This function configures all the hardware required for the audio application (codec, I2C, I2S, 
+      GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK.
+      if the returned value is different from 0 or the function is stuck then the communication with
+      the codec has failed (try to un-plug the power or reset device in this case).
+      + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream.
+      + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream.
+      + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented 
+         into the audio jack on the evaluation board). When the Headphone is connected it is used
+         as output. When the headphone is disconnected from the audio jack, the output is
+         automatically switched to Speaker.
+      + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream
+         at the same time.
+
+   - Call the function EVAL_AUDIO_Play(
+                                  pBuffer: pointer to the audio data file address
+                                  Size: size of the buffer to be sent in Bytes
+                                 )
+      to start playing (for the first time) from the audio file/stream.
+
+   - Call the function EVAL_AUDIO_PauseResume(
+                                         Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or 
+                                               any value different from 0) to resume playing.
+                                         )
+       Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called
+          for resume (it is not allowed to call EVAL_AUDIO_Play() in this case).
+       Note. This function should be called only when the audio file is played or paused (not stopped).
+
+   - For each mode, you may need to implement the relative callback functions into your code.
+      The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in 
+      the stm32373c_eval_audio_codec.h file. (refer to the example for more details on the callbacks implementations)
+
+   - To Stop playing, to modify the volume level or to mute, use the functions
+       EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute().
+
+   - The driver API and the callback functions are at the end of the stm32373c_eval_audio_codec.h file.
+ 
+
+   Driver architecture:
+   --------------------
+   This driver is composed of three main layers:
+     o High Audio Layer: consists of the function API exported in the stm32373c_eval_audio_codec.h file
+       (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...)
+     o Codec Control layer: consists of the functions API controlling the audio codec (CS43L22) and 
+       included as local functions in file stm32373c_eval_audio_codec.c (Codec_Init(), Codec_Play() ...)
+     o Media Access Layer (MAL): which consists of functions allowing to access the media containing/
+       providing the audio file/stream. These functions are also included as local functions into
+       the stm32373c_eval_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...)
+    Each set of functions (layer) may be implemented independently of the others and customized when 
+    needed.    
+
+2. Modes description:
+---------------------
+     + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location.
+     + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a 
+        memory location or from a device at real time (double buffer could be used).
+
+3. DMA interrupts description:
+------------------------------
+     + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has finished the transfer.
+     + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has reached the half of the buffer transfer (generally, it is useful 
+        to load the first half of buffer while DMA is loading from the second half).
+     + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer.
+
+4. Known Limitations:
+---------------------
+   1- When using the Speaker, if the audio file quality is not high enough, the speaker output
+      may produce high and uncomfortable noise level. To avoid this issue, to use speaker
+      output properly, try to increase audio file sampling rate (typically higher than 48KHz).
+      This operation will lead to larger file size.
+   2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some
+      user interrupt routines (in this case, interrupts could be disabled just before the start of 
+      communication then re-enabled when it is over). Note that this communication is only done at
+      the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is 
+      performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is 
+      required with the audio codec.
+  3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, 
+     File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.
+  4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice 
+     on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing).
+  5- Supports only 16-bit audio data size.
+===============================================================================================================================*/
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval_audio_codec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL_AUDIO_CODEC
+  * @brief       This file includes the low layer driver for CS43L22 Audio Codec
+  *              available on STM32373C_EVAL evaluation board(MB988).
+  * @{
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Defines
+  * @{
+  */ 
+
+/* Mask for the bit EN of the I2S CFGR register */
+#define I2S_ENABLE_MASK                 0x0400
+
+/* Delay for the Codec to be correctly reset */
+#define CODEC_RESET_DELAY               0x4FFF
+
+/* Codec audio Standards */
+#ifdef I2S_STANDARD_PHILLIPS
+ #define  CODEC_STANDARD                0x04
+ #define I2S_STANDARD                   I2S_Standard_Phillips         
+#elif defined(I2S_STANDARD_MSB)
+ #define  CODEC_STANDARD                0x00
+ #define I2S_STANDARD                   I2S_Standard_MSB    
+#elif defined(I2S_STANDARD_LSB)
+ #define  CODEC_STANDARD                0x08
+ #define I2S_STANDARD                   I2S_Standard_LSB    
+#else 
+ #error "Error: No audio communication standard selected !"
+#endif /* I2S_STANDARD */
+
+/* The 7 bits Codec address (sent through I2C interface) */
+#define CODEC_ADDRESS                   0x94  /* b00100111 */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Variables
+  * @{
+  */
+/* This structure is declared global because it is handled by two different functions */
+DMA_InitTypeDef DMA_InitStructure; 
+DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure;
+
+uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */
+uint32_t AudioRemSize   = 0xFFFF; /* This variable holds the remaining data in audio file */
+uint16_t *CurrentPos;             /* This variable holds the current position of audio pointer */
+
+__IO uint32_t  CODECTimeout = CODEC_LONG_TIMEOUT;   
+__IO uint8_t OutputDev = 0;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Private_Functions
+  * @{
+  */ 
+
+/*----------------------------------------------------------------------------
+                           Audio Codec functions 
+  ----------------------------------------------------------------------------*/
+/* High Layer codec functions */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+static uint32_t Codec_DeInit(void);
+static uint32_t Codec_Play(void);
+static uint32_t Codec_PauseResume(uint32_t Cmd);
+static uint32_t Codec_Stop(uint32_t Cmd);
+static uint32_t Codec_VolumeCtrl(uint8_t Volume);
+static uint32_t Codec_Mute(uint32_t Cmd);
+/* Low layer codec functions */
+static void     Codec_CtrlInterface_Init(void);
+static void     Codec_CtrlInterface_DeInit(void);
+static void     Codec_AudioInterface_Init(uint32_t AudioFreq);
+static void     Codec_AudioInterface_DeInit(void);
+static void     Codec_Reset(void);
+static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue);
+static uint32_t Codec_ReadRegister(uint8_t RegisterAddr);
+static void     Codec_GPIO_Init(void);
+static void     Codec_GPIO_DeInit(void);
+static void     Delay(__IO uint32_t nCount);
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                   MAL (Media Access Layer) functions 
+  ----------------------------------------------------------------------------*/
+/* Peripherals configuration functions */
+static void     Audio_MAL_Init(void);
+static void     Audio_MAL_DeInit(void);
+static void     Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr);
+static void     Audio_MAL_Stop(void);
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief  Configure the audio peripherals.
+  * @param  OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{    
+  /* Perform low layer Codec initialization */
+  if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0)
+  {
+    return 1;                
+  }
+  else
+  {    
+    /* I2S data transfer preparation:
+    Prepare the Media to be used for the audio transfer from memory to I2S peripheral */
+    Audio_MAL_Init();
+    
+    /* Return 0 when all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Deinitializes all the resources used by the codec (those initialized
+  *         by EVAL_AUDIO_Init() function) EXCEPT the I2C resources since they are 
+  *         used by the IOExpander as well (and eventually other modules). 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_DeInit(void)
+{ 
+  /* DeInitialize the Media layer */
+  Audio_MAL_DeInit();
+  
+  /* DeInitialize Codec */  
+  Codec_DeInit();  
+  
+  return 0;
+}
+
+/**
+  * @brief  Starts playing audio stream from a data buffer for a determined size. 
+  * @param  pBuffer: Pointer to the buffer 
+  * @param  Size: Number of audio data BYTES.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size)
+{
+  /* Set the total number of data to be played (count in half-word) */
+  AudioTotalSize = Size/2;
+
+  /* Call the audio Codec Play function */
+  Codec_Play();
+  
+  /* Update the Media layer and enable it for play */  
+  Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2)));
+  
+  /* Update the remaining number of data to be played */
+  AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize);
+  
+  /* Update the current audio pointer position */
+  CurrentPos = pBuffer + DMA_MAX(AudioTotalSize);
+  
+  return 0;
+}
+
+/**
+  * @brief  This function Pauses or Resumes the audio file stream. In case
+  *         of using DMA, the DMA Pause feature is used. In all cases the I2S 
+  *         peripheral is disabled. 
+  * 
+  * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only
+  *          this function should be called for resume (use of EVAL_AUDIO_Play() 
+  *          function for resume could lead to unexpected behavior).
+  * 
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd)
+{    
+  /* Call the Audio Codec Pause/Resume function */
+  if (Codec_PauseResume(Cmd) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call the Media layer pause/resume function */
+    Audio_MAL_PauseResume(Cmd, 0);
+    
+    /* Return 0 if all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Stops audio playing and Power down the Audio Codec. 
+  * @param  Option: could be one of the following parameters 
+  *           - CODEC_PDWN_SW: for software power off (by writing registers). 
+  *                            Then no need to reconfigure the Codec after power on.
+  *           - CODEC_PDWN_HW: completely shut down the codec (physically). 
+  *                            Then need to reconfigure the Codec after power on.  
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Stop(uint32_t Option)
+{
+  /* Call Audio Codec Stop function */
+  if (Codec_Stop(Option) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call Media layer Stop function */
+    Audio_MAL_Stop();
+    
+    /* Update the remaining data number */
+    AudioRemSize = AudioTotalSize;    
+    
+    /* Return 0 when all operations are correctly done */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Controls the current audio volume level. 
+  * @param  Volume: Volume level to be set in percentage from 0% to 100% (0 for 
+  *         Mute and 100 for Max volume level).
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume)
+{
+  /* Call the codec volume control function with converted volume value */
+  return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume)));
+}
+
+/**
+  * @brief  Enables or disables the MUTE mode by software 
+  * @param  Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to 
+  *         unmute the codec and restore previous volume level.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Mute(uint32_t Cmd)
+{ 
+  /* Call the Codec Mute function */
+  return (Codec_Mute(Cmd));
+}
+
+/**
+  * @brief  This function handles main Media layer interrupt. 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+void Audio_MAL_IRQHandler(void)
+{    
+#ifndef AUDIO_MAL_MODE_NORMAL
+  uint16_t *pAddr = (uint16_t *)CurrentPos;
+  uint32_t Size = AudioRemSize;
+#endif /* AUDIO_MAL_MODE_NORMAL */
+  
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+  /* Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TC) != RESET)
+  {     
+ #ifdef AUDIO_MAL_MODE_NORMAL
+    /* Check if the end of file has been reached */
+    if (AudioRemSize > 0)
+    {      
+      /* Wait the DMA Channel to be effectively disabled */
+      while (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TC) != SET)
+      {}
+      
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);  
+      
+      /* Re-Configure the buffer address and size */
+      DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) CurrentPos;
+      DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize));
+      
+      /* Configure the DMA Channel with the new parameters */
+      DMA_Init(AUDIO_MAL_DMA_CHANNEL , &DMA_InitStructure);
+      
+      /* Enable the I2S DMA Channel */
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL , ENABLE);    
+      
+      /* Update the current pointer position */
+      CurrentPos += DMA_MAX(AudioRemSize);        
+      
+      /* Update the remaining number of data to be played */
+      AudioRemSize -= DMA_MAX(AudioRemSize);    
+    }
+    else
+    {
+      /* Disable the I2S DMA Channel */
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL , DISABLE);   
+      
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);       
+      
+      /* Manage the remaining file size and new address offset: This function 
+      should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+      EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0);       
+    }
+    
+ #elif defined(AUDIO_MAL_MODE_CIRCULAR)
+    /* Manage the remaining file size and new address offset: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_TransferComplete_CallBack(pAddr, Size);    
+    
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC);
+ #endif /* AUDIO_MAL_MODE_NORMAL */  
+  }
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+
+#ifdef AUDIO_MAL_DMA_IT_HT_EN  
+  /* Half Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_HT) != RESET)
+  {
+    /* Manage the remaining file size and new address offset: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size);    
+   
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_HT);    
+  }
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+  
+#ifdef AUDIO_MAL_DMA_IT_TE_EN  
+  /* FIFO Error interrupt */
+  if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_TE) != RESET) || \
+     (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_FE) != RESET) || \
+     (DMA_GetFlagStatus(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_DME) != RESET))
+    
+  {
+    /* Manage the error generated on DMA FIFO: This function 
+       should be coded by user (its prototype is already declared in stm32_eval_audio_codec.h) */  
+    EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr);    
+    
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_CHANNEL, AUDIO_MAL_DMA_FLAG_TE | AUDIO_MAL_DMA_FLAG_FE | \
+                                        AUDIO_MAL_DMA_FLAG_DME);
+  }  
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+}
+
+/*============================================================================
+                CS43L22 Audio Codec Control Functions
+  ============================================================================*/
+/**
+  * @brief  Initializes the audio codec and all related interfaces (control 
+  *         interface: I2C and audio interface: I2S)
+  * @param  OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{
+  uint32_t counter = 0; 
+
+  /* Configure the Codec related IOs */
+  Codec_GPIO_Init();   
+  
+  /* Reset the Codec Registers */
+  Codec_Reset();
+
+  /* Initialize the Control interface of the Audio Codec */
+  Codec_CtrlInterface_Init();     
+  
+  /* Keep Codec powered OFF */
+  counter += Codec_WriteRegister(0x02, 0x01);  
+
+  switch (OutputDevice)
+  {
+    case OUTPUT_DEVICE_SPEAKER:
+      counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+      OutputDev = 0xFA;
+      break;
+      
+    case OUTPUT_DEVICE_HEADPHONE:
+      counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+      OutputDev = 0xAF;
+      break;
+      
+    case OUTPUT_DEVICE_BOTH:
+      counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+      OutputDev = 0xAA;
+      break;
+      
+    case OUTPUT_DEVICE_AUTO:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+      
+    default:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+  }
+  
+  /* Clock configuration: Auto detection */  
+  counter += Codec_WriteRegister(0x05, 0x81);
+  
+  /* Set the Slave Mode and the audio Standard */  
+  counter += Codec_WriteRegister(0x06, CODEC_STANDARD);
+      
+  /* Set the Master volume */
+  Codec_VolumeCtrl(Volume);
+
+  /* If the Speaker is enabled, set the Mono mode and volume attenuation level */
+  if (OutputDevice != OUTPUT_DEVICE_HEADPHONE)
+  {
+    /* Set the Speaker Mono mode */  
+    counter += Codec_WriteRegister(0x0F , 0x06);
+    
+    /* Set the Speaker attenuation level */  
+    counter += Codec_WriteRegister(0x24, 0x00);
+    counter += Codec_WriteRegister(0x25, 0x00);
+  }
+  
+  /* Power on the Codec */
+  counter += Codec_WriteRegister(0x02, 0x9E);  
+  
+  /* Additional configuration for the CODEC. These configurations are done to reduce
+      the time needed for the Codec to power off. If these configurations are removed, 
+      then a long delay should be added between powering off the Codec and switching 
+      off the I2S peripheral MCLK clock (which is the operating clock for Codec).
+      If this delay is not inserted, then the codec will not shut down properly and
+      it results in high noise after shut down. */
+  
+  /* Disable the analog soft ramp */
+  counter += Codec_WriteRegister(0x0A, 0x00);
+  /* Disable the digital soft ramp */
+  counter += Codec_WriteRegister(0x0E, 0x04);
+  /* Disable the limiter attack level */
+  counter += Codec_WriteRegister(0x27, 0x00);
+  /* Adjust Bass and Treble levels */
+  counter += Codec_WriteRegister(0x1F, 0x0F);
+  /* Adjust PCM volume level */
+  counter += Codec_WriteRegister(0x1A, 0x0A);
+  counter += Codec_WriteRegister(0x1B, 0x0A);
+
+  /* Configure the I2S peripheral */
+  Codec_AudioInterface_Init(AudioFreq);  
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Restore the audio codec state to default state and free all used 
+  *         resources.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_DeInit(void)
+{
+  uint32_t counter = 0; 
+
+  /* Reset the Codec Registers */
+  Codec_Reset();  
+  
+  /* Keep Codec powered OFF */
+  counter += Codec_WriteRegister(0x02, 0x01);    
+  
+  /* Deinitialize all use GPIOs */
+  Codec_GPIO_DeInit();
+
+  /* Disable the Codec control interface */
+  Codec_CtrlInterface_DeInit();
+  
+  /* Deinitialize the Codec audio interface (I2S) */
+  Codec_AudioInterface_DeInit(); 
+  
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Start the audio Codec play feature.
+  * @note   For this codec no Play options are required.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Play(void)
+{
+  /* 
+     No actions required on Codec level for play command
+     */  
+
+  /* Return communication control value */
+  return 0;  
+}
+
+/**
+  * @brief  Pauses and resumes playing on the audio codec.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_PauseResume(uint32_t Cmd)
+{
+  uint32_t counter = 0;   
+  
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  { 
+    /* Mute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_ON);
+
+    /* Put the Codec in Power save mode */    
+    counter += Codec_WriteRegister(0x02, 0x01);    
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Unmute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_OFF);
+    
+    counter += Codec_WriteRegister(0x04, OutputDev);
+    
+    /* Exit the Power save mode */
+    counter += Codec_WriteRegister(0x02, 0x9E); 
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Stops audio Codec playing. It powers down the codec.
+  * @param  CodecPdwnMode: selects the  power down mode.
+  *          - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this 
+  *                           mode the codec keeps the previous initialization
+  *                           (no need to re-Initialize the codec registers).
+  *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
+  *                           mode, the codec is set to default configuration 
+  *                           (user should re-Initialize the codec in order to 
+  *                            play again the audio stream).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Stop(uint32_t CodecPdwnMode)
+{
+  uint32_t counter = 0;   
+
+  /* Mute the output first */
+  Codec_Mute(AUDIO_MUTE_ON);
+  
+  if (CodecPdwnMode == CODEC_PDWN_SW)
+  {    
+    /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
+    counter += Codec_WriteRegister(0x02, 0x9F);
+  }
+  else /* CODEC_PDWN_HW */
+  { 
+    /* Power down the components */
+    counter += Codec_WriteRegister(0x02, 0x9F);
+
+    /* Wait at least 100us */
+    Delay(0xFFF);
+
+    /* Reset The pin */
+    GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
+  }
+  
+  return counter;    
+}
+
+/**
+  * @brief  Sets higher or lower the codec volume level.
+  * @param  Volume: a byte value from 0 to 255 (refer to codec registers 
+  *         description for more details).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_VolumeCtrl(uint8_t Volume)
+{
+  uint32_t counter = 0;
+  
+  if (Volume > 0xE6)
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume - 0xE7); 
+    counter += Codec_WriteRegister(0x21, Volume - 0xE7);     
+  }
+  else
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume + 0x19); 
+    counter += Codec_WriteRegister(0x21, Volume + 0x19); 
+  }
+
+  return counter;  
+}
+
+/**
+  * @brief  Enables or disables the mute feature on the audio codec.
+  * @param  Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
+  *             mute mode.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Mute(uint32_t Cmd)
+{
+  uint32_t counter = 0;  
+  
+  /* Set the Mute mode */
+  if (Cmd == AUDIO_MUTE_ON)
+  {
+    counter += Codec_WriteRegister(0x04, 0xFF);
+  }
+  else /* AUDIO_MUTE_OFF Disable the Mute */
+  {
+    counter += Codec_WriteRegister(0x04, OutputDev);
+  }
+  
+  return counter; 
+}
+
+/**
+  * @brief  Resets the audio codec. It restores the default configuration of the 
+  *         codec (this function shall be called before initializing the codec).
+  * @note   This function calls an external driver function: The IO Expander driver.
+  * @param  None
+  * @retval None
+  */
+static void Codec_Reset(void)
+{
+  /* Power Down the codec */
+  GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
+
+  /* wait for a delay to insure registers erasing */
+  Delay(CODEC_RESET_DELAY);
+
+  /* Power on the codec */
+  GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_SET);
+}
+
+/**
+  * @brief  Switch dynamically (while audio file is played) the output target 
+  *         (speaker or headphone).
+  * @note   This function modifies a global variable of the audio codec driver: OutputDev.
+  * @param  Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
+  *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t Codec_SwitchOutput(uint8_t Output)
+{
+  uint8_t counter = 0;
+  
+  switch (Output) 
+  {
+    case OUTPUT_DEVICE_SPEAKER:
+      counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+      OutputDev = 0xFA;
+      break;
+      
+    case OUTPUT_DEVICE_HEADPHONE:
+      counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+      OutputDev = 0xAF;
+      break;
+      
+    case OUTPUT_DEVICE_BOTH:
+      counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+      OutputDev = 0xAA;
+      break;
+      
+    case OUTPUT_DEVICE_AUTO:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;    
+      
+    default:
+      counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+      OutputDev = 0x05;
+      break;
+  }
+  
+  return counter;
+}
+
+/**
+  * @brief  Writes a Byte to a given register into the audio codec through the 
+            control interface (I2C)
+  * @param  RegisterAddr: The address (location) of the register to be written.
+  * @param  RegisterValue: the Byte value to be written into destination register.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t result = 0;
+  
+  /* Test on BUSY Flag */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_BUSY) != RESET) 
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 2, I2C_AutoEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;  
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterAddr );
+    
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }  
+  
+  /* Write data to TXDR */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterValue);
+  
+  /* Wait until STOPF flag is set */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_STOPF) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }   
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(CODEC_I2C, I2C_ICR_STOPCF);
+
+#ifdef VERIFY_WRITTENDATA
+  /* Verify that the data has been correctly written */  
+  result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1;
+#endif /* VERIFY_WRITTENDATA */
+
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return result;
+}
+
+/**
+  * @brief  Reads and returns the value of an audio codec register through the
+  *         control interface (I2C).
+  * @param  RegisterAddr: Address of the register to be read.
+  * @retval Value of the register to be read or dummy value if the communication
+  *         fails.
+  */
+static uint32_t Codec_ReadRegister(uint8_t RegisterAddr)
+{
+   uint32_t result = 0;
+  
+  /* Test on BUSY Flag */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_BUSY) != RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 1, I2C_SoftEnd_Mode, I2C_Generate_Start_Write);
+  
+  /* Wait until TXIS flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TXIS) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Send Register address */
+  I2C_SendData(CODEC_I2C, (uint8_t)RegisterAddr);
+  
+  /* Wait until TC flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_TC) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }  
+  
+  /* Configure slave address, nbytes, reload, end mode and start or stop generation */
+  I2C_TransferHandling(CODEC_I2C, CODEC_ADDRESS, 1, I2C_AutoEnd_Mode, I2C_Generate_Start_Read);
+  
+  /* Wait until RXNE flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;  
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_RXNE) == RESET)  
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Read data from RXDR */
+  result = I2C_ReceiveData(CODEC_I2C);  
+  
+  /* Wait until STOPF flag is set */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_ISR_STOPF) == RESET) 
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+  
+  /* Clear STOPF flag */
+  I2C_ClearFlag(CODEC_I2C, I2C_ICR_STOPCF);
+
+  /* Return the byte read from Codec */
+  return result;
+}
+
+/**
+  * @brief  Initializes the Audio Codec control interface (I2C).
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_Init(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* Configure the I2C clock source. The clock is derived from the SYSCLK */
+  RCC_I2CCLKConfig(RCC_I2C2CLK_SYSCLK);
+  
+  /* Enable the CODEC_I2C peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE);
+  
+  /* CODEC_I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x33;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = CODEC_I2C_TIMING;
+  
+  /* Enable the I2C peripheral */  
+  I2C_Init(CODEC_I2C, &I2C_InitStructure);
+  I2C_Cmd(CODEC_I2C, ENABLE);
+}
+
+/**
+  * @brief  Restore the Audio Codec control interface to its default state.
+  *         This function doesn't de-initialize the I2C because the I2C peripheral
+  *         may be used by other modules.
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_DeInit(void)
+{
+  /* Disable the I2C peripheral */ /* This step is not done here because 
+     the I2C interface can be used by other modules */
+  /* I2C_DeInit(CODEC_I2C); */
+}
+
+/**
+  * @brief  Initializes the Audio Codec audio interface (I2S)
+  * @note   This function assumes that the I2S input clock (through PLL_R in 
+  *         Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
+  *         is already configured and ready to be used.    
+  * @param  AudioFreq: Audio frequency to be configured for the I2S peripheral. 
+  * @retval None
+  */
+static void Codec_AudioInterface_Init(uint32_t AudioFreq)
+{
+  I2S_InitTypeDef I2S_InitStructure;
+
+  /* Enable the CODEC_I2S peripheral clock */
+  RCC_APB2PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
+
+  /* CODEC_I2S peripheral configuration */
+  SPI_I2S_DeInit(CODEC_I2S);
+  I2S_InitStructure.I2S_AudioFreq = AudioFreq;
+  I2S_InitStructure.I2S_Standard = I2S_STANDARD;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+#ifdef CODEC_MCLK_ENABLED
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
+#elif defined(CODEC_MCLK_DISABLED)
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+#else
+ #error "No selection for the MCLK output has been defined !"
+#endif /* CODEC_MCLK_ENABLED */
+
+  /* Initialize the I2S peripheral with the structure above */
+  I2S_Init(CODEC_I2S, &I2S_InitStructure);
+
+  /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function 
+       or by user functions if DMA mode not enabled */  
+}
+
+/**
+  * @brief  Restores the Audio Codec audio interface to its default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_AudioInterface_DeInit(void)
+{
+  /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+  
+  /* Deinitialize the CODEC_I2S peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+  
+  /* Disable the CODEC_I2S peripheral clock */
+  RCC_APB2PeriphClockCmd(CODEC_I2S_CLK, DISABLE); 
+}
+
+/**
+  * @brief Initializes IOs used by the Audio Codec (on the control and audio 
+  *        interfaces).
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Enable Reset GPIO Clock */
+  RCC_AHBPeriphClockCmd(AUDIO_RESET_GPIO_CLK,ENABLE);
+  
+  /* Audio reset pin configuration ---------------------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = AUDIO_RESET_PIN; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(AUDIO_RESET_GPIO, &GPIO_InitStructure);
+  
+  /* Enable I2S and I2C GPIO clocks */
+  RCC_AHBPeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE);
+  
+  /* Connect pins to I2C peripheral */
+  GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF);
+  
+  /* CODEC_I2C SCL and SDA pins configuration ----------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN | CODEC_I2C_SDA_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2C_GPIO, &GPIO_InitStructure);     
+  
+  
+  /* CODEC_I2S pins configuration: WS, SCK and SD pins -------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN | CODEC_I2S_WS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+  
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF);
+  
+ #ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins configuration: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);   
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); 
+ #endif /* CODEC_MCLK_ENABLED */   
+}
+
+/**
+  * @brief  Restores the IOs used by the Audio Codec interface to their default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_DeInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /* Deinitialize all the GPIOs used by the driver (EXCEPT the I2C IOs since 
+     they are used by the IOExpander as well) */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN | CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);     
+  
+#ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins deinitialization: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; 
+  GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);   
+  /* Disconnect pins from I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); 
+#endif /* CODEC_MCLK_ENABLED */    
+}
+
+/**
+  * @brief  Inserts a delay time (not accurate timing).
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void Delay( __IO uint32_t nCount)
+{
+  for (; nCount != 0; nCount--);
+}
+
+#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
+/**
+  * @brief  Basic management of the timeout situation.
+  * @param  None
+  * @retval None
+  */
+uint32_t Codec_TIMEOUT_UserCallback(void)
+{
+  /* The following code allows I2C error recovery and return to normal communication
+     if the error source doesn’t still exist (ie. hardware issue..) */
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* LCD_ErrLog("> I2C Timeout error occurred\n"); */
+
+  I2C_GenerateSTOP(CODEC_I2C, ENABLE);
+  I2C_SoftwareResetCmd(CODEC_I2C, ENABLE);
+  I2C_SoftwareResetCmd(CODEC_I2C, DISABLE);
+    
+  /* CODEC_I2C peripheral configuration */
+  I2C_DeInit(CODEC_I2C);
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x33;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
+  /* Enable the I2C peripheral */
+  I2C_Cmd(CODEC_I2C, ENABLE);  
+  I2C_Init(CODEC_I2C, &I2C_InitStructure);  
+
+  /* At this stage the I2C error should be recovered and device can communicate
+     again (except if the error source still exist).
+     User can implement mechanism (ex. test on max trial number) to manage situation
+     when the I2C can't recover from current error. */
+
+  /* LCD_UsrLog("> I2C error recovered.\n"); */
+
+  return 0;
+}
+#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
+
+/*============================================================================
+                Audio MAL Interface Control Functions
+  ============================================================================*/
+
+/**
+  * @brief  Initializes and prepares the Media to perform audio data transfer 
+  *         from Media to the I2S peripheral.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Init(void)  
+{   
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;
+#endif
+  
+  /* Enable the DMA clock */
+  RCC_AHBPeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE); 
+  
+  /* Configure the DMA Channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+  /* Set the parameters to be configured */
+ 
+  DMA_InitStructure.DMA_PeripheralBaseAddr = CODEC_I2S_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;      /* This field will be configured in play function */
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;      /* This field will be configured in play function */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
+  DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; 
+#ifdef AUDIO_MAL_MODE_NORMAL
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+#elif defined(AUDIO_MAL_MODE_CIRCULAR)
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+#else
+  #error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
+#endif /* AUDIO_MAL_MODE_NORMAL */  
+  DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);  
+
+  /* Enable the selected DMA interrupts (selected in "stm32_eval_audio_codec.h" defines) */
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+#ifdef AUDIO_MAL_DMA_IT_HT_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_HT, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+#ifdef AUDIO_MAL_DMA_IT_TE_EN
+  DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+  
+  /* Enable the I2S DMA request */
+  SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+  
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  /* I2S DMA IRQ Channel configuration */
+  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+#endif 
+}
+
+/**
+  * @brief  Restore default state of the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_DeInit(void)  
+{   
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;  
+  
+  /* Deinitialize the NVIC interrupt for the I2S DMA Channel */
+  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
+  NVIC_Init(&NVIC_InitStructure);  
+#endif 
+  
+  /* Disable the DMA before the deinit */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  
+  /* Dinitialize the DMA Channel */
+  DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+  
+  /* The DMA clock is not disabled  */ 
+}
+
+/**
+  * @brief  Starts playing audio stream from the audio Media.
+  * @param  None
+  * @retval None
+  */
+void Audio_MAL_Play(uint32_t Addr, uint32_t Size)
+{   
+  /* Configure the buffer address and size */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Addr;
+  DMA_InitStructure.DMA_BufferSize = (uint32_t)Size/2;
+
+  /* Configure the DMA Channel with the new parameters */
+  DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);
+  
+  /* Enable the I2S DMA Channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+
+  /* If the I2S peripheral is still not enabled, enable it */
+  if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
+  {
+    I2S_Cmd(CODEC_I2S, ENABLE);
+  }   
+}
+
+/**
+  * @brief  Pauses or Resumes the audio stream playing from the Media.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *              from 0) to resume. 
+  * @param  Addr: Address from/at which the audio stream should resume/pause.
+  * @retval None
+  */
+static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr)
+{
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  {   
+    /* Disable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE);
+
+    /* Pause the I2S DMA Channel 
+        Note. For the STM32F37x devices, the DMA implements a pause feature, 
+              by disabling the channel, all configuration is preserved and data 
+              transfer is paused till the next enable of the channel.*/
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Enable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+  
+    /* Resume the I2S DMA Channel 
+        Note. For the STM32F37x devices, the DMA implements a pause feature, 
+              by disabling the channel, all configuration is preserved and data 
+              transfer is paused till the next enable of the channel.*/
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+    
+    /* If the I2S peripheral is still not enabled, enable it */
+    if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
+    {
+      I2S_Cmd(CODEC_I2S, ENABLE);
+    }    
+  }  
+}
+
+/**
+  * @brief  Stops audio stream playing on the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Stop(void)
+{   
+  /* Stop the Transfer on the I2S side: Stop and disable the DMA channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+
+  /* Clear all the DMA flags for the next transfer */
+  DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC|AUDIO_MAL_DMA_FLAG_HT|AUDIO_MAL_DMA_FLAG_TE);
+  
+  /*  
+           The I2S DMA requests are not disabled here.
+                                                            */
+  
+  /* In all modes, disable the I2S peripheral */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.h
new file mode 100644
index 0000000..6204868
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_audio_codec.h
@@ -0,0 +1,284 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_audio_codec.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32373c_eval_audio_codec.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_AUDIOCODEC_H
+#define __STM32373C_EVAL_AUDIOCODEC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+    
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC 
+  * @{
+  */    
+
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Exported_Types
+  * @{
+  */
+  
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Exported_Constants
+  * @{
+  */ 
+
+/*----------------------------------------------------------------------------
+             CONFIGURATION: Audio Codec Driver Configuration parameters
+  ----------------------------------------------------------------------------*/
+/* Audio Transfer mode (DMA, Interrupt or Polling) */
+#define AUDIO_MAL_MODE_NORMAL         /* Uncomment this line to enable the audio 
+                                         Transfer using DMA */
+/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio 
+                                         Transfer using DMA */
+
+/* For the DMA modes select the interrupt that will be used */
+#define AUDIO_MAL_DMA_IT_TC_EN   /* Uncomment this line to enable DMA Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_HT_EN */  /* Uncomment this line to enable DMA Half Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_TE_EN */  /* Uncomment this line to enable DMA Transfer Error interrupt */
+
+/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
+#define EVAL_AUDIO_IRQ_PREPRIO           0   /* Select the preemption priority level(0 is the highest) */
+#define EVAL_AUDIO_IRQ_SUBRIO            0   /* Select the sub-priority level (0 is the highest) */
+
+/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() 
+   function implemented in stm32373c_eval_audio_codec.c file.
+   Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                    OPTIONAL Configuration defines parameters
+  ----------------------------------------------------------------------------*/
+/* I2C clock speed configuration (in Hz) 
+  WARNING: 
+   Make sure that this define is not already declared in other files (ie. 
+  stm32373c_eval.h file). It can be used in parallel by other modules. */
+
+/* I2C TIMING Register define when I2C clock source is SYSCLK */
+/* set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define CODEC_I2C_TIMING             0xC062121F
+
+/* Uncomment defines below to select standard for audio communication between 
+  Codec and I2S peripheral */
+#define I2S_STANDARD_PHILLIPS
+/* #define I2S_STANDARD_MSB */
+/* #define I2S_STANDARD_LSB */
+
+/* Uncomment the defines below to select if the Master clock mode should be 
+  enabled or not */
+#define CODEC_MCLK_ENABLED
+/* #deine CODEC_MCLK_DISABLED */
+
+/* Uncomment this line to enable verifying data sent to codec after each write 
+  operation */
+#define VERIFY_WRITTENDATA 
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                    Hardware Configuration defines parameters
+  ----------------------------------------------------------------------------*/
+/* Audio Reset Pin definition */
+#define AUDIO_RESET_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define AUDIO_RESET_PIN                GPIO_Pin_11
+#define AUDIO_RESET_GPIO               GPIOD
+
+/* I2S peripheral configuration defines */
+#define CODEC_I2S                      SPI1
+#define CODEC_I2S_CLK                  RCC_APB2Periph_SPI1
+#define CODEC_I2S_ADDRESS              0x4001300C
+#define CODEC_I2S_GPIO_AF              GPIO_AF_5
+#define CODEC_I2S_IRQ                  SPI1_IRQn
+#define CODEC_I2S_GPIO_CLOCK           (RCC_AHBPeriph_GPIOC)
+#define CODEC_I2S_WS_PIN               GPIO_Pin_6
+#define CODEC_I2S_SCK_PIN              GPIO_Pin_7
+#define CODEC_I2S_SD_PIN               GPIO_Pin_9
+#define CODEC_I2S_MCK_PIN              GPIO_Pin_8
+#define CODEC_I2S_WS_PINSRC            GPIO_PinSource6
+#define CODEC_I2S_SCK_PINSRC           GPIO_PinSource7
+#define CODEC_I2S_SD_PINSRC            GPIO_PinSource9
+#define CODEC_I2S_MCK_PINSRC           GPIO_PinSource8
+#define CODEC_I2S_GPIO                 GPIOC
+#define CODEC_I2S_MCK_GPIO             GPIOC
+
+ /* I2S DMA channel definitions */
+#define AUDIO_MAL_DMA_CLOCK            RCC_AHBPeriph_DMA1
+#define AUDIO_MAL_DMA_CHANNEL          DMA1_Channel3
+#define AUDIO_MAL_DMA_IRQ              DMA1_Channel3_IRQn
+#define AUDIO_MAL_DMA_FLAG_TC          DMA1_FLAG_TC3
+#define AUDIO_MAL_DMA_FLAG_HT          DMA1_FLAG_HT3
+#define AUDIO_MAL_DMA_FLAG_TE          DMA1_FLAG_TE3
+
+#define Audio_MAL_IRQHandler           DMA1_Channel3_IRQHandler
+#define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord
+#define AUDIO_MAL_DMA_MEM_DATA_SIZE    DMA_MemoryDataSize_HalfWord
+#define DMA_MAX_SZE                    0xFFFF
+
+/* I2C peripheral configuration defines (control interface of the audio codec) */
+#define CODEC_I2C                      I2C2
+#define CODEC_I2C_CLK                  RCC_APB1Periph_I2C2
+#define CODEC_I2C_GPIO_CLOCK           RCC_AHBPeriph_GPIOB
+#define CODEC_I2C_GPIO_AF              GPIO_AF_4
+#define CODEC_I2C_GPIO                 GPIOA
+#define CODEC_I2C_SCL_PIN              GPIO_Pin_9
+#define CODEC_I2C_SDA_PIN              GPIO_Pin_10
+#define CODEC_I2S_SCL_PINSRC           GPIO_PinSource9
+#define CODEC_I2S_SDA_PINSRC           GPIO_PinSource10
+
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define CODEC_FLAG_TIMEOUT             ((uint32_t)0x1000)
+#define CODEC_LONG_TIMEOUT             ((uint32_t)(300 * CODEC_FLAG_TIMEOUT))
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+                        Audio Codec User defines
+  ----------------------------------------------------------------------------*/
+/* Codec output DEVICE */
+#define OUTPUT_DEVICE_SPEAKER         1
+#define OUTPUT_DEVICE_HEADPHONE       2
+#define OUTPUT_DEVICE_BOTH            3
+#define OUTPUT_DEVICE_AUTO            4
+
+/* Volume Levels values */
+#define DEFAULT_VOLMIN                0x00
+#define DEFAULT_VOLMAX                0xFF
+#define DEFAULT_VOLSTEP               0x04
+
+#define AUDIO_PAUSE                   0
+#define AUDIO_RESUME                  1
+
+/* Codec POWER DOWN modes */
+#define CODEC_PDWN_HW                 1
+#define CODEC_PDWN_SW                 2
+
+/* MUTE commands */
+#define AUDIO_MUTE_ON                 1
+#define AUDIO_MUTE_OFF                0
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Exported_Macros
+  * @{
+  */ 
+#define VOLUME_CONVERT(x)    ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100)))
+#define DMA_MAX(x)           (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_AUDIO_CODEC_Exported_Functions
+  * @{
+  */ 
+
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+uint32_t EVAL_AUDIO_DeInit(void);
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size);
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd);
+uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode);
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume);
+uint32_t EVAL_AUDIO_Mute(uint32_t Command);
+
+uint32_t Codec_SwitchOutput(uint8_t Output);
+
+/* User Callbacks: user has to implement these functions in his code if
+  they are needed. -----------------------------------------------------------*/
+
+/* This function is called when the requested data has been completely transferred.
+   In Normal mode (when  the define AUDIO_MAL_MODE_NORMAL is enabled) this function
+   is called at the end of the whole audio file.
+   In circular mode (when  the define AUDIO_MAL_MODE_CIRCULAR is enabled) this 
+   function is called at the end of the current buffer transmission. */
+void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when half of the requested buffer has been transferred 
+   This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR 
+   define is enabled)*/
+void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when an Interrupt due to transfer error on or peripheral
+   error occurs. */
+void EVAL_AUDIO_Error_CallBack(void* pData);
+
+/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...) on the Codec control interface (I2C).
+   You can use the default timeout callback implementation by uncommenting the 
+   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32373c_eval_audio_codec.h file.
+   Typically the user implementation of this callback should reset I2C peripheral
+   and re-initialize communication or in worst case reset all the application. */
+uint32_t Codec_TIMEOUT_UserCallback(void);
+void Audio_MAL_IRQHandler(void);
+void Audio_MAL_Play(uint32_t Addr, uint32_t Size);
+ 
+#endif /* __STM32373C_EVAL_AUDIOCODEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */    
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.c
new file mode 100644
index 0000000..1641cea
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.c
@@ -0,0 +1,2033 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_cec.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides all the STM32373C-EVAL HDMI-CEC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval_cec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+
+/** @defgroup STM32373C_EVAL_CEC
+  * @brief This file includes the CEC Stack driver for HDMI-CEC Module
+  *        of STM32373C-EVAL board
+  * @{
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Defines
+  * @{
+  */
+
+/* Uncomment the define to use the LSE as a source clock */
+/* #define LSE_SOURCE_CLK */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Variables
+  * @{
+  */
+
+__IO uint32_t ReceivedFrame = 0;
+__IO uint32_t SendFrame = 0;
+uint32_t BufferCount = 0, TxCounter = 0, RxCounter = 0;
+__IO uint8_t BufferPointer[15];
+__IO uint32_t ReceiveStatus = 0;
+__IO uint32_t SendStatus = 0;
+__IO uint8_t TransErrorCode = 0;
+uint8_t MyLogicalAddress = 0;
+uint16_t MyPhysicalAddress = 0;
+__IO uint8_t DeviceType = 0;
+#ifdef HDMI_CEC_USE_DDC
+uint8_t pBuffer[256];
+__IO uint16_t NumByteToRead = 255;
+#endif
+
+__IO uint8_t CECDevicesNumber = 0;
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_RX_MessageStructPrivate;
+HDMI_CEC_Message HDMI_CEC_TX_MessageStructure;
+
+__IO uint8_t FeatureOpcode = 0;
+__IO uint8_t AbortReason = 0;
+__IO uint8_t DeviceCount = 0;
+
+HDMI_CEC_Map HDMI_CEC_MapStruct;
+HDMI_CEC_Map HDMI_CEC_DeviceMap[14];
+
+/* CEC follower addresses */
+uint8_t* HDMI_CEC_Follower_String[13][2] =
+  {
+    {(uint8_t *)"         TV         ", (uint8_t *)"0"},
+    {(uint8_t *)" Recording Device 1 ", (uint8_t *)"0"},
+    {(uint8_t *)" Recording Device 2 ", (uint8_t *)"0"},
+    {(uint8_t *)"      Tuner 1       ", (uint8_t *)"0"},
+    {(uint8_t *)"  Playback Device 1 ", (uint8_t *)"0"},
+    {(uint8_t *)"    Audio System    ", (uint8_t *)"0"},
+    {(uint8_t *)"      Tuner 2       ", (uint8_t *)"0"},
+    {(uint8_t *)"      Tuner 3       ", (uint8_t *)"0"},
+    {(uint8_t *)"  Playback Device 2 ", (uint8_t *)"0"},
+    {(uint8_t *)" Recording Device 3 ", (uint8_t *)"0"},
+    {(uint8_t *)"      Tuner 4       ", (uint8_t *)"0"},
+    {(uint8_t *)"  Playback Device 3 ", (uint8_t *)"0"},
+    {(uint8_t *)"      Broadcast     ", (uint8_t *)"1"}
+  };
+
+/* EDID & CEA861 Extension */
+const uint8_t EDID_Structure[256] =
+{
+  /*-------------------------- Block0: 128Bytes ------------------------------*/
+  /* Header */
+  0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+  /* Vendor & Product Identification */
+  0x4C, 0x2D, 0x57, 0x03, 0x00, 0x00, 0x00, 0x00, 0x22, 0x11,
+  /* EDID Structure Version & Revision */
+  0x01, 0x03, 
+  /* Basic Display Parameters & Features */
+  0x80, 0x10, 0x09, 0x78, 0x0A, 
+  /* Color Characteristics */
+  0x1D, 0xED, 0xA7, 0x53, 0x34, 0xAC, 0x25, 0x12, 0x47, 0x4A,
+  /* Established Timings */
+  0x20, 0x00, 0x00,
+  /* Standard Timings */
+  0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+  0x01, 0x01, 0x01,
+  /* Byte Data Blocks*/
+  0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xA0, 
+  0x5A, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 
+  0x6E, 0x28, 0x55, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 
+  0xFD, 0x00, 0x17, 0x3D, 0x1A, 0x44, 0x17, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 
+  0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x53, 0x41, 0x4D, 0x53, 0x55, 0x4E, 
+  0x47, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
+  /* Extension Block Count */
+  0x01,
+  /* Checksum C */
+  0xF3,
+  /* ------------------------ Block1: 128Bytes------------------------------- */
+  /* Refer to CEA 861 Standard for definitions */
+  /* CEA 861 EXTENSION Block – Version 3 */
+  0x02, 0x03,
+  /* Byte number within this block where the 18-byte DTDs begin */
+  0x21,
+  /* Number of DTDs present */
+  0x00,
+  /* Start of Data Block Collection */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* IEEE Registration Identifier */
+  0x03, 0x0C, 0x00,
+  /* Vendor Specific Data: Physical Address */
+  0x10, 0x00,
+  /* Byte Data Blocks */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+  0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Function_Prototypes
+  * @{
+  */
+static HDMI_CEC_Error SinkPhysicalAddressDiscovery(void);
+static HDMI_CEC_Error SourcePhysicalAddressDiscovery(void);
+static HDMI_CEC_Error LogicalAddressAllocation(void);
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the HDMI CEC.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  CEC_InitTypeDef CEC_InitStructure;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint8_t sendcount = 0;
+  uint32_t  idx = 0;
+  
+#ifdef LSE_SOURCE_CLK
+  /* LSE */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+  PWR_BackupAccessCmd(ENABLE);
+  
+  RCC_LSEConfig(RCC_LSE_ON);
+  while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
+  {}
+  
+  RCC_CECCLKConfig(RCC_CECCLK_LSE);
+#endif
+  
+  for(idx=0; idx<12; idx++)
+  {
+    HDMI_CEC_Follower_String[idx][1] = (uint8_t *)"0";
+  }
+  
+  /* Enable CEC and PWR clocks */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CEC | RCC_APB1Periph_PWR, ENABLE);
+  
+  /* Enable CEC_LINE_GPIO clocks */
+  RCC_AHBPeriphClockCmd(HDMI_CEC_LINE_GPIO_CLK, ENABLE);
+  
+  /* Configure CEC_LINE_GPIO as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_LINE_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(HDMI_CEC_LINE_GPIO_PORT, &GPIO_InitStructure);
+  
+  GPIO_PinAFConfig(HDMI_CEC_LINE_GPIO_PORT,HDMI_CEC_LINE_PIN_SOURCE,HDMI_CEC_GPIO_AF);
+  
+  /* CEC DeInit */
+  CEC_DeInit();
+  
+  /* Configure CEC */
+  CEC_InitStructure.CEC_SignalFreeTime = CEC_SignalFreeTime_Standard/*CEC_SignalFreeTime_1T*/;
+  CEC_InitStructure.CEC_RxTolerance = CEC_RxTolerance_Standard;
+  CEC_InitStructure.CEC_StopReception = CEC_StopReception_Off;
+  CEC_InitStructure.CEC_BitRisingError = CEC_BitRisingError_Off;
+  CEC_InitStructure.CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
+  CEC_InitStructure.CEC_BRDNoGen = CEC_BRDNoGen_Off;
+  CEC_InitStructure.CEC_SFTOption = CEC_SFTOption_Off;
+  CEC_Init(&CEC_InitStructure);
+  
+  /* Disable Listen Mode */
+  CEC_ListenModeCmd(DISABLE);
+  
+  /* Enable CEC */
+  CEC_Cmd(ENABLE);
+  
+  if (HDMI_CEC_ROOT == 0x1)
+  {
+    /* Logical Address Allocation */
+    sendcount = 0;
+    errorstatus = LogicalAddressAllocation();
+    
+    while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+    {
+      sendcount++;
+      errorstatus = LogicalAddressAllocation();
+    }
+    
+    if (errorstatus != HDMI_CEC_OK)
+    {
+      /* Device Unregistered */
+      return(errorstatus);
+    }
+    
+    HDMI_CEC_CheckConnectedDevices();
+    
+    /* Set the CEC initiator address */
+    CEC_OwnAddressConfig(MyLogicalAddress);
+    
+    /* Sink Physical Address discovery */
+    errorstatus = SinkPhysicalAddressDiscovery();
+    
+    if (errorstatus != HDMI_CEC_OK)
+    {
+      /* Device not connected (Physical Address lost) */
+      return(errorstatus);
+    }
+  }
+  else
+  {
+    /* Source Physical Address discovery */
+    errorstatus = SourcePhysicalAddressDiscovery();
+    
+    if (errorstatus != HDMI_CEC_OK)
+    {
+      /* Device not connected (Physical Address lost) */
+      return(errorstatus);
+    }
+    
+    /* Logical Address Allocation */
+    sendcount = 0;
+    errorstatus = LogicalAddressAllocation();
+    
+    while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+    {
+      sendcount++;
+      errorstatus = LogicalAddressAllocation();
+    }
+    
+    if (errorstatus != HDMI_CEC_OK)
+    {
+      /* Device Unregistered */
+      return(errorstatus);
+    }
+    
+    HDMI_CEC_CheckConnectedDevices();
+    
+    /* Set the CEC initiator address */
+    CEC_OwnAddressConfig(MyLogicalAddress);
+  }
+  
+  /* Activate CEC interrupts associated to the set of TX flags */
+  CEC_ITConfig(CEC_IT_TXEND|CEC_IT_TXBR,ENABLE);
+  
+  /* Activate CEC interrupts associated to the set of RX flags */
+  CEC_ITConfig(CEC_IT_RXEND|CEC_IT_RXBR,ENABLE);
+  
+  /* Activate CEC interrupts associated to the set of TX error */
+  CEC_ITConfig(CEC_IT_TXACKE|CEC_IT_TXERR|CEC_IT_TXUDR|CEC_IT_ARBLST,ENABLE);
+  
+  /* Activate CEC interrupts associated to the set of RX error */
+  CEC_ITConfig(CEC_IT_RXACKE|CEC_IT_LBPE|CEC_IT_SBPE|CEC_IT_BRE|CEC_IT_RXOVR,ENABLE);
+  
+  /* Report physical address */
+  errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  sendcount = 0;
+  RxCounter = 0;
+  
+  while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+  {
+    sendcount++;
+    errorstatus = HDMI_CEC_ReportPhysicalAddress();
+  }
+  
+  if (errorstatus != HDMI_CEC_OK)
+  {
+    /* Device Unregistred */
+    return(errorstatus);
+  }
+  return errorstatus;
+}
+
+/**
+  * @brief  Transmit message by taking data from typedef struct CEC_Meassage
+  * @param  CEC_TX_MessageStructure: pointer to an CEC_Message structure that contains
+  *         the message to be sent.
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  __IO uint32_t count = 0, j = 0;
+
+  SendFrame = 0;
+  SendStatus = 0;
+  TxCounter = 0;
+  BufferCount = 0;
+
+  HDMI_CEC_TX_MessageStructPrivate = *HDMI_CEC_TX_MessageStructure;
+
+  /* Initialize BufferPointer */
+  for (j = 0; j < 15; j++)
+  {
+    BufferPointer[j] = 0;
+  }
+
+  BufferPointer[0] =  HDMI_CEC_TX_MessageStructPrivate.Opcode;
+
+  for (BufferCount = 1; BufferCount < HDMI_CEC_TX_MessageStructPrivate.TxMessageLength + 1; BufferCount++)
+  {
+    BufferPointer[BufferCount] = HDMI_CEC_TX_MessageStructPrivate.Operande[BufferCount - 1];
+  }
+
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /* Write single Data in the TX Buffer to Transmit through the CEC peripheral */
+  CEC_SendData(HDMI_CEC_TX_MessageStructPrivate.Header);
+
+  /* Initiate Message Transmission */
+  CEC_StartOfMessage();
+
+  while ((SendFrame == 0) && (count < HDMI_CEC_TIMEOUT_VALUE))
+  {
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (SendStatus == 0)
+  {
+    errorstatus = (HDMI_CEC_Error) TransErrorCode;
+  }
+  return errorstatus;
+}
+
+/**
+  * @brief  Get the ISR register status.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code
+  */
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+
+  /* RX Overrun error case*/
+  if (CEC_GetFlagStatus(CEC_FLAG_RXOVR) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_OVERRUN;
+    CEC_ClearFlag(CEC_FLAG_RXOVR);
+  }
+  /* Bit Rising error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_BRE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_BIT_RISING;
+    CEC_ClearFlag(CEC_FLAG_BRE);
+  }
+  /* Short Bit Period error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_SBPE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_SHORT_BIT_PERIOD;
+    CEC_ClearFlag(CEC_FLAG_SBPE);
+  }
+  /* Long Bit Period error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_LBPE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_LONG_BIT_PERIOD;
+    CEC_ClearFlag(CEC_FLAG_LBPE);
+  }
+  /* RX Acknowledge error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_RXACKE) != RESET)
+  {
+    errorstatus = HDMI_CEC_RX_ACKNOWLEDGE;
+    CEC_ClearFlag(CEC_FLAG_RXACKE);
+  }
+  /* Arbitration Lost error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_ARBLST) != RESET)
+  {
+    errorstatus = HDMI_CEC_ARBITRATION_LOST;
+    CEC_ClearFlag(CEC_FLAG_ARBLST);
+  }
+  /* TX underrun error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_TXUDR) != RESET)
+  {
+    errorstatus = HDMI_CEC_TX_UNDERRUN;
+    CEC_ClearFlag(CEC_FLAG_TXUDR);
+  }
+  /* TX error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_TXERR) != RESET)
+  {
+    errorstatus = HDMI_CEC_TX_ERROR;
+    CEC_ClearFlag(CEC_FLAG_TXERR);
+  }
+  /* TX Acknowledge error case */
+  if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+  {
+    errorstatus = HDMI_CEC_TX_ACKNOWLEDGE;
+    CEC_ClearFlag(CEC_FLAG_TXACKE);
+  } 
+  return errorstatus;
+}
+
+/**
+  * @brief  Allows to process all the interrupts that are high.
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_ProcessIRQSrc(void)
+{
+  /********************** Reception *******************************************/
+  /* Check if a reception error occured */
+  if (CEC->ISR & (CEC_IT_RXACKE | CEC_IT_LBPE | CEC_IT_SBPE | CEC_IT_BRE | CEC_IT_RXOVR))
+  {
+    /* Set receive status bit (Error) */
+    ReceiveStatus  = 0;
+    ReceivedFrame  = 1;
+    CEC->ISR = (CEC_IT_RXACKE | CEC_IT_LBPE | CEC_IT_SBPE | CEC_IT_BRE | CEC_IT_RXOVR);
+  }
+
+  if (CEC_GetITStatus(CEC_IT_RXBR))
+  {
+    /* Check if the byte received is a Header */
+    if (RxCounter == 0)
+    {
+      HDMI_CEC_RX_MessageStructPrivate.Header = CEC_ReceiveData();
+      RxCounter ++;
+    }
+    else if(RxCounter == 1)   /* Receive opcode in the reception buffer */
+    {
+      HDMI_CEC_RX_MessageStructPrivate.Opcode = CEC_ReceiveData();
+      RxCounter++;
+    }
+    else /* Receive each byte except header and opcode in the reception buffer */
+    {
+      HDMI_CEC_RX_MessageStructPrivate.Operande[RxCounter-2] = CEC_ReceiveData();
+      RxCounter++;
+    }  
+    CEC_ClearITPendingBit(CEC_IT_RXBR);
+  }
+
+  /* Check if the byte received is the last one of the message */
+  if (CEC_GetITStatus(CEC_IT_RXEND))
+  {
+    if (RxCounter == 1)
+    {
+
+      HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter-1;
+    }
+    else
+    {
+      HDMI_CEC_RX_MessageStructPrivate.RxMessageLength = RxCounter-2;
+      ReceivedFrame = 1;
+    }
+
+    /* Set the receive status */
+    ReceiveStatus = SUCCESS;
+    RxCounter = 0;
+    
+    /* Clear all reception flags */
+    CEC_ClearITPendingBit(CEC_IT_RXEND);
+  }
+
+  /********************** Transmission ****************************************/
+  /* Check if a transmission error occurred */
+  if (CEC->ISR & (CEC_IT_TXACKE | CEC_IT_TXERR | CEC_IT_TXUDR | CEC_IT_ARBLST))
+  {
+    TransErrorCode = HDMI_CEC_GetErrorStatus();
+    CEC->ISR = (CEC_IT_TXACKE | CEC_IT_TXERR | CEC_IT_TXUDR | CEC_IT_ARBLST);
+    SendFrame = 1;
+    SendStatus = 0;
+  }
+
+  /* Check if end of message bit is set in the data to be transmitted */
+  if (CEC_GetITStatus(CEC_IT_TXEND))
+  {
+    CEC_ClearITPendingBit(CEC_IT_TXEND | CEC_IT_TXBR);
+    SendFrame = 1;
+    SendStatus = SUCCESS;
+  }
+  /* Check if data byte has been sent */
+  else if (CEC_GetITStatus(CEC_IT_TXBR))
+  {
+    /* Set EOM bit if the byte to be transmitted is the last one of the Transmit Buffer */
+    if (TxCounter == (HDMI_CEC_TX_MessageStructPrivate.TxMessageLength))
+    {
+      CEC_EndOfMessage();
+      CEC_SendData(BufferPointer[TxCounter++]);
+    }
+    else
+    {
+      /* Put the byte in the TX Buffer */
+      CEC_SendData(BufferPointer[TxCounter++]);
+    }
+    CEC_ClearITPendingBit(CEC_IT_TXBR);
+  }
+}
+
+/**
+  * @brief  Report physical address to all other devices thus allowing any
+            device to create a map of the network.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  HDMI_CEC_Message HDMI_CEC_TX_Message;
+
+  HDMI_CEC_TX_Message.Header = ((MyLogicalAddress << 4) | 0xF);
+  HDMI_CEC_TX_Message.Opcode = HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS;
+  HDMI_CEC_TX_Message.Operande[0] = MyPhysicalAddress >> 8;
+  HDMI_CEC_TX_Message.Operande[1] = MyPhysicalAddress & 0xFF;
+  HDMI_CEC_TX_Message.Operande[2] = DeviceType;
+  HDMI_CEC_TX_Message.TxMessageLength = 0x03;
+
+  errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_Message);
+
+  return  errorstatus;
+}
+
+/**
+  * @brief  Handle CEC command receive callback.
+  *         When receiving the STANDBY Opcode command, the system is entered in
+  *         Stop mode and when wakeup, the PLL is configured as system clock and
+  *         the HSI is selected as PLL source.      
+  * @param  None
+  * @retval None
+  */
+void HDMI_CEC_CommandCallBack(void)
+{
+  uint8_t i = 0, sendcount = 0;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  ErrorStatus HSEStartUpStatus;
+
+  switch (HDMI_CEC_RX_MessageStructPrivate.Opcode)
+  {
+    case HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS:
+      HDMI_CEC_MapStruct.PhysicalAddress_A = HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_B = HDMI_CEC_RX_MessageStructPrivate.Operande[1] & 0x0F;
+      HDMI_CEC_MapStruct.PhysicalAddress_C = HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4;
+      HDMI_CEC_MapStruct.PhysicalAddress_D = HDMI_CEC_RX_MessageStructPrivate.Operande[0] & 0x0F;
+      HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+      HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+      HDMI_CEC_DeviceMap[DeviceCount] = HDMI_CEC_MapStruct;
+      HDMI_CEC_Follower_String[(HDMI_CEC_DeviceMap[DeviceCount].LogicalAddress)][1] = (uint8_t *)"1";
+      DeviceCount++;
+      break;
+
+    case HDMI_CEC_OPCODE_STANDBY:
+
+      /* Request to enter Stop mode */
+      PWR_EnterSTOPMode(PWR_Regulator_ON, PWR_STOPEntry_WFI);
+
+      /* Enable HSE */
+      RCC_HSEConfig(RCC_HSE_ON);
+
+      /* Wait till HSE is ready */
+      HSEStartUpStatus = RCC_WaitForHSEStartUp();
+      if (HSEStartUpStatus == SUCCESS)
+      {
+        /* Enable PLL */
+        RCC_PLLCmd(ENABLE);
+        /* Wait till PLL is ready */
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+        {}
+        /* Select PLL as system clock source */
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+        /* Wait till PLL is used as system clock source */
+        while (RCC_GetSYSCLKSource() != 0x08)
+        {}
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GET_CEC_VERSION:
+      /* Send the Used CEC version */
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_CEC_VERSION;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = HDMI_CEC_VERSION; /* CEC Version */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x01;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS:
+      /* Send the Physical address */
+      errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_ReportPhysicalAddress();
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_FEATURE_ABORT:
+      /* The device doesn't support the requested message type, or that it cannot
+      execute it at the present time. */
+      FeatureOpcode = HDMI_CEC_RX_MessageStructPrivate.Operande[0];
+      AbortReason = HDMI_CEC_RX_MessageStructPrivate.Operande[1];
+      break;
+
+    case HDMI_CEC_OPCODE_GIVE_OSD_NAME:
+      /* Send the OSD name = STM32373C CEC */
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_SET_OSD_NAME;
+      /* STM32373C */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x53;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = 0x54;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[2] = 0x4D;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[3] = 0x33;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[4] = 0x32;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[5] = 0x33;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[6] = 0x37;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[7] = 0x33;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[8] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[9] = 0x20;
+      /* CEC */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[10] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[11] = 0x45;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[12] = 0x43;
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 13;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+
+    case HDMI_CEC_OPCODE_ROUTING_CHANGE:
+      for (i = 0;i < 0x14;i++)
+      {
+        if ((HDMI_CEC_DeviceMap[i].PhysicalAddress_A == (HDMI_CEC_RX_MessageStructPrivate.Operande[1] >> 4)) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_B == (HDMI_CEC_RX_MessageStructPrivate.Operande[1]&0x0F)) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_C == (HDMI_CEC_RX_MessageStructPrivate.Operande[0] >> 4)) &&
+            (HDMI_CEC_DeviceMap[i].PhysicalAddress_D == (HDMI_CEC_RX_MessageStructPrivate.Operande[0]&0x0F)))
+        {
+          HDMI_CEC_MapStruct.LogicalAddress = (HDMI_CEC_RX_MessageStructPrivate.Header >> 0x4) & 0x0F;
+          HDMI_CEC_MapStruct.DeviceType = HDMI_CEC_RX_MessageStructPrivate.Operande[2];
+          HDMI_CEC_DeviceMap[i] = HDMI_CEC_MapStruct;
+        }
+      }
+      break;
+
+    default:
+      /* Send Abort feature */
+      HDMI_CEC_TX_MessageStructPrivate.Header = ((MyLogicalAddress << 4) | HDMI_CEC_RX_MessageStructPrivate.Header >> 4);
+      HDMI_CEC_TX_MessageStructPrivate.Opcode = HDMI_CEC_OPCODE_FEATURE_ABORT;
+      HDMI_CEC_TX_MessageStructPrivate.Operande[0] = 0x02; /* Defines command to be performed */
+      HDMI_CEC_TX_MessageStructPrivate.Operande[1] = HDMI_CEC_REFUSED; /* Reason for abort feature */
+      HDMI_CEC_TX_MessageStructPrivate.TxMessageLength = 0x02;
+      errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      sendcount = 0;
+      /* Retransmit message until 5 time */
+      while ((errorstatus != HDMI_CEC_OK) && sendcount < 0x5)
+      {
+        sendcount++;
+        errorstatus = HDMI_CEC_TransmitMessage(&HDMI_CEC_TX_MessageStructPrivate);
+      }
+      break;
+  }
+}
+
+/**
+  * @brief  Check the connected CEC devices.
+  * @param  None
+  * @retval HDMI_CEC_Error
+  */
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0, i = 1;
+
+  /*------------------------------- TV device --------------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x0);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    { 
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag( CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[0][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Recording device 1 --------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4)|0x1);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    { 
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag( CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[1][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Recording device 2 --------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x2);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {  
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag( CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[2][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*------------------------------ Tuner 1 -----------------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x3);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag( CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[3][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Playback device 1 ---------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x4);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[4][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*-------------------------------- Audio system ----------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x5); 
+  
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[5][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*--------------------------------- Tuner 2 --------------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x6);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[6][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*--------------------------------- Tuner 3 --------------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x7);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    { 
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[7][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Playback device 2 ---------------------------*/  
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x8);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while(count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[8][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Recording device 3 --------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0x9);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while(count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[9][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*-------------------------------- Tuner 4 ---------------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4) | 0xA);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while (count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    { 
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[10][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  /*---------------------------- Playback device 3 ---------------------------*/
+  CEC_EndOfMessage();
+
+  CEC_SendData((MyLogicalAddress << 4)|0xB);
+
+  /* Start of message */
+  CEC_StartOfMessage();
+
+  /* Wait till the header message is sent */
+  while(count < HDMI_CEC_TIMEOUT_VALUE)
+  {
+    if (CEC_GetFlagStatus(CEC_FLAG_TXACKE) != RESET)
+    {
+      errorstatus = HDMI_CEC_GetErrorStatus();
+      CEC_ClearFlag(CEC_FLAG_TXACKE);
+      break;
+    }
+    else if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+    {
+      errorstatus = HDMI_CEC_OK;
+      break;
+    }
+    count++;
+  }
+
+  if (count >= HDMI_CEC_TIMEOUT_VALUE)
+  {
+    errorstatus = HDMI_CEC_TIMEOUT;
+    return(errorstatus);
+  }
+
+  if (errorstatus == HDMI_CEC_OK)
+  {
+    HDMI_CEC_Follower_String[11][1] = (uint8_t *)"1";
+    i++;
+    errorstatus = HDMI_CEC_OK;
+  }
+  /* Clear CEC ISR register */
+  CEC_ClearFlag(CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+  CECDevicesNumber = i - 1;
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Sink Physical address discovery.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error SinkPhysicalAddressDiscovery(void)
+{
+  uint32_t DataNum=0;
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+
+  I2C_InitTypeDef  I2C_InitStructure;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /*------------------------------ Physical address discovery ----------------*/
+  /* if HDMI_CEC_ROOT == 0x1*/
+  MyPhysicalAddress = 0x0000;
+  /* The HDMI-CEC here is configured as sink or as a repeater. The configuration
+  of the +5V power signal and the HPD should be well configured.
+  Implement here the EDID Structure to be sent to the HDMI source.
+  For more details please refer to the HDMI specification. 
+  The EDID structure should be sent to the device source using the DDC Channel
+  and using the HPD signal. */
+
+  /* Enable CEC_I2C clocks */
+  RCC_APB1PeriphClockCmd(HDMI_CEC_SINK_I2C_CLK, ENABLE);
+
+  /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
+  RCC_AHBPeriphClockCmd(HDMI_CEC_SINK_I2C_GPIO_CLK | HDMI_CEC_HPD_SINK_GPIO_CLK, ENABLE);
+
+  I2C_DeInit(HDMI_CEC_SINK_I2C);
+
+  GPIO_PinAFConfig(HDMI_CEC_SINK_I2C_GPIO_PORT, HDMI_CEC_SINK_I2C_SCL_PIN_SOURCE, GPIO_AF_1);
+  GPIO_PinAFConfig(HDMI_CEC_SINK_I2C_GPIO_PORT, HDMI_CEC_SINK_I2C_SDA_PIN_SOURCE, GPIO_AF_1);
+
+  /* Set PF6/PF7 as OD AF - I2C2_SCL/I2C2_SDA of Source*/
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_SINK_I2C_SDA_PIN | HDMI_CEC_SINK_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_Init(HDMI_CEC_SINK_I2C_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Set PA11 as PP - HPD */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_SINK_PIN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_Init(HDMI_CEC_HPD_SINK_GPIO_PORT, &GPIO_InitStructure);
+
+  RCC_I2CCLKConfig(RCC_I2C1CLK_HSI);
+
+  HDMI_CEC_SINK_I2C->CR1 &= (uint16_t)(~I2C_CR1_NOSTRETCH);
+
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_Timing = HDMI_CEC_I2C_TIMING;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  /* Initialize the I2C_DigitalFilter member */
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = HDMI_CEC_I2C_SLAVE_ADDRESS7;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_Init(HDMI_CEC_SINK_I2C, &I2C_InitStructure);
+
+  /* Enable HDMI_CEC_SINK_I2C */
+  I2C_Cmd(HDMI_CEC_SINK_I2C, ENABLE);
+
+  /* Wait until ADDR is set */
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_ADDR));
+
+  /* Clear ADDR flag */
+  HDMI_CEC_SINK_I2C->ICR = I2C_ICR_ADDRCF;
+
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_RXNE));
+
+  HDMI_CEC_SINK_I2C->RXDR;
+
+  /* Wait until ADDR is set */
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_ADDR));
+
+  /* Clear ADDR flag */
+  HDMI_CEC_SINK_I2C->ICR = I2C_ICR_ADDRCF;
+
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_TXIS));
+
+  while (DataNum != 256)
+  {
+    if (HDMI_CEC_SINK_I2C->ISR & I2C_ISR_TXIS)
+    {
+      /* Write data to TXDR */
+      HDMI_CEC_SINK_I2C->TXDR = (uint8_t)(EDID_Structure[DataNum++]);
+    }
+  }
+
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_STOPF));
+  while (!(HDMI_CEC_SINK_I2C->ISR & I2C_ISR_NACKF));
+
+  /* Clear STOPF and NACKF flag */
+  HDMI_CEC_SINK_I2C->ICR = ( I2C_ICR_STOPCF | I2C_ICR_NACKCF);
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Source Physical address discovery.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error SourcePhysicalAddressDiscovery(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+
+#ifdef HDMI_CEC_USE_DDC
+  uint32_t  i = 0;
+  uint32_t DataNum=0;
+  GPIO_InitTypeDef GPIO_InitStructure;
+  I2C_InitTypeDef  I2C_InitStructure;
+
+  /* Enable CEC_I2C clocks */
+  RCC_APB1PeriphClockCmd(HDMI_CEC_I2C_CLK, ENABLE);
+
+  /* Enable CEC_I2C_GPIO and CEC_HPD_GPIO clocks */
+  RCC_AHBPeriphClockCmd(HDMI_CEC_I2C_GPIO_CLK|HDMI_CEC_HPD_SOURCE_GPIO_CLK, ENABLE);
+
+  GPIO_PinAFConfig(HDMI_CEC_I2C_GPIO_PORT,HDMI_CEC_I2C_SCL_PIN_SOURCE,GPIO_AF_1);
+  GPIO_PinAFConfig(HDMI_CEC_I2C_GPIO_PORT,HDMI_CEC_I2C_SDA_PIN_SOURCE,GPIO_AF_1);
+
+  /* Configure CEC_I2C_SCL_PIN and CEC_I2C_SDA_PIN  as Output open drain */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_I2C_SCL_PIN|HDMI_CEC_I2C_SDA_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(HDMI_CEC_I2C_GPIO_PORT, &GPIO_InitStructure);
+
+/* This configuration is only when the HDMI CEC is configured as source.
+   The HDMI source has to provide the +5V Power signal to the sink. 
+   Then, the source will wait for HPD signal to be asserted from the sink.
+   Once the HPD signal is detected the source shall read the EDID structure 
+   through the DDC channel. */
+  /* Configure CEC_HPD_GPIO as Input pull down */
+  GPIO_InitStructure.GPIO_Pin = HDMI_CEC_HPD_SOURCE_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_Init(HDMI_CEC_HPD_SOURCE_GPIO_PORT, &GPIO_InitStructure);
+
+  /* I2C configuration */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+  I2C_InitStructure.I2C_DigitalFilter = 0x00;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack =I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_Timing = HDMI_CEC_I2C_TIMING;
+
+  /* I2C configuration */
+  I2C_Init(HDMI_CEC_I2C, &I2C_InitStructure);
+
+  /* I2C Peripheral Enable */
+  I2C_Cmd(HDMI_CEC_I2C, ENABLE);
+
+  /* The HDMI-CEC here is configured as source or as a repeater. The configuration
+  of the +5V power signal and the HPD should be well configured.
+  The source should wait for HPD and then read the EDID structure. */
+  while(GPIO_ReadInputDataBit(HDMI_CEC_HPD_SOURCE_GPIO_PORT, HDMI_CEC_HPD_SOURCE_PIN) == RESET)
+  {
+  }
+
+  /* Wait for 100 ms after HPD was received */
+  for(i = 0; i <0x5FFFFF; i++)
+  {
+  }
+  
+  /* Configure slave address, nbytes, reload and generate start */
+  HDMI_CEC_I2C->CR2 = (uint32_t)(0xA0)|(uint32_t)(1 << 16)|I2C_CR2_START;
+
+  /* Wait until TXIS is set */
+  while (!(HDMI_CEC_I2C->ISR & I2C_ISR_TXIS));
+
+    /* Send memory address */
+    HDMI_CEC_I2C->TXDR = (uint8_t)(0x00);
+
+    /* Wait until TC is set */
+    while (!(HDMI_CEC_I2C->ISR & I2C_ISR_TC));
+
+    /* Update CR2 : set Nbytes and reload */
+    HDMI_CEC_I2C->CR2 = (uint32_t)(0xA0)|I2C_CR2_RD_WRN|I2C_CR2_START |(uint32_t)(255 << 16)|I2C_CR2_RELOAD;
+
+    /* Wait until all data are received */
+    while (DataNum != 255)
+    {
+      /* Wait until RXNE flag is set */
+      while (!(HDMI_CEC_I2C->ISR & I2C_ISR_RXNE));
+
+      /* Read data from RXDR */
+      pBuffer[DataNum]= (uint8_t)HDMI_CEC_I2C->RXDR;
+
+      /* Update number of received data */
+      DataNum++;
+    }
+
+    /* Wait until TCR flag is set */
+    while (!(HDMI_CEC_I2C->ISR & I2C_ISR_TCR));
+
+    /* Update CR2 : set Nbytes and end mode */
+    HDMI_CEC_I2C->CR2 = (uint32_t)(1 << 16)|I2C_CR2_AUTOEND;
+
+    while (!(HDMI_CEC_I2C->ISR & I2C_ISR_RXNE));
+
+    /* Read data from RXDR */
+    pBuffer[DataNum]= (uint8_t)HDMI_CEC_I2C->RXDR;
+
+    /* Wait until STOPF flag is set */      
+    while (!(HDMI_CEC_I2C->ISR & I2C_ISR_STOPF));
+
+    /* Clear STOPF flag */
+    HDMI_CEC_I2C->ICR = I2C_ICR_STOPCF;
+
+    MyPhysicalAddress = ((pBuffer[158] << 8)|pBuffer[159]);
+#else
+    MyPhysicalAddress = 0x1000;
+#endif
+
+  return errorstatus;
+}
+
+/**
+  * @brief  Allocate the logical address.
+  * @param  None
+  * @retval HDMI_CEC_Error: CEC Error code.
+  */
+static HDMI_CEC_Error LogicalAddressAllocation(void)
+{
+  HDMI_CEC_Error errorstatus = HDMI_CEC_OK;
+  uint32_t count = 0;
+
+  /*------------------ Logical address allocation ----------------------------*/
+  /* Get the device type */
+  /* Device type = CEC_TV */
+  if (DeviceType == HDMI_CEC_TV)
+  {
+    if (HDMI_CEC_ROOT)
+    {
+      MyLogicalAddress = 0x00;
+    }
+    else
+    {
+      CEC_OwnAddressConfig(0xE); /* Own address = 0xE */
+
+      CEC_EndOfMessage();
+
+      CEC_SendData(0xEE);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+        {
+          break;
+        }
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x0E;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        MyLogicalAddress = 0x0F;
+        errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+      }
+    }
+    /* Clear CEC ISR register */
+    CEC_ClearFlag(CEC_FLAG_TXEND);
+  }
+
+  /* Device type = CEC_RECORDING */
+  if (DeviceType == HDMI_CEC_RECORDING)
+  {
+    CEC_OwnAddressConfig(0x1); /* Own address = 0x1 */
+
+    CEC_EndOfMessage();
+
+    CEC_SendData(0x11);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+      {
+        break;
+      }
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x01;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC ISR register */
+      CEC_ClearFlag(CEC_FLAG_TXEND|CEC_FLAG_TXACKE|CEC_FLAG_TXBR);
+
+      /* Clear the OAR */
+      CEC_OwnAddressClear();
+
+      CEC_OwnAddressConfig(0x2); /* Own address = 0x2 */
+
+      CEC_EndOfMessage();
+
+      CEC_SendData(0x22);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+        {
+          break;
+        }
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x02;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC ISR register */
+        CEC_ClearFlag( CEC_FLAG_TXEND);
+
+        CEC_OwnAddressClear();
+
+        CEC_OwnAddressConfig(0x9); /* Own address = 0x9 */
+
+        CEC_EndOfMessage();
+
+        CEC_SendData(0x99);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+          {
+            break;
+          }
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x09;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+    /* Clear CEC ISR register */
+    CEC_ClearFlag(CEC_FLAG_TXEND|CEC_FLAG_TXACKE|CEC_FLAG_TXBR);
+  }
+
+  /* Device type = CEC_TUNER */
+  if (DeviceType == HDMI_CEC_TUNER)
+  {
+    CEC_OwnAddressConfig(0x3); /* Own address = 0x3 */
+
+    CEC_EndOfMessage();
+
+    CEC_SendData(0x33);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+      {
+        break;
+      }
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x03;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC ISR register */
+      CEC_ClearFlag(CEC_FLAG_TXEND);
+
+      /* Clear the OAR */
+      CEC_OwnAddressClear();
+
+      CEC_OwnAddressConfig(0x6); /* Own address = 0x6 */
+
+      CEC_EndOfMessage();
+
+      CEC_SendData(0x66);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+        {
+          break;
+        }
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x06;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC ISR register */
+        CEC_ClearFlag(CEC_FLAG_TXEND);
+
+        /* Clear the OAR */
+        CEC_OwnAddressClear();
+
+        CEC_OwnAddressConfig(0x7); /* Own address = 0x7 */
+
+        CEC_EndOfMessage();
+
+        CEC_SendData(0x77);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+          {
+            break;
+          }
+          count++;
+        }
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x07;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          /* Clear CEC ISR register */
+          CEC_ClearFlag(CEC_FLAG_TXEND);
+
+          /* Clear the OAR */
+          CEC_OwnAddressClear();
+
+          CEC_OwnAddressConfig(0xA); /* Own address = 0xA */
+
+          CEC_EndOfMessage();
+
+          CEC_SendData(0xAA);
+
+          /* Start of message */
+          CEC_StartOfMessage();
+
+          count = 0;
+
+          /* Wait till the header message is sent */
+          while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+          {
+            if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+            {
+              break;
+            }
+            count++;
+          }
+          if (count >= HDMI_CEC_TIMEOUT_VALUE)
+          {
+            errorstatus = HDMI_CEC_TIMEOUT;
+            return(errorstatus);
+          }
+          errorstatus = HDMI_CEC_GetErrorStatus();
+          
+          if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+          {
+            MyLogicalAddress = 0x0A;
+            errorstatus = HDMI_CEC_OK;
+          }
+          else if (errorstatus == HDMI_CEC_OK)
+          {
+            MyLogicalAddress = 0x0F;
+            errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+          }
+        }
+      }
+    }
+    /* Clear CEC ISR register */
+    CEC_ClearFlag(CEC_FLAG_TXEND);
+  }
+
+  /* Device type = CEC_PLAYBACK */
+  if (DeviceType == HDMI_CEC_PLAYBACK)
+  {
+    CEC_OwnAddressConfig(0x4); /* Own address = 0x4 */
+
+    CEC_EndOfMessage();
+
+     CEC_SendData(0x44);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+      {
+        break;
+      }
+      count++;
+    }
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x04;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      /* Clear CEC ISR register */
+      CEC_ClearFlag(CEC_FLAG_TXEND);
+
+      /* Clear the OAR */
+      CEC_OwnAddressClear();
+
+      CEC_OwnAddressConfig(0x8); /* Own address = 0x8 */
+
+      CEC_EndOfMessage();
+
+      CEC_SendData(0x88);
+
+      /* Start of message */
+      CEC_StartOfMessage();
+
+      count = 0;
+
+      /* Wait till the header message is sent */
+      while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+      {
+        if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+        {
+          break;
+        }
+        count++;
+      }
+
+      if (count >= HDMI_CEC_TIMEOUT_VALUE)
+      {
+        errorstatus = HDMI_CEC_TIMEOUT;
+        return(errorstatus);
+      }
+      errorstatus = HDMI_CEC_GetErrorStatus();
+
+      if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+      {
+        MyLogicalAddress = 0x08;
+        errorstatus = HDMI_CEC_OK;
+      }
+      else if (errorstatus == HDMI_CEC_OK)
+      {
+        /* Clear CEC ISR register */
+        CEC_ClearFlag(CEC_FLAG_TXEND);
+
+        /* Clear the OAR */
+        CEC_OwnAddressClear();
+
+        CEC_OwnAddressConfig(0xB); /* Own address = 0xBB */
+
+        CEC_EndOfMessage();
+
+        CEC_SendData(0xBB);
+
+        /* Start of message */
+        CEC_StartOfMessage();
+
+        count = 0;
+
+        /* Wait till the header message is sent */
+        while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+        {
+          if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+          {
+            break;
+          }
+          count++;
+        }
+        /* Clear the OAR */
+        CEC_OwnAddressClear();
+
+        if (count >= HDMI_CEC_TIMEOUT_VALUE)
+        {
+          errorstatus = HDMI_CEC_TIMEOUT;
+          return(errorstatus);
+        }
+
+        errorstatus = HDMI_CEC_GetErrorStatus();
+
+        if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+        {
+          MyLogicalAddress = 0x0B;
+          errorstatus = HDMI_CEC_OK;
+        }
+        else if (errorstatus == HDMI_CEC_OK)
+        {
+          MyLogicalAddress = 0x0F;
+          errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+        }
+      }
+    }
+    /* Clear CEC ISR register */
+    CEC_ClearFlag(CEC_FLAG_TXEND);
+  }
+
+  /* Device type = CEC Audio System */
+  if (DeviceType == HDMI_CEC_AUDIOSYSTEM)
+  {
+    CEC_OwnAddressConfig(0x5); /* Own address = 0x5 */
+
+    CEC_EndOfMessage();
+
+    CEC_SendData(0x55);
+
+    /* Start of message */
+    CEC_StartOfMessage();
+
+    count = 0;
+
+    /* Wait till the header message is sent */
+    while ((CEC_GetFlagStatus(CEC_FLAG_TXACKE) == RESET) && (count < HDMI_CEC_TIMEOUT_VALUE))
+    {
+      if(CEC_GetFlagStatus(CEC_FLAG_TXEND) != RESET)
+      {
+        break;
+      }
+      count++;
+    }
+
+    if (count >= HDMI_CEC_TIMEOUT_VALUE)
+    {
+      errorstatus = HDMI_CEC_TIMEOUT;
+      return(errorstatus);
+    }
+    
+    errorstatus = HDMI_CEC_GetErrorStatus();
+
+    if (errorstatus == HDMI_CEC_TX_ACKNOWLEDGE)
+    {
+      MyLogicalAddress = 0x05;
+      errorstatus = HDMI_CEC_OK;
+    }
+    else if (errorstatus == HDMI_CEC_OK)
+    {
+      MyLogicalAddress = 0x0F;
+      errorstatus = HDMI_CEC_DEVICE_UNREGISTRED;
+    }
+
+    /* Clear CEC ISR register */
+    CEC_ClearFlag(CEC_FLAG_TXEND);
+  }
+
+  return errorstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.h
new file mode 100644
index 0000000..c5cd7e6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_cec.h
@@ -0,0 +1,309 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_cec.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the stm32373c_eval_cec
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_CEC_H
+#define __STM32373C_EVAL_CEC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+  /* Includes ------------------------------------------------------------------*/
+#include "stm32f37x.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+
+/** @defgroup STM32373C_EVAL_CEC
+  * @{
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Exported_Types
+  * @{
+  */
+typedef enum
+{
+  HDMI_CEC_RX_OVERRUN              = (1),  /*!< CEC Receive overrun Error     */
+  HDMI_CEC_RX_BIT_RISING           = (2),  /*!< CEC Rx Bit Rising Error       */
+  HDMI_CEC_RX_SHORT_BIT_PERIOD     = (3),  /*!< CEC Rx Short Bit Period Error */
+  HDMI_CEC_RX_LONG_BIT_PERIOD      = (4),  /*!< CEC Rx Long Bit Period Error  */
+  HDMI_CEC_RX_ACKNOWLEDGE          = (5),  /*!< CEC RX Acknowledge Error      */
+  HDMI_CEC_ARBITRATION_LOST        = (6),  /*!< Arbitration Lost Error   */
+  HDMI_CEC_TX_UNDERRUN             = (7),  /*!< CEC Transmit Underrun Error */
+  HDMI_CEC_TX_ERROR                = (8),  /*!< CEC Transmit Error */
+  HDMI_CEC_TX_ACKNOWLEDGE          = (9),  /*!< CEC TX Acknowledge Error */
+  HDMI_CEC_DEVICE_UNREGISTRED      = (10), /*!< CEC Device Unregistered */
+  HDMI_CEC_TIMEOUT                 = (11), /*!< CEC TimeOut */
+  HDMI_CEC_OK                      = (12)  /*!< CEC OK */
+}HDMI_CEC_Error;
+
+typedef struct
+{
+  uint8_t PhysicalAddress_A;
+  uint8_t PhysicalAddress_B;
+  uint8_t PhysicalAddress_C;
+  uint8_t PhysicalAddress_D;
+  uint8_t LogicalAddress;
+  uint8_t DeviceType;
+}HDMI_CEC_Map;
+
+#define HDMI_CEC_TX_MESSAGE_LENGTH_MAX       ((uint32_t)0x0000000E)
+#define HDMI_CEC_TIMEOUT_VALUE               ((uint32_t)0x001FFFFF)
+
+/**
+* @brief  CEC Init Structure definition
+*/
+typedef struct
+{
+  __IO uint8_t Header;
+  __IO uint8_t Opcode;
+  __IO uint8_t Operande[HDMI_CEC_TX_MESSAGE_LENGTH_MAX];
+  __IO uint8_t TxMessageLength;
+  __IO uint8_t RxMessageLength;
+}HDMI_CEC_Message;
+
+/**
+* @}
+*/
+
+/** @defgroup STM32373C_EVAL_CEC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @brief CEC device types
+  */
+#define HDMI_CEC_TV                                         0x00
+#define HDMI_CEC_RECORDING                                  0x01
+#define HDMI_CEC_TUNER                                      0x03
+#define HDMI_CEC_PLAYBACK                                   0x04
+#define HDMI_CEC_AUDIOSYSTEM                                0x05
+
+/**
+  * @brief  HDMI CEC I2C Interface pins
+  */
+#define HDMI_CEC_I2C_SCL_PIN                                GPIO_Pin_9
+#define HDMI_CEC_I2C_SDA_PIN                                GPIO_Pin_10
+#define HDMI_CEC_I2C_SCL_PIN_SOURCE                         GPIO_PinSource9
+#define HDMI_CEC_I2C_SDA_PIN_SOURCE                         GPIO_PinSource10
+#define HDMI_CEC_I2C_GPIO_PORT                              GPIOA
+#define HDMI_CEC_I2C_GPIO_CLK                               RCC_AHBPeriph_GPIOA
+#define HDMI_CEC_I2C                                        I2C2
+#define HDMI_CEC_I2C_CLK                                    RCC_APB1Periph_I2C2
+
+#define HDMI_CEC_SINK_I2C_SCL_PIN                           GPIO_Pin_6
+#define HDMI_CEC_SINK_I2C_SDA_PIN                           GPIO_Pin_7
+#define HDMI_CEC_SINK_I2C_SCL_PIN_SOURCE                    GPIO_PinSource6
+#define HDMI_CEC_SINK_I2C_SDA_PIN_SOURCE                    GPIO_PinSource7
+#define HDMI_CEC_SINK_I2C_GPIO_PORT                         GPIOB
+#define HDMI_CEC_SINK_I2C_GPIO_CLK                          RCC_AHBPeriph_GPIOB
+#define HDMI_CEC_SINK_I2C                                   I2C1
+#define HDMI_CEC_SINK_I2C_CLK                               RCC_APB1Periph_I2C1
+/**
+  * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
+  */
+#define HDMI_CEC_HPD_SINK_PIN                               GPIO_Pin_9
+#define HDMI_CEC_HPD_SINK_GPIO_PORT                         GPIOD
+#define HDMI_CEC_HPD_SINK_GPIO_CLK                          RCC_AHBPeriph_GPIOD
+
+/**
+  * @brief  HDMI CEC HPD (Hot Plug Detect) Interface pin
+  */
+#define HDMI_CEC_HPD_SOURCE_PIN                             GPIO_Pin_7
+#define HDMI_CEC_HPD_SOURCE_GPIO_PORT                       GPIOD
+#define HDMI_CEC_HPD_SOURCE_GPIO_CLK                        RCC_AHBPeriph_GPIOD
+
+/**
+  * @brief  HDMI CEC Interface pin
+  */
+#define HDMI_CEC_LINE_PIN                                   GPIO_Pin_8
+#define HDMI_CEC_LINE_GPIO_PORT                             GPIOB
+#define HDMI_CEC_LINE_GPIO_CLK                              RCC_AHBPeriph_GPIOB
+#define HDMI_CEC_LINE_PIN_SOURCE                            GPIO_PinSource8
+#define HDMI_CEC_GPIO_AF                                    GPIO_AF_6
+
+#define HDMI_CEC_I2C_TIMING                                 0x00330E10
+#define HDMI_CEC_I2C_SLAVE_ADDRESS7                         0xA0
+
+/**
+  * @brief  HDMI CEC Root (Mainly for TV with a fixed physical address (0.0.0.0))
+  *         If you want to configure the STM32373C-EVAL board as CEC Root (Sink)
+  *         change the following define to 0x1    
+  */
+#define HDMI_CEC_ROOT                                       0x00
+
+/**
+  * @brief  To select if the DDC Channel will be used for physical address discovery
+  *         or not. To use the DDC Channel to read the EDID structure uncomment
+  *         the following line.   
+  *         If the device is configured as HMDI source it should read his own physical
+  *         address from the sink that is connected to.
+  */
+/* #define HDMI_CEC_USE_DDC    */
+
+/**
+  * @brief  CEC version: V1.4
+  */
+#define HDMI_CEC_VERSION                                    0x05  /*0x04 For CEC version: V1.3.a*/
+
+/**
+  * @brief  Reason for Abort feature
+  */
+#define HDMI_CEC_UNRECOGNIZED_OPCODE                        0x00
+#define HDMI_CEC_NOT_CORRECT_MODETORESPOND                  0x01
+#define HDMI_CEC_CANNOTPROVIDE_SOURCE                       0x02
+#define HDMI_CEC_INVALID_OPERAND                            0x03
+#define HDMI_CEC_REFUSED                                    0x04
+
+/**
+  * @brief  HDMI CEC specific commands
+  */
+#define HDMI_CEC_OPCODE_ACTIVE_SOURCE                       ((uint8_t) 0x82)
+#define HDMI_CEC_OPCODE_IMAGE_VIEW_ON                       ((uint8_t) 0x04)
+#define HDMI_CEC_OPCODE_TEXT_VIEW_ON                        ((uint8_t) 0x0D)
+#define HDMI_CEC_OPCODE_INACTIVE_SOURCE                     ((uint8_t) 0x9D)
+#define HDMI_CEC_OPCODE_REQUEST_ACTIVE_SOURCE               ((uint8_t) 0x85)
+#define HDMI_CEC_OPCODE_ROUTING_CHANGE                      ((uint8_t) 0x80)
+#define HDMI_CEC_OPCODE_ROUTING_INFORMATION                 ((uint8_t) 0x81)
+#define HDMI_CEC_OPCODE_SET_STREAM_PATH                     ((uint8_t) 0x86)
+#define HDMI_CEC_OPCODE_STANDBY                             ((uint8_t) 0x36)
+#define HDMI_CEC_OPCODE_RECORD_OFF                          ((uint8_t) 0x0B)
+#define HDMI_CEC_OPCODE_RECORD_ON                           ((uint8_t) 0x09)
+#define HDMI_CEC_OPCODE_RECORD_STATUS                       ((uint8_t) 0x0A)
+#define HDMI_CEC_OPCODE_RECORD_TV_SCREEN                    ((uint8_t) 0x0F)
+#define HDMI_CEC_OPCODE_CLEAR_ANALOGUE_TIMER                ((uint8_t) 0x33)
+#define HDMI_CEC_OPCODE_CLEAR_DIGITAL_TIMER                 ((uint8_t) 0x99)
+#define HDMI_CEC_OPCODE_CLEAR_EXTERNAL_TIMER                ((uint8_t) 0xA1)
+#define HDMI_CEC_OPCODE_SET_ANALOGUE_TIMER                  ((uint8_t) 0x34)
+#define HDMI_CEC_OPCODE_SET_DIGITAL_TIMER                   ((uint8_t) 0x97)
+#define HDMI_CEC_OPCODE_SET_EXTERNAL_TIMER                  ((uint8_t) 0xA2)
+#define HDMI_CEC_OPCODE_SET_TIMER_PROGRAM_TITLE             ((uint8_t) 0x67)
+#define HDMI_CEC_OPCODE_TIMER_CLEARED_STATUS                ((uint8_t) 0x43)
+#define HDMI_CEC_OPCODE_TIMER_STATUS                        ((uint8_t) 0x35)
+#define HDMI_CEC_OPCODE_CEC_VERSION                         ((uint8_t) 0x9E)
+#define HDMI_CEC_OPCODE_GET_CEC_VERSION                     ((uint8_t) 0x9F)
+#define HDMI_CEC_OPCODE_GIVE_PHYSICAL_ADDRESS               ((uint8_t) 0x83)
+#define HDMI_CEC_OPCODE_GET_MENU_LANGUAGE                   ((uint8_t) 0x91)
+#define HDMI_CEC_OPCODE_REPORT_PHYSICAL_ADDRESS             ((uint8_t) 0x84)
+#define HDMI_CEC_OPCODE_SET_MENU_LANGUAGE                   ((uint8_t) 0x32)
+#define HDMI_CEC_OPCODE_DECK_CONTROL                        ((uint8_t) 0x42)
+#define HDMI_CEC_OPCODE_DECK_STATUS                         ((uint8_t) 0x1B)
+#define HDMI_CEC_OPCODE_GIVE_DECK_STATUS                    ((uint8_t) 0x1A)
+#define HDMI_CEC_OPCODE_PLAY                                ((uint8_t) 0x41)
+#define HDMI_CEC_OPCODE_GIVE_TUNER_DEVICE_STATUS            ((uint8_t) 0x08)
+#define HDMI_CEC_OPCODE_SELECT_ANALOGUE_SERVICE             ((uint8_t) 0x92)
+#define HDMI_CEC_OPCODE_SELECT_DIGITAL_SERVICE              ((uint8_t) 0x93)
+#define HDMI_CEC_OPCODE_TUNER_DEVICE_STATUS                 ((uint8_t) 0x07)
+#define HDMI_CEC_OPCODE_TUNER_STEP_DECREMENT                ((uint8_t) 0x06)
+#define HDMI_CEC_OPCODE_TUNER_STEP_INCREMENT                ((uint8_t) 0x05)
+#define HDMI_CEC_OPCODE_DEVICE_VENDOR_ID                    ((uint8_t) 0x87)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_VENDOR_ID               ((uint8_t) 0x8C)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND                      ((uint8_t) 0x89)
+#define HDMI_CEC_OPCODE_VENDOR_COMMAND_WITH_ID              ((uint8_t) 0xA0)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_DOWN           ((uint8_t) 0x8A)
+#define HDMI_CEC_OPCODE_VENDOR_REMOTE_BUTTON_UP             ((uint8_t) 0x8B)
+#define HDMI_CEC_OPCODE_SET_OSD_STRING                      ((uint8_t) 0x64)
+#define HDMI_CEC_OPCODE_GIVE_OSD_NAME                       ((uint8_t) 0x46)
+#define HDMI_CEC_OPCODE_SET_OSD_NAME                        ((uint8_t) 0x47)
+#define HDMI_CEC_OPCODE_MENU_REQUEST                        ((uint8_t) 0x8D)
+#define HDMI_CEC_OPCODE_MENU_STATUS                         ((uint8_t) 0x8E)
+#define HDMI_CEC_OPCODE_USER_CONTROL_PRESSED                ((uint8_t) 0x44)
+#define HDMI_CEC_OPCODE_USER_CONTROL_RELEASED               ((uint8_t) 0x45)
+#define HDMI_CEC_OPCODE_GIVE_DEVICE_POWER_STATUS            ((uint8_t) 0x8F)
+#define HDMI_CEC_OPCODE_REPORT_POWER_STATUS                 ((uint8_t) 0x90)
+#define HDMI_CEC_OPCODE_FEATURE_ABORT                       ((uint8_t) 0x00)
+#define HDMI_CEC_OPCODE_ABORT                               ((uint8_t) 0xFF)
+#define HDMI_CEC_OPCODE_GIVE_AUDIO_STATUS                   ((uint8_t) 0x71)
+#define HDMI_CEC_OPCODE_GIVE_SYSTEM_AUDIO_MODE_STATUS       ((uint8_t) 0x7D)
+#define HDMI_CEC_OPCODE_REPORT_AUDIO_STATUS                 ((uint8_t) 0x7A)
+#define HDMI_CEC_OPCODE_SET_SYSTEM_AUDIO_MODE               ((uint8_t) 0x72)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_REQUEST           ((uint8_t) 0x70)
+#define HDMI_CEC_OPCODE_SYSTEM_AUDIO_MODE_STATUS            ((uint8_t) 0x7E)
+#define HDMI_CEC_OPCODE_SET_AUDIO_RATE                      ((uint8_t) 0x9A)
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32373C_EVAL_CEC_Exported_Functions
+  * @{
+  */
+HDMI_CEC_Error HDMI_CEC_Init(void);
+HDMI_CEC_Error HDMI_CEC_TransmitMessage(HDMI_CEC_Message *HDMI_CEC_TX_MessageStructure);
+HDMI_CEC_Error HDMI_CEC_GetErrorStatus (void);
+void HDMI_CEC_ProcessIRQSrc(void);
+HDMI_CEC_Error HDMI_CEC_ReportPhysicalAddress(void);
+void HDMI_CEC_CommandCallBack(void);
+HDMI_CEC_Error HDMI_CEC_CheckConnectedDevices(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32373C_EVAL_CEC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.c
new file mode 100644
index 0000000..8cc95d1
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.c
@@ -0,0 +1,580 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_i2c_ee_cpal.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides a set of functions needed to manage I2C  
+  *          EEPROM memory. 
+  *            
+  *          ===================================================================
+  *          Notes: 
+  *           - This driver is intended for STM32F37x families devices only.
+  *           - The I2C EEPROM memory (M24LR64) is available in RF EEPROM daughter 
+  *             board (ANT7-M24LR-A) provided with the EVAL board, to use this 
+  *             driver you have to connect the ANT7-M24LR-A to CN12 connector.   
+  *          ===================================================================  
+  *
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. 
+  *        
+  *          @note This file has been updated to use the CPAL library drivers 
+  *                 instead of the Standard peripheral drivers.
+  *
+  *          @note In this driver, basic read and write functions (sEE_ReadBuffer() 
+  *                and sEE_WritePage()) use the DMA or Interrupt  to perform the 
+  *                data transfer to/from EEPROM memory.
+  *                Thus, after calling these two functions, user application may 
+  *                perform other tasks while data transfer is ongoing. 
+  *                The application should then monitor the variable holding 
+  *                the state of EEPROM in order to determine when the transfer is
+  *                completed . Stopping transfer tasks are performed into DMA or I2C                  
+  *                interrupt handlers (which are integrated into this driver).
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval_i2c_ee_cpal.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+
+/*========= sEE_Write_TypeDef =========*/
+/* sEE Write parameter structure definition */   
+
+typedef struct  
+{
+  __IO uint32_t sEEDataNum;             /*!< The number of data that will be written in next transfer */ 
+  
+  uint32_t sEEWriteAddr;                /*!< Physical memory address of EEPROM where data will be written */ 
+  
+  __IO uint8_t *sEEpBuffer;             /*!< The address of the buffer from which data transfer should start */
+  
+  __IO uint16_t sEENumOfPage;           /*!< The number of page that will be written  */  
+  
+  __IO uint8_t sEENumOfSingle;          /*!< The number of single data that will be written */ 
+  
+  __IO uint8_t sEENextWrite;            /*!< This member indicates there is remaining transfers  */   
+  
+} sEE_WriteTypeDef; 
+
+/* Private defines -----------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/*========= Local Structures declaration =========*/
+
+#ifdef CPAL_USE_I2C1 
+ sEE_InitTypeDef sEE1_DevStructure = {&I2C1_DevStructure, 0, 0, 0, sEE_STATE_IDLE};          /* Initialize All structure parameters to 0 */  
+#endif /* CPAL_USE_I2C1 */
+
+#ifdef CPAL_USE_I2C2 
+ sEE_InitTypeDef sEE2_DevStructure = {&I2C2_DevStructure, 0, 0, 0, sEE_STATE_IDLE};          /* Initialize All structure parameters to 0 */  
+#endif /* CPAL_USE_I2C2 */
+
+sEE_InitTypeDef* sEE_DevStructures[CPAL_I2C_DEV_NUM] =
+{
+#ifdef CPAL_USE_I2C1 
+  &sEE1_DevStructure,
+#else
+  pNULL,
+#endif
+
+#ifdef CPAL_USE_I2C2 
+  &sEE2_DevStructure,
+#else
+  pNULL,
+#endif
+};
+
+#ifdef CPAL_USE_I2C1 
+ sEE_WriteTypeDef sEE1_WriteStructure = {0, 0, pNULL, 0, 0, 0};          /* Initialize All structure parameters to 0 */  
+#endif /* CPAL_USE_I2C1 */
+
+#ifdef CPAL_USE_I2C2 
+ sEE_WriteTypeDef sEE2_WriteStructure = {0, 0, pNULL, 0, 0, 0};          /* Initialize All structure parameters to 0 */  
+#endif /* CPAL_USE_I2C2 */
+
+sEE_WriteTypeDef* sEE_WriteStructures[CPAL_I2C_DEV_NUM] =
+{
+#ifdef CPAL_USE_I2C1 
+  &sEE1_WriteStructure,
+#else
+  pNULL,
+#endif
+
+#ifdef CPAL_USE_I2C2 
+  &sEE2_WriteStructure,
+#else
+  pNULL,
+#endif
+};
+
+#ifdef CPAL_USE_I2C1 
+CPAL_TransferTypeDef  sEE1_TXTransfer = { 
+                        /* Initialize TX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+
+CPAL_TransferTypeDef  sEE1_RXTransfer = {
+                        /* Initialize RX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+#endif /* CPAL_USE_I2C1 */
+
+#ifdef CPAL_USE_I2C2 
+CPAL_TransferTypeDef  sEE2_TXTransfer = { 
+                        /* Initialize TX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+
+CPAL_TransferTypeDef  sEE2_RXTransfer = {
+                        /* Initialize RX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+#endif /* CPAL_USE_I2C2 */
+
+CPAL_TransferTypeDef* sEE_TXTransfer[CPAL_I2C_DEV_NUM] =
+{
+#ifdef CPAL_USE_I2C1 
+  &sEE1_TXTransfer,
+#else
+  pNULL,
+#endif
+
+#ifdef CPAL_USE_I2C2 
+  &sEE2_TXTransfer,
+#else
+  pNULL,
+#endif
+};
+
+
+CPAL_TransferTypeDef* sEE_RXTransfer[CPAL_I2C_DEV_NUM] =
+{
+#ifdef CPAL_USE_I2C1 
+  &sEE1_RXTransfer,
+#else
+  pNULL,
+#endif
+
+#ifdef CPAL_USE_I2C2 
+  &sEE2_RXTransfer,
+#else
+  pNULL,
+#endif
+};
+
+/**
+  * @}
+  */ 
+
+/* Private function prototypes -----------------------------------------------*/
+
+
+static uint32_t sEE_WritePage(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, \
+                              uint16_t WriteAddr, uint32_t NumByteToWrite);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  DeInitialize peripherals used by the I2C EEPROM driver.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @retval None
+  */
+void sEE_DeInit(sEE_InitTypeDef* sEEInitStruct)
+{ 
+  /* Deinitialize CPAL peripheral */
+  CPAL_I2C_DeInit(sEEInitStruct->sEE_CPALStructure);
+}
+
+/**
+  * @brief  Initialize peripherals used by the I2C EEPROM driver.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @retval None
+  */
+void sEE_Init(sEE_InitTypeDef* sEEInitStruct)
+{ 
+  /* Initialize CPAL peripheral */
+  CPAL_I2C_Init(sEEInitStruct->sEE_CPALStructure);  
+}
+
+/**
+  * @brief  Initialize sEE CPAL Structure used by the I2C EEPROM driver.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @retval None
+  */
+void sEE_StructInit(sEE_InitTypeDef* sEEInitStruct)
+{   
+  /* Set CPAL structure parameters to their default values */  
+  CPAL_I2C_StructInit(sEEInitStruct->sEE_CPALStructure);
+  
+  /* Set I2C clock speed */
+  sEEInitStruct->sEE_CPALStructure->pCPAL_I2C_Struct->I2C_Timing = sEE_I2C_TIMING;
+
+#ifdef sEE_IT
+  /* Select Interrupt programming model */
+  sEEInitStruct->sEE_CPALStructure->CPAL_ProgModel =  CPAL_PROGMODEL_INTERRUPT;
+#else
+  /* Select DMA programming model */
+  sEEInitStruct->sEE_CPALStructure->CPAL_ProgModel =  CPAL_PROGMODEL_DMA;
+#endif /* sEE_IT */
+  
+  /* Disable all options */
+  sEEInitStruct->sEE_CPALStructure->wCPAL_Options = 0;    
+}
+
+/**
+  * @brief  Reads a block of data from the EEPROM.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @param  pBuffer : pointer to the buffer that receives the data read from 
+  *         the EEPROM.
+  * @param  ReadAddr : EEPROM's internal address to read from.
+  * @param  NumByteToRead : pointer to the variable holding number of bytes to 
+  *         read from the EEPROM. 
+  * 
+  *        @note The variable pointed by NumByteToRead is reset to 0 when all the 
+  *              data are read from the EEPROM. Application should monitor this 
+  *              variable in order know when the transfer is complete.
+  * 
+  * @note When number of data to be read is higher than 1, this function just 
+  *       configure the communication and enable the DMA channel to transfer data.
+  *       Meanwhile, the user application may perform other tasks.
+  *       When number of data to be read is 1, then the DMA is not used.
+  * 
+  * @retval None
+  */
+uint32_t sEE_ReadBuffer(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, \
+                        uint16_t ReadAddr, uint32_t NumByteToRead)
+{  
+  if (sEEInitStruct->sEEState == sEE_STATE_IDLE)
+  {
+    sEEInitStruct->sEEState = sEE_STATE_READING;
+    
+    sEEInitStruct->sEE_CPALStructure->wCPAL_Options = 0;
+
+ /* Enable 16Bit memory register option on CPAL */
+  if (sEEInitStruct->sEEMemoryAddrMode & sEE_OPT_16BIT_REG)
+  {
+    sEEInitStruct->sEE_CPALStructure->wCPAL_Options = CPAL_OPT_16BIT_REG;
+  }
+  
+   /* Enable no memory addressing mode option on CPAL */
+  if (sEEInitStruct->sEEMemoryAddrMode & sEE_OPT_NO_MEM_ADDR)
+  {
+    sEEInitStruct->sEE_CPALStructure->wCPAL_Options |= CPAL_OPT_NO_MEM_ADDR;
+  }
+    
+    sEEInitStruct->sEE_CPALStructure->pCPAL_TransferRx   = sEE_RXTransfer[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]; 
+    
+    sEEInitStruct->sEE_CPALStructure->pCPAL_TransferRx->wNumData = (uint32_t)(NumByteToRead);
+    sEEInitStruct->sEE_CPALStructure->pCPAL_TransferRx->pbBuffer = pBuffer;
+    sEEInitStruct->sEE_CPALStructure->pCPAL_TransferRx->wAddr1   = (uint32_t)((uint8_t)sEEInitStruct->sEEAddress);
+    sEEInitStruct->sEE_CPALStructure->pCPAL_TransferRx->wAddr2   = (uint32_t)((uint16_t)ReadAddr);
+    
+    return CPAL_I2C_Read(sEEInitStruct->sEE_CPALStructure);  
+  }
+  else
+  {
+    return CPAL_FAIL;
+  }
+}
+
+/**
+  * @brief  Writes buffer of data to the I2C EEPROM.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @param  pBuffer : pointer to the buffer  containing the data to be written 
+  *         to the EEPROM.
+  * @param  WriteAddr : EEPROM's internal address to write to.
+  * @param  NumByteToWrite : number of bytes to write to the EEPROM.
+  * @retval None
+  */
+uint32_t sEE_WriteBuffer(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, \
+                         uint16_t WriteAddr, uint32_t NumByteToWrite)
+{   
+  uint32_t  DataNum = 0;
+  uint16_t count = 0;
+  uint16_t Addr = 0;
+  
+  if (sEEInitStruct->sEEState == sEE_STATE_IDLE)
+  {
+    sEEInitStruct->sEEState = sEE_STATE_WRITING;
+    
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEDataNum = 0;
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEWriteAddr = 0;
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEpBuffer = pNULL;
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfPage = 0;
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENextWrite = 0;
+    sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfSingle = 0;
+    
+    /* if one data will be written */
+    if (NumByteToWrite == 1)
+    { 
+      /* Transfer complete */
+      sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENextWrite = 0;
+      
+      /* update number od data for write */
+      DataNum = NumByteToWrite;
+      
+      if(sEE_WritePage(sEEInitStruct, pBuffer, WriteAddr, DataNum) != CPAL_PASS)
+      {    
+        return CPAL_FAIL;
+      }      
+    }
+    /* Use Write page */
+    else
+    {            
+      /* if Address aligned reset count value to 0 */
+      Addr = WriteAddr % sEEInitStruct->sEEPageSize;
+      
+      if (Addr == 0)
+      {
+        count = 0;
+      }
+      else
+      { 
+       count = sEEInitStruct->sEEPageSize - Addr;
+       
+       if (NumByteToWrite <= count)
+        {
+          count = NumByteToWrite;
+        }        
+      }
+      
+      /* Get Number of page for write and number of single byte */
+      sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfPage = \
+                                 (uint16_t)((NumByteToWrite - count) / sEEInitStruct->sEEPageSize);
+      sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfSingle = \
+                                  (uint8_t)((NumByteToWrite - count) % sEEInitStruct->sEEPageSize);
+           
+      /* If WriteAddr is sEE_PAGESIZE is not aligned  */
+      if (Addr != 0) 
+      {
+        /* Update Number of data to write */
+        sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEDataNum = count; 
+      }    
+      /* If WriteAddr is sEE_PAGESIZE is aligned  */
+      else
+      {
+        /* if only single byte must be written */
+        if (sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfPage == 0)
+        {
+          /* update number of data to write */
+          sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEDataNum = \
+            sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfSingle;
+          
+          /* reset number of single */
+          sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfSingle = 0;
+        }
+        else
+        {
+          /* update number of data to write */
+          sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEDataNum =  (uint32_t)((uint16_t)sEEInitStruct->sEEPageSize); 
+          
+          /* update number of page */
+          sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfPage--;
+        }      
+      }
+      
+      /* update global variable */
+      DataNum = sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEDataNum;
+      sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEWriteAddr = (uint32_t)((uint16_t)WriteAddr);
+      sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEEpBuffer = pBuffer;
+            
+      /* If there are remaining data to transfer */
+      if ((sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfPage != 0) 
+          || (sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENumOfSingle != 0))
+      {     
+        /* update global variable */
+        sEE_WriteStructures[sEEInitStruct->sEE_CPALStructure->CPAL_Dev]->sEENextWrite = 1;         
+      } 
+           
+      /* Write data on EEPROM */
+      if (sEE_WritePage(sEEInitStruct, pBuffer, WriteAddr, DataNum) != CPAL_PASS)
+      {
+        return CPAL_FAIL;
+      }     
+      
+    }  
+    return CPAL_PASS;
+  }
+  else
+  {
+    return CPAL_FAIL;
+  }
+}
+
+/**
+  * @brief  Handle EEPROM Write operation 
+  * @param  Device : sEE CPAL device instance
+  * @retval None
+  */
+uint32_t sEE_WriteHandler(CPAL_DevTypeDef Device)      
+{  
+  uint32_t  DataNum = 0;
+  
+  /* wait until EEPROM ready for transfer */
+  while (sEE_WaitEepromStandbyState(Device) == CPAL_FAIL);
+  
+  /* if there are remaining data for write */
+  if (sEE_WriteStructures[Device]->sEENextWrite != 0)
+  {  
+    sEE_WriteStructures[Device]->sEEWriteAddr += sEE_WriteStructures[Device]->sEEDataNum;
+    sEE_WriteStructures[Device]->sEEpBuffer += sEE_WriteStructures[Device]->sEEDataNum;
+    sEE_WriteStructures[Device]->sEENextWrite = 0;
+        
+    /* if page must be written in EEPROM */
+    if(sEE_WriteStructures[Device]->sEENumOfPage != 0)
+    {
+      sEE_WriteStructures[Device]->sEEDataNum = (uint32_t)((uint16_t)sEE_DevStructures[Device]->sEEPageSize);
+      sEE_WriteStructures[Device]->sEENumOfPage--;
+    }
+    /* if single byte must be written in EEPROM */
+    else if (sEE_WriteStructures[Device]->sEENumOfSingle != 0)
+    {
+      sEE_WriteStructures[Device]->sEEDataNum = (uint32_t)((uint8_t)sEE_WriteStructures[Device]->sEENumOfSingle);
+      sEE_WriteStructures[Device]->sEENumOfSingle = 0;
+      sEE_WriteStructures[Device]->sEENextWrite = 0;
+    }
+    
+    /* update number of date for write */
+    DataNum = sEE_WriteStructures[Device]->sEEDataNum;
+    
+     /* if another data must be written */
+    if ((sEE_WriteStructures[Device]->sEENumOfPage != 0) 
+        || (sEE_WriteStructures[Device]->sEENumOfSingle != 0))
+    {      
+      sEE_WriteStructures[Device]->sEENextWrite = 1;
+    }   
+    
+    /* write data in EEPROM */
+    sEE_WritePage(sEE_DevStructures[Device],(uint8_t*)sEE_WriteStructures[Device]->sEEpBuffer, \
+                                            sEE_WriteStructures[Device]->sEEWriteAddr, DataNum); 
+  }
+  else
+  {
+    if (sEE_DevStructures[Device]->sEEState != sEE_STATE_ERROR)
+    {
+      /* Reset EEPROM State */
+      sEE_DevStructures[Device]->sEEState = sEE_STATE_IDLE;
+    }
+  }
+  
+  return CPAL_PASS;
+}
+
+
+/**
+  * @brief  Handle EEPROM Read operation 
+  * @param  Device : sEE CPAL device instance
+  * @retval None
+  */
+uint32_t sEE_ReadHandler(CPAL_DevTypeDef Device)      
+{  
+  if (sEE_DevStructures[Device]->sEEState != sEE_STATE_ERROR)
+  {
+    /* Reset EEPROM State */
+    sEE_DevStructures[Device]->sEEState = sEE_STATE_IDLE;
+  }
+  
+  return CPAL_PASS;
+}
+
+
+/**
+  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle.
+  * @note   The number of byte can't exceed the EEPROM page size.
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @param  pBuffer : pointer to the buffer containing the data to be written to 
+  *         the EEPROM.
+  * @param  WriteAddr : EEPROM's internal address to write to.
+  * @param  NumByteToWrite : pointer to the variable holding number of bytes to 
+  *         written to the EEPROM. 
+  * 
+  *        @note The variable pointed by NumByteToWrite is reset to 0 when all the 
+  *              data are read from the EEPROM. Application should monitor this 
+  *              variable in order know when the transfer is complete.
+  * 
+  * @note When number of data to be written is higher than 1, this function just 
+  *       configure the communication and enable the DMA channel to transfer data.
+  *       Meanwhile, the user application may perform other tasks.
+  *       When number of data to be written is 1, then the DMA is not used.
+  * 
+  * @retval None
+  */
+static uint32_t sEE_WritePage(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, \
+                              uint16_t WriteAddr, uint32_t NumByteToWrite)
+{     
+  sEEInitStruct->sEE_CPALStructure->wCPAL_Options = 0;
+  
+  /* Enable 16Bit memory register option on CPAL */
+  if (sEEInitStruct->sEEMemoryAddrMode & sEE_OPT_16BIT_REG)
+  {
+    sEEInitStruct->sEE_CPALStructure->wCPAL_Options = CPAL_OPT_16BIT_REG;
+  }
+  
+  sEEInitStruct->sEE_CPALStructure->pCPAL_TransferTx   = sEE_TXTransfer[sEEInitStruct->sEE_CPALStructure->CPAL_Dev];  
+  
+  /* Configure transfer parameters */  
+  sEEInitStruct->sEE_CPALStructure->pCPAL_TransferTx->wNumData = (uint32_t)(NumByteToWrite);
+  sEEInitStruct->sEE_CPALStructure->pCPAL_TransferTx->pbBuffer = pBuffer;
+  sEEInitStruct->sEE_CPALStructure->pCPAL_TransferTx->wAddr1   = (uint32_t)((uint8_t)sEEInitStruct->sEEAddress);
+  sEEInitStruct->sEE_CPALStructure->pCPAL_TransferTx->wAddr2   = (uint32_t)((uint16_t)WriteAddr);
+  
+  /* Write Operation */
+  return CPAL_I2C_Write(sEEInitStruct->sEE_CPALStructure);
+  
+}
+
+/**
+  * @brief  Wait for EEPROM Standby state
+  * @param  Device : sEE CPAL device instance
+  * @retval None
+  */
+uint32_t sEE_WaitEepromStandbyState(CPAL_DevTypeDef Device)      
+{   
+  sEE_DevStructures[Device]->sEE_CPALStructure->pCPAL_TransferTx = sEE_TXTransfer[Device];     
+  sEE_DevStructures[Device]->sEE_CPALStructure->pCPAL_TransferTx->wAddr1 = \
+                            (uint32_t)((uint8_t)sEE_DevStructures[Device]->sEEAddress);
+  
+  return CPAL_I2C_IsDeviceReady(sEE_DevStructures[Device]->sEE_CPALStructure);
+}
+
+
+/**
+  * @brief  Wait for EEPROM Standby state
+  * @param  sEEInitStruct : Pointer to sEE Device structure
+  * @retval None
+  */
+uint32_t sEE_GetEepromState(sEE_InitTypeDef* sEEInitStruct)      
+{       
+  return sEEInitStruct->sEEState;
+}
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.h
new file mode 100644
index 0000000..9779bb9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_ee_cpal.h
@@ -0,0 +1,231 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_i2c_ee_cpal.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for 
+  *          the stm32373c_eval_i2c_ee_cpal.c firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_I2C_EE_CPAL_H
+#define __STM32373C_EVAL_I2C_EE_CPAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*===================================================================================
+                                      User NOTES
+=====================================================================================
+
+---------------------------------
+   How To use the EEPROM Driver:
+---------------------------------
+----- All EEPROM operations are controlled and monitored through a single
+      structure. This structure holds all necessary parameters to manage EEPROM
+      communication (pointer to CPAL I2C device structure, EEPROM address, 
+      EEPROM page size, EEPROM memory addressing mode, EEPROM state).
+         
+----- User should follow these steps to use this driver correctly :
+
+      -1-  STRUCTURE INITIALIZATION 
+      Start by initializing the structure holding EEPROM Information. To perform 
+      this action, the global variable sEEx_DevStructure declared in EEPROM driver 
+      as sEE_InitTypeDef (sEE1_DevStructure for EEPROM connected with I2C1, 
+      sEE2_DevStructure for EEPROM connected with I2C1 ...) must be used.
+
+      sEE_InitTypeDef structure contains five parameters:
+
+           *- CPAL_InitTypeDef* sEE_CPALStructure : Pointer on a CPAL Device structure 
+                                                    relative to the device instantiated 
+                                                    to communicate with EEPROM.
+
+           *- uint32_t sEEAddress : Contains the EEPROM device Address.
+  
+           *- uint32_t sEEPageSize : Contains the page size of EEPROM Memory.
+
+           *- uint8_t sEEMemoryAddrMode : Bit-field value specifying Memory Addressing Mode.
+
+           *- __IO sEE_StateTypeDef sEEState : Holds the current State of the EEPROM device. 
+
+       To configure this structure, user must initialize only three parameters 
+       (sEEAddress, sEEPageSize, sEEMemoryAddrMode).
+       
+       Example:
+         sEE1_DevStructure.sEEAddress = 0xA0; // set EEPROM address to 0xA0 
+         sEE1_DevStructure.sEEPageSize = 32;  // set page size to 32
+         sEE1_DevStructure.sEEMemoryAddrMode = sEE_OPT_16BIT_REG; // enable 16Bit memory addressing mode
+                           
+      -2- DEVICE CONFIGURATION 
+      Call the function sEE_StructInit() to initialize I2Cx CPAL device structure 
+      relative to EEPROM than call sEE_Init() to configure the selected device
+      with the selected configuration.
+      
+      -3- READ / WRITE OPERATIONS 
+      Call the function sEE_WriteBuffer() or sEE_ReadBuffer() to perform transfer operations. 
+      These functions start data transfer and exit. sEE_WriteHandler() and sEE_ReadHandler()
+      handle the remainder of the communication. sEE_WriteHandler() must be called in 
+      CPAL_I2C_TXTC_UserCallback() and sEE_ReadHandler() must be called in CPAL_I2C_RXTC_UserCallback().
+      These two callbacks are implemented in "cpal_usercallback.c" file.      
+           
+      Example of how to implement sEE_WriteHandler() in CPAL_I2C_TXTC_UserCallback():
+      
+            1** Comment "#define CPAL_I2C_TXTC_UserCallback   (void)" in cpal_conf.h.
+            2** Implement CPAL_I2C_TXTC_UserCallback in "cpal_usercallback.c" file.
+               
+               void CPAL_I2C_TXTC_UserCallback(CPAL_InitTypeDef* pDevInitStruct)
+               {
+                 sEE_WriteHandler(pDevInitStruct->CPAL_Dev);
+               }
+      
+      User should monitor transfer by testing the value of sEEState parameter of
+      sEEx_DevStructure. When transfer is ongoing sEEState is equal to sEE_STATE_WRITING
+      or sEE_STATE_READING. After transfer complete this parameter is set to sEE_STATE_IDLE.
+      
+      Example of how to wait until EEPROM communication finishes:
+            
+            while(sEE_GetEepromState(&sEE_DevStructure) != sEE_STATE_IDLE)
+              {
+                //Application may perform other tasks while transfer operation is ongoing 
+              }
+      
+      -4- DEVICE DEINITIALIZATION 
+      When transfer operations are finished, you may call sEE_DeInit() to disable I2Cx device 
+      and related resources (GPIO, DMA , IT and NVIC) relative to used EEPROM. 
+      
+*****************************END OF User Notes**********************************************/
+ 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_i2c_cpal.h"
+   
+/* Exported types ------------------------------------------------------------*/
+
+/*========= sEE_State_Enum =========*/
+/* sEE global State enumeration contains the current state of EEPROM. 
+   Before starting each operation this state is tested. After each operation 
+   sEE_State is updated with the new value resulting from the relative operation.*/
+
+ typedef enum
+{ 
+  sEE_STATE_IDLE        = 0x01,         /*!<This state indicates that the EEPROM device is in idle state */ 
+
+  sEE_STATE_WRITING     = 0x02,         /*!<This state indicates that write operation is ongoing */
+
+  sEE_STATE_READING     = 0x03,         /*!<This state indicates that read operation is ongoing */
+  
+  sEE_STATE_ERROR       = 0x04,         /*!<This state indicates that an error is occurred during 
+                                            last operation */
+  
+}sEE_StateTypeDef;
+
+
+/*========= CPAL_sEE_TypeDef =========*/
+/* sEE Device structure definition */
+typedef struct  
+{
+  CPAL_InitTypeDef* sEE_CPALStructure;  /*!< Pointer on a CPAL Device structure relative to the device 
+                                             instantiated to communicate with EEPROM */
+  
+  uint16_t sEEPageSize;                 /*!< Contains the page size of EEPROM Memory*/ 
+  
+  uint8_t sEEAddress;                   /*!< Contains the EEPROM device Address */
+  
+  
+  uint8_t sEEMemoryAddrMode;            /*!< Bit-field value specifying Memory Addressing Mode. Can be 
+                                             any combination of following values: 
+                                             sEE_Memory_Addressing_Mode_Defines */ 
+  
+  __IO sEE_StateTypeDef sEEState;       /*!< Holds the current State of the EEPROM device. The state 
+                                             parameter can be one of the following values: sEE_State_Enum  */
+  
+} sEE_InitTypeDef;   
+
+
+/*========= sEE_Global_Device_Structures =========*/
+/* sEE Global Device Structures are the Global default structures which 
+   are used to handle sEE configuration and status.*/ 
+   
+extern sEE_InitTypeDef* sEE_DevStructures[];
+
+#ifdef CPAL_USE_I2C1 
+extern sEE_InitTypeDef sEE1_DevStructure;
+#endif /* CPAL_USE_I2C1 */
+
+#ifdef CPAL_USE_I2C2 
+extern sEE_InitTypeDef sEE2_DevStructure;
+#endif /* CPAL_USE_I2C2 */
+
+/* Exported constants --------------------------------------------------------*/
+
+/*============== TIMING Configuration ==========================*/
+/* I2C TIMING Register define */
+/* I2C TIMING is calculated in case of the I2C Clock source is the SYSCLK = 72 MHz */
+/* When using sEE_M24M01 set TIMING to 0x00C4092A to reach 1 MHz speed (Rise time = 26ns, Fall time = 2ns) */
+/* When using sEE_M24LR64 set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define sEE_I2C_TIMING             0xC062121F
+
+
+/*============== Programming model Configuration ==========================*/
+/* Select interrupt programming model : By default DMA programming model is selected.
+ To select interrupt programming model uncomment this define */
+//#define sEE_IT
+
+/*========= sEE_Memory_Addressing_Mode_Defines =========*/
+/* sEE Memory_Addressing_Mode defines can be affected to sEEMemoryAddrMode which is 
+   a bit-field argument so any combination of these parameters can be selected. 
+   If one option is not selected then the relative feature is disabled.*/
+   
+
+#define sEE_OPT_NO_MEM_ADDR            ((uint8_t)0x01)  /*!<Enable No Memory addressing mode for read operation : only EEPROM 
+                                                            device address sent. No Register/Physical address to be sent after 
+                                                            addressing phase */  
+
+#define sEE_OPT_16BIT_REG              ((uint8_t)0x02)  /*!<Enable 16-Bit Register/Physical addressing mode (two bytes, 
+                                                            MSB first). This option is supported only when sEE_OPT_NO_MEM_ADDR 
+                                                            option is not set */ 
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void sEE_DeInit(sEE_InitTypeDef* sEEInitStruct);
+void sEE_Init(sEE_InitTypeDef* sEEInitStruct);
+void sEE_StructInit(sEE_InitTypeDef* sEEInitStruct);
+uint32_t sEE_WriteBuffer(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, uint16_t WriteAddr, uint32_t NumByteToWrite);
+uint32_t sEE_WriteHandler(CPAL_DevTypeDef Device);
+uint32_t sEE_ReadBuffer(sEE_InitTypeDef* sEEInitStruct, uint8_t* pBuffer, uint16_t ReadAddr, uint32_t NumByteToRead);
+uint32_t sEE_ReadHandler(CPAL_DevTypeDef Device);
+uint32_t sEE_WaitEepromStandbyState(CPAL_DevTypeDef Device);
+uint32_t sEE_GetEepromState(sEE_InitTypeDef* sEEInitStruct);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32373C_EVAL_I2C_EE_CPAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.c
new file mode 100644
index 0000000..db14977
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.c
@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_i2c_tsensor_cpal.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides a set of functions needed to manage the I2C LM75 
+  *          temperature sensor mounted on STM32373C-EVAL board . 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this sensor. 
+  *            
+  *          @note This file is a modified version of stm32373c_eval_i2c_tsensor.c driver;
+  *                I2C CPAL library drivers are used instead of the Standard Peripherals
+  *                I2C driver.
+  *                 
+  *
+  *     +-----------------------------------------------------------------+
+  *     |                        Pin assignment                           |                 
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32 I2C Pins                       |   STLM75  |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | LM75_I2C_SDA_PIN/ SDA                 |   SDA     |    1        |
+  *     | LM75_I2C_SCL_PIN/ SCL                 |   SCL     |    2        |
+  *     |                                       |   OS/INT  |    3        |
+  *     | .                                     |   GND     |    4  (0V)  |
+  *     | .                                     |   GND     |    5  (0V)  |
+  *     | .                                     |   GND     |    6  (0V)  |
+  *     | .                                     |   GND     |    7  (0V)  |
+  *     | .                                     |   VDD     |    8  (3.3V)|
+  *     +---------------------------------------+-----------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval_i2c_tsensor_cpal.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+#define LM75_SD_SET      0x01 /*!< Set SD bit in the configuration register */
+#define LM75_SD_RESET    0xFE /*!< Reset SD bit in the configuration register */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+  
+CPAL_TransferTypeDef  LM75_RXTransfer = { 
+                        /* Initialize TX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+
+CPAL_TransferTypeDef  LM75_TXTransfer = {
+                        /* Initialize RX Transfer structure */
+                        pNULL,
+                        0,
+                        0,
+                        0};
+
+uint8_t LM75_Buffer[2] = {0x00,0x00}; 
+
+extern CPAL_InitTypeDef LM75_DevStructure;
+
+
+__IO uint32_t  LM75_Timeout = LM75_TIMEOUT; 
+
+/* Private function prototypes -----------------------------------------------*/
+static void LM75_StructInit(void);
+static void LM75_Init(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Configure the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_Config(void)
+{
+  LM75_StructInit ();
+  LM75_Init();
+}
+
+/**
+  * @brief  Deinitialize the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_DeInit(void)
+{
+    /* Initialize CPAL peripheral */
+  CPAL_I2C_DeInit(&LM75_DevStructure);
+}
+
+/**
+  * @brief  Initializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+static void LM75_Init(void)
+{
+  /* Initialize CPAL peripheral */
+  CPAL_I2C_Init(&LM75_DevStructure);
+}
+
+/**
+  * @brief  Initializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+static void LM75_StructInit(void)
+{
+  /* Set CPAL structure parameters to their default values */  
+  CPAL_I2C_StructInit(&LM75_DevStructure);
+    
+  /* Set I2C clock speed */
+  LM75_DevStructure.pCPAL_I2C_Struct->I2C_Timing = LM75_I2C_TIMING;
+  			 
+#ifdef LM75_IT
+  /* Select Interrupt programming model */
+  LM75_DevStructure.CPAL_ProgModel = CPAL_PROGMODEL_INTERRUPT;
+#else
+  /* Select DMA programming model */
+  LM75_DevStructure.CPAL_ProgModel = CPAL_PROGMODEL_DMA;
+#endif /* LM75_IT */  
+  
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options  = 0;
+  
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferTx = &LM75_TXTransfer;
+  LM75_DevStructure.pCPAL_TransferRx = &LM75_RXTransfer;
+}
+
+static uint32_t LM75_Status (void)
+{
+  LM75_DevStructure.pCPAL_TransferTx = &LM75_TXTransfer;     
+  LM75_DevStructure.pCPAL_TransferTx->wAddr1 = (uint32_t)LM75_ADDR;
+  
+  return CPAL_I2C_IsDeviceReady(&LM75_DevStructure);
+}
+
+/**
+  * @brief  Checks the LM75 status.
+  * @param  None
+  * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS).
+  */
+ErrorStatus LM75_GetStatus(void)
+{  
+  /* Test if LM75 is ready */
+  while ((LM75_Status() == CPAL_FAIL) && LM75_Timeout)  
+  {
+    LM75_Timeout--;
+  }
+  
+  /* If LM75 is not responding return ERROR */
+  if (LM75_Timeout == 0)
+  {
+    return ERROR;
+  }
+  
+  /* In other case return SUCCESS */
+  return SUCCESS;  
+}
+/**
+  * @brief  Read the specified register from the LM75.
+  * @param  RegName: specifies the LM75 register to be read.
+  *              This member can be one of the following values:  
+  *                  - LM75_REG_TEMP: temperature register
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @retval LM75 register value.
+  */
+uint16_t LM75_ReadReg(uint8_t RegName)
+{   
+  uint16_t tmp = 0;
+  
+  LM75_Buffer[0] = 0;
+  LM75_Buffer[1] = 0;
+  
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferRx = &LM75_RXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferRx->wNumData = 2;
+  LM75_DevStructure.pCPAL_TransferRx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr2   = (uint32_t)RegName;
+  
+  /* Read Operation */
+  if(CPAL_I2C_Read(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+  }
+  
+  /* Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_Buffer[0] << 8);
+  tmp |= LM75_Buffer[1];
+  
+  /* return a Reg value */
+  return (uint16_t)tmp;  
+}
+
+/**
+  * @brief  Write to the specified register of the LM75.
+  * @param  RegName: specifies the LM75 register to be written.
+  *              This member can be one of the following values:    
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @param  RegValue: value to be written to LM75 register.  
+  * @retval None
+  */
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue)
+{   
+  LM75_Buffer[0] = (uint8_t)(RegValue >> 8);
+  LM75_Buffer[1] = (uint8_t)(RegValue);
+     
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+  
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferTx = &LM75_TXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferTx->wNumData = 2;
+  LM75_DevStructure.pCPAL_TransferTx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr2   = (uint32_t)RegName;
+  
+  /* Write Operation */
+  if(CPAL_I2C_Write(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+    
+    if (LM75_DevStructure.CPAL_State == CPAL_STATE_ERROR)
+    {
+      return LM75_FAIL;
+    }
+  }
+  else
+  {
+    return LM75_FAIL;
+  }
+  
+  return LM75_OK;
+}
+
+/**
+  * @brief  Read Temperature register of LM75: double temperature value.
+  * @param  None
+  * @retval LM75 measured temperature value.
+  */
+uint16_t LM75_ReadTemp(void)
+{   
+  uint16_t tmp = 0;
+  
+  LM75_Buffer[0] = 0;
+  LM75_Buffer[1] = 0;
+  
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferRx = &LM75_RXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferRx->wNumData = 2;
+  LM75_DevStructure.pCPAL_TransferRx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr2   = (uint32_t)LM75_REG_TEMP;
+  
+  /* Read Operation */
+  if(CPAL_I2C_Read(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+  }
+  
+  /* Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_Buffer[0] << 8);
+  tmp |= LM75_Buffer[1];    
+  
+  /* Return Temperature value */
+  return (uint16_t)(tmp >> 7);
+}
+
+/**
+  * @brief  Read the configuration register from the LM75.
+  * @param  None
+  * @retval LM75 configuration register value.
+  */
+uint8_t LM75_ReadConfReg(void)
+{    
+  LM75_Buffer[0] = 0;
+  
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+  
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferRx = &LM75_RXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferRx->wNumData = 1;
+  LM75_DevStructure.pCPAL_TransferRx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr2   = (uint32_t)LM75_REG_CONF;
+  
+  /* Read Operation */
+  if(CPAL_I2C_Read(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+  }
+  
+  /* Return Temperature value */
+  return (uint8_t)LM75_Buffer[0];
+}
+
+/**
+  * @brief  Write to the configuration register of the LM75.
+  * @param  RegValue: specifies the value to be written to LM75 configuration 
+  *         register.
+  * @retval None
+  */
+uint8_t LM75_WriteConfReg(uint8_t RegValue)
+{   
+  LM75_Buffer[0] = (uint8_t)(RegValue);
+    
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+  
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferTx = &LM75_TXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferTx->wNumData = 1;
+  LM75_DevStructure.pCPAL_TransferTx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr2   = (uint32_t)LM75_REG_CONF;
+  
+  /* Write Operation */
+  if(CPAL_I2C_Write(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+    
+    if (LM75_DevStructure.CPAL_State == CPAL_STATE_ERROR)
+    {
+      return LM75_FAIL;
+    }
+  }
+  else
+  {
+    return LM75_FAIL;
+  }
+  
+  return LM75_OK;
+  
+}
+
+/**
+  * @brief  Enables or disables the LM75.
+  * @param  NewState: specifies the LM75 new status. This parameter can be ENABLE
+  *         or DISABLE.  
+  * @retval None
+  */
+uint8_t LM75_ShutDown(FunctionalState NewState)
+{   
+  __IO uint8_t RegValue = 0;    
+  
+  LM75_Buffer[0] = 0;
+  		  
+  /* Disable all options */
+  LM75_DevStructure.wCPAL_Options = 0;
+
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferRx = &LM75_RXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferRx->wNumData = 1;
+  LM75_DevStructure.pCPAL_TransferRx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferRx->wAddr2   = (uint32_t)LM75_REG_CONF;
+  
+  /* Read Operation */
+  if(CPAL_I2C_Read(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+  }
+  
+  /* Get received data */
+  RegValue = (uint8_t)LM75_Buffer[0];
+  
+  /*---------------------------- Transmission Phase ---------------------------*/
+  
+  /* Enable or disable SD bit */
+  if (NewState != DISABLE)
+  {
+    /* Enable LM75 */
+    LM75_Buffer[0] = RegValue & LM75_SD_RESET;
+  }
+  else
+  {
+    /* Disable LM75 */
+    LM75_Buffer[0] = RegValue | LM75_SD_SET;
+  }  
+  
+  /* point to CPAL_TransferTypeDef structure */
+  LM75_DevStructure.pCPAL_TransferTx = &LM75_TXTransfer;
+  
+  /* Configure transfer parameters */  
+  LM75_DevStructure.pCPAL_TransferTx->wNumData = 1;
+  LM75_DevStructure.pCPAL_TransferTx->pbBuffer = LM75_Buffer ;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr1   = (uint32_t)LM75_ADDR;
+  LM75_DevStructure.pCPAL_TransferTx->wAddr2   = (uint32_t)LM75_REG_CONF;
+  
+  /* Write Operation */
+  if(CPAL_I2C_Write(&LM75_DevStructure) == CPAL_PASS)
+  {
+    while ((LM75_DevStructure.CPAL_State != CPAL_STATE_READY) && (LM75_DevStructure.CPAL_State != CPAL_STATE_ERROR) )
+    { }
+    
+    if (LM75_DevStructure.CPAL_State == CPAL_STATE_ERROR)
+    {
+      return LM75_FAIL;
+    }
+  }
+  else
+  {
+    return LM75_FAIL;
+  }
+  
+  return LM75_OK;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.h
new file mode 100644
index 0000000..dd868b4
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_i2c_tsensor_cpal.h
@@ -0,0 +1,129 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_i2c_tsensor_cpal.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32373c_eval_i2c_tsensor_cpal.c firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_I2C_TSENSOR_CPAL_H
+#define __STM32373C_EVAL_I2C_TSENSOR_CPAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+   
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f37x_i2c_cpal.h"
+   
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  LM75_OK = 0,
+  LM75_FAIL
+}LM75_Status_TypDef;
+
+/* Exported constants --------------------------------------------------------*/
+    
+/*====================== CPAL Structure configuration ========================*/ 
+/* Select I2C device (uncomment relative define) */
+
+//#define LM75_DevStructure                I2C1_DevStructure   
+#define LM75_DevStructure                I2C2_DevStructure  
+
+   
+/*============== TIMING Configuration ==========================*/
+/* I2C TIMING Register define when I2C clock source is SYSCLK */
+/* I2C TIMING is calculated in case of the I2C Clock source is the SYSCLK = 72 MHz */
+/* set TIMING to 0xC062121F to reach 100 KHz speed (Rise time = 640ns, Fall time = 20ns) */
+
+#define LM75_I2C_TIMING              0xC062121F
+
+
+/*=================== Programming model Configuration ========================*/
+/* Select interrupt programming model : By default DMA programming model is selected.
+ To select interrupt programming model uncomment this define */
+//#define LM75_IT
+
+
+/* Maximum Timeout values for waiting until device is ready for communication.*/
+   
+#define LM75_TIMEOUT        ((uint32_t)0x3FFFF)
+
+/**
+  * @brief  Internal register Memory
+  */
+#define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
+#define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
+#define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
+#define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
+#define LM75_ADDR           0x90   /*!< LM75 address */
+   
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+void LM75_DeInit(void);
+void LM75_Config(void);
+ErrorStatus LM75_GetStatus(void);
+uint16_t LM75_ReadTemp(void);
+uint16_t LM75_ReadReg(uint8_t RegName);
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t LM75_ReadConfReg(void);
+uint8_t LM75_WriteConfReg(uint8_t RegValue);
+uint8_t LM75_ShutDown(FunctionalState NewState);
+
+
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32373C_EVAL_I2C_TSENSOR_CPAL_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.c
new file mode 100644
index 0000000..33e9f74
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.c
@@ -0,0 +1,908 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_spi_sd.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file provides a set of functions needed to manage the SPI SD 
+  *          Card memory mounted on STM32373C-EVAL board.
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32F37x hardware resources (SPI and 
+  *          GPIO) are defined in stm32373c_eval.h file, and the initialization is 
+  *          performed in SD_LowLevel_Init() function declared in stm32373c_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SD_LowLevel_Init() function.
+  *            
+  *          +-------------------------------------------------------+
+  *          |                     Pin assignment                    |
+  *          +-------------------------+---------------+-------------+
+  *          |  STM32F0xx SPI Pins     |     SD        |    Pin      |
+  *          +-------------------------+---------------+-------------+
+  *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |
+  *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |
+  *          |                         |   GND         |    3 (0 V)  |
+  *          |                         |   VDD         |    4 (3.3 V)|
+  *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |
+  *          |                         |   GND         |    6 (0 V)  |
+  *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |
+  *          +-------------------------+---------------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval_spi_sd.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL_SPI_SD
+  * @brief      This file includes the SD card driver of STM32373C-EVAL boards.
+  * @{
+  */ 
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Variables
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Function_Prototypes
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the SD/SD communication.
+  * @param  None
+  * @retval None
+  */
+void SD_DeInit(void)
+{
+  SD_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the SD/SD communication.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_Init(void)
+{
+  uint32_t i = 0;
+
+  /*!< Initialize SD_SPI */
+  SD_LowLevel_Init(); 
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF, 10 times with CS high */
+  /*!< Rise CS and MOSI for 80 clocks cycles */
+  for (i = 0; i <= 9; i++)
+  {
+    /*!< Send dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+  }
+  
+  /*------------Put SD in SPI mode--------------*/
+  /*!< SD initialized and set to SPI mode properly */
+  return (SD_GoIdleState());
+}
+
+/**
+ * @brief  Detect if SD card is correctly plugged in the memory slot.
+ * @param  None
+ * @retval Return if SD is detected or not
+ */
+uint8_t SD_Detect(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  /*!< Check GPIO to detect SD */
+  if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN)
+  {
+    status = SD_NOT_PRESENT;
+  }
+  return status;
+}
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD 
+  *         card information.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
+{
+  SD_Error status = SD_RESPONSE_FAILURE;
+
+  SD_GetCSDRegister(&(cardinfo->SD_csd));
+  status = SD_GetCIDRegister(&(cardinfo->SD_cid));
+  cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
+  cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
+  cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
+  cardinfo->CardCapacity *= cardinfo->CardBlockSize;
+
+  /*!< Returns the reponse */
+  return status;
+}
+
+/**
+  * @brief  Reads a block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+  SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Save the received data */
+        *pBuffer = SD_ReadByte();
+       
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Reads multiple block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be read.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+    SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return  SD_RESPONSE_FAILURE;
+    }
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Read the pointed data */
+        *pBuffer = SD_ReadByte();
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Set next read address*/
+      Offset += 512;
+      /*!< get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes a block on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */
+  SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Send a dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(0xFE);
+
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes many blocks on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be written.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */
+    SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return SD_RESPONSE_FAILURE;
+    }
+    /*!< Send dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE);
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Set next write address */
+    Offset += 512;
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CSD card register.
+  *         Reading the contents of the CSD register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_csd: pointer on an SCD register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CSD_Tab[16];
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Send CMD9 (CSD register) or CMD10(CSD register) */
+  SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF);
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      for (i = 0; i < 16; i++)
+      {
+        /*!< Store CSD register value on CSD_Tab */
+        CSD_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
+  SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
+  SD_csd->Reserved1 = CSD_Tab[0] & 0x03;
+
+  /*!< Byte 1 */
+  SD_csd->TAAC = CSD_Tab[1];
+
+  /*!< Byte 2 */
+  SD_csd->NSAC = CSD_Tab[2];
+
+  /*!< Byte 3 */
+  SD_csd->MaxBusClkFrec = CSD_Tab[3];
+
+  /*!< Byte 4 */
+  SD_csd->CardComdClasses = CSD_Tab[4] << 4;
+
+  /*!< Byte 5 */
+  SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
+  SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
+
+  /*!< Byte 6 */
+  SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
+  SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
+  SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
+  SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
+  SD_csd->Reserved2 = 0; /*!< Reserved */
+
+  SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
+
+  /*!< Byte 7 */
+  SD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
+
+  /*!< Byte 8 */
+  SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
+
+  SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
+  SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
+
+  /*!< Byte 9 */
+  SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
+  SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
+  SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
+  /*!< Byte 10 */
+  SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
+    
+  SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6;
+  SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1;
+
+  /*!< Byte 11 */
+  SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7;
+  SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F);
+
+  /*!< Byte 12 */
+  SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
+  SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
+  SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
+  SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
+
+  /*!< Byte 13 */
+  SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6;
+  SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
+  SD_csd->Reserved3 = 0;
+  SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
+
+  /*!< Byte 14 */
+  SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
+  SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
+  SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
+  SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
+  SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
+  SD_csd->ECC = (CSD_Tab[14] & 0x03);
+
+  /*!< Byte 15 */
+  SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1;
+  SD_csd->Reserved4 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CID card register.
+  *         Reading the contents of the CID register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_cid: pointer on an CID register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CID_Tab[16];
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD10 (CID register) */
+  SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF);
+  
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Store CID register value on CID_Tab */
+      for (i = 0; i < 16; i++)
+      {
+        CID_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_cid->ManufacturerID = CID_Tab[0];
+
+  /*!< Byte 1 */
+  SD_cid->OEM_AppliID = CID_Tab[1] << 8;
+
+  /*!< Byte 2 */
+  SD_cid->OEM_AppliID |= CID_Tab[2];
+
+  /*!< Byte 3 */
+  SD_cid->ProdName1 = CID_Tab[3] << 24;
+
+  /*!< Byte 4 */
+  SD_cid->ProdName1 |= CID_Tab[4] << 16;
+
+  /*!< Byte 5 */
+  SD_cid->ProdName1 |= CID_Tab[5] << 8;
+
+  /*!< Byte 6 */
+  SD_cid->ProdName1 |= CID_Tab[6];
+
+  /*!< Byte 7 */
+  SD_cid->ProdName2 = CID_Tab[7];
+
+  /*!< Byte 8 */
+  SD_cid->ProdRev = CID_Tab[8];
+
+  /*!< Byte 9 */
+  SD_cid->ProdSN = CID_Tab[9] << 24;
+
+  /*!< Byte 10 */
+  SD_cid->ProdSN |= CID_Tab[10] << 16;
+
+  /*!< Byte 11 */
+  SD_cid->ProdSN |= CID_Tab[11] << 8;
+
+  /*!< Byte 12 */
+  SD_cid->ProdSN |= CID_Tab[12];
+
+  /*!< Byte 13 */
+  SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
+  SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
+
+  /*!< Byte 14 */
+  SD_cid->ManufactDate |= CID_Tab[14];
+
+  /*!< Byte 15 */
+  SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;
+  SD_cid->Reserved2 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Send 5 bytes command to the SD card.
+  * @param  Cmd: The user expected command to send to SD card.
+  * @param  Arg: The command argument.
+  * @param  Crc: The CRC.
+  * @retval None
+  */
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
+{
+  uint32_t i = 0x00;
+  
+  uint8_t Frame[6];
+  
+  Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
+  
+  Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
+  
+  Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
+  
+  Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
+  
+  Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
+  
+  Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
+  
+  for (i = 0; i < 6; i++)
+  {
+    SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
+  }
+}
+
+/**
+  * @brief  Get SD card data response.
+  * @param  None
+  * @retval The SD status: Read data response xxx0<status>1
+  *         - status 010: Data accecpted
+  *         - status 101: Data rejected due to a crc error
+  *         - status 110: Data rejected due to a Write error.
+  *         - status 111: Data rejected due to other error.
+  */
+uint8_t SD_GetDataResponse(void)
+{
+  uint32_t i = 0;
+  uint8_t response, rvalue;
+
+  while (i <= 64)
+  {
+    /*!< Read resonse */
+    response = SD_ReadByte();
+    /*!< Mask unused bits */
+    response &= 0x1F;
+    switch (response)
+    {
+      case SD_DATA_OK:
+      {
+        rvalue = SD_DATA_OK;
+        break;
+      }
+      case SD_DATA_CRC_ERROR:
+        return SD_DATA_CRC_ERROR;
+      case SD_DATA_WRITE_ERROR:
+        return SD_DATA_WRITE_ERROR;
+      default:
+      {
+        rvalue = SD_DATA_OTHER_ERROR;
+        break;
+      }
+    }
+    /*!< Exit loop in case of data ok */
+    if (rvalue == SD_DATA_OK)
+      break;
+    /*!< Increment loop counter */
+    i++;
+  }
+
+  /*!< Wait null data */
+  while (SD_ReadByte() == 0);
+
+  /*!< Return response */
+  return response;
+}
+
+/**
+  * @brief  Returns the SD response.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetResponse(uint8_t Response)
+{
+  uint32_t Count = 0xFFF;
+
+  /* Check if response is got or a timeout is happen */
+  while ((SD_ReadByte() != Response) && Count)
+  {
+    Count--;
+  }
+
+  if (Count == 0)
+  {
+    /* After time out */
+    return SD_RESPONSE_FAILURE;
+  }
+  else
+  {
+    /* Right response got */
+    return SD_RESPONSE_NO_ERROR;
+  }
+}
+
+/**
+  * @brief  Returns the SD status.
+  * @param  None
+  * @retval The SD status.
+  */
+uint16_t SD_GetStatus(void)
+{
+  uint16_t Status = 0;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */
+  SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF);
+
+  Status = SD_ReadByte();
+  Status |= (uint16_t)(SD_ReadByte() << 8);
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  return Status;
+}
+
+/**
+  * @brief  Put SD in Idle state.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GoIdleState(void)
+{
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
+  SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
+  
+  /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
+  if (SD_GetResponse(SD_IN_IDLE_STATE))
+  {
+    /*!< No Idle State Response: return response failue */
+    return SD_RESPONSE_FAILURE;
+  }
+  /*----------Activates the card initialization process-----------*/
+  do
+  {
+    /*!< SD chip select high */
+    SD_CS_HIGH();
+    
+    /*!< Send Dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    
+    /*!< SD chip select low */
+    SD_CS_LOW();
+    
+    /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
+    SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
+    /*!< Wait for no error Response (R1 Format) equal to 0x00 */
+  }
+  while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
+  
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  return SD_RESPONSE_NO_ERROR;
+}
+
+/**
+  * @brief  Write a byte on the SD.
+  * @param  Data: byte to send.
+  * @retval None
+  */
+uint8_t SD_WriteByte(uint8_t Data)
+{
+  /*!< Wait until the transmit buffer is empty */
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  
+  /*!< Send the byte */
+  SPI_SendData8(SD_SPI, Data);
+  
+  /*!< Wait to receive a byte*/
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  
+  /*!< Return the byte read from the SPI bus */ 
+  return SPI_ReceiveData8(SD_SPI);
+}
+
+/**
+  * @brief  Read a byte from the SD.
+  * @param  None
+  * @retval The received byte.
+  */
+uint8_t SD_ReadByte(void)
+{
+  uint8_t Data = 0;
+  
+  /*!< Wait until the transmit buffer is empty */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  /*!< Send the byte */
+  SPI_SendData8(SD_SPI, SD_DUMMY_BYTE);
+
+  /*!< Wait until a data is received */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  /*!< Get the received data */
+  Data = SPI_ReceiveData8(SD_SPI);
+
+  /*!< Return the shifted data */
+  return Data;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.h
new file mode 100644
index 0000000..7282545
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32373C_EVAL/stm32373c_eval_spi_sd.h
@@ -0,0 +1,286 @@
+/**
+  ******************************************************************************
+  * @file    stm32373c_eval_spi_sd.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    20-September-2012
+  * @brief   This file contains all the functions prototypes for the stm32373c_eval_spi_sd
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32373C_EVAL_SPI_SD_H
+#define __STM32373C_EVAL_SPI_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32373c_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32373C_EVAL_SPI_SD
+  * @{
+  */  
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Exported_Types
+  * @{
+  */ 
+
+typedef enum
+{
+/**
+  * @brief  SD reponses and error flags
+  */
+  SD_RESPONSE_NO_ERROR      = (0x00),
+  SD_IN_IDLE_STATE          = (0x01),
+  SD_ERASE_RESET            = (0x02),
+  SD_ILLEGAL_COMMAND        = (0x04),
+  SD_COM_CRC_ERROR          = (0x08),
+  SD_ERASE_SEQUENCE_ERROR   = (0x10),
+  SD_ADDRESS_ERROR          = (0x20),
+  SD_PARAMETER_ERROR        = (0x40),
+  SD_RESPONSE_FAILURE       = (0xFF),
+
+/**
+  * @brief  Data response error
+  */
+  SD_DATA_OK                = (0x05),
+  SD_DATA_CRC_ERROR         = (0x0B),
+  SD_DATA_WRITE_ERROR       = (0x0D),
+  SD_DATA_OTHER_ERROR       = (0xFF)
+} SD_Error;
+
+/** 
+  * @brief  Card Specific Data: CSD Register
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32373C_EVAL_SPI_SD_Exported_Constants
+  * @{
+  */ 
+    
+/**
+  * @brief  Block Size
+  */
+#define SD_BLOCK_SIZE    0x200
+
+/**
+  * @brief  Dummy byte
+  */
+#define SD_DUMMY_BYTE   0xFF
+
+/**
+  * @brief  Start Data tokens:
+  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is 
+  *         on the data/command line)  
+  */
+#define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
+#define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
+#define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
+#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
+#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT        ((uint8_t)0x01)
+#define SD_NOT_PRESENT    ((uint8_t)0x00)
+
+
+/**
+  * @brief  Commands: CMDxx = CMD-number | 0x40
+  */
+#define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
+#define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
+#define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
+#define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
+#define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
+#define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
+#define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
+#define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
+#define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
+#define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
+#define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
+#define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
+#define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
+#define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
+#define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
+#define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
+#define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
+#define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
+#define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
+#define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
+#define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
+#define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
+#define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32373C_EVAL_SPI_SD_Exported_Macros
+  * @{
+  */
+/** 
+  * @brief  Select SD Card: ChipSelect pin low   
+  */  
+#define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/** 
+  * @brief  Deselect SD Card: ChipSelect pin high   
+  */ 
+#define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32373C_EVAL_SPI_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);  
+SD_Error SD_Init(void);
+uint8_t SD_Detect(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
+
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
+SD_Error SD_GetResponse(uint8_t Response);
+uint8_t SD_GetDataResponse(void);
+SD_Error SD_GoIdleState(void);
+uint16_t SD_GetStatus(void);
+
+uint8_t SD_WriteByte(uint8_t byte);
+uint8_t SD_ReadByte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32373C_EVAL_SPI_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c
new file mode 100644
index 0000000..540c87e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.c
@@ -0,0 +1,882 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file provides
+  *            - set of firmware functions to manage Leds, push-button and COM ports
+  *            - low level initialization functions for SD card (on SDIO), SPI serial
+  *              flash (sFLASH) and temperature sensor (LM75)
+  *          available on STM32L152D-EVAL evaluation board from STMicroelectronics.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_i2c.h"
+#include "stm32l1xx_sdio.h"
+#include "stm32l1xx_dma.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL 
+  * @brief This file provides firmware functions to manage Leds, push-buttons, 
+  *        COM ports, SD card on SDIO, serial flash (sFLASH), serial EEPROM (sEE) 
+  *        and temperature sensor (LM75) available on STM32L152D-EVAL evaluation 
+  *        board from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
+                                 LED4_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+                                 LED4_GPIO_CLK};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
+
+const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
+                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
+                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
+
+const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
+
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE,
+                                            RIGHT_BUTTON_EXTI_LINE,
+                                            LEFT_BUTTON_EXTI_LINE,
+                                            UP_BUTTON_EXTI_LINE,
+                                            DOWN_BUTTON_EXTI_LINE,
+                                            SEL_BUTTON_EXTI_LINE};
+
+const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE,
+                                             RIGHT_BUTTON_EXTI_PORT_SOURCE,
+                                             LEFT_BUTTON_EXTI_PORT_SOURCE,
+                                             UP_BUTTON_EXTI_PORT_SOURCE,
+                                             DOWN_BUTTON_EXTI_PORT_SOURCE,
+                                             SEL_BUTTON_EXTI_PORT_SOURCE};
+								 
+const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE,
+                                            RIGHT_BUTTON_EXTI_PIN_SOURCE,
+                                            LEFT_BUTTON_EXTI_PIN_SOURCE,
+                                            UP_BUTTON_EXTI_PIN_SOURCE,
+                                            DOWN_BUTTON_EXTI_PIN_SOURCE,
+                                            SEL_BUTTON_EXTI_PIN_SOURCE}; 
+
+const uint8_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
+                                      LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
+                                      DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
+
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1}; 
+
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT};
+ 
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT};
+
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
+
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK};
+ 
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK};
+
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN};
+
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN};
+ 
+const uint8_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE};
+
+const uint8_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE};
+ 
+const uint8_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF};
+ 
+const uint8_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF};
+
+DMA_InitTypeDef   sEEDMA_InitStructure; 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4
+  * @retval None
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Enable the GPIO_LED Clock */
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button
+  * @param  Button_Mode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                     generation capability  
+  * @retval None
+  */
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* There is no Wakeup and Tamper buttons on STM32L152D-EVAL. */
+    
+  /* Enable the BUTTON Clock */
+  RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+  /* Configure Button pin as input */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+
+  if (Button_Mode == BUTTON_MODE_EXTI)
+  {
+    /* Connect Button EXTI Line to Button GPIO Pin */
+    SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+
+    /* Configure Button EXTI line */
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    
+    if(Button != BUTTON_KEY) 
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+    }
+    else
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
+    }
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+    EXTI_Init(&EXTI_InitStructure);
+
+    /* Enable and set Button EXTI Interrupt to the lowest priority */
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+    NVIC_Init(&NVIC_InitStructure); 
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter can be one of following parameters:    
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    
+  * @retval The Button GPIO pin value.
+  */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+  /* There is no Wakeup and Tamper pins on STM32L152D-EVAL. */
+  
+  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+/**
+  * @brief  Configures COM port.
+  * @param  COM: Specifies the COM port to be configured.
+  *   This parameter can be one of following parameters:    
+  *     @arg COM1
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
+  *   contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
+
+  /* Enable USART1 clock */
+  RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE); 
+
+  /* Connect PXx to USARTx_Tx */
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
+
+  /* Connect PXx to USARTx_Rx */
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
+  
+  /* Configure USART Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
+    
+  /* Configure USART Rx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
+
+  /* USART configuration */
+  USART_Init(COM_USART[COM], USART_InitStruct);
+    
+  /* Enable USART */
+  USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+  * @brief  DeInitializes the SDIO interface.
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /*!< Disable SDIO Clock */
+  SDIO_ClockCmd(DISABLE);
+  
+  /*!< Set Power State to OFF */
+  SDIO_SetPowerState(SDIO_PowerState_OFF);
+
+  /*!< DeInitializes the SDIO peripheral */
+  SDIO_DeInit();
+  
+  /* Disable the SDIO APB2 Clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, DISABLE);
+
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_MCO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_MCO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_MCO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_MCO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_MCO);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_MCO);
+
+  /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /* Configure PD.02 CMD line */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /* Configure PC.12 pin: CLK pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /* GPIOC and GPIOD Periph clock enable */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_GPIOD | SD_DETECT_GPIO_CLK, ENABLE);
+
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_SDIO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_SDIO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SDIO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SDIO);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SDIO);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_SDIO);
+
+  /* Configure PC.08, PC.09, PC.10, PC.11 pins: D0, D1, D2, D3 pins */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /* Configure PD.02 CMD line */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /* Configure PC.12 pin: CLK pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+  
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Enable the SDIO APB2 Clock */
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE);
+
+  /* Enable the DMA2 Clock */
+  RCC_AHBPeriphClockCmd(SD_SDIO_DMA_CLK, ENABLE);
+}
+
+/**
+  * @brief  Configures the DMA2 Channel4 for SDIO Tx request.
+  * @param  BufferSRC: pointer to the source buffer
+  * @param  BufferSize: buffer size
+  * @retval None
+  */
+void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+
+  DMA_ClearFlag(SD_SDIO_DMA_FLAG_TC | SD_SDIO_DMA_FLAG_TE | SD_SDIO_DMA_FLAG_HT | SD_SDIO_DMA_FLAG_GL);
+
+  /*!< SDIO DMA CHANNEL disable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, DISABLE);
+
+  /*!< SDIO DMA CHANNEL Config */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferSRC;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(SD_SDIO_DMA_CHANNEL, &DMA_InitStructure);
+  DMA_ITConfig(SD_SDIO_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+  /*!< SDIO DMA CHANNEL enable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, ENABLE);  
+}
+
+/**
+  * @brief  Configures the DMA2 Channel4 for SDIO Rx request.
+  * @param  BufferDST: pointer to the destination buffer
+  * @param  BufferSize: buffer size
+  * @retval None
+  */
+void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+
+  DMA_ClearFlag(SD_SDIO_DMA_FLAG_TC | SD_SDIO_DMA_FLAG_TE | SD_SDIO_DMA_FLAG_HT | SD_SDIO_DMA_FLAG_GL);
+
+  /*!< SDIO DMA CHANNEL disable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, DISABLE);
+
+  /*!< SDIO DMA CHANNEL Config */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SDIO_FIFO_ADDRESS;
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)BufferDST;
+  DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+  DMA_InitStructure.DMA_BufferSize = BufferSize / 4;
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(SD_SDIO_DMA_CHANNEL, &DMA_InitStructure);
+  DMA_ITConfig(SD_SDIO_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+  /*!< SDIO DMA CHANNEL enable */
+  DMA_Cmd(SD_SDIO_DMA_CHANNEL, ENABLE); 
+}
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< Disable LM75_I2C */
+  I2C_Cmd(LM75_I2C, DISABLE);
+  
+  /*!< DeInitializes the LM75_I2C */
+  I2C_DeInit(LM75_I2C);
+  
+  /*!< LM75_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
+    
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the LM75_I2C..
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< LM75_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
+    
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
+                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
+   
+  /* Connect PXx to I2C_SCL */
+  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
+
+  /* Connect PXx to I2C_SDA */
+  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); 
+
+  /* Connect PXx to I2C_SMBUSALER */
+  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF); 
+  
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  DeInitializes the SPI interface.
+  * @param  None
+  * @retval None
+  */
+void sEE_SPI_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  SPI_Cmd(sEE_SPI, DISABLE); /*!< sEE_SPI disable */
+  SPI_I2S_DeInit(sEE_SPI);   /*!< DeInitializes the sEE_SPI */
+  
+  /*!< sEE_SPI Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_SPI_CLK, DISABLE); 
+
+  /*!< Configure sEE_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MISO_PIN;
+  GPIO_Init(sEE_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MOSI_PIN;
+  GPIO_Init(sEE_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_CS_PIN pin: sEE Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_CS_PIN;
+  GPIO_Init(sEE_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SPI interface for EEPROM
+  * @param  None
+  * @retval None
+  */
+void sEE_SPI_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  SPI_InitTypeDef   SPI_InitStructure;
+
+  /*!< sEE_CS_GPIO, sEE_MOSI_GPIO, sEE_MISO_GPIO and sEE_SCK_GPIO 
+       Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_SPI_CS_GPIO_CLK | sEE_SPI_MOSI_GPIO_CLK | sEE_SPI_MISO_GPIO_CLK |
+                        sEE_SPI_SCK_GPIO_CLK , ENABLE);
+
+  /*!< sEE Periph clock enable */
+  RCC_APB2PeriphClockCmd(sEE_SPI_CLK, ENABLE); 
+
+  /*!< Configure sEE pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(sEE_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MISO_PIN;
+  GPIO_Init(sEE_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_MOSI_PIN;
+  GPIO_Init(sEE_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_SPI_CS_PIN pin: sEE_SPI Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = sEE_SPI_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_Init(sEE_SPI_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PXx to sEE_SPI_SCK */
+  GPIO_PinAFConfig(sEE_SPI_SCK_GPIO_PORT, sEE_SPI_SCK_SOURCE, sEE_SPI_SCK_AF);
+
+  /* Connect PXx to sEE_SPI_MISO */
+  GPIO_PinAFConfig(sEE_SPI_MISO_GPIO_PORT, sEE_SPI_MISO_SOURCE, sEE_SPI_MISO_AF); 
+
+  /* Connect PXx to sEE_SPI_MOSI */
+  GPIO_PinAFConfig(sEE_SPI_MOSI_GPIO_PORT, sEE_SPI_MOSI_SOURCE, sEE_SPI_MOSI_AF);  
+  
+  /*!< sEE SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(sEE_SPI, &SPI_InitStructure);
+
+  SPI_Cmd(sEE_SPI, ENABLE); /*!< sEE_SPI enable */
+}
+
+/**
+  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure; 
+  NVIC_InitTypeDef NVIC_InitStructure;    
+   
+  /* sEE_I2C Peripheral Disable */
+  I2C_Cmd(sEE_I2C, DISABLE);
+ 
+  /* sEE_I2C DeInit */
+  I2C_DeInit(sEE_I2C);
+
+  /*!< sEE_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
+    
+  /*!< GPIO configuration */  
+  /*!< Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Configure and enable I2C DMA TX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Configure and enable I2C DMA RX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_Init(&NVIC_InitStructure);   
+  
+  /* Disable and Deinitialize the DMA channels */
+  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
+  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
+}
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;  
+  
+  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
+  
+  /*!< sEE_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
+  
+  /* Connect PXx to I2C_SCL*/
+  GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
+  
+  /* Connect PXx to I2C_SDA*/
+  GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);
+  
+  /*!< GPIO configuration */  
+  /*!< Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+  
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure); 
+  
+  /* Configure and enable I2C DMA TX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+  
+  /* Configure and enable I2C DMA RX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_Init(&NVIC_InitStructure);  
+  
+  /*!< I2C DMA TX and RX channels configuration */
+  /* Enable the DMA clock */
+  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
+  
+  /* I2C TX DMA Channel configuration */
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
+  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
+  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
+  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
+  
+  /* I2C RX DMA Channel configuration */
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
+  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
+  
+  /* Enable the DMA Channels Interrupts */
+  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
+  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
+}
+
+
+/**
+  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
+{ 
+  /* Initialize the DMA with the new parameters */
+  if (Direction == sEE_DIRECTION_TX)
+  {
+    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
+    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
+    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
+    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
+    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
+  }
+  else
+  { 
+    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
+    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
+    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
+    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.h
new file mode 100644
index 0000000..f7e40bd
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval.h
@@ -0,0 +1,465 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file contains definitions for STM32L152D_EVAL's Leds, push-buttons
+  *          COM ports and Temperature Sensor LM75 (on I2C) hardware resources.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152D_EVAL_H
+#define __STM32L152D_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+#include "stm32_eval_legacy.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */  
+  
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL
+  * @{
+  */ 
+  
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{
+  BUTTON_KEY = 0,
+  BUTTON_RIGHT = 1,
+  BUTTON_LEFT = 2,
+  BUTTON_UP = 3,
+  BUTTON_DOWN = 4,
+  BUTTON_SEL = 5
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;   
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief  Define for STM32L152D_EVAL board  
+  */ 
+#if !defined (USE_STM32L152D_EVAL)
+ #define USE_STM32L152D_EVAL
+#endif
+  
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_3
+#define LED1_GPIO_PORT                   GPIOD
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED2_PIN                         GPIO_Pin_7
+#define LED2_GPIO_PORT                   GPIOD
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+
+#define LED3_PIN                         GPIO_Pin_14  
+#define LED3_GPIO_PORT                   GPIOG
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOG  
+
+#define LED4_PIN                         GPIO_Pin_15
+#define LED4_GPIO_PORT                   GPIOG
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOG
+
+/**
+  * @}
+  */
+  
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          6 
+/* On STM32L152D-EVAL board, the KEY button is connected to PA.00 and it can
+   be use as Wakeup pin button. */
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_0
+#define KEY_BUTTON_GPIO_PORT             GPIOA
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOA
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line0
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOA
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource0
+#define KEY_BUTTON_EXTI_IRQn             EXTI0_IRQn
+
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_7
+#define RIGHT_BUTTON_GPIO_PORT           GPIOG
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOG
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line7
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOG
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource7
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI9_5_IRQn
+
+/**
+ * @brief Joystick Left push-button
+ */    
+#define LEFT_BUTTON_PIN                  GPIO_Pin_6
+#define LEFT_BUTTON_GPIO_PORT            GPIOG
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOG
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line6
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOG
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource6
+#define LEFT_BUTTON_EXTI_IRQn            EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_11
+#define UP_BUTTON_GPIO_PORT              GPIOG
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOG
+#define UP_BUTTON_EXTI_LINE              EXTI_Line11
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOG
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource11
+#define UP_BUTTON_EXTI_IRQn              EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Down push-button
+ */   
+#define DOWN_BUTTON_PIN                  GPIO_Pin_8
+#define DOWN_BUTTON_GPIO_PORT            GPIOG
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOG
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line8
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOG
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource8
+#define DOWN_BUTTON_EXTI_IRQn            EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Sel push-button
+ */  
+#define SEL_BUTTON_PIN                   GPIO_Pin_13
+#define SEL_BUTTON_GPIO_PORT             GPIOG
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOG
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line13
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOG
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource13
+#define SEL_BUTTON_EXTI_IRQn             EXTI15_10_IRQn          
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             1
+
+/**
+ * @brief Definition for COM port1, connected to USART1
+ */ 
+#define EVAL_COM1                        USART1
+#define EVAL_COM1_CLK                    RCC_APB2Periph_USART1
+
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_9
+#define EVAL_COM1_TX_GPIO_PORT           GPIOA
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOA
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource9
+#define EVAL_COM1_TX_AF                  GPIO_AF_USART1
+
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_10
+#define EVAL_COM1_RX_GPIO_PORT           GPIOA
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOA
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource10
+#define EVAL_COM1_RX_AF                  GPIO_AF_USART1
+
+#define EVAL_COM1_IRQn                   USART1_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_SD_FLASH
+  * @{
+  */
+/**
+  * @brief  SD FLASH SDIO Interface
+  */ 
+#define SD_DETECT_PIN                    GPIO_Pin_7                  /* PC.07 */
+#define SD_DETECT_EXTI_LINE              EXTI_Line7
+#define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource7
+
+#define SD_DETECT_GPIO_PORT              GPIOC                       /* GPIOC */
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOC
+#define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOC
+#define SD_DETECT_EXTI_IRQn              EXTI9_5_IRQn
+
+
+#define SDIO_FIFO_ADDRESS                ((uint32_t)0x40012C80)
+/** 
+  * @brief  SDIO Intialization Frequency (400KHz max)
+  */
+#define SDIO_INIT_CLK_DIV                ((uint8_t)0x76)
+/** 
+  * @brief  SDIO Data Transfer Frequency (24MHz max) 
+  */
+#define SDIO_TRANSFER_CLK_DIV            ((uint8_t)0x1)
+
+
+#define SD_SDIO_DMA                      DMA2
+#define SD_SDIO_DMA_CLK                  RCC_AHBPeriph_DMA2
+#define SD_SDIO_DMA_CHANNEL              DMA2_Channel4
+#define SD_SDIO_DMA_FLAG_TC              DMA2_FLAG_TC4
+#define SD_SDIO_DMA_FLAG_TE              DMA2_FLAG_TE4
+#define SD_SDIO_DMA_FLAG_HT              DMA2_FLAG_HT4
+#define SD_SDIO_DMA_FLAG_GL              DMA2_FLAG_GL4
+#define SD_SDIO_DMA_IRQn                 DMA2_Channel4_IRQn
+#define SD_SDIO_DMA_IRQHANDLER           DMA2_Channel4_IRQHandler
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  LM75 Temperature Sensor I2C Interface pins
+  */  
+#define LM75_I2C                         I2C1
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_8                  /* PB.08 */
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource8
+#define LM75_I2C_SCL_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_9                  /* PB.09 */
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource9
+#define LM75_I2C_SDA_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1
+#define LM75_I2C_DR                      ((uint32_t)0x40005410)
+
+#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
+#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
+#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
+#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
+/**
+  * @}
+  */
+  
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_SPI_EE
+  * @{
+  */
+/**
+  * @brief  sEE SPI Interface pins
+  */
+#define sEE_SPI                          SPI1
+#define sEE_SPI_CLK                      RCC_APB2Periph_SPI1
+   
+#define sEE_SPI_SCK_PIN                  GPIO_Pin_5                  /* PA.05 */
+#define sEE_SPI_SCK_GPIO_PORT            GPIOA                       /* GPIOA */
+#define sEE_SPI_SCK_GPIO_CLK             RCC_AHBPeriph_GPIOA
+#define sEE_SPI_SCK_SOURCE               GPIO_PinSource5
+#define sEE_SPI_SCK_AF                   GPIO_AF_SPI1
+
+#define sEE_SPI_MISO_PIN                 GPIO_Pin_14                 /* PE.14 */
+#define sEE_SPI_MISO_GPIO_PORT           GPIOE                       /* GPIOE */
+#define sEE_SPI_MISO_GPIO_CLK            RCC_AHBPeriph_GPIOE
+#define sEE_SPI_MISO_SOURCE              GPIO_PinSource14
+#define sEE_SPI_MISO_AF                  GPIO_AF_SPI1
+
+#define sEE_SPI_MOSI_PIN                 GPIO_Pin_15                 /* PE.15 */
+#define sEE_SPI_MOSI_GPIO_PORT           GPIOE                       /* GPIOE */
+#define sEE_SPI_MOSI_GPIO_CLK            RCC_AHBPeriph_GPIOE
+#define sEE_SPI_MOSI_SOURCE              GPIO_PinSource15
+#define sEE_SPI_MOSI_AF                  GPIO_AF_SPI1
+
+#define sEE_SPI_CS_PIN                   GPIO_Pin_5                  /* PC.05 */
+#define sEE_SPI_CS_GPIO_PORT             GPIOC                       /* GPIOC */
+#define sEE_SPI_CS_GPIO_CLK              RCC_AHBPeriph_GPIOC   
+
+/**
+  * @brief  sEE SPI Interface Type
+  */
+#define sEE_M95040   
+   
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L152D_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+#define sEE_I2C                          I2C1
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
+   
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_8                  /* PB.08 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SCL_SOURCE               GPIO_PinSource8
+#define sEE_I2C_SCL_AF                   GPIO_AF_I2C1
+
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_9                  /* PB.09 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SDA_SOURCE               GPIO_PinSource9
+#define sEE_I2C_SDA_AF                   GPIO_AF_I2C1
+
+#define sEE_M24LR64
+
+#define sEE_I2C_DMA                      DMA1   
+#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
+#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
+#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
+#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
+#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
+#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
+#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
+#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
+#define sEE_USE_DMA
+   
+#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
+#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
+#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
+#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler   
+#define sEE_I2C_DMA_PREPRIO              0
+#define sEE_I2C_DMA_SUBPRIO              0   
+   
+#define sEE_DIRECTION_TX                 0
+#define sEE_DIRECTION_RX                 1   
+
+/* Time constant for the delay caclulation allowing to have a millisecond 
+   incrementing counter. This value should be equal to (System Clock / 1000).
+   ie. if system clock = 32MHz then sEE_TIME_CONST should be 32. */
+#define sEE_TIME_CONST                   32 
+   
+/**
+  * @}
+  */
+   
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */ 
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void SD_LowLevel_DMA_TxConfig(uint32_t *BufferSRC, uint32_t BufferSize);
+void SD_LowLevel_DMA_RxConfig(uint32_t *BufferDST, uint32_t BufferSize);
+void LM75_LowLevel_DeInit(void);
+void LM75_LowLevel_Init(void); 
+void sEE_SPI_LowLevel_DeInit(void);
+void sEE_SPI_LowLevel_Init(void); 
+void sEE_LowLevel_DeInit(void);
+void sEE_LowLevel_Init(void); 
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+  
+#endif /* __STM32L152D_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.c
new file mode 100644
index 0000000..4fad206
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.c
@@ -0,0 +1,1489 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_audio_codec.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file includes the low layer driver for CS43L22 Audio Codec
+  *          mounted on STM32L152D-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/*==============================================================================================================================
+                                             User NOTES
+1. How To use this driver:
+--------------------------
+   - This driver supports STM32L1xx devices on STM32L152D-EVAL Evaluation boards.
+
+   - Configure the options in file stm32l152d_eval_audio_codec.h in the section CONFIGURATION.
+     Refer to the sections 2 and 3 to have more details on the possible configurations.
+
+   - Call the function EVAL_AUDIO_Init(
+                                    OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, 
+                                                 OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or 
+                                                 OUTPUT_DEVICE_BOTH)
+                                    Volume: intial volume to be set (0 is min (mute), 100 is max (100%)
+                                    AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...)
+                                     this parameter is relative to the audio file/stream type.
+                                   )
+      This function configures all the hardware required for the audio application (codec, I2C, I2S, 
+      GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK.
+      if the returned value is different from 0 or the function is stuck then the communication with
+      the codec or the IOExpander has failed (try to unplug the power or reset device in this case).
+      + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream.
+      + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream.
+      + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented 
+         into the audio jack on the evaluation board). When the Headphone is connected it is used
+         as output. When the headphone is disconnected from tha audio jack, the output is 
+         automatically switched to Speaker.
+      + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream
+         at the same time.
+
+   - Call the function EVAL_AUDIO_Play(
+                                  pBuffer: pointer to the audio data file address
+                                  Size: size of the buffer to be sent in Bytes
+                                 )
+      to start playing (for the first time) from the audio file/stream.
+
+   - Call the function EVAL_AUDIO_PauseResume(
+                                         Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or 
+                                               any value different from 0) to resume palying.
+                                         )
+       Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called
+          for resume (it is not allowed to call EVAL_AUDIO_Play() in this case).
+       Note. This function should be called only when the audio file is played or paused (not stopped).
+
+   - For each mode, you may need to implement the relative callback functions into your code.
+      The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in 
+      the stm324xg_eval_audio_codec.h file. (refer to the example for more details on the callbacks implementations)
+
+   - To Stop playing, to modify the volume level or to mute, use the functions
+       EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute().
+
+   - The driver API and the callback functions are at the end of the stm324xg_eval_audio_codec.h file.
+ 
+
+ Driver architecture:
+ --------------------
+ This driver is composed of three main layers:
+   o High Audio Layer: consists of the function API exported in the stm324xg_eval_audio_codec.h file
+     (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...)
+   o Codec Control layer: consists of the functions API controlling the audio codec (CS43L22) and 
+     included as local functions in file stm324xg_eval_audio_codec.c (Codec_Init(), Codec_Play() ...)
+   o Media Access Layer (MAL): which consists of functions allowing to access the media containing/
+     providing the audio file/stream. These functions are also included as local functions into
+     the stm324xg_eval_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...)
+  Each set of functions (layer) may be implemented independently of the others and customized when 
+  needed.
+
+2. Modes description:
+---------------------
+     + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location.
+     + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a 
+        memory location or from a device at real time (double buffer could be used).
+
+3. DMA interrupts description:
+------------------------------
+     + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has finished the transfer.
+     + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt.
+        then, a callback should be implemented by user to perform specific actions
+        when the DMA has reached the half of the buffer transfer (generally, it is useful 
+        to load the first half of buffer while DMA is loading from the second half).
+     + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer.
+
+4. Known Limitations:
+---------------------
+   1- When using the Speaker, if the audio file quality is not high enough, the speaker output
+      may produce high and uncomfortable noise level. To avoid this issue, to use speaker
+      output properly, try to increase audio file sampling rate (typically higher than 48KHz).
+      This operation will lead to larger file size.
+   2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some
+      user interrupt routines (in this case, interrupts could be disabled just before the start of 
+      communication then re-enabled when it is over). Note that this communication is only done at
+      the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is 
+      performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is 
+      required with the audio codec.
+  3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, 
+     File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file.
+  4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice 
+     on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing).
+  5- Supports only 16-bit audio data size.
+===============================================================================================================================*/
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval_audio_codec.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */  
+  
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32L152D_EVAL_AUDIO_CODEC
+  * @brief       This file includes the low layer driver for CS43L22 Audio Codec
+  *              available on STM32L152D-EVAL Eval.
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Defines
+  * @{
+  */ 
+
+/* Mask for the bit EN of the I2S CFGR register */
+#define I2S_ENABLE_MASK                 0x0400
+
+/* Delay for the Codec to be correctly reset */
+#define CODEC_RESET_DELAY               0x4FFF
+
+/* Codec audio Standards */
+#ifdef I2S_STANDARD_PHILLIPS
+#define  CODEC_STANDARD                0x04
+#define I2S_STANDARD                   I2S_Standard_Phillips
+#elif defined(I2S_STANDARD_MSB)
+#define  CODEC_STANDARD                0x00
+#define I2S_STANDARD                   I2S_Standard_MSB
+#elif defined(I2S_STANDARD_LSB)
+#define  CODEC_STANDARD                0x08
+#define I2S_STANDARD                   I2S_Standard_LSB
+#else 
+#error "Error: No audio communication standard selected !"
+#endif /* I2S_STANDARD */
+
+/* The 7 bits Codec address (sent through I2C interface) */
+#define CODEC_ADDRESS                   0x94  /* b00100111 */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Variables
+  * @{
+  */
+/* This structure is declared global because it is handled by two different functions */
+static DMA_InitTypeDef DMA_InitStructure;
+
+DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure;
+
+uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */
+uint32_t AudioRemSize   = 0xFFFF; /* This variable holds the remaining data in audio file */
+uint16_t *CurrentPos;             /* This variable holds the current position of audio pointer */
+
+__IO uint32_t  CODECTimeout = CODEC_LONG_TIMEOUT;
+__IO uint8_t OutputDev = 0;
+
+__IO uint32_t CurrAudioInterface = AUDIO_INTERFACE_I2S;
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Private_Functions
+  * @{
+  */ 
+static void Audio_MAL_IRQHandler(void);
+/*-----------------------------------
+Audio Codec functions 
+------------------------------------------*/
+/* High Layer codec functions */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+static uint32_t Codec_DeInit(void);
+static uint32_t Codec_Play(void);
+static uint32_t Codec_PauseResume(uint32_t Cmd);
+static uint32_t Codec_Stop(uint32_t Cmd);
+static uint32_t Codec_VolumeCtrl(uint8_t Volume);
+static uint32_t Codec_Mute(uint32_t Cmd);
+/* Low layer codec functions */
+static void     Codec_CtrlInterface_Init(void);
+static void     Codec_CtrlInterface_DeInit(void);
+static void     Codec_AudioInterface_Init(uint32_t AudioFreq);
+static void     Codec_AudioInterface_DeInit(void);
+static void     Codec_Reset(void);
+static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue);
+static uint32_t Codec_ReadRegister(uint8_t RegisterAddr);
+static void     Codec_GPIO_Init(void);
+static void     Codec_GPIO_DeInit(void);
+static void     Delay(__IO uint32_t nCount);
+/*----------------------------------------------------------------------------*/
+
+/*-----------------------------------
+MAL (Media Access Layer) functions 
+------------------------------------------*/
+/* Peripherals configuration functions */
+static void     Audio_MAL_Init(void);
+static void     Audio_MAL_DeInit(void);
+static void     Audio_MAL_Play(uint32_t Addr, uint32_t Size);
+static void     Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr);
+static void     Audio_MAL_Stop(void);
+
+/*----------------------------------------------------------------------------*/
+
+/* DMA Channel definitions */
+DMA_Channel_TypeDef* AUDIO_MAL_DMA_CHANNEL  = AUDIO_I2S_DMA_CHANNEL;
+uint32_t AUDIO_MAL_DMA_CLOCK    = AUDIO_I2S_DMA_CLOCK;
+uint32_t AUDIO_MAL_DMA_DREG     = AUDIO_I2S_DMA_DREG;
+uint32_t AUDIO_MAL_DMA_IRQ      = AUDIO_I2S_DMA_IRQ;
+uint32_t AUDIO_MAL_DMA_FLAG_TC  = AUDIO_I2S_DMA_FLAG_TC;
+uint32_t AUDIO_MAL_DMA_FLAG_HT  = AUDIO_I2S_DMA_FLAG_HT;
+uint32_t AUDIO_MAL_DMA_FLAG_TE  = AUDIO_I2S_DMA_FLAG_TE;
+
+
+/**
+  * @brief  Set the current audio interface (I2S).
+  * @param  Interface: AUDIO_INTERFACE_I2S
+  * @retval None
+  */
+void EVAL_AUDIO_SetAudioInterface(uint32_t Interface)
+{
+  CurrAudioInterface = Interface;
+
+  if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
+  {
+    /* DMA Channel definitions */
+    AUDIO_MAL_DMA_CLOCK    = AUDIO_I2S_DMA_CLOCK;
+    AUDIO_MAL_DMA_DREG     = AUDIO_I2S_DMA_DREG;
+    AUDIO_MAL_DMA_CHANNEL  = AUDIO_I2S_DMA_CHANNEL;
+    AUDIO_MAL_DMA_IRQ      = AUDIO_I2S_DMA_IRQ  ;
+    AUDIO_MAL_DMA_FLAG_TC  = AUDIO_I2S_DMA_FLAG_TC;
+    AUDIO_MAL_DMA_FLAG_HT  = AUDIO_I2S_DMA_FLAG_HT;
+    AUDIO_MAL_DMA_FLAG_TE  = AUDIO_I2S_DMA_FLAG_TE;
+  }
+}
+
+/**
+  * @brief  Configure the audio peripherals.
+  * @param  OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{
+  /* Perform low layer Codec initialization */
+  if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* I2S data transfer preparation:
+    Prepare the Media to be used for the audio transfer from memory to I2S peripheral */
+    Audio_MAL_Init();
+    
+    /* Return 0 when all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Deinitializes all the resources used by the codec (those initialized
+  *         by EVAL_AUDIO_Init() function). 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_DeInit(void)
+{
+  /* DeInitialize the Media layer */
+  Audio_MAL_DeInit();
+
+  /* DeInitialize Codec */
+  Codec_DeInit();
+
+  return 0;
+}
+
+/**
+  * @brief  Starts playing audio stream from a data buffer for a determined size. 
+  * @param  pBuffer: Pointer to the buffer 
+  * @param  Size: Number of audio data BYTES.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size)
+{
+  /* Set the total number of data to be played (count in half-word) */
+  AudioTotalSize = Size/2;
+
+  /* Call the audio Codec Play function */
+  Codec_Play();
+
+  /* Update the Media layer and enable it for play */  
+  Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2)));
+
+  /* Update the remaining number of data to be played */
+  AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize);
+
+  /* Update the current audio pointer position */
+  CurrentPos = pBuffer + DMA_MAX(AudioTotalSize);
+
+  return 0;
+}
+
+/**
+  * @brief  This function Pauses or Resumes the audio file stream. In case
+  *         of using DMA, the DMA Pause feature is used. In all cases the I2S 
+  *         peripheral is disabled. 
+  * 
+  * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only
+  *          this function should be called for resume (use of EVAL_AUDIO_Play() 
+  *          function for resume could lead to unexpected behavior).
+  * 
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd)
+{
+  /* Call the Audio Codec Pause/Resume function */
+  if (Codec_PauseResume(Cmd) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call the Media layer pause/resume function */
+    Audio_MAL_PauseResume(Cmd, 0);
+
+    /* Return 0 if all operations are OK */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Stops audio playing and Power down the Audio Codec. 
+  * @param  Option: could be one of the following parameters 
+  *           - CODEC_PDWN_SW: for software power off (by writing registers). 
+  *                            Then no need to reconfigure the Codec after power on.
+  *           - CODEC_PDWN_HW: completely shut down the codec (physically). 
+  *                            Then need to reconfigure the Codec after power on.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Stop(uint32_t Option)
+{
+  /* Call Audio Codec Stop function */
+  if (Codec_Stop(Option) != 0)
+  {
+    return 1;
+  }
+  else
+  {
+    /* Call Media layer Stop function */
+    Audio_MAL_Stop();
+
+    /* Update the remaining data number */
+    AudioRemSize = AudioTotalSize;    
+
+    /* Return 0 when all operations are correctly done */
+    return 0;
+  }
+}
+
+/**
+  * @brief  Controls the current audio volume level. 
+  * @param  Volume: Volume level to be set in percentage from 0% to 100% (0 for 
+  *         Mute and 100 for Max volume level).
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume)
+{
+  /* Call the codec volume control function with converted volume value */
+  return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume)));
+}
+
+/**
+  * @brief  Enables or disables the MUTE mode by software 
+  * @param  Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to 
+  *         unmute the codec and restore previous volume level.
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t EVAL_AUDIO_Mute(uint32_t Cmd)
+{
+  /* Call the Codec Mute function */
+  return (Codec_Mute(Cmd));
+}
+
+/**
+  * @brief  This function handles main Media layer interrupt. 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static void Audio_MAL_IRQHandler(void)
+{
+#ifndef AUDIO_MAL_MODE_NORMAL
+  uint16_t *pAddr = (uint16_t *)CurrentPos;
+  uint32_t Size = AudioRemSize;
+#endif /* AUDIO_MAL_MODE_NORMAL */
+
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+  /* Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TC) != RESET)
+  {
+#ifdef AUDIO_MAL_MODE_NORMAL
+    /* Check if the end of file has been reached */
+    if (AudioRemSize > 0)
+    {
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag( AUDIO_MAL_DMA_FLAG_TC);  
+
+      /* Re-Configure the buffer address and size */
+      DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) CurrentPos;
+      DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize));
+
+      /* Configure the DMA Channel with the new parameters */
+      DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);
+
+      /* Enable the I2S DMA Channel*/
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+
+      /* Update the current pointer position */
+      CurrentPos += DMA_MAX(AudioRemSize);
+
+      /* Update the remaining number of data to be played */
+      AudioRemSize -= DMA_MAX(AudioRemSize);
+    }
+    else
+    {
+      /* Disable the I2S DMA Channel*/
+      DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+
+      /* Clear the Interrupt flag */
+      DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);
+      
+      /* Manage the remaining file size and new address offset: This function 
+      should be coded by user (its prototype is already declared in stm32l152d_eval_audio_codec.h) */
+      EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0);
+    }
+    
+#elif defined(AUDIO_MAL_MODE_CIRCULAR)
+    /* Manage the remaining file size and new address offset: This function 
+    should be coded by user (its prototype is already declared in stm32l152d_eval_audio_codec.h) */
+    EVAL_AUDIO_TransferComplete_CallBack(*pAddr, Size);
+
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC);
+#endif /* AUDIO_MAL_MODE_NORMAL */
+  }
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+
+#ifdef AUDIO_MAL_DMA_IT_HT_EN
+  /* Half Transfer complete interrupt */
+  if (DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_HT) != RESET)
+  {
+    /* Manage the remaining file size and new address offset: This function 
+    should be coded by user (its prototype is already declared in stm32l152d_eval_audio_codec.h) */
+    EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size);
+
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_HT);
+  }
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+
+#ifdef AUDIO_MAL_DMA_IT_TE_EN
+  /* FIFO Error interrupt */
+  if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_FLAG_TE) != RESET))
+    
+  {
+    /* Manage the error generated on DMA FIFO: This function 
+    should be coded by user (its prototype is already declared in stm32l152d_eval_audio_codec.h) */
+    EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr);
+
+    /* Clear the Interrupt flag */
+    DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TE);
+  }
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+}
+
+/**
+  * @brief  This function handles main I2S interrupt. 
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+void Audio_MAL_I2S_IRQHandler(void)
+{ 
+  Audio_MAL_IRQHandler();
+}
+
+/**
+  * @brief  I2S interrupt management
+  * @param  None
+  * @retval None
+  */
+void Audio_I2S_IRQHandler(void)
+{
+  EVAL_Audio_I2S_IRQHandler();
+}
+
+/*==============================================================================
+                  CS43L22 Audio Codec Control Functions
+==============================================================================*/
+/**
+  * @brief  Initializes the audio codec and all related interfaces (control 
+  *         interface: I2C and audio interface: I2S)
+  * @param  OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
+  *                       OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
+  * @param  Volume: Initial volume level (from 0 (Mute) to 100 (Max))
+  * @param  AudioFreq: Audio frequency used to play the audio stream.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
+{
+  uint32_t counter = 0;
+
+  /* Configure the Codec related IOs */
+  Codec_GPIO_Init();
+
+  /* Reset the Codec Registers */
+  Codec_Reset();
+
+  /* Initialize the Control interface of the Audio Codec */
+  Codec_CtrlInterface_Init();
+
+  /* Keep Codec powered OFF */
+  counter += Codec_WriteRegister(0x02, 0x01);
+
+  switch (OutputDevice)
+  {
+  case OUTPUT_DEVICE_SPEAKER:
+    counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+    OutputDev = 0xFA;
+    break;
+    
+  case OUTPUT_DEVICE_HEADPHONE:
+    counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+    OutputDev = 0xAF;
+    break;
+    
+  case OUTPUT_DEVICE_BOTH:
+    counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+    OutputDev = 0xAA;
+    break;
+    
+  case OUTPUT_DEVICE_AUTO:
+    counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+    OutputDev = 0x05;
+    break;
+    
+  default:
+    counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+    OutputDev = 0x05;
+    break;
+  }
+
+  /* Clock configuration: Auto detection */  
+  counter += Codec_WriteRegister(0x05, 0x81);
+
+  /* Set the Slave Mode and the audio Standard */  
+  counter += Codec_WriteRegister(0x06, CODEC_STANDARD);
+
+  /* Set the Master volume */
+  Codec_VolumeCtrl(Volume);
+
+  /* If the Speaker is enabled, set the Mono mode and volume attenuation level */
+  if (OutputDevice != OUTPUT_DEVICE_HEADPHONE)
+  {
+    /* Set the Speaker Mono mode */  
+    counter += Codec_WriteRegister(0x0F , 0x06);
+
+    /* Set the Speaker attenuation level */
+    counter += Codec_WriteRegister(0x24, 0xF0);
+    counter += Codec_WriteRegister(0x25, 0xF0);
+  }
+
+  /* Power on the Codec */
+  counter += Codec_WriteRegister(0x02, 0x9E);
+
+  /* Configure the I2S peripheral */
+  Codec_AudioInterface_Init(AudioFreq);
+
+  /* Return communication control value */
+  return counter;  
+}
+
+/**
+  * @brief  Restore the audio codec state to default state and free all used 
+  *         resources.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_DeInit(void)
+{
+  uint32_t counter = 0; 
+
+  /* Reset the Codec Registers */
+  Codec_Reset();
+
+  /* Keep Codec powered OFF */
+  counter += Codec_WriteRegister(0x02, 0x01);
+
+  /* Deinitialize all use GPIOs */
+  Codec_GPIO_DeInit();
+
+  /* Disable the Codec control interface */
+  Codec_CtrlInterface_DeInit();
+
+  /* Deinitialize the Codec audio interface (I2S) */
+  Codec_AudioInterface_DeInit();
+
+  /* Return communication control value */
+  return counter;
+}
+
+/**
+  * @brief  Start the audio Codec play feature.
+  * @note   For this codec no Play options are required.
+  * @param  None
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Play(void)
+{
+  /* 
+  No actions required on Codec level for play command
+  */
+  
+  /* Return communication control value */
+  return 0;
+}
+
+/**
+  * @brief  Pauses and resumes playing on the audio codec.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *         from 0) to resume. 
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_PauseResume(uint32_t Cmd)
+{
+  uint32_t counter = 0;
+
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  {
+    /* Mute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_ON);
+
+    /* Put the Codec in Power save mode */
+    counter += Codec_WriteRegister(0x02, 0x01);
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Unmute the output first */
+    counter += Codec_Mute(AUDIO_MUTE_OFF);
+
+    counter += Codec_WriteRegister(0x04, OutputDev);
+
+    /* Exit the Power save mode */
+    counter += Codec_WriteRegister(0x02, 0x9E);
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Stops audio Codec playing. It powers down the codec.
+  * @param  CodecPdwnMode: selects the  power down mode.
+  *          - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this 
+  *                           mode the codec keeps the previous initialization
+  *                           (no need to re-Initialize the codec registers).
+  *          - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
+  *                           mode, the codec is set to default configuration 
+  *                           (user should re-Initialize the codec in order to 
+  *                            play again the audio stream).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Stop(uint32_t CodecPdwnMode)
+{
+  uint32_t counter = 0;
+
+  /* Mute the output first */
+  Codec_Mute(AUDIO_MUTE_ON);
+
+  if (CodecPdwnMode == CODEC_PDWN_SW)
+  {
+    /* Power down the speaker (PMSPK bits)*/
+    counter += Codec_WriteRegister(0x02, 0x9F);
+  }
+  else /* CODEC_PDWN_HW */
+  {
+    /* Power down the components */
+    counter += Codec_WriteRegister(0x02, 0x9F);
+
+    /* Wait at least 100us */
+    Delay(0xFFF);
+
+    /* Reset The pin */
+    GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
+  }
+  
+  return counter;
+}
+
+/**
+  * @brief  Sets higher or lower the codec volume level.
+  * @param  Volume: a byte value from 0 to 255 (refer to codec registers 
+  *         description for more details).
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_VolumeCtrl(uint8_t Volume)
+{
+  uint32_t counter = 0;
+
+  if (Volume > 0xE6)
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume - 0xE7);
+    counter += Codec_WriteRegister(0x21, Volume - 0xE7);
+  }
+  else
+  {
+    /* Set the Master volume */
+    counter += Codec_WriteRegister(0x20, Volume + 0x19);
+    counter += Codec_WriteRegister(0x21, Volume + 0x19);
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Enables or disables the mute feature on the audio codec.
+  * @param  Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
+  *             mute mode.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_Mute(uint32_t Cmd)
+{
+  uint32_t counter = 0;
+
+  /* Set the Mute mode */
+  if (Cmd == AUDIO_MUTE_ON)
+  {
+    counter += Codec_WriteRegister(0x04, 0xFF);
+  }
+  else /* AUDIO_MUTE_OFF Disable the Mute */
+  {
+    counter += Codec_WriteRegister(0x04, OutputDev);
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Resets the audio codec. It restores the default configuration of the 
+  *         codec (this function shall be called before initializing the codec).
+  * @note   This function calls an external driver function: The IO Expander driver.
+  * @param  None
+  * @retval None
+  */
+static void Codec_Reset(void)
+{
+  /* Power Down the codec */
+  GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET);
+
+  /* wait for a delay to insure registers erasing */
+  Delay(CODEC_RESET_DELAY);
+
+  /* Power on the codec */
+  GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_SET);
+}
+
+/**
+  * @brief  Writes a Byte to a given register into the audio codec through the 
+  *         control interface (I2C)
+  * @param  RegisterAddr: The address (location) of the register to be written.
+  * @param  RegisterValue: the Byte value to be written into destination register.
+  * @retval 0 if correct communication, else wrong communication
+  */
+static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+  uint32_t result = 0;
+
+  /*!< While the bus is busy */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Start the config sequence */
+  I2C_GenerateSTART(CODEC_I2C, ENABLE);
+
+  /* Test on EV5 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter);
+
+  /* Test on EV6 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Transmit the first address for write operation */
+  I2C_SendData(CODEC_I2C, RegisterAddr);
+
+  /* Test on EV8 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Prepare the register value to be sent */
+  I2C_SendData(CODEC_I2C, RegisterValue);
+
+  /*!< Wait till all data have been physically transferred on the bus */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(!I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF))
+  {
+    if((CODECTimeout--) == 0) Codec_TIMEOUT_UserCallback();
+  }
+
+  /* End the configuration sequence */
+  I2C_GenerateSTOP(CODEC_I2C, ENABLE);
+
+#ifdef VERIFY_WRITTENDATA
+  /* Verify that the data has been correctly written */  
+  result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1;
+#endif /* VERIFY_WRITTENDATA */
+
+  /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+  return result;
+}
+
+/**
+  * @brief  Reads and returns the value of an audio codec register through the
+  *         control interface (I2C).
+  * @param  RegisterAddr: Address of the register to be read.
+  * @retval Value of the register to be read or dummy value if the communication
+  *         fails.
+  */
+static uint32_t Codec_ReadRegister(uint8_t RegisterAddr)
+{
+  uint32_t result = 0;
+
+  /*!< While the bus is busy */
+  CODECTimeout = CODEC_LONG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Start the config sequence */
+  I2C_GenerateSTART(CODEC_I2C, ENABLE);
+
+  /* Test on EV5 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter);
+
+  /* Test on EV6 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /* Transmit the register address to be read */
+  I2C_SendData(CODEC_I2C, RegisterAddr);
+
+  /* Test on EV8 and clear it */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /*!< Send START condition a second time */
+  I2C_GenerateSTART(CODEC_I2C, ENABLE);
+
+  /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /*!< Send Codec address for read */
+  I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Receiver);
+
+  /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_ADDR) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /*!< Disable Acknowledgment */
+  I2C_AcknowledgeConfig(CODEC_I2C, DISABLE);
+
+  /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
+  (void)CODEC_I2C->SR2;
+
+  /*!< Send STOP Condition */
+  I2C_GenerateSTOP(CODEC_I2C, ENABLE);
+
+  /* Wait for the byte to be received */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_RXNE) == RESET)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /*!< Read the byte received from the Codec */
+  result = I2C_ReceiveData(CODEC_I2C);
+
+  /* Wait to make sure that STOP flag has been cleared */
+  CODECTimeout = CODEC_FLAG_TIMEOUT;
+  while(CODEC_I2C->CR1 & I2C_CR1_STOP)
+  {
+    if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback();
+  }
+
+  /*!< Re-Enable Acknowledgment to be ready for another reception */
+  I2C_AcknowledgeConfig(CODEC_I2C, ENABLE);
+
+  /* Clear AF flag for next communication */
+  I2C_ClearFlag(CODEC_I2C, I2C_FLAG_AF);
+
+  /* Return the byte read from Codec */
+  return result;
+}
+
+/**
+  * @brief  Initializes the Audio Codec control interface (I2C).
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_Init(void)
+{
+  I2C_InitTypeDef I2C_InitStructure;
+  
+  /* Enable the CODEC_I2C peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE);
+
+  /* CODEC_I2C peripheral configuration */
+  I2C_DeInit(CODEC_I2C);
+  I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x33;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED;
+  /* Enable the I2C peripheral */
+  I2C_Cmd(CODEC_I2C, ENABLE);  
+  I2C_Init(CODEC_I2C, &I2C_InitStructure);
+}
+
+/**
+  * @brief  Restore the Audio Codec control interface to its default state.
+  *         This function doesn't de-initialize the I2C because the I2C peripheral
+  *         may be used by other modules.
+  * @param  None
+  * @retval None
+  */
+static void Codec_CtrlInterface_DeInit(void)
+{
+  /* Disable the I2C peripheral */ /* This step is not done here because 
+  the I2C interface can be used by other modules */
+  I2C_DeInit(CODEC_I2C); 
+}
+
+/**
+  * @brief  Initializes the Audio Codec audio interface (I2S)
+  * @note   This function assumes that the I2S input clock (through PLL_R in 
+  *         Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
+  *         is already configured and ready to be used.    
+  * @param  AudioFreq: Audio frequency to be configured for the I2S peripheral.
+  * @retval None
+  */
+static void Codec_AudioInterface_Init(uint32_t AudioFreq)
+{
+  I2S_InitTypeDef I2S_InitStructure;
+
+  /* Enable the CODEC_I2S peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
+
+  /* CODEC_I2S peripheral configuration */
+  SPI_I2S_DeInit(CODEC_I2S);
+  I2S_InitStructure.I2S_AudioFreq = AudioFreq;
+  I2S_InitStructure.I2S_Standard = I2S_STANDARD;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
+
+#ifdef CODEC_MCLK_ENABLED
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
+#elif defined(CODEC_MCLK_DISABLED)
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+#else
+#error "No selection for the MCLK output has been defined !"
+#endif /* CODEC_MCLK_ENABLED */
+
+  /* Initialize the I2S peripheral with the structure above */
+  I2S_Init(CODEC_I2S, &I2S_InitStructure);
+  /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function 
+  or by user functions if DMA mode not enabled */  
+}
+
+/**
+  * @brief  Restores the Audio Codec audio interface to its default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_AudioInterface_DeInit(void)
+{
+  /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+
+  /* Deinitialize the CODEC_I2S peripheral */
+  SPI_I2S_DeInit(CODEC_I2S);
+
+  /* Disable the CODEC_I2S peripheral clock */
+  RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, DISABLE);
+}
+
+/**
+  * @brief  Initializes IOs used by the Audio Codec (on the control and audio 
+  *         interfaces).
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable Reset GPIO Clock */
+  RCC_AHBPeriphClockCmd(AUDIO_RESET_GPIO_CLK,ENABLE);
+
+/* Audio reset pin configuration ---------------------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = AUDIO_RESET_PIN; 
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(AUDIO_RESET_GPIO, &GPIO_InitStructure);
+
+  /* Enable I2S and I2C GPIO clocks */
+  RCC_AHBPeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE);
+
+/* CODEC_I2C SCL and SDA pins configuration ----------------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN | CODEC_I2C_SDA_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2C_GPIO, &GPIO_InitStructure);     
+  /* Connect pins to I2C peripheral */
+  GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF);
+
+/* CODEC_I2S pins configuration: WS, SCK and SD pins -------------------------*/
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN |
+                                CODEC_I2S_SD_PIN |
+                                CODEC_I2S_WS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF);
+
+#ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins configuration: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);
+  /* Connect pins to I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF);
+#endif /* CODEC_MCLK_ENABLED */
+}
+
+/**
+  * @brief  Restores the IOs used by the Audio Codec interface to their default state.
+  * @param  None
+  * @retval None
+  */
+static void Codec_GPIO_DeInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Deinitialize all the GPIOs used by the driver */
+  GPIO_InitStructure.GPIO_Pin =  CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
+  GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure);
+
+  /* Disconnect pins from I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_WS_PINSRC, 0x00);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, 0x00);
+  GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, 0x00);
+
+#ifdef CODEC_MCLK_ENABLED
+  /* CODEC_I2S pins deinitialization: MCK pin */
+  GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN;
+  GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure);
+  /* Disconnect pins from I2S peripheral  */
+  GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF);
+#endif /* CODEC_MCLK_ENABLED */
+}
+
+/**
+  * @brief  Inserts a delay time (not accurate timing).
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void Delay( __IO uint32_t nCount)
+{
+  for (; nCount != 0; nCount--);
+}
+
+#ifdef USE_DEFAULT_TIMEOUT_CALLBACK
+/**
+  * @brief  Basic management of the timeout situation.
+  * @param  None
+  * @retval None
+  */
+uint32_t Codec_TIMEOUT_UserCallback(void)
+{
+  /* Block communication and all processes */
+  while (1)
+  {
+  }
+}
+#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
+
+/*==============================================================================
+                  Audio MAL Interface Control Functions
+==============================================================================*/
+
+/**
+  * @brief  Initializes and prepares the Media to perform audio data transfer 
+  *         from Media to the I2S peripheral.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Init(void)
+{
+
+#ifdef I2S_INTERRUPT
+  NVIC_InitTypeDef   NVIC_InitStructure;
+
+  NVIC_InitStructure.NVIC_IRQChannel = CODEC_I2S_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority =0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  SPI_I2S_ITConfig(CODEC_I2S, SPI_I2S_IT_TXE, ENABLE);
+
+#else
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;
+#endif
+
+  if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
+  {
+    /* Enable the DMA clock */
+    RCC_AHBPeriphClockCmd(AUDIO_I2S_DMA_CLOCK, ENABLE);
+
+    /* Configure the DMA Channel */
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+    DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+    /* Set the parameters to be configured */
+    DMA_InitStructure.DMA_PeripheralBaseAddr = AUDIO_MAL_DMA_DREG;
+    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0; /* This field will be configured in play function */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */
+    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+    DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
+    DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; 
+#ifdef AUDIO_MAL_MODE_NORMAL
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+#elif defined(AUDIO_MAL_MODE_CIRCULAR)
+    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
+#else
+#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
+#endif /* AUDIO_MAL_MODE_NORMAL */  
+    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+    DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);  
+
+    /* Enable the selected DMA interrupts (selected in "stm32l152d_eval_eval_audio_codec.h" defines) */
+#ifdef AUDIO_MAL_DMA_IT_TC_EN
+    DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_TC, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TC_EN */
+#ifdef AUDIO_MAL_DMA_IT_HT_EN
+    DMA_ITConfig(AUDIO_MAL_DMA_CHANNEL, DMA_IT_HT, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_HT_EN */
+#ifdef AUDIO_MAL_DMA_IT_TE_EN
+    DMA_ITConfig(AUDIO_MAL_DMA_CHANNEl, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
+#endif /* AUDIO_MAL_DMA_IT_TE_EN */
+
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+    /* I2S DMA IRQ Channel configuration */
+    NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+#endif
+  }
+
+  if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
+  {
+    /* Enable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+  }
+#endif
+}
+
+/**
+  * @brief  Restore default state of the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_DeInit(void)
+{
+#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* Deinitialize the NVIC interrupt for the I2S DMA Channel */
+  NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
+  NVIC_Init(&NVIC_InitStructure);  
+#endif 
+
+  /* Disable the DMA channel before the deinit */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+
+  /* Dinitialize the DMA Channel */
+  DMA_DeInit(AUDIO_MAL_DMA_CHANNEL);
+
+  /* 
+  The DMA clock is not disabled, since it can be used by other channels 
+  */ 
+}
+
+/**
+  * @brief  Starts playing audio stream from the audio Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Play(uint32_t Addr, uint32_t Size)
+{
+#ifndef I2S_INTERRUPT
+  if (CurrAudioInterface == AUDIO_INTERFACE_I2S)
+  {
+    /* Configure the buffer address and size */
+    DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)Addr;
+    DMA_InitStructure.DMA_BufferSize = (uint32_t)Size;
+
+    /* Configure the DMA Channel with the new parameters */
+    DMA_Init(AUDIO_MAL_DMA_CHANNEL, &DMA_InitStructure);
+
+    /* Enable the I2S DMA Channel*/
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+  }
+#else
+  /* If the I2S peripheral is still not enabled, enable it */
+  if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
+  {
+    I2S_Cmd(CODEC_I2S, ENABLE);
+  }
+#endif /* I2S_INTERRUPT */
+}
+
+/**
+  * @brief  Switch dynamically (while audio file is played) the output target 
+  *         (speaker or headphone).
+  * @note   This function modifies a global variable of the audio codec driver: OutputDev.
+  * @param  Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
+  *         OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO 
+  * @retval 0 if correct communication, else wrong communication
+  */
+uint32_t Codec_SwitchOutput(uint8_t Output)
+{
+  uint8_t counter = 0;
+
+  switch (Output)
+  {
+  case OUTPUT_DEVICE_SPEAKER:
+    counter += Codec_WriteRegister(0x04, 0xFA); /* SPK always ON & HP always OFF */
+    OutputDev = 0xFA;
+    break;
+
+  case OUTPUT_DEVICE_HEADPHONE:
+    counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */
+    OutputDev = 0xAF;
+    break;
+
+  case OUTPUT_DEVICE_BOTH:
+    counter += Codec_WriteRegister(0x04, 0xAA); /* SPK always ON & HP always ON */
+    OutputDev = 0xAA;
+    break;
+
+  case OUTPUT_DEVICE_AUTO:
+    counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+    OutputDev = 0x05;
+    break;
+
+  default:
+    counter += Codec_WriteRegister(0x04, 0x05); /* Detect the HP or the SPK automatically */
+    OutputDev = 0x05;
+    break;
+  }
+
+  return counter;
+}
+
+/**
+  * @brief  Pauses or Resumes the audio stream playing from the Media.
+  * @param  Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
+  *              from 0) to resume. 
+  * @param  Addr: Address from/at which the audio stream should resume/pause.
+  * @retval None
+  */
+static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr)
+{
+  /* Pause the audio file playing */
+  if (Cmd == AUDIO_PAUSE)
+  {
+    /* Disable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE);
+
+    /* Pause the I2S DMA Channel 
+    Note. For the STM32L1xx devices, the DMA implements a pause feature, 
+    by disabling the Channel, all configuration is preserved and data 
+    transfer is paused till the next enable of the Channel.
+    This feature is not available on STM32L1xx devices. */
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+  }
+  else /* AUDIO_RESUME */
+  {
+    /* Enable the I2S DMA request */
+    SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
+
+    /* Resume the I2S DMA Channel 
+    Note. For the STM32L1xx devices, the DMA implements a pause feature, 
+    by disabling the channel, all configuration is preserved and data 
+    transfer is paused till the next enable of the channel.
+    This feature is not available on STM32L1xx devices. */
+    DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, ENABLE);
+
+    /* If the I2S peripheral is still not enabled, enable it */
+    if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
+    {
+      I2S_Cmd(CODEC_I2S, ENABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Stops audio stream playing on the used Media.
+  * @param  None
+  * @retval None
+  */
+static void Audio_MAL_Stop(void)
+{
+  /* Stop the Transfer on the I2S side: Stop and disable the DMA channel */
+  DMA_Cmd(AUDIO_MAL_DMA_CHANNEL, DISABLE);
+
+  /* Clear all the DMA flags for the next transfer */
+  DMA_ClearFlag(AUDIO_MAL_DMA_FLAG_TC |AUDIO_MAL_DMA_FLAG_HT | AUDIO_MAL_DMA_FLAG_TE);
+
+  /*
+  The I2S DMA requests are not disabled here.
+  */
+  /* In all modes, disable the I2S peripheral */
+  I2S_Cmd(CODEC_I2S, DISABLE);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.h
new file mode 100644
index 0000000..cb808e9
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_audio_codec.h
@@ -0,0 +1,283 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_audio_codec.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32l152d_eval_audio_codec.c driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152D_EVAL_AUDIOCODEC_H
+#define __STM32L152D_EVAL_AUDIOCODEC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152D_EVAL_AUDIO_CODEC
+  * @{
+  */  
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Exported_Constants
+  * @{
+  */
+
+/*------------------------------------
+             CONFIGURATION: Audio Codec Driver Configuration parameters
+                                      ----------------------------------------*/
+#define I2S_INTERRUPT   /* Comment this line to enable the DMA Handler */
+/* Audio Transfer mode (DMA, Interrupt or Polling) */
+#define AUDIO_MAL_MODE_NORMAL         /* Uncomment this line to enable the audio
+                                         Transfer using DMA with normal mode */
+/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio
+                                         Transfer using DMA with circular mode */
+
+/* For the DMA modes select the interrupt that will be used */
+#define AUDIO_MAL_DMA_IT_TC_EN        /* Uncomment this line to enable DMA Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_HT_EN */  /* Uncomment this line to enable DMA Half Transfer Complete interrupt */
+/* #define AUDIO_MAL_DMA_IT_TE_EN */  /* Uncomment this line to enable DMA Transfer Error interrupt */
+
+/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
+#define EVAL_AUDIO_IRQ_PREPRIO           0   /* Select the preemption priority level(0 is the highest) */
+#define EVAL_AUDIO_IRQ_SUBRIO            0   /* Select the sub-priority level (0 is the highest) */
+
+/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() 
+   function implemented in stm32l152d_eval_audio_codec.c file.
+   Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */
+/* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------
+                    OPTIONAL Configuration defines parameters
+                                      ----------------------------------------*/
+/* I2C clock speed configuration (in Hz) 
+  WARNING: 
+    Make sure that this define is not already declared in other files (ie. 
+    stm32l152d_eval.h file). It can be used in parallel by other modules. */
+#ifndef I2C_SPEED
+ #define I2C_SPEED                        100000
+#endif /* I2C_SPEED */
+
+/* Uncomment defines below to select standard for audio communication between 
+  Codec and I2S peripheral */
+#define I2S_STANDARD_PHILLIPS
+/* #define I2S_STANDARD_MSB */
+/* #define I2S_STANDARD_LSB */
+
+/* Uncomment the defines below to select if the Master clock mode should be 
+  enabled or not */
+#define CODEC_MCLK_ENABLED
+/* #define CODEC_MCLK_DISABLED */
+
+/* Uncomment this line to enable verifying data sent to codec after each write 
+  operation */
+#define VERIFY_WRITTENDATA
+/*----------------------------------------------------------------------------*/
+
+/*-----------------------------------
+                    Hardware Configuration defines parameters
+                                     -----------------------------------------*/
+/* Audio Reset Pin definition */
+#define AUDIO_RESET_GPIO_CLK           RCC_AHBPeriph_GPIOB
+#define AUDIO_RESET_PIN                GPIO_Pin_1
+#define AUDIO_RESET_GPIO               GPIOB
+
+/* I2S peripheral configuration defines */
+#define CODEC_I2S                      SPI2
+#define CODEC_I2S_CLK                  RCC_APB1Periph_SPI2
+#define CODEC_I2S_ADDRESS              0x4000380C
+#define CODEC_I2S_GPIO_AF              GPIO_AF_SPI2
+#define CODEC_I2S_IRQ                  SPI2_IRQn
+#define CODEC_I2S_GPIO_CLOCK           (RCC_AHBPeriph_GPIOC | RCC_AHBPeriph_GPIOB)
+#define CODEC_I2S_WS_PIN               GPIO_Pin_12
+#define CODEC_I2S_SCK_PIN              GPIO_Pin_13
+#define CODEC_I2S_SD_PIN               GPIO_Pin_15
+#define CODEC_I2S_MCK_PIN              GPIO_Pin_6
+#define CODEC_I2S_WS_PINSRC            GPIO_PinSource12
+#define CODEC_I2S_SCK_PINSRC           GPIO_PinSource13
+#define CODEC_I2S_SD_PINSRC            GPIO_PinSource15
+#define CODEC_I2S_MCK_PINSRC           GPIO_PinSource6
+#define CODEC_I2S_GPIO                 GPIOB
+#define CODEC_I2S_MCK_GPIO             GPIOC
+#define Audio_I2S_IRQHandler           SPI2_IRQHandler
+
+
+#define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord
+#define AUDIO_MAL_DMA_MEM_DATA_SIZE    DMA_MemoryDataSize_HalfWord
+#define DMA_MAX_SZE                    0xFFFF
+
+ /* I2S DMA Channel definitions */
+#define AUDIO_I2S_DMA_CLOCK            RCC_AHBPeriph_DMA1
+#define AUDIO_I2S_DMA_DREG             CODEC_I2S_ADDRESS
+#define AUDIO_I2S_DMA_CHANNEL          DMA1_Channel5
+#define AUDIO_I2S_DMA_IRQ              DMA1_Channel5_IRQn
+#define AUDIO_I2S_DMA_FLAG_TC          DMA1_FLAG_TC5
+#define AUDIO_I2S_DMA_FLAG_HT          DMA1_FLAG_HT5
+#define AUDIO_I2S_DMA_FLAG_TE          DMA1_FLAG_TE5
+
+#define Audio_MAL_I2S_IRQHandler       DMA1_Channel5_IRQHandler
+
+/* I2C peripheral configuration defines (control interface of the audio codec) */
+#define CODEC_I2C                      I2C1
+#define CODEC_I2C_CLK                  RCC_APB1Periph_I2C1
+#define CODEC_I2C_GPIO_CLOCK           RCC_AHBPeriph_GPIOB
+#define CODEC_I2C_GPIO_AF              GPIO_AF_I2C1
+#define CODEC_I2C_GPIO                 GPIOB
+#define CODEC_I2C_SCL_PIN              GPIO_Pin_8
+#define CODEC_I2C_SDA_PIN              GPIO_Pin_9
+#define CODEC_I2S_SCL_PINSRC           GPIO_PinSource8
+#define CODEC_I2S_SDA_PINSRC           GPIO_PinSource9
+
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define CODEC_FLAG_TIMEOUT             ((uint32_t)0x1000)
+#define CODEC_LONG_TIMEOUT             ((uint32_t)(300 * CODEC_FLAG_TIMEOUT))
+/*----------------------------------------------------------------------------*/
+
+/*-----------------------------------
+                        Audio Codec User defines
+                                     -----------------------------------------*/
+/* Audio interface : I2S */
+#define AUDIO_INTERFACE_I2S           1
+
+/* Codec output DEVICE */
+#define OUTPUT_DEVICE_SPEAKER         1
+#define OUTPUT_DEVICE_HEADPHONE       2
+#define OUTPUT_DEVICE_BOTH            3
+#define OUTPUT_DEVICE_AUTO            4
+
+/* Volume Levels values */
+#define DEFAULT_VOLMIN                0x00
+#define DEFAULT_VOLMAX                0xFF
+#define DEFAULT_VOLSTEP               0x04
+
+#define AUDIO_PAUSE                   0
+#define AUDIO_RESUME                  1
+
+/* Codec POWER DOWN modes */
+#define CODEC_PDWN_HW                 1
+#define CODEC_PDWN_SW                 2
+
+/* MUTE commands */
+#define AUDIO_MUTE_ON                 1
+#define AUDIO_MUTE_OFF                0
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Exported_Macros
+  * @{
+  */ 
+#define VOLUME_CONVERT(x)    ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100)))
+#define DMA_MAX(x)           (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_AUDIO_CODEC_Exported_Functions
+  * @{
+  */ 
+void EVAL_AUDIO_SetAudioInterface(uint32_t Interface);
+uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
+uint32_t EVAL_AUDIO_DeInit(void);
+uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size);
+uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd);
+uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode);
+uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume);
+uint32_t EVAL_AUDIO_Mute(uint32_t Command);
+uint32_t Codec_SwitchOutput(uint8_t Output) ;
+
+/* User Callbacks: user has to implement these functions in his code if
+  they are needed. -----------------------------------------------------------*/
+
+extern uint16_t EVAL_AUDIO_GetSampleCallBack(void);
+
+/* User I2S IrqnHandler : user has to implement these functions in his code if
+  they are needed. -----------------------------------------------------------*/
+extern void EVAL_Audio_I2S_IRQHandler(void);
+
+
+/* This function is called when the requested data has been completely transferred.
+   In Normal mode (when  the define AUDIO_MAL_MODE_NORMAL is enabled) this function
+   is called at the end of the whole audio file.
+   In circular mode (when  the define AUDIO_MAL_MODE_CIRCULAR is enabled) this 
+   function is called at the end of the current buffer transmission. */
+void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when half of the requested buffer has been transferred 
+   This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR 
+   define is enabled)*/
+void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size);
+
+/* This function is called when an Interrupt due to transfer error on or peripheral
+   error occurs. */
+void EVAL_AUDIO_Error_CallBack(void* pData);
+
+/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition 
+   occurs during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...) on the Codec control interface (I2C).
+   You can use the default timeout callback implementation by uncommenting the 
+   define USE_DEFAULT_TIMEOUT_CALLBACK in stm32l152d_eval_audio_codec.h file.
+   Typically the user implementation of this callback should reset I2C peripheral
+   and re-initialize communication or in worst case reset all the application. */
+uint32_t Codec_TIMEOUT_UserCallback(void);
+
+#endif /* __STM32L152D_EVAL_AUDIOCODEC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_nor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_nor.c
new file mode 100644
index 0000000..9d6484f
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_fsmc_nor.c
@@ -0,0 +1,535 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_fsmc_nor.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to drive the M29W128FL, 
+  *          M29W128GL and S29GL128P NOR memories mounted on STM32L152D-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval_fsmc_nor.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152D_EVAL_FSMC_NOR
+  * @brief      This file provides a set of functions needed to drive the M29W128FL, 
+  *             M29W128GL and S29GL128P NOR memories mounted on STM32L152D-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_FSMC_NOR_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_FSMC_NOR_Private_Defines
+  * @{
+  */ 
+/** 
+  * @brief  FSMC Bank 1 NOR/SRAM2  
+  */
+#define Bank1_NOR2_ADDR       ((uint32_t)0x64000000)
+
+/* Delay definition */   
+#define BlockErase_Timeout    ((uint32_t)0x00A00000)
+#define ChipErase_Timeout     ((uint32_t)0x30000000) 
+#define Program_Timeout       ((uint32_t)0x00001400)     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_FSMC_NOR_Private_Macros
+  * @{
+  */
+#define ADDR_SHIFT(A) (Bank1_NOR2_ADDR + (2 * (A)))
+#define NOR_WRITE(Address, Data)  (*(__IO uint16_t *)(Address) = (Data))  
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32L152D_EVAL_FSMC_NOR_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroupSTM32L152D_EVAL_FSMC_NOR_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_FSMC_NOR_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the FSMC and GPIOs to interface with the NOR memory.
+  *         This function must be called before any write/read operation
+  *         on the NOR.
+  * @param  None
+  * @retval None
+  */
+void NOR_Init(void)
+{
+  FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+  FSMC_NORSRAMTimingInitTypeDef  p;
+    
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOF |
+                         RCC_AHBPeriph_GPIOG, ENABLE);
+
+/*-- GPIO Configuration ------------------------------------------------------*/
+  /*!< NOR Data lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
+                                GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC);
+
+  /*!< NOR Address lines configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
+                                GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);  
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FSMC);	   
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource2, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource3, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource4, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource5, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource13, GPIO_AF_FSMC);          
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource14, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource15, GPIO_AF_FSMC);          
+    
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | 
+                                GPIO_Pin_4 | GPIO_Pin_5;                               
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource0, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource1, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource2, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource3, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource4, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource5, GPIO_AF_FSMC);          
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; 
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_FSMC);
+   
+  /*!< NOE and NWE configuration */  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 |GPIO_Pin_5;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);
+    
+  /*!< NE2 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource9, GPIO_AF_FSMC);  
+  
+  /*!< NBL0, NBL1 configuration */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6; 
+  GPIO_Init(GPIOE, &GPIO_InitStructure); 
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource3, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource4, GPIO_AF_FSMC); 
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource5, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource6, GPIO_AF_FSMC); 
+
+  /*!< Configure PD6 for NOR memory Ready/Busy signal */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC);  
+  
+  /*-- FSMC Configuration ----------------------------------------------------*/
+  p.FSMC_AddressSetupTime = 0x02;
+  p.FSMC_AddressHoldTime = 0x00;
+  p.FSMC_DataSetupTime = 0x05;
+  p.FSMC_BusTurnAroundDuration = 0x00;
+  p.FSMC_CLKDivision = 0x00;
+  p.FSMC_DataLatency = 0x00;
+  p.FSMC_AccessMode = FSMC_AccessMode_B;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+  /*!< Enable FSMC Bank1_NOR Bank */
+  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
+}
+
+/**
+  * @brief  Reads NOR memory's Manufacturer and Device Code.
+  * @param  NOR_ID: pointer to a NOR_IDTypeDef structure which will hold the 
+  *         Manufacturer and Device Code.  
+  * @retval None
+  */
+void NOR_ReadID(NOR_IDTypeDef* NOR_ID)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0090);
+
+  NOR_ID->Manufacturer_Code = *(__IO uint16_t *) ADDR_SHIFT(0x0000);
+  NOR_ID->Device_Code1 = *(__IO uint16_t *) ADDR_SHIFT(0x0001);
+  NOR_ID->Device_Code2 = *(__IO uint16_t *) ADDR_SHIFT(0x000E);
+  NOR_ID->Device_Code3 = *(__IO uint16_t *) ADDR_SHIFT(0x000F);
+}
+
+/**
+  * @brief  Erases the specified Nor memory block.
+  * @param  BlockAddr: address of the block to erase.
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_EraseBlock(uint32_t BlockAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + BlockAddr), 0x30);
+
+  return (NOR_GetStatus(BlockErase_Timeout));
+}
+
+/**
+  * @brief  Erases the entire chip.
+  * @param  None                      
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_EraseChip(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0080);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x0010);
+
+  return (NOR_GetStatus(ChipErase_Timeout));
+}
+
+/**
+  * @brief  Writes a half-word to the NOR memory.
+  * @param  WriteAddr: NOR memory internal address to write to.
+  * @param  Data: Data to write. 
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_WriteHalfWord(uint32_t WriteAddr, uint16_t Data)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00A0);
+  NOR_WRITE((Bank1_NOR2_ADDR + WriteAddr), Data);
+
+  return (NOR_GetStatus(Program_Timeout));
+}
+
+/**
+  * @brief  Writes a half-word buffer to the FSMC NOR memory. 
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: NOR memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of Half words to write. 
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  NOR_Status status = NOR_ONGOING; 
+
+  do
+  {
+    /*!< Transfer data to the memory */
+    status = NOR_WriteHalfWord(WriteAddr, *pBuffer++);
+    WriteAddr = WriteAddr + 2;
+    NumHalfwordToWrite--;
+  }
+  while((status == NOR_SUCCESS) && (NumHalfwordToWrite != 0));
+  
+  return (status); 
+}
+
+/**
+  * @brief  Writes a half-word buffer to the FSMC NOR memory. This function 
+  *         must be used only with S29GL128P NOR memory.
+  * @param  pBuffer: pointer to buffer. 
+  * @param  WriteAddr: NOR memory internal address from which the data will be 
+  *         written.
+  * @param  NumHalfwordToWrite: number of Half words to write.
+  *         The maximum allowed value is 32 Half words (64 bytes).
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_ProgramBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
+{
+  uint32_t lastloadedaddress = 0x00;
+  uint32_t currentaddress = 0x00;
+  uint32_t endaddress = 0x00;
+
+  /*!< Initialize variables */
+  currentaddress = WriteAddr;
+  endaddress = WriteAddr + NumHalfwordToWrite - 1;
+  lastloadedaddress = WriteAddr;
+
+  /*!< Issue unlock command sequence */
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA);
+
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);  
+
+  /*!< Write Write Buffer Load Command */
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), 0x0025);
+  NOR_WRITE(ADDR_SHIFT(WriteAddr), (NumHalfwordToWrite - 1));
+
+  /*!< Load Data into NOR Buffer */
+  while(currentaddress <= endaddress)
+  {
+    /*!< Store last loaded address & data value (for polling) */
+    lastloadedaddress = currentaddress;
+ 
+    NOR_WRITE(ADDR_SHIFT(currentaddress), *pBuffer++);
+    currentaddress += 1; 
+  }
+
+  NOR_WRITE(ADDR_SHIFT(lastloadedaddress), 0x29);
+  
+  return(NOR_GetStatus(Program_Timeout));
+}
+
+/**
+  * @brief  Reads a half-word from the NOR memory. 
+  * @param  ReadAddr: NOR memory internal address to read from.
+  * @retval Half-word read from the NOR memory
+  */
+uint16_t NOR_ReadHalfWord(uint32_t ReadAddr)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055);  
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0 );
+
+  return (*(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr)));
+}
+
+/**
+  * @brief  Reads a block of data from the FSMC NOR memory.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *         NOR memory.
+  * @param  ReadAddr: NOR memory internal address to read from.
+  * @param  NumHalfwordToRead : number of Half word to read.
+  * @retval None
+  */
+void NOR_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHalfwordToRead)
+{
+  NOR_WRITE(ADDR_SHIFT(0x0555), 0x00AA);
+  NOR_WRITE(ADDR_SHIFT(0x02AA), 0x0055);
+  NOR_WRITE((Bank1_NOR2_ADDR + ReadAddr), 0x00F0);
+
+  for(; NumHalfwordToRead != 0x00; NumHalfwordToRead--) /*!< while there is data to read */
+  {
+    /*!< Read a Halfword from the NOR */
+    *pBuffer++ = *(__IO uint16_t *)((Bank1_NOR2_ADDR + ReadAddr));
+    ReadAddr = ReadAddr + 2; 
+  }  
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode.
+  * @param  None
+  * @retval NOR_SUCCESS
+  */
+NOR_Status NOR_ReturnToReadMode(void)
+{
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0);
+
+  return (NOR_SUCCESS);
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode and resets the errors in the NOR 
+  *         memory Status Register.  
+  * @param  None
+  * @retval NOR_SUCCESS
+  */
+NOR_Status NOR_Reset(void)
+{
+  NOR_WRITE(ADDR_SHIFT(0x00555), 0x00AA); 
+  NOR_WRITE(ADDR_SHIFT(0x002AA), 0x0055); 
+  NOR_WRITE(Bank1_NOR2_ADDR, 0x00F0); 
+
+  return (NOR_SUCCESS);
+}
+
+/**
+  * @brief  Returns the NOR operation status.
+  * @param  Timeout: NOR progamming Timeout
+  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
+  *         or NOR_TIMEOUT
+  */
+NOR_Status NOR_GetStatus(uint32_t Timeout)
+{ 
+  uint16_t val1 = 0x00, val2 = 0x00;
+  NOR_Status status = NOR_ONGOING; 
+  uint32_t timeout = Timeout;
+
+  /*!< Poll on NOR memory Ready/Busy signal ----------------------------------*/
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) != RESET) && (timeout > 0)) 
+  {
+    timeout--;
+  }
+
+  timeout = Timeout;
+  
+  while((GPIO_ReadInputDataBit(GPIOD, GPIO_Pin_6) == RESET) && (timeout > 0))   
+  {
+    timeout--;
+  }
+  
+  /*!< Get the NOR memory operation status -----------------------------------*/
+  while((Timeout != 0x00) && (status != NOR_SUCCESS))
+  {
+    Timeout--;
+
+    /*!< Read DQ6 and DQ5 */
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+
+    /*!< If DQ6 did not toggle between the two reads then return NOR_Success */
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+
+    if((val1 & 0x0020) != 0x0020)
+    {
+      status = NOR_ONGOING;
+    }
+
+    val1 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    val2 = *(__IO uint16_t *)(Bank1_NOR2_ADDR);
+    
+    if((val1 & 0x0040) == (val2 & 0x0040)) 
+    {
+      return NOR_SUCCESS;
+    }
+    else if((val1 & 0x0020) == 0x0020)
+    {
+      return NOR_ERROR;
+    }
+  }
+
+  if(Timeout == 0x00)
+  {
+    status = NOR_TIMEOUT;
+  } 
+
+  /*!< Return the operation status */
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.c
new file mode 100644
index 0000000..08dae7e
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.c
@@ -0,0 +1,3479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_glass_lcd.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file includes the LCD Glass driver for LCD XHO5002B Module of 
+  *          STM32L152D-EVAL board.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval_glass_lcd.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @defgroup STM32L152D_EVAL_GLASS_LCD 
+  * @brief This file includes the LCD Glass driver for LCD_XHO5002B Module of 
+  *        STM32L152D-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */   
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Private_Variables
+  * @{
+  */ 
+
+/**
+  @verbatim
+================================================================================
+                              GLASS LCD MAPPING
+================================================================================
+               A
+       _  ----------
+     P|_| |\   |H  /|
+         F| G  |  I |B
+          |  \ | /  |
+          --M-- --N--
+          |   /| \  |
+         E|  L |  J |C
+       _  | /  |K  \|
+     Q|_| -----------
+              D
+
+A LCD character coding is based on the following matrix:
+             COM0    COM1    COM4    COM5     COM6    COM7
+  SEG(n)    { 0 ,     0 ,     I ,     B ,      C ,     J }
+  SEG(n+1)  { D ,     K ,     A ,     H ,      M ,     N }
+  SEG(n+2)  { Q ,     L ,     G ,     F ,      P ,     E }
+
+The character A for example is:
+-----------------------------------------------------------
+             COM0    COM1     COM4    COM5    COM6     COM7
+  SEG(n)    { 0 ,     0 ,      0 ,     1 ,     1 ,      0 }
+  SEG(n+1)  { 0 ,     0 ,      1 ,     0 ,     1 ,      1 }
+  SEG(n+2)  { 0 ,     0 ,      0 ,     1 ,     0 ,      1 }
+   --------------------------------------------------------
+           =  0       0        2       5       3        6 hex
+
+   => 'A' = 0x002536
+
+  @endverbatim
+  */
+
+/**
+  * @brief LETTERS AND NUMBERS MAPPING DEFINITION
+  */
+uint16_t i;
+__I uint32_t Mask[] =
+  {
+    0x00F00000, 0x000F0000, 0x0000F000, 0x00000F00, 0x000000F0, 0x0000000F
+  };
+const uint8_t Shift[6] =
+  {
+    20, 16, 12, 8, 4, 0
+  };
+
+uint32_t Digit[6];     /* Digit frame buffer */
+
+/* Letters and number map of the custom LCD 8x40(STM8L152D-EVAL evaluation board) */
+__I uint32_t LetterMap[26] =
+  {
+    /*  A            B          C           D           E            F   */
+    0x00002536, 0x00202536, 0x00202404, 0x00222310, 0x00202426, 0x00002426, 
+    /*   G            H          I            J           K         L    */ 
+    0x00202416, 0x00000536, 0x00222200, 0x00200114, 0x00001425, 0x00200404,
+    /*   M          N           O            P          Q         R      */ 
+    0x00005514, 0x00004515, 0x00202514, 0x00002526, 0x00002532, 0x00002527,
+    /*   S           T           U           V           W           X   */
+    0x00202432, 0x00022200, 0x00200514, 0x00041404, 0x00050515, 0x00045001, 
+    /*  Y          Z     */
+    0x00025000, 0x00243000
+  };
+
+__I uint32_t NumberMap[10] =
+  {
+    /*   0           1           2          3           4   */
+    0x00202514, 0x00000110, 0x00202126, 0x00202132, 0x00000532,
+    /*    5         6            7          8           9   */
+    0x00202432, 0x00202436, 0x00002110, 0x00202536, 0x00202532
+  };
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32L152D_EVAL_LCD_Private_Function_Prototypes
+  * @{
+  */
+static void Convert(uint8_t* c, Point_Typedef Point, DoublePoint_Typedef DoublePoint);
+static void delay(__IO uint32_t nCount);
+static void LCD_GPIOConfig(void);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_LCD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
+  * @param  None 
+  * @retval None
+  */
+void LCD_GLASS_Init(void)
+{
+  LCD_InitTypeDef LCD_InitStructure;
+
+  LCD_GPIOConfig(); /*!< Configure the LCD Glass GPIO pins */
+
+  /*!< Configure the LCD interface -------------------------------------------*/
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE); /*!< Enable LCD APB1 Clock */
+
+  LCD_InitStructure.LCD_Prescaler = LCD_Prescaler_4;
+  LCD_InitStructure.LCD_Divider = LCD_Divider_16;
+  LCD_InitStructure.LCD_Duty = LCD_Duty_1_8;
+  LCD_InitStructure.LCD_Bias = LCD_Bias_1_4;
+  LCD_InitStructure.LCD_VoltageSource = LCD_VoltageSource_Internal;
+  LCD_Init(&LCD_InitStructure);
+
+  /*!< Configure the Pulse On Duration */
+  LCD_PulseOnDurationConfig(LCD_PulseOnDuration_2);
+
+  /*!< Configure the LCD Contrast (3.51V) */
+  LCD_ContrastConfig(LCD_Contrast_Level_7);
+
+  /*!< Wait Until the LCD FCR register is synchronized */
+  LCD_WaitForSynchro();
+
+  /*!< Enable LCD peripheral */
+  LCD_Cmd(ENABLE);
+
+  /*!< Wait Until the LCD is enabled */
+  while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)
+  {
+  }
+  /*!< Wait Until the LCD Booster is ready */  
+  while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)
+  {
+  }
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ch: The character to display.
+  * @param  point: A point to add in front of char.
+  *          This parameter  can be one of the following values:
+  *              @arg POINT_OFF : No point to add in front of char.
+  *              @arg POINT_ON : Add a point in front of char.
+  * @param  apostrophe: Flag indicating if a apostrophe has to be add in front 
+  *                     of displayed character.
+  *          This parameter  can be one of the following values:
+  *              @arg APOSTROPHE_OFF : No apostrophe to add in back of char.
+  *              @arg APOSTROPHE_ON : Add an apostrophe in back of char.
+  * @param  position: Position in the LCD of the caracter to write.
+  *          This parameter can be any value in range [0:7].
+  * @retval None
+  */
+void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, DoublePoint_Typedef DoublePoint, uint8_t position)
+{
+  Convert(ch, point, DoublePoint);
+
+  switch (position)
+  {
+    /* Position 0 on LCD */
+    case 0: 
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFBFF;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x09);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFF3FF;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x09);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFF1FF;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x09);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFF1FF;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x09);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFF9FF;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x09);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFF1FF;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x09);
+      break;
+
+    /* Position 1 on LCD */
+    case 1:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFF9FFF;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x0C);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFF9FFF;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x0C);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x0C);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x0C);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x0C);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x0C);
+      break;
+
+    /* Position 2 on LCD */
+    case 2:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFCFFFF;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x0F);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFCFFFF;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x0F);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x0F);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x0F);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x0F);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x0F);
+      break;
+
+    /* Position 3 on LCD */
+    case 3:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFE7FFFF;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x12);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFE7FFFF;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x12);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x12);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x12);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x12);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x12);
+      break;
+
+    /* Position 4 on LCD */
+    case 4:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF9;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] );
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF9;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1]);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2]);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3]);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4]);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5]);
+      break;
+
+      /* Position 5 on LCD */
+    case 5:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFCF;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x03);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFCF;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x03);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x03);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x03);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x03);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x03);
+      break;
+
+    /* Position 6 on LCD */
+    case 6:
+      /* Write Digit 0 on COM0 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFE7F;
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(Digit[0] << (uint32_t)0x06);
+      /* Write Digit 1 on COM1 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFE7F;
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(Digit[1] << (uint32_t)0x06);
+      /* Write Digit 2 on COM4 */
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)(Digit[2] << (uint32_t)0x06);
+      /* Write Digit 3 on COM5 */
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)(Digit[3] << (uint32_t)0x06);
+      /* Write Digit 4 on COM6 */
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)(Digit[4] << (uint32_t)0x06);
+      /* Write Digit 5 on COM7 */
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)(Digit[5] << (uint32_t)0x06);
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief This function Clear a char in the LCD RAM.
+  * @param position: Position in the LCD of the caracter to write.
+  *                  This parameter can be any value in range [0:7].
+  * @retval None
+  */
+void LCD_GLASS_ClearChar(uint8_t position)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+  switch (position)
+  {
+    /* Clear position 0 on LCD */
+    case 0:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFBFF;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFF3FF;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFF1FF;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFF1FF;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFF9FF;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFF1FF;
+      break;
+
+    /* Clear position 1 on LCD */
+    case 1:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFF9FFF;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFF9FFF;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFF8FFF;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFF8FFF;
+      break;
+
+    /* Clear position 2 on LCD */
+    case 2:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFCFFFF;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFCFFFF;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFC7FFF;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFC7FFF;
+      break;
+
+    /* Clear position 3 on LCD */
+    case 3:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFE7FFFF;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFE7FFFF;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFE3FFFF;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFE3FFFF;
+      break;
+
+    /* Clear position 4 on LCD */
+    case 4:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF9;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF9;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFFF8;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFFF8;
+      break;
+
+    /* Clear position 5 on LCD */
+    case 5:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFCF;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFCF;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFFC7;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFFC7;
+      break;
+
+    /* Clear position 6 on LCD */
+    case 6:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFE7F;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFE7F;
+      LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFFE3F;
+      LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFFFFE3F;
+      break;
+
+    default:
+      break;
+  }
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ch: The character to display.
+  * @param  point: A point to add in front of char.
+  *          This parameter  can be one of the following values:  
+  *              @arg POINT_OFF: No point to add in front of char.
+  *              @arg POINT_ON: Add a point in front of char.
+  * @param  apostrophe: Flag indicating if a apostrophe has to be add in front 
+  *                     of displayed character.
+  *          This parameter  can be one of the following values:
+  *              @arg APOSTROPHE_OFF: No apostrophe to add in back of char.
+  *              @arg APOSTROPHE_ON: Add an apostrophe in back of char.
+  * @param  position: Position in the LCD of the caracter to write.
+  *                   This parameter can be any value in range [0:7].
+  * @retval None
+  */
+void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, DoublePoint_Typedef DoublePoint, uint8_t position)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+  /*!< LCD Write Char */
+  LCD_GLASS_WriteChar(ch, point, DoublePoint, position);
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ptr: Pointer to string to display on the LCD Glass.
+  * @retval None
+  */
+void LCD_GLASS_DisplayString(uint8_t* ptr)
+{
+  uint8_t i = 0x00;
+
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  /*!< Send the string character by character on lCD */
+  while ((*ptr != 0) & (i < 8))
+  {
+    /*!< Display one character on LCD */
+    LCD_GLASS_WriteChar(ptr, POINT_OFF, DOUBLEPOINT_OFF, i);
+    /*!< Point on the next character */
+    ptr++;
+    /*!< Increment the character counter */
+    i++;
+  }
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Display a string in scrolling mode
+  * @note   The LCD should be cleared before to start the write operation.  
+  * @param  ptr: Pointer to string to display on the LCD Glass.
+  * @param  nScroll: Specifies how many time the message will be scrolled
+  * @param  ScrollSpeed: Specifies the speed of the scroll.
+  *                     Low value gives higher speed. 
+  * @retval None
+  */
+void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)
+{
+  uint8_t Repetition = 0;
+  uint8_t* ptr1;
+  uint8_t str[8] = "";
+  ptr1 = ptr;
+
+  LCD_GLASS_DisplayString(ptr1);
+
+  delay(ScrollSpeed);
+
+  for (Repetition = 0; Repetition < nScroll; Repetition++)
+  {
+    *(str + 1) = *ptr1;
+    *(str + 2) = *(ptr1 + 1);
+    *(str + 3) = *(ptr1 + 2);
+    *(str + 4) = *(ptr1 + 3);
+    *(str + 5) = *(ptr1 + 4);
+    *(str + 6) = *(ptr1 + 5);
+    *(str + 7) =*(ptr1 + 6);
+    *(str) = *(ptr1 + 7);    
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 7);
+    *(str + 2) = *ptr1;
+    *(str + 3) = *(ptr1 + 1);
+    *(str + 4) = *(ptr1 + 2);
+    *(str + 5) = *(ptr1 + 3);
+    *(str + 6) = *(ptr1 + 4);
+    *(str + 7) = *(ptr1 + 5);
+    *(str) = *(ptr1 + 6);    
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 6);
+    *(str + 2) = *(ptr1 + 7);
+    *(str + 3) = *ptr1;
+    *(str + 4) = *(ptr1 + 1);
+    *(str + 5) = *(ptr1 + 2);
+    *(str + 6) = *(ptr1 + 3);
+    *(str + 7) = *(ptr1 + 4);
+    *(str) = *(ptr1 + 5);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 5);
+    *(str + 2) = *(ptr1 + 6);
+    *(str + 3) = *(ptr1 + 7);
+    *(str + 4) = *ptr1;
+    *(str + 5) = *(ptr1 + 1);
+    *(str + 6) = *(ptr1 + 2);
+    *(str + 7) = *(ptr1 + 3);
+    *(str) = *(ptr1 + 4);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 4);
+    *(str + 2) = *(ptr1 + 5);
+    *(str + 3) = *(ptr1 + 6);
+    *(str + 4) = *(ptr1 + 7);
+    *(str + 5) = *ptr1;
+    *(str + 6) = *(ptr1 + 1);
+    *(str + 7) = *(ptr1 + 2);
+    *(str) = *(ptr1 + 3);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 3);
+    *(str + 2) = *(ptr1 + 4);
+    *(str + 3) = *(ptr1 + 5);
+    *(str + 4) = *(ptr1 + 6);
+    *(str + 5) = *(ptr1 + 7);
+    *(str + 6) = *ptr1;
+    *(str + 7) = *(ptr1 + 1);
+    *(str) = *(ptr1 + 2);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 2);
+    *(str + 2) = *(ptr1 + 3);
+    *(str + 3) = *(ptr1 + 4);
+    *(str + 4) = *(ptr1 + 5);
+    *(str + 5) = *(ptr1 + 6);
+    *(str + 6) = *(ptr1 + 7);
+    *(str + 7) = *ptr1;
+    *(str) = *(ptr1 + 1);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 1);
+    *(str + 2) = *(ptr1 + 2);
+    *(str + 3) = *(ptr1 + 3);
+    *(str + 4) = *(ptr1 + 4);
+    *(str + 5) = *(ptr1 + 5);
+    *(str + 6) = *(ptr1 + 6);
+    *(str + 7) = *(ptr1 + 7);
+    *(str) = *(ptr1);
+    LCD_GLASS_ClearTextZone();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+  }
+}
+
+/**
+  * @brief  This function Clears the LCD Glass Text Zone.
+  * @param  None
+  * @retval None
+  */
+void LCD_GLASS_ClearTextZone(void)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFE49A49;
+  LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFE49249;
+  LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFE00000;
+  LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFE00000;
+  LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFE00800;
+  LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFE00000;
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  This function Clear the whole LCD RAM.
+  * @param  None 
+  * @retval None
+  */
+void LCD_GLASS_Clear(void)
+{
+  uint32_t counter = 0;
+
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  for (counter = 0; counter <= 0x0F; counter++)
+  {
+    LCD->RAM[counter] = (uint32_t)0x00;
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure ST Logo display.
+  * @param  NewState: enable or disable the logo display .
+  * @retval None
+  */
+void LCD_GLASS_DisplayLogo(FunctionalState NewState)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  if (NewState != DISABLE)
+  {
+    /* Set logo on  */
+    LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000040;
+  }
+  else
+  {
+    /* Set logo of  */
+    LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFBF;
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure the LCD Battery Level.
+  * @param  BatteryLevel: Specify the Battery Level to set.
+  * @retval None
+  */
+void LCD_GLASS_BatteryLevelConfig(BatteryLevel_TypeDef BatteryLevel)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (BatteryLevel)
+  {
+    /* BATTERYLEVEL 1/4 */
+    case BATTERYLEVEL_1_4:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF6;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF6;
+      /* Set BATTERYLEVEL_1_4  on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000001;
+      break;
+
+    /* BATTERYLEVEL 1/2 */
+    case BATTERYLEVEL_1_2:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF6;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF6;
+      /* Set BatteryLevel_1_4 on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000001;
+      /* Set BatteryLevel_1_2 on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000001;
+      break;
+
+    /* Battery Level 3/4 */
+    case BATTERYLEVEL_3_4:
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF6;
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF6;
+      /* Set BATTERYLEVEL_3_4 on  */
+      /* Set BatteryLevel_1_4 on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000001;
+      /* Set BatteryLevel_1_2 on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000009;
+      break;
+
+    /* BATTERYLEVEL_FULL */
+    case BATTERYLEVEL_FULL:
+      /* Set BATTERYLEVEL_3_4 on  */
+      /* Set BatteryLevel_1_4 on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000009;
+      /* Set BATTERYLEVEL_FULL on  */
+      /* Set BatteryLevel_1_2 on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000009;
+      break;
+
+    case BATTERYLEVEL_OFF:
+      /* Set BATTERYLEVEL_3_4 off  */
+      /* Set BATTERYLEVEL_1_4 off  */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFFF6;
+      /* Set BATTERYLEVEL_1_2 off  */
+      /* Set BATTERYLEVEL_FULL off  */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFFF6;
+      break;
+
+    default:
+      break;
+  }
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure the LCD ArrowDirection.
+  * @param  Arrow: Specify the ArrowDirection to set.
+  * @retval None
+  */
+void LCD_GLASS_ArrowConfig(ArrowDirection_TypeDef ArrowDirection)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (ArrowDirection)
+  {
+    /* ARROWDIRECTION_UP */
+    case ARROWDIRECTION_UP:
+      /* Set ARROWDIRECTION_UP on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00001000;
+      break;
+
+    /* ARROWDIRECTION_LEFT */
+    case ARROWDIRECTION_LEFT :
+      /* Set ARROWDIRECTION_LEFT on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00001000;
+      break;
+
+    /* ARROWDIRECTION_DOWN */
+    case ARROWDIRECTION_DOWN:
+      /* Set ARROWDIRECTION_DOWN on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00008000;
+      break;
+
+    /* ARROWDIRECTION_RIGHT */
+    case ARROWDIRECTION_RIGHT:
+      /* Set ARROWDIRECTION_RIGHT on  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00008000;
+      break;
+
+    case ARROWDIRECTION_OFF:
+      /* Set ARROWDIRECTION_UP off  */
+      /* Set ARROWDIRECTION_RIGHT off  */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFF6FFF;
+      /* Set ARROWDIRECTION_LEFT off  */
+      /* Set ARROWDIRECTION_DOWN off  */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFF6FFF;
+      break;
+
+    default:
+      break;
+  }
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure the LCD Temperature level display .
+  * @param  Temperature: indicate the Temperature level to set.
+  * @retval None
+  */
+void LCD_GLASS_TemperatureConfig(TemperatureLevel_TypeDef Temperature)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (Temperature)
+  {
+    /* Temperature level 1*/
+    case TEMPERATURELEVEL_1 :
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1*/
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      break;
+
+    /* Temperature level 2 */
+    case TEMPERATURELEVEL_2:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1 */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      /* Set Temperature level 2 */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000200;
+      break;
+
+      /* Temperature level 3 */
+    case TEMPERATURELEVEL_3:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1 */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      /* Set Temperature level 2 */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000200;
+      /* Set Temperature level 3 */
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000400;
+      break;
+
+      /* Temperature level 4*/
+    case TEMPERATURELEVEL_4:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      /* Set Temperature level 2  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000200;
+      /* Set Temperature level 3 */
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000400;
+      /* Set Temperature level 4 */
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000400;
+      break;
+
+      /* Temperature_2*/
+    case TEMPERATURELEVEL_5:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1 */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      /* Set Temperature level 2 */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000200;
+      /* Set Temperature level 3 and level 5 */
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000C00;
+      /* Set Temperature level 4 */
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000400;
+      break;
+
+      /* Temperature_6*/
+    case  TEMPERATURELEVEL_6:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      /* Set Temperature level 1 */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000200;
+      /* Set Temperature level 2 */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000200;
+      /* Set Temperature level 3 and level 5 */
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000C00;
+      /* Set Temperature level 4 and level 6 */
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000C00;
+      break;
+
+    case TEMPERATURELEVEL_OFF:
+      /* Clear Temperature level 5 */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 6 */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFFFDFF;
+      /* Clear Temperature level 4 and level 2 */
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFF3FF;
+      /* Clear Temperature level 1 and level 3 */
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFF3FF;
+      break;
+
+    default:
+      break;
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure the LCD Value Unit.
+  * @param  ValueUnit: indicate the Value Unit to set.
+  * @param  NewState: enable or disable the Digit.
+  * @retval None
+  */
+void LCD_GLASS_ValueUnitConfig(ValueUnit_TypeDef ValueUnit)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (ValueUnit)
+  {
+    /* VALUEUNIT MILLIAMPERE*/
+    case VALUEUNIT_MILLIAMPERE:
+      /* Set VALUEUNIT_MILLIAMPERE on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00040000;
+      break;
+
+    /* VALUEUNIT MICROAMPERE)*/
+    case VALUEUNIT_MICROAMPERE:
+      /* Set VALUEUNIT_MICROAMPERE  */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00040000;
+      break;
+
+    /* VALUEUNIT NANOAMPERE*/
+    case  VALUEUNIT_NANOAMPERE:
+      /* Set VALUEUNIT_NANOAMPERE on  */
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00000040;
+      break;
+
+    case  VALUEUNIT_OFF:
+      /* Set VALUEUNIT_MILLIAMPERE and VALUEUNIT_NANOAMPERE OFF */
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFFBFFBF;
+      /* Set VALUEUNIT_MICROAMPERE off  */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFBFFFF;
+      break;
+
+    default:
+      break;
+  }
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Configure the LCD sign.
+  * @param  Sign: indicate the sign to set.
+  * @param  NewState: enable or disable the Digit.
+  * @retval None
+  */
+void LCD_GLASS_SignCmd(Sign_TypeDef Sign, FunctionalState NewState)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  if (NewState != DISABLE)
+  {
+    switch (Sign)
+    {
+      /* Sign positive */
+      case SIGN_POSITIVE:
+        /* Set SIGN_POSITIVE on */
+        LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x00000800;
+        break;
+
+      /* Sign negative*/
+      case SIGN_NEGATIVE:
+        /* Set SIGN_NEGATIVE on */
+        LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00000800;
+        break;
+
+      default:
+        break;
+    }
+  }
+  else
+  {
+    switch (Sign)
+    {
+      /* Sign positive */
+      case SIGN_POSITIVE:
+        /* Set SIGN_POSITIVE off */
+        LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFFFF7FF;
+        break;
+
+      /* Sign negative */
+      case SIGN_NEGATIVE:
+        /* Set SIGN_NEGATIVE off */
+        LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFFFF7FF;
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+/**
+  * @brief  Set Matrix Pixel on.
+  * @param  PixelRow: Specify Matrix Row.
+  * @param  PixelColumn: Specify Matrix Column.
+  * @retval None
+  */
+void LCD_GLASS_WriteMatrixPixel(PixelRow_TypeDef PixelRow, PixelColumn_TypeDef PixelColumn)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (PixelRow)
+  {
+    case PIXELROW_1:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 1 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000200;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 1 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00004000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 1 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00002000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 1 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00001000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 1 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00020000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 1 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00010000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 1 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00008000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 1 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00100000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 1 , Column = 9 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00080000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 1 , Column = 10 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00040000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 1 , Column = 11 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 1 , Column = 12 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 1 , Column = 13 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 1 , Column = 14 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 1 , Column = 15 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 1 , Column = 16 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 1 , Column = 17 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000100;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 1 , Column = 18 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000080;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 1 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00000040;
+          break;
+
+        default:
+          break;
+
+      }
+      break;
+
+    case PIXELROW_2:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 2 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000200;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 2 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00004000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 2 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00002000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 2 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00001000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 2 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00020000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 2 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00010000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 2 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00008000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 2 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00100000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 2 , Column = 9 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00080000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 2 , Column = 10 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00040000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 2 , Column = 11 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 2 , Column = 12 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 2 , Column = 13 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 2 , Column = 14 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 2 , Column = 15 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 2 , Column = 16 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 2 , Column = 17 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000100;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 2 , Column = 18 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000080;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 2 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00000040;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_3:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 3 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 3 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 3 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 3 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 3 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 3 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 3 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 3 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 3 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 3 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 3 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 3 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 3 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 3 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 3 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 3 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 3 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 3 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 3 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_4:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 4 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 4 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 4 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 4 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 4 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 4 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 4 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 4 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 4 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 4 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 4 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 4 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 4 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 4 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 4 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 4 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 4 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 4 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 4 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+
+      }
+      break;
+
+    case PIXELROW_5:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 5 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 5 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 5 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 5 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 5 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 5 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 5 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 5 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 5 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 5 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 5 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 5 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 5 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 5 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 5 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 5 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 5 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 5 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 5 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_6:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 6 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 6 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 6 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 6 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 6 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 6 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 6 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 6 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 6 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 6 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 6 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 6 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 6 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 6 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 6 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 6 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 6 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 6 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 6 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_7:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 7 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 7 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 7 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 7 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 7 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 7 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 7 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 7 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 7 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 7 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 7 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_14] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 7 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 7 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 7 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 7 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 7 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 7 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 7 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 7 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_15] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_8:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 8 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 8 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 8 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 8 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 8 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 8 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 8 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 8 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 8 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 8 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 8 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_12] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 8 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 8 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 8 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 8 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 8 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 8 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 8 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 8 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_13] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_9:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 9 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 9 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 9 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 9 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 9 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 9 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 9 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 9 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 9 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 9 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 9 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_10] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 9 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 9 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 9 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 9 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 9 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 9 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 9 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 9 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_11] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_10:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 10 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x00200000;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 10 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x00400000;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 10 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x00800000;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 10 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x01000000;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 10 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x02000000;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 10 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x04000000;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 10 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x08000000;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 10 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x10000000;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 10 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x20000000;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 10 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x40000000;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 10 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_8] |= (uint32_t)0x80000000;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 10 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000001;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 10 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000002;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 10 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000004;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 10 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000008;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 10 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000010;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 10 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000020;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 10 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000040;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 10 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_9] |= (uint32_t)0x00000080;
+          break;
+
+        default:
+          break;
+      }
+    break;
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Set Matrix Pixel off.
+  * @param  PixelRow: Specify Matrix Row.
+  * @param  PixelColumn: Specify Matrix Column.
+  * @retval None
+  */
+void LCD_GLASS_ClearMatrixPixel(PixelRow_TypeDef PixelRow, PixelColumn_TypeDef PixelColumn)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  switch (PixelRow)
+  {
+    case PIXELROW_1:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 1 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFDFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 1 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFBFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 1 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFDFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 1 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFEFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 1 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFDFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 1 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFEFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 1 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFF7FFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 1 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFEFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 1 , Column = 9 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFF7FFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 1 , Column = 10 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFBFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 1 , Column = 11 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 1 , Column = 12 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 1 , Column = 13 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 1 , Column = 14 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 1 , Column = 15 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 1 , Column = 16 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 1 , Column = 17 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFEFF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 1 , Column = 18 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 1 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_2:
+
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 2 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFDFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 2 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFBFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 2 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFDFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 2 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFEFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 2 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFDFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 2 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFEFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 2 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFF7FFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 2 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFEFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 2 , Column = 9 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFF7FFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 2 , Column = 10 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFBFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 2 , Column = 11 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 2 , Column = 12 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 2 , Column = 13 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 2 , Column = 14 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 2 , Column = 15 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 2 , Column = 16 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 2 , Column = 17 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFEFF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 2 , Column = 18 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 2 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_3:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 3 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 3 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 3 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 3 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 3 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 3 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 3 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 3 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 3 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 3 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 3 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 3 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 3 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 3 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 3 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 3 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 3 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 3 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 3 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_4:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 4 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 4 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 4 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 4 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 4 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 4 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 4 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 4 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 4 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 4 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 4 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 4 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 4 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 4 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 4 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 4 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 4 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 4 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 4 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_5:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 5 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 5 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 5 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 5 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 5 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 5 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 5 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 5 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 5 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 5 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 5 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 5 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 5 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 5 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 5 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 5 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 5 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 5 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 5 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_6:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 6 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 6 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 6 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 6 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 6 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 6 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 6 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 6 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 6 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 6 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 6 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 6 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 6 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 6 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 6 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 6 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 6 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 6 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 6 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_7:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 7 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 7 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 7 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 7 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 7 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 7 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 7 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 7 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 7 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 7 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 7 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_14] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 7 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 7 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 7 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 7 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 7 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 7 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 7 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 7 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_15] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_8:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 8 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 8 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 8 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 8 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFEFFFFF0;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 8 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 8 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xFBFFFFF0;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 8 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 8 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 8 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 8 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 8 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_12] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 8 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 8 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 8 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 8 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 8 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 8 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 8 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 8 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_13] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_9:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 9 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 9 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 9 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 9 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 9 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 9 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 9 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 9 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 9 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 9 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0xBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 9 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_10] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 9 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 9 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 9 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 9 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 9 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 9 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 9 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 9 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_11] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+      break;
+
+    case PIXELROW_10:
+      switch (PixelColumn)
+      {
+        case PIXELCOLUMN_1:
+          /* Position : Row = 10 , Column = 1 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFDFFFFF;
+          break;
+
+        case PIXELCOLUMN_2:
+          /* Position : Row = 10 , Column = 2 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFFBFFFFF;
+          break;
+
+        case PIXELCOLUMN_3:
+          /* Position : Row = 10 , Column = 3 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFF7FFFFF;
+          break;
+
+        case PIXELCOLUMN_4:
+          /* Position : Row = 10 , Column = 4 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFEFFFFFF;
+          break;
+
+        case PIXELCOLUMN_5:
+          /* Position : Row = 10 , Column = 5 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFDFFFFFF;
+          break;
+
+        case PIXELCOLUMN_6:
+          /* Position : Row = 10 , Column = 6 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xFBFFFFFF;
+          break;
+
+        case PIXELCOLUMN_7:
+          /* Position : Row = 10 , Column = 7 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xF7FFFFFF;
+          break;
+
+        case PIXELCOLUMN_8:
+          /* Position : Row = 10 , Column = 8 */
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xEFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_9:
+          /* Position : Row = 10 , Column = 9*/
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xDFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_10:
+          /* Position : Row = 10 , Column = 10*/
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0xBFFFFFFF;
+          break;
+
+        case PIXELCOLUMN_11:
+          /* Position : Row = 10 , Column = 11*/
+          LCD->RAM[LCD_RAMRegister_8] &= (uint32_t)0x7FFFFFFF;
+          break;
+
+        case PIXELCOLUMN_12:
+          /* Position : Row = 10 , Column = 12*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFFE;
+          break;
+
+        case PIXELCOLUMN_13:
+          /* Position : Row = 10 , Column = 13*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFFD;
+          break;
+
+        case PIXELCOLUMN_14:
+          /* Position : Row = 10 , Column = 14*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFFB;
+          break;
+
+        case PIXELCOLUMN_15:
+          /* Position : Row = 10 , Column = 15*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFF7;
+          break;
+
+        case PIXELCOLUMN_16:
+          /* Position : Row = 10 , Column = 16*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFEF;
+          break;
+
+        case PIXELCOLUMN_17:
+          /* Position : Row = 10 , Column = 17*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFDF;
+          break;
+
+        case PIXELCOLUMN_18:
+          /* Position : Row = 10 , Column = 18*/
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFFBF;
+          break;
+
+        case PIXELCOLUMN_19:
+          /* Position : Row = 10 , Column = 19 */
+          LCD->RAM[LCD_RAMRegister_9] &= (uint32_t)0xFFFFFF7F;
+          break;
+
+        default:
+          break;
+      }
+    break;
+  }
+
+  /*!< Request LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  Converts an ascii char to the a LCD Digit (previous coding).
+  * @param  c: a char to display.
+  * @param  Point: a point to add in front of a char
+  *         This parameter can be: POINT_OFF or POINT_ON
+  * @param  DoublePoint: flag indicating if Double Point has to be added in front
+  *         of the displayed character.
+  *         This parameter can be: DOUBLEPOINT_ON or DOUBLEPOINT_OFF.
+  * @retval None
+  */
+static void Convert(uint8_t* c, Point_Typedef Point, DoublePoint_Typedef DoublePoint)
+{
+  uint32_t ch = 0 , tmp = 0;
+  uint8_t i = 0;
+
+  /* The character c is a letter in upper case*/
+  if ((*c < (uint8_t)0x5B)&(*c > (uint8_t)0x40))
+  {
+    ch = LetterMap[*c-(uint8_t)0x41];
+  }
+  /* The character c is a number*/
+  if ((*c < (uint8_t)0x3A)&(*c > (uint8_t)0x2F))
+  {
+    ch = NumberMap[*c-(uint8_t)0x30];
+  }
+  /* The character c is a space character */
+  if (*c == (uint8_t)0x20)
+  {
+    ch = (uint32_t)0x00;
+  }
+  /* Set the Q pixel in the character that can be displayed if the point is on */
+  if (Point == POINT_ON)
+  {
+    ch |= (uint32_t)0x00400000;
+  }
+
+  /* Set the P pixel in the character that can be displayed if the double point is on */
+  if (DoublePoint == DOUBLEPOINT_ON)
+  {
+    ch |= (uint32_t)0x00000040;
+  }
+
+  for (i = 0;i < 6; i++)
+  {
+    tmp = ch & Mask[i];
+    Digit[i] = (uint8_t)(tmp >> (uint8_t)Shift[i]);
+  }
+}
+
+/**
+  * @brief  Configures the LCD Segments and Coms GPIOs.
+  * @param  None 
+  * @retval None
+  */
+static void LCD_GPIOConfig(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /*!< Enable GPIOA, GPIOB, GPIOC, GPIOD and GPIOE AHB Clocks */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC
+                        | RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE, ENABLE);
+
+  /*!< Connect PA.08 to LCD COM0 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PA.09 to LCD COM1 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PA.10 to LCD COM2 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PB.09 to LCD COM3 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PA.01 to LCD SEG0 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PA.02 to LCD SEG1 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PA.03 to LCD SEG2 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PA.06 to LCD SEG3 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_LCD);
+
+  /*!< Connect PA.07 to LCD SEG4 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_LCD);
+
+  /*!< Connect PB.00 to LCD SEG5 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PB.01 to LCD SEG6 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PB.03 to LCD SEG7 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PB.04 to LCD SEG8 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_LCD);
+
+  /*!< Connect PB.05 to LCD SEG9 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_LCD); 
+
+  /*!< Connect PB.10 to LCD SEG10 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PB.11 to LCD SEG11 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PB.12 to LCD SEG12 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_LCD);
+
+  /*!< Connect PB.13 to LCD SEG13 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_LCD);
+
+  /*!< Connect PB.14 to LCD SEG14 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_LCD);
+
+  /*!< Connect PB.15 to LCD SEG15 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_LCD);
+
+  /*!< Connect PB.8 to LCD SEG16 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PA15 to LCD SEG17 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_LCD);
+
+  /*!< Connect PC.00 to LCD SEG18 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PC.01 to LCD SEG19 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PC.02 to LCD SEG20 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PC.03 to LCD SEG21 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PC.04 to LCD SEG22 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_LCD);
+
+  /*!< Connect PC.05 to LCD SEG23 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_LCD);
+
+  /*!< Connect PC.06 to LCD SEG24 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource6, GPIO_AF_LCD);
+
+  /*!< Connect PC.07 to LCD SEG25 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource7, GPIO_AF_LCD);
+
+  /*!< Connect PC.08 to LCD SEG26 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PC.09 to LCD SEG27 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PD.08 to LCD SEG28 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PD.09 to LCD SEG29 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PD.10 to LCD SEG30 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PD.11 to LCD SEG31 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PD.12 to LCD SEG32 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_LCD);
+
+  /*!< Connect PD.13 to LCD SEG33 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_LCD);
+
+  /*!< Connect PD.14 to LCD SEG34 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_LCD);
+
+  /*!< Connect PD.15 to LCD SEG35 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_LCD);
+
+  /*!< Connect PE.00 to LCD SEG36 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PE.01 to LCD SEG37 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PE.02 to LCD SEG38 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PE.03 to LCD SEG39 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PC.10 to LCD SEG40 or LCD COM4 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PC.11 to LCD SEG41 or LCD COM5 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PC.12 to LCD SEG42 or LCD COM6 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_LCD);
+
+  /*!< Connect PD.02 to LCD SEG43 or LCD COM7 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_LCD);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | \
+                                GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \
+                                GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3 | GPIO_Pin_4 | \
+                                GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | \
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | \
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | \
+                                GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | \
+                                GPIO_Pin_12;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | \
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = (0xFF * nCount); index != 0; index--)
+  {
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.h
new file mode 100644
index 0000000..10c9e68
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_glass_lcd.h
@@ -0,0 +1,264 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_glass_lcd.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   Header file for stm32l152d_eval_glass_lcd.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152D_EVAL_GLASS_LCD_H
+#define __STM32L152D_EVAL_GLASS_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32L152D_EVAL_GLASS_LCD
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief LCD Glass point
+  * Warning: element values correspond to LCD Glass point.
+  */
+
+typedef enum
+{
+  POINT_OFF = 0,
+  POINT_ON = 1
+}Point_Typedef;
+
+/**
+  * @brief LCD Glass Double point
+  * Warning: element values correspond to LCD Glass Double point.
+  */
+typedef enum
+{
+  DOUBLEPOINT_OFF = 0,
+  DOUBLEPOINT_ON = 1
+}DoublePoint_Typedef;
+
+/**
+  * @brief LCD Glass Battery Level
+  * Warning: element values correspond to LCD Glass Battery Level.
+  */
+
+typedef enum
+{
+  BATTERYLEVEL_OFF  = 0,
+  BATTERYLEVEL_1_4  = 1,
+  BATTERYLEVEL_1_2  = 2,
+  BATTERYLEVEL_3_4  = 3,
+  BATTERYLEVEL_FULL = 4
+}BatteryLevel_TypeDef;
+
+/**
+  * @brief LCD Glass Temperature Level
+  * Warning: element values correspond to LCD Glass Temperature Level.
+  */
+
+typedef enum
+{
+  TEMPERATURELEVEL_OFF = 0,
+  TEMPERATURELEVEL_1   = 1,
+  TEMPERATURELEVEL_2   = 2,
+  TEMPERATURELEVEL_3   = 3,
+  TEMPERATURELEVEL_4   = 4,
+  TEMPERATURELEVEL_5   = 5,
+  TEMPERATURELEVEL_6   = 6
+}TemperatureLevel_TypeDef;
+
+/**
+  * @brief LCD Glass Arrow Direction
+  * Warning: element values correspond to LCD Glass Arrow Direction.
+  */
+
+typedef enum
+{
+  ARROWDIRECTION_OFF   = 0,
+  ARROWDIRECTION_UP    = 1,
+  ARROWDIRECTION_DOWN  = 2,
+  ARROWDIRECTION_LEFT  = 3,
+  ARROWDIRECTION_RIGHT = 4
+}ArrowDirection_TypeDef;
+
+/**
+  * @brief LCD Glass Value Unit
+  * Warning: element values correspond to LCD Glass Value Unit.
+  */
+typedef enum
+{
+  VALUEUNIT_OFF         = 0,
+  VALUEUNIT_MILLIAMPERE = 1,
+  VALUEUNIT_MICROAMPERE = 2,
+  VALUEUNIT_NANOAMPERE  = 3
+}ValueUnit_TypeDef;
+
+/**
+  * @brief LCD Glass Sign
+  * Warning: element values correspond to LCD Glass Sign.
+  */
+typedef enum
+{
+  SIGN_POSITIVE = 0,
+  SIGN_NEGATIVE = 1
+}Sign_TypeDef;
+
+/**
+  * @brief LCD Glass Pixel Row
+  * Warning: element values correspond to LCD Glass Pixel Row.
+  */
+typedef enum
+{
+  PIXELROW_1 = 1,
+  PIXELROW_2 = 2,
+  PIXELROW_3 = 3,
+  PIXELROW_4 = 4,
+  PIXELROW_5 = 5,
+  PIXELROW_6 = 6,
+  PIXELROW_7 = 7,
+  PIXELROW_8 = 8,
+  PIXELROW_9 = 9,
+  PIXELROW_10 = 10
+}PixelRow_TypeDef;
+
+/**
+  * @brief LCD Glass Pixel Column
+  * Warning: element values correspond to LCD Glass Pixel Column.
+  */
+typedef enum
+{
+  PIXELCOLUMN_1 = 1,
+  PIXELCOLUMN_2 = 2,
+  PIXELCOLUMN_3 = 3,
+  PIXELCOLUMN_4 = 4,
+  PIXELCOLUMN_5 = 5,
+  PIXELCOLUMN_6 = 6,
+  PIXELCOLUMN_7 = 7,
+  PIXELCOLUMN_8 = 8,
+  PIXELCOLUMN_9 = 9,
+  PIXELCOLUMN_10 = 10,
+  PIXELCOLUMN_11 = 11,
+  PIXELCOLUMN_12 = 12,
+  PIXELCOLUMN_13 = 13,
+  PIXELCOLUMN_14 = 14,
+  PIXELCOLUMN_15 = 15,
+  PIXELCOLUMN_16 = 16,
+  PIXELCOLUMN_17 = 17,
+  PIXELCOLUMN_18 = 18,
+  PIXELCOLUMN_19 = 19
+}PixelColumn_TypeDef;
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Exported_Constants
+  * @{
+  */ 
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_GLASS_LCD_Exported_Functions
+  * @{
+  */
+void LCD_GLASS_Init(void);
+void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, DoublePoint_Typedef DoublePoint,uint8_t position);
+void LCD_GLASS_DisplayString(uint8_t* ptr);
+void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, DoublePoint_Typedef DoublePoint,uint8_t position);
+void LCD_GLASS_ClearChar(uint8_t position);
+void LCD_GLASS_Clear(void);
+void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);
+
+void LCD_GLASS_ClearTextZone(void);
+void LCD_GLASS_DisplayLogo(FunctionalState NewState);
+void LCD_GLASS_BatteryLevelConfig(BatteryLevel_TypeDef BatteryLevel);
+void LCD_GLASS_ArrowConfig(ArrowDirection_TypeDef ArrowDirection);
+void LCD_GLASS_TemperatureConfig(TemperatureLevel_TypeDef TemperatureLevel);
+void LCD_GLASS_ValueUnitConfig(ValueUnit_TypeDef ValueUnit);
+void LCD_GLASS_SignCmd(Sign_TypeDef Sign, FunctionalState NewState);
+
+void LCD_GLASS_WriteMatrixPixel(PixelRow_TypeDef PixelRow, PixelColumn_TypeDef PixelColumn);
+void LCD_GLASS_ClearMatrixPixel(PixelRow_TypeDef PixelRow, PixelColumn_TypeDef PixelColumn);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152D_EVAL_GLASS_LCD_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+
+/**
+  * @}
+  */   
+
+/**
+  * @}
+  */   
+
+/**
+  * @}
+  */   
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_lcd.c
index fe2bfdf..eaf7823 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_lcd.c
@@ -1,28 +1,35 @@
 /**
   ******************************************************************************
-  * @file    stm32100e_eval_lcd.c
+  * @file    stm32l152d_eval_lcd.c
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H 
-  *          (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H 
-  *          (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file includes the LCD driver for AM-240320D4TOQW-T00H(R),
+  *          AM240320L8TNQW-00H(ILI9320), AM-240320LDTNQW-00H(SPFD5408B), 
+  *          AM240320LDTNQW04H00(ILI9325 or RM68050) and AM240320LGTNQW00H (HX8347-D)
+  *          Liquid Crystal Display Module of STM32L152D-EVAL board.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32100e_eval_lcd.h"
+#include "stm32l152d_eval_lcd.h"
 #include "../Common/fonts.c"
 
 /** @addtogroup Utilities
@@ -33,68 +40,76 @@
   * @{
   */ 
 
-/** @addtogroup STM32100E_EVAL
+/** @addtogroup STM32L152D_EVAL
   * @{
   */
-    
-/** @defgroup STM32100E_EVAL_LCD 
-  * @brief This file includes the LCD driver for AM-240320L8TNQW00H 
-  *        (LCD_ILI9320), AM240320D5TOQW01H (LCD_ILI9325) and AM-240320LDTNQW00H 
-  *        (LCD_SPFD5408B) Liquid Crystal Display Module of STM32100E-EVAL board.
+
+/** @defgroup STM32L152D_EVAL_LCD 
+  * @brief    This file includes the LCD driver for AM-240320D4TOQW-T00H(R),
+  *           AM240320L8TNQW-00H(ILI9320), AM-240320LDTNQW-00H(SPFD5408B), 
+  *           AM240320LDTNQW04H00(ILI9325 or RM68050) and AM240320LGTNQW00H (HX8347-D)
+  *           Liquid Crystal Display Module of STM32L152D-EVAL board.
   * @{
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Private_TypesDefinitions
+/** @defgroup STM32L152D_EVAL_LCD_Private_TypesDefinitions
   * @{
   */ 
 typedef struct
 {
-  __IO uint16_t LCD_REG;
-  __IO uint16_t LCD_RAM;
-} LCD_TypeDef;
+  __IO uint16_t LCD_REG_R; /* Read Register */
+  __IO uint16_t LCD_RAM_R; /* Read RAM */
+  __IO uint16_t LCD_REG_W; /* Write Register */
+  __IO uint16_t LCD_RAM_W; /* Write RAM */
+} TFT_LCD_TypeDef;
 /**
   * @}
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LCD_Private_Defines
+/** @defgroup STM32L152D_EVAL_LCD_Private_Defines
   * @{
   */
 /* Note: LCD /CS is CE4 - Bank 4 of NOR/SRAM Bank 1~4 */
-#define LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
-#define LCD                ((LCD_TypeDef *) LCD_BASE)
+#define TFT_LCD_BASE           ((uint32_t)(0x60000000 | 0x0C000000))
+#define TFT_LCD                ((TFT_LCD_TypeDef *) TFT_LCD_BASE)
 #define MAX_POLY_CORNERS   200
 #define POLY_Y(Z)          ((int32_t)((Points + Z)->X))
-#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))                                
+#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))
+#define LCD_ILI9325        0x9325
+#define LCD_ILI9320        0x9320
+#define LCD_SPFD5408       0x5408
+#define LCD_HX8347D        0x0047
 /**
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Private_Macros
+/** @defgroup STM32L152D_EVAL_LCD_Private_Macros
   * @{
   */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))    
+#define ABS(X)  ((X) > 0 ? (X) : -(X))
 /**
   * @}
   */ 
   
-/** @defgroup STM32100E_EVAL_LCD_Private_Variables
+/** @defgroup STM32L152D_EVAL_LCD_Private_Variables
   * @{
   */ 
 static sFONT *LCD_Currentfonts;
 /* Global variables to set the written text color */
 static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
-  
+static __IO uint16_t LCD_ID = 0;
+
 /**
   * @}
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LCD_Private_FunctionPrototypes
+/** @defgroup STM32L152D_EVAL_LCD_Private_FunctionPrototypes
   * @{
   */ 
 #ifndef USE_Delay
-static void delay(vu32 nCount);
+static void delay(__IO uint32_t nCount);
 #endif /* USE_Delay*/
 static void PutPixel(int16_t x, int16_t y);
 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
@@ -103,7 +118,7 @@ static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint1
   */ 
 
 
-/** @defgroup STM32100E_EVAL_LCD_Private_Functions
+/** @defgroup STM32L152D_EVAL_LCD_Private_Functions
   * @{
   */ 
 
@@ -112,7 +127,7 @@ static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint1
   * @param  None
   * @retval None
   */
-void LCD_DeInit(void)
+void STM32L152D_LCD_DeInit(void)
 { 
   GPIO_InitTypeDef GPIO_InitStructure;
 
@@ -124,26 +139,53 @@ void LCD_DeInit(void)
   
   /*!< LCD_SPI DeInit */
   FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
-   
+
+/*-- GPIO Configuration ------------------------------------------------------*/
   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
      PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
                                 GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
   GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_EVENTOUT);
+
   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
-     PE.14(D11), PE.15(D12) as alternate function push pull */
+     PE.14(D11), PE.15(D12) as input floating */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
                                 GPIO_Pin_15;
   GPIO_Init(GPIOE, &GPIO_InitStructure);
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
+
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_EVENTOUT);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_EVENTOUT);
+
+  /* Set PF.00(A0 (RS)) as input floating */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
   GPIO_Init(GPIOF, &GPIO_InitStructure);
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_EVENTOUT);
+
+  /* Set PG.12(NE4 (LCD/CS)) as input floating - NE4(LCD /CS) */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
-  GPIO_Init(GPIOG, &GPIO_InitStructure); 
+  GPIO_Init(GPIOG, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource12, GPIO_AF_EVENTOUT);
 }
 
 /**
@@ -151,22 +193,114 @@ void LCD_DeInit(void)
   * @param  None
   * @retval None
   */
-void STM32100E_LCD_Init(void)
-{ 
-  __IO uint32_t lcdid = 0;
-  
+void STM32L152D_LCD_Init(void)
+{
 /* Configure the LCD Control pins --------------------------------------------*/
   LCD_CtrlLinesConfig();
 /* Configure the FSMC Parallel interface -------------------------------------*/
   LCD_FSMCConfig();
   
-  _delay_(5); /* delay 50 ms */
-  
+  _delay_(5); /* Delay 50 ms */
+
   /* Read the LCD ID */
-  lcdid = LCD_ReadReg(0x00);
+  LCD_ID = LCD_ReadReg(0x00);
+  
+  /* Check if the LCD is HX8347D Controller */
+  if(LCD_ID == LCD_HX8347D)
+  {
+    /* Driving ability setting */
+    LCD_WriteReg(LCD_REG_234, 0x00);
+    LCD_WriteReg(LCD_REG_235, 0x20);
+    LCD_WriteReg(LCD_REG_236, 0x0C);
+    LCD_WriteReg(LCD_REG_237, 0xC4);
+    LCD_WriteReg(LCD_REG_232, 0x40);
+    LCD_WriteReg(LCD_REG_233, 0x38);
+    LCD_WriteReg(LCD_REG_241, 0x01); /* RGB 18-bit interface ;0x0110 */
+    LCD_WriteReg(LCD_REG_242, 0x10);
+    LCD_WriteReg(LCD_REG_39, 0xA3);
+
+    /* Adjust the Gamma Curve */
+    LCD_WriteReg(LCD_REG_64, 0x01);
+    LCD_WriteReg(LCD_REG_65, 0x00);
+    LCD_WriteReg(LCD_REG_66, 0x00);
+    LCD_WriteReg(LCD_REG_67, 0x10);
+    LCD_WriteReg(LCD_REG_68, 0x0E);
+    LCD_WriteReg(LCD_REG_69, 0x24);
+    LCD_WriteReg(LCD_REG_70, 0x04);
+    LCD_WriteReg(LCD_REG_71, 0x50);
+    LCD_WriteReg(LCD_REG_72, 0x02);
+    LCD_WriteReg(LCD_REG_73, 0x13);
+    LCD_WriteReg(LCD_REG_74, 0x19);
+    LCD_WriteReg(LCD_REG_75, 0x19);
+    LCD_WriteReg(LCD_REG_76, 0x16);
+
+    LCD_WriteReg(LCD_REG_80, 0x1B);
+    LCD_WriteReg(LCD_REG_81, 0x31);
+    LCD_WriteReg(LCD_REG_82, 0x2F);
+    LCD_WriteReg(LCD_REG_83, 0x3F);
+    LCD_WriteReg(LCD_REG_84, 0x3F);
+    LCD_WriteReg(LCD_REG_85, 0x3E);
+    LCD_WriteReg(LCD_REG_86, 0x2F);
+    LCD_WriteReg(LCD_REG_87, 0x7B);
+    LCD_WriteReg(LCD_REG_88, 0x09);
+    LCD_WriteReg(LCD_REG_89, 0x06);
+    LCD_WriteReg(LCD_REG_90, 0x06);
+    LCD_WriteReg(LCD_REG_91, 0x0C);
+    LCD_WriteReg(LCD_REG_92, 0x1D);
+    LCD_WriteReg(LCD_REG_93, 0xCC);
+
+    /* Power voltage setting */
+    LCD_WriteReg(LCD_REG_27, 0x1B);
+    LCD_WriteReg(LCD_REG_26, 0x01);
+    LCD_WriteReg(LCD_REG_36, 0x2F);
+    LCD_WriteReg(LCD_REG_37, 0x57);
+    /*****VCOM offset ****/
+    LCD_WriteReg(LCD_REG_35, 0x86);
   
+    /* Power on setting */
+    LCD_WriteReg(LCD_REG_24, 0x36); /* Display frame rate:75Hz(2.85MHz X 117%) */
+    LCD_WriteReg(LCD_REG_25, 0x01); /* Internal oscillator start to oscillate */
+    LCD_WriteReg(LCD_REG_1,0x00);
+    LCD_WriteReg(LCD_REG_31, 0x88); /* Step-up Circuit 1 on,open abnormal power-off monitor */
+    _delay_(2);
+    LCD_WriteReg(LCD_REG_31, 0x80); /* Step-up Circuit 1 off */
+    _delay_(2);
+    LCD_WriteReg(LCD_REG_31, 0x90); /* VCOML voltage can output to negative voltage,
+                                (1.0V ~ VCL+0.5V) */
+    _delay_(2);
+    LCD_WriteReg(LCD_REG_31, 0xD0); /* Step-up Circuit 2 on */
+    _delay_(2);
+
+    LCD_WriteReg(LCD_REG_23, 0x05);  /* COLMOD control */
+
+    /* Set GRAM Area - Partial Display Control */
+    LCD_WriteReg(LCD_REG_1, 0x00); /* Scroll off */
+
+    LCD_WriteReg(LCD_REG_2, 0x00);
+    LCD_WriteReg(LCD_REG_3, 0x00);
+    LCD_WriteReg(LCD_REG_4, 0x01); /* X,Y swap */
+    LCD_WriteReg(LCD_REG_5, 0x3F); /* X,Y swap */
+
+    LCD_WriteReg(LCD_REG_6, 0x00);
+    LCD_WriteReg(LCD_REG_7, 0x00);
+    LCD_WriteReg(LCD_REG_8, 0x00); /* X,Y swap */
+    LCD_WriteReg(LCD_REG_9, 0xEF); /* X,Y swap */
+
+    /* Memory access control */
+    /* bit7 controls left,right swap(X) */
+    /* bit6 controls up,down swap(Y) */
+    /* bit5 controls X,Y swap */
+    LCD_WriteReg(LCD_REG_22, 0x28);
+
+    /* SET PANEL */
+    LCD_WriteReg(LCD_REG_54, 0x00); /* Panel characteristic control */
+    LCD_WriteReg(LCD_REG_54, 0x04); /* Panel characteristic control: gate driver shift reverse[work] */
+    LCD_WriteReg(LCD_REG_40, 0x38); /* Display control3: source output->PT(0,0) */
+    _delay_(6);
+    LCD_WriteReg(LCD_REG_40, 0x3C); /* Display control3: source output->Display */
+  }
   /* Check if the LCD is SPFD5408B Controller */
-  if(lcdid == 0x5408)
+  else if(LCD_ID == LCD_SPFD5408)
   {
     /* Start Initial Sequence ------------------------------------------------*/
     LCD_WriteReg(LCD_REG_1, 0x0100);  /* Set SS bit */
@@ -240,10 +374,86 @@ void STM32100E_LCD_Init(void)
        AM=1 (address is updated in vertical writing direction) */
     LCD_WriteReg(LCD_REG_3, 0x1018);
     LCD_WriteReg(LCD_REG_7, 0x0112); /* 262K color and display ON */
-    LCD_SetFont(&LCD_DEFAULT_FONT);
-    return;
   }
-  else if(lcdid == 0x9325) /* Check if the LCD is ILI9325 Controller */
+  /* Check if the LCD is ILI9320 Controller */
+  else if(LCD_ID == LCD_ILI9320)
+  {
+    /* Start Initial Sequence ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
+    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
+    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
+    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
+
+    /* Power On sequence -----------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                  /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
+    _delay_(5);                  /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
+    _delay_(5);                  /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
+
+    /* Adjust the Gamma Curve ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0006);
+    LCD_WriteReg(LCD_REG_49, 0x0101);
+    LCD_WriteReg(LCD_REG_50, 0x0003);
+    LCD_WriteReg(LCD_REG_53, 0x0106);
+    LCD_WriteReg(LCD_REG_54, 0x0b02);
+    LCD_WriteReg(LCD_REG_55, 0x0302);
+    LCD_WriteReg(LCD_REG_56, 0x0707);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0600);
+    LCD_WriteReg(LCD_REG_61, 0x020b);
+  
+    /* Set GRAM area ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
+
+    /* Partial Display Control -----------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+
+    /* Panel Control ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */  
+  }
+  else if(LCD_ID == LCD_ILI9325) /* Check if the LCD is ILI9325 Controller */
   {
     /* Start Initial Sequence ------------------------------------------------*/
     LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */
@@ -313,85 +523,14 @@ void STM32100E_LCD_Init(void)
     LCD_WriteReg(LCD_REG_151, 0x0000);
     LCD_WriteReg(LCD_REG_152, 0x0000);
 
-    /* set GRAM write direction and BGR = 1 */
+    /* Set GRAM write direction and BGR = 1 */
     /* I/D=00 (Horizontal : increment, Vertical : decrement) */
     /* AM=1 (address is updated in vertical writing direction) */
     LCD_WriteReg(LCD_REG_3, 0x1018);
 
-    LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */
-    LCD_SetFont(&LCD_DEFAULT_FONT);
-    return;  
+    LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */ 
   }
-  /* Check if the LCD is ILI9320 Controller */
-/* Start Initial Sequence ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_229,0x8000); /* Set the internal vcore voltage */
-  LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-  LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-  LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-  LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-  LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-  LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-  LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-  LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-  LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-  LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-  LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-/* Power On sequence ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-  LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-/* Adjust the Gamma Curve ----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_48, 0x0006);
-  LCD_WriteReg(LCD_REG_49, 0x0101);
-  LCD_WriteReg(LCD_REG_50, 0x0003);
-  LCD_WriteReg(LCD_REG_53, 0x0106);
-  LCD_WriteReg(LCD_REG_54, 0x0b02);
-  LCD_WriteReg(LCD_REG_55, 0x0302);
-  LCD_WriteReg(LCD_REG_56, 0x0707);
-  LCD_WriteReg(LCD_REG_57, 0x0007);
-  LCD_WriteReg(LCD_REG_60, 0x0600);
-  LCD_WriteReg(LCD_REG_61, 0x020b);
-  
-/* Set GRAM area -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-  LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-  LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-  LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-  LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-/* Partial Display Control ---------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_128, 0x0000);
-  LCD_WriteReg(LCD_REG_129, 0x0000);
-  LCD_WriteReg(LCD_REG_130, 0x0000);
-  LCD_WriteReg(LCD_REG_131, 0x0000);
-  LCD_WriteReg(LCD_REG_132, 0x0000);
-  LCD_WriteReg(LCD_REG_133, 0x0000);
-/* Panel Control -------------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_144, 0x0010);
-  LCD_WriteReg(LCD_REG_146, 0x0000);
-  LCD_WriteReg(LCD_REG_147, 0x0003);
-  LCD_WriteReg(LCD_REG_149, 0x0110);
-  LCD_WriteReg(LCD_REG_151, 0x0000);
-  LCD_WriteReg(LCD_REG_152, 0x0000);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
-  LCD_SetFont(&LCD_DEFAULT_FONT);  
+  LCD_SetFont(&LCD_DEFAULT_FONT); 
 }
 
 /**
@@ -402,7 +541,7 @@ void STM32100E_LCD_Init(void)
   */
 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)
 {
-  TextColor = _TextColor; 
+  TextColor = _TextColor;
   BackColor = _BackColor;
 }
 
@@ -463,24 +602,39 @@ sFONT *LCD_GetFont(void)
 /**
   * @brief  Clears the selected line.
   * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
+  *         This parameter can be one of the following values:
+  *           @arg Linex: where x can be 0..n
   * @retval None
   */
-void LCD_ClearLine(uint8_t Line)
+void LCD_ClearLine(uint16_t Line)
 {
   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
-  /* Send the string character by character on lCD */
-  while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
+
+  if(LCD_ID == LCD_HX8347D)
   {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, ' ');
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
+    refcolumn = 0;
+    /* Send the string character by character on LCD */
+    while ((LCD_PIXEL_WIDTH - (refcolumn & 0xFFFF)) >= LCD_Currentfonts->Width)
+    {
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, ' ');
+      /* Increment the column position by 16 */
+      refcolumn += LCD_Currentfonts->Width;
+    }    
+  }
+  else
+  {
+    /* Send the string character by character on lCD */
+    while (((refcolumn + 1)&0xFFFF) >= LCD_Currentfonts->Width)
+    {
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, ' ');
+      /* Decrement the column position by 16 */
+      refcolumn -= LCD_Currentfonts->Width;
+    }    
   }
 }
 
-
 /**
   * @brief  Clears the hole LCD.
   * @param  Color: the color of the background.
@@ -489,29 +643,44 @@ void LCD_ClearLine(uint8_t Line)
 void LCD_Clear(uint16_t Color)
 {
   uint32_t index = 0;
-  
-  LCD_SetCursor(0x00, 0x013F); 
+
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_SetCursor(0x00, 0x0000);
+  }
+  else
+  {
+    LCD_SetCursor(0x00, 0x013F);
+  }
   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
   for(index = 0; index < 76800; index++)
   {
-    LCD->LCD_RAM = Color;
-  }  
+    TFT_LCD->LCD_RAM_W = Color;
+  }
 }
 
-
 /**
   * @brief  Sets the cursor position.
   * @param  Xpos: specifies the X position.
-  * @param  Ypos: specifies the Y position. 
+  * @param  Ypos: specifies the Y position.
   * @retval None
   */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
+void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos)
 {
-  LCD_WriteReg(LCD_REG_32, Xpos);
-  LCD_WriteReg(LCD_REG_33, Ypos);
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_WriteReg(LCD_REG_2, Ypos >> 8);
+    LCD_WriteReg(LCD_REG_3, Ypos & 0xFF);
+    LCD_WriteReg(LCD_REG_6, 0x00);
+    LCD_WriteReg(LCD_REG_7, Xpos);
+  }
+  else
+  {
+    LCD_WriteReg(LCD_REG_32, Xpos);
+    LCD_WriteReg(LCD_REG_33, Ypos);
+  }
 }
 
-
 /**
   * @brief  Draws a character on LCD.
   * @param  Xpos: the Line where to display the character shape.
@@ -519,10 +688,10 @@ void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
   * @param  c: pointer to the character data.
   * @retval None
   */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
+void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c)
 {
   uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
+  uint16_t Xaddress = 0;
    
   Xaddress = Xpos;
   
@@ -549,7 +718,6 @@ void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
   }
 }
 
-
 /**
   * @brief  Displays one character (16dots width, 24dots height).
   * @param  Line: the Line where to display the character shape .
@@ -559,13 +727,12 @@ void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
   * @retval None
   */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
+void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii)
 {
   Ascii -= 32;
   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
 }
 
-
 /**
   * @brief  Displays a maximum of 20 char on the LCD.
   * @param  Line: the Line where to display the character shape .
@@ -574,23 +741,39 @@ void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
   * @param  *ptr: pointer to string to display on LCD.
   * @retval None
   */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
+void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr)
 {
   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
 
-  /* Send the string character by character on lCD */
-  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
+  if(LCD_ID == LCD_HX8347D)
+  {
+    refcolumn = 0;
+    /* Send the string character by character on LCD */
+    while ((*ptr != 0) & ((LCD_PIXEL_WIDTH - (refcolumn & 0xFFFF)) >= LCD_Currentfonts->Width))
+    {
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, *ptr);
+      /* Increment the column position by 16 */
+      refcolumn += LCD_Currentfonts->Width;
+      /* Point on the next character */
+      ptr++;
+    }
+  }
+  else
   {
-    /* Display one character on LCD */
-    LCD_DisplayChar(Line, refcolumn, *ptr);
-    /* Decrement the column position by 16 */
-    refcolumn -= LCD_Currentfonts->Width;
-    /* Point on the next character */
-    ptr++;
+    /* Send the string character by character on LCD */
+    while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))
+    {
+      /* Display one character on LCD */
+      LCD_DisplayChar(Line, refcolumn, *ptr);
+      /* Decrement the column position by 16 */
+      refcolumn -= LCD_Currentfonts->Width;
+      /* Point on the next character */
+      ptr++;
+    }
   }
 }
 
-
 /**
   * @brief  Sets a display window
   * @param  Xpos: specifies the X buttom left position.
@@ -599,34 +782,50 @@ void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
   * @param  Width: display window width.
   * @retval None
   */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
 {
-  /* Horizontal GRAM Start Address */
-  if(Xpos >= Height)
-  {
-    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
-  }
-  else
-  {
-    LCD_WriteReg(LCD_REG_80, 0);
+  if(LCD_ID == LCD_HX8347D)
+  {    
+    LCD_WriteReg(LCD_REG_2, (319 - Ypos) >> 8); /* SC */
+    LCD_WriteReg(LCD_REG_3, (319 - Ypos) & 0xFF); /* SC */
+
+    LCD_WriteReg(LCD_REG_4, (319 - (Ypos - Width + 1)) >> 8); /* EC */
+    LCD_WriteReg(LCD_REG_5, (319 - (Ypos - Width + 1)) & 0xFF); /* EC */
+
+    LCD_WriteReg(LCD_REG_6, 0x0); /* SP */
+    LCD_WriteReg(LCD_REG_7, (239 - Xpos) & 0xFF); /* SP */
+
+    LCD_WriteReg(LCD_REG_8, 0x0); /* EP */
+    LCD_WriteReg(LCD_REG_9, (239 - (Xpos - Height + 1)) & 0xFF); /* EP */
   }
-  /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_81, Xpos);
-  /* Vertical GRAM Start Address */
-  if(Ypos >= Width)
-  {
-    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
-  }  
   else
   {
-    LCD_WriteReg(LCD_REG_82, 0);
+    /* Horizontal GRAM Start Address */
+    if(Xpos >= Height)
+    {
+      LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));
+    }
+    else
+    {
+      LCD_WriteReg(LCD_REG_80, 0);
+    }
+    /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_81, Xpos);
+    /* Vertical GRAM Start Address */
+    if(Ypos >= Width)
+    {
+      LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));
+    }
+    else
+    {
+      LCD_WriteReg(LCD_REG_82, 0);
+    }
+    /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_83, Ypos);
+    LCD_SetCursor(Xpos, Ypos);
   }
-  /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_83, Ypos);
-  LCD_SetCursor(Xpos, Ypos);
 }
 
-
 /**
   * @brief  Disables LCD Window mode.
   * @param  None
@@ -635,24 +834,35 @@ void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t
 void LCD_WindowModeDisable(void)
 {
   LCD_SetDisplayWindow(239, 0x13F, 240, 320);
-  LCD_WriteReg(LCD_REG_3, 0x1018);    
+  
+  if(LCD_ID != LCD_HX8347D)
+  {
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+  }
 }
 
-
 /**
   * @brief  Displays a line.
-  * @param Xpos: specifies the X position.
-  * @param Ypos: specifies the Y position.
-  * @param Length: line length.
-  * @param Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
+  * @param  Xpos: specifies the X position.
+  * @param  Ypos: specifies the Y position.
+  * @param  Length: line length.
+  * @param  Direction: line direction.
+  *         This parameter can be one of the following values: Vertical or Horizontal.
   * @retval None
   */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
+void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
 {
   uint32_t i = 0;
-  
-  LCD_SetCursor(Xpos, Ypos);
+
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_SetCursor(Xpos, (LCD_PIXEL_WIDTH - 1) - Ypos);
+  }
+  else
+  {
+    LCD_SetCursor(Xpos, Ypos);
+  }
+
   if(Direction == LCD_DIR_HORIZONTAL)
   {
     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
@@ -668,12 +878,18 @@ void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Directio
       LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
       LCD_WriteRAM(TextColor);
       Xpos++;
-      LCD_SetCursor(Xpos, Ypos);
+      if(LCD_ID == LCD_HX8347D)
+      {
+        LCD_SetCursor(Xpos, (LCD_PIXEL_WIDTH - 1) - Ypos);
+      }
+      else
+      {
+        LCD_SetCursor(Xpos, Ypos);
+      }
     }
   }
 }
 
-
 /**
   * @brief  Displays a rectangle.
   * @param  Xpos: specifies the X position.
@@ -682,7 +898,7 @@ void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Directio
   * @param  Width: display rectangle width.
   * @retval None
   */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
 {
   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
@@ -691,7 +907,6 @@ void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
   LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);
 }
 
-
 /**
   * @brief  Displays a circle.
   * @param  Xpos: specifies the X position.
@@ -699,12 +914,16 @@ void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
   * @param  Radius
   * @retval None
   */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
+void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
 {
   int32_t  D;/* Decision Variable */ 
   uint32_t  CurX;/* Current X Value */
   uint32_t  CurY;/* Current Y Value */ 
-  
+
+  if(LCD_ID == LCD_HX8347D)
+  {
+    Ypos = (LCD_PIXEL_WIDTH - 1) - Ypos;
+  }  
   D = 3 - (Radius << 1);
   CurX = 0;
   CurY = Radius;
@@ -748,7 +967,6 @@ void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
   }
 }
 
-
 /**
   * @brief  Displays a monocolor picture.
   * @param  Pict: pointer to the picture array.
@@ -757,7 +975,16 @@ void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
 void LCD_DrawMonoPict(const uint32_t *Pict)
 {
   uint32_t index = 0, i = 0;
-  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
+
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_SetCursor(0, 0);
+  }
+  else
+  {
+    LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));
+  }
+
   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
   for(index = 0; index < 2400; index++)
   {
@@ -775,7 +1002,6 @@ void LCD_DrawMonoPict(const uint32_t *Pict)
   }
 }
 
-
 /**
   * @brief  Displays a bitmap picture loaded in the internal Flash.
   * @param  BmpAddress: Bmp picture address in the internal Flash.
@@ -1057,7 +1283,6 @@ void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)
   LCD_PolyLineRelativeClosed(Points, PointCount, 1);
 }
 
-
 /**
   * @brief  Displays a  full polyline (between many points).
   * @param  Points: pointer to the points array.
@@ -1107,7 +1332,8 @@ void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
 
     for (i = 0; i < PointCount; i++) 
     {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
+      if (((POLY_Y(i)<(double) pixelY) && (POLY_Y(j)>=(double) pixelY)) || \
+          ((POLY_Y(j)<(double) pixelY) && (POLY_Y(i)>=(double) pixelY)))
       {
         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
       }
@@ -1174,12 +1400,11 @@ void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
 void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
 {
   /* Write 16-bit Index, then Write Reg */
-  LCD->LCD_REG = LCD_Reg;
+  TFT_LCD->LCD_REG_W = LCD_Reg;
   /* Write 16-bit Reg */
-  LCD->LCD_RAM = LCD_RegValue;
+  TFT_LCD->LCD_RAM_W = LCD_RegValue;
 }
 
-
 /**
   * @brief  Reads the selected LCD Register.
   * @param  LCD_Reg: address of the selected register.
@@ -1188,12 +1413,11 @@ void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
 {
   /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_Reg;
+  TFT_LCD->LCD_REG_W = LCD_Reg;
   /* Read 16-bit Reg */
-  return (LCD->LCD_RAM);
+  return (TFT_LCD->LCD_RAM_R);
 }
 
-
 /**
   * @brief  Prepare to write to the LCD RAM.
   * @param  None
@@ -1201,10 +1425,9 @@ uint16_t LCD_ReadReg(uint8_t LCD_Reg)
   */
 void LCD_WriteRAM_Prepare(void)
 {
-  LCD->LCD_REG = LCD_REG_34;
+  TFT_LCD->LCD_REG_W = LCD_REG_34;
 }
 
-
 /**
   * @brief  Writes to the LCD RAM.
   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
@@ -1213,10 +1436,9 @@ void LCD_WriteRAM_Prepare(void)
 void LCD_WriteRAM(uint16_t RGB_Code)
 {
   /* Write 16-bit GRAM Reg */
-  LCD->LCD_RAM = RGB_Code;
+  TFT_LCD->LCD_RAM_W = RGB_Code;
 }
 
-
 /**
   * @brief  Reads the LCD RAM.
   * @param  None
@@ -1225,12 +1447,11 @@ void LCD_WriteRAM(uint16_t RGB_Code)
 uint16_t LCD_ReadRAM(void)
 {
   /* Write 16-bit Index (then Read Reg) */
-  LCD->LCD_REG = LCD_REG_34; /* Select GRAM Reg */
+  TFT_LCD->LCD_REG_W = LCD_REG_34; /* Select GRAM Reg */
   /* Read 16-bit Reg */
-  return LCD->LCD_RAM;
+  return TFT_LCD->LCD_RAM_R;
 }
 
-
 /**
   * @brief  Power on the LCD.
   * @param  None
@@ -1255,7 +1476,6 @@ void LCD_PowerOn(void)
   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
 }
 
-
 /**
   * @brief  Enables the Display.
   * @param  None
@@ -1263,11 +1483,19 @@ void LCD_PowerOn(void)
   */
 void LCD_DisplayOn(void)
 {
-  /* Display On */
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_WriteReg(LCD_REG_40, 0x38);
+    _delay_(6);
+    LCD_WriteReg(LCD_REG_40, 0x3C);
+  }
+  else
+  {
+    /* Display On */
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+  }
 }
 
-
 /**
   * @brief  Disables the Display.
   * @param  None
@@ -1275,11 +1503,19 @@ void LCD_DisplayOn(void)
   */
 void LCD_DisplayOff(void)
 {
-  /* Display Off */
-  LCD_WriteReg(LCD_REG_7, 0x0); 
+  if(LCD_ID == LCD_HX8347D)
+  {
+    LCD_WriteReg(LCD_REG_40, 0x38);
+    _delay_(6);
+    LCD_WriteReg(LCD_REG_40, 0x04);
+  }
+  else
+  {
+    /* Display Off */
+    LCD_WriteReg(LCD_REG_7, 0x0);
+  }
 }
 
-
 /**
   * @brief  Configures LCD Control lines (FSMC Pins) in alternate function mode.
   * @param  None
@@ -1289,35 +1525,60 @@ void LCD_CtrlLinesConfig(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
 
-  /* Enable FSMC, GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
-                         RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG |
-                         RCC_APB2Periph_AFIO, ENABLE);
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOF |
+                         RCC_AHBPeriph_GPIOG, ENABLE);
 
+/*-- GPIO Configuration ------------------------------------------------------*/
   /* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
      PD.10(D15), PD.14(D0), PD.15(D1) as alternate function push pull */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
                                 GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | 
                                 GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
   GPIO_Init(GPIOD, &GPIO_InitStructure);
 
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);
+
   /* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
      PE.14(D11), PE.15(D12) as alternate function push pull */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | 
                                 GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | 
                                 GPIO_Pin_15;
   GPIO_Init(GPIOE, &GPIO_InitStructure);
-  
-  /* Set PF.00(A0 (RS)) as alternate function push pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_Init(GPIOF, &GPIO_InitStructure);
-  
-  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull */
+
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC);
+
+  /* Set PF.00(A0 (RS)) and PF.01 (A1 (Level Shifter Direction) as alternate 
+     function push pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
+  GPIO_Init(GPIOF, &GPIO_InitStructure);  
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FSMC);
+  GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FSMC);	   
+
+  /* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - NE4(LCD /CS) */
   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
   GPIO_Init(GPIOG, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOG, GPIO_PinSource12, GPIO_AF_FSMC);
 }
 
 /**
@@ -1329,6 +1590,10 @@ void LCD_FSMCConfig(void)
 {
   FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
   FSMC_NORSRAMTimingInitTypeDef  p;
+
+  /* Enable FSMC clock */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+    
 /*-- FSMC Configuration ------------------------------------------------------*/
 /*----------------------- SRAM Bank 4 ----------------------------------------*/
   /* FSMC_Bank1_NORSRAM4 configuration */
@@ -1388,10 +1653,10 @@ static void PutPixel(int16_t x, int16_t y)
   * @param  nCount: specifies the delay time length.
   * @retval None
   */
-static void delay(vu32 nCount)
+static void delay(__IO uint32_t nCount)
 {
-  vu32 index = 0; 
-  for(index = (34000 * nCount); index != 0; index--)
+  __IO uint32_t index = 0; 
+  for(index = (10000 * nCount); index != 0; index--)
   {
   }
 }
@@ -1416,4 +1681,4 @@ static void delay(vu32 nCount)
   * @}
   */  
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_lcd.h
index 66320cd..46016c8 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32100E_EVAL/stm32100e_eval_lcd.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_lcd.h
@@ -1,35 +1,41 @@
 /**
   ******************************************************************************
-  * @file    stm32100e_eval_lcd.h
+  * @file    stm32l152d_eval_lcd.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32100e_eval_lcd
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the stm32l152d_eval_lcd
   *          firmware driver.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32100E_EVAL_LCD_H
-#define __STM32100E_EVAL_LCD_H
+#ifndef __STM32L152D_EVAL_LCD_H
+#define __STM32L152D_EVAL_LCD_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif 
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
+#include "stm32l152d_eval.h"
 #include "../Common/fonts.h"
 
 /** @addtogroup Utilities
@@ -40,15 +46,15 @@
   * @{
   */ 
 
-/** @addtogroup STM32100E_EVAL
+/** @addtogroup STM32L152D_EVAL
   * @{
   */
     
-/** @addtogroup STM32100E_EVAL_LCD
+/** @addtogroup STM32L152D_EVAL_LCD
   * @{
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Exported_Types
+/** @defgroup STM32L152D_EVAL_LCD_Exported_Types
   * @{
   */
 typedef struct 
@@ -60,7 +66,7 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Exported_Constants
+/** @defgroup STM32L152D_EVAL_LCD_Exported_Constants
   * @{
   */ 
 
@@ -116,8 +122,10 @@ typedef struct
 #define LCD_REG_32            0x20
 #define LCD_REG_33            0x21
 #define LCD_REG_34            0x22
+#define LCD_REG_35            0x23
 #define LCD_REG_36            0x24
 #define LCD_REG_37            0x25
+#define LCD_REG_39            0x27
 #define LCD_REG_40            0x28
 #define LCD_REG_41            0x29
 #define LCD_REG_43            0x2B
@@ -158,6 +166,16 @@ typedef struct
 #define LCD_REG_81            0x51
 #define LCD_REG_82            0x52
 #define LCD_REG_83            0x53
+#define LCD_REG_84            0x54
+#define LCD_REG_85            0x55
+#define LCD_REG_86            0x56
+#define LCD_REG_87            0x57
+#define LCD_REG_88            0x58
+#define LCD_REG_89            0x59
+#define LCD_REG_90            0x5A
+#define LCD_REG_91            0x5B
+#define LCD_REG_92            0x5C
+#define LCD_REG_93            0x5D
 #define LCD_REG_96            0x60
 #define LCD_REG_97            0x61
 #define LCD_REG_106           0x6A
@@ -191,6 +209,14 @@ typedef struct
 #define LCD_REG_192           0xC0
 #define LCD_REG_193           0xC1
 #define LCD_REG_229           0xE5
+#define LCD_REG_232           0xE8
+#define LCD_REG_233           0xE9
+#define LCD_REG_234           0xEA
+#define LCD_REG_235           0xEB
+#define LCD_REG_236           0xEC
+#define LCD_REG_237           0xED
+#define LCD_REG_241           0xF1
+#define LCD_REG_242           0xF2
 
 /** 
   * @brief  LCD color  
@@ -261,7 +287,7 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Exported_Macros
+/** @defgroup STM32L152D_EVAL_LCD_Exported_Macros
   * @{
   */ 
 #define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))  
@@ -269,31 +295,31 @@ typedef struct
   * @}
   */ 
 
-/** @defgroup STM32100E_EVAL_LCD_Exported_Functions
+/** @defgroup STM32L152D_EVAL_LCD_Exported_Functions
   * @{
   */ 
 /** @defgroup  
   * @{
   */ 
-void LCD_DeInit(void);  
-void STM32100E_LCD_Init(void);
+void STM32L152D_LCD_DeInit(void);  
+void STM32L152D_LCD_Init(void);
 void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
 void LCD_SetTextColor(__IO uint16_t Color);
 void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
+void LCD_ClearLine(uint16_t Line);
 void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
+void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos);
+void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c);
+void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii);
 void LCD_SetFont(sFONT *fonts);
 sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr);
+void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
 void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
+void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
+void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
 void LCD_DrawMonoPict(const uint32_t *Pict);
 void LCD_WriteBMP(uint32_t BmpAddress);
 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
@@ -339,7 +365,7 @@ void LCD_FSMCConfig(void);
 }
 #endif
 
-#endif /* __STM32100E_EVAL_LCD_H */
+#endif /* __STM32L152D_EVAL_LCD_H */
 /**
   * @}
   */ 
@@ -356,4 +382,4 @@ void LCD_FSMCConfig(void);
   * @}
   */
   
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c
new file mode 100644
index 0000000..f95f418
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.c
@@ -0,0 +1,2818 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_sdio_sd.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to manage the SDIO SD 
+  *          Card memory mounted on STM32L152D-EVAL evaluation board. 
+  *          
+  *            
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                   How to use this driver
+  *          ===================================================================
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32 hardware resources (SDIO and 
+  *          GPIO) are defined in stm32l152d_eval.h file, and the initialization is 
+  *          performed in SD_LowLevel_Init() function declared in stm32l152d_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SD_LowLevel_Init() function.
+  *
+  *          A - SD Card Initialization and configuration
+  *          ============================================    
+  *            - To initialize the SD Card, use the SD_Init() function.  It 
+  *              Initializes the SD Card and put it into StandBy State (Ready 
+  *              for data transfer). This function provide the following operations:
+  *
+  *              1 - Apply the SD Card initialization process at 400KHz and check
+  *                  the SD Card type (Standard Capacity or High Capacity). You 
+  *                  can change or adapt this frequency by adjusting the 
+  *                  "SDIO_INIT_CLK_DIV" define inside the stm32l152d_eval.h file. 
+  *                  The SD Card frequency (SDIO_CK) is computed as follows:
+  *
+  *                     +---------------------------------------------+
+  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
+  *                     +---------------------------------------------+
+  *
+  *                  In initialization mode and according to the SD Card standard, 
+  *                  make sure that the SDIO_CK frequency don't exceed 400KHz.
+  *
+  *              2 - Get the SD CID and CSD data. All these information are
+  *                  managed by the SDCardInfo structure. This structure provide
+  *                  also ready computed SD Card capacity and Block size.   
+  *
+  *              3 - Configure the SD Card Data transfer frequency. By Default,
+  *                  the card transfer frequency is set to 24MHz. You can change
+  *                  or adapt this frequency by adjusting the "SDIO_TRANSFER_CLK_DIV" 
+  *                  define inside the stm32l152d_eval.h file.
+  *                  The SD Card frequency (SDIO_CK) is computed as follows:
+  *
+  *                     +---------------------------------------------+
+  *                     | SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) |
+  *                     +---------------------------------------------+
+  *
+  *                  In transfer mode and according to the SD Card standard, 
+  *                  make sure that the SDIO_CK frequency don't exceed 25MHz
+  *                  and 50MHz in High-speed mode switch.
+  *                  To be able to use a frequency higher than 24MHz, you should
+  *                  use the SDIO peripheral in bypass mode. Refer to the 
+  *                  corresponding reference manual for more details.
+  *
+  *              4 -  Select the corresponding SD Card according to the address
+  *                   read with the step 2.
+  *
+  *              5 -  Configure the SD Card in wide bus mode: 4-bits data.
+  *
+  *          B - SD Card Read operation
+  *          ========================== 
+  *           - You can read SD card by using two function: SD_ReadBlock() and
+  *             SD_ReadMultiBlocks() functions. These functions support only
+  *             512-byte block length.
+  *           - The SD_ReadBlock() function read only one block (512-byte). This
+  *             function can transfer the data using DMA controller or using 
+  *             polling mode. To select between DMA or polling mode refer to 
+  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32l152d_eval_sdio_sd.h
+  *             file and uncomment the corresponding line. By default the SD DMA
+  *             mode is selected          
+  *           - The SD_ReadMultiBlocks() function read only mutli blocks (multiple 
+  *             of 512-byte). 
+  *           - Any read operation should be followed by two functions to check
+  *             if the DMA Controller and SD Card status.
+  *              - SD_ReadWaitOperation(): this function insure that the DMA
+  *                controller has finished all data transfer.
+  *              - SD_GetStatus(): to check that the SD Card has finished the 
+  *                data transfer and it is ready for data.
+  *
+  *           - The DMA transfer is finished by the SDIO Data End interrupt. 
+  *             User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler()
+  *             and SD_ProcessDMAIRQ() function inside the DMA2_Channel4_IRQHandler().
+  *             Don't forget to enable the SDIO_IRQn and DMA2_Channel4_IRQn 
+  *             interrupts using the NVIC controller.
+  *
+  *          C - SD Card Write operation
+  *          =========================== 
+  *           - You can write SD card by using two function: SD_WriteBlock() and
+  *             SD_WriteMultiBlocks() functions. These functions support only
+  *             512-byte block length.   
+  *           - The SD_WriteBlock() function write only one block (512-byte). This
+  *             function can transfer the data using DMA controller or using 
+  *             polling mode. To select between DMA or polling mode refer to 
+  *             "SD_DMA_MODE" or "SD_POLLING_MODE" inside the stm32l152d_eval_sdio_sd.h
+  *             file and uncomment the corresponding line. By default the SD DMA
+  *             mode is selected          
+  *           - The SD_WriteMultiBlocks() function write only mutli blocks (multiple 
+  *             of 512-byte). 
+  *           - Any write operation should be followed by two functions to check
+  *             if the DMA Controller and SD Card status.
+  *              - SD_ReadWaitOperation(): this function insure that the DMA
+  *                controller has finished all data transfer.
+  *              - SD_GetStatus(): to check that the SD Card has finished the 
+  *                data transfer and it is ready for data.
+  *
+  *           - The DMA transfer is finished by the SDIO Data End interrupt. 
+  *             User has to call the SD_ProcessIRQ() function inside the SDIO_IRQHandler()
+  *             and SD_ProcessDMAIRQ() function inside the DMA2_Channel4_IRQHandler().
+  *             Don't forget to enable the SDIO_IRQn and DMA2_Channel4_IRQn 
+  *             interrupts using the NVIC controller.
+  *
+  *
+  *          D - SD card status
+  *          ================== 
+  *           - At any time, you can check the SD Card status and get the SD card
+  *             state by using the SD_GetStatus() function. This function checks
+  *             first if the SD card is still connected and then get the internal
+  *             SD Card transfer state.     
+  *           - You can also get the SD card SD Status register by using the 
+  *             SD_SendSDStatus() function.
+  *
+  *          E - Programming Model (Selecting DMA for SDIO data Transfer)
+  *          ============================================================ 
+  *             Status = SD_Init(); // Initialization Step as described in section A
+  *
+  *             // SDIO Interrupt ENABLE
+  *             NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
+  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  *             NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  *             NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  *             NVIC_Init(&NVIC_InitStructure);
+  *             // DMA2 Channel4 Interrupt ENABLE
+  *             NVIC_InitStructure.NVIC_IRQChannel = SD_SDIO_DMA_IRQn;
+  *             NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  *             NVIC_Init(&NVIC_InitStructure);
+  *               
+  *             // Write operation as described in Section C
+  *             Status = SD_WriteBlock(buffer, address, 512);
+  *             Status = SD_WaitWriteOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             Status = SD_WriteMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
+  *             Status = SD_WaitWriteOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             // Read operation as described in Section B
+  *             Status = SD_ReadBlock(buffer, address, 512);
+  *             Status = SD_WaitReadOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             Status = SD_ReadMultiBlocks(buffer, address, 512, NUMBEROFBLOCKS);
+  *             Status = SD_WaitReadOperation();
+  *             while(SD_GetStatus() != SD_TRANSFER_OK);
+  *
+  *             - Add the SDIO and DMA2 Channel4 IRQ Handlers:   
+  *                 void SDIO_IRQHandler(void)
+  *                 {
+  *                   SD_ProcessIRQ();  
+  *                 }   
+  *                 void SD_SDIO_DMA_IRQHANDLER(void)
+  *                 {
+  *                   SD_ProcessDMAIRQ();  
+  *                 }     
+  *
+  *          F - Programming Model (Selecting Polling for SDIO data Transfer)
+  *          ================================================================
+  *            //Only SD Card Single Block operation are managed.   
+  *            Status = SD_Init(); // Initialization Step as described in section
+  *               
+  *            // Write operation as described in Section C
+  *            Status = SD_WriteBlock(buffer, address, 512);
+  *
+  *            // Read operation as described in Section B
+  *            Status = SD_ReadBlock(buffer, address, 512);
+  *                 
+  *          STM32 SDIO Pin assignment
+  *          =========================
+  *          +-----------------------------------------------------------+
+  *          |                     Pin assignment                        |
+  *          +-----------------------------+---------------+-------------+
+  *          |  STM32 SDIO Pins            |     SD        |    Pin      |
+  *          +-----------------------------+---------------+-------------+
+  *          |      SDIO D2                |   D2          |    1        |
+  *          |      SDIO D3                |   D3          |    2        |
+  *          |      SDIO CMD               |   CMD         |    3        |
+  *          |                             |   VCC         |    4 (3.3 V)|
+  *          |      SDIO CLK               |   CLK         |    5        |
+  *          |                             |   GND         |    6 (0 V)  |
+  *          |      SDIO D0                |   D0          |    7        |
+  *          |      SDIO D1                |   D1          |    8        |
+  *          +-----------------------------+---------------+-------------+
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval_sdio_sd.h"
+
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152D_EVAL_SDIO_SD
+  * @brief      This file provides all the SD Card driver firmware functions.
+  * @{
+  */ 
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Defines
+  * @{
+  */ 
+
+/** 
+  * @brief  SDIO Static flags, TimeOut, FIFO Address  
+  */
+#define NULL 0
+#define SDIO_STATIC_FLAGS               ((uint32_t)0x000005FF)
+#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
+
+/** 
+  * @brief  Mask for errors Card Status R1 (OCR Register) 
+  */
+#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
+#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
+#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
+#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
+#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
+#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
+#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
+#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
+
+#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
+#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
+#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
+#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
+
+#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
+#define SD_ALLZERO                      ((uint32_t)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
+#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
+
+#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
+#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
+#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
+#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
+#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
+#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
+
+#define SD_HALFFIFO                     ((uint32_t)0x00000008)
+#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Command Class Supported 
+  */
+#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
+#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
+#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
+
+/** 
+  * @brief  Following commands are SD Card Specific commands.
+  *         SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SDIO_SEND_IF_COND               ((uint32_t)0x00000008)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Variables
+  * @{
+  */
+
+static uint32_t CardType =  SDIO_STD_CAPACITY_SD_CARD_V1_1;
+static uint32_t CSD_Tab[4], CID_Tab[4], RCA = 0;
+static uint8_t SDSTATUS_Tab[16];
+__IO uint32_t StopCondition = 0;
+__IO SD_Error TransferError = SD_OK;
+__IO uint32_t TransferEnd = 0, DMAEndOfTransfer = 0;
+SD_CardInfo SDCardInfo;
+
+SDIO_InitTypeDef SDIO_InitStructure;
+SDIO_CmdInitTypeDef SDIO_CmdInitStructure;
+SDIO_DataInitTypeDef SDIO_DataInitStructure;
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Function_Prototypes
+  * @{
+  */
+static SD_Error CmdError(void);
+static SD_Error CmdResp1Error(uint8_t cmd);
+static SD_Error CmdResp7Error(void);
+static SD_Error CmdResp3Error(void);
+static SD_Error CmdResp2Error(void);
+static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca);
+static SD_Error SDEnWideBus(FunctionalState NewState);
+static SD_Error IsCardProgramming(uint8_t *pstatus);
+static SD_Error FindSCR(uint16_t rca, uint32_t *pscr);
+uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes);
+  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Private_Functions
+  * @{
+  */  
+
+/**
+  * @brief  DeInitializes the SDIO interface.
+  * @param  None
+  * @retval None
+  */
+void SD_DeInit(void)
+{ 
+  SD_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for data 
+  *         transfer).
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_Init(void)
+{
+  __IO SD_Error errorstatus = SD_OK;
+  
+  /* SDIO Peripheral Low Level Init */
+  SD_LowLevel_Init();
+
+  SDIO_DeInit();
+
+  errorstatus = SD_PowerON();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  errorstatus = SD_InitializeCards();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  /*!< Configure the SDIO peripheral */
+  /*!< SDIO_CK = SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2) */
+  /*!< on STM32L1xx devices, SDIOCLK is fixed to 48MHz */
+  SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV;
+  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+  SDIO_Init(&SDIO_InitStructure);
+
+  /*----------------- Read CSD/CID MSD registers ------------------*/
+  errorstatus = SD_GetCardInfo(&SDCardInfo);
+
+  if (errorstatus == SD_OK)
+  {
+    /*----------------- Select Card --------------------------------*/
+    errorstatus = SD_SelectDeselect((uint32_t) (SDCardInfo.RCA << 16));
+  }
+
+  if (errorstatus == SD_OK)
+  {
+    errorstatus = SD_EnableWideBusOperation(SDIO_BusWide_4b);
+  }  
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Gets the cuurent sd card data transfer status.
+  * @param  None
+  * @retval SDTransferState: Data Transfer state.
+  *   This value can be: 
+  *        - SD_TRANSFER_OK: No data transfer is acting
+  *        - SD_TRANSFER_BUSY: Data transfer is acting
+  */
+SDTransferState SD_GetStatus(void)
+{
+  SDCardState cardstate =  SD_CARD_TRANSFER;
+
+  cardstate = SD_GetState();
+  
+  if (cardstate == SD_CARD_TRANSFER)
+  {
+    return(SD_TRANSFER_OK);
+  }
+  else if(cardstate == SD_CARD_ERROR)
+  {
+    return (SD_TRANSFER_ERROR);
+  }
+  else
+  {
+    return(SD_TRANSFER_BUSY);
+  }
+}
+
+/**
+  * @brief  Returns the current card's state.
+  * @param  None
+  * @retval SDCardState: SD Card Error or SD Card Current State.
+  */
+SDCardState SD_GetState(void)
+{
+  uint32_t resp1 = 0;
+  
+  if(SD_Detect()== SD_PRESENT)
+  {
+    if (SD_SendStatus(&resp1) != SD_OK)
+    {
+      return SD_CARD_ERROR;
+    }
+    else
+    {
+      return (SDCardState)((resp1 >> 9) & 0x0F);
+    }
+  }
+  else
+  {
+    return SD_CARD_ERROR;
+  }
+}
+
+/**
+ * @brief  Detect if SD card is correctly plugged in the memory slot.
+ * @param  None
+ * @retval Return if SD is detected or not
+ */
+uint8_t SD_Detect(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  /*!< Check GPIO to detect SD */
+  if (GPIO_ReadInputDataBit(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != Bit_RESET)
+  {
+    status = SD_NOT_PRESENT;
+  }
+  return status;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures 
+  *   clock controls.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_PowerON(void)
+{
+  __IO SD_Error errorstatus = SD_OK;
+  uint32_t response = 0, count = 0, validvoltage = 0;
+  uint32_t SDType = SD_STD_CAPACITY;
+
+  /*!< Power ON Sequence -----------------------------------------------------*/
+  /*!< Configure the SDIO peripheral */
+  /*!< SDIO_CK = SDIOCLK / (SDIO_INIT_CLK_DIV + 2) */
+  /*!< on STM32L1xx devices, SDIOCLK is fixed to 48MHz */
+  /*!< SDIO_CK for initialization should not exceed 400 KHz */  
+  SDIO_InitStructure.SDIO_ClockDiv = SDIO_INIT_CLK_DIV;
+  SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+  SDIO_Init(&SDIO_InitStructure);
+
+  /*!< Set Power State to ON */
+  SDIO_SetPowerState(SDIO_PowerState_ON);
+
+  /*!< Enable SDIO Clock */
+  SDIO_ClockCmd(ENABLE);
+
+  /*!< CMD0: GO_IDLE_STATE ---------------------------------------------------*/
+  /*!< No CMD response required */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_GO_IDLE_STATE;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdError();
+
+  if (errorstatus != SD_OK)
+  {
+    /*!< CMD Response TimeOut (wait for CMDSENT flag) */
+    return(errorstatus);
+  }
+
+  /*!< CMD8: SEND_IF_COND ----------------------------------------------------*/
+  /*!< Send CMD8 to verify SD card interface operating condition */
+  /*!< Argument: - [31:12]: Reserved (shall be set to '0')
+               - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+               - [7:0]: Check Pattern (recommended 0xAA) */
+  /*!< CMD Response: R7 */
+  SDIO_CmdInitStructure.SDIO_Argument = SD_CHECK_PATTERN;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SDIO_SEND_IF_COND;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp7Error();
+
+  if (errorstatus == SD_OK)
+  {
+    CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; /*!< SD Card 2.0 */
+    SDType = SD_HIGH_CAPACITY;
+  }
+  else
+  {
+    /*!< CMD55 */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+    errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+  }
+  /*!< CMD55 */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  /*!< If errorstatus is Command TimeOut, it is a MMC card */
+  /*!< If errorstatus is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  if (errorstatus == SD_OK)
+  {
+    /*!< SD CARD */
+    /*!< Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+    while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
+    {
+
+      /*!< SEND CMD55 APP_CMD with RCA as 0 */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+      SDIO_CmdInitStructure.SDIO_Argument = SD_VOLTAGE_WINDOW_SD | SDType;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_OP_COND;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp3Error();
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      response = SDIO_GetResponse(SDIO_RESP1);
+      validvoltage = (((response >> 31) == 1) ? 1 : 0);
+      count++;
+    }
+    if (count >= SD_MAX_VOLT_TRIAL)
+    {
+      errorstatus = SD_INVALID_VOLTRANGE;
+      return(errorstatus);
+    }
+
+    if (response &= SD_HIGH_CAPACITY)
+    {
+      CardType = SDIO_HIGH_CAPACITY_SD_CARD;
+    }
+
+  }/*!< else MMC Card */
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Turns the SDIO output signals off.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_PowerOFF(void)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Set Power State to OFF */
+  SDIO_SetPowerState(SDIO_PowerState_OFF);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Intialises all cards or single card as the case may be Card(s) come 
+  *         into standby state.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_InitializeCards(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint16_t rca = 0x01;
+
+  if (SDIO_GetPowerState() == SDIO_PowerState_OFF)
+  {
+    errorstatus = SD_REQUEST_NOT_APPLICABLE;
+    return(errorstatus);
+  }
+
+  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
+  {
+    /*!< Send CMD2 ALL_SEND_CID */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ALL_SEND_CID;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp2Error();
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+
+    CID_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
+    CID_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
+    CID_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
+    CID_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) ||  (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) ||  (SDIO_SECURE_DIGITAL_IO_COMBO_CARD == CardType)
+      ||  (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    /*!< Send CMD3 SET_REL_ADDR with argument 0 */
+    /*!< SD Card publishes its RCA. */
+    SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_REL_ADDR;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp6Error(SD_CMD_SET_REL_ADDR, &rca);
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+  }
+
+  if (SDIO_SECURE_DIGITAL_IO_CARD != CardType)
+  {
+    RCA = rca;
+
+    /*!< Send CMD9 SEND_CSD with argument as card's RCA */
+    SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)(rca << 16);
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_CSD;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Long;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp2Error();
+
+    if (SD_OK != errorstatus)
+    {
+      return(errorstatus);
+    }
+
+    CSD_Tab[0] = SDIO_GetResponse(SDIO_RESP1);
+    CSD_Tab[1] = SDIO_GetResponse(SDIO_RESP2);
+    CSD_Tab[2] = SDIO_GetResponse(SDIO_RESP3);
+    CSD_Tab[3] = SDIO_GetResponse(SDIO_RESP4);
+  }
+
+  errorstatus = SD_OK; /*!< All cards get intialized */
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD card 
+  *         information.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
+{
+  SD_Error errorstatus = SD_OK;
+  uint8_t tmp = 0;
+
+  cardinfo->CardType = (uint8_t)CardType;
+  cardinfo->RCA = (uint16_t)RCA;
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.CSDStruct = (tmp & 0xC0) >> 6;
+  cardinfo->SD_csd.SysSpecVersion = (tmp & 0x3C) >> 2;
+  cardinfo->SD_csd.Reserved1 = tmp & 0x03;
+
+  /*!< Byte 1 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.TAAC = tmp;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((CSD_Tab[0] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.NSAC = tmp;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)(CSD_Tab[0] & 0x000000FF);
+  cardinfo->SD_csd.MaxBusClkFrec = tmp;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.CardComdClasses = tmp << 4;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.CardComdClasses |= (tmp & 0xF0) >> 4;
+  cardinfo->SD_csd.RdBlockLen = tmp & 0x0F;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)((CSD_Tab[1] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.PartBlockRead = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.WrBlockMisalign = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.RdBlockMisalign = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.DSRImpl = (tmp & 0x10) >> 4;
+  cardinfo->SD_csd.Reserved2 = 0; /*!< Reserved */
+
+  if ((CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || (CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0))
+  {
+    cardinfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
+
+    /*!< Byte 7 */
+    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
+    cardinfo->SD_csd.DeviceSize |= (tmp) << 2;
+
+    /*!< Byte 8 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
+    cardinfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
+
+    cardinfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
+    cardinfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
+
+    /*!< Byte 9 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
+    cardinfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
+    cardinfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
+    cardinfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
+    /*!< Byte 10 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
+    cardinfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
+    
+    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
+    cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
+    cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
+    cardinfo->CardCapacity *= cardinfo->CardBlockSize;
+  }
+  else if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    /*!< Byte 7 */
+    tmp = (uint8_t)(CSD_Tab[1] & 0x000000FF);
+    cardinfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
+
+    /*!< Byte 8 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0xFF000000) >> 24);
+
+    cardinfo->SD_csd.DeviceSize |= (tmp << 8);
+
+    /*!< Byte 9 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x00FF0000) >> 16);
+
+    cardinfo->SD_csd.DeviceSize |= (tmp);
+
+    /*!< Byte 10 */
+    tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8);
+    
+    cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) * 512 * 1024;
+    cardinfo->CardBlockSize = 512;    
+  }
+
+
+  cardinfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(CSD_Tab[2] & 0x000000FF);
+  cardinfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0xFF000000) >> 24);
+  cardinfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
+  cardinfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
+  cardinfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0x00FF0000) >> 16);
+  cardinfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
+  cardinfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.Reserved3 = 0;
+  cardinfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
+
+  /*!< Byte 14 */
+  tmp = (uint8_t)((CSD_Tab[3] & 0x0000FF00) >> 8);
+  cardinfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
+  cardinfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
+  cardinfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
+  cardinfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
+  cardinfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
+  cardinfo->SD_csd.ECC = (tmp & 0x03);
+
+  /*!< Byte 15 */
+  tmp = (uint8_t)(CSD_Tab[3] & 0x000000FF);
+  cardinfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
+  cardinfo->SD_csd.Reserved4 = 1;
+
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((CID_Tab[0] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ManufacturerID = tmp;
+
+  /*!< Byte 1 */
+  tmp = (uint8_t)((CID_Tab[0] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.OEM_AppliID = tmp << 8;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((CID_Tab[0] & 0x000000FF00) >> 8);
+  cardinfo->SD_cid.OEM_AppliID |= tmp;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)(CID_Tab[0] & 0x000000FF);
+  cardinfo->SD_cid.ProdName1 = tmp << 24;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)((CID_Tab[1] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdName1 |= tmp << 16;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)((CID_Tab[1] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.ProdName1 |= tmp << 8;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)((CID_Tab[1] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ProdName1 |= tmp;
+
+  /*!< Byte 7 */
+  tmp = (uint8_t)(CID_Tab[1] & 0x000000FF);
+  cardinfo->SD_cid.ProdName2 = tmp;
+
+  /*!< Byte 8 */
+  tmp = (uint8_t)((CID_Tab[2] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdRev = tmp;
+
+  /*!< Byte 9 */
+  tmp = (uint8_t)((CID_Tab[2] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.ProdSN = tmp << 24;
+
+  /*!< Byte 10 */
+  tmp = (uint8_t)((CID_Tab[2] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ProdSN |= tmp << 16;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(CID_Tab[2] & 0x000000FF);
+  cardinfo->SD_cid.ProdSN |= tmp << 8;
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)((CID_Tab[3] & 0xFF000000) >> 24);
+  cardinfo->SD_cid.ProdSN |= tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((CID_Tab[3] & 0x00FF0000) >> 16);
+  cardinfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
+  cardinfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
+
+  /*!< Byte 14 */
+  tmp = (uint8_t)((CID_Tab[3] & 0x0000FF00) >> 8);
+  cardinfo->SD_cid.ManufactDate |= tmp;
+
+  /*!< Byte 15 */
+  tmp = (uint8_t)(CID_Tab[3] & 0x000000FF);
+  cardinfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
+  cardinfo->SD_cid.Reserved2 = 1;
+  
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
+  *         card.
+  * @param  WideMode: Specifies the SD card wide bus mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
+  *     @arg SDIO_BusWide_4b: 4-bit data transfer
+  *     @arg SDIO_BusWide_1b: 1-bit data transfer
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  uint8_t tmp = 0;
+
+  errorstatus = SD_SendSDStatus((uint32_t *)SDSTATUS_Tab);
+
+  if (errorstatus  != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0xC0) >> 6);
+  cardstatus->DAT_BUS_WIDTH = tmp;
+
+  /*!< Byte 0 */
+  tmp = (uint8_t)((SDSTATUS_Tab[0] & 0x20) >> 5);
+  cardstatus->SECURED_MODE = tmp;
+
+  /*!< Byte 2 */
+  tmp = (uint8_t)((SDSTATUS_Tab[2] & 0xFF));
+  cardstatus->SD_CARD_TYPE = tmp << 8;
+
+  /*!< Byte 3 */
+  tmp = (uint8_t)((SDSTATUS_Tab[3] & 0xFF));
+  cardstatus->SD_CARD_TYPE |= tmp;
+
+  /*!< Byte 4 */
+  tmp = (uint8_t)(SDSTATUS_Tab[4] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA = tmp << 24;
+
+  /*!< Byte 5 */
+  tmp = (uint8_t)(SDSTATUS_Tab[5] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 16;
+
+  /*!< Byte 6 */
+  tmp = (uint8_t)(SDSTATUS_Tab[6] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp << 8;
+
+  /*!< Byte 7 */
+  tmp = (uint8_t)(SDSTATUS_Tab[7] & 0xFF);
+  cardstatus->SIZE_OF_PROTECTED_AREA |= tmp;
+
+  /*!< Byte 8 */
+  tmp = (uint8_t)((SDSTATUS_Tab[8] & 0xFF));
+  cardstatus->SPEED_CLASS = tmp;
+
+  /*!< Byte 9 */
+  tmp = (uint8_t)((SDSTATUS_Tab[9] & 0xFF));
+  cardstatus->PERFORMANCE_MOVE = tmp;
+
+  /*!< Byte 10 */
+  tmp = (uint8_t)((SDSTATUS_Tab[10] & 0xF0) >> 4);
+  cardstatus->AU_SIZE = tmp;
+
+  /*!< Byte 11 */
+  tmp = (uint8_t)(SDSTATUS_Tab[11] & 0xFF);
+  cardstatus->ERASE_SIZE = tmp << 8;
+
+  /*!< Byte 12 */
+  tmp = (uint8_t)(SDSTATUS_Tab[12] & 0xFF);
+  cardstatus->ERASE_SIZE |= tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0xFC) >> 2);
+  cardstatus->ERASE_TIMEOUT = tmp;
+
+  /*!< Byte 13 */
+  tmp = (uint8_t)((SDSTATUS_Tab[13] & 0x3));
+  cardstatus->ERASE_OFFSET = tmp;
+ 
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables wide bus opeartion for the requeseted card if supported by 
+  *         card.
+  * @param  WideMode: Specifies the SD card wide bus mode. 
+  *   This parameter can be one of the following values:
+  *     @arg SDIO_BusWide_8b: 8-bit data transfer (Only for MMC)
+  *     @arg SDIO_BusWide_4b: 4-bit data transfer
+  *     @arg SDIO_BusWide_1b: 1-bit data transfer
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< MMC Card doesn't support this feature */
+  if (SDIO_MULTIMEDIA_CARD == CardType)
+  {
+    errorstatus = SD_UNSUPPORTED_FEATURE;
+    return(errorstatus);
+  }
+  else if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    if (SDIO_BusWide_8b == WideMode)
+    {
+      errorstatus = SD_UNSUPPORTED_FEATURE;
+      return(errorstatus);
+    }
+    else if (SDIO_BusWide_4b == WideMode)
+    {
+      errorstatus = SDEnWideBus(ENABLE);
+
+      if (SD_OK == errorstatus)
+      {
+        /*!< Configure the SDIO peripheral */
+        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
+        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_4b;
+        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+        SDIO_Init(&SDIO_InitStructure);
+      }
+    }
+    else
+    {
+      errorstatus = SDEnWideBus(DISABLE);
+
+      if (SD_OK == errorstatus)
+      {
+        /*!< Configure the SDIO peripheral */
+        SDIO_InitStructure.SDIO_ClockDiv = SDIO_TRANSFER_CLK_DIV; 
+        SDIO_InitStructure.SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+        SDIO_InitStructure.SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+        SDIO_InitStructure.SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+        SDIO_InitStructure.SDIO_BusWide = SDIO_BusWide_1b;
+        SDIO_InitStructure.SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+        SDIO_Init(&SDIO_InitStructure);
+      }
+    }
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Selects od Deselects the corresponding card.
+  * @param  addr: Address of the Card to be selected.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SelectDeselect(uint32_t addr)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Send CMD7 SDIO_SEL_DESEL_CARD */
+  SDIO_CmdInitStructure.SDIO_Argument =  addr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEL_DESEL_CARD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SEL_DESEL_CARD);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to read one block from a specified address in a card. The Data
+  *         transfer can be managed by DMA mode or Polling mode. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.            
+  * @param  readbuff: pointer to the buffer that will contain the received data
+  * @param  ReadAddr: Address from where data are to be read.  
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize)
+{
+  SD_Error errorstatus = SD_OK;
+#if defined (SD_POLLING_MODE) 
+  uint32_t count = 0, *tempbuff = (uint32_t *)readbuff;
+#endif
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 0;
+  
+  SDIO->DCTRL = 0x0;
+
+  
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+  
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send CMD17 READ_SINGLE_BLOCK */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_READ_SINGLE_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+#if defined (SD_POLLING_MODE)  
+  /*!< In case of single block transfer, no need of stop transfer at all.*/
+  /*!< Polling mode */
+  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
+    {
+      for (count = 0; count < 8; count++)
+      {
+        *(tempbuff + count) = SDIO_ReadData();
+      }
+      tempbuff += 8;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+  count = SD_DATATIMEOUT;
+  while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
+  {
+    *tempbuff = SDIO_ReadData();
+    tempbuff++;
+    count--;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+#elif defined (SD_DMA_MODE)
+    SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+    SDIO_DMACmd(ENABLE);
+    SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, BlockSize);
+#endif
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to read blocks from a specified address  in a card.  The Data
+  *         transfer can be managed by DMA mode or Polling mode. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.   
+  * @param  readbuff: pointer to the buffer that will contain the received data.
+  * @param  ReadAddr: Address from where data are to be read.
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @param  NumberOfBlocks: number of blocks to be read.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SD_Error errorstatus = SD_OK;
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 1;
+	
+  SDIO->DCTRL = 0x0;
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    ReadAddr /= 512;
+  }
+
+  /*!< Set Block Size for Card */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+    
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send CMD18 READ_MULT_BLOCK with argument data address */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)ReadAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_READ_MULT_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_READ_MULT_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SDIO_DMACmd(ENABLE);
+  SD_LowLevel_DMA_RxConfig((uint32_t *)readbuff, (NumberOfBlocks * BlockSize));
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  *         This function should be called after SDIO_ReadMultiBlocks() function
+  *         to insure that all data sent by the card are already transferred by 
+  *         the DMA controller.
+  * @param  None.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WaitReadOperation(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0))
+  {
+    timeout--;
+  }
+  
+  DMAEndOfTransfer = 0x00;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while(((SDIO->STA & SDIO_FLAG_RXACT)) && (timeout > 0))
+  {
+    timeout--;  
+  }
+
+  if (StopCondition == 1)
+  {
+    errorstatus = SD_StopTransfer();
+  }
+  
+  if ((timeout == 0) && (errorstatus == SD_OK))
+  {
+    errorstatus = SD_DATA_TIMEOUT;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  if (TransferError != SD_OK)
+  {
+    return(TransferError);
+  }
+  else
+  {
+    return(errorstatus);  
+  }
+}
+
+/**
+  * @brief  Allows to write one block starting from a specified address in a card.
+  *         The Data transfer can be managed by DMA mode or Polling mode.
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.      
+  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
+  * @param  WriteAddr: Address from where data are to be read.   
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize)
+{
+  SD_Error errorstatus = SD_OK;
+
+#if defined (SD_POLLING_MODE)
+  uint32_t bytestransferred = 0, count = 0, restwords = 0;
+  uint32_t *tempbuff = (uint32_t *)writebuff;
+#endif
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 0;
+  
+  SDIO->DCTRL = 0x0;
+
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+    
+  /*!< Send CMD24 WRITE_SINGLE_BLOCK */
+  SDIO_CmdInitStructure.SDIO_Argument = WriteAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_WRITE_SINGLE_BLOCK);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< In case of single data block transfer no need of stop command at all */
+#if defined (SD_POLLING_MODE) 
+  while (!(SDIO->STA & (SDIO_FLAG_DBCKEND | SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_TXFIFOHE) != RESET)
+    {
+      if ((512 - bytestransferred) < 32)
+      {
+        restwords = ((512 - bytestransferred) % 4 == 0) ? ((512 - bytestransferred) / 4) : (( 512 -  bytestransferred) / 4 + 1);
+        for (count = 0; count < restwords; count++, tempbuff++, bytestransferred += 4)
+        {
+          SDIO_WriteData(*tempbuff);
+        }
+      }
+      else
+      {
+        for (count = 0; count < 8; count++)
+        {
+          SDIO_WriteData(*(tempbuff + count));
+        }
+        tempbuff += 8;
+        bytestransferred += 32;
+      }
+    }
+  }
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_TXUNDERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_TXUNDERR);
+    errorstatus = SD_TX_UNDERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+#elif defined (SD_DMA_MODE)
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, BlockSize);
+  SDIO_DMACmd(ENABLE);
+#endif
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to write blocks starting from a specified address in a card.
+  *         The Data transfer can be managed by DMA mode only. 
+  * @note   This operation should be followed by two functions to check if the 
+  *         DMA Controller and SD Card status.
+  *          - SD_ReadWaitOperation(): this function insure that the DMA
+  *            controller has finished all data transfer.
+  *          - SD_GetStatus(): to check that the SD Card has finished the 
+  *            data transfer and it is ready for data.     
+  * @param  WriteAddr: Address from where data are to be read.
+  * @param  writebuff: pointer to the buffer that contain the data to be transferred.
+  * @param  BlockSize: the SD card Data block size. The Block size should be 512.
+  * @param  NumberOfBlocks: number of blocks to be written.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  SD_Error errorstatus = SD_OK;
+
+  TransferError = SD_OK;
+  TransferEnd = 0;
+  StopCondition = 1;
+  
+  SDIO->DCTRL = 0x0;
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    BlockSize = 512;
+    WriteAddr /= 512;
+  }
+
+  /* Set Block Size for Card */ 
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) BlockSize;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+  
+  /*!< To improve performance */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) (RCA << 16);
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+  /*!< To improve performance */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)NumberOfBlocks;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCK_COUNT;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCK_COUNT);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+
+  /*!< Send CMD25 WRITE_MULT_BLOCK with argument data address */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)WriteAddr;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_WRITE_MULT_BLOCK);
+
+  if (SD_OK != errorstatus)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = NumberOfBlocks * BlockSize;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = (uint32_t) 9 << 4;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND | SDIO_IT_RXOVERR | SDIO_IT_STBITERR, ENABLE);
+  SDIO_DMACmd(ENABLE);
+  SD_LowLevel_DMA_TxConfig((uint32_t *)writebuff, (NumberOfBlocks * BlockSize));
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  *         This function should be called after SDIO_WriteBlock() and
+  *         SDIO_WriteMultiBlocks() function to insure that all data sent by the 
+  *         card are already transferred by the DMA controller.        
+  * @param  None.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_WaitWriteOperation(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while ((DMAEndOfTransfer == 0x00) && (TransferEnd == 0) && (TransferError == SD_OK) && (timeout > 0))
+  {
+    timeout--;
+  }
+  
+  DMAEndOfTransfer = 0x00;
+
+  timeout = SD_DATATIMEOUT;
+  
+  while(((SDIO->STA & SDIO_FLAG_TXACT)) && (timeout > 0))
+  {
+    timeout--;  
+  }
+
+  if (StopCondition == 1)
+  {
+    errorstatus = SD_StopTransfer();
+  }
+  
+  if ((timeout == 0) && (errorstatus == SD_OK))
+  {
+    errorstatus = SD_DATA_TIMEOUT;
+  }
+  
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+  
+  if (TransferError != SD_OK)
+  {
+    return(TransferError);
+  }
+  else
+  {
+    return(errorstatus);
+  }
+}
+
+/**
+  * @brief  Gets the cuurent data transfer state.
+  * @param  None
+  * @retval SDTransferState: Data Transfer state.
+  *   This value can be: 
+  *        - SD_TRANSFER_OK: No data transfer is acting
+  *        - SD_TRANSFER_BUSY: Data transfer is acting
+  */
+SDTransferState SD_GetTransferState(void)
+{
+  if (SDIO->STA & (SDIO_FLAG_TXACT | SDIO_FLAG_RXACT))
+  {
+    return(SD_TRANSFER_BUSY);
+  }
+  else
+  {
+    return(SD_TRANSFER_OK);
+  }
+}
+
+/**
+  * @brief  Aborts an ongoing data transfer.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_StopTransfer(void)
+{
+  SD_Error errorstatus = SD_OK;
+
+  /*!< Send CMD12 STOP_TRANSMISSION  */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_STOP_TRANSMISSION;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_STOP_TRANSMISSION);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to erase memory area specified for the given card.
+  * @param  startaddr: the start address.
+  * @param  endaddr: the end address.
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t delay = 0;
+  __IO uint32_t maxdelay = 0;
+  uint8_t cardstate = 0;
+
+  /*!< Check if the card coomnd class supports erase command */
+  if (((CSD_Tab[1] >> 20) & SD_CCCC_ERASE) == 0)
+  {
+    errorstatus = SD_REQUEST_NOT_APPLICABLE;
+    return(errorstatus);
+  }
+
+  maxdelay = 120000 / ((SDIO->CLKCR & 0xFF) + 2);
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  if (CardType == SDIO_HIGH_CAPACITY_SD_CARD)
+  {
+    startaddr /= 512;
+    endaddr /= 512;
+  }
+  
+  /*!< According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+  if ((SDIO_STD_CAPACITY_SD_CARD_V1_1 == CardType) || (SDIO_STD_CAPACITY_SD_CARD_V2_0 == CardType) || (SDIO_HIGH_CAPACITY_SD_CARD == CardType))
+  {
+    /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+    SDIO_CmdInitStructure.SDIO_Argument = startaddr;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_START;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_START);
+    if (errorstatus != SD_OK)
+    {
+      return(errorstatus);
+    }
+
+    /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+    SDIO_CmdInitStructure.SDIO_Argument = endaddr;
+    SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_ERASE_GRP_END;
+    SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+    SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+    SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+    errorstatus = CmdResp1Error(SD_CMD_SD_ERASE_GRP_END);
+    if (errorstatus != SD_OK)
+    {
+      return(errorstatus);
+    }
+  }
+
+  /*!< Send CMD38 ERASE */
+  SDIO_CmdInitStructure.SDIO_Argument = 0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_ERASE;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_ERASE);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  for (delay = 0; delay < maxdelay; delay++)
+  {}
+
+  /*!< Wait till the card is in programming state */
+  errorstatus = IsCardProgramming(&cardstate);
+  delay = SD_DATATIMEOUT;
+  while ((delay > 0) && (errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate)))
+  {
+    errorstatus = IsCardProgramming(&cardstate);
+    delay--;
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  pcardstatus: pointer to the buffer that will contain the SD card 
+  *         status (Card Status register).
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SendStatus(uint32_t *pcardstatus)
+{
+  SD_Error errorstatus = SD_OK;
+
+  if (pcardstatus == NULL)
+  {
+    errorstatus = SD_INVALID_PARAMETER;
+    return(errorstatus);
+  }
+
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SEND_STATUS);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  *pcardstatus = SDIO_GetResponse(SDIO_RESP1);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Returns the current SD card's status.
+  * @param  psdstatus: pointer to the buffer that will contain the SD card status 
+  *         (SD Status register).
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_SendSDStatus(uint32_t *psdstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t count = 0;
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  /*!< Set block size for card if it is not equal to current block size for card. */
+  SDIO_CmdInitStructure.SDIO_Argument = 64;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< CMD55 */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = 64;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_64b;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+  /*!< Send ACMD13 SD_APP_STAUS  with argument as card's RCA.*/
+  SDIO_CmdInitStructure.SDIO_Argument = 0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_STAUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+  errorstatus = CmdResp1Error(SD_CMD_SD_APP_STAUS);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  while (!(SDIO->STA &(SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXFIFOHF) != RESET)
+    {
+      for (count = 0; count < 8; count++)
+      {
+        *(psdstatus + count) = SDIO_ReadData();
+      }
+      psdstatus += 8;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+
+  count = SD_DATATIMEOUT;
+  while ((SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET) && (count > 0))
+  {
+    *psdstatus = SDIO_ReadData();
+    psdstatus++;
+    count--;
+  }
+  /*!< Clear all the static status flags*/
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Allows to process all the interrupts that are high.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+SD_Error SD_ProcessIRQSrc(void)
+{ 
+  if (SDIO_GetITStatus(SDIO_IT_DATAEND) != RESET)
+  {
+    TransferError = SD_OK;
+    SDIO_ClearITPendingBit(SDIO_IT_DATAEND);
+    TransferEnd = 1;
+  }  
+  else if (SDIO_GetITStatus(SDIO_IT_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_DCRCFAIL);
+    TransferError = SD_DATA_CRC_FAIL;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_DTIMEOUT);
+    TransferError = SD_DATA_TIMEOUT;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_RXOVERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_RXOVERR);
+    TransferError = SD_RX_OVERRUN;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_TXUNDERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_TXUNDERR);
+    TransferError = SD_TX_UNDERRUN;
+  }
+  else if (SDIO_GetITStatus(SDIO_IT_STBITERR) != RESET)
+  {
+    SDIO_ClearITPendingBit(SDIO_IT_STBITERR);
+    TransferError = SD_START_BIT_ERR;
+  }
+
+  SDIO_ITConfig(SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |
+                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |
+                SDIO_IT_RXOVERR | SDIO_IT_STBITERR, DISABLE);
+  return(TransferError);
+}
+
+/**
+  * @brief  This function waits until the SDIO DMA data transfer is finished. 
+  * @param  None.
+  * @retval None.
+  */
+void SD_ProcessDMAIRQ(void)
+{
+  if(DMA2->ISR & SD_SDIO_DMA_FLAG_TC)
+  {
+    DMAEndOfTransfer = 0x01;
+    DMA_ClearFlag(SD_SDIO_DMA_FLAG_TC | SD_SDIO_DMA_FLAG_TE | SD_SDIO_DMA_FLAG_HT | SD_SDIO_DMA_FLAG_GL);
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdError(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t timeout;
+
+  timeout = SDIO_CMD0TIMEOUT; /*!< 10000 */
+
+  while ((timeout > 0) && (SDIO_GetFlagStatus(SDIO_FLAG_CMDSENT) == RESET))
+  {
+    timeout--;
+  }
+
+  if (timeout == 0)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp7Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t timeout = SDIO_CMD0TIMEOUT;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) && (timeout > 0))
+  {
+    timeout--;
+    status = SDIO->STA;
+  }
+
+  if ((timeout == 0) || (status & SDIO_FLAG_CTIMEOUT))
+  {
+    /*!< Card is not V2.0 complient or card does not support the set voltage range */
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+
+  if (status & SDIO_FLAG_CMDREND)
+  {
+    /*!< Card is SD V2.0 compliant */
+    errorstatus = SD_OK;
+    SDIO_ClearFlag(SDIO_FLAG_CMDREND);
+    return(errorstatus);
+  }
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  cmd: The sent command index.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp1Error(uint8_t cmd)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t response_r1;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Check response received is of desired command */
+  if (SDIO_GetCommandResponse() != cmd)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  /*!< We have received response, retrieve it for analysis  */
+  response_r1 = SDIO_GetResponse(SDIO_RESP1);
+
+  if ((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return(errorstatus);
+  }
+
+  if (response_r1 & SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+
+  if (response_r1 & SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+
+  if (response_r1 & SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+
+  if (response_r1 & SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+
+  if (response_r1 & SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+
+  if (response_r1 & SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+
+  if (response_r1 & SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (response_r1 & SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+
+  if (response_r1 & SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+
+  if (response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (response_r1 & SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+
+  if (response_r1 & SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+
+  if (response_r1 & SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+
+  if (response_r1 & SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+
+  if (response_r1 & SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+
+  if (response_r1 & SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+
+  if (response_r1 & SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp3Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  None
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp2Error(void)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  cmd: The sent command index.
+  * @param  prca: pointer to the variable that will contain the SD card relative 
+  *         address RCA. 
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error CmdResp6Error(uint8_t cmd, uint16_t *prca)
+{
+  SD_Error errorstatus = SD_OK;
+  uint32_t status;
+  uint32_t response_r1;
+
+  status = SDIO->STA;
+
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  /*!< Check response received is of desired command */
+  if (SDIO_GetCommandResponse() != cmd)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  /*!< We have received response, retrieve it.  */
+  response_r1 = SDIO_GetResponse(SDIO_RESP1);
+
+  if (SD_ALLZERO == (response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)))
+  {
+    *prca = (uint16_t) (response_r1 >> 16);
+    return(errorstatus);
+  }
+
+  if (response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (response_r1 & SD_R6_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (response_r1 & SD_R6_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Enables or disables the SDIO wide bus mode.
+  * @param  NewState: new state of the SDIO wide bus mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error SDEnWideBus(FunctionalState NewState)
+{
+  SD_Error errorstatus = SD_OK;
+
+  uint32_t scr[2] = {0, 0};
+
+  if (SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED)
+  {
+    errorstatus = SD_LOCK_UNLOCK_FAILED;
+    return(errorstatus);
+  }
+
+  /*!< Get SCR Register */
+  errorstatus = FindSCR((uint16_t)RCA, scr);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< If wide bus operation to be enabled */
+  if (NewState == ENABLE)
+  {
+    /*!< If requested card supports wide bus operation */
+    if ((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+    {
+      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
+      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x2;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+      return(errorstatus);
+    }
+    else
+    {
+      errorstatus = SD_REQUEST_NOT_APPLICABLE;
+      return(errorstatus);
+    }
+  }   /*!< If wide bus operation to be disabled */
+  else
+  {
+    /*!< If requested card supports 1 bit mode operation */
+    if ((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+    {
+      /*!< Send CMD55 APP_CMD with argument as card's RCA.*/
+      SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
+      SDIO_CmdInitStructure.SDIO_Argument = 0x00;
+      SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
+      SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+      SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+      SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+      SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+      errorstatus = CmdResp1Error(SD_CMD_APP_SD_SET_BUSWIDTH);
+
+      if (errorstatus != SD_OK)
+      {
+        return(errorstatus);
+      }
+
+      return(errorstatus);
+    }
+    else
+    {
+      errorstatus = SD_REQUEST_NOT_APPLICABLE;
+      return(errorstatus);
+    }
+  }
+}
+
+/**
+  * @brief  Checks if the SD card is in programming state.
+  * @param  pstatus: pointer to the variable that will contain the SD card state.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error IsCardProgramming(uint8_t *pstatus)
+{
+  SD_Error errorstatus = SD_OK;
+  __IO uint32_t respR1 = 0, status = 0;
+
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SEND_STATUS;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  status = SDIO->STA;
+  while (!(status & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)))
+  {
+    status = SDIO->STA;
+  }
+
+  if (status & SDIO_FLAG_CTIMEOUT)
+  {
+    errorstatus = SD_CMD_RSP_TIMEOUT;
+    SDIO_ClearFlag(SDIO_FLAG_CTIMEOUT);
+    return(errorstatus);
+  }
+  else if (status & SDIO_FLAG_CCRCFAIL)
+  {
+    errorstatus = SD_CMD_CRC_FAIL;
+    SDIO_ClearFlag(SDIO_FLAG_CCRCFAIL);
+    return(errorstatus);
+  }
+
+  status = (uint32_t)SDIO_GetCommandResponse();
+
+  /*!< Check response received is of desired command */
+  if (status != SD_CMD_SEND_STATUS)
+  {
+    errorstatus = SD_ILLEGAL_CMD;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+
+  /*!< We have received response, retrieve it for analysis  */
+  respR1 = SDIO_GetResponse(SDIO_RESP1);
+
+  /*!< Find out card status */
+  *pstatus = (uint8_t) ((respR1 >> 9) & 0x0000000F);
+
+  if ((respR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
+  {
+    return(errorstatus);
+  }
+
+  if (respR1 & SD_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return(SD_ADDR_OUT_OF_RANGE);
+  }
+
+  if (respR1 & SD_OCR_ADDR_MISALIGNED)
+  {
+    return(SD_ADDR_MISALIGNED);
+  }
+
+  if (respR1 & SD_OCR_BLOCK_LEN_ERR)
+  {
+    return(SD_BLOCK_LEN_ERR);
+  }
+
+  if (respR1 & SD_OCR_ERASE_SEQ_ERR)
+  {
+    return(SD_ERASE_SEQ_ERR);
+  }
+
+  if (respR1 & SD_OCR_BAD_ERASE_PARAM)
+  {
+    return(SD_BAD_ERASE_PARAM);
+  }
+
+  if (respR1 & SD_OCR_WRITE_PROT_VIOLATION)
+  {
+    return(SD_WRITE_PROT_VIOLATION);
+  }
+
+  if (respR1 & SD_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return(SD_LOCK_UNLOCK_FAILED);
+  }
+
+  if (respR1 & SD_OCR_COM_CRC_FAILED)
+  {
+    return(SD_COM_CRC_FAILED);
+  }
+
+  if (respR1 & SD_OCR_ILLEGAL_CMD)
+  {
+    return(SD_ILLEGAL_CMD);
+  }
+
+  if (respR1 & SD_OCR_CARD_ECC_FAILED)
+  {
+    return(SD_CARD_ECC_FAILED);
+  }
+
+  if (respR1 & SD_OCR_CC_ERROR)
+  {
+    return(SD_CC_ERROR);
+  }
+
+  if (respR1 & SD_OCR_GENERAL_UNKNOWN_ERROR)
+  {
+    return(SD_GENERAL_UNKNOWN_ERROR);
+  }
+
+  if (respR1 & SD_OCR_STREAM_READ_UNDERRUN)
+  {
+    return(SD_STREAM_READ_UNDERRUN);
+  }
+
+  if (respR1 & SD_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return(SD_STREAM_WRITE_OVERRUN);
+  }
+
+  if (respR1 & SD_OCR_CID_CSD_OVERWRIETE)
+  {
+    return(SD_CID_CSD_OVERWRITE);
+  }
+
+  if (respR1 & SD_OCR_WP_ERASE_SKIP)
+  {
+    return(SD_WP_ERASE_SKIP);
+  }
+
+  if (respR1 & SD_OCR_CARD_ECC_DISABLED)
+  {
+    return(SD_CARD_ECC_DISABLED);
+  }
+
+  if (respR1 & SD_OCR_ERASE_RESET)
+  {
+    return(SD_ERASE_RESET);
+  }
+
+  if (respR1 & SD_OCR_AKE_SEQ_ERROR)
+  {
+    return(SD_AKE_SEQ_ERROR);
+  }
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Find the SD card SCR register value.
+  * @param  rca: selected card address.
+  * @param  pscr: pointer to the buffer that will contain the SCR value.
+  * @retval SD_Error: SD Card Error code.
+  */
+static SD_Error FindSCR(uint16_t rca, uint32_t *pscr)
+{
+  uint32_t index = 0;
+  SD_Error errorstatus = SD_OK;
+  uint32_t tempscr[2] = {0, 0};
+
+  /*!< Set Block Size To 8 Bytes */
+  /*!< Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t)8;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SET_BLOCKLEN;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SET_BLOCKLEN);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  /*!< Send CMD55 APP_CMD with argument as card's RCA */
+  SDIO_CmdInitStructure.SDIO_Argument = (uint32_t) RCA << 16;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_APP_CMD;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_APP_CMD);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+  SDIO_DataInitStructure.SDIO_DataTimeOut = SD_DATATIMEOUT;
+  SDIO_DataInitStructure.SDIO_DataLength = 8;
+  SDIO_DataInitStructure.SDIO_DataBlockSize = SDIO_DataBlockSize_8b;
+  SDIO_DataInitStructure.SDIO_TransferDir = SDIO_TransferDir_ToSDIO;
+  SDIO_DataInitStructure.SDIO_TransferMode = SDIO_TransferMode_Block;
+  SDIO_DataInitStructure.SDIO_DPSM = SDIO_DPSM_Enable;
+  SDIO_DataConfig(&SDIO_DataInitStructure);
+
+
+  /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
+  SDIO_CmdInitStructure.SDIO_Argument = 0x0;
+  SDIO_CmdInitStructure.SDIO_CmdIndex = SD_CMD_SD_APP_SEND_SCR;
+  SDIO_CmdInitStructure.SDIO_Response = SDIO_Response_Short;
+  SDIO_CmdInitStructure.SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStructure.SDIO_CPSM = SDIO_CPSM_Enable;
+  SDIO_SendCommand(&SDIO_CmdInitStructure);
+
+  errorstatus = CmdResp1Error(SD_CMD_SD_APP_SEND_SCR);
+
+  if (errorstatus != SD_OK)
+  {
+    return(errorstatus);
+  }
+
+  while (!(SDIO->STA & (SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)))
+  {
+    if (SDIO_GetFlagStatus(SDIO_FLAG_RXDAVL) != RESET)
+    {
+      *(tempscr + index) = SDIO_ReadData();
+      index++;
+    }
+  }
+
+  if (SDIO_GetFlagStatus(SDIO_FLAG_DTIMEOUT) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DTIMEOUT);
+    errorstatus = SD_DATA_TIMEOUT;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_DCRCFAIL) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_DCRCFAIL);
+    errorstatus = SD_DATA_CRC_FAIL;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_RXOVERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_RXOVERR);
+    errorstatus = SD_RX_OVERRUN;
+    return(errorstatus);
+  }
+  else if (SDIO_GetFlagStatus(SDIO_FLAG_STBITERR) != RESET)
+  {
+    SDIO_ClearFlag(SDIO_FLAG_STBITERR);
+    errorstatus = SD_START_BIT_ERR;
+    return(errorstatus);
+  }
+
+  /*!< Clear all the static flags */
+  SDIO_ClearFlag(SDIO_STATIC_FLAGS);
+
+  *(pscr + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
+
+  *(pscr) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
+
+  return(errorstatus);
+}
+
+/**
+  * @brief  Converts the number of bytes in power of two and returns the power.
+  * @param  NumberOfBytes: number of bytes.
+  * @retval None
+  */
+uint8_t convert_from_bytes_to_power_of_two(uint16_t NumberOfBytes)
+{
+  uint8_t count = 0;
+
+  while (NumberOfBytes != 1)
+  {
+    NumberOfBytes >>= 1;
+    count++;
+  }
+  return(count);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.h
new file mode 100644
index 0000000..942c72c
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_sdio_sd.h
@@ -0,0 +1,406 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_sdio_sd.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the SD Card 
+  *          stm32l152d_eval_sdio_sd driver firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152D_EVAL_SDIO_SD_H
+#define __STM32L152D_EVAL_SDIO_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152D_EVAL_SDIO_SD
+  * @{
+  */  
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Exported_Types
+  * @{
+  */ 
+typedef enum
+{
+/** 
+  * @brief  SDIO specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1), /*!< Command response received (but CRC check failed) */
+  SD_DATA_CRC_FAIL                   = (2), /*!< Data bock sent/received (CRC check Failed) */
+  SD_CMD_RSP_TIMEOUT                 = (3), /*!< Command response timeout */
+  SD_DATA_TIMEOUT                    = (4), /*!< Data time out */
+  SD_TX_UNDERRUN                     = (5), /*!< Transmit FIFO under-run */
+  SD_RX_OVERRUN                      = (6), /*!< Receive FIFO over-run */
+  SD_START_BIT_ERR                   = (7), /*!< Start bit not detected on all data signals in widE bus mode */
+  SD_CMD_OUT_OF_RANGE                = (8), /*!< CMD's argument was out of range.*/
+  SD_ADDR_MISALIGNED                 = (9), /*!< Misaligned address */
+  SD_BLOCK_LEN_ERR                   = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11), /*!< An error in the sequence of erase command occurs.*/
+  SD_BAD_ERASE_PARAM                 = (12), /*!< An Invalid selection for erase groups */
+  SD_WRITE_PROT_VIOLATION            = (13), /*!< Attempt to program a write protect block */
+  SD_LOCK_UNLOCK_FAILED              = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15), /*!< CRC check of the previous command failed */
+  SD_ILLEGAL_CMD                     = (16), /*!< Command is not legal for the card state */
+  SD_CARD_ECC_FAILED                 = (17), /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18), /*!< Internal card controller error */
+  SD_GENERAL_UNKNOWN_ERROR           = (19), /*!< General or Unknown error */
+  SD_STREAM_READ_UNDERRUN            = (20), /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21), /*!< The card could not sustain data programming in stream mode */
+  SD_CID_CSD_OVERWRITE               = (22), /*!< CID/CSD overwrite error */
+  SD_WP_ERASE_SKIP                   = (23), /*!< only partial address space was erased */
+  SD_CARD_ECC_DISABLED               = (24), /*!< Command has been executed without using internal ECC */
+  SD_ERASE_RESET                     = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26), /*!< Error in sequence of authentication. */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDIO_DISABLED                   = (30),
+  SD_SDIO_FUNCTION_BUSY              = (31),
+  SD_SDIO_FUNCTION_FAILED            = (32),
+  SD_SDIO_UNKNOWN_FUNCTION           = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR, 
+  SD_NOT_CONFIGURED,
+  SD_REQUEST_PENDING, 
+  SD_REQUEST_NOT_APPLICABLE, 
+  SD_INVALID_PARAMETER,  
+  SD_UNSUPPORTED_FEATURE,  
+  SD_UNSUPPORTED_HW,  
+  SD_ERROR,  
+  SD_OK = 0 
+} SD_Error;
+
+/** 
+  * @brief  SDIO Transfer state  
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK  = 0,
+  SD_TRANSFER_BUSY = 1,
+  SD_TRANSFER_ERROR
+} SDTransferState;
+
+/** 
+  * @brief  SD Card States 
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)
+}SDCardState;
+
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card Status 
+  */
+typedef struct
+{
+  __IO uint8_t DAT_BUS_WIDTH;
+  __IO uint8_t SECURED_MODE;
+  __IO uint16_t SD_CARD_TYPE;
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;
+  __IO uint8_t SPEED_CLASS;
+  __IO uint8_t PERFORMANCE_MOVE;
+  __IO uint8_t AU_SIZE;
+  __IO uint16_t ERASE_SIZE;
+  __IO uint8_t ERASE_TIMEOUT;
+  __IO uint8_t ERASE_OFFSET;
+} SD_CardStatus;
+
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint64_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+  uint16_t RCA;
+  uint8_t CardType;
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief SDIO Commands  Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)
+#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)
+#define SD_CMD_SEND_CID                            ((uint8_t)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11) /*!< SD Card doesn't support it */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14)
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20) /*!< SD Card doesn't support it */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23) /*!< SD Card doesn't support it */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)
+#define SD_CMD_PROG_CID                            ((uint8_t)26) /*!< reserved for manufacturers */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32) /*!< To set the address of the first write
+                                                                  block to be erased. (For SD card only) */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For SD card only) */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35) /*!< To set the address of the first write block to be erased.
+                                                                  (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36) /*!< To set the address of the last write block of the
+                                                                  continuous range to be erased. (For MMC card only spec 3.31) */
+
+#define SD_CMD_ERASE                               ((uint8_t)38)
+#define SD_CMD_FAST_IO                             ((uint8_t)39) /*!< SD Card doesn't support it */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40) /*!< SD Card doesn't support it */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)
+#define SD_CMD_APP_CMD                             ((uint8_t)55)
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)
+#define SD_CMD_NO_CMD                              ((uint8_t)64)
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)  /*!< For SD Card only */
+#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22) /*!< For SD Card only */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51) /*!< For SD Card only */
+#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52) /*!< For SD I/O Card only */
+#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53) /*!< For SD I/O Card only */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDIO_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47) /*!< For SD Card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38) /*!< For SD Card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49) /*!< For SD Card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48) /*!< For SD Card only */
+  
+/* Uncomment the following line to select the SDIO Data transfer mode */  
+#if !defined (SD_DMA_MODE) && !defined (SD_POLLING_MODE)
+#define SD_DMA_MODE                                ((uint32_t)0x00000000)
+/*#define SD_POLLING_MODE                            ((uint32_t)0x00000002)*/
+#endif
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT                                 ((uint8_t)0x01)
+#define SD_NOT_PRESENT                             ((uint8_t)0x00)
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define SDIO_MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_SDIO_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);
+SD_Error SD_Init(void);
+SDTransferState SD_GetStatus(void);
+SDCardState SD_GetState(void);
+uint8_t SD_Detect(void);
+SD_Error SD_PowerON(void);
+SD_Error SD_PowerOFF(void);
+SD_Error SD_InitializeCards(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_GetCardStatus(SD_CardStatus *cardstatus);
+SD_Error SD_EnableWideBusOperation(uint32_t WideMode);
+SD_Error SD_SelectDeselect(uint32_t addr);
+SD_Error SD_ReadBlock(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t *readbuff, uint64_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t *writebuff, uint64_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SDTransferState SD_GetTransferState(void);
+SD_Error SD_StopTransfer(void);
+SD_Error SD_Erase(uint32_t startaddr, uint32_t endaddr);
+SD_Error SD_SendStatus(uint32_t *pcardstatus);
+SD_Error SD_SendSDStatus(uint32_t *psdstatus);
+SD_Error SD_ProcessIRQSrc(void);
+void SD_ProcessDMAIRQ(void);
+SD_Error SD_WaitReadOperation(void);
+SD_Error SD_WaitWriteOperation(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152D_EVAL_SDIO_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.c
new file mode 100644
index 0000000..9c23813
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.c
@@ -0,0 +1,476 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_spi_ee.c
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to manage the SPI M95xxx
+  *          EEPROM memory mounted on STM32L152D-EVAL board (refer to stm32l152d_eval.h
+  *          to know about the boards supporting this memory). 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32 hardware resources (SPI and 
+  *          GPIO) are defined in stm32l152d_eval.h file, and the initialization is 
+  *          performed in SPI_sEE_LowLevel_Init() function declared in stm32l152d_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SPI_sEE_LowLevel_Init() function.
+  *            
+  *          +-----------------------------------------------------------+
+  *          |                     Pin assignment                        |
+  *          +-----------------------------+---------------+-------------+
+  *          |  STM32 SPI Pins             |      sEE      |    Pin      |
+  *          +-----------------------------+---------------+-------------+
+  *          | sEE_CS_PIN                  | ChipSelect    |    1 (/S)   |
+  *          | sEE_MISO_PIN / MISO         |   DataOut     |    2 (Q)    |
+  *          | sEE_WP_PIN                  | WriteProtect  |    3 (/W)   |
+  *          |                             |   GND         |    4 (0 V)  |
+  *          | sEE_MOSI_PIN / MOSI         |   DataIn      |    5 (D)    |
+  *          | sEE_SCK_PIN / SCLK          |   Clock       |    6 (C)    |
+  *          |                             |   Hold        |    7 (/HOLD)|
+  *          |                             |   VCC         |    8 (3.3 V)|  
+  *          +-----------------------------+---------------+-------------+  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval_spi_ee.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152D_EVAL_SPI_EEPROM
+  * @brief      This file includes the M95xxx SPI EEPROM driver of STM32-EVAL boards.
+  * @{
+  */  
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Defines
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Function_Prototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the peripherals used by the SPI EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_DeInit(void)
+{
+  sEE_SPI_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the peripherals used by the SPI EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_Init(void)
+{
+  sEE_SPI_LowLevel_Init();
+    
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+}
+
+/**
+  * @brief  Writes more than one byte to the EEPROM with a single WRITE cycle 
+  *         (Page WRITE sequence).
+  * @note   The number of byte can't exceed the EEPROM page size.
+  * @param  pBuffer: pointer to the buffer  containing the data to be written
+  *         to the EEPROM.
+  * @param  WriteAddr: EEPROM's internal address to write to.
+  * @param  NumByteToWrite: number of bytes to write to the EEPROM, must be equal
+  *         or less than "sEE_PAGESIZE" value.
+  * @retval None
+  */
+uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t* NumByteToWrite)
+{
+  /*!< Enable the write access to the EEPROM */
+  sEE_WriteEnable();
+  
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+
+  /*!< Send "Write to Memory" instruction and MSB of WriteAddr  */
+  sEE_SendByte(sEE_CMD_WRITE | (uint8_t)((WriteAddr & 0x0100)>>5));
+  
+  /*!< Send WriteAddr address byte to write to */
+  sEE_SendByte(WriteAddr & 0xFF);
+  
+  /*!< while there is data to be written on the EEPROM */
+  while ((*NumByteToWrite)--)
+  {
+    /*!< Send the current byte */
+    sEE_SendByte(*pBuffer);
+    /*!< Point on the next byte to be written */
+    pBuffer++;
+  }
+  
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+  
+  /*!< Wait the end of EEPROM writing */
+  sEE_WaitEepromStandbyState();
+  
+  /*!< Disable the write access to the EEROM */
+  sEE_WriteDisable();
+  
+  return 0;
+}
+
+/**
+  * @brief  Writes block of data to the EEPROM. In this function, the number of
+  *         WRITE cycles are reduced, using Page WRITE sequence.
+  * @param  pBuffer: pointer to the buffer  containing the data to be written
+  *         to the EEPROM.
+  * @param  WriteAddr: EEPROM's internal address to write to.
+  * @param  NumByteToWrite: number of bytes to write to the EEPROM.
+  * @retval None
+  */
+void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
+{
+  uint16_t NumOfPage = 0, NumOfSingle = 0, Addr = 0, count = 0, temp = 0;
+  uint16_t   sEE_DataNum = 0;
+  
+  Addr = WriteAddr % sEE_PAGESIZE;
+  count = sEE_PAGESIZE - Addr;
+  NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
+  NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
+
+  if (Addr == 0) /*!< WriteAddr is sEE_PAGESIZE aligned  */
+  {
+    if (NumOfPage == 0) /*!< NumByteToWrite < sEE_PAGESIZE */
+    {
+      sEE_DataNum = NumByteToWrite;      
+      sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+    }
+    else /*!< NumByteToWrite > sEE_PAGESIZE */
+    {
+      while (NumOfPage--)
+      {
+        sEE_DataNum = sEE_PAGESIZE;
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+        WriteAddr +=  sEE_PAGESIZE;
+        pBuffer += sEE_PAGESIZE;
+      }
+      
+      sEE_DataNum = NumOfSingle;
+      sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+    }
+  }
+  else /*!< WriteAddr is not sEE_PAGESIZE aligned  */
+  {
+    if (NumOfPage == 0) /*!< NumByteToWrite < sEE_PAGESIZE */
+    {
+      if (NumOfSingle > count) /*!< (NumByteToWrite + WriteAddr) > sEE_PAGESIZE */
+      {
+        temp = NumOfSingle - count;
+        sEE_DataNum = count;
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+        WriteAddr +=  count;
+        pBuffer += count;
+        
+        sEE_DataNum = temp;
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+      }
+      else
+      {
+        sEE_DataNum = NumByteToWrite; 
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+      }
+    }
+    else /*!< NumByteToWrite > sEE_PAGESIZE */
+    {
+      NumByteToWrite -= count;
+      NumOfPage =  NumByteToWrite / sEE_PAGESIZE;
+      NumOfSingle = NumByteToWrite % sEE_PAGESIZE;
+
+      sEE_DataNum = count;
+        
+      sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+      WriteAddr +=  count;
+      pBuffer += count;
+
+      while (NumOfPage--)
+      {
+        sEE_DataNum = sEE_PAGESIZE;
+        
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+        WriteAddr +=  sEE_PAGESIZE;
+        pBuffer += sEE_PAGESIZE;
+      }
+
+      if (NumOfSingle != 0)
+      {
+        sEE_DataNum = NumOfSingle;
+        
+        sEE_WritePage(pBuffer, WriteAddr, &sEE_DataNum);
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Reads a block of data from the EEPROM.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the EEPROM.
+  * @param  ReadAddr: EEPROM's internal address to read from.
+  * @param  NumByteToRead: number of bytes to read from the EEPROM.
+  * @retval None
+  */
+uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead)
+{
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+  
+  /*!< Send "Read from Memory" instruction and MSB of WriteAddr  */
+  sEE_SendByte(sEE_CMD_READ | (uint8_t)((ReadAddr & 0x100)>>5));
+
+  /*!< Send WriteAddr address byte to write to */
+  sEE_SendByte(ReadAddr & 0xFF);
+  
+  while ((*NumByteToRead)--) /*!< while there is data to be read */
+  {
+    /*!< Read a byte from the EEPROM */
+    *pBuffer = sEE_SendByte(sEE_DUMMY_BYTE);
+    /*!< Point to the next location where the byte read will be saved */
+    pBuffer++;
+  }
+  
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+  
+  return 0;
+}
+
+
+/**
+  * @brief  Reads a byte from the SPI EEPROM.
+  * @note   This function must be used only if the Start_Read_Sequence function
+  *         has been previously called.
+  * @param  None
+  * @retval Byte Read from the SPI EEPROM.
+  */
+uint8_t sEE_ReadByte(void)
+{
+  return (sEE_SendByte(sEE_DUMMY_BYTE));
+}
+
+/**
+  * @brief  Sends a byte through the SPI interface and return the byte received
+  *         from the SPI bus.
+  * @param  byte: byte to send.
+  * @retval The value of the received byte.
+  */
+uint8_t sEE_SendByte(uint8_t byte)
+{
+  /*!< Loop while DR register in not empty */
+  while (SPI_I2S_GetFlagStatus(sEE_SPI, SPI_I2S_FLAG_TXE) == RESET);
+
+  /*!< Send byte through the SPI peripheral */
+  SPI_SendData(sEE_SPI, byte);
+
+  /*!< Wait to receive a byte */
+  while (SPI_I2S_GetFlagStatus(sEE_SPI, SPI_I2S_FLAG_RXNE) == RESET);
+
+  /*!< Return the byte read from the SPI bus */
+  return (uint8_t)SPI_ReceiveData(sEE_SPI);
+}
+/**
+  * @brief  Enables the write access to the EEPROM.
+  * @param  None
+  * @retval None
+  */
+void sEE_WriteEnable(void)
+{
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+
+  /*!< Send "Write Enable" instruction */
+  sEE_SendByte(sEE_CMD_WREN);
+
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+}
+
+/**
+  * @brief  Disables the write access to the EEPROM.
+  * @param  None
+  * @retval None
+  */
+void sEE_WriteDisable(void)
+{
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+
+  /*!< Send "Write Disable" instruction */
+  sEE_SendByte(sEE_CMD_WRDI);
+
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+}
+
+/**
+  * @brief  Write new value in EEPROM Status Register.
+  * @param  regval : new value of register
+  * @retval None
+  */
+void sEE_WriteStatusRegister(uint8_t regval)
+{
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+
+  /*!< Enable the write access to the EEPROM */
+  sEE_WriteEnable();
+  
+  /*!< Send "Write Status Register" instruction */
+  sEE_SendByte(sEE_CMD_WRSR);
+  
+  /*!< Write regval in status register */
+  sEE_SendByte(regval);  
+
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+}
+
+/**
+  * @brief  Read EEPROM Status Register.
+  * @param  None
+  * @retval The value of the Status register.
+  */
+uint8_t sEE_ReadStatusRegister(void)
+{
+  uint8_t sEEstatus = 0;
+  
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+  
+  /*!< Send "Read Status Register" instruction */
+  sEE_SendByte(sEE_CMD_RDSR);
+  
+  /*!< Send a dummy byte to generate the clock needed by the EEPROM
+  and put the value of the status register in EEPROM Status variable */
+  sEEstatus = sEE_SendByte(sEE_DUMMY_BYTE);
+  
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+  
+  return sEEstatus;
+}
+
+/**
+  * @brief  Polls the status of the Write In Progress (WIP) flag in the EEPROM's
+  *         status register and loop until write operation has completed.
+  * @param  None
+  * @retval None
+  */
+uint32_t sEE_WaitEepromStandbyState(void)      
+{
+  uint8_t sEEstatus = 0;
+
+  /*!< Select the EEPROM: Chip Select low */
+  sEE_CS_LOW();
+
+  /*!< Send "Read Status Register" instruction */
+  sEE_SendByte(sEE_CMD_RDSR);
+
+  /*!< Loop as long as the memory is busy with a write cycle */
+  do
+  {
+    /*!< Send a dummy byte to generate the clock needed by the EEPROM
+    and put the value of the status register in EEPROM Status variable */
+    sEEstatus = sEE_SendByte(sEE_DUMMY_BYTE);
+
+  }
+  while ((sEEstatus & sEE_WIP_FLAG) == SET); /* Write in progress */
+
+  /*!< Deselect the EEPROM: Chip Select high */
+  sEE_CS_HIGH();
+  
+  return 0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.h
new file mode 100644
index 0000000..f1abfac
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152D_EVAL/stm32l152d_eval_spi_ee.h
@@ -0,0 +1,156 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152d_eval_spi_ee.h
+  * @author  MCD Application Team
+  * @version V1.0.1
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the stm32l152d_eval_spi_ee
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152D_EVAL_SPI_EE_H
+#define __STM32L152D_EVAL_SPI_EE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152d_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152D_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32L152D_EVAL_SPI_EEPROM
+  * @{
+  */  
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Exported_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+  
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Exported_Constants
+  * @{
+  */
+/**
+  * @brief  M95 SPI EEPROM supported commands
+  */  
+#define sEE_CMD_WREN           0x06  /*!< Write enable instruction */
+#define sEE_CMD_WRDI           0x04  /*!< Write disable instruction */
+#define sEE_CMD_RDSR           0x05  /*!< Read Status Register instruction  */
+#define sEE_CMD_WRSR           0x01  /*!< Write Status Register instruction */
+#define sEE_CMD_WRITE          0x02  /*!< Write to Memory instruction */
+#define sEE_CMD_READ           0x03  /*!< Read from Memory instruction */
+
+/**
+ * @brief  M95040 SPI EEPROM defines
+ */  
+#define sEE_WIP_FLAG           0x01  /*!< Write In Progress (WIP) flag */
+
+#define sEE_DUMMY_BYTE         0xA5
+
+#define sEE_PAGESIZE           16
+
+
+  
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Exported_Macros
+  * @{
+  */
+/**
+  * @brief  Select EEPROM: Chip Select pin low
+  */
+#define sEE_CS_LOW()       GPIO_ResetBits(sEE_SPI_CS_GPIO_PORT, sEE_SPI_CS_PIN)
+/**
+  * @brief  Deselect EEPROM: Chip Select pin high
+  */
+#define sEE_CS_HIGH()      GPIO_SetBits(sEE_SPI_CS_GPIO_PORT, sEE_SPI_CS_PIN)   
+/**
+  * @}
+  */
+
+
+
+/** @defgroup STM32L152D_EVAL_SPI_EEPROM_Exported_Functions
+  * @{
+  */
+/**
+  * @brief  High layer functions
+  */
+void     sEE_DeInit(void);
+void     sEE_Init(void);
+uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead);
+void     sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite);
+uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t* NumByteToWrite);
+uint32_t sEE_WaitEepromStandbyState(void);
+
+/**
+  * @brief  Low layer functions
+  */
+uint8_t sEE_ReadByte(void);
+uint8_t sEE_SendByte(uint8_t byte);
+void sEE_WriteEnable(void);
+void sEE_WriteDisable(void);
+void sEE_WriteStatusRegister(uint8_t regval);
+uint8_t sEE_ReadStatusRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152D_EVAL_SPI_EE_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
new file mode 100644
index 0000000..0ef5928
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.c
@@ -0,0 +1,740 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval.c
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file provides:
+  *            - set of firmware functions to manage Leds, push-button and COM ports
+  *            - low level initialization functions for SD card (on SPI) and
+  *              temperature sensor (LM75) available on STM32L152-EVAL 
+  *              evaluation board RevB from STMicroelectronics.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval.h"
+#include "stm32l1xx_spi.h"
+#include "stm32l1xx_i2c.h"
+
+/** @addtogroup Utilities
+  * @{
+  */ 
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */   
+    
+/** @defgroup STM32L152_EVAL_LOW_LEVEL 
+  * @brief This file provides firmware functions to manage Leds, push-buttons, 
+  *        COM ports, SD card on SPI and temperature sensor (LM75) available on 
+  *        STM32L152-EVAL evaluation board from STMicroelectronics.
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables
+  * @{
+  */ 
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+                                 LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,
+                                 LED4_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+                                 LED4_GPIO_CLK};
+
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; 
+
+const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
+                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,
+                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; 
+
+const uint32_t BUTTON_CLK[BUTTONn] = {KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};
+
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {KEY_BUTTON_EXTI_LINE,
+                                            RIGHT_BUTTON_EXTI_LINE,
+                                            LEFT_BUTTON_EXTI_LINE,
+                                            UP_BUTTON_EXTI_LINE,
+                                            DOWN_BUTTON_EXTI_LINE,
+                                            SEL_BUTTON_EXTI_LINE};
+
+const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PORT_SOURCE,
+                                             RIGHT_BUTTON_EXTI_PORT_SOURCE,
+                                             LEFT_BUTTON_EXTI_PORT_SOURCE,
+                                             UP_BUTTON_EXTI_PORT_SOURCE,
+                                             DOWN_BUTTON_EXTI_PORT_SOURCE,
+                                             SEL_BUTTON_EXTI_PORT_SOURCE};
+								 
+const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {KEY_BUTTON_EXTI_PIN_SOURCE,
+                                            RIGHT_BUTTON_EXTI_PIN_SOURCE,
+                                            LEFT_BUTTON_EXTI_PIN_SOURCE,
+                                            UP_BUTTON_EXTI_PIN_SOURCE,
+                                            DOWN_BUTTON_EXTI_PIN_SOURCE,
+                                            SEL_BUTTON_EXTI_PIN_SOURCE}; 
+                                             
+const uint8_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,
+                                      LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,
+                                      DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};
+
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; 
+
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};
+ 
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};
+
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
+
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};
+ 
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};
+
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};
+
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
+ 
+const uint8_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};
+
+const uint8_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};
+ 
+const uint8_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};
+ 
+const uint8_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};
+
+DMA_InitTypeDef   sEEDMA_InitStructure;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures LED GPIO.
+  * @param  Led: Specifies the Led to be configured. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4
+  * @retval None
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  /* Enable the GPIO_LED Clock */
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+  /* Configure the GPIO_LED pin */
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED On.
+  * @param  Led: Specifies the Led to be set on. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Turns selected LED Off.
+  * @param  Led: Specifies the Led to be set off. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4 
+  * @retval None
+  */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];  
+}
+
+/**
+  * @brief  Toggles the selected LED.
+  * @param  Led: Specifies the Led to be toggled. 
+  *   This parameter can be one of following parameters:
+  *     @arg LED1
+  *     @arg LED2
+  *     @arg LED3
+  *     @arg LED4  
+  * @retval None
+  */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+  * @brief  Configures Button GPIO and EXTI Line.
+  * @param  Button: Specifies the Button to be configured.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button
+  * @param  Button_Mode: Specifies Button mode.
+  *   This parameter can be one of following parameters:   
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO 
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
+  *                     generation capability  
+  * @retval None
+  */
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* There is no Wakeup and Tamper buttons on STM32L152-EVAL. */
+   
+  /* Enable the BUTTON Clock */
+  RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+  /* Configure Button pin as input */
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+  if (Button_Mode == BUTTON_MODE_EXTI)
+  {
+    /* Connect Button EXTI Line to Button GPIO Pin */
+    SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+    /* Configure Button EXTI line */
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+    
+    if(Button != BUTTON_KEY) 
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  
+    }
+    else
+    {
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  
+    }
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+    EXTI_Init(&EXTI_InitStructure);
+
+    /* Enable and set Button EXTI Interrupt to the lowest priority */
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+    NVIC_Init(&NVIC_InitStructure); 
+  }
+}
+
+/**
+  * @brief  Returns the selected Button state.
+  * @param  Button: Specifies the Button to be checked.
+  *   This parameter can be one of following parameters:    
+  *     @arg BUTTON_KEY: Key Push Button 
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button 
+  *     @arg BUTTON_LEFT: Joystick Left Push Button 
+  *     @arg BUTTON_UP: Joystick Up Push Button 
+  *     @arg BUTTON_DOWN: Joystick Down Push Button
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    
+  * @retval Button GPIO pin value is returned. 
+  */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+  /* There is no Wakeup and Tamper pins on STM32L152-EVAL. */
+  
+  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+/**
+  * @brief  Configures COM port.
+  * @param  COM: Specifies the COM port to be configured.
+  *   This parameter can be one of following parameters:    
+  *     @arg COM1
+  *     @arg COM2  
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that
+  *   contains the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable GPIO clock */
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);
+
+  /* Enable UART clock */
+  RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+
+  /* Connect PXx to USARTx_Tx */
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);
+
+  /* Connect PXx to USARTx_Rx */
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);
+  
+  /* Configure USART Tx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);
+    
+  /* Configure USART Rx as alternate function push-pull */
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);
+
+  /* USART configuration */
+  USART_Init(COM_USART[COM], USART_InitStruct);
+    
+  /* Enable USART */
+  USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+  * @brief  DeInitializes the SPI interface.
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  
+  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */
+  SPI_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */
+  
+  /*!< SD_SPI Periph clock disable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); 
+
+  /*!< Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for 
+  *         data transfer).
+  * @param  None
+  * @retval None
+  */
+void SD_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  SPI_InitTypeDef   SPI_InitStructure;
+
+  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO 
+       and SD_SPI_SCK_GPIO Periph clock enable */
+  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |
+                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);
+
+  /*!< SD_SPI Periph clock enable */
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); 
+
+  /*!< Configure SD_SPI pins: SCK */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MISO */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI pins: MOSI */
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PXx to SD_SPI_SCK */
+  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);
+
+  /* Connect PXx to SD_SPI_MISO */
+  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); 
+
+  /* Connect PXx to SD_SPI_MOSI */
+  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  
+  
+  /*!< SD_SPI Config */
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
+  SPI_Init(SD_SPI, &SPI_InitStructure);
+  
+  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */
+}
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_DeInit(void)
+{ 
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< Disable LM75_I2C */
+  I2C_Cmd(LM75_I2C, DISABLE);
+  
+  /*!< DeInitializes the LM75_I2C */
+  I2C_DeInit(LM75_I2C);
+  
+  /*!< LM75_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);
+    
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Initializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_LowLevel_Init(void)
+{ 
+  GPIO_InitTypeDef  GPIO_InitStructure;
+
+  /*!< LM75_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);
+    
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK 
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |
+                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);
+
+  /* Connect PXx to I2C_SCL */
+  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);
+
+  /* Connect PXx to I2C_SDA */
+  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); 
+
+  /* Connect PXx to I2C_SMBUSALER */
+  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);   
+   
+  /*!< Configure LM75_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  DeInitializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_DeInit(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure; 
+  NVIC_InitTypeDef NVIC_InitStructure;    
+     
+  /* sEE_I2C Peripheral Disable */
+  I2C_Cmd(sEE_I2C, DISABLE);
+ 
+  /* sEE_I2C DeInit */
+  I2C_DeInit(sEE_I2C);
+
+  /*!< sEE_I2C Periph clock disable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, DISABLE);
+    
+  /*!< GPIO configuration */  
+  /*!< Configure sEE_I2C pins: SCL */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Configure and enable I2C DMA TX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Configure and enable I2C DMA RX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_Init(&NVIC_InitStructure);   
+  
+  /* Disable and Deinitialize the DMA channels */
+  DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, DISABLE);
+  DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, DISABLE);
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
+}
+
+/**
+  * @brief  Initializes peripherals used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_Init(void)
+{
+  GPIO_InitTypeDef  GPIO_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure;  
+   
+  /*!< sEE_I2C Periph clock enable */
+  RCC_APB1PeriphClockCmd(sEE_I2C_CLK, ENABLE);
+  
+  /*!< sEE_I2C_SCL_GPIO_CLK and sEE_I2C_SDA_GPIO_CLK Periph clock enable */
+  RCC_AHBPeriphClockCmd(sEE_I2C_SCL_GPIO_CLK | sEE_I2C_SDA_GPIO_CLK, ENABLE);
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  
+  /* Reset sEE_I2C peripheral */
+  RCC_APB1PeriphResetCmd(sEE_I2C_CLK, ENABLE);
+  
+  /* Release reset signal of sEE_I2C IP */
+  RCC_APB1PeriphResetCmd(sEE_I2C_CLK, DISABLE);
+    
+  /*!< GPIO configuration */  
+  /* Connect PXx to I2C_SCL*/
+  GPIO_PinAFConfig(sEE_I2C_SCL_GPIO_PORT, sEE_I2C_SCL_SOURCE, sEE_I2C_SCL_AF);
+
+  /* Connect PXx to I2C_SDA*/
+  GPIO_PinAFConfig(sEE_I2C_SDA_GPIO_PORT, sEE_I2C_SDA_SOURCE, sEE_I2C_SDA_AF);  
+
+  /*!< Configure sEE_I2C pins: SCL */   
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SCL_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
+  GPIO_Init(sEE_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);
+
+  /*!< Configure sEE_I2C pins: SDA */
+  GPIO_InitStructure.GPIO_Pin = sEE_I2C_SDA_PIN;
+  GPIO_Init(sEE_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);
+
+
+  /* Configure and enable I2C DMA TX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_TX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  /* Configure and enable I2C DMA RX Channel interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = sEE_I2C_DMA_RX_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = sEE_I2C_DMA_PREPRIO;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = sEE_I2C_DMA_SUBPRIO;
+  NVIC_Init(&NVIC_InitStructure);  
+  
+  /*!< I2C DMA TX and RX channels configuration */
+  /* Enable the DMA clock */
+  RCC_AHBPeriphClockCmd(sEE_I2C_DMA_CLK, ENABLE);
+
+  /* I2C TX DMA Channel configuration */
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_TX);
+  sEEDMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)sEE_I2C_DR_Address;
+  sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)0;   /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_BufferSize = 0xFFFF;            /* This parameter will be configured durig communication */
+  sEEDMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  sEEDMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  sEEDMA_InitStructure.DMA_PeripheralDataSize = DMA_MemoryDataSize_Byte;
+  sEEDMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  sEEDMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  sEEDMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  sEEDMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
+  
+  /* I2C RX DMA Channel configuration */
+  DMA_DeInit(sEE_I2C_DMA_CHANNEL_RX);
+  DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);  
+  
+  /* Enable the DMA Channels Interrupts */
+  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_TX, DMA_IT_TC, ENABLE);
+  DMA_ITConfig(sEE_I2C_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);    
+}
+
+/**
+  * @brief  Initializes DMA channel used by the I2C EEPROM driver.
+  * @param  None
+  * @retval None
+  */
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction)
+{ 
+  /* Initialize the DMA with the new parameters */
+  if (Direction == sEE_DIRECTION_TX)
+  {
+    /* Configure the DMA Tx Channel with the buffer address and the buffer size */
+    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
+    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;    
+    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;  
+    DMA_Init(sEE_I2C_DMA_CHANNEL_TX, &sEEDMA_InitStructure);  
+  }
+  else
+  { 
+    /* Configure the DMA Rx Channel with the buffer address and the buffer size */
+    sEEDMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)pBuffer;
+    sEEDMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    sEEDMA_InitStructure.DMA_BufferSize = (uint32_t)BufferSize;      
+    DMA_Init(sEE_I2C_DMA_CHANNEL_RX, &sEEDMA_InitStructure);    
+  }
+}
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+
+/**
+  * @}
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h
new file mode 100644
index 0000000..9bdef11
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval.h
@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file contains definitions for STM32L152_EVAL's Leds, push-buttons
+  *          and COM ports hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152_EVAL_H
+#define __STM32L152_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+#include "stm32_eval_legacy.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+      
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED1 = 0,
+  LED2 = 1,
+  LED3 = 2,
+  LED4 = 3
+} Led_TypeDef;
+
+typedef enum 
+{
+  BUTTON_KEY = 0,
+  BUTTON_RIGHT = 1,
+  BUTTON_LEFT = 2,
+  BUTTON_UP = 3,
+  BUTTON_DOWN = 4,
+  BUTTON_SEL = 5
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;
+
+typedef enum 
+{ 
+  JOY_NONE = 0,
+  JOY_SEL = 1,
+  JOY_DOWN = 2,
+  JOY_LEFT = 3,
+  JOY_RIGHT = 4,
+  JOY_UP = 5
+} JOYState_TypeDef
+;
+
+typedef enum 
+{
+  COM1 = 0,
+  COM2 = 1
+} COM_TypeDef;  
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** 
+  * @brief  Define for STM32L152_EVAL board  
+  */ 
+#if !defined (USE_STM32L152_EVAL)
+ #define USE_STM32L152_EVAL
+#endif
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED1_PIN                         GPIO_Pin_0
+#define LED1_GPIO_PORT                   GPIOD
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED2_PIN                         GPIO_Pin_1
+#define LED2_GPIO_PORT                   GPIOD
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED3_PIN                         GPIO_Pin_4
+#define LED3_GPIO_PORT                   GPIOD
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOD  
+  
+#define LED4_PIN                         GPIO_Pin_5
+#define LED4_GPIO_PORT                   GPIOD
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOD
+
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          6 
+/* On STM32L152-EVAL board, the KEY button is connected to PA.00 and it can
+   be use as Wakeup pin button. */
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PIN                   GPIO_Pin_0
+#define KEY_BUTTON_GPIO_PORT             GPIOA
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOA
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line0
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOA
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource0
+#define KEY_BUTTON_EXTI_IRQn             EXTI0_IRQn
+
+/**
+ * @brief Joystick Right push-button
+ */
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_11
+#define RIGHT_BUTTON_GPIO_PORT           GPIOE
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOE
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line11
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOE
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource11
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn
+
+/**
+ * @brief Joystick Left push-button
+ */
+#define LEFT_BUTTON_PIN                  GPIO_Pin_12
+#define LEFT_BUTTON_GPIO_PORT            GPIOE
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line12
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource12
+#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Up push-button
+ */
+#define UP_BUTTON_PIN                    GPIO_Pin_9
+#define UP_BUTTON_GPIO_PORT              GPIOE
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define UP_BUTTON_EXTI_LINE              EXTI_Line9
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource9
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  
+
+/**
+ * @brief Joystick Down push-button
+ */  
+#define DOWN_BUTTON_PIN                  GPIO_Pin_10
+#define DOWN_BUTTON_GPIO_PORT            GPIOE
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line10
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource10
+#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  
+
+/**
+ * @brief Joystick Sel push-button
+ */
+#define SEL_BUTTON_PIN                   GPIO_Pin_8
+#define SEL_BUTTON_GPIO_PORT             GPIOE
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line8
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource8
+#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn 
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM
+  * @{
+  */
+#define COMn                             2
+
+/**
+ * @brief Definition for COM port1, connected to USART2
+ */ 
+#define EVAL_COM1                        USART2
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2
+
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource5
+#define EVAL_COM1_TX_AF                  GPIO_AF_USART2
+
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource6
+#define EVAL_COM1_RX_AF                  GPIO_AF_USART2
+
+#define EVAL_COM1_RTS_PIN                GPIO_Pin_4
+#define EVAL_COM1_RTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_RTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_RTS_SOURCE             GPIO_PinSource4
+#define EVAL_COM1_RTS_AF                 GPIO_AF_USART2
+
+#define EVAL_COM1_CTS_PIN                GPIO_Pin_3
+#define EVAL_COM1_CTS_GPIO_PORT          GPIOD
+#define EVAL_COM1_CTS_GPIO_CLK           RCC_AHBPeriph_GPIOD
+#define EVAL_COM1_CTS_SOURCE             GPIO_PinSource3
+#define EVAL_COM1_CTS_AF                 GPIO_AF_USART2
+
+#define EVAL_COM1_IRQn                   USART2_IRQn
+
+/**
+ * @brief Definition for COM port2, connected to USART3
+ */ 
+#define EVAL_COM2                        USART3
+#define EVAL_COM2_CLK                    RCC_APB1Periph_USART3
+
+#define EVAL_COM2_TX_PIN                 GPIO_Pin_10
+#define EVAL_COM2_TX_GPIO_PORT           GPIOC
+#define EVAL_COM2_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC
+#define EVAL_COM2_TX_SOURCE              GPIO_PinSource10
+#define EVAL_COM2_TX_AF                  GPIO_AF_USART3
+
+#define EVAL_COM2_RX_PIN                 GPIO_Pin_11
+#define EVAL_COM2_RX_GPIO_PORT           GPIOC
+#define EVAL_COM2_RX_GPIO_CLK            RCC_AHBPeriph_GPIOC
+#define EVAL_COM2_RX_SOURCE              GPIO_PinSource11
+#define EVAL_COM2_RX_AF                  GPIO_AF_USART3
+
+#define EVAL_COM2_IRQn                   USART3_IRQn
+
+/**
+  * @}
+  */ 
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH
+  * @{
+  */ 
+/**
+  * @brief  SD Card SPI Interface
+  */  
+#define SD_SPI                           SPI2
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI2
+#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PB.13 */
+#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOB
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource13
+#define SD_SPI_SCK_AF                    GPIO_AF_SPI2
+#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PB.14 */
+#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource14
+#define SD_SPI_MISO_AF                   GPIO_AF_SPI2
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */
+#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource15
+#define SD_SPI_MOSI_AF                   GPIO_AF_SPI2
+#define SD_CS_PIN                        GPIO_Pin_7                  /* PD.07 */
+#define SD_CS_GPIO_PORT                  GPIOD                       /* GPIOD */
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOD
+#define SD_DETECT_PIN                    GPIO_Pin_6                  /* PE.06 */
+#define SD_DETECT_EXTI_LINE              EXTI_Line6
+#define SD_DETECT_EXTI_PIN_SOURCE        EXTI_PinSource6
+
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE
+#define SD_DETECT_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE
+#define SD_DETECT_EXTI_IRQn              EXTI9_5_IRQn 
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C
+  * @{
+  */
+/**
+  * @brief  LM75 Temperature Sensor I2C Interface pins
+  */  
+#define LM75_I2C                         I2C1
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource6
+#define LM75_I2C_SCL_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource7
+#define LM75_I2C_SDA_AF                  GPIO_AF_I2C1
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1
+#define LM75_I2C_DR                      ((uint32_t)0x40005410)
+
+#define LM75_DMA_CLK                     RCC_AHBPeriph_DMA1
+#define LM75_DMA_TX_CHANNEL              DMA1_Channel6
+#define LM75_DMA_RX_CHANNEL              DMA1_Channel7
+#define LM75_DMA_TX_TCFLAG               DMA1_FLAG_TC6
+#define LM75_DMA_RX_TCFLAG               DMA1_FLAG_TC7
+
+/**
+  * @}
+  */  
+
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_I2C_EE
+  * @{
+  */
+/**
+  * @brief  I2C EEPROM Interface pins
+  */  
+
+#define sEE_I2C                          I2C1
+#define sEE_I2C_CLK                      RCC_APB1Periph_I2C1
+#define sEE_I2C_SCL_PIN                  GPIO_Pin_6                  /* PB.06 */
+#define sEE_I2C_SCL_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SCL_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SCL_SOURCE               GPIO_PinSource6
+#define sEE_I2C_SCL_AF                   GPIO_AF_I2C1
+#define sEE_I2C_SDA_PIN                  GPIO_Pin_7                  /* PB.07 */
+#define sEE_I2C_SDA_GPIO_PORT            GPIOB                       /* GPIOB */
+#define sEE_I2C_SDA_GPIO_CLK             RCC_AHBPeriph_GPIOB
+#define sEE_I2C_SDA_SOURCE               GPIO_PinSource7
+#define sEE_I2C_SDA_AF                   GPIO_AF_I2C1
+#define sEE_M24C64_32
+
+#define sEE_I2C_DMA                      DMA1   
+#define sEE_I2C_DMA_CHANNEL_TX           DMA1_Channel6
+#define sEE_I2C_DMA_CHANNEL_RX           DMA1_Channel7 
+#define sEE_I2C_DMA_FLAG_TX_TC           DMA1_IT_TC6   
+#define sEE_I2C_DMA_FLAG_TX_GL           DMA1_IT_GL6 
+#define sEE_I2C_DMA_FLAG_RX_TC           DMA1_IT_TC7 
+#define sEE_I2C_DMA_FLAG_RX_GL           DMA1_IT_GL7    
+#define sEE_I2C_DMA_CLK                  RCC_AHBPeriph_DMA1
+#define sEE_I2C_DR_Address               ((uint32_t)0x40005410)
+#define sEE_USE_DMA
+   
+#define sEE_I2C_DMA_TX_IRQn              DMA1_Channel6_IRQn
+#define sEE_I2C_DMA_RX_IRQn              DMA1_Channel7_IRQn
+#define sEE_I2C_DMA_TX_IRQHandler        DMA1_Channel6_IRQHandler
+#define sEE_I2C_DMA_RX_IRQHandler        DMA1_Channel7_IRQHandler  
+#define sEE_I2C_DMA_PREPRIO              0
+#define sEE_I2C_DMA_SUBPRIO              0
+ 
+#define sEE_DIRECTION_TX                 0
+#define sEE_DIRECTION_RX                 1 
+
+/* Time constant for the delay caclulation allowing to have a millisecond 
+   incrementing counter. This value should be equal to (System Clock / 1000).
+   ie. if system clock = 32MHz then sEE_TIME_CONST should be 32. */
+#define sEE_TIME_CONST          32 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); 
+void SD_LowLevel_DeInit(void);
+void SD_LowLevel_Init(void); 
+void LM75_LowLevel_DeInit(void);
+void LM75_LowLevel_Init(void);  
+void sEE_LowLevel_DeInit(void);
+void sEE_LowLevel_Init(void);
+void sEE_LowLevel_DMAConfig(uint32_t pBuffer, uint32_t BufferSize, uint32_t Direction);
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152_EVAL_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c
new file mode 100644
index 0000000..5a80c56
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.c
@@ -0,0 +1,861 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_glass_lcd.c
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file includes the LCD Glass driver for Pacific Display 
+  *          (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board RevB.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval_glass_lcd.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @defgroup STM32L152_EVAL_GLASS_LCD 
+  * @brief This file includes the LCD Glass driver for Pacific Display 
+  *        (LCD_PD878, PD878-DP-FH-W-LV-6-RH) Module of STM32L152-EVAL board.
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */   
+
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Private_Variables
+  * @{
+  */ 
+
+/**
+  @verbatim      
+================================================================================
+                              GLASS LCD MAPPING
+================================================================================
+               A
+      --  ----------
+    X \/  |\   |I  /|
+         F| H  |  J |B
+          |  \ | /  |
+          --G-- --K--
+          |   /| \  |
+        E |  L |  N |C
+          | /  |M  \|   _
+          -----------  | |DP
+              D         -
+
+A LCD character coding is based on the following matrix:
+
+
+{ X , F , E , D  }
+{ I , J , K , N  }
+{ A , B , C , DP }
+{ H , G , L , M  }
+
+The character A for example is:
+-------------------------------
+ { 0 , 1 , 1 , 0 }
+ { 0 , 0 , 1 , 0 }
+ { 1 , 1 , 1 , 0 }
+ { 0 , 1 , 0 , 0 }
+-------------------
+=  4   D   7   0   hex
+
+=> 'A' = 0x4D70
+
+  @endverbatim
+  */
+
+/**
+  * @brief LETTERS AND NUMBERS MAPPING DEFINITION
+  */
+uint8_t digit[4];     /* Digit LCD RAM buffer */
+__I uint16_t mask[4] = {0xF000, 0x0F00, 0x00F0, 0x000F};
+__I uint8_t shift[4] = {0x0C, 0x08, 0x04, 0x00};
+  
+/* Letters and number map of PD_878 LCD */
+__I uint16_t LetterMap[26]=
+{
+/* A       B       C       D       E       F       G       H       I  */
+0x4D70, 0x6469, 0x4111, 0x6449, 0x4911, 0x4910, 0x4171, 0x0D70, 0x6009,
+/* J       K       L       M       N       O       P       Q       R  */
+0x0451, 0x0B12, 0x0111, 0x8750, 0x8552, 0x4551, 0x4D30, 0x4553, 0x4D32,
+/* S       T       U       V       W       X       Y       Z  */
+0x4961, 0x6008, 0x0551, 0x0390, 0x05D2, 0x8282, 0x8208, 0x4281
+};
+
+__I uint16_t NumberMap[10]= 
+{
+/* 0       1       2       3       4       5       6       7       8       9  */
+0x47D1, 0x0640, 0x4C31, 0x4C61, 0x0D60, 0x4961, 0x4971, 0x4440, 0x4D71, 0x4D61
+};
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
+  * @{
+  */ 
+static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe);
+static void delay(__IO uint32_t nCount);
+static void LCD_GPIOConfig(void);
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152_EVAL_LCD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
+  * @param  None 
+  * @retval None
+  */
+void LCD_GLASS_Init(void)
+{
+  LCD_InitTypeDef LCD_InitStructure;
+  
+  LCD_GPIOConfig(); /*!< Configure the LCD Glass GPIO pins */
+
+  /*!< Configure the LCD interface -------------------------------------------*/
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE); /*!< Enable LCD APB1 Clock */
+  
+  LCD_InitStructure.LCD_Prescaler = LCD_Prescaler_8;
+  LCD_InitStructure.LCD_Divider = LCD_Divider_16;
+  LCD_InitStructure.LCD_Duty = LCD_Duty_1_4;
+  LCD_InitStructure.LCD_Bias = LCD_Bias_1_3;
+  LCD_InitStructure.LCD_VoltageSource = LCD_VoltageSource_Internal;
+  LCD_Init(&LCD_InitStructure);
+
+  /*!< Configure the Pulse On Duration */
+  LCD_PulseOnDurationConfig(LCD_PulseOnDuration_2);
+  
+  /*!< Configure the LCD Contrast (3.51V) */
+  LCD_ContrastConfig(LCD_Contrast_Level_7);
+
+  /*!< Wait Until the LCD FCR register is synchronized */
+  LCD_WaitForSynchro();
+  
+  /*!< Enable LCD peripheral */
+  LCD_Cmd(ENABLE);
+  
+  /*!< Wait Until the LCD is enabled */
+  while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)
+  {
+  }
+  /*!< Wait Until the LCD Booster is ready */  
+  while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)
+  {
+  }    
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ch: The character to dispaly.
+  * @param  point: A point to add in front of char.
+  *          This parameter  can be one of the following values:  
+  *              @arg POINT_OFF: No point to add in front of char.
+  *              @arg POINT_ON: Add a point in front of char.
+  * @param  apostrophe: Flag indicating if a apostrophe has to be add in front 
+  *                     of displayed character.
+  *          This parameter  can be one of the following values:
+  *              @arg APOSTROPHE_OFF: No apostrophe to add in back of char.
+  *              @arg APOSTROPHE_ON: Add an apostrophe in back of char.
+  * @param  position: Position in the LCD of the caracter to write.
+  *                   This parameter can be any value in range [0:7].
+  * @retval None
+  */
+void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
+{
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+  /*!< LCD Write Char */
+  LCD_GLASS_WriteChar(ch, point, apostrophe, position);
+
+  /*!< Requesy LCD RAM update */
+  LCD_UpdateDisplayRequest();  
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ptr: Pointer to string to display on the LCD Glass.
+  * @retval None
+  */
+void LCD_GLASS_DisplayString(uint8_t* ptr)
+{
+  uint8_t i = 0x00;
+
+  /*!< Wait Until the last LCD RAM update finish */
+  while(LCD_GetFlagStatus(LCD_FLAG_UDR) != RESET)
+  {
+  }
+
+  /*!< Send the string character by character on lCD */
+  while ((*ptr != 0) & (i < 8))
+  {
+    /*!< Display one character on LCD */
+    LCD_GLASS_WriteChar(ptr, POINT_OFF, APOSTROPHE_OFF, i);
+    /*!< Point on the next character */
+    ptr++;
+    /*!< Increment the character counter */
+    i++;
+  }
+  /*!< Requesy LCD RAM update */
+  LCD_UpdateDisplayRequest();
+}
+
+/**
+  * @brief  This function writes a char in the LCD RAM.
+  * @param  ch: The character to dispaly.
+  * @param  point: A point to add in front of char.
+  *          This parameter  can be one of the following values:  
+  *              @arg POINT_OFF : No point to add in front of char.
+  *              @arg POINT_ON : Add a point in front of char.
+  * @param  apostrophe: Flag indicating if a apostrophe has to be add in front 
+  *                     of displayed character.
+  *          This parameter  can be one of the following values:
+  *              @arg APOSTROPHE_OFF : No apostrophe to add in back of char.
+  *              @arg APOSTROPHE_ON : Add an apostrophe in back of char.
+  * @param  position: Position in the LCD of the caracter to write.
+  *          This parameter can be any value in range [0:7].
+  * @retval None
+  */
+void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe, uint8_t position)
+{
+  uint32_t tmp = 0x00;
+    
+  Convert(ch, point, apostrophe); /*!< Convert the corresponding character */
+
+  switch (position)
+  {
+    case 7:
+      /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0);
+  
+      /*!< Write the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0]);
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1]);
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2]);
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3]);
+      break;
+      
+    case 6:
+      /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F);
+  
+      /*!< Write the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
+      tmp = (((digit[0] & 0x8) << 7) | ((digit[0]& 0x7) << 4));
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t) tmp;
+      tmp = (((digit[1] & 0x8) << 7) | ((digit[1]& 0x7) << 4));
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t) tmp;
+      tmp = (((digit[2] & 0x8) << 7) | ((digit[2]& 0x7) << 4));
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t) tmp;
+      tmp = (((digit[3] & 0x8) << 7) | ((digit[3]& 0x7) << 4));
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t) tmp;
+      break;
+      
+    case 5:
+      /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF);
+  
+      /*!< Write the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
+      tmp = (((digit[0] & 0x1) << 11) | ((digit[0]& 0x2) << 15) | ((digit[0]& 0xC) << 16));
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(tmp);
+      tmp = (((digit[1] & 0x1) << 11) | ((digit[1]& 0x2) << 15) | ((digit[1]& 0xC) << 16));
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(tmp);
+      tmp = (((digit[2] & 0x1) << 11) | ((digit[2]& 0x2) << 15) | ((digit[2]& 0xC) << 16));
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(tmp);
+      tmp = (((digit[3] & 0x1) << 11) | ((digit[3]& 0x2) << 15) | ((digit[3]& 0xC) << 16));
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(tmp);
+      break;
+      
+    case 4:
+      /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF);
+  
+      /*!< Write the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 20);
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 20);
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 20);
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 20);
+      break;
+      
+    case 3:
+      /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF);
+  
+      /*!< Write the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
+      LCD->RAM[LCD_RAMRegister_0] |= (uint32_t)(digit[0] << 28);
+      LCD->RAM[LCD_RAMRegister_2] |= (uint32_t)(digit[1] << 28);
+      LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(digit[2] << 28);
+      LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(digit[3] << 28);
+      break;
+      
+    case 2:
+      /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0);
+  
+      /*!< Write the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
+      LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 0);
+      LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 0);
+      LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 0);
+      LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 0);
+      break;
+      
+    case 1:
+      /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F);
+
+      /*!< Write the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
+      LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 4);
+      LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 4);
+      LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 4);
+      LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 4);
+      
+      break;
+      
+    case 0:
+      /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF);
+  
+      /*!< Write the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
+      LCD->RAM[LCD_RAMRegister_1] |= (uint32_t)(digit[0] << 8);
+      LCD->RAM[LCD_RAMRegister_3] |= (uint32_t)(digit[1] << 8);
+      LCD->RAM[LCD_RAMRegister_5] |= (uint32_t)(digit[2] << 8);
+      LCD->RAM[LCD_RAMRegister_7] |= (uint32_t)(digit[3] << 8);
+      break;
+  }
+}
+
+/**
+  * @brief  Display a string in scrolling mode
+  * @note   The LCD should be cleared before to start the write operation.  
+  * @param  ptr: Pointer to string to display on the LCD Glass.
+  * @param  nScroll: Specifies how many time the message will be scrolled
+  * @param  ScrollSpeed: Speciifes the speed of the scroll.
+  *                     Low value gives higher speed. 
+  * @retval None
+  */
+void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)
+{
+  uint8_t Repetition = 0;
+  uint8_t* ptr1;
+  uint8_t str[8] = "";
+  ptr1 = ptr;
+
+  LCD_GLASS_DisplayString(ptr1);
+
+  delay(ScrollSpeed);
+		
+  for (Repetition = 0; Repetition < nScroll; Repetition++)
+  {
+    *(str + 1) = *ptr1;
+    *(str + 2) = *(ptr1 + 1);
+    *(str + 3) = *(ptr1 + 2);
+    *(str + 4) = *(ptr1 + 3);
+    *(str + 5) = *(ptr1 + 4);
+    *(str + 6) = *(ptr1 + 5);
+    *(str + 7) =*(ptr1 + 6);
+    *(str) = *(ptr1 + 7);    
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 7);
+    *(str + 2) = *ptr1;
+    *(str + 3) = *(ptr1 + 1);
+    *(str + 4) = *(ptr1 + 2);
+    *(str + 5) = *(ptr1 + 3);
+    *(str + 6) = *(ptr1 + 4);
+    *(str + 7) = *(ptr1 + 5);
+    *(str) = *(ptr1 + 6);    
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 6);
+    *(str + 2) = *(ptr1 + 7);
+    *(str + 3) = *ptr1;
+    *(str + 4) = *(ptr1 + 1);
+    *(str + 5) = *(ptr1 + 2);
+    *(str + 6) = *(ptr1 + 3);
+    *(str + 7) = *(ptr1 + 4);    
+    *(str) = *(ptr1 + 5);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 5);
+    *(str + 2) = *(ptr1 + 6);
+    *(str + 3) = *(ptr1 + 7);
+    *(str + 4) = *ptr1;
+    *(str + 5) = *(ptr1 + 1);
+    *(str + 6) = *(ptr1 + 2);
+    *(str + 7) = *(ptr1 + 3);    
+    *(str) = *(ptr1 + 4);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 4);
+    *(str + 2) = *(ptr1 + 5);
+    *(str + 3) = *(ptr1 + 6);
+    *(str + 4) = *(ptr1 + 7);
+    *(str + 5) = *ptr1;
+    *(str + 6) = *(ptr1 + 1);
+    *(str + 7) = *(ptr1 + 2);    
+    *(str) = *(ptr1 + 3);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 3);
+    *(str + 2) = *(ptr1 + 4);
+    *(str + 3) = *(ptr1 + 5);
+    *(str + 4) = *(ptr1 + 6);
+    *(str + 5) = *(ptr1 + 7);
+    *(str + 6) = *ptr1;
+    *(str + 7) = *(ptr1 + 1);    
+    *(str) = *(ptr1 + 2);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+
+    *(str + 1) = *(ptr1 + 2);
+    *(str + 2) = *(ptr1 + 3);
+    *(str + 3) = *(ptr1 + 4);
+    *(str + 4) = *(ptr1 + 5);
+    *(str + 5) = *(ptr1 + 6);
+    *(str + 6) = *(ptr1 + 7);
+    *(str + 7) = *ptr1;    
+    *(str) = *(ptr1 + 1);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+    
+    *(str + 1) = *(ptr1 + 1);
+    *(str + 2) = *(ptr1 + 2);
+    *(str + 3) = *(ptr1 + 3);
+    *(str + 4) = *(ptr1 + 4);
+    *(str + 5) = *(ptr1 + 5);
+    *(str + 6) = *(ptr1 + 6);
+    *(str + 7) = *(ptr1 + 7);    
+    *(str) = *(ptr1);
+    LCD_GLASS_Clear();
+    LCD_GLASS_DisplayString(str);
+    delay(ScrollSpeed);
+  }
+}
+
+/**
+  * @brief This function Clear a char in the LCD RAM.
+  * @param position: Position in the LCD of the caracter to write.
+  *                  This parameter can be any value in range [0:7]. 
+  * @retval None
+  */
+void LCD_GLASS_ClearChar(uint8_t position)
+{
+  switch (position)
+  {
+    case 7:
+      /*!< Clear the corresponding segments (SEG0, SEG1, SEG2, SEG3) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFFF0);
+      break;
+      
+    case 6:
+      /*!< Clear the corresponding segments (SEG4, SEG5, SEG6, SEG10) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFFFFB8F);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFFFFB8F);
+      break;
+      
+    case 5:
+      /*!< Clear the corresponding segments (SEG11, SEG16, SEG18, SEG19) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFFF2F7FF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFFF2F7FF);
+      break;
+      
+    case 4:
+      /*!< Clear the corresponding segments (SEG20, SEG21, SEG22, SEG23) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0xFF0FFFFF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0xFF0FFFFF);
+      break;
+      
+    case 3:
+      /*!< Clear the corresponding segments (SEG28, SEG29, SEG30, SEG31) */
+      LCD->RAM[LCD_RAMRegister_0] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_2] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_4] &= (uint32_t)(0x0FFFFFFF);
+      LCD->RAM[LCD_RAMRegister_6] &= (uint32_t)(0x0FFFFFFF);
+      break;
+      
+    case 2:
+      /*!< Clear the corresponding segments (SEG32, SEG33, SEG34, SEG35) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFFF0);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFFF0);
+      break;
+      
+    case 1:
+      /*!< Clear the corresponding segments (SEG36, SEG37, SEG38, SEG39) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFFF0F);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFFF0F);
+      break;
+      
+    case 0:
+      /*!< Clear the corresponding segments (SEG40, SEG41, SEG42, SEG43) */
+      LCD->RAM[LCD_RAMRegister_1] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_3] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_5] &= (uint32_t)(0xFFFFF0FF);
+      LCD->RAM[LCD_RAMRegister_7] &= (uint32_t)(0xFFFFF0FF);
+      break;
+  }
+}
+
+/**
+  * @brief  This function Clear the whole LCD RAM.
+  * @param  None 
+  * @retval None
+  */
+void LCD_GLASS_Clear(void)
+{
+  uint32_t counter = 0;
+
+  for (counter = 0; counter < 0x0F; counter++)
+  {
+    LCD->RAM[counter] =  (uint32_t)0x00;
+  }
+}
+
+/**
+  * @brief  Converts an ascii char to an LCD digit.
+  * @param  c: Char to display.
+  * @param  point: A point to add in front of char.
+  *          This parameter  can be one of the following values:  
+  *              @arg POINT_OFF : No point to add in front of char.
+  *              @arg POINT_ON : Add a point in front of char.
+  * @param  apostrophe: Flag indicating if a apostrophe has to be add in front 
+  *                     of displayed character.
+  *          This parameter  can be one of the following values:
+  *              @arg APOSTROPHE_OFF : No apostrophe to add in back of char.
+  *              @arg APOSTROPHE_ON : Add an apostrophe in back of char.
+  * @retval None
+  */
+static void Convert(uint8_t* c, Point_Typedef point, Apostrophe_Typedef apostrophe)
+{
+  uint16_t ch = 0, tmp = 0;
+  uint8_t i = 0;
+
+  /*!< The character c is a letter in upper case*/
+  if ((*c < 0x5B) & (*c > 0x40))
+  {
+    ch = LetterMap[*c - 0x41];
+  }
+  
+  /*!< The character c is a number*/
+  if ((*c < 0x3A) & (*c > 0x2F))
+  {
+    ch = NumberMap[*c - 0x30];
+  }
+  
+  /*!< The character c is a space character */
+  if (*c == 0x20)
+  {
+    ch =0x00;
+  }
+  
+  /*!< Set the DP seg in the character that can be displayed if the point is on */
+  if (point == POINT_ON)
+  {
+    ch |= 0x0004;
+  }
+
+  /*!< Set the X seg in the character that can be displayed if the apostrophe is on */
+  if (apostrophe == APOSTROPHE_ON)
+  {
+    ch |= 0x1000;
+  }
+
+  for (i = 0; i < 4; i++)
+  {
+    tmp = ch & mask[i];
+    digit[i] =(uint8_t)(tmp >> shift[i]);
+  }
+}
+
+/**
+  * @brief  Configures the LCD Segments and Coms GPIOs.
+  * @param  None 
+  * @retval None
+  */
+static void LCD_GPIOConfig(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  
+  /*!< Enable GPIOA, GPIOB, GPIOC, GPIOD and GPIOE AHB Clocks */
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC
+                        | RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE, ENABLE);
+
+  /*!< Connect PA.08 to LCD COM0 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PA.09 to LCD COM1 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PA.10 to LCD COM2 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PB.09 to LCD COM3 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PA.01 to LCD SEG0 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PA.02 to LCD SEG1 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PA.03 to LCD SEG2 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PA.06 to LCD SEG3 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_LCD);
+
+  /*!< Connect PA.07 to LCD SEG4 */
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_LCD);
+
+  /*!< Connect PB.00 to LCD SEG5 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PB.01 to LCD SEG6 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PB.10 to LCD SEG10 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PB.11 to LCD SEG11 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PB.08 to LCD SEG16 */
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PC.00 to LCD SEG18 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PC.01 to LCD SEG19 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PC.02 to LCD SEG20 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PC.03 to LCD SEG21 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PC.04 to LCD SEG22 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_LCD);
+
+  /*!< Connect PC.05 to LCD SEG23 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_LCD);
+
+  /*!< Connect PD.08 to LCD SEG28 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_LCD);
+
+  /*!< Connect PD.09 to LCD SEG29 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_LCD);
+
+  /*!< Connect PD.10 to LCD SEG30 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PD.11 to LCD SEG31 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PD.12 to LCD SEG32 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_LCD);
+
+  /*!< Connect PD.13 to LCD SEG33 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_LCD);
+
+  /*!< Connect PD.14 to LCD SEG34 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_LCD);
+
+  /*!< Connect PD.15 to LCD SEG35 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_LCD);
+
+  /*!< Connect PE.00 to LCD SEG36 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_LCD);
+
+  /*!< Connect PE.01 to LCD SEG37 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_LCD);
+
+  /*!< Connect PE.02 to LCD SEG38 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource2, GPIO_AF_LCD);
+
+  /*!< Connect PE.03 to LCD SEG39 */
+  GPIO_PinAFConfig(GPIOE, GPIO_PinSource3, GPIO_AF_LCD);
+
+  /*!< Connect PC.10 to LCD SEG40 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_LCD);
+
+  /*!< Connect PC.11 to LCD SEG41 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_LCD);
+
+  /*!< Connect PC.12 to LCD SEG42 */
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_LCD);
+
+  /*!< Connect PD.02 to LCD SEG43 */
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_LCD);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | \
+                                GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | \
+                                GPIO_Pin_10 | GPIO_Pin_11;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | \
+                                GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_11 | \
+                                GPIO_Pin_12;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | \
+                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | \
+                                GPIO_Pin_15;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3;
+  GPIO_Init(GPIOE, &GPIO_InitStructure);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = (0xFF * nCount); index != 0; index--)
+  {
+  }    
+}
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h
new file mode 100644
index 0000000..5dde106
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_glass_lcd.h
@@ -0,0 +1,131 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_glass_lcd.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   Header file for stm32l152_eval_glass_lcd.c module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152_EVAL_GLASS_LCD_H
+#define __STM32L152_EVAL_GLASS_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152_EVAL_GLASS_LCD
+  * @{
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Types
+  * @{
+  */
+typedef enum
+{
+  POINT_OFF = 0,
+  POINT_ON = 1
+}Point_Typedef;
+
+typedef enum
+{
+  APOSTROPHE_OFF = 0,
+  APOSTROPHE_ON = 1
+}Apostrophe_Typedef;   
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Constants
+  * @{
+  */ 
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_GLASS_LCD_Exported_Functions
+  * @{
+  */
+void LCD_GLASS_Init(void);
+void LCD_GLASS_DisplayChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position);
+void LCD_GLASS_DisplayString(uint8_t* ptr);
+void LCD_GLASS_WriteChar(uint8_t* ch, Point_Typedef point, Apostrophe_Typedef apostrophe,uint8_t position);
+void LCD_GLASS_ClearChar(uint8_t position);
+void LCD_GLASS_Clear(void);
+void LCD_GLASS_ScrollString(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152_EVAL_GLASS_LCD_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */   
+
+/**
+  * @}
+  */   
+  
+/**
+  * @}
+  */   
+ 
+/**
+  * @}
+  */   
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
index 027653d..e67441f 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.c
@@ -1,21 +1,23 @@
 /**
   ******************************************************************************
-  * @file    stm32_eval_i2c_ee.c
+  * @file    stm32l152_eval_i2c_ee.c
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file provides a set of functions needed to manage the I2C M24CXX 
-  *          EEPROM memory mounted on STM32xx-EVAL board (refer to stm32_eval.h
-  *          to know about the boards supporting this memory). 
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to manage an I2C M24CXX 
+  *          EEPROM memory.
   *          
   *          ===================================================================      
-  *          Note: This driver is intended for STM32F10x families devices only.
+  *          Notes: 
+  *           - This driver is intended for STM32L1xx families devices only.
+  *           - There is no I2C EEPROM memory available in STM32L152-EVAL board,
+  *             to use this driver you have to build your own hardware.     
   *          ===================================================================
-  *            
+  *              
   *          It implements a high level communication layer for read and write 
   *          from/to this memory. The needed STM32 hardware resources (I2C and 
-  *          GPIO) are defined in stm32xx_eval.h file, and the initialization is 
-  *          performed in sEE_LowLevel_Init() function declared in stm32xx_eval.c 
+  *          GPIO) are defined in stm32l152_eval.h file, and the initialization is 
+  *          performed in sEE_LowLevel_Init() function declared in stm32l152_eval.c 
   *          file.
   *          You can easily tailor this driver to any other development board, 
   *          by just adapting the defines for hardware resources and 
@@ -49,38 +51,44 @@
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_i2c_ee.h"
+#include "stm32l152_eval_i2c_ee.h"
 
 /** @addtogroup Utilities
   * @{
   */
-  
+
 /** @addtogroup STM32_EVAL
   * @{
   */ 
 
-/** @addtogroup Common
+/** @addtogroup STM32L152_EVAL
   * @{
   */
   
-/** @addtogroup STM32_EVAL_I2C_EE
-  * @brief      This file includes the I2C EEPROM driver of STM32-EVAL boards.
+/** @addtogroup STM32L152_EVAL_I2C_EE
+  * @brief      This file includes the I2C EEPROM driver of STM32L152-EVAL board.
   * @{
   */ 
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Types
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Types
   * @{
   */ 
 /**
@@ -88,7 +96,7 @@
   */ 
 
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Defines
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Defines
   * @{
   */  
 /**
@@ -96,7 +104,7 @@
   */ 
 
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Macros
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Macros
   * @{
   */
 /**
@@ -104,7 +112,7 @@
   */ 
   
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Variables
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Variables
   * @{
   */
 __IO uint16_t  sEEAddress = 0;   
@@ -117,7 +125,7 @@ __IO uint8_t   sEEDataNum;
   */ 
 
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Function_Prototypes
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Function_Prototypes
   * @{
   */ 
 /**
@@ -125,7 +133,7 @@ __IO uint8_t   sEEDataNum;
   */ 
 
 
-/** @defgroup STM32_EVAL_I2C_EE_Private_Functions
+/** @defgroup STM32L152_EVAL_I2C_EE_Private_Functions
   * @{
   */ 
 
@@ -262,7 +270,7 @@ uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteTo
 
   /*!< Test on EV8 and clear it */
   sEETimeout = sEE_FLAG_TIMEOUT;
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
   {
     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
   }
@@ -305,18 +313,12 @@ uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteTo
     
     /*!< Disable Acknowledgement */
     I2C_AcknowledgeConfig(sEE_I2C, DISABLE);   
-
-    /* Call User callback for critical section start (should typically disable interrupts) */
-    sEE_EnterCriticalSection_UserCallback();
     
     /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */
     (void)sEE_I2C->SR2;
     
     /*!< Send STOP Condition */
     I2C_GenerateSTOP(sEE_I2C, ENABLE);
-   
-    /* Call User callback for critical section end (should typically re-enable interrupts) */
-    sEE_ExitCriticalSection_UserCallback();
     
     /* Wait for the byte to be received */
     sEETimeout = sEE_FLAG_TIMEOUT;
@@ -357,7 +359,7 @@ uint32_t sEE_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteTo
     I2C_DMALastTransferCmd(sEE_I2C, ENABLE); 
     
     /* Enable the DMA Rx Channel */
-    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);  
+    DMA_Cmd(sEE_I2C_DMA_CHANNEL_RX, ENABLE);    
   }
   
   /* If all operations OK, return sEE_OK (0) */
@@ -439,7 +441,7 @@ uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToW
 
   /*!< Test on EV8 and clear it */
   sEETimeout = sEE_FLAG_TIMEOUT;  
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
   {
     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
   }  
@@ -451,14 +453,14 @@ uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToW
   
   /*!< Test on EV8 and clear it */
   sEETimeout = sEE_FLAG_TIMEOUT; 
-  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+  while(!I2C_CheckEvent(sEE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING))
   {
     if((sEETimeout--) == 0) return sEE_TIMEOUT_UserCallback();
   }  
   
   /* Configure the DMA Tx Channel with the buffer address and the buffer size */
   sEE_LowLevel_DMAConfig((uint32_t)pBuffer, (uint8_t)(*NumByteToWrite), sEE_DIRECTION_TX);
-    
+  
   /* Enable the DMA Tx Channel */
   DMA_Cmd(sEE_I2C_DMA_CHANNEL_TX, ENABLE);
   
@@ -476,7 +478,7 @@ uint32_t sEE_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToW
   */
 void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite)
 {
-  uint8_t NumOfPage = 0, NumOfSingle = 0, count = 0;
+  uint16_t NumOfPage = 0, NumOfSingle = 0, count = 0;
   uint16_t Addr = 0;
 
   Addr = WriteAddr % sEE_PAGESIZE;
@@ -643,15 +645,11 @@ void sEE_WriteBuffer(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWri
   * @brief  Wait for EEPROM Standby state.
   * 
   * @note  This function allows to wait and check that EEPROM has finished the 
-  *        last Write operation. It is mostly used after Write operation: after 
-  *        receiving the buffer to be written, the EEPROM may need additional 
-  *        time to actually perform the write operation. During this time, it 
-  *        doesn't answer to I2C packets addressed to it. Once the write operation 
-  *        is complete the EEPROM responds to its address.
-  *        
-  * @note  It is not necessary to call this function after sEE_WriteBuffer() 
-  *        function (sEE_WriteBuffer() already calls this function after each
-  *        write page operation).    
+  *        last operation. It is mostly used after Write operation: after receiving
+  *        the buffer to be written, the EEPROM may need additional time to actually
+  *        perform the write operation. During this time, it doesn't answer to
+  *        I2C packets addressed to it. Once the write operation is complete
+  *        the EEPROM responds to its address.
   * 
   * @param  None
   * @retval sEE_OK (0) if operation is correctly performed, else return value 
@@ -671,7 +669,7 @@ uint32_t sEE_WaitEepromStandbyState(void)
 
   /* Keep looping till the slave acknowledge his address or maximum number 
      of trials is reached (this number is defined by sEE_MAX_TRIALS_NUMBER define
-     in stm32_eval_i2c_ee.h file) */
+     in stm32l152_eval_i2c_ee.h file) */
   while (1)
   {
     /*!< Send START condition */
@@ -736,7 +734,7 @@ uint32_t sEE_WaitEepromStandbyState(void)
   */
 void sEE_I2C_DMA_TX_IRQHandler(void)
 {
-  /* Check if the DMA transfer is complete */ 
+  /* Check if the DMA transfer is complete */
   if(DMA_GetFlagStatus(sEE_I2C_DMA_FLAG_TX_TC) != RESET)
   {  
     /* Disable the DMA Tx Channel and Clear all its Flags */  
@@ -753,10 +751,6 @@ void sEE_I2C_DMA_TX_IRQHandler(void)
     /*!< Send STOP condition */
     I2C_GenerateSTOP(sEE_I2C, ENABLE);
     
-    /* Perform a read on SR1 and SR2 register to clear eventualaly pending flags */
-    (void)sEE_I2C->SR1;
-    (void)sEE_I2C->SR2;
-    
     /* Reset the variable holding the number of data to be written */
     *sEEDataWritePointer = 0;  
   }
@@ -799,42 +793,10 @@ uint32_t sEE_TIMEOUT_UserCallback(void)
 }
 #endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
 
-#ifdef USE_DEFAULT_CRITICAL_CALLBACK
-/**
-  * @brief  Start critical section: these callbacks should be typically used
-  *         to disable interrupts when entering a critical section of I2C communication
-  *         You may use default callbacks provided into this driver by uncommenting the 
-  *         define USE_DEFAULT_CRITICAL_CALLBACK.
-  *         Or you can comment that line and implement these callbacks into your 
-  *         application.
-  * @param  None.
-  * @retval None.
-  */
-void sEE_EnterCriticalSection_UserCallback(void)
-{
-  __disable_irq();  
-}
-
-/**
-  * @brief  Start and End of critical section: these callbacks should be typically used
-  *         to re-enable interrupts when exiting a critical section of I2C communication
-  *         You may use default callbacks provided into this driver by uncommenting the 
-  *         define USE_DEFAULT_CRITICAL_CALLBACK.
-  *         Or you can comment that line and implement these callbacks into your 
-  *         application.
-  * @param  None.
-  * @retval None.
-  */
-void sEE_ExitCriticalSection_UserCallback(void)
-{
-  __enable_irq();
-}
-#endif /* USE_DEFAULT_CRITICAL_CALLBACK */
-
 /**
   * @}
   */
-
+  
 /**
   * @}
   */
@@ -851,4 +813,4 @@ void sEE_ExitCriticalSection_UserCallback(void)
   * @}
   */  
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
index fa00fb7..fc41d9b 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/Common/stm32_eval_i2c_ee.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_ee.h
@@ -1,35 +1,41 @@
 /**
   ******************************************************************************
-  * @file    stm32_eval_i2c_ee.h
+  * @file    stm32l152_eval_i2c_ee.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm32_eval_i2c_ee
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the stm32l152_eval_i2c_ee
   *          firmware driver.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_EVAL_I2C_EE_H
-#define __STM32_EVAL_I2C_EE_H
+#ifndef __STM32L152_EVAL_I2C_EE_H
+#define __STM32L152_EVAL_I2C_EE_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
+#include "stm32l152_eval.h"
 
 /** @addtogroup Utilities
   * @{
@@ -39,15 +45,15 @@
   * @{
   */ 
 
-/** @addtogroup Common
+/** @addtogroup STM32L152_EVAL
   * @{
   */
   
-/** @addtogroup STM32_EVAL_I2C_EE
+/** @addtogroup STM32L152_EVAL_I2C_EE
   * @{
   */  
 
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Types
+/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Types
   * @{
   */ 
 
@@ -55,19 +61,9 @@
   * @}
   */
   
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Constants
+/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Constants
   * @{
   */
-  
-/* Uncomment this line to use the default start and end of critical section 
-   callbacks (it disables then enabled all interrupts) */
-#define USE_DEFAULT_CRITICAL_CALLBACK 
-/* Start and End of critical section: these callbacks should be typically used
-   to disable interrupts when entering a critical section of I2C communication
-   You may use default callbacks provided into this driver by uncommenting the 
-   define USE_DEFAULT_CRITICAL_CALLBACK.
-   Or you can comment that line and implement these callbacks into your 
-   application */
 
 /* Uncomment the following line to use the default sEE_TIMEOUT_UserCallback() 
    function implemented in stm32_evel_i2c_ee.c file.
@@ -101,7 +97,7 @@
 
 #endif /* sEE_M24C64_32 */
 
-#define I2C_SPEED               300000
+#define I2C_SPEED               200000
 #define I2C_SLAVE_ADDRESS7      0xA0
 
 #if defined (sEE_M24C08)
@@ -119,7 +115,7 @@
 #define sEE_LONG_TIMEOUT         ((uint32_t)(10 * sEE_FLAG_TIMEOUT))
 
 /* Maximum number of trials for sEE_WaitEepromStandbyState() function */
-#define sEE_MAX_TRIALS_NUMBER     150
+#define sEE_MAX_TRIALS_NUMBER     300
    
 /* Defintions for the state of the DMA transfer */   
 #define sEE_STATE_READY           0
@@ -133,14 +129,14 @@
   * @}
   */ 
   
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Macros
+/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Macros
   * @{
   */    
 /**
   * @}
   */ 
 
-/** @defgroup STM32_EVAL_I2C_EE_Exported_Functions
+/** @defgroup STM32L152_EVAL_I2C_EE_Exported_Functions
   * @{
   */ 
 void     sEE_DeInit(void);
@@ -161,21 +157,11 @@ uint32_t sEE_WaitEepromStandbyState(void);
    and re-initialize communication or in worst case reset all the application. */
 uint32_t sEE_TIMEOUT_UserCallback(void);
 
-/* Start and End of critical section: these callbacks should be typically used
-   to disable interrupts when entering a critical section of I2C communication
-   You may use default callbacks provided into this driver by uncommenting the 
-   define USE_DEFAULT_CRITICAL_CALLBACK in stm32_evel_i2c_ee.h file..
-   Or you can comment that line and implement these callbacks into your 
-   application */
-void sEE_EnterCriticalSection_UserCallback(void);
-void sEE_ExitCriticalSection_UserCallback(void);
-
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32_EVAL_I2C_EE_H */
+#endif /* __STM32L152_EVAL_I2C_EE_H */
 /**
   * @}
   */
@@ -196,6 +182,6 @@ void sEE_ExitCriticalSection_UserCallback(void);
   * @}
   */
 
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
 
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.c
new file mode 100644
index 0000000..3c15376
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.c
@@ -0,0 +1,982 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_i2c_tsensor.c
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to manage the I2C LM75 
+  *          temperature sensor mounted on STM32L152-EVAL board. 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this sensor. The needed STM32L hardware resources (I2C and 
+  *          GPIO) are defined in stm32l152_eval.h file, and the initialization is 
+  *          performed in LM75_LowLevel_Init() function declared in stm32l152_eval.c 
+  *          file.
+  *            
+  *          Note:
+  *          -----    
+  *          This driver uses the DMA method to send and receive data on I2C bus,
+  *          which allows higher efficiency and reliability  of the communication.
+  *                 
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          LM75_LowLevel_Init() function.
+  *
+  *     +-----------------------------------------------------------------+
+  *     |                        Pin assignment                           |                 
+  *     +---------------------------------------+-----------+-------------+
+  *     |  STM32 I2C Pins                       |   STLM75  |   Pin       |
+  *     +---------------------------------------+-----------+-------------+
+  *     | LM75_I2C_SDA_PIN/ SDA                 |   SDA     |    1        |
+  *     | LM75_I2C_SCL_PIN/ SCL                 |   SCL     |    2        |
+  *     | LM75_I2C_SMBUSALERT_PIN/ SMBUS ALERT  |   OS/INT  |    3        |
+  *     | .                                     |   GND     |    4  (0V)  |
+  *     | .                                     |   GND     |    5  (0V)  |
+  *     | .                                     |   GND     |    6  (0V)  |
+  *     | .                                     |   GND     |    7  (0V)  |
+  *     | .                                     |   VDD     |    8  (3.3V)|
+  *     +---------------------------------------+-----------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval_i2c_tsensor.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152_EVAL_I2C_TSENSOR
+  * @brief      This file includes the LM75 Temperature Sensor driver of 
+  *             STM32-EVAL boards.
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Defines
+  * @{
+  */ 
+#define LM75_SD_SET                0x01 /*!< Set SD bit in the configuration register */
+#define LM75_SD_RESET              0xFE /*!< Reset SD bit in the configuration register */
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Variables
+  * @{
+  */ 
+  
+__IO uint32_t  LM75_Timeout = LM75_LONG_TIMEOUT; 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Function_Prototypes
+  * @{
+  */ 
+static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData);
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_DeInit(void)
+{
+  LM75_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the LM75_I2C.
+  * @param  None
+  * @retval None
+  */
+void LM75_Init(void)
+{
+  I2C_InitTypeDef   I2C_InitStructure;
+  
+  LM75_LowLevel_Init();
+  
+  I2C_DeInit(LM75_I2C);
+
+  /*!< LM75_I2C Init */
+  I2C_InitStructure.I2C_Mode = I2C_Mode_SMBusHost;
+  I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+  I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+  I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+  I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+  I2C_InitStructure.I2C_ClockSpeed = LM75_I2C_SPEED;
+  I2C_Init(LM75_I2C, &I2C_InitStructure);
+
+  /*!< Enable SMBus Alert interrupt */
+  I2C_ITConfig(LM75_I2C, I2C_IT_ERR, ENABLE);
+
+  /*!< LM75_I2C Init */
+  I2C_Cmd(LM75_I2C, ENABLE);
+}
+
+
+/**
+  * @brief  Configure the DMA Peripheral used to handle communication via I2C.
+  * @param  None
+  * @retval None
+  */
+
+static void LM75_DMA_Config(LM75_DMADirection_TypeDef Direction, uint8_t* buffer, uint8_t NumData)
+{
+  DMA_InitTypeDef DMA_InitStructure;
+  
+  RCC_AHBPeriphClockCmd(LM75_DMA_CLK, ENABLE);
+  
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStructure.DMA_PeripheralBaseAddr = LM75_I2C_DR;
+  /* Initialize the DMA_MemoryBaseAddr member */
+  DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)buffer;
+   /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+  /* Initialize the DMA_Mode member */
+  DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+  /* Initialize the DMA_Priority member */
+  DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
+  /* Initialize the DMA_M2M member */
+  DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+  
+  /* If using DMA for Reception */
+  if (Direction == LM75_DMA_RX)
+  {
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = NumData;
+    
+    DMA_DeInit(LM75_DMA_RX_CHANNEL);
+    
+    DMA_Init(LM75_DMA_RX_CHANNEL, &DMA_InitStructure);
+  }
+   /* If using DMA for Transmission */
+  else if (Direction == LM75_DMA_TX)
+  { 
+    /* Initialize the DMA_DIR member */
+    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+    
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStructure.DMA_BufferSize = NumData;
+    
+    DMA_DeInit(LM75_DMA_TX_CHANNEL);
+    
+    DMA_Init(LM75_DMA_TX_CHANNEL, &DMA_InitStructure);
+  }
+}
+
+
+/**
+  * @brief  Checks the LM75 status.
+  * @param  None
+  * @retval ErrorStatus: LM75 Status (ERROR or SUCCESS).
+  */
+ErrorStatus LM75_GetStatus(void)
+{
+  uint32_t I2C_TimeOut = I2C_TIMEOUT;
+
+  /*!< Clear the LM75_I2C AF flag */
+  I2C_ClearFlag(LM75_I2C, I2C_FLAG_AF);
+
+  /*!< Enable LM75_I2C acknowledgement if it is already disabled by other function */
+  I2C_AcknowledgeConfig(LM75_I2C, ENABLE);
+
+  /*---------------------------- Transmission Phase ---------------------------*/
+
+  /*!< Send LM75_I2C START condition */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+
+  /*!< Test on LM75_I2C EV5 and clear it */
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) && I2C_TimeOut)  /*!< EV5 */
+  {
+    I2C_TimeOut--;
+  }
+  if (I2C_TimeOut == 0)
+  {
+    return ERROR;
+  }
+  
+  I2C_TimeOut = I2C_TIMEOUT;
+
+  /*!< Send STLM75 slave address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+
+  while ((!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) && I2C_TimeOut)/* EV6 */
+  {
+    I2C_TimeOut--;
+  }
+
+  if ((I2C_GetFlagStatus(LM75_I2C, I2C_FLAG_AF) != 0x00) || (I2C_TimeOut == 0))
+  {
+    return ERROR;
+  }
+  else
+  {
+    return SUCCESS;
+  }
+}
+/**
+  * @brief  Read the specified register from the LM75.
+  * @param  RegName: specifies the LM75 register to be read.
+  *              This member can be one of the following values:  
+  *                  - LM75_REG_TEMP: temperature register
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @retval LM75 register value.
+  */
+uint16_t LM75_ReadReg(uint8_t RegName)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint16_t tmp = 0;    
+  
+   /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, RegName);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
+  tmp |= LM75_BufferRX[1];
+  
+  /* return a Reg value */
+  return (uint16_t)tmp;  
+}
+
+/**
+  * @brief  Write to the specified register of the LM75.
+  * @param  RegName: specifies the LM75 register to be written.
+  *              This member can be one of the following values:    
+  *                  - LM75_REG_TOS: Over-limit temperature register
+  *                  - LM75_REG_THYS: Hysteresis temperature register
+  * @param  RegValue: value to be written to LM75 register.  
+  * @retval None
+  */
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue)
+{   
+  uint8_t LM75_BufferTX[2] ={0,0};
+  LM75_BufferTX[0] = (uint8_t)(RegValue >> 8);
+  LM75_BufferTX[1] = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)LM75_BufferTX, 2);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, RegName);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);
+  
+  return LM75_OK;
+}
+
+/**
+  * @brief  Read Temperature register of LM75: double temperature value.
+  * @param  None
+  * @retval LM75 measured temperature value.
+  */
+uint16_t LM75_ReadTemp(void)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint16_t tmp = 0;
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_TEMP);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Store LM75_I2C received data */
+  tmp = (uint16_t)(LM75_BufferRX[0] << 8);
+  tmp |= LM75_BufferRX[1];    
+  
+  /*!< Return Temperature value */
+  return (uint16_t)(tmp >> 7);
+}
+
+/**
+  * @brief  Read the configuration register from the LM75.
+  * @param  None
+  * @retval LM75 configuration register value.
+  */
+uint8_t LM75_ReadConfReg(void)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0}; 
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Return Temperature value */
+  return (uint8_t)LM75_BufferRX[0];
+}
+
+/**
+  * @brief  Write to the configuration register of the LM75.
+  * @param  RegValue: sepecifies the value to be written to LM75 configuration 
+  *         register.
+  * @retval None
+  */
+uint8_t LM75_WriteConfReg(uint8_t RegValue)
+{   
+  uint8_t LM75_BufferTX = 0;  
+  LM75_BufferTX = (uint8_t)(RegValue);
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
+  
+  return LM75_OK;
+  
+}
+
+/**
+  * @brief  Enables or disables the LM75.
+  * @param  NewState: specifies the LM75 new status. This parameter can be ENABLE
+  *         or DISABLE.  
+  * @retval None
+  */
+uint8_t LM75_ShutDown(FunctionalState NewState)
+{   
+  uint8_t LM75_BufferRX[2] ={0,0};
+  uint8_t LM75_BufferTX = 0;
+  __IO uint8_t RegValue = 0;    
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_RX, (uint8_t*)LM75_BufferRX, 2);  
+  
+  /* Enable DMA NACK automatic generation */
+  I2C_DMALastTransferCmd(LM75_I2C, ENABLE);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send device address for write */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send the device's internal address to write to */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);  
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send START condition a second time */  
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send LM75 address for read */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Receiver);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))   
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_RX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }        
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA RX Channel */
+  DMA_Cmd(LM75_DMA_RX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA RX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_RX_TCFLAG);
+  
+  /*!< Get received data */
+  RegValue = (uint8_t)LM75_BufferRX[0];
+  
+  /*---------------------------- Transmission Phase ---------------------------*/
+  
+  /*!< Enable or disable SD bit */
+  if (NewState != DISABLE)
+  {
+    /*!< Enable LM75 */
+    LM75_BufferTX = RegValue & LM75_SD_RESET;
+  }
+  else
+  {
+    /*!< Disable LM75 */
+    LM75_BufferTX = RegValue | LM75_SD_SET;
+  }  
+  
+  /* Test on BUSY Flag */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BUSY)) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Configure DMA Peripheral */
+  LM75_DMA_Config(LM75_DMA_TX, (uint8_t*)(&LM75_BufferTX), 1);
+  
+  /* Enable the I2C peripheral */
+  I2C_GenerateSTART(LM75_I2C, ENABLE);
+  
+  /* Test on SB Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_SB) == RESET) 
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the slave address and enable writing operation */
+  I2C_Send7bitAddress(LM75_I2C, LM75_ADDR, I2C_Direction_Transmitter);
+  
+  /* Test on ADDR Flag */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while (!I2C_CheckEvent(LM75_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Transmit the first address for r/w operations */
+  I2C_SendData(LM75_I2C, LM75_REG_CONF);
+  
+  /* Test on TXE FLag (data sent) */
+  LM75_Timeout = LM75_FLAG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_TXE)) && (!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Enable I2C DMA request */
+  I2C_DMACmd(LM75_I2C,ENABLE);
+  
+  /* Enable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, ENABLE);
+  
+  /* Wait until DMA Transfer Complete */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while (!DMA_GetFlagStatus(LM75_DMA_TX_TCFLAG))
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }  
+  
+  /* Wait until BTF Flag is set before generating STOP */
+  LM75_Timeout = LM75_LONG_TIMEOUT;
+  while ((!I2C_GetFlagStatus(LM75_I2C,I2C_FLAG_BTF)))  
+  {
+    if((LM75_Timeout--) == 0) return LM75_TIMEOUT_UserCallback();
+  }
+  
+  /* Send STOP Condition */
+  I2C_GenerateSTOP(LM75_I2C, ENABLE);
+  
+  /* Disable DMA TX Channel */
+  DMA_Cmd(LM75_DMA_TX_CHANNEL, DISABLE);
+  
+  /* Disable I2C DMA request */  
+  I2C_DMACmd(LM75_I2C,DISABLE);
+  
+  /* Clear DMA TX Transfer Complete Flag */
+  DMA_ClearFlag(LM75_DMA_TX_TCFLAG);  
+  
+  return LM75_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.h
new file mode 100644
index 0000000..668ac91
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_i2c_tsensor.h
@@ -0,0 +1,179 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_i2c_tsensor.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the 
+  *          stm32l152_eval_i2c_tsensor firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152_EVAL_I2C_TSENSOR_H
+#define __STM32L152_EVAL_I2C_TSENSOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152_EVAL_I2C_TSENSOR
+  * @{
+  */  
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Exported_Types
+  * @{
+  */
+   
+ /** 
+  * @brief  IOE DMA Direction  
+  */ 
+typedef enum
+{
+  LM75_DMA_TX = 0,
+  LM75_DMA_RX = 1
+}LM75_DMADirection_TypeDef;
+
+/** 
+  * @brief  TSENSOR Status  
+  */ 
+typedef enum
+{
+  LM75_OK = 0,
+  LM75_FAIL
+}LM75_Status_TypDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Exported_Constants
+  * @{
+  */ 
+    
+/* Uncomment the following line to use Timeout_User_Callback LM75_TimeoutUserCallback(). 
+   If This Callback is enabled, it should be implemented by user in main function .
+   LM75_TimeoutUserCallback() function is called whenever a timeout condition 
+   occure during communication (waiting on an event that doesn't occur, bus 
+   errors, busy devices ...). */   
+/* #define USE_TIMEOUT_USER_CALLBACK */    
+    
+/* Maximum Timeout values for flags and events waiting loops. These timeouts are
+   not based on accurate values, they just guarantee that the application will 
+   not remain stuck if the I2C communication is corrupted.
+   You may modify these timeout values depending on CPU frequency and application
+   conditions (interrupts routines ...). */   
+#define LM75_FLAG_TIMEOUT         ((uint32_t)0x1000)
+#define LM75_LONG_TIMEOUT         ((uint32_t)(10 * LM75_FLAG_TIMEOUT))    
+    
+
+/**
+  * @brief  Block Size
+  */
+#define LM75_REG_TEMP       0x00  /*!< Temperature Register of LM75 */
+#define LM75_REG_CONF       0x01  /*!< Configuration Register of LM75 */
+#define LM75_REG_THYS       0x02  /*!< Temperature Register of LM75 */
+#define LM75_REG_TOS        0x03  /*!< Over-temp Shutdown threshold Register of LM75 */
+#define I2C_TIMEOUT         ((uint32_t)0x3FFFF) /*!< I2C Time out */
+#define LM75_ADDR           0x90   /*!< LM75 address */
+#define LM75_I2C_SPEED      100000 /*!< I2C Speed */
+  
+   
+
+/**
+  * @}
+  */
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_I2C_TSENSOR_Exported_Functions
+  * @{
+  */ 
+void LM75_DeInit(void);
+void LM75_Init(void);
+ErrorStatus LM75_GetStatus(void);
+uint16_t LM75_ReadTemp(void);
+uint16_t LM75_ReadReg(uint8_t RegName);
+uint8_t LM75_WriteReg(uint8_t RegName, uint16_t RegValue);
+uint8_t LM75_ReadConfReg(void);
+uint8_t LM75_WriteConfReg(uint8_t RegValue);
+uint8_t LM75_ShutDown(FunctionalState NewState);
+
+/** 
+  * @brief  Timeout user callback function. This function is called when a timeout
+  *         condition occurs during communication with IO Expander. Only protoype
+  *         of this function is decalred in IO Expander driver. Its implementation
+  *         may be done into user application. This function may typically stop
+  *         current operations and reset the I2C peripheral and IO Expander.
+  *         To enable this function use uncomment the define USE_TIMEOUT_USER_CALLBACK
+  *         at the top of this file.          
+  */
+#ifdef USE_TIMEOUT_USER_CALLBACK 
+ uint8_t LM75_TIMEOUT_UserCallback(void);
+#else
+ #define LM75_TIMEOUT_UserCallback()  LM75_FAIL
+#endif /* USE_TIMEOUT_USER_CALLBACK */
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152_EVAL_I2C_TSENSOR_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
index 3f547e3..1572a8e 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.c
@@ -1,27 +1,34 @@
 /**
   ******************************************************************************
-  * @file    stm3210c_eval_lcd.c
+  * @file    stm32l152_eval_lcd.c
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
-  *          Liquid Crystal Display Module of STM3210C-EVAL board.
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) and AM240320D5TOQW01H (LCD_ILI9325) 
+  *          Liquid Crystal Display Module of STM32L152-EVAL board RevB.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm3210c_eval_lcd.h"
+#include "stm32l152_eval_lcd.h"
 #include "../Common/fonts.c"
 
 /** @addtogroup Utilities
@@ -32,27 +39,30 @@
   * @{
   */ 
 
-/** @addtogroup STM3210C_EVAL
+/** @addtogroup STM32L152_EVAL
   * @{
   */
     
-/** @defgroup STM3210C_EVAL_LCD 
-  * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
-  *        Liquid Crystal Display Module of STM3210C-EVAL board.
+/** @defgroup STM32L152_EVAL_LCD 
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320), 
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) and AM240320D5TOQW01H (LCD_ILI9325) 
+  *          Liquid Crystal Display Module of STM32L152-EVAL board.
   * @{
   */ 
 
-/** @defgroup STM3210C_EVAL_LCD_Private_TypesDefinitions
+/** @defgroup STM32L152_EVAL_LCD_Private_Types
   * @{
   */ 
 /**
   * @}
   */ 
 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Defines
+/** @defgroup STM32L152_EVAL_LCD_Private_Defines
   * @{
   */ 
+#define LCD_ILI9325        0x9325
+#define LCD_ILI9320        0x9320
+#define LCD_SPFD5408       0x5408
 #define START_BYTE         0x70
 #define SET_INDEX          0x00
 #define READ_STATUS        0x01
@@ -65,41 +75,40 @@
   * @}
   */ 
 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Macros
+/** @defgroup STM32L152_EVAL_LCD_Private_Macros
   * @{
-  */
-#define ABS(X)  ((X) > 0 ? (X) : -(X))    
+  */ 
+#define ABS(X)  ((X) > 0 ? (X) : -(X))  
 /**
   * @}
   */ 
 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Variables
+/** @defgroup STM32L152_EVAL_LCD_Private_Variables
   * @{
   */ 
 static sFONT *LCD_Currentfonts;
 /* Global variables to set the written text color */
-static  __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
+static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
+static __IO uint32_t LCDType = LCD_SPFD5408;
 /**
   * @}
   */ 
 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_FunctionPrototypes
+/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes
   * @{
   */ 
 #ifndef USE_Delay
 static void delay(__IO uint32_t nCount);
 #endif /* USE_Delay*/
+
 static void PutPixel(int16_t x, int16_t y);
 static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);
+
 /**
   * @}
   */ 
 
-
-/** @defgroup STM3210C_EVAL_LCD_Private_Functions
+/** @defgroup STM32L152_EVAL_LCD_Private_Functions
   * @{
   */ 
 
@@ -108,7 +117,7 @@ static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint1
   * @param  None
   * @retval None
   */
-void LCD_DeInit(void)
+void STM32L152_LCD_DeInit(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
 
@@ -119,15 +128,15 @@ void LCD_DeInit(void)
   SPI_Cmd(LCD_SPI, DISABLE);
   
   /*!< LCD_SPI DeInit */
-  SPI_I2S_DeInit(LCD_SPI);
+  SPI_DeInit(LCD_SPI);
    
   /*!< Disable SPI clock  */
   RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, DISABLE);
     
   /* Configure NCS in Output Push-Pull mode */
   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
   GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
    
   /* Configure SPI pins: SCK, MISO and MOSI */
@@ -152,76 +161,229 @@ void LCD_Setup(void)
   LCD_CtrlLinesConfig();
   
 /* Configure the LCD_SPI interface ----------------------------------------------*/
-  LCD_SPIConfig();
-  _delay_(5); /* Delay 50 ms */
-  /* Start Initial Sequence ------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
-  LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
-  LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
-  LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
-  LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
-  LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
-  LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
-  LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
-  LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
-  LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
-  LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
-  LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
-  /* Power On sequence -----------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
-  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
-  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
-  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
-  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
-  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* Delay 50 ms */
-  LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
-  LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
-  /* Adjust the Gamma Curve ------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_48, 0x0006);
-  LCD_WriteReg(LCD_REG_49, 0x0101);
-  LCD_WriteReg(LCD_REG_50, 0x0003);
-  LCD_WriteReg(LCD_REG_53, 0x0106);
-  LCD_WriteReg(LCD_REG_54, 0x0b02);
-  LCD_WriteReg(LCD_REG_55, 0x0302);
-  LCD_WriteReg(LCD_REG_56, 0x0707);
-  LCD_WriteReg(LCD_REG_57, 0x0007);
-  LCD_WriteReg(LCD_REG_60, 0x0600);
-  LCD_WriteReg(LCD_REG_61, 0x020b);
+  LCD_SPIConfig(); 
+    
+  if(LCDType == LCD_SPFD5408)
+  {   
+    /* Start Initial Sequence --------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */
+    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */
+    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */
+    /* Power On sequence -------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */  
+    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                 /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    _delay_(5);                  /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */
+    _delay_(5);                 /* Delay 50 ms */ 
+    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */
+    _delay_(5);                 /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */
+    /* Adjust the Gamma Curve --------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0007);
+    LCD_WriteReg(LCD_REG_49, 0x0302);
+    LCD_WriteReg(LCD_REG_50, 0x0105);
+    LCD_WriteReg(LCD_REG_53, 0x0206);
+    LCD_WriteReg(LCD_REG_54, 0x0808);
+    LCD_WriteReg(LCD_REG_55, 0x0206);
+    LCD_WriteReg(LCD_REG_56, 0x0504);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0105);
+    LCD_WriteReg(LCD_REG_61, 0x0808);
+    /* Set GRAM area -----------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */
+    /* Partial Display Control -------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+    /* Panel Control -----------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+    /* Set GRAM write direction and BGR = 1
+       I/D=01 (Horizontal : increment, Vertical : decrement)
+       AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */
+  } 
+  else if(LCDType == LCD_ILI9320)
+  {
+    _delay_(5); /* Delay 50 ms */
+    /* Start Initial Sequence ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */
+    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */
+    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */
+    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
+    /* Power On sequence -----------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
+    /* Adjust the Gamma Curve ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0006);
+    LCD_WriteReg(LCD_REG_49, 0x0101);
+    LCD_WriteReg(LCD_REG_50, 0x0003);
+    LCD_WriteReg(LCD_REG_53, 0x0106);
+    LCD_WriteReg(LCD_REG_54, 0x0b02);
+    LCD_WriteReg(LCD_REG_55, 0x0302);
+    LCD_WriteReg(LCD_REG_56, 0x0707);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0600);
+    LCD_WriteReg(LCD_REG_61, 0x020b);
   
-  /* Set GRAM area ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
-  LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
-  LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
-  LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
-  LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
-  LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
-  LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
-  /* Partial Display Control -----------------------------------------------*/
-  LCD_WriteReg(LCD_REG_128, 0x0000);
-  LCD_WriteReg(LCD_REG_129, 0x0000);
-  LCD_WriteReg(LCD_REG_130, 0x0000);
-  LCD_WriteReg(LCD_REG_131, 0x0000);
-  LCD_WriteReg(LCD_REG_132, 0x0000);
-  LCD_WriteReg(LCD_REG_133, 0x0000);
-  /* Panel Control ---------------------------------------------------------*/
-  LCD_WriteReg(LCD_REG_144, 0x0010);
-  LCD_WriteReg(LCD_REG_146, 0x0000);
-  LCD_WriteReg(LCD_REG_147, 0x0003);
-  LCD_WriteReg(LCD_REG_149, 0x0110);
-  LCD_WriteReg(LCD_REG_151, 0x0000);
-  LCD_WriteReg(LCD_REG_152, 0x0000);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=01 (Horizontal : increment, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+    /* Set GRAM area ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
+    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
+    /* Partial Display Control -----------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+    /* Panel Control ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D=01 (Horizontal : increment, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
+  }
+  else if(LCDType == LCD_ILI9325)
+  {
+    /* Start Initial Sequence ------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_0, 0x0001); /* Start internal OSC. */
+    LCD_WriteReg(LCD_REG_1, 0x0100); /* Set SS and SM bit */
+    LCD_WriteReg(LCD_REG_2, 0x0700); /* Set 1 line inversion */
+    LCD_WriteReg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */
+    LCD_WriteReg(LCD_REG_4, 0x0000); /* Resize register */
+    LCD_WriteReg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */
+    LCD_WriteReg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */
+
+    /* Power On sequence -----------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
+    _delay_(5);                       /* Delay 50 ms */
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */
+
+    /* Adjust the Gamma Curve (ILI9325)---------------------------------------*/
+    LCD_WriteReg(LCD_REG_48, 0x0007);
+    LCD_WriteReg(LCD_REG_49, 0x0302);
+    LCD_WriteReg(LCD_REG_50, 0x0105);
+    LCD_WriteReg(LCD_REG_53, 0x0206);
+    LCD_WriteReg(LCD_REG_54, 0x0808);
+    LCD_WriteReg(LCD_REG_55, 0x0206);
+    LCD_WriteReg(LCD_REG_56, 0x0504);
+    LCD_WriteReg(LCD_REG_57, 0x0007);
+    LCD_WriteReg(LCD_REG_60, 0x0105);
+    LCD_WriteReg(LCD_REG_61, 0x0808);
+
+    /* Set GRAM area ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */
+
+    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */
+
+    /* Partial Display Control -----------------------------------------------*/
+    LCD_WriteReg(LCD_REG_128, 0x0000);
+    LCD_WriteReg(LCD_REG_129, 0x0000);
+    LCD_WriteReg(LCD_REG_130, 0x0000);
+    LCD_WriteReg(LCD_REG_131, 0x0000);
+    LCD_WriteReg(LCD_REG_132, 0x0000);
+    LCD_WriteReg(LCD_REG_133, 0x0000);
+
+    /* Panel Control ---------------------------------------------------------*/
+    LCD_WriteReg(LCD_REG_144, 0x0010);
+    LCD_WriteReg(LCD_REG_146, 0x0000);
+    LCD_WriteReg(LCD_REG_147, 0x0003);
+    LCD_WriteReg(LCD_REG_149, 0x0110);
+    LCD_WriteReg(LCD_REG_151, 0x0000);
+    LCD_WriteReg(LCD_REG_152, 0x0000);
+
+    /* set GRAM write direction and BGR = 1 */
+    /* I/D=00 (Horizontal : increment, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+
+    LCD_WriteReg(LCD_REG_7, 0x0133); /* 262K color and display ON */ 
+  }  
 }
 
 
@@ -230,10 +392,33 @@ void LCD_Setup(void)
   * @param  None
   * @retval None
   */
-void STM3210C_LCD_Init(void)
-{
+void STM32L152_LCD_Init(void)
+{ 
+  __IO uint32_t lcdid = 0;
+  
   /* Setups the LCD */
   LCD_Setup();
+
+  /* Read the LCD ID */
+  lcdid = LCD_ReadReg(0x00);  
+  
+  if (lcdid == LCD_SPFD5408)
+  {
+    LCDType = LCD_SPFD5408;
+  }
+  else if (lcdid == LCD_ILI9320)
+  {
+    LCDType = LCD_ILI9320;
+    /* Setups the LCD */
+    LCD_Setup();    
+  }  
+  else
+  {
+    LCDType = LCD_ILI9325;
+    /* Setups the LCD */
+    LCD_Setup();
+  } 
+    
   LCD_SetFont(&LCD_DEFAULT_FONT);
 }
 
@@ -306,15 +491,16 @@ sFONT *LCD_GetFont(void)
 /**
   * @brief  Clears the selected line.
   * @param  Line: the Line to be cleared.
-  *   This parameter can be one of the following values:
-  *     @arg Linex: where x can be 0..n
+  *         This parameter can be one of the following values:
+  *             @arg Linex: where x can be 0..n
   * @retval None
   */
-void LCD_ClearLine(uint8_t Line)
+void LCD_ClearLine(uint16_t Line)
 {
   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
+  
   /* Send the string character by character on lCD */
-  while (((refcolumn + 1)& 0xFFFF) >= LCD_Currentfonts->Width)
+  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)
   {
     /* Display one character on LCD */
     LCD_DisplayChar(Line, refcolumn, ' ');
@@ -334,13 +520,16 @@ void LCD_Clear(uint16_t Color)
   uint32_t index = 0;
   
   LCD_SetCursor(0x00, 0x013F); 
+
   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  
   for(index = 0; index < 76800; index++)
   {
     LCD_WriteRAM(Color);
   }
+
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
-  
+ 
 }
 
 
@@ -350,10 +539,10 @@ void LCD_Clear(uint16_t Color)
   * @param  Ypos: specifies the Y position. 
   * @retval None
   */
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
+void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos)
 {
- LCD_WriteReg(LCD_REG_32, Xpos);
- LCD_WriteReg(LCD_REG_33, Ypos);
+  LCD_WriteReg(LCD_REG_32, Xpos);
+  LCD_WriteReg(LCD_REG_33, Ypos);
 }
 
 
@@ -364,10 +553,10 @@ void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
   * @param  c: pointer to the character data.
   * @retval None
   */
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
+void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c)
 {
   uint32_t index = 0, i = 0;
-  uint8_t Xaddress = 0;
+  uint16_t Xaddress = 0;
    
   Xaddress = Xpos;
   
@@ -376,6 +565,7 @@ void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
   for(index = 0; index < LCD_Currentfonts->Height; index++)
   {
     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+
     for(i = 0; i < LCD_Currentfonts->Width; i++)
     {
       if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||
@@ -388,7 +578,8 @@ void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
       {
         LCD_WriteRAM(TextColor);
       }
-    }   
+    }
+
     LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET); 
     Xaddress++;
     LCD_SetCursor(Xaddress, Ypos);
@@ -405,7 +596,7 @@ void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
   * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.
   * @retval None
   */
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
+void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii)
 {
   Ascii -= 32;
   LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);
@@ -420,7 +611,7 @@ void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
   * @param  *ptr: pointer to string to display on LCD.
   * @retval None
   */
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
+void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr)
 {
   uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;
 
@@ -445,8 +636,8 @@ void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
   * @param  Width: display window width.
   * @retval None
   */
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
-{ 
+void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+{
   /* Horizontal GRAM Start Address */
   if(Xpos >= Height)
   {
@@ -469,6 +660,7 @@ void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t
   }
   /* Vertical GRAM End Address */
   LCD_WriteReg(LCD_REG_83, Ypos);
+
   LCD_SetCursor(Xpos, Ypos);
 }
 
@@ -484,24 +676,25 @@ void LCD_WindowModeDisable(void)
   LCD_WriteReg(LCD_REG_3, 0x1018);    
 }
 
-
 /**
   * @brief  Displays a line.
   * @param  Xpos: specifies the X position.
   * @param  Ypos: specifies the Y position.
   * @param  Length: line length.
   * @param  Direction: line direction.
-  *   This parameter can be one of the following values: Vertical or Horizontal.
+  *         This parameter can be one of the following values: Vertical or Horizontal.
   * @retval None
   */
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
+void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
 {
   uint32_t i = 0;
   
   LCD_SetCursor(Xpos, Ypos);
+  
   if(Direction == LCD_DIR_HORIZONTAL)
   { 
     LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+    
     for(i = 0; i < Length; i++)
     {
       LCD_WriteRAM(TextColor);
@@ -528,7 +721,7 @@ void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Directio
   * @param  Width: display rectangle width.
   * @retval None
   */
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
 {
   LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);
   LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);
@@ -545,9 +738,9 @@ void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
   * @param  Radius
   * @retval None
   */
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
+void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
 {
-  s32  D;/* Decision Variable */ 
+  int32_t  D;/* Decision Variable */ 
   uint32_t  CurX;/* Current X Value */
   uint32_t  CurY;/* Current Y Value */ 
   
@@ -559,20 +752,27 @@ void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
   {
     LCD_SetCursor(Xpos + CurX, Ypos + CurY);
     LCD_WriteRAMWord(TextColor);
-    LCD_SetCursor(Xpos + CurX, Ypos - CurY);
+    LCD_SetCursor(Xpos + CurX, Ypos - CurY); 
     LCD_WriteRAMWord(TextColor);
+    
     LCD_SetCursor(Xpos - CurX, Ypos + CurY);
     LCD_WriteRAMWord(TextColor);
+
     LCD_SetCursor(Xpos - CurX, Ypos - CurY);
     LCD_WriteRAMWord(TextColor);
+ 
     LCD_SetCursor(Xpos + CurY, Ypos + CurX);
     LCD_WriteRAMWord(TextColor);
+
     LCD_SetCursor(Xpos + CurY, Ypos - CurX);
     LCD_WriteRAMWord(TextColor);
+
     LCD_SetCursor(Xpos - CurY, Ypos + CurX);
     LCD_WriteRAMWord(TextColor);
+
     LCD_SetCursor(Xpos - CurY, Ypos - CurX);
     LCD_WriteRAMWord(TextColor);
+
     if (D < 0)
     { 
       D += (CurX << 2) + 6;
@@ -586,6 +786,7 @@ void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
   }
 }
 
+
 /**
   * @brief  Displays a monocolor picture.
   * @param  Pict: pointer to the picture array.
@@ -595,7 +796,9 @@ void LCD_DrawMonoPict(const uint32_t *Pict)
 {
   uint32_t index = 0, i = 0;
   LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1)); 
+
   LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+
   for(index = 0; index < 2400; index++)
   {
     for(i = 0; i < 32; i++)
@@ -610,102 +813,71 @@ void LCD_DrawMonoPict(const uint32_t *Pict)
       }
     }
   }
+
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
 }
 
-#ifdef USE_LCD_DrawBMP
+#ifdef USE_LCD_DrawBMP 
 /**
   * @brief  Displays a bitmap picture loaded in the SPI Flash.
   * @param  BmpAddress: Bmp picture address in the SPI Flash.
   * @retval None
   */
-//void LCD_DrawBMP(uint32_t BmpAddress)
-//{
-//  uint32_t i = 0, size = 0;
-//
-//  /* Read bitmap size */
-//  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
-//
-//  /* get bitmap data address offset */
-//  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
-//  
-//  size = (size - i)/2;
-//
-//  sFLASH_StartReadSequence(BmpAddress + i);
-//
-//  /* Disable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, DISABLE);
-//  /* SPI in 16-bit mode */
-//  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
-//
-//  /* Enable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, ENABLE);
-//  
-//  /* Set GRAM write direction and BGR = 1 */
-//  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-//  /* AM=1 (address is updated in vertical writing direction) */
-//  LCD_WriteReg(LCD_REG_3, 0x1008);
-//
-//  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
-//
-//  /* Read bitmap data from SPI Flash and send them to LCD */
-//  for(i = 0; i < size; i++)
-//  {
-//    LCD_WriteRAM(__REV_HalfWord(sFLASH_SendHalfWord(0xA5A5)));
-//  }
-//
-//  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-//
-//  /* Deselect the FLASH: Chip Select high */
-//  sFLASH_CS_HIGH();
-//
-//  /* Disable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, DISABLE);
-//  /* SPI in 8-bit mode */
-//  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
-//
-//  /* Enable LCD_SPI  */
-//  SPI_Cmd(LCD_SPI, ENABLE);
-//
-//  /* Set GRAM write direction and BGR = 1 */
-//  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-//  /* AM = 1 (address is updated in vertical writing direction) */
-//  LCD_WriteReg(LCD_REG_3, 0x1018);
-//}
-
-
-/**
-  * @brief  Displays a bitmap picture loaded in the Internal FLASH.
-  * @param  BmpAddress: Bmp picture address in the Internal FLASH.
-  * @retval None
-  */
-void LCD_DrawBMP(const uint16_t *BmpAddress)
+void LCD_DrawBMP(uint32_t BmpAddress)
 {
   uint32_t i = 0, size = 0;
   /* Read bitmap size */
-  size = BmpAddress[1] | (BmpAddress[2] << 16);
+  sFLASH_ReadBuffer((uint8_t*)&size, BmpAddress + 2, 4);
   /* get bitmap data address offset */
-  i = BmpAddress[5] | (BmpAddress[6] << 16);
+  sFLASH_ReadBuffer((uint8_t*)&i, BmpAddress + 10, 4);
+  
   size = (size - i)/2;
-  BmpAddress += i/2;
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
-  /* AM=1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1008);
-  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  sFLASH_StartReadSequence(BmpAddress + i);
+  /* Disable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, DISABLE);
+  /* SPI in 16-bit mode */
+  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_16b);
+  /* Enable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, ENABLE);
+  
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
+    /* AM=1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1008);
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+  }
+  
   /* Read bitmap data from SPI Flash and send them to LCD */
   for(i = 0; i < size; i++)
   {
-    LCD_WriteRAM(BmpAddress[i]);
+    LCD_WriteRAM(__REV16(sFLASH_SendHalfWord(0xA5A5)));
   }
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-  /* Set GRAM write direction and BGR = 1 */
-  /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
-  /* AM = 1 (address is updated in vertical writing direction) */
-  LCD_WriteReg(LCD_REG_3, 0x1018);
-}
-#endif
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+  }
+
+  /* Deselect the FLASH: Chip Select high */
+  sFLASH_CS_HIGH();
+  /* Disable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, DISABLE);
+  /* SPI in 8-bit mode */
+  SPI_DataSizeConfig(LCD_SPI, SPI_DataSize_8b);
+  /* Enable LCD_SPI  */
+  SPI_Cmd(LCD_SPI, ENABLE);
 
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))
+  {
+    /* Set GRAM write direction and BGR = 1 */
+    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
+    /* AM = 1 (address is updated in vertical writing direction) */
+    LCD_WriteReg(LCD_REG_3, 0x1018);
+  }
+}
+#endif /* USE_LCD_DrawBMP */
+ 
 /**
   * @brief  Displays a full rectangle.
   * @param  Xpos: specifies the X position.
@@ -1002,7 +1174,8 @@ void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
 
     for (i = 0; i < PointCount; i++) 
     {
-      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY) 
+      if (((POLY_Y(i)<(double) pixelY) && (POLY_Y(j)>=(double) pixelY)) || \
+          ((POLY_Y(j)<(double) pixelY) && (POLY_Y(i)>=(double) pixelY)))
       {
         nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i))); 
       }
@@ -1068,12 +1241,15 @@ void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)
 void LCD_nCS_StartByte(uint8_t Start_Byte)
 {
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
-  SPI_I2S_SendData(LCD_SPI, Start_Byte);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+
+  SPI_SendData(LCD_SPI, Start_Byte);
+
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
 }
 
+
 /**
   * @brief  Writes index to select the LCD register.
   * @param  LCD_Reg: address of the selected register.
@@ -1083,22 +1259,58 @@ void LCD_WriteRegIndex(uint8_t LCD_Reg)
 {
   /* Reset LCD control line(/CS) and Send Start-Byte */
   LCD_nCS_StartByte(START_BYTE | SET_INDEX);
+
   /* Write 16-bit Reg Index (High Byte is 0) */
-  SPI_I2S_SendData(LCD_SPI, 0x00);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  SPI_SendData(LCD_SPI, 0x00);
+
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
+  {
+  }
+
+  SPI_SendData(LCD_SPI, LCD_Reg);
+
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
+  {
+  }
+
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+  * @brief  Writes to the selected LCD ILI9320 register.
+  * @param  LCD_Reg: address of the selected register.
+  * @param  LCD_RegValue: value to write to the selected register.
+  * @retval None
+  */
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
+{
+  /* Write 16-bit Index (then Write Reg) */
+  LCD_WriteRegIndex(LCD_Reg);
+
+  /* Write 16-bit Reg */
+  /* Reset LCD control line(/CS) and Send Start-Byte */
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
+
+  SPI_SendData(LCD_SPI, LCD_RegValue >> 8);
+
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
-  SPI_I2S_SendData(LCD_SPI, LCD_Reg);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+
+  SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
+
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
+
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
 }
 
 
 /**
   * @brief  Reads the selected LCD Register.
-  * @param  None
+  * @param  LCD_Reg: address of the selected register.
   * @retval LCD Register Value.
   */
 uint16_t LCD_ReadReg(uint8_t LCD_Reg)
@@ -1117,40 +1329,47 @@ uint16_t LCD_ReadReg(uint8_t LCD_Reg)
   
   for(i = 0; i < 5; i++)
   {
-    SPI_I2S_SendData(LCD_SPI, 0xFF);
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+    SPI_SendData(LCD_SPI, 0xFF);
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
     {
     }
     /* One byte of invalid dummy data read after the start byte */
-    while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
     {    
     }
-    SPI_I2S_ReceiveData(LCD_SPI); 
+    SPI_ReceiveData(LCD_SPI); 
   }
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
+
+  SPI_SendData(LCD_SPI, 0xFF);
+
   /* Read upper byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
+
   /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
   {
   }
-  tmp = SPI_I2S_ReceiveData(LCD_SPI);
+  tmp = SPI_ReceiveData(LCD_SPI);
   
   
-  SPI_I2S_SendData(LCD_SPI, 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  SPI_SendData(LCD_SPI, 0xFF);
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
+
   /* Read lower byte */
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)
   {
   }
-  tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
+
+  tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+
   /* LCD_SPI prescaler: 2 */
   LCD_SPI->CR1 &= 0xFFC7;
+
   return tmp;
 }
 
@@ -1163,6 +1382,7 @@ uint16_t LCD_ReadReg(uint8_t LCD_Reg)
 void LCD_WriteRAM_Prepare(void)
 {
   LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */
+
   /* Reset LCD control line(/CS) and Send Start-Byte */
   LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
 }
@@ -1176,36 +1396,12 @@ void LCD_WriteRAM_Prepare(void)
 void LCD_WriteRAMWord(uint16_t RGB_Code)
 {
   LCD_WriteRAM_Prepare();
-  LCD_WriteRAM(RGB_Code);
-  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
-}
 
+  LCD_WriteRAM(RGB_Code);
 
-/**
-  * @brief  Writes to the selected LCD register.
-  * @param  LCD_Reg: address of the selected register.
-  * @param  LCD_RegValue: value to write to the selected register.
-  * @retval None
-  */
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
-{
-  /* Write 16-bit Index (then Write Reg) */
-  LCD_WriteRegIndex(LCD_Reg);
-  /* Write 16-bit Reg */
-  /* Reset LCD control line(/CS) and Send Start-Byte */
-  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
-  SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
-  SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
-  {
-  }
   LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
 }
 
-
 /**
   * @brief  Writes to the LCD RAM.
   * @param  RGB_Code: the pixel color in RGB mode (5-6-5).
@@ -1213,12 +1409,12 @@ void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
   */
 void LCD_WriteRAM(uint16_t RGB_Code)
 {
-  SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  SPI_SendData(LCD_SPI, RGB_Code >> 8);
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
-  SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
-  while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+  SPI_SendData(LCD_SPI, RGB_Code & 0xFF);
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)
   {
   }
 }
@@ -1230,7 +1426,7 @@ void LCD_WriteRAM(uint16_t RGB_Code)
   * @retval None
   */
 void LCD_PowerOn(void)
-{ 
+{
   /* Power On sequence ---------------------------------------------------------*/
   LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
   LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
@@ -1239,15 +1435,16 @@ void LCD_PowerOn(void)
   _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */
   LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
   LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
-  _delay_(5);                  /* Delay 50 ms */
+  _delay_(5);                /* Delay 50 ms */
   LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */
-  _delay_(5);                  /* delay 50 ms */
+  _delay_(5);                /* delay 50 ms */
   LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
   LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */
-  _delay_(5);                  /* delay 50 ms */
+  _delay_(5);                /* delay 50 ms */
   LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */
 }
 
+
 /**
   * @brief  Enables the Display.
   * @param  None
@@ -1257,9 +1454,9 @@ void LCD_DisplayOn(void)
 {
   /* Display On */
   LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */
- 
 }
 
+
 /**
   * @brief  Disables the Display.
   * @param  None
@@ -1271,6 +1468,7 @@ void LCD_DisplayOff(void)
   LCD_WriteReg(LCD_REG_7, 0x0);
 }
 
+
 /**
   * @brief  Configures LCD control lines in Output Push-Pull mode.
   * @param  None
@@ -1280,21 +1478,28 @@ void LCD_CtrlLinesConfig(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
 
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
-
-  /* Configure NCS in Output Push-Pull mode */
+  RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
+  
+  /* Configure NCS (PF.02) in Output Push-Pull mode */
   GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
+    
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
 }
 
+
 /**
   * @brief  Sets or reset LCD control lines.
   * @param  GPIOx: where x can be B or D to select the GPIO peripheral.
-  * @param  CtrlPins: the Control line. This parameter can be:
+  * @param  CtrlPins: the Control line.
+  *   This parameter can be:
   *     @arg LCD_NCS_PIN: Chip Select pin
+  *     @arg LCD_NWR_PIN: Read/Write Selection pin
+  *     @arg LCD_RS_PIN: Register/RAM Selection pin
   * @param  BitVal: specifies the value to be written to the selected bit.
   *   This parameter can be:
   *     @arg Bit_RESET: to clear the port pin
@@ -1318,27 +1523,38 @@ void LCD_SPIConfig(void)
   SPI_InitTypeDef    SPI_InitStructure;
   GPIO_InitTypeDef   GPIO_InitStructure;
 
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK
-                         | RCC_APB2Periph_AFIO, ENABLE);
-  GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
+  /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */
+  RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);
 
-  /* Enable SPI clock  */
-  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, ENABLE);
+  /* Enable LCD_SPI and SYSCFG clock  */
+  RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);
   
-  /* Configure SPI pins: SCK, MISO and MOSI */
+  /* Configure LCD_SPI SCK pin */
   GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
   GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
 
+  /* Configure LCD_SPI MISO pin */
   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;
   GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);
-  
+
+  /* Configure LCD_SPI MOSI pin */
   GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;
   GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+
+  /* Connect PE.13 to SPI SCK */
+  GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);
+
+  /* Connect PE.14 to SPI MISO */
+  GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);
+
+  /* Connect PE.15 to SPI MOSI */
+  GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);
   
-  SPI_I2S_DeInit(LCD_SPI);
+  SPI_DeInit(LCD_SPI);
   
   /* SPI Config */
   SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
@@ -1349,6 +1565,7 @@ void LCD_SPIConfig(void)
   SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
   SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
   SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+  SPI_InitStructure.SPI_CRCPolynomial = 7;
   SPI_Init(LCD_SPI, &SPI_InitStructure);
 
   /* SPI enable */
@@ -1379,7 +1596,7 @@ static void PutPixel(int16_t x, int16_t y)
 static void delay(__IO uint32_t nCount)
 {
   __IO uint32_t index = 0; 
-  for(index = (100000 * nCount); index != 0; index--)
+  for(index = (34000 * nCount); index != 0; index--)
   {
   }
 }
@@ -1394,14 +1611,14 @@ static void delay(__IO uint32_t nCount)
 
 /**
   * @}
-  */
-  
+  */ 
+
 /**
   * @}
   */ 
-  
+
 /**
   * @}
-  */  
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+  */ 
+    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h
index 6c7f982..9f1383a 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_lcd.h
@@ -2,23 +2,29 @@
   ******************************************************************************
   * @file    stm32l152_eval_lcd.h
   * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
+  * @version V5.0.2
+  * @date    09-March-2012
   * @brief   This file contains all the functions prototypes for the stm32l152_eval_lcd
   *          firmware driver.
   ******************************************************************************
   * @attention
   *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
   *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L152_EVAL_LCD_H
@@ -29,7 +35,7 @@
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
+#include "stm32l152_eval.h"
 #include "../Common/fonts.h"
 
 /** @addtogroup Utilities
@@ -324,19 +330,19 @@ void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);
 void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor); 
 void LCD_SetTextColor(__IO uint16_t Color);
 void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
+void LCD_ClearLine(uint16_t Line);
 void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
+void LCD_SetCursor(uint16_t Xpos, uint16_t Ypos);
+void LCD_DrawChar(uint16_t Xpos, uint16_t Ypos, const uint16_t *c);
+void LCD_DisplayChar(uint16_t Line, uint16_t Column, uint8_t Ascii);
 void LCD_SetFont(sFONT *fonts);
 sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DisplayStringLine(uint16_t Line, uint8_t *ptr);
+void LCD_SetDisplayWindow(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
 void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
+void LCD_DrawLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
+void LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
 void LCD_DrawMonoPict(const uint32_t *Pict);
 void LCD_DrawBMP(uint32_t BmpAddress);
 void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
@@ -389,4 +395,4 @@ void LCD_SPIConfig(void);
   * @}
   */   
   
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c
new file mode 100644
index 0000000..b8104f6
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.c
@@ -0,0 +1,912 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_spi_sd.c
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file provides a set of functions needed to manage the SPI SD 
+  *          Card memory mounted on STM32L152-EVAL board. 
+  *          It implements a high level communication layer for read and write 
+  *          from/to this memory. The needed STM32L hardware resources (SPI and 
+  *          GPIO) are defined in stm32l152_eval.h file, and the initialization is 
+  *          performed in SD_LowLevel_Init() function declared in stm32l152_eval.c 
+  *          file.
+  *          You can easily tailor this driver to any other development board, 
+  *          by just adapting the defines for hardware resources and 
+  *          SD_LowLevel_Init() function.
+  *
+  *          ===================================================================
+  *          Notes: 
+  *           - This driver is intended for STM32L1xx families devices only.
+  *           - This driver doesn't support SD High Capacity cards.
+  *          ===================================================================
+  *
+  *          +-------------------------------------------------------+
+  *          |                     Pin assignment                    |
+  *          +-------------------------+---------------+-------------+
+  *          |  STM32 SPI Pins         |     SD        |    Pin      |
+  *          +-------------------------+---------------+-------------+
+  *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |
+  *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |
+  *          |                         |   GND         |    3 (0 V)  |
+  *          |                         |   VDD         |    4 (3.3 V)|
+  *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |
+  *          |                         |   GND         |    6 (0 V)  |
+  *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |
+  *          +-------------------------+---------------+-------------+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval_spi_sd.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152_EVAL_SPI_SD
+  * @brief      This file includes the SD card driver of STM32L152-EVAL boards.
+  * @{
+  */ 
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Function_Prototypes
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  DeInitializes the SD/SD communication.
+  * @param  None
+  * @retval None
+  */
+void SD_DeInit(void)
+{
+  SD_LowLevel_DeInit();
+}
+
+/**
+  * @brief  Initializes the SD/SD communication.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_Init(void)
+{
+  uint32_t i = 0;
+
+  /*!< Initialize SD_SPI */
+  SD_LowLevel_Init(); 
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF, 10 times with CS high */
+  /*!< Rise CS and MOSI for 80 clocks cycles */
+  for (i = 0; i <= 9; i++)
+  {
+    /*!< Send dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+  }
+  /*------------Put SD in SPI mode--------------*/
+  /*!< SD initialized and set to SPI mode properly */
+  return (SD_GoIdleState());
+}
+
+/**
+ * @brief  Detect if SD card is correctly plugged in the memory slot.
+ * @param  None
+ * @retval Return if SD is detected or not
+ */
+uint8_t SD_Detect(void)
+{
+  __IO uint8_t status = SD_PRESENT;
+
+  /*!< Check GPIO to detect SD */
+  if (GPIO_ReadInputData(SD_DETECT_GPIO_PORT) & SD_DETECT_PIN)
+  {
+    status = SD_NOT_PRESENT;
+  }
+  return status;
+}
+
+/**
+  * @brief  Returns information about specific card.
+  * @param  cardinfo: pointer to a SD_CardInfo structure that contains all SD 
+  *         card information.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo)
+{
+  SD_Error status = SD_RESPONSE_FAILURE;
+
+  status = SD_GetCSDRegister(&(cardinfo->SD_csd));
+  status = SD_GetCIDRegister(&(cardinfo->SD_cid));
+  cardinfo->CardCapacity = (cardinfo->SD_csd.DeviceSize + 1) ;
+  cardinfo->CardCapacity *= (1 << (cardinfo->SD_csd.DeviceSizeMul + 2));
+  cardinfo->CardBlockSize = 1 << (cardinfo->SD_csd.RdBlockLen);
+  cardinfo->CardCapacity *= cardinfo->CardBlockSize;
+
+  /*!< Returns the reponse */
+  return status;
+}
+
+/**
+  * @brief  Reads a block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+  SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, ReadAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Save the received data */
+        *pBuffer = SD_ReadByte();
+       
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Reads multiple block of data from the SD.
+  * @param  pBuffer: pointer to the buffer that receives the data read from the 
+  *                  SD.
+  * @param  ReadAddr: SD's internal address to read from.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be read.
+  * @retval The SD Response:
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */
+    SD_SendCmd (SD_CMD_READ_SINGLE_BLOCK, ReadAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return  SD_RESPONSE_FAILURE;
+    }
+    /*!< Now look for the data token to signify the start of the data */
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Read the SD block data : read NumByteToRead data */
+      for (i = 0; i < BlockSize; i++)
+      {
+        /*!< Read the pointed data */
+        *pBuffer = SD_ReadByte();
+        /*!< Point to the next location where the byte read will be saved */
+        pBuffer++;
+      }
+      /*!< Set next read address*/
+      Offset += 512;
+      /*!< get CRC bytes (not really needed by us, but required by SD) */
+      SD_ReadByte();
+      SD_ReadByte();
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes a block on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write multiple block */
+  SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr, 0xFF);
+  
+  /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    /*!< Send a dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(0xFE);
+
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Writes many blocks on the SD
+  * @param  pBuffer: pointer to the buffer containing the data to be written on 
+  *                  the SD.
+  * @param  WriteAddr: address to write on.
+  * @param  BlockSize: the SD card Data block size.
+  * @param  NumberOfBlocks: number of blocks to be written.
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks)
+{
+  uint32_t i = 0, Offset = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Data transfer */
+  while (NumberOfBlocks--)
+  {
+    /*!< Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks */
+    SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, WriteAddr + Offset, 0xFF);
+    /*!< Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */
+    if (SD_GetResponse(SD_RESPONSE_NO_ERROR))
+    {
+      return SD_RESPONSE_FAILURE;
+    }
+    /*!< Send dummy byte */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Send the data token to signify the start of the data */
+    SD_WriteByte(SD_START_DATA_SINGLE_BLOCK_WRITE);
+    /*!< Write the block data to SD : write count data by block */
+    for (i = 0; i < BlockSize; i++)
+    {
+      /*!< Send the pointed byte */
+      SD_WriteByte(*pBuffer);
+      /*!< Point to the next location where the byte read will be saved */
+      pBuffer++;
+    }
+    /*!< Set next write address */
+    Offset += 512;
+    /*!< Put CRC bytes (not really needed by us, but required by SD) */
+    SD_ReadByte();
+    SD_ReadByte();
+    /*!< Read data response */
+    if (SD_GetDataResponse() == SD_DATA_OK)
+    {
+      /*!< Set response value to success */
+      rvalue = SD_RESPONSE_NO_ERROR;
+    }
+    else
+    {
+      /*!< Set response value to failure */
+      rvalue = SD_RESPONSE_FAILURE;
+    }
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  /*!< Returns the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CSD card register.
+  *         Reading the contents of the CSD register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_csd: pointer on an SCD register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CSD_Tab[16];
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  /*!< Send CMD9 (CSD register) or CMD10(CSD register) */
+  SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF);
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      for (i = 0; i < 16; i++)
+      {
+        /*!< Store CSD register value on CSD_Tab */
+        CSD_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;
+  SD_csd->SysSpecVersion = (CSD_Tab[0] & 0x3C) >> 2;
+  SD_csd->Reserved1 = CSD_Tab[0] & 0x03;
+
+  /*!< Byte 1 */
+  SD_csd->TAAC = CSD_Tab[1];
+
+  /*!< Byte 2 */
+  SD_csd->NSAC = CSD_Tab[2];
+
+  /*!< Byte 3 */
+  SD_csd->MaxBusClkFrec = CSD_Tab[3];
+
+  /*!< Byte 4 */
+  SD_csd->CardComdClasses = CSD_Tab[4] << 4;
+
+  /*!< Byte 5 */
+  SD_csd->CardComdClasses |= (CSD_Tab[5] & 0xF0) >> 4;
+  SD_csd->RdBlockLen = CSD_Tab[5] & 0x0F;
+
+  /*!< Byte 6 */
+  SD_csd->PartBlockRead = (CSD_Tab[6] & 0x80) >> 7;
+  SD_csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;
+  SD_csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;
+  SD_csd->DSRImpl = (CSD_Tab[6] & 0x10) >> 4;
+  SD_csd->Reserved2 = 0; /*!< Reserved */
+
+  SD_csd->DeviceSize = (CSD_Tab[6] & 0x03) << 10;
+
+  /*!< Byte 7 */
+  SD_csd->DeviceSize |= (CSD_Tab[7]) << 2;
+
+  /*!< Byte 8 */
+  SD_csd->DeviceSize |= (CSD_Tab[8] & 0xC0) >> 6;
+
+  SD_csd->MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;
+  SD_csd->MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);
+
+  /*!< Byte 9 */
+  SD_csd->MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;
+  SD_csd->MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;
+  SD_csd->DeviceSizeMul = (CSD_Tab[9] & 0x03) << 1;
+  /*!< Byte 10 */
+  SD_csd->DeviceSizeMul |= (CSD_Tab[10] & 0x80) >> 7;
+    
+  SD_csd->EraseGrSize = (CSD_Tab[10] & 0x40) >> 6;
+  SD_csd->EraseGrMul = (CSD_Tab[10] & 0x3F) << 1;
+
+  /*!< Byte 11 */
+  SD_csd->EraseGrMul |= (CSD_Tab[11] & 0x80) >> 7;
+  SD_csd->WrProtectGrSize = (CSD_Tab[11] & 0x7F);
+
+  /*!< Byte 12 */
+  SD_csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;
+  SD_csd->ManDeflECC = (CSD_Tab[12] & 0x60) >> 5;
+  SD_csd->WrSpeedFact = (CSD_Tab[12] & 0x1C) >> 2;
+  SD_csd->MaxWrBlockLen = (CSD_Tab[12] & 0x03) << 2;
+
+  /*!< Byte 13 */
+  SD_csd->MaxWrBlockLen |= (CSD_Tab[13] & 0xC0) >> 6;
+  SD_csd->WriteBlockPaPartial = (CSD_Tab[13] & 0x20) >> 5;
+  SD_csd->Reserved3 = 0;
+  SD_csd->ContentProtectAppli = (CSD_Tab[13] & 0x01);
+
+  /*!< Byte 14 */
+  SD_csd->FileFormatGrouop = (CSD_Tab[14] & 0x80) >> 7;
+  SD_csd->CopyFlag = (CSD_Tab[14] & 0x40) >> 6;
+  SD_csd->PermWrProtect = (CSD_Tab[14] & 0x20) >> 5;
+  SD_csd->TempWrProtect = (CSD_Tab[14] & 0x10) >> 4;
+  SD_csd->FileFormat = (CSD_Tab[14] & 0x0C) >> 2;
+  SD_csd->ECC = (CSD_Tab[14] & 0x03);
+
+  /*!< Byte 15 */
+  SD_csd->CSD_CRC = (CSD_Tab[15] & 0xFE) >> 1;
+  SD_csd->Reserved4 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Read the CID card register.
+  *         Reading the contents of the CID register in SPI mode is a simple 
+  *         read-block transaction.
+  * @param  SD_cid: pointer on an CID register structure
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid)
+{
+  uint32_t i = 0;
+  SD_Error rvalue = SD_RESPONSE_FAILURE;
+  uint8_t CID_Tab[16];
+  
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD10 (CID register) */
+  SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF);
+  
+  /*!< Wait for response in the R1 format (0x00 is no errors) */
+  if (!SD_GetResponse(SD_RESPONSE_NO_ERROR))
+  {
+    if (!SD_GetResponse(SD_START_DATA_SINGLE_BLOCK_READ))
+    {
+      /*!< Store CID register value on CID_Tab */
+      for (i = 0; i < 16; i++)
+      {
+        CID_Tab[i] = SD_ReadByte();
+      }
+    }
+    /*!< Get CRC bytes (not really needed by us, but required by SD) */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    SD_WriteByte(SD_DUMMY_BYTE);
+    /*!< Set response value to success */
+    rvalue = SD_RESPONSE_NO_ERROR;
+  }
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  /*!< Send dummy byte: 8 Clock pulses of delay */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  /*!< Byte 0 */
+  SD_cid->ManufacturerID = CID_Tab[0];
+
+  /*!< Byte 1 */
+  SD_cid->OEM_AppliID = CID_Tab[1] << 8;
+
+  /*!< Byte 2 */
+  SD_cid->OEM_AppliID |= CID_Tab[2];
+
+  /*!< Byte 3 */
+  SD_cid->ProdName1 = CID_Tab[3] << 24;
+
+  /*!< Byte 4 */
+  SD_cid->ProdName1 |= CID_Tab[4] << 16;
+
+  /*!< Byte 5 */
+  SD_cid->ProdName1 |= CID_Tab[5] << 8;
+
+  /*!< Byte 6 */
+  SD_cid->ProdName1 |= CID_Tab[6];
+
+  /*!< Byte 7 */
+  SD_cid->ProdName2 = CID_Tab[7];
+
+  /*!< Byte 8 */
+  SD_cid->ProdRev = CID_Tab[8];
+
+  /*!< Byte 9 */
+  SD_cid->ProdSN = CID_Tab[9] << 24;
+
+  /*!< Byte 10 */
+  SD_cid->ProdSN |= CID_Tab[10] << 16;
+
+  /*!< Byte 11 */
+  SD_cid->ProdSN |= CID_Tab[11] << 8;
+
+  /*!< Byte 12 */
+  SD_cid->ProdSN |= CID_Tab[12];
+
+  /*!< Byte 13 */
+  SD_cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;
+  SD_cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;
+
+  /*!< Byte 14 */
+  SD_cid->ManufactDate |= CID_Tab[14];
+
+  /*!< Byte 15 */
+  SD_cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;
+  SD_cid->Reserved2 = 1;
+
+  /*!< Return the reponse */
+  return rvalue;
+}
+
+/**
+  * @brief  Send 5 bytes command to the SD card.
+  * @param  Cmd: The user expected command to send to SD card.
+  * @param  Arg: The command argument.
+  * @param  Crc: The CRC.
+  * @retval None
+  */
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc)
+{
+  uint32_t i = 0x00;
+  
+  uint8_t Frame[6];
+  
+  Frame[0] = (Cmd | 0x40); /*!< Construct byte 1 */
+  
+  Frame[1] = (uint8_t)(Arg >> 24); /*!< Construct byte 2 */
+  
+  Frame[2] = (uint8_t)(Arg >> 16); /*!< Construct byte 3 */
+  
+  Frame[3] = (uint8_t)(Arg >> 8); /*!< Construct byte 4 */
+  
+  Frame[4] = (uint8_t)(Arg); /*!< Construct byte 5 */
+  
+  Frame[5] = (Crc); /*!< Construct CRC: byte 6 */
+  
+  for (i = 0; i < 6; i++)
+  {
+    SD_WriteByte(Frame[i]); /*!< Send the Cmd bytes */
+  }
+}
+
+/**
+  * @brief  Get SD card data response.
+  * @param  None
+  * @retval The SD status: Read data response xxx0<status>1
+  *         - status 010: Data accecpted
+  *         - status 101: Data rejected due to a crc error
+  *         - status 110: Data rejected due to a Write error.
+  *         - status 111: Data rejected due to other error.
+  */
+uint8_t SD_GetDataResponse(void)
+{
+  uint32_t i = 0;
+  uint8_t response, rvalue;
+
+  while (i <= 64)
+  {
+    /*!< Read resonse */
+    response = SD_ReadByte();
+    /*!< Mask unused bits */
+    response &= 0x1F;
+    switch (response)
+    {
+      case SD_DATA_OK:
+      {
+        rvalue = SD_DATA_OK;
+        break;
+      }
+      case SD_DATA_CRC_ERROR:
+        return SD_DATA_CRC_ERROR;
+      case SD_DATA_WRITE_ERROR:
+        return SD_DATA_WRITE_ERROR;
+      default:
+      {
+        rvalue = SD_DATA_OTHER_ERROR;
+        break;
+      }
+    }
+    /*!< Exit loop in case of data ok */
+    if (rvalue == SD_DATA_OK)
+      break;
+    /*!< Increment loop counter */
+    i++;
+  }
+
+  /*!< Wait null data */
+  while (SD_ReadByte() == 0);
+
+  /*!< Return response */
+  return response;
+}
+
+/**
+  * @brief  Returns the SD response.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GetResponse(uint8_t Response)
+{
+  uint32_t Count = 0xFFF;
+
+  /*!< Check if response is got or a timeout is happen */
+  while ((SD_ReadByte() != Response) && Count)
+  {
+    Count--;
+  }
+  if (Count == 0)
+  {
+    /*!< After time out */
+    return SD_RESPONSE_FAILURE;
+  }
+  else
+  {
+    /*!< Right response got */
+    return SD_RESPONSE_NO_ERROR;
+  }
+}
+
+/**
+  * @brief  Returns the SD status.
+  * @param  None
+  * @retval The SD status.
+  */
+uint16_t SD_GetStatus(void)
+{
+  uint16_t Status = 0;
+
+  /*!< SD chip select low */
+  SD_CS_LOW();
+
+  /*!< Send CMD13 (SD_SEND_STATUS) to get SD status */
+  SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF);
+
+  Status = SD_ReadByte();
+  Status |= (uint16_t)(SD_ReadByte() << 8);
+
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+
+  return Status;
+}
+
+/**
+  * @brief  Put SD in Idle state.
+  * @param  None
+  * @retval The SD Response: 
+  *         - SD_RESPONSE_FAILURE: Sequence failed
+  *         - SD_RESPONSE_NO_ERROR: Sequence succeed
+  */
+SD_Error SD_GoIdleState(void)
+{
+  /*!< SD chip select low */
+  SD_CS_LOW();
+  
+  /*!< Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode */
+  SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95);
+  
+  /*!< Wait for In Idle State Response (R1 Format) equal to 0x01 */
+  if (SD_GetResponse(SD_IN_IDLE_STATE))
+  {
+    /*!< No Idle State Response: return response failue */
+    return SD_RESPONSE_FAILURE;
+  }
+  /*----------Activates the card initialization process-----------*/
+  do
+  {
+    /*!< SD chip select high */
+    SD_CS_HIGH();
+    
+    /*!< Send Dummy byte 0xFF */
+    SD_WriteByte(SD_DUMMY_BYTE);
+    
+    /*!< SD chip select low */
+    SD_CS_LOW();
+    
+    /*!< Send CMD1 (Activates the card process) until response equal to 0x0 */
+    SD_SendCmd(SD_CMD_SEND_OP_COND, 0, 0xFF);
+    /*!< Wait for no error Response (R1 Format) equal to 0x00 */
+  }
+  while (SD_GetResponse(SD_RESPONSE_NO_ERROR));
+  
+  /*!< SD chip select high */
+  SD_CS_HIGH();
+  
+  /*!< Send dummy byte 0xFF */
+  SD_WriteByte(SD_DUMMY_BYTE);
+  
+  return SD_RESPONSE_NO_ERROR;
+}
+
+/**
+  * @brief  Write a byte on the SD.
+  * @param  Data: byte to send.
+  * @retval None
+  */
+uint8_t SD_WriteByte(uint8_t Data)
+{
+  /*!< Wait until the transmit buffer is empty */
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  
+  /*!< Send the byte */
+  SPI_I2S_SendData(SD_SPI, Data);
+  
+  /*!< Wait to receive a byte*/
+  while(SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  
+  /*!< Return the byte read from the SPI bus */ 
+  return (uint8_t)SPI_I2S_ReceiveData(SD_SPI);
+}
+
+/**
+  * @brief  Read a byte from the SD.
+  * @param  None
+  * @retval The received byte.
+  */
+uint8_t SD_ReadByte(void)
+{
+  uint8_t Data = 0;
+  
+  /*!< Wait until the transmit buffer is empty */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_TXE) == RESET)
+  {
+  }
+  /*!< Send the byte */
+  SPI_I2S_SendData(SD_SPI, SD_DUMMY_BYTE);
+
+  /*!< Wait until a data is received */
+  while (SPI_I2S_GetFlagStatus(SD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+  {
+  }
+  /*!< Get the received data */
+  Data = (uint8_t)SPI_I2S_ReceiveData(SD_SPI);
+
+  /*!< Return the shifted data */
+  return Data;
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.h b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.h
new file mode 100644
index 0000000..3c47702
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/Utilities/STM32_EVAL/STM32L152_EVAL/stm32l152_eval_spi_sd.h
@@ -0,0 +1,286 @@
+/**
+  ******************************************************************************
+  * @file    stm32l152_eval_spi_sd.h
+  * @author  MCD Application Team
+  * @version V5.0.2
+  * @date    09-March-2012
+  * @brief   This file contains all the functions prototypes for the stm32l152_eval_spi_sd
+  *          firmware driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L152_EVAL_SPI_SD_H
+#define __STM32L152_EVAL_SPI_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l152_eval.h"
+
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32_EVAL
+  * @{
+  */ 
+
+/** @addtogroup STM32L152_EVAL
+  * @{
+  */
+  
+/** @addtogroup STM32L152_EVAL_SPI_SD
+  * @{
+  */  
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Exported_Types
+  * @{
+  */ 
+
+typedef enum
+{
+/**
+  * @brief  SD reponses and error flags
+  */
+  SD_RESPONSE_NO_ERROR      = (0x00),
+  SD_IN_IDLE_STATE          = (0x01),
+  SD_ERASE_RESET            = (0x02),
+  SD_ILLEGAL_COMMAND        = (0x04),
+  SD_COM_CRC_ERROR          = (0x08),
+  SD_ERASE_SEQUENCE_ERROR   = (0x10),
+  SD_ADDRESS_ERROR          = (0x20),
+  SD_PARAMETER_ERROR        = (0x40),
+  SD_RESPONSE_FAILURE       = (0xFF),
+
+/**
+  * @brief  Data response error
+  */
+  SD_DATA_OK                = (0x05),
+  SD_DATA_CRC_ERROR         = (0x0B),
+  SD_DATA_WRITE_ERROR       = (0x0D),
+  SD_DATA_OTHER_ERROR       = (0xFF)
+} SD_Error;
+
+/** 
+  * @brief  Card Specific Data: CSD Register   
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version */
+  __IO uint8_t  Reserved1;            /*!< Reserved */
+  __IO uint8_t  TAAC;                 /*!< Data read access-time 1 */
+  __IO uint8_t  NSAC;                 /*!< Data read access-time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented */
+  __IO uint8_t  Reserved2;            /*!< Reserved */
+  __IO uint32_t DeviceSize;           /*!< Device Size */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed */
+  __IO uint8_t  Reserved3;            /*!< Reserded */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP) */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection */
+  __IO uint8_t  FileFormat;           /*!< File Format */
+  __IO uint8_t  ECC;                  /*!< ECC code */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC */
+  __IO uint8_t  Reserved4;            /*!< always 1*/
+} SD_CSD;
+
+/** 
+  * @brief  Card Identification Data: CID Register   
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;       /*!< ManufacturerID */
+  __IO uint16_t OEM_AppliID;          /*!< OEM/Application ID */
+  __IO uint32_t ProdName1;            /*!< Product Name part1 */
+  __IO uint8_t  ProdName2;            /*!< Product Name part2*/
+  __IO uint8_t  ProdRev;              /*!< Product Revision */
+  __IO uint32_t ProdSN;               /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;            /*!< Reserved1 */
+  __IO uint16_t ManufactDate;         /*!< Manufacturing Date */
+  __IO uint8_t  CID_CRC;              /*!< CID CRC */
+  __IO uint8_t  Reserved2;            /*!< always 1 */
+} SD_CID;
+
+/** 
+  * @brief SD Card information 
+  */
+typedef struct
+{
+  SD_CSD SD_csd;
+  SD_CID SD_cid;
+  uint32_t CardCapacity;  /*!< Card Capacity */
+  uint32_t CardBlockSize; /*!< Card Block Size */
+} SD_CardInfo;
+
+/**
+  * @}
+  */
+  
+/** @defgroup STM32L152_EVAL_SPI_SD_Exported_Constants
+  * @{
+  */ 
+    
+/**
+  * @brief  Block Size
+  */
+#define SD_BLOCK_SIZE    0x200
+
+/**
+  * @brief  Dummy byte
+  */
+#define SD_DUMMY_BYTE   0xFF
+
+/**
+  * @brief  Start Data tokens:
+  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is 
+  *         on the data/command line)  
+  */
+#define SD_START_DATA_SINGLE_BLOCK_READ    0xFE  /*!< Data token start byte, Start Single Block Read */
+#define SD_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /*!< Data token start byte, Start Multiple Block Read */
+#define SD_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /*!< Data token start byte, Start Single Block Write */
+#define SD_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /*!< Data token start byte, Start Multiple Block Write */
+#define SD_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /*!< Data toke stop byte, Stop Multiple Block Write */
+
+/**
+  * @brief  SD detection on its memory slot
+  */
+#define SD_PRESENT        ((uint8_t)0x01)
+#define SD_NOT_PRESENT    ((uint8_t)0x00)
+
+
+/**
+  * @brief  Commands: CMDxx = CMD-number | 0x40
+  */
+#define SD_CMD_GO_IDLE_STATE          0   /*!< CMD0 = 0x40 */
+#define SD_CMD_SEND_OP_COND           1   /*!< CMD1 = 0x41 */
+#define SD_CMD_SEND_CSD               9   /*!< CMD9 = 0x49 */
+#define SD_CMD_SEND_CID               10  /*!< CMD10 = 0x4A */
+#define SD_CMD_STOP_TRANSMISSION      12  /*!< CMD12 = 0x4C */
+#define SD_CMD_SEND_STATUS            13  /*!< CMD13 = 0x4D */
+#define SD_CMD_SET_BLOCKLEN           16  /*!< CMD16 = 0x50 */
+#define SD_CMD_READ_SINGLE_BLOCK      17  /*!< CMD17 = 0x51 */
+#define SD_CMD_READ_MULT_BLOCK        18  /*!< CMD18 = 0x52 */
+#define SD_CMD_SET_BLOCK_COUNT        23  /*!< CMD23 = 0x57 */
+#define SD_CMD_WRITE_SINGLE_BLOCK     24  /*!< CMD24 = 0x58 */
+#define SD_CMD_WRITE_MULT_BLOCK       25  /*!< CMD25 = 0x59 */
+#define SD_CMD_PROG_CSD               27  /*!< CMD27 = 0x5B */
+#define SD_CMD_SET_WRITE_PROT         28  /*!< CMD28 = 0x5C */
+#define SD_CMD_CLR_WRITE_PROT         29  /*!< CMD29 = 0x5D */
+#define SD_CMD_SEND_WRITE_PROT        30  /*!< CMD30 = 0x5E */
+#define SD_CMD_SD_ERASE_GRP_START     32  /*!< CMD32 = 0x60 */
+#define SD_CMD_SD_ERASE_GRP_END       33  /*!< CMD33 = 0x61 */
+#define SD_CMD_UNTAG_SECTOR           34  /*!< CMD34 = 0x62 */
+#define SD_CMD_ERASE_GRP_START        35  /*!< CMD35 = 0x63 */
+#define SD_CMD_ERASE_GRP_END          36  /*!< CMD36 = 0x64 */
+#define SD_CMD_UNTAG_ERASE_GROUP      37  /*!< CMD37 = 0x65 */
+#define SD_CMD_ERASE                  38  /*!< CMD38 = 0x66 */
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32L152_EVAL_SPI_SD_Exported_Macros
+  * @{
+  */
+/** 
+  * @brief  Select SD Card: ChipSelect pin low   
+  */  
+#define SD_CS_LOW()     GPIO_ResetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/** 
+  * @brief  Deselect SD Card: ChipSelect pin high   
+  */ 
+#define SD_CS_HIGH()    GPIO_SetBits(SD_CS_GPIO_PORT, SD_CS_PIN)
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32L152_EVAL_SPI_SD_Exported_Functions
+  * @{
+  */ 
+void SD_DeInit(void);  
+SD_Error SD_Init(void);
+uint8_t SD_Detect(void);
+SD_Error SD_GetCardInfo(SD_CardInfo *cardinfo);
+SD_Error SD_ReadBlock(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize);
+SD_Error SD_ReadMultiBlocks(uint8_t* pBuffer, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_WriteBlock(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize);
+SD_Error SD_WriteMultiBlocks(uint8_t* pBuffer, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks);
+SD_Error SD_GetCSDRegister(SD_CSD* SD_csd);
+SD_Error SD_GetCIDRegister(SD_CID* SD_cid);
+
+void SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc);
+SD_Error SD_GetResponse(uint8_t Response);
+uint8_t SD_GetDataResponse(void);
+SD_Error SD_GoIdleState(void);
+uint16_t SD_GetStatus(void);
+
+uint8_t SD_WriteByte(uint8_t byte);
+uint8_t SD_ReadByte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L152_EVAL_SPI_SD_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */    
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/CMSIS_Logo_Final.jpg b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/CMSIS_Logo_Final.jpg
index e045601..e045601 100644
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/_htmresc/CMSIS_Logo_Final.jpg
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/CMSIS_Logo_Final.jpg
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/USB-RGB-1008.jpg b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/USB-RGB-1008.jpg
new file mode 100644
index 0000000..ca6d667
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/USB-RGB-1008.jpg
diff --git a/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/ar_s.gif b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/ar_s.gif
new file mode 100644
index 0000000..f94bc11
--- /dev/null
+++ b/thirdparty/STM32_USB-FS-Device_Lib_V4.0.0/_htmresc/ar_s.gif
diff --git a/thirdparty/tinyprintf b/thirdparty/tinyprintf
new file mode 160000
+Subproject 2ee30120ec15e321566b43f83c731d060bb437f
diff --git a/tinyprintf/LICENSE.BSD-new b/tinyprintf/LICENSE.BSD-new
deleted file mode 100644
index c088c77..0000000
--- a/tinyprintf/LICENSE.BSD-new
+++ /dev/null
@@ -1,24 +0,0 @@
-Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of Kustaa Nyholm or SpareTimeLabs nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/tinyprintf/Makefile b/tinyprintf/Makefile
deleted file mode 100644
index 43adc13..0000000
--- a/tinyprintf/Makefile
+++ /dev/null
@@ -1,39 +0,0 @@
-
-CPPFLAGS+=-I.
-CFLAGS+=-Wall -W -Wextra -O3 -g
-# RUNNER:=valgrind
-
-.PHONY: all test tests compiletests runtests clean
-
-all: tests
-
-test tests: compiletests runtests
-
-runtests: test/printf test/sprintf
-	set -x ; for prg in $^ ; do $(RUNNER) $$prg || exit $$? ; done
-
-compiletests:
-	$(COMPILE.c) \
-	  -DTINYPRINTF_DEFINE_TFP_PRINTF=0 \
-	  -DTINYPRINTF_DEFINE_TFP_SPRINTF=0 \
-	  -DTINYPRINTF_OVERRIDE_LIBC=0 \
-	  -o tinyprintf_minimal.o tinyprintf.c
-	$(COMPILE.c) \
-	  -DTINYPRINTF_DEFINE_TFP_PRINTF=1 \
-	  -DTINYPRINTF_DEFINE_TFP_SPRINTF=0 \
-	  -DTINYPRINTF_OVERRIDE_LIBC=0 \
-	  -o tinyprintf_only_tfp_printf.o tinyprintf.c
-	$(COMPILE.c) \
-	  -DTINYPRINTF_DEFINE_TFP_PRINTF=0 \
-	  -DTINYPRINTF_DEFINE_TFP_SPRINTF=1 \
-	  -DTINYPRINTF_OVERRIDE_LIBC=0 \
-	  -o tinyprintf_only_tfp_sprintf.o tinyprintf.c
-
-test/printf: test/printf.o tinyprintf.o
-	$(LINK.c) -o $@ $^
-
-test/sprintf: test/sprintf.o tinyprintf.o
-	$(LINK.c) -o $@ $^
-
-clean:
-	$(RM) *.o test/*.o *~ test/*~ test/printf test/sprintf
diff --git a/tinyprintf/README b/tinyprintf/README
deleted file mode 100644
index 64f27e5..0000000
--- a/tinyprintf/README
+++ /dev/null
@@ -1,6 +0,0 @@
-tinyprintf originally from http://www.sparetimelabs.com/tinyprintf/index.html
-Copyright (C) 2004,2012  Kustaa Nyholm
-Licenses: LGPL 2.1 or later (see LICENSE.LGPL-2.1)
-      or  BSD-new           (see LICENSE.BSD-new)
-
-"You are free to use the LGPL license [...] or the BSD license"
diff --git a/tinyprintf/test/sprintf.c b/tinyprintf/test/sprintf.c
deleted file mode 100644
index 06a01ed..0000000
--- a/tinyprintf/test/sprintf.c
+++ /dev/null
@@ -1,80 +0,0 @@
-
-#define TINYPRINTF_DEFINE_TFP_PRINTF 0
-#define TINYPRINTF_DEFINE_TFP_SPRINTF 1
-#define TINYPRINTF_OVERRIDE_LIBC 0
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <assert.h>
-#include <limits.h>
-
-#include "tinyprintf.h"
-
-/* Use malloc so that valgrind can catch array overflows */
-#define TPRINTF(expr...)                                                \
-  ({ char *s1, *s2; size_t sz1, sz2;                                    \
-    /* Test format ok */                                                \
-    s1 = malloc(1024); s2 = malloc(1024);                               \
-    sz1 = snprintf(s1, 1024, expr); sz2 = tfp_snprintf(s2, 256, expr);  \
-    printf("libc_snprintf(%s) -> %d: ", #expr, (int)sz1); puts(s1);     \
-    printf(" tfp_snprintf(%s) -> %d: ", #expr, (int)sz2); puts(s2);     \
-    assert(sz1 == sz2);                                                 \
-    assert(0 == strcmp(s1, s2));                                        \
-    /* Test no array verflow */                                         \
-    free(s1); free(s2); s1 = malloc(1); s2 = malloc(1);                 \
-    assert(snprintf(s1, 1, expr) == tfp_snprintf(s2, 1, expr));         \
-    assert(strlen(s1) == 0); assert(strlen(s2) == 0);                   \
-    assert(0 == strcmp(s1, s2));                                        \
-    /* Test correct truncation */                                       \
-    free(s1); free(s2); s1 = malloc(16); s2 = malloc(16);               \
-    assert(snprintf(s1, 16, expr) == tfp_snprintf(s2, 16, expr));       \
-    assert(strlen(s1) < 16); assert(strlen(s2) < 16);                   \
-    assert(0 == strcmp(s1, s2));                                        \
-    free(s1); free(s2);                                                 \
-  })
-
-
-int main()
-{
-  printf("Fun with sprintf and %%!\n");
-
-  TPRINTF("d1=%016llx d2=%016lx d3=%02x d4=%02X 42=%03d",
-          (long long unsigned)0xd1, (long unsigned)0xd2, 0xd3, 0xd4, 42);
-  TPRINTF("d1=%04x d2=%06x d3=%08x %%100", 0xd1, 0xd2, 0xd3);
-  TPRINTF("|%-14s| |%-16s| d2=%2x |%-30s|", "str14", "str16", 0xd2,
-          "12345678901234567890123456789012345");
-  TPRINTF("|%4s|", "string4");
-  TPRINTF("|%-4s|", "string4");
-  TPRINTF("42=%3d d1=%4.4x |%4s| d2=%8.8x", 42, 0xd1, "string4", 0xd2);
-  TPRINTF("42=%3d d1=%4.4x |%-4s| d2=%8.8x", 42, 0xd1, "string4", 0xd2);
-  TPRINTF("84=%d 21=%ds |%s| |%sOK| d1=%x d2=%#x",
-          84, 21, "hello", "fine", 0xd1, 0xd2);
-
-  TPRINTF("%lld", LLONG_MIN);
-  TPRINTF("%lld", LLONG_MAX);
-  TPRINTF("%llu", ULLONG_MAX);
-  TPRINTF("%llx", LLONG_MIN);
-  TPRINTF("%llx", LLONG_MAX);
-  TPRINTF("%llx", ULLONG_MAX);
-
-  TPRINTF("d1=%4.4x", 0xd1);
-
-  {
-    char blah[256];
-    TPRINTF("a=%zd", sizeof(blah));
-    TPRINTF("a=%zu", sizeof(blah));
-    TPRINTF("a=%zi", sizeof(blah));
-    TPRINTF("a=0x%zx", sizeof(blah));
-  }
-
-  TPRINTF("Hello |%15s|.", "12345678901234");
-
-  {
-    int in_stack;
-    TPRINTF("Adddress of main: %p", main);
-    TPRINTF("Adddress of stack variable: %p", &in_stack);
-  }
-
-  return 0;
-}
diff --git a/tinyprintf/tinyprintf.c b/tinyprintf/tinyprintf.c
deleted file mode 100644
index 42d05b0..0000000
--- a/tinyprintf/tinyprintf.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
-File: tinyprintf.c
-
-Copyright (C) 2004  Kustaa Nyholm
-
-This library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Lesser General Public
-License as published by the Free Software Foundation; either
-version 2.1 of the License, or (at your option) any later version.
-
-This library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public
-License along with this library; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-*/
-
-#include "tinyprintf.h"
-
-
-/*
- * Configuration
- */
-
-/* Enable long int support */
-#define PRINTF_LONG_SUPPORT
-
-/* Enable long long int support (implies long int support) */
-//#define PRINTF_LONG_LONG_SUPPORT
-
-/* Enable %z (size_t) support */
-#define PRINTF_SIZE_T_SUPPORT
-
-/*
- * Configuration adjustments
- */
-#ifdef PRINTF_SIZE_T_SUPPORT
-#include <sys/types.h>
-#endif
-
-#ifdef PRINTF_LONG_LONG_SUPPORT
-# define PRINTF_LONG_SUPPORT
-#endif
-
-/* __SIZEOF_<type>__ defined at least by gcc */
-#ifdef __SIZEOF_POINTER__
-# define SIZEOF_POINTER __SIZEOF_POINTER__
-#endif
-#ifdef __SIZEOF_LONG_LONG__
-# define SIZEOF_LONG_LONG __SIZEOF_LONG_LONG__
-#endif
-#ifdef __SIZEOF_LONG__
-# define SIZEOF_LONG __SIZEOF_LONG__
-#endif
-#ifdef __SIZEOF_INT__
-# define SIZEOF_INT __SIZEOF_INT__
-#endif
-
-#ifdef __GNUC__
-# define _TFP_GCC_NO_INLINE_  __attribute__ ((noinline))
-#else
-# define _TFP_GCC_NO_INLINE_
-#endif
-
-/*
- * Implementation
- */
-struct param {
-    char lz:1;          /**<  Leading zeros */
-    char alt:1;         /**<  alternate form */
-    char uc:1;          /**<  Upper case (for base16 only) */
-    char align_left:1;  /**<  0 == align right (default), 1 == align left */
-    unsigned int width; /**<  field width */
-    char sign;          /**<  The sign to display (if any) */
-    unsigned int base;  /**<  number base (e.g.: 8, 10, 16) */
-    char *bf;           /**<  Buffer to output */
-};
-
-
-#ifdef PRINTF_LONG_LONG_SUPPORT
-static void _TFP_GCC_NO_INLINE_ ulli2a(
-    unsigned long long int num, struct param *p)
-{
-    int n = 0;
-    unsigned long long int d = 1;
-    char *bf = p->bf;
-    while (num / d >= p->base)
-        d *= p->base;
-    while (d != 0) {
-        int dgt = num / d;
-        num %= d;
-        d /= p->base;
-        if (n || dgt > 0 || d == 0) {
-            *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
-            ++n;
-        }
-    }
-    *bf = 0;
-}
-
-static void lli2a(long long int num, struct param *p)
-{
-    if (num < 0) {
-        num = -num;
-        p->sign = '-';
-    }
-    ulli2a(num, p);
-}
-#endif
-
-#ifdef PRINTF_LONG_SUPPORT
-static void uli2a(unsigned long int num, struct param *p)
-{
-    int n = 0;
-    unsigned long int d = 1;
-    char *bf = p->bf;
-    while (num / d >= p->base)
-        d *= p->base;
-    while (d != 0) {
-        int dgt = num / d;
-        num %= d;
-        d /= p->base;
-        if (n || dgt > 0 || d == 0) {
-            *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
-            ++n;
-        }
-    }
-    *bf = 0;
-}
-
-static void li2a(long num, struct param *p)
-{
-    if (num < 0) {
-        num = -num;
-        p->sign = '-';
-    }
-    uli2a(num, p);
-}
-#endif
-
-static void ui2a(unsigned int num, struct param *p)
-{
-    int n = 0;
-    unsigned int d = 1;
-    char *bf = p->bf;
-    while (num / d >= p->base)
-        d *= p->base;
-    while (d != 0) {
-        int dgt = num / d;
-        num %= d;
-        d /= p->base;
-        if (n || dgt > 0 || d == 0) {
-            *bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
-            ++n;
-        }
-    }
-    *bf = 0;
-}
-
-static void i2a(int num, struct param *p)
-{
-    if (num < 0) {
-        num = -num;
-        p->sign = '-';
-    }
-    ui2a(num, p);
-}
-
-static int a2d(char ch)
-{
-    if (ch >= '0' && ch <= '9')
-        return ch - '0';
-    else if (ch >= 'a' && ch <= 'f')
-        return ch - 'a' + 10;
-    else if (ch >= 'A' && ch <= 'F')
-        return ch - 'A' + 10;
-    else
-        return -1;
-}
-
-static char a2u(char ch, const char **src, int base, unsigned int *nump)
-{
-    const char *p = *src;
-    unsigned int num = 0;
-    int digit;
-    while ((digit = a2d(ch)) >= 0) {
-        if (digit > base)
-            break;
-        num = num * base + digit;
-        ch = *p++;
-    }
-    *src = p;
-    *nump = num;
-    return ch;
-}
-
-static void putchw(void *putp, putcf putf, struct param *p)
-{
-    char ch;
-    int n = p->width;
-    char *bf = p->bf;
-
-    /* Number of filling characters */
-    while (*bf++ && n > 0)
-        n--;
-    if (p->sign)
-        n--;
-    if (p->alt && p->base == 16)
-        n -= 2;
-    else if (p->alt && p->base == 8)
-        n--;
-
-    /* Fill with space to align to the right, before alternate or sign */
-    if (!p->lz && !p->align_left) {
-        while (n-- > 0)
-            putf(putp, ' ');
-    }
-
-    /* print sign */
-    if (p->sign)
-        putf(putp, p->sign);
-
-    /* Alternate */
-    if (p->alt && p->base == 16) {
-        putf(putp, '0');
-        putf(putp, (p->uc ? 'X' : 'x'));
-    } else if (p->alt && p->base == 8) {
-        putf(putp, '0');
-    }
-
-    /* Fill with zeros, after alternate or sign */
-    if (p->lz) {
-        while (n-- > 0)
-            putf(putp, '0');
-    }
-
-    /* Put actual buffer */
-    bf = p->bf;
-    while ((ch = *bf++))
-        putf(putp, ch);
-
-    /* Fill with space to align to the left, after string */
-    if (!p->lz && p->align_left) {
-        while (n-- > 0)
-            putf(putp, ' ');
-    }
-}
-
-void tfp_format(void *putp, putcf putf, const char *fmt, va_list va)
-{
-    struct param p;
-#ifdef PRINTF_LONG_SUPPORT
-    char bf[23];  /* long = 64b on some architectures */
-#else
-    char bf[12];  /* int = 32b on some architectures */
-#endif
-    char ch;
-    p.bf = bf;
-
-    while ((ch = *(fmt++))) {
-        if (ch != '%') {
-            putf(putp, ch);
-        } else {
-#ifdef PRINTF_LONG_SUPPORT
-            char lng = 0;  /* 1 for long, 2 for long long */
-#endif
-            /* Init parameter struct */
-            p.lz = 0;
-            p.alt = 0;
-            p.width = 0;
-            p.align_left = 0;
-            p.sign = 0;
-
-            /* Flags */
-            while ((ch = *(fmt++))) {
-                switch (ch) {
-                case '-':
-                    p.align_left = 1;
-                    continue;
-                case '0':
-                    p.lz = 1;
-                    continue;
-                case '#':
-                    p.alt = 1;
-                    continue;
-                default:
-                    break;
-                }
-                break;
-            }
-
-            /* Width */
-            if (ch >= '0' && ch <= '9') {
-                ch = a2u(ch, &fmt, 10, &(p.width));
-            }
-
-            /* We accept 'x.y' format but don't support it completely:
-             * we ignore the 'y' digit => this ignores 0-fill
-             * size and makes it == width (ie. 'x') */
-            if (ch == '.') {
-              p.lz = 1;  /* zero-padding */
-              /* ignore actual 0-fill size: */
-              do {
-                ch = *(fmt++);
-              } while ((ch >= '0') && (ch <= '9'));
-            }
-
-#ifdef PRINTF_SIZE_T_SUPPORT
-# ifdef PRINTF_LONG_SUPPORT
-            if (ch == 'z') {
-                ch = *(fmt++);
-                if (sizeof(size_t) == sizeof(unsigned long int))
-                    lng = 1;
-#  ifdef PRINTF_LONG_LONG_SUPPORT
-                else if (sizeof(size_t) == sizeof(unsigned long long int))
-                    lng = 2;
-#  endif
-            } else
-# endif
-#endif
-
-#ifdef PRINTF_LONG_SUPPORT
-            if (ch == 'l') {
-                ch = *(fmt++);
-                lng = 1;
-#ifdef PRINTF_LONG_LONG_SUPPORT
-                if (ch == 'l') {
-                  ch = *(fmt++);
-                  lng = 2;
-                }
-#endif
-            }
-#endif
-            switch (ch) {
-            case 0:
-                goto abort;
-            case 'u':
-                p.base = 10;
-#ifdef PRINTF_LONG_SUPPORT
-#ifdef PRINTF_LONG_LONG_SUPPORT
-                if (2 == lng)
-                    ulli2a(va_arg(va, unsigned long long int), &p);
-                else
-#endif
-                  if (1 == lng)
-                    uli2a(va_arg(va, unsigned long int), &p);
-                else
-#endif
-                    ui2a(va_arg(va, unsigned int), &p);
-                putchw(putp, putf, &p);
-                break;
-            case 'd':
-            case 'i':
-                p.base = 10;
-#ifdef PRINTF_LONG_SUPPORT
-#ifdef PRINTF_LONG_LONG_SUPPORT
-                if (2 == lng)
-                    lli2a(va_arg(va, long long int), &p);
-                else
-#endif
-                  if (1 == lng)
-                    li2a(va_arg(va, long int), &p);
-                else
-#endif
-                    i2a(va_arg(va, int), &p);
-                putchw(putp, putf, &p);
-                break;
-#ifdef SIZEOF_POINTER
-            case 'p':
-                p.alt = 1;
-# if defined(SIZEOF_INT) && SIZEOF_POINTER <= SIZEOF_INT
-                lng = 0;
-# elif defined(SIZEOF_LONG) && SIZEOF_POINTER <= SIZEOF_LONG
-                lng = 1;
-# elif defined(SIZEOF_LONG_LONG) && SIZEOF_POINTER <= SIZEOF_LONG_LONG
-                lng = 2;
-# endif
-#endif
-            case 'x':
-            case 'X':
-                p.base = 16;
-                p.uc = (ch == 'X')?1:0;
-#ifdef PRINTF_LONG_SUPPORT
-#ifdef PRINTF_LONG_LONG_SUPPORT
-                if (2 == lng)
-                    ulli2a(va_arg(va, unsigned long long int), &p);
-                else
-#endif
-                  if (1 == lng)
-                    uli2a(va_arg(va, unsigned long int), &p);
-                else
-#endif
-                    ui2a(va_arg(va, unsigned int), &p);
-                putchw(putp, putf, &p);
-                break;
-            case 'o':
-                p.base = 8;
-                ui2a(va_arg(va, unsigned int), &p);
-                putchw(putp, putf, &p);
-                break;
-            case 'c':
-                putf(putp, (char)(va_arg(va, int)));
-                break;
-            case 's':
-                p.bf = va_arg(va, char *);
-                putchw(putp, putf, &p);
-                p.bf = bf;
-                break;
-            case '%':
-                putf(putp, ch);
-            default:
-                break;
-            }
-        }
-    }
- abort:;
-}
-
-#if TINYPRINTF_DEFINE_TFP_PRINTF
-static putcf stdout_putf;
-static void *stdout_putp;
-
-void init_printf(void *putp, putcf putf)
-{
-    stdout_putf = putf;
-    stdout_putp = putp;
-}
-
-void tfp_printf(const char *fmt, ...)
-{
-    va_list va;
-    va_start(va, fmt);
-    tfp_format(stdout_putp, stdout_putf, fmt, va);
-    va_end(va);
-}
-#endif
-
-#if TINYPRINTF_DEFINE_TFP_SPRINTF
-struct _vsnprintf_putcf_data
-{
-  size_t dest_capacity;
-  char *dest;
-  size_t num_chars;
-};
-
-static void _vsnprintf_putcf(void *p, char c)
-{
-  struct _vsnprintf_putcf_data *data = (struct _vsnprintf_putcf_data*)p;
-  if (data->num_chars < data->dest_capacity)
-    data->dest[data->num_chars] = c;
-  data->num_chars ++;
-}
-
-int tfp_vsnprintf(char *str, size_t size, const char *format, va_list ap)
-{
-  struct _vsnprintf_putcf_data data;
-
-  if (size < 1)
-    return 0;
-
-  data.dest = str;
-  data.dest_capacity = size-1;
-  data.num_chars = 0;
-  tfp_format(&data, _vsnprintf_putcf, format, ap);
-
-  if (data.num_chars < data.dest_capacity)
-    data.dest[data.num_chars] = '\0';
-  else
-    data.dest[data.dest_capacity] = '\0';
-
-  return data.num_chars;
-}
-
-int tfp_snprintf(char *str, size_t size, const char *format, ...)
-{
-  va_list ap;
-  int retval;
-
-  va_start(ap, format);
-  retval = tfp_vsnprintf(str, size, format, ap);
-  va_end(ap);
-  return retval;
-}
-
-struct _vsprintf_putcf_data
-{
-  char *dest;
-  size_t num_chars;
-};
-
-static void _vsprintf_putcf(void *p, char c)
-{
-  struct _vsprintf_putcf_data *data = (struct _vsprintf_putcf_data*)p;
-  data->dest[data->num_chars++] = c;
-}
-
-int tfp_vsprintf(char *str, const char *format, va_list ap)
-{
-  struct _vsprintf_putcf_data data;
-  data.dest = str;
-  data.num_chars = 0;
-  tfp_format(&data, _vsprintf_putcf, format, ap);
-  data.dest[data.num_chars] = '\0';
-  return data.num_chars;
-}
-
-int tfp_sprintf(char *str, const char *format, ...)
-{
-  va_list ap;
-  int retval;
-
-  va_start(ap, format);
-  retval = tfp_vsprintf(str, format, ap);
-  va_end(ap);
-  return retval;
-}
-#endif
diff --git a/tinyprintf/tinyprintf.h b/tinyprintf/tinyprintf.h
deleted file mode 100644
index 7ba9595..0000000
--- a/tinyprintf/tinyprintf.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
-File: tinyprintf.h
-
-Copyright (C) 2004  Kustaa Nyholm
-
-This library is free software; you can redistribute it and/or
-modify it under the terms of the GNU Lesser General Public
-License as published by the Free Software Foundation; either
-version 2.1 of the License, or (at your option) any later version.
-
-This library is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public
-License along with this library; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-This library is really just two files: 'tinyprintf.h' and 'tinyprintf.c'.
-
-They provide a simple and small (+400 loc) printf functionality to
-be used in embedded systems.
-
-I've found them so useful in debugging that I do not bother with a
-debugger at all.
-
-They are distributed in source form, so to use them, just compile them
-into your project.
-
-Two printf variants are provided: printf and the 'sprintf' family of
-functions ('snprintf', 'sprintf', 'vsnprintf', 'vsprintf').
-
-The formats supported by this implementation are:
-'c' 'd' 'i' 'o' 'p' 'u' 's' 'x' 'X'.
-
-Zero padding and field width are also supported.
-
-If the library is compiled with 'PRINTF_SUPPORT_LONG' defined, then
-the long specifier is also supported. Note that this will pull in some
-long math routines (pun intended!) and thus make your executable
-noticeably longer. Likewise with 'PRINTF_LONG_LONG_SUPPORT' for the
-long long specifier, and with 'PRINTF_SIZE_T_SUPPORT' for the size_t
-specifier.
-
-The memory footprint of course depends on the target CPU, compiler and
-compiler options, but a rough guesstimate (based on a H8S target) is about
-1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space.
-Not too bad. Your mileage may vary. By hacking the source code you can
-get rid of some hundred bytes, I'm sure, but personally I feel the balance of
-functionality and flexibility versus  code size is close to optimal for
-many embedded systems.
-
-To use the printf, you need to supply your own character output function,
-something like :
-
-void putc ( void* p, char c)
-{
-    while (!SERIAL_PORT_EMPTY) ;
-    SERIAL_PORT_TX_REGISTER = c;
-}
-
-Before you can call printf, you need to initialize it to use your
-character output function with something like:
-
-init_printf(NULL,putc);
-
-Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc',
-the NULL (or any pointer) you pass into the 'init_printf' will eventually be
-passed to your 'putc' routine. This allows you to pass some storage space (or
-anything really) to the character output function, if necessary.
-This is not often needed but it was implemented like that because it made
-implementing the sprintf function so neat (look at the source code).
-
-The code is re-entrant, except for the 'init_printf' function, so it is safe
-to call it from interrupts too, although this may result in mixed output.
-If you rely on re-entrancy, take care that your 'putc' function is re-entrant!
-
-The printf and sprintf functions are actually macros that translate to
-'tfp_printf' and 'tfp_sprintf' when 'TINYPRINTF_OVERRIDE_LIBC' is set
-(default). Setting it to 0 makes it possible to use them along with
-'stdio.h' printf's in a single source file. When
-'TINYPRINTF_OVERRIDE_LIBC' is set, please note that printf/sprintf are
-not function-like macros, so if you have variables or struct members
-with these names, things will explode in your face.  Without variadic
-macros this is the best we can do to wrap these function. If it is a
-problem, just give up the macros and use the functions directly, or
-rename them.
-
-It is also possible to avoid defining tfp_printf and/or tfp_sprintf by
-clearing 'TINYPRINTF_DEFINE_TFP_PRINTF' and/or
-'TINYPRINTF_DEFINE_TFP_SPRINTF' to 0. This allows for example to
-export only tfp_format, which is at the core of all the other
-functions.
-
-For further details see source code.
-
-regs Kusti, 23.10.2004
-*/
-
-#ifndef __TFP_PRINTF__
-#define __TFP_PRINTF__
-
-#include <stdarg.h>
-
-/* Global configuration */
-
-/* Set this to 0 if you do not want to provide tfp_printf */
-#ifndef TINYPRINTF_DEFINE_TFP_PRINTF
-# define TINYPRINTF_DEFINE_TFP_PRINTF 1
-#endif
-
-/* Set this to 0 if you do not want to provide
-   tfp_sprintf/snprintf/vsprintf/vsnprintf */
-#ifndef TINYPRINTF_DEFINE_TFP_SPRINTF
-# define TINYPRINTF_DEFINE_TFP_SPRINTF 1
-#endif
-
-/* Set this to 0 if you do not want tfp_printf and
-   tfp_{vsn,sn,vs,s}printf to be also available as
-   printf/{vsn,sn,vs,s}printf */
-#ifndef TINYPRINTF_OVERRIDE_LIBC
-# define TINYPRINTF_OVERRIDE_LIBC 1
-#endif
-
-/* Optional external types dependencies */
-
-#if TINYPRINTF_DEFINE_TFP_SPRINTF
-# include <sys/types.h>  /* size_t */
-#endif
-
-/* Declarations */
-
-#ifdef __GNUC__
-# define _TFP_SPECIFY_PRINTF_FMT(fmt_idx,arg1_idx) \
-    __attribute__((format (printf, fmt_idx, arg1_idx)))
-#else
-# define _TFP_SPECIFY_PRINTF_FMT(fmt_idx,arg1_idx)
-#endif
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-typedef void (*putcf) (void *, char);
-
-/*
-   'tfp_format' really is the central function for all tinyprintf. For
-   each output character after formatting, the 'putf' callback is
-   called with 2 args:
-     - an arbitrary void* 'putp' param defined by the user and
-       passed unmodified from 'tfp_format',
-     - the character.
-   The 'tfp_printf' and 'tfp_sprintf' functions simply define their own
-   callback and pass to it the right 'putp' it is expecting.
-*/
-void tfp_format(void *putp, putcf putf, const char *fmt, va_list va);
-
-#if TINYPRINTF_DEFINE_TFP_SPRINTF
-int tfp_vsnprintf(char *str, size_t size, const char *fmt, va_list ap);
-int tfp_snprintf(char *str, size_t size, const char *fmt, ...) \
-     _TFP_SPECIFY_PRINTF_FMT(3, 4);
-int tfp_vsprintf(char *str, const char *fmt, va_list ap);
-int tfp_sprintf(char *str, const char *fmt, ...) \
-    _TFP_SPECIFY_PRINTF_FMT(2, 3);
-# if TINYPRINTF_OVERRIDE_LIBC
-#  define vsnprintf tfp_vsnprintf
-#  define snprintf tfp_snprintf
-#  define vsprintf tfp_vsprintf
-#  define sprintf tfp_sprintf
-# endif
-#endif
-
-#if TINYPRINTF_DEFINE_TFP_PRINTF
-void init_printf(void *putp, putcf putf);
-void tfp_printf(const char *fmt, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2);
-# if TINYPRINTF_OVERRIDE_LIBC
-#  define printf tfp_printf
-# endif
-#endif
-
-#ifdef  __cplusplus
-}
-#endif
-
-#endif
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm
deleted file mode 100644
index 5a17f1a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CMSIS_changes.htm
+++ /dev/null
@@ -1,320 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Changes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
------------------------------------------------------------*/
-body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: 
-               Verdana, Arial, 'Sans Serif' }
-a:link       { color: #0000FF; text-decoration: underline }
-a:visited    { color: #0000FF; text-decoration: underline }
-a:active     { color: #FF0000; text-decoration: underline }
-a:hover      { color: #FF0000; text-decoration: underline }
-h1           { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; 
-               text-align: Center; margin-right: 3 }
-h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; 
-               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; 
-               padding: 6 }
-h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: 
-               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; 
-               margin-left: 24; margin-right: 24 }
-ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
-ol           { margin-top: 6pt; margin-bottom: 0 }
-li           { clear: both; margin-bottom: 6pt }
-table        { font-size: 100%; border-width: 0; padding: 0 }
-th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: 
-               bottom; padding-right: 6pt }
-tr           { text-align: left; vertical-align: top }
-td           { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT       { font-size: 8pt; color: #808080 }
-.TinyT       { font-size: 8pt; text-align: Center }
-code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; 
-               line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------
-Notes
------------------------------------------------------------*/
-p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------
-Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand      { text-decoration: none; margin-bottom: 3pt }
-img.expand   { border-style: none; border-width: medium }
-div.expand   { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
-Where List Tags
------------------------------------------------------------*/
-p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh     { width: 100% }
-td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 
-               6pt }
-td.whDesc    { padding-bottom: 6pt }
-/*-----------------------------------------------------------
-Keil Table Tags
------------------------------------------------------------*/
-table.kt     { border: 1pt solid #000000 }
-th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; 
-               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
-tr.kt        {  }
-td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; 
-               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; 
-               padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>Changes to CMSIS version V1.20</h1>
-
-<hr>
-
-<h2>1. Removed CMSIS Middelware packages</h2>
-<p>
-  CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-</p>
-
-<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
-<p>
-  The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
-  because the variable holds the clock value at which the core is running.
-</p>
-
-<h2>3. Changed startup concept</h2>
-<p>
-  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 
-  from main) has the weakness that it does not work for controllers which need a already 
-  configuerd clock system to configure the external memory controller.
-</p>
-
-<h3>Changed startup concept</h3>
-<ul>
-  <li>
-    SystemInit() is called from startup file before <strong>premain</strong>.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> configures the clock system and also configures
-    an existing external memory controller.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> must not use global variables.
-  </li>
-  <li>
-    <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
-  </li>
-  <li>
-    Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
-   <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
-   and must be called whenever the core clock is changed.<br>
-   <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
-   the current core clock.
-  </li>
-</ul>
-      
-
-<h2>4. Advanced Debug Functions</h2>
-<p>
-  ITM communication channel is only capable for OUT direction. To allow also communication for
-  IN direction a simple concept is provided.
-</p>
-<ul>
-  <li>
-    Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
-  </li>
-  <li>
-    Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
-  </li>
-  <li>
-    Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
-  </li>
-</ul>
-
-<p>
-  For detailed explanation see file <strong>CMSIS debug support.htm</strong>. 
-</p>
-
-
-<h2>5. Core Register Bit Definitions</h2>
-<p>
-  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
-  defines correspond with the Cortex-M Technical Reference Manual.  
-</p>
-<p>
-  e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
-
-<h2>7. DoxyGen Tags</h2>
-<p>
-  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
-  using DoxyGen.
-</p>
-
-<h2>8. Folder Structure</h2>
-<p>
-  The folder structure is changed to differentiate the single support packages.
-</p>
-
-  <ul>
-    <li>CM0</li>
-    <li>CM3
-       <ul>
-         <li>CoreSupport</li>
-         <li>DeviceSupport</li>
-           <ul>
-             <li>Vendor 
-               <ul>
-                 <li>Device
-                   <ul>
-                      <li>Startup
-                        <ul>
-                          <li>Toolchain</li>
-                          <li>Toolchain</li>
-                          <li>...</li>
-                        </ul>
-                      </li>
-                   </ul>
-                 </li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Vendor</li>
-             <li>...</li>
-           </ul>
-         </li>
-         <li>Example
-           <ul>
-             <li>Toolchain 
-               <ul>
-                 <li>Device</li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Toolchain</li>
-             <li>...</li>
-           </ul>
-         </li>
-       </ul>
-    </li>
-     
-    <li>Documentation</li>
-  </ul>
-
-<h2>9. Open Points</h2>
-<p>
-  Following points need to be clarified and solved:
-</p>
-<ul>
-  <li>
-    <p>
-      Equivalent C and Assembler startup files.
-    </p>
-    <p>
-      Is there a need for having C startup files although assembler startup files are
-      very efficient and do not need to be changed?
-    <p/>
-  </li>
-  <li>
-    <p>
-      Placing of HEAP in external RAM.
-    </p>
-    <p>
-      It must be possible to place HEAP in external RAM if the device supports an 
-      external memory controller.
-    </p>
-  </li>
-  <li>
-    <p>
-      Placing of STACK /HEAP.
-    </p>
-    <p>
-      STACK should always be placed at the end of internal RAM.
-    </p>
-    <p>
-      If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-    </p>
-  </li>
-  <li>
-    <p>
-      Removing core_cm3.c and core_cm0.c.
-    </p>
-    <p>
-      On a long term the functions in core_cm3.c and core_cm0.c must be replaced with 
-      appropriate compiler intrinsics.
-    </p>
-  </li>
-</ul>
-
-
-<h2>10. Limitations</h2>
-<p>
-  The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
-  No <strong>C startup files</strong> for ARM toolchain are provided. 
- </li>
- <li>
-  No <strong>C startup files</strong> for GNU toolchain are provided. 
- </li>
- <li>
-  No <strong>C startup files</strong> for IAR toolchain are provided. 
- </li>
- <li>
-  No <strong>Tasking</strong> projects are provided yet. 
- </li>
-</ul>
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt
deleted file mode 100644
index 2a57195..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/ADC/ExtLinesTrigger/readme.txt
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
-  @page ADC_ExtLinesTrigger ADC external lines trigger example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    ADC/ExtLinesTrigger/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the ADC external lines trigger example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example describes how to trigger ADC regular and injected groups channels 
-conversion using two external line events. Discontinuous mode is enabled for regular
-group channel conversion and configured to convert one regular channel on each 
-external trigger.
-
-ADC1 is configured to start regular group channel conversion on EXTI11 event.
-On detection of the first rising edge on PE.11 pin (PF.11 pin for High-Density Value line),
-the conversion of the first regular channel (ADC channel4) is done and its converted 
-value is transferred by DMA to ADC_RegularConvertedValueTab table. On the following edge 
-detection, the second regular channel (ADC channel14) is automatically converted and 
-its converted value is stored by DMA in the same table. The number of transmitted data 
-by DMA, in this example is limited to 64 data.
-
-The procedure is repeated for both regular channels on each EXTI11 event.
-ADC1 is configured to start injected group channel conversion on EXTI15 event.
-On detection of the first rising edge on PE.15 pin all selected injected channels, which
-are two in this example (ADC channel11 and channel12), are converted and an interrupt 
-is generated on JEOC flag rising at the end of all injected channels conversion. 
-Both injected channels converted results are stored in ADC_InjectedConvertedValueTab 
-table inside the interrupt routine.
-The procedure is repeated for injected channels on each EXTI15 event.
-The ADC1 clock is set to 12 MHz on Value line devices and to 14MHz on other 
-devices.
-
-@par Directory contents 
-
-  - ADC/ExtLinesTrigger/stm32f10x_conf.h     Library Configuration file
-  - ADC/ExtLinesTrigger/stm32f10x_it.c       Interrupt handlers
-  - ADC/ExtLinesTrigger/stm32f10x_it.h       Interrupt handlers header file
-  - ADC/ExtLinesTrigger/system_stm32f10x.c   STM32F10x system source file  
-  - ADC/ExtLinesTrigger/main.c               Main program
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, Medium-Density Value line, Low-Density and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100B-EVAL (Medium-Density
-    Value line), STM3210C-EVAL (Connectivity line), STM3210E-EVAL (High-Density and
-    XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can be easily
-    tailored to any other supported device and development board.
-
-  - STM32100B-EVAL Set-up
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV2), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-    @note Make shure that jumper JP3 is open.
-    
-  - STM32100E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PF.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210C-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210E-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).
-
-  - STM3210B-EVAL Set-up 
-    - Connect a known voltage, between 0-3.3V, to ADC Channel14 mapped on pin 
-      PC.04 (potentiometer RV1), ADC Channel4 mapped on pin PA.04, ADC Channel11 
-      mapped on pin PC.01 and ADC Channel12 mapped on pin PC.02.
-    - Connect a push-button to pin PE.11 (EXTI Line11) and another push-button 
-      to pin PE.15 (EXTI Line15).              
-   
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.  
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt
deleted file mode 100644
index 49d3c67..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/BKP/Tamper/readme.txt
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  @page BKP_Tamper BKP Tamper example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    BKP/Tamper/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the BKP Tamper example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example shows how to write/read data to/from Backup data registers and 
-demonstrates the Tamper detection feature.
-
-The associated firmware performs the following:
-
-1. It configures the ANTI_TAMP pin to be active low, and enables the Tamper interrupt.
-
-2. It writes the data to all Backup data registers, then check whether the data were
-correctly written. If yes, LED1 turns on, otherwise LED2 turns on.
-
-3. On applying a low level on the ANTI_TAMP pin (PC.13), the Backup data registers
-are reset and the Tamper interrupt is generated. The corresponding ISR then checks
-whether the Backup data registers are cleared. If yes, LED3 on, otherwise LED4
-turns on.
-
-
-@par Directory contents 
-
-  - BKP/Tamper/stm32f10x_conf.h    Library Configuration file
-  - BKP/Tamper/stm32f10x_it.h      Interrupt handlers header file
-  - BKP/Tamper/stm32f10x_it.c      Interrupt handlers
-  - BKP/Tamper/main.h              Main header file
-  - BKP/Tamper/main.c              Main program
-  - BKP/Tamper/system_stm32f10x.c  STM32F10x system source file
-
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    High-Density Value line, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL 
-    (Connectivity line), STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL 
-    (Medium-Density) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins  
-    - Use the Tamper push-button connected to pin PC.13 (set jumper JP1 in position 2-3). 
-      PC13 is already connected to VDD on the eval board.
-    
-  - STM3210E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.   
-
-  - STM3210B-EVAL Set-up  
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.
-	  
-  - STM32100E-EVAL Set-up 
-    - Use LD1, LD2, LD3 and LD4 leds connected respectively to PF.06, PF0.7, 
-      PF.08 and PF.09 pins
-    - Use the Tamper push-button connected to pin PC.13. PC13 is already 
-      connected to VDD on the eval board.   
-         
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-   
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
deleted file mode 100644
index 6651d04..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/LoopBack/main.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/LoopBack/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_LoopBack
-  * @{
-  */ 
-
-
-
-/* Private define ------------------------------------------------------------*/
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/   /* Please check that you device is 
-                                Connectivity line when using CAN2 */
-
-#ifdef  __CAN1_USED__
-  #define CANx CAN1
-#else /*__CAN2_USED__*/
-  #define CANx CAN2
-#endif  /* __CAN1_USED__ */
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t ret = 0; /* for return of the interrupt handling */
-volatile TestStatus TestRx;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-TestStatus CAN_Polling(void);
-TestStatus CAN_Interrupt(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-
-
-#ifdef  __CAN1_USED__
-  /* CANx Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  /* CAN1 & 2  Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-
-  /* NVIC Configuration */
-  NVIC_Configuration();
-  
-  /* Configures LED 1..4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  
-  /* Turns selected LED Off */  
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
-  
-  /* CAN transmit at 125Kb/s and receive by polling in loopback mode */
-  TestRx = CAN_Polling();
-
-  if (TestRx == FAILED)
-  {
-    /* Turn on led LD3 */
-    STM_EVAL_LEDOn(LED3);
-  }
-  else
-  {
-    /* Turn on led LD1 */
-    STM_EVAL_LEDOn(LED1);
-  }
-
-  /* CAN transmit at 500Kb/s and receive by interrupt in loopback mode */
-  TestRx = CAN_Interrupt();
-
-  if (TestRx == FAILED)
-  {
-    /* Turn on led LD4 */
-    STM_EVAL_LEDOn(LED4);
-  }
-  else
-  {
-    /* Turn on led LD2 */
-    STM_EVAL_LEDOn(LED2);
-  }
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the CAN, transmit and receive by polling
-  * @param  None
-  * @retval PASSED if the reception is well done, FAILED in other case
-  */
-TestStatus CAN_Polling(void)
-{
-  CAN_InitTypeDef        CAN_InitStructure;
-  CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-  CanTxMsg TxMessage;
-  CanRxMsg RxMessage;
-  uint32_t i = 0;
-  uint8_t TransmitMailbox = 0;
-
-  /* CAN register init */
-  CAN_DeInit(CANx);
-
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM=DISABLE;
-  CAN_InitStructure.CAN_ABOM=DISABLE;
-  CAN_InitStructure.CAN_AWUM=DISABLE;
-  CAN_InitStructure.CAN_NART=DISABLE;
-  CAN_InitStructure.CAN_RFLM=DISABLE;
-  CAN_InitStructure.CAN_TXFP=DISABLE;
-  CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
-  
-  /* Baudrate = 125kbps*/
-  CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
-  CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
-  CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
-  CAN_InitStructure.CAN_Prescaler=48;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber=0;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber=14;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;  
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment=0;
-
-
-  CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-
-  /* transmit */
-  TxMessage.StdId=0x11;
-  TxMessage.RTR=CAN_RTR_DATA;
-  TxMessage.IDE=CAN_ID_STD;
-  TxMessage.DLC=2;
-  TxMessage.Data[0]=0xCA;
-  TxMessage.Data[1]=0xFE;
-
-  TransmitMailbox=CAN_Transmit(CANx, &TxMessage);
-  i = 0;
-  while((CAN_TransmitStatus(CANx, TransmitMailbox) != CANTXOK) && (i != 0xFFFF))
-  {
-    i++;
-  }
-
-  i = 0;
-  while((CAN_MessagePending(CANx, CAN_FIFO0) < 1) && (i != 0xFFFF))
-  {
-    i++;
-  }
-
-  /* receive */
-  RxMessage.StdId=0x00;
-  RxMessage.IDE=CAN_ID_STD;
-  RxMessage.DLC=0;
-  RxMessage.Data[0]=0x00;
-  RxMessage.Data[1]=0x00;
-  CAN_Receive(CANx, CAN_FIFO0, &RxMessage);
-
-  if (RxMessage.StdId!=0x11)
-  {
-    return FAILED;  
-  }
-
-  if (RxMessage.IDE!=CAN_ID_STD)
-  {
-    return FAILED;
-  }
-
-  if (RxMessage.DLC!=2)
-  {
-    return FAILED;  
-  }
-
-  if ((RxMessage.Data[0]<<8|RxMessage.Data[1])!=0xCAFE)
-  {
-    return FAILED;
-  }
-  
-  return PASSED; /* Test Passed */
-}
-
-/**
-  * @brief  Configures the CAN, transmit and receive using interrupt.
-  * @param  None
-  * @retval PASSED if the reception is well done, FAILED in other case
-  */
-TestStatus CAN_Interrupt(void)
-{
-  CAN_InitTypeDef        CAN_InitStructure;
-  CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-  CanTxMsg TxMessage;
-  uint32_t i = 0;
-
-  /* CAN register init */
-  CAN_DeInit(CANx);
-
-
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM=DISABLE;
-  CAN_InitStructure.CAN_ABOM=DISABLE;
-  CAN_InitStructure.CAN_AWUM=DISABLE;
-  CAN_InitStructure.CAN_NART=DISABLE;
-  CAN_InitStructure.CAN_RFLM=DISABLE;
-  CAN_InitStructure.CAN_TXFP=DISABLE;
-  CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
-  CAN_InitStructure.CAN_SJW=CAN_SJW_1tq;
-  
-  /* Baudrate = 500 Kbps */
-  CAN_InitStructure.CAN_BS1=CAN_BS1_2tq;
-  CAN_InitStructure.CAN_BS2=CAN_BS2_3tq;
-  CAN_InitStructure.CAN_Prescaler=12;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber=1;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber=15;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
-  CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-
-  /* CAN FIFO0 message pending interrupt enable */ 
-  CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
-
-  /* transmit 1 message */
-  TxMessage.StdId=0;
-  TxMessage.ExtId=0x1234;
-  TxMessage.IDE=CAN_ID_EXT;
-  TxMessage.RTR=CAN_RTR_DATA;
-  TxMessage.DLC=2;
-  TxMessage.Data[0]=0xDE;
-  TxMessage.Data[1]=0xCA;
-  CAN_Transmit(CANx, &TxMessage);
-
-  /* initialize the value that will be returned */
-  ret = 0xFF;
-       
-  /* receive message with interrupt handling */
-  i=0;
-  while((ret == 0xFF) && (i < 0xFFF))
-  {
-    i++;
-  }
-  
-  if (i == 0xFFF)
-  {
-    ret=0;  
-  }
-
-  /* disable interrupt handling */
-  CAN_ITConfig(CANx, CAN_IT_FMP0, DISABLE);
-
-  return (TestStatus)ret;
-}
-
-/**
-  * @brief  Configures the NVIC and Vector Table base address.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Enable CANx RX0 interrupt IRQ channel */
-#ifndef STM32F10X_CL
-
-#ifdef  __CAN1_USED__
-  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  /* CAN2 is not implemented in the device */
-   #error "CAN2 is implemented only in Connectivity line devices"
-  
-#endif /*__CAN1_USED__*/
-#else
-#ifdef  __CAN1_USED__ 
-  NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
-#endif /*__CAN1_USED__*/
-
-#endif /* STM32F10X_CL*/
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
deleted file mode 100644
index fca0acd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CAN/Networking/main.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CAN/Networking/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CAN_Networking
-  * @{
-  */ 
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define __CAN1_USED__
-/* #define __CAN2_USED__*/
-
-#ifdef  __CAN1_USED__
-  #define CANx                       CAN1
-  #define GPIO_CAN                   GPIO_CAN1
-  #define GPIO_Remapping_CAN         GPIO_Remapping_CAN1
-  #define GPIO_CAN                   GPIO_CAN1
-  #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN1_RX
-  #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN1_TX
-#else /*__CAN2_USED__*/
-  #define CANx                       CAN2
-  #define GPIO_CAN                   GPIO_CAN2
-  #define GPIO_Remapping_CAN             GPIO_Remap_CAN2
-  #define GPIO_CAN                   GPIO_CAN2
-  #define GPIO_Pin_CAN_RX            GPIO_Pin_CAN2_RX
-  #define GPIO_Pin_CAN_TX            GPIO_Pin_CAN2_TX
-#endif  /* __CAN1_USED__ */
-
-#define KEY_PRESSED     0x01
-#define KEY_NOT_PRESSED 0x00
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-CAN_InitTypeDef        CAN_InitStructure;
-CAN_FilterInitTypeDef  CAN_FilterInitStructure;
-CanTxMsg TxMessage;
-uint8_t KeyNumber = 0x0;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Config(void);
-void CAN_Config(void);
-void LED_Display(uint8_t Ledstatus);
-void Init_RxMes(CanRxMsg *RxMessage);
-void Delay(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* NVIC configuration */
-  NVIC_Config();
-
-  /* Configures LED 1..4 */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);
-  
-  /* Configure Push button key */
-  STM_EVAL_PBInit(BUTTON_KEY, BUTTON_MODE_GPIO); 
-   
-  /* CAN configuration */
-  CAN_Config();
-  
-  CAN_ITConfig(CANx, CAN_IT_FMP0, ENABLE);
-
-  /* turn off all leds*/
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
- 
-  /* Infinite loop */
-  while(1)
-  {
-    while(STM_EVAL_PBGetState(BUTTON_KEY) == KEY_PRESSED)
-    {
-      if(KeyNumber == 0x4) 
-      {
-        KeyNumber = 0x00;
-      }
-      else
-      {
-        LED_Display(++KeyNumber);
-        TxMessage.Data[0] = KeyNumber;
-        CAN_Transmit(CANx, &TxMessage);
-        Delay();
-        
-        while(STM_EVAL_PBGetState(BUTTON_KEY) != KEY_NOT_PRESSED)
-        {
-        }
-      }
-    }
-  }
-}
-
-/**
-  * @brief  Configures the CAN.
-  * @param  None
-  * @retval None
-  */
-void CAN_Config(void)
-{
-  GPIO_InitTypeDef  GPIO_InitStructure;
-  
-  /* GPIO clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
-#ifdef  __CAN1_USED__
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN1, ENABLE);
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIO_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-  /* Configure CAN pin: RX */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_RX;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
-  
-  /* Configure CAN pin: TX */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_CAN_TX;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIO_CAN, &GPIO_InitStructure);
-  
-  GPIO_PinRemapConfig(GPIO_Remapping_CAN , ENABLE);
-  
-  /* CANx Periph clock enable */
-#ifdef  __CAN1_USED__
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-#else /*__CAN2_USED__*/
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE);
-#endif  /* __CAN1_USED__ */
-  
-  
-  /* CAN register init */
-  CAN_DeInit(CANx);
-  CAN_StructInit(&CAN_InitStructure);
-
-  /* CAN cell init */
-  CAN_InitStructure.CAN_TTCM = DISABLE;
-  CAN_InitStructure.CAN_ABOM = DISABLE;
-  CAN_InitStructure.CAN_AWUM = DISABLE;
-  CAN_InitStructure.CAN_NART = DISABLE;
-  CAN_InitStructure.CAN_RFLM = DISABLE;
-  CAN_InitStructure.CAN_TXFP = DISABLE;
-  CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
-  
-  /* CAN Baudrate = 1MBps*/
-  CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
-  CAN_InitStructure.CAN_BS1 = CAN_BS1_3tq;
-  CAN_InitStructure.CAN_BS2 = CAN_BS2_5tq;
-  CAN_InitStructure.CAN_Prescaler = 4;
-  CAN_Init(CANx, &CAN_InitStructure);
-
-  /* CAN filter init */
-#ifdef  __CAN1_USED__
-  CAN_FilterInitStructure.CAN_FilterNumber = 0;
-#else /*__CAN2_USED__*/
-  CAN_FilterInitStructure.CAN_FilterNumber = 14;
-#endif  /* __CAN1_USED__ */
-  CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
-  CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
-  CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
-  CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
-  CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
-  CAN_FilterInit(&CAN_FilterInitStructure);
-  
-  /* Transmit */
-  TxMessage.StdId = 0x321;
-  TxMessage.ExtId = 0x01;
-  TxMessage.RTR = CAN_RTR_DATA;
-  TxMessage.IDE = CAN_ID_STD;
-  TxMessage.DLC = 1;
-}
-
-/**
-  * @brief  Configures the NVIC for CAN.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Config(void)
-{
-  NVIC_InitTypeDef  NVIC_InitStructure;
-
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
-  
-#ifndef STM32F10X_CL
-#ifdef  __CAN1_USED__
-  NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  /* CAN2 is not implemented in the device */
-   #error "CAN2 is implemented only in Connectivity line devices"
-#endif /*__CAN1_USED__*/
-#else
-#ifdef  __CAN1_USED__ 
-  NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
-#else  /*__CAN2_USED__*/
-  NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
-#endif /*__CAN1_USED__*/
-
-#endif /* STM32F10X_CL*/
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Initializes a Rx Message.
-  * @param  CanRxMsg *RxMessage
-  * @retval None
-  */
-void Init_RxMes(CanRxMsg *RxMessage)
-{
-  uint8_t i = 0;
-
-  RxMessage->StdId = 0x00;
-  RxMessage->ExtId = 0x00;
-  RxMessage->IDE = CAN_ID_STD;
-  RxMessage->DLC = 0;
-  RxMessage->FMI = 0;
-  for (i = 0;i < 8;i++)
-  {
-    RxMessage->Data[i] = 0x00;
-  }
-}
-
-/**
-  * @brief  Turn ON/OFF the dedicate led
-  * @param  Ledstatus: Led number from 0 to 3.
-  * @retval None
-  */
-void LED_Display(uint8_t Ledstatus)
-{
-  /* Turn off all leds */
-  STM_EVAL_LEDOff(LED1);
-  STM_EVAL_LEDOff(LED2);
-  STM_EVAL_LEDOff(LED3);
-  STM_EVAL_LEDOff(LED4);
-  
-  switch(Ledstatus)
-  {
-    case(1): 
-      STM_EVAL_LEDOn(LED1);
-      break;
-   
-    case(2): 
-      STM_EVAL_LEDOn(LED2);
-      break;
- 
-    case(3): 
-      STM_EVAL_LEDOn(LED3);
-      break;
-
-    case(4): 
-      STM_EVAL_LEDOn(LED4);
-      break;
-    default:
-      break;
-  }
-}
-
-/**
-  * @brief  Delay
-  * @param  None
-  * @retval None
-  */
-void Delay(void)
-{
-  uint16_t nTime = 0x0000;
-
-  for(nTime = 0; nTime <0xFFF; nTime++)
-  {
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
deleted file mode 100644
index 0646e17..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CRC/CRC_Calculation/main.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CRC/CRC_Calculation/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CRC_Calculation
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BUFFER_SIZE    114
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static const uint32_t DataBuffer[BUFFER_SIZE] =
-  {
-    0x00001021, 0x20423063, 0x408450a5, 0x60c670e7, 0x9129a14a, 0xb16bc18c,
-    0xd1ade1ce, 0xf1ef1231, 0x32732252, 0x52b54294, 0x72f762d6, 0x93398318,
-    0xa35ad3bd, 0xc39cf3ff, 0xe3de2462, 0x34430420, 0x64e674c7, 0x44a45485,
-    0xa56ab54b, 0x85289509, 0xf5cfc5ac, 0xd58d3653, 0x26721611, 0x063076d7,
-    0x569546b4, 0xb75ba77a, 0x97198738, 0xf7dfe7fe, 0xc7bc48c4, 0x58e56886,
-    0x78a70840, 0x18612802, 0xc9ccd9ed, 0xe98ef9af, 0x89489969, 0xa90ab92b,
-    0x4ad47ab7, 0x6a961a71, 0x0a503a33, 0x2a12dbfd, 0xfbbfeb9e, 0x9b798b58,
-    0xbb3bab1a, 0x6ca67c87, 0x5cc52c22, 0x3c030c60, 0x1c41edae, 0xfd8fcdec,
-    0xad2abd0b, 0x8d689d49, 0x7e976eb6, 0x5ed54ef4, 0x2e321e51, 0x0e70ff9f,
-    0xefbedfdd, 0xcffcbf1b, 0x9f598f78, 0x918881a9, 0xb1caa1eb, 0xd10cc12d,
-    0xe16f1080, 0x00a130c2, 0x20e35004, 0x40257046, 0x83b99398, 0xa3fbb3da,
-    0xc33dd31c, 0xe37ff35e, 0x129022f3, 0x32d24235, 0x52146277, 0x7256b5ea,
-    0x95a88589, 0xf56ee54f, 0xd52cc50d, 0x34e224c3, 0x04817466, 0x64475424,
-    0x4405a7db, 0xb7fa8799, 0xe75ff77e, 0xc71dd73c, 0x26d336f2, 0x069116b0,
-    0x76764615, 0x5634d94c, 0xc96df90e, 0xe92f99c8, 0xb98aa9ab, 0x58444865,
-    0x78066827, 0x18c008e1, 0x28a3cb7d, 0xdb5ceb3f, 0xfb1e8bf9, 0x9bd8abbb,
-    0x4a755a54, 0x6a377a16, 0x0af11ad0, 0x2ab33a92, 0xed0fdd6c, 0xcd4dbdaa,
-    0xad8b9de8, 0x8dc97c26, 0x5c644c45, 0x3ca22c83, 0x1ce00cc1, 0xef1fff3e,
-    0xdf7caf9b, 0xbfba8fd9, 0x9ff86e17, 0x7e364e55, 0x2e933eb2, 0x0ed11ef0
-  };
-
-__IO uint32_t CRCValue = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void Delay(__IO uint32_t nCount);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* Enable CRC clock */
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
-
-  /* Compute the CRC of "DataBuffer" */
-  CRCValue = CRC_CalcBlockCRC((uint32_t *)DataBuffer, BUFFER_SIZE);
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Inserts a delay time.
-  * @param  nCount: specifies the delay time length.
-  * @retval None
-  */
-void Delay(__IO uint32_t nCount)
-{
-  for(; nCount != 0; nCount--);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c
deleted file mode 100644
index 50875b0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/accesspermission.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/accesspermission.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Access rights configuration using Cortex-M3 MPU regions.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup CortexM3_MPU
-  * @{
-  */
-  
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define ARRAY_ADDRESS_START    (0x20002000UL)
-#define ARRAY_SIZE             (0x09UL << 0UL)
-#define ARRAY_REGION_NUMBER    (0x03UL << MPU_RNR_REGION_Pos) 
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-#if defined ( __CC_ARM   )
-uint8_t privilegedreadonlyarray[32] __attribute__((at(0x20002000)));
-
-#elif defined ( __ICCARM__ )
-#pragma location=0x20002000
-__no_init uint8_t privilegedreadonlyarray[32];
-
-#elif defined   (  __GNUC__  )
-uint8_t privilegedreadonlyarray[32] __attribute__((section(".ROarraySection")));
-
-#elif defined   (  __TASKING__  )
-uint8_t privilegedreadonlyarray[32] __at(0x20002000);
-#endif
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  This function configure the access right using Cortex-M3 MPU regions.
-  * @param  None
-  * @retval None
-  */
-void accesspermission(void)
-{
- uint8_t a; 
-  
-  /* Configure region for privilegedreadonlyarray as REGION NÝ3, 32byte and R 
-     only in privileged mode */
-  MPU->RNR  = ARRAY_REGION_NUMBER;
-  MPU->RBAR |= ARRAY_ADDRESS_START;
-  MPU->RASR |= ARRAY_SIZE | portMPU_REGION_PRIVILEGED_READ_ONLY;
-  
-  /* Read from privilegedreadonlyarray. This will not generate error */
-  a = privilegedreadonlyarray[0];
-  
-  /* Uncomment the following line to write to privilegedreadonlyarray. This will
-     generate error */
-  //privilegedreadonlyarray[0] = 'e';
-  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h
deleted file mode 100644
index 7e3ff4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/MPU/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/MPU/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h
deleted file mode 100644
index e9b6cd4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/CortexM3/Mode_Privilege/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    CortexM3/Mode_Privilege/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h
deleted file mode 100644
index 0fb1fe6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DAC/TwoChannels_TriangleWave/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    DAC/TwoChannels_TriangleWave/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt
deleted file mode 100644
index 5ef0865..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/Complete list of DMA examples.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
-  @page DMA_EXAMPLES DMA_EXAMPLES
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   STM32F10x Standard Peripherals DMA Examples List.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-   
-In addition to these examples, there are other examples using the DMA peripheral:
-
-  * <ul>
-  * <li><B>  Complet List of DMA Examples </B>
-  * - @subpage ADC_3ADCs_DMA
-  * - @subpage ADC_ADC1_DMA
-  * - @subpage ADC_ExtLinesTrigger
-  * - @subpage ADC_RegSimul_DualMode 
-  * - @subpage ADC_TIMTrigger_AutoInjection
-  * - @subpage DAC_DualModeDMA_SineWave 
-  * - @subpage DAC_OneChannelDMA_Escalator     
-  * - @subpage I2C_EEPROM
-  * - @subpage I2C_TSENSOR
-  * - @subpage IOExpander_Example
-  * - @subpage NVIC_DMA_WFIMode 
-  * - @subpage SDIO_Example   
-  * - @subpage SPI_DMA
-  * - @subpage TIM_DMA 
-  * - @subpage USART_DMA_Interrupt
-  * - @subpage USART_DMA_Polling 
-  * </ul>  
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */ 
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt
deleted file mode 100644
index f5118ec..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/DMA/I2C_RAM/readme.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  @page DMA_I2C_RAM DMA I2C to RAM example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    DMA/I2C_RAM/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the DMA I2C to RAM example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use two DMA channels to transfer a 
-data buffer from memory to I2C2 through I2C1.
-
-I2C1 is set as the master transmitter and I2C2 as the slave receiver. DMA1 Channel5 is
-configured to store the data received from I2C2 into the Rx buffer (reception buffer).
-DMA1 Channel6 is configured to transfer data from the Tx buffer (transmission buffer)
-to the I2C1 DR register. After the generation of the Start condition and once the slave
-address has been acknowledged, DMA capability is enabled for both I2C1 and I2C2. 
-As soon as the two I2C DMAEN bits are set in the I2C1_CR2 and I2C2_CR2 registers, 
-the transmission of the Tx buffer is started by DMA1 Channel5 and at the same time the
-data received on I2C2 is stored in Rx buffer using DMA1 Channel6 .
-The transmitted and the received buffers are compared to check that all data have been
-correctly transferred.
-
-
-@par Directory contents 
-
-  - DMA/I2C_RAM/stm32f10x_conf.h    Library Configuration file
-  - DMA/I2C_RAM/stm32f10x_it.c      Interrupt handlers
-  - DMA/I2C_RAM/stm32f10x_it.h      Interrupt handlers header file
-  - DMA/I2C_RAM/main.c              Main program
-  - DMA/I2C_RAM/system_stm32f10x.c  STM32F10x system source file
-  
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, Medium-Density, 
-    XL-Density, High-Density Value line, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation boards and can 
-    be easily tailored to any other supported device and development board.
-    This example can't be tested with STMicroelectronics STM3210C-EVAL (STM32F10x 
-    Connectivity-Line) evaluation boards since the I2C2 pins (PB10 and PB11) are 
-    already used by Ethernet PHY module. 
-    This example can't be tested with STMicroelectronics STM32100B-EVAL (STM32F10x 
-    Medium-Density Value line) and STM32100E-EVAL (High-Density Value line) 
-    evaluation boards since the I2C1/I2C2 pins (PB6/PB10 and PB7/PB11) are already 
-    used by HDMI-CEC module.     
-
-  - STM3210E-EVAL Set-up 
-    - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
-    - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin	(PB.11)
-    - Check that a pull-up resistor is connected on one I2C SDA pin
-    - Check that a pull-up resistor is connected on one I2C SCL pin
-
-  - STM3210B-EVAL Set-up 
-    - Connect I2C1 SCL pin (PB.06) to I2C2 SCL pin (PB.10)
-    - Connect I2C1 SDA pin (PB.07) to I2C2 SDA pin	(PB.11)
-    - Check that a pull-up resistor is connected on one I2C SDA pin
-    - Check that a pull-up resistor is connected on one I2C SCL pin    
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt
deleted file mode 100644
index b27b7b4..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FLASH/Dual_Boot/readme.txt
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
-  @page Dual_Boot XL-Density devices FLASH Dual Boot capability example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FLASH/Dual_Boot/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the XL-Density devices FLASH Dual Boot capability example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demonstrates the dual Flash boot capability of XL-Density devices:
-boot from Flash memory Bank1 or Bank2.
-
-At startup, if BFB2 option bit is reset and the boot pins are in the boot from main
-Flash memory configuration, the device boots from Flash memory Bank1 or Bank2,
-depending on the activation of the bank. The active banks are checked in the following
-order: Bank2, followed by Bank1.
-The active bank is identified by the value programmed at the base address of the 
-bank (corresponding to the initial stack pointer value in the interrupt vector table). 
-For further details, please refer to AN2606 "STM32 microcontroller system memory boot mode."
-
-To demonstrate this feature, this example provides two programs:
-  - 1st program will be loaded in Flash Bank1 (starting from @ 0x08000000), for this
-     you have to enable BOOT_FROM_BANK1 define in main.c 
-  - 2nd program will be loaded in Flash Bank2 (starting from @ 0x08080000), for this
-     you have to enable BOOT_FROM_BANK2 define in main.c 
-
-Once these two programs are loaded and boot pins set in boot from Flash memory,
-after reset the device will boot from Bank1 (default). Then you have to follow
-the instructions provided on the LCD:
-  - "Joystick-DOWN: reset BFB2 bit to Boot from Bank2" => when pushing the Joystick
-     DOWN button, BFB2 option bit will be reset then a system (SW) reset will be
-     generated. After startup from reset, the device will boot from Bank2. 
-      - Note: when booting from Bank2 the same menu will be displayed
- 
-  - "Joystick-UP: set BFB2 bit to Boot from Bank1" => when pushing the Joystick
-     UP button, BFB2 option bit will be set then a system (SW) reset will be
-     generated. After startup from reset, the device will boot from Bank1.       
- 
-  - "Joystick-SEL: program to 0x0 the base @ of Bank1/2" => when pushing the Joystick
-     SEL button, the content of address 0x08080000 and 0x08000000 will be programmed to 0x0.
-       - If the program was previously booting from Bank2 (i.e. BFB2 bit is reset), 
-         in this case after reset no program is executed and the Bootloader code
-         is executed instead. 
-       - If the program was previously booting from Bank1 (i.e. BFB2 bit is set), 
-         in this case after reset no program is executed.
-       - You have to load again the two programs to Bank1 and Bank2.
- 
-@b Important Note
-=================
-When BFB2 bit is cleared and Bank2 or/and Bank1 contain valid user application code,
-the Bootloader will always jump to this code and never continue normal code execution 
-(i.e. it’s no more possible to use the Bootloader for code upgrade and option bytes
-programming). As consequence, if the user has cleared BFB2 bit (to boot from Bank2),
-in order to be able to execute the embedded Bootloader code he has to: 
-   - either, set BFB2 bit to 1
-   - or, program the content of address 0x08080000 and 0x08000000 to 0x0
-=> This example allows performing the two actions described above.
-
-
-@par Directory contents 
-
-  - FLASH/Dual_Boot/stm32f10x_conf.h    Library Configuration file
-  - FLASH/Dual_Boot/stm32f10x_it.h      Interrupt handlers header file
-  - FLASH/Dual_Boot/stm32f10x_it.c      Interrupt handlers
-  - FLASH/Dual_Boot/main.c              Main program
-  - FLASH/Dual_Boot/system_stm32f10x.c  STM32F10x system source file
-
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (XL-Density) 
-    evaluation board and can be easily tailored to any development board. 
-
- 
-@par How to use it ? 
-    
-In order to load the IAP code, you have to do the following:
- - EWARM:
-    - Open the Project.eww workspace
-    - In the workspace toolbar select the project config:
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor)
-    - Rebuild all files: Project->Rebuild all
-    - Load project image: Project->Debug
-    - Run program: Debug->Go(F5)
-
- - HiTOP
-    - Open the HiTOP toolchain.
-    - Browse to open:
-        -STM32F10X_XL_BANK1.htp: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                             already defined in the project preprocessor)
-        -STM32F10X_XL_BANK2.htp: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                             already defined in the project preprocessor)  
-     - A "Download application" window is displayed, click "cancel".
-     - Rebuild all files: Project->Rebuild all
-     - Load project image : Click "ok" in the "Download application" window.
-     - Run the "RESET_GO_MAIN" script to set the PC at the "main"
-     - Run program: Debug->Go(F5).
-     
- - MDK-ARM 
-    - Open Project.uvproj project
-    - In the build toolbar select the project config:
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor)  
-    - Rebuild all files: Project->Rebuild all target files
-    - Load project image: Debug->Start/Stop Debug Session
-    - Run program: Debug->Run (F5)
-
- - TrueSTUDIO 
-    - Open the TrueSTUDIO toolchain.
-    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
-      directory.
-    - Click on File->Import, select General->'Existing Projects into Workspace' 
-      and then click "Next". 
-    - Browse to the TrueSTUDIO workspace directory and select the project: 
-        - STM32F10X_XL_BANK1: to load the program in Flash bank1 (BOOT_FROM_BANK1
-                              already defined in the project preprocessor)    
-        - STM32F10X_XL_BANK2: to load the program in Flash bank2 (BOOT_FROM_BANK2
-                              already defined in the project preprocessor) 
-    - Under Windows->Preferences->General->Workspace->Linked Resources, add 
-      a variable path named "CurPath" which points to the folder containing
-      "Libraries", "Project" and "Utilities" folders.
-    - Rebuild all project files: Select the project in the "Project explorer" 
-      window then click on Project->build project menu.
-    - Run program: Select the project in the "Project explorer" window then click 
-      Run->Debug (F11)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.  
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h
deleted file mode 100644
index 39e43ea..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
deleted file mode 100644
index c508705..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/binary/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt
deleted file mode 100644
index ee90ac8..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/readme.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
-  @page FSMC_NOR_CodeExecute FSMC NOR CodeExecute example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    FSMC/NOR_CodeExecute/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the FSMC NOR CodeExecute example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This directory contains a set of sources files that describes how to build an
-application to be loaded into the NOR memory mounted on STM3210E-EVAL board then
-execute it from internal Flash.
-
-@par Directory contents 
-
- - FSMC/NOR_CodeExecute/binary: Contains a set of sources files that build the 
-                                application to be loaded into the NOR memory 
-                                mounted on STM3210E-EVAL board.
- - FSMC/NOR_CodeExecute/stm32f10x_conf.h    Library Configuration file 
- - FSMC/NOR_CodeExecute/stm32f10x_it.c      Interrupt handlers 
- - FSMC/NOR_CodeExecute/stm32f10x_it.h      Header for stm32f10x_it.c 
- - FSMC/NOR_CodeExecute/main.c              Main program 
- - FSMC/NOR_CodeExecute/system_stm32f10x.c  STM32F10x system source file
-    
-@par Hardware and Software environment 
-
-  - This example runs only on STM32F10x High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM3210E-EVAL (High-Density
-    and XL-Density) evaluation board and can be easily tailored to any other 
-    supported device and development board.
-    
-@par How to use it ? 
-
-In order to make the program work, you must do the following:
-
-1. Program the NOR memory with the example provided in the "binary" directory
-
-2. Program the internal Flash with the code that will jump to the NOR memory to execute 
-   the loaded example, for this you have to:      
-   - Copy all source files from this example folder to the template folder under
-     Project\STM32F10x_StdPeriph_Template
-   - Open your preferred toolchain 
-   - Rebuild all files and load your image into target memory
-   - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.   
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h
deleted file mode 100644
index b9ae62b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/NOR_CodeExecute/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/NOR_CodeExecute/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
deleted file mode 100644
index 9ef7497..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/OneNAND/main.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/OneNAND/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-#include "stm32100e_eval_fsmc_onenand.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup FSMC_OneNAND
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define OneNAND_SAMSUNG_MANUFACTURER_ID     0x00EC
-#define OneNAND_SAMSUNG_DEVICE_ID           0x0025
-
-#define OneNAND_BUFFER_SIZE                 0x0400 /* Page size: 1024 x 16 bits = 2048 Bytes */
-#define OneNAND_WRITE_BLOCK_NUMBER          0x0000 /* should be between 0 and 511, the block size is 128 KBytes */
-#define OneNAND_WRITE_PAGE_NUMBER           0x0000 /* The page size inside a Block is 2 KBytes */
-#define OneNAND_NUMBER_OF_PAGE_PER_BLOCK    0x0040 /* 64 pages per block */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-OneNAND_IDTypeDef OneNAND_ID;
-OneNAND_ADDRESS Address;
-uint16_t TxBuffer[OneNAND_BUFFER_SIZE], RxBuffer_A[OneNAND_BUFFER_SIZE], RxBuffer_S[OneNAND_BUFFER_SIZE];
-uint32_t j = 0, PageIndex = 0, Status = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset);
-
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-  
-  /* Initialize LEDs on STM3220F-EVAL board */
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);  
-  STM_EVAL_LEDInit(LED4); 
-  
-  /* FSMC Initialization */
-  OneNAND_Init();
-
-  /* Read OneNAND memory ID */
-  OneNAND_ReadID(&OneNAND_ID);
-
-  /* Verify the OneNAND ID */ 
-  if((OneNAND_ID.Manufacturer_ID == OneNAND_SAMSUNG_MANUFACTURER_ID) && 
-     (OneNAND_ID.Device_ID == OneNAND_SAMSUNG_DEVICE_ID)) 
-  {
-    /* Fill the buffer to send */
-    Fill_hBuffer(TxBuffer, OneNAND_BUFFER_SIZE , 0x320F);
-    Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-    Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-    
-
-    /***** Erase then write to the OneNAND memory ******************************/  
-    /* Unlock the selected OneNAND block */
-    Status = OneNAND_UnlockBlock(OneNAND_WRITE_BLOCK_NUMBER);
-
-    if (Status == 0)
-    { 
-      /* Erase the selected OneNAND block */
-      Status = OneNAND_EraseBlock(Address.Block);
-
-      if (Status == 0)
-      { 
-        /* Write data to the OneNAND memory (128Kbytes by page 2KBytes each) */
-        for(PageIndex = 0; (PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK) && (Status ==0); PageIndex++)
-        {
-          Status = OneNAND_WriteBuffer(TxBuffer, Address, OneNAND_BUFFER_SIZE);
-          Address.Page++;
-        }
-
-        if (Status == 0)
-        { 
-          /***** Verify of the written data using asynchronous read ***********/
-          Fill_hBuffer(RxBuffer_A, OneNAND_BUFFER_SIZE , 0xFF);
-          Status = 0;
-          Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-          Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-
-          for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
-          {
-            /* Read back the written data (By page) */
-            OneNAND_AsynchronousRead(RxBuffer_A, Address, OneNAND_BUFFER_SIZE);
-   
-            /* Verify the written data */
-            for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
-            {
-              if(TxBuffer[j] != RxBuffer_A[j])
-              {
-                Status++;
-              }
-            }
-            Address.Page++;
-          }
-          
-          if (Status != 0)
-          { 
-            /* Turn ON LED2 */
-            STM_EVAL_LEDOn(LED2); 
-          }
-
-          /***** Verify of the written data using synchronous read ************/   
-          Fill_hBuffer(RxBuffer_S, OneNAND_BUFFER_SIZE , 0xFF);
-          Status = 0;
-          Address.Block = OneNAND_WRITE_BLOCK_NUMBER;
-          Address.Page = OneNAND_WRITE_PAGE_NUMBER;
-
-          for(PageIndex = 0; PageIndex < OneNAND_NUMBER_OF_PAGE_PER_BLOCK; PageIndex++)
-          {
-            /* Read back the written data (By page) */
-            OneNAND_SynchronousRead(RxBuffer_S, Address, OneNAND_BUFFER_SIZE);
-   
-            /* Verify the written data */
-            for(j = 0; j < OneNAND_BUFFER_SIZE; j++)
-            {
-              if(TxBuffer[j] != RxBuffer_S[j])
-              {
-                Status++;
-              }
-            }
-            Address.Page++;
-          }
-
-          if (Status != 0)
-          { 
-            /* Turn ON LED3 */
-            STM_EVAL_LEDOn(LED3);
-          }
-        }        
-        else
-        { 
-          /* Turn ON LED4 */
-          STM_EVAL_LEDOn(LED4); 
-        }
-      } 
-      else
-      { 
-        /* Turn ON LED2 and LED4*/
-        STM_EVAL_LEDOn(LED2); 
-        STM_EVAL_LEDOn(LED4); 
-      }     
-    } 
-    else
-    { 
-      /* Turn ON LED3 and LED4 */
-      STM_EVAL_LEDOn(LED3);
-      STM_EVAL_LEDOn(LED4); 
-    }  
-  }
-  else
-  {
-    /* Turn ON LED2, LED3 and LED4 */
-    STM_EVAL_LEDOn(LED2);    
-    STM_EVAL_LEDOn(LED3);
-    STM_EVAL_LEDOn(LED4);
-  }
-
-  if (Status == 0)
-  { 
-   /* Turn ON LED1 */
-   STM_EVAL_LEDOn(LED1);
-  }
-  		  
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Fills a global 16-bit buffer
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  BufferSize: size of the buffer to fill
-  * @param  Offset: first value to fill on the Buffer
-  * @retval None
-  */
-void Fill_hBuffer(uint16_t *pBuffer, uint16_t BufferLenght, uint32_t Offset)
-{
-  uint16_t IndexTmp = 0;
-
-  /* Put in global buffer different values */
-  for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
-  {
-    pBuffer[IndexTmp] = IndexTmp + Offset;
-  }
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h
deleted file mode 100644
index 32e2cf2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/FSMC/SRAM/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    FSMC/SRAM/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h
deleted file mode 100644
index 210aea2..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/GPIO/JTAG_Remap/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    GPIO/JTAG_Remap/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
deleted file mode 100644
index ce8cb69..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/EEPROM/main.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/EEPROM/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval_i2c_ee.h"
-
-
-#ifdef USE_STM3210E_EVAL
- #include "stm3210e_eval_lcd.h"
-#elif defined(USE_STM3210B_EVAL)
- #include "stm3210b_eval_lcd.h"
-#elif defined(USE_STM3210C_EVAL)
- #include "stm3210c_eval_lcd.h"
-#elif defined(USE_STM32100B_EVAL)
- #include "stm32100b_eval_lcd.h"
-#elif defined(USE_STM32100E_EVAL)
- #include "stm32100e_eval_lcd.h"
-#endif /* USE_STM3210E_EVAL */  
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup I2C_EEPROM
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-/* Uncomment the following line to enable using LCD screen for messages display */
-#define ENABLE_LCD_MSG_DISPLAY
-
-#define sEE_WRITE_ADDRESS1        0x50
-#define sEE_READ_ADDRESS1         0x50
-#define BUFFER_SIZE1             (countof(Tx1_Buffer)-1)
-#define BUFFER_SIZE2             (countof(Tx2_Buffer)-1)
-#define sEE_WRITE_ADDRESS2       (sEE_WRITE_ADDRESS1 + BUFFER_SIZE1)
-#define sEE_READ_ADDRESS2        (sEE_READ_ADDRESS1 + BUFFER_SIZE1)
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a) (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-uint8_t Tx1_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
-                        buffer 1 transfer into address sEE_WRITE_ADDRESS1 */ \
-                        Example Description \
-                        This firmware provides a basic example of how to use the I2C firmware library and\
-                        an associate I2C EEPROM driver to communicate with an I2C EEPROM device (here the\
-                        example is interfacing with M24C64 EEPROM)\
-                          \
-                        I2C peripheral is configured in Master transmitter during write operation and in\
-                        Master receiver during read operation from I2C EEPROM. \
-                          \
-                        The peripheral used is I2C1 but can be configured by modifying the defines values\
-                        in stm32xxxx_eval.h file. The speed is set to 200kHz and can be configured by \
-                        modifying the relative define in stm32_eval_i2c_ee.h file.\
-                         \
-                        For M24C64 devices all the memory is accessible through the two-bytes \
-                        addressing mode and need to define block addresses. In this case, only the physical \
-                        address has to be defined (according to the address pins (E0,E1 and E2) connection).\
-                        This address is defined in i2c_ee.h (default is 0xA0: E0, E1 and E2 tied to ground).\
-                        The EEPROM addresses where the program start the write and the read operations \
-                        is defined in the main.c file. \
-                         \
-                        First, the content of Tx1_Buffer is written to the EEPROM_WriteAddress1 and the\
-                        written data are read. The written and the read buffers data are then compared.\
-                        Following the read operation, the program waits that the EEPROM reverts to its \
-                        Standby state. A second write operation is, then, performed and this time, Tx2_Buffer\
-                        is written to EEPROM_WriteAddress2, which represents the address just after the last \
-                        written one in the first write. After completion of the second write operation, the \
-                        written data are read. The contents of the written and the read buffers are compared.\
-                         \
-                        All transfers are managed in DMA mode (except when 1-byte read/write operation is\
-                        required). Once sEE_ReadBuffer() or sEE_WriteBuffer() function is called, the \
-                        use application may perform other tasks in parallel while Read/Write operation is\
-                        managed by DMA.\
-                          \
-                        This example provides the possibility to use the STM32XXXX-EVAL LCD screen for\
-                        messages display (transfer status: Ongoing, PASSED, FAILED).\
-                        To enable this option uncomment the define ENABLE_LCD_MSG_DISPLAY in the main.c\
-                        file.                                                                              ";
-uint8_t Tx2_Buffer[] = "/* STM32F10xx I2C Firmware Library EEPROM driver example: \
-                        buffer 2 transfer into address sEE_WRITE_ADDRESS2 */";
-uint8_t Rx1_Buffer[BUFFER_SIZE1], Rx2_Buffer[BUFFER_SIZE2];
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-volatile uint16_t NumDataRead = 0;
-
-/* Private functions ---------------------------------------------------------*/
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-#ifdef ENABLE_LCD_MSG_DISPLAY
-  /* Initialize the LCD screen for information display */
- #ifdef USE_STM3210E_EVAL
-  STM3210E_LCD_Init();
- #elif defined(USE_STM3210B_EVAL)
-  STM3210B_LCD_Init();
- #elif defined(USE_STM3210C_EVAL)
-  STM3210C_LCD_Init();
- #elif defined(USE_STM32100B_EVAL)
-  STM32100B_LCD_Init();
- #elif defined(USE_STM32100E_EVAL)
-  STM32100E_LCD_Init();
- #endif /* USE_STM3210E_EVAL */  
-  
-  /* Display application information */
-  LCD_Clear(LCD_COLOR_BLUE);  
-  LCD_SetBackColor(LCD_COLOR_BLUE);
-  LCD_SetTextColor(LCD_COLOR_WHITE);
-  LCD_DisplayStringLine(LCD_LINE_0, "SMT32F1xx FW Library");
-  LCD_DisplayStringLine(LCD_LINE_1, "   EEPROM Example   ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */    
-  
-  /* Initialize the I2C EEPROM driver ----------------------------------------*/
-  sEE_Init();  
-
-  /* First write in the memory followed by a read of the written data --------*/
-  /* Write on I2C EEPROM from sEE_WRITE_ADDRESS1 */
-  sEE_WriteBuffer(Tx1_Buffer, sEE_WRITE_ADDRESS1, BUFFER_SIZE1);
-
-  /* Set the Number of data to be read */
-  NumDataRead = BUFFER_SIZE1;
-  
-  /* Read from I2C EEPROM from sEE_READ_ADDRESS1 */
-  sEE_ReadBuffer(Rx1_Buffer, sEE_READ_ADDRESS1, (uint16_t *)(&NumDataRead)); 
-
-#ifdef ENABLE_LCD_MSG_DISPLAY  
-  LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 Ongoing ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */   
-
-  /* Wait till DMA transfer is complete (Transfer complete interrupt handler 
-    resets the variable holding the number of data to be read) */
-  while (NumDataRead > 0)
-  {    
-    /* Starting from this point, if the requested number of data is higher than 1, 
-       then only the DMA is managing the data transfer. Meanwhile, CPU is free to 
-       perform other tasks:
-       
-      // Add your code here: 
-      //...
-      //...
-  
-       For simplicity reasons, this example is just waiting till the end of the 
-       transfer. */    
-  }
-  
-  /* Check if the data written to the memory is read correctly */
-  TransferStatus1 = Buffercmp(Tx1_Buffer, Rx1_Buffer, BUFFER_SIZE1);
-  /* TransferStatus1 = PASSED, if the transmitted and received data 
-     to/from the EEPROM are the same */
-  /* TransferStatus1 = FAILED, if the transmitted and received data 
-     to/from the EEPROM are different */
-#ifdef ENABLE_LCD_MSG_DISPLAY  
-  if (TransferStatus1 == PASSED)
-  {
-    LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 PASSED  ");
-  }
-  else
-  {
-    LCD_DisplayStringLine(LCD_LINE_3, " Transfer 1 FAILED  ");
-  }  
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-
-/*----------------------------------
-  
-                                    ------------------------------------------*/
-  
-  /* Second write in the memory followed by a read of the written data -------*/
-  /* Write on I2C EEPROM from sEE_WRITE_ADDRESS2 */
-  sEE_WriteBuffer(Tx2_Buffer, sEE_WRITE_ADDRESS2, BUFFER_SIZE2);
-
-  /* Set the Number of data to be read */
-  NumDataRead = BUFFER_SIZE2;  
-  
-  /* Read from I2C EEPROM from sEE_READ_ADDRESS2 */
-  sEE_ReadBuffer(Rx2_Buffer, sEE_READ_ADDRESS2, (uint16_t *)(&NumDataRead));
-
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 Ongoing ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */  
-  
-  /* Wait till DMA transfer is complete (Transfer complete interrupt handler 
-    resets the variable holding the number of data to be read) */
-  while (NumDataRead > 0)
-  {
-    /* Starting from this point, if the requested number of data is higher than 1, 
-       then only the DMA is managing the data transfer. Meanwhile, CPU is free to 
-       perform other tasks:
-       
-      // Add your code here: 
-      //...
-      //...
-  
-       For simplicity reasons, this example is just waiting till the end of the 
-       transfer. */    
-  }
-  
-  /* Check if the data written to the memory is read correctly */
-  TransferStatus2 = Buffercmp(Tx2_Buffer, Rx2_Buffer, BUFFER_SIZE2);
-  /* TransferStatus2 = PASSED, if the transmitted and received data 
-     to/from the EEPROM are the same */
-  /* TransferStatus2 = FAILED, if the transmitted and received data 
-     to/from the EEPROM are different */
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  if (TransferStatus1 == PASSED)
-  {
-    LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 PASSED  ");
-  }
-  else
-  {
-    LCD_DisplayStringLine(LCD_LINE_5, " Transfer 2 FAILED  ");
-  }  
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-  
-  /* Free all used resources */
-  sEE_DeInit();
-
-#ifdef ENABLE_LCD_MSG_DISPLAY
-  /* Display end of example information */
-  LCD_DisplayStringLine(LCD_LINE_7, "---End Of Example---");
-#endif /* ENABLE_LCD_MSG_DISPLAY */  
-
-  while (1)
-  {
-  }
-}
-
-#ifndef USE_DEFAULT_TIMEOUT_CALLBACK
-/**
-  * @brief  Example of timeout situation management.
-  * @param  None.
-  * @retval None.
-  */
-uint32_t sEE_TIMEOUT_UserCallback(void)
-{
-  /* Use application may try to recover the communication by resetting I2C
-    peripheral (calling the function I2C_SoftwareResetCmd()) then re-start
-    the transmission/reception from a previously stored recover point.
-    For simplicity reasons, this example only shows a basic way for errors 
-    managements which consists of stopping all the process and requiring system
-    reset. */
-  
-#ifdef ENABLE_LCD_MSG_DISPLAY   
-  /* Display error message on screen */
-  LCD_Clear(LCD_COLOR_RED);  
-  LCD_DisplayStringLine(LCD_LINE_4, "Communication ERROR!");
-  LCD_DisplayStringLine(LCD_LINE_5, "Try again after res-");
-  LCD_DisplayStringLine(LCD_LINE_6, "  etting the Board  ");
-#endif /* ENABLE_LCD_MSG_DISPLAY */
-  
-  /* Block communication and all processes */
-  while (1)
-  {   
-  }  
-}
-
-#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-    
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;  
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c
deleted file mode 100644
index a892d06..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2C/IOExpander/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2C/IOExpander/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h
deleted file mode 100644
index d78b0da..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/I2S/Interrupt/stm32f10x_it.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    I2S/Interrupt/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void SPI2_IRQHandler(void);
-void SPI3_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
deleted file mode 100644
index 2d6baa3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/Lib_DEBUG/RunTime_Check/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Lib_DEBUG/RunTime_Check/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-#define USE_FULL_ASSERT    1
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h
deleted file mode 100644
index f21d3d0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/DMA_WFIMode/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    NVIC/DMA_WFIMode/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk
deleted file mode 100644
index 3f877d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/NVIC/VectorTable_Relocation/linker/HiTOP/STM3210C-EVAL/link_offset.lnk
+++ /dev/null
@@ -1,5 +0,0 @@
--d"./settings/STM32F10x_offset.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
---output=.\Objects\$(Target)
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h
deleted file mode 100644
index f5534f0..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c
deleted file mode 100644
index b0e6201..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RCC/RCC_ClockConfig/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RCC/RCC_ClockConfig/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
deleted file mode 100644
index e2e18ec..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/main.c
+++ /dev/null
@@ -1,410 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval.h"
-#include <stdio.h>
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup RTC_Calendar
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define RTCClockOutput_Enable  /* RTC Clock/64 is output on tamper pin(PC.13) */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-__IO uint32_t TimeDisplay = 0;
-USART_InitTypeDef USART_InitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RTC_Configuration(void);
-void NVIC_Configuration(void);
-uint32_t Time_Regulate(void);
-void Time_Adjust(void);
-void Time_Show(void);
-void Time_Display(uint32_t TimeVar);
-uint8_t USART_Scanf(uint32_t value);
-
-#ifdef __GNUC__
-/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
-   set to 'Yes') calls __io_putchar() */
-#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
-#else
-#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
-#endif /* __GNUC__ */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-
-  /* Initialize LED1 mounted on STM3210X-EVAL board */       
-  STM_EVAL_LEDInit(LED1);
-
-  /* USARTx configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-
-
-  /* NVIC configuration */
-  NVIC_Configuration();
-
-  if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
-  {
-    /* Backup data register value is not correct or not yet programmed (when
-       the first time the program is executed) */
-
-    printf("\r\n\n RTC not yet configured....");
-
-    /* RTC Configuration */
-    RTC_Configuration();
-
-    printf("\r\n RTC configured....");
-
-    /* Adjust time by values entered by the user on the hyperterminal */
-    Time_Adjust();
-
-    BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
-  }
-  else
-  {
-    /* Check if the Power On Reset flag is set */
-    if (RCC_GetFlagStatus(RCC_FLAG_PORRST) != RESET)
-    {
-      printf("\r\n\n Power On Reset occurred....");
-    }
-    /* Check if the Pin Reset flag is set */
-    else if (RCC_GetFlagStatus(RCC_FLAG_PINRST) != RESET)
-    {
-      printf("\r\n\n External Reset occurred....");
-    }
-
-    printf("\r\n No need to configure RTC....");
-    /* Wait for RTC registers synchronization */
-    RTC_WaitForSynchro();
-
-    /* Enable the RTC Second */
-    RTC_ITConfig(RTC_IT_SEC, ENABLE);
-    /* Wait until last write operation on RTC registers has finished */
-    RTC_WaitForLastTask();
-  }
-
-#ifdef RTCClockOutput_Enable
-  /* Enable PWR and BKP clocks */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Allow access to BKP Domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Disable the Tamper Pin */
-  BKP_TamperPinCmd(DISABLE); /* To output RTCCLK/64 on Tamper pin, the tamper
-                                 functionality must be disabled */
-
-  /* Enable RTC Clock Output on Tamper Pin */
-  BKP_RTCOutputConfig(BKP_RTCOutputSource_CalibClock);
-#endif
-
-  /* Clear reset flags */
-  RCC_ClearFlag();
-
-  /* Display time in infinite loop */
-  Time_Show();
-}
-
-
-/**
-  * @brief  Configures the nested vectored interrupt controller.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure one bit for preemption priority */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-
-  /* Enable the RTC Interrupt */
-  NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Configures the RTC.
-  * @param  None
-  * @retval None
-  */
-void RTC_Configuration(void)
-{
-  /* Enable PWR and BKP clocks */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
-
-  /* Allow access to BKP Domain */
-  PWR_BackupAccessCmd(ENABLE);
-
-  /* Reset Backup Domain */
-  BKP_DeInit();
-
-  /* Enable LSE */
-  RCC_LSEConfig(RCC_LSE_ON);
-  /* Wait till LSE is ready */
-  while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
-  {}
-
-  /* Select LSE as RTC Clock Source */
-  RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
-  /* Enable RTC Clock */
-  RCC_RTCCLKCmd(ENABLE);
-
-  /* Wait for RTC registers synchronization */
-  RTC_WaitForSynchro();
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-
-  /* Enable the RTC Second */
-  RTC_ITConfig(RTC_IT_SEC, ENABLE);
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-
-  /* Set RTC prescaler: set RTC period to 1sec */
-  RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
-
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-}
-
-/**
-  * @brief  Returns the time entered by user, using Hyperterminal.
-  * @param  None
-  * @retval Current time RTC counter value
-  */
-uint32_t Time_Regulate(void)
-{
-  uint32_t Tmp_HH = 0xFF, Tmp_MM = 0xFF, Tmp_SS = 0xFF;
-
-  printf("\r\n==============Time Settings=====================================");
-  printf("\r\n  Please Set Hours");
-
-  while (Tmp_HH == 0xFF)
-  {
-    Tmp_HH = USART_Scanf(23);
-  }
-  printf(":  %d", Tmp_HH);
-  printf("\r\n  Please Set Minutes");
-  while (Tmp_MM == 0xFF)
-  {
-    Tmp_MM = USART_Scanf(59);
-  }
-  printf(":  %d", Tmp_MM);
-  printf("\r\n  Please Set Seconds");
-  while (Tmp_SS == 0xFF)
-  {
-    Tmp_SS = USART_Scanf(59);
-  }
-  printf(":  %d", Tmp_SS);
-
-  /* Return the value to store in RTC counter register */
-  return((Tmp_HH*3600 + Tmp_MM*60 + Tmp_SS));
-}
-
-/**
-  * @brief  Adjusts time.
-  * @param  None
-  * @retval None
-  */
-void Time_Adjust(void)
-{
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-  /* Change the current time */
-  RTC_SetCounter(Time_Regulate());
-  /* Wait until last write operation on RTC registers has finished */
-  RTC_WaitForLastTask();
-}
-
-/**
-  * @brief  Displays the current time.
-  * @param  TimeVar: RTC counter value.
-  * @retval None
-  */
-void Time_Display(uint32_t TimeVar)
-{
-  uint32_t THH = 0, TMM = 0, TSS = 0;
-  
-  /* Reset RTC Counter when Time is 23:59:59 */
-  if (RTC_GetCounter() == 0x0001517F)
-  {
-     RTC_SetCounter(0x0);
-     /* Wait until last write operation on RTC registers has finished */
-     RTC_WaitForLastTask();
-  }
-  
-  /* Compute  hours */
-  THH = TimeVar / 3600;
-  /* Compute minutes */
-  TMM = (TimeVar % 3600) / 60;
-  /* Compute seconds */
-  TSS = (TimeVar % 3600) % 60;
-
-  printf("Time: %0.2d:%0.2d:%0.2d\r", THH, TMM, TSS);
-}
-
-/**
-  * @brief  Shows the current time (HH:MM:SS) on the Hyperterminal.
-  * @param  None
-  * @retval None
-  */   
-void Time_Show(void)
-{
-  printf("\n\r");
-
-  /* Infinite loop */
-  while (1)
-  {
-    /* If 1s has been elapsed */
-    if (TimeDisplay == 1)
-    {
-      /* Display current time */
-      Time_Display(RTC_GetCounter());
-      TimeDisplay = 0;
-    }
-  }
-}
-
-
-/**
-  * @brief  Retargets the C library printf function to the USART.
-  * @param  None
-  * @retval None
-  */
-PUTCHAR_PROTOTYPE
-{
-  /* Place your implementation of fputc here */
-  /* e.g. write a character to the USART */
-  USART_SendData(EVAL_COM1, (uint8_t) ch);
-
-  /* Loop until the end of transmission */
-  while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_TC) == RESET)
-  {}
-
-  return ch;
-}
-
-/**
-  * @brief  Gets numeric values from the hyperterminal.
-  * @param  None
-  * @retval None
-  */
-uint8_t USART_Scanf(uint32_t value)
-{
-  uint32_t index = 0;
-  uint32_t tmp[2] = {0, 0};
-
-  while (index < 2)
-  {
-    /* Loop until RXNE = 1 */
-    while (USART_GetFlagStatus(EVAL_COM1, USART_FLAG_RXNE) == RESET)
-    {}
-    tmp[index++] = (USART_ReceiveData(EVAL_COM1));
-    if ((tmp[index - 1] < 0x30) || (tmp[index - 1] > 0x39))
-    {
-      printf("\n\rPlease enter valid number between 0 and 9");
-      index--;
-    }
-  }
-  /* Calculate the Corresponding value */
-  index = (tmp[1] - 0x30) + ((tmp[0] - 0x30) * 10);
-  /* Checks */
-  if (index > value)
-  {
-    printf("\n\rPlease enter valid number between 0 and %d", value);
-    return 0xFF;
-  }
-  return index;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h
deleted file mode 100644
index 861a5e1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/Calendar/stm32f10x_it.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    RTC/Calendar/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void RTC_IRQHandler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt
deleted file mode 100644
index f465c39..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/RTC/LSI_Calib/readme.txt
+++ /dev/null
@@ -1,111 +0,0 @@
-
-/**
-  @page RTC_LSI_Calib RTC LSI_Calib example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    RTC/LSI_Calib/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the RTC LSI_Calib example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example demonstrates and explains how to use the LSI clock source auto
-calibration to get a precise RTC clock. 
-As an application example, it demonstrates how to configure the TIM5 timer
-internally connected to LSI clock output, in order to adjust the RTC prescaler. 
-
-The Low Speed External (LSI) clock is used as RTC clock source.
-After reset, the RTC prescaler is set with the default value (40000). 
-The inaccuracy of the LSI clock causes the RTC Second signal to be inaccurate. This
-signal is output on the Tamper pin (PC.13) and can be measured by on oscilloscope
-or a frequencymeter.
-
-The program waits until Key Push button is pressed to begin the auto calibration procedure:
- - Configure the TIM5 to remap internally the TIM5 Channel 4 Input Capture to the
-   LSI clock output.
- - Enable the TIM5 Input Capture interrupt: after one cycle of LSI clock, the
-   period value is stored in a variable and compared to the HCLK clock to get
-   its real value.
- - The RTC prescaler is adjusted with this LSI frequency value so that the RTC
-   Second value become more accurate.
- - When calibration is done a led connected to PF.07 is turned ON to indicate the
-    end of this operation. At this moment, you can  monitor the Second signal on
-    an oscilloscope to measure its accuracy again.
-
-The RTC Second signal can be monitored either on Tamper pin or on LED1 which is 
-toggled into the RTC Second interrupt service routine.
-    
- 
-@par Directory contents 
-
-  - RTC/LSI_Calib/stm32f10x_conf.h     Library Configuration file
-  - RTC/LSI_Calib/stm32f10x_it.c       Interrupt handlers
-  - RTC/LSI_Calib/stm32f10x_it.h       Header for stm32f10x_it.c
-  - RTC/LSI_Calib/main.h               Main header file
-  - RTC/LSI_Calib/main.c               Main program
-  - RTC/LSI_Calib/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density Value line,
-    High-Density and XL-Density Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM3210E-EVAL (High-Density and XL-Density) and STM3210C-EVAL 
-    (Connectivity Line) evaluation boards and can be easily tailored to any other 
-    supported device and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file (under Utilities\STM32_EVAL)
-
-  - STM32100E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the Key push button connected to PG.08 pin
-    
-  - STM3210C-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PD.07 and PD.13 pins
-    - Use the Key push-button connected to PB.09 pin
-
-  - STM3210E-EVAL Set-up 
-    - Use LD1 and LD2 leds connected respectively to PF.06 and PF.07 pins
-    - Use the Key push button connected to PG.08 pin
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
deleted file mode 100644
index 3a28739..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/main.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "stm32_eval_sdio_sd.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SDIO_uSDCard
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BLOCK_SIZE            512 /* Block Size in Bytes */
-
-#define NUMBER_OF_BLOCKS      32  /* For Multi Blocks operation (Read/Write) */
-#define MULTI_BUFFER_SIZE    (BLOCK_SIZE * NUMBER_OF_BLOCKS)
-
-#define SD_OPERATION_ERASE          0
-#define SD_OPERATION_BLOCK          1
-#define SD_OPERATION_MULTI_BLOCK    2 
-#define SD_OPERATION_END            3
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint8_t Buffer_Block_Tx[BLOCK_SIZE], Buffer_Block_Rx[BLOCK_SIZE];
-uint8_t Buffer_MultiBlock_Tx[MULTI_BUFFER_SIZE], Buffer_MultiBlock_Rx[MULTI_BUFFER_SIZE];
-volatile TestStatus EraseStatus = FAILED, TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-SD_Error Status = SD_OK;
-__IO uint32_t SDCardOperation = SD_OPERATION_ERASE;
-
-/* Private function prototypes -----------------------------------------------*/
-void NVIC_Configuration(void);
-void SD_EraseTest(void);
-void SD_SingleBlockTest(void);
-void SD_MultiBlockTest(void);
-void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength);
-TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program.
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */
-
-  /* Initialize LEDs available on STM3210X-EVAL board *************************/
-  STM_EVAL_LEDInit(LED1);
-  STM_EVAL_LEDInit(LED2);
-  STM_EVAL_LEDInit(LED3);
-  STM_EVAL_LEDInit(LED4);  
-
-  /* Interrupt Config */
-  NVIC_Configuration();
-
-  /*------------------------------ SD Init ---------------------------------- */
-  if((Status = SD_Init()) != SD_OK)
-  {
-    STM_EVAL_LEDOn(LED4); 
-  }
-        
-  while((Status == SD_OK) && (SDCardOperation != SD_OPERATION_END) && (SD_Detect()== SD_PRESENT))
-  {
-    switch(SDCardOperation)
-    {
-      /*-------------------------- SD Erase Test ---------------------------- */
-      case (SD_OPERATION_ERASE):
-      {
-        SD_EraseTest();
-        SDCardOperation = SD_OPERATION_BLOCK;
-        break;
-      }
-      /*-------------------------- SD Single Block Test --------------------- */
-      case (SD_OPERATION_BLOCK):
-      {
-        SD_SingleBlockTest();
-        SDCardOperation = SD_OPERATION_MULTI_BLOCK;
-        break;
-      }       
-      /*-------------------------- SD Multi Blocks Test --------------------- */
-      case (SD_OPERATION_MULTI_BLOCK):
-      {
-        SD_MultiBlockTest();
-        SDCardOperation = SD_OPERATION_END;
-        break;
-      }              
-    }
-  }
-  
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures SDIO IRQ channel.
-  * @param  None
-  * @retval None
-  */
-void NVIC_Configuration(void)
-{
-  NVIC_InitTypeDef NVIC_InitStructure;
-
-  /* Configure the NVIC Preemption Priority Bits */
-  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
-
-  NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
-
-/**
-  * @brief  Tests the SD card erase operation.
-  * @param  None
-  * @retval None
-  */
-void SD_EraseTest(void)
-{
-  /*------------------- Block Erase ------------------------------------------*/
-  if (Status == SD_OK)
-  {
-    /* Erase NumberOfBlocks Blocks of WRITE_BL_LEN(512 Bytes) */
-    Status = SD_Erase(0x00, (BLOCK_SIZE * NUMBER_OF_BLOCKS));
-  }
-
-  if (Status == SD_OK)
-  {
-    Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-
-    /* Wait until end of DMA transfer */
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of erased blocks */
-  if (Status == SD_OK)
-  {
-    EraseStatus = eBuffercmp(Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
-  }
-  
-  if(EraseStatus == PASSED)
-  {
-    STM_EVAL_LEDOn(LED1);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED1);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Tests the SD card Single Blocks operations.
-  * @param  None
-  * @retval None
-  */
-void SD_SingleBlockTest(void)
-{
-  /*------------------- Block Read/Write --------------------------*/
-  /* Fill the buffer to send */
-  Fill_Buffer(Buffer_Block_Tx, BLOCK_SIZE, 0x320F);
-
-  if (Status == SD_OK)
-  {
-    /* Write block of 512 bytes on address 0 */
-    Status = SD_WriteBlock(Buffer_Block_Tx, 0x00, BLOCK_SIZE);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitWriteOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  if (Status == SD_OK)
-  {
-    /* Read block of 512 bytes from address 0 */
-    Status = SD_ReadBlock(Buffer_Block_Rx, 0x00, BLOCK_SIZE);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of written data */
-  if (Status == SD_OK)
-  {
-    TransferStatus1 = Buffercmp(Buffer_Block_Tx, Buffer_Block_Rx, BLOCK_SIZE);
-  }
-  
-  if(TransferStatus1 == PASSED)
-  {
-    STM_EVAL_LEDOn(LED2);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED2);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Tests the SD card Multiple Blocks operations.
-  * @param  None
-  * @retval None
-  */
-void SD_MultiBlockTest(void)
-{
-  /*--------------- Multiple Block Read/Write ---------------------*/
-  /* Fill the buffer to send */
-  Fill_Buffer(Buffer_MultiBlock_Tx, MULTI_BUFFER_SIZE, 0x0);
-
-  if (Status == SD_OK)
-  {
-    /* Write multiple block of many bytes on address 0 */
-    Status = SD_WriteMultiBlocks(Buffer_MultiBlock_Tx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitWriteOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  if (Status == SD_OK)
-  {
-    /* Read block of many bytes from address 0 */
-    Status = SD_ReadMultiBlocks(Buffer_MultiBlock_Rx, 0x00, BLOCK_SIZE, NUMBER_OF_BLOCKS);
-    /* Check if the Transfer is finished */
-    Status = SD_WaitReadOperation();
-    while(SD_GetStatus() != SD_TRANSFER_OK);
-  }
-
-  /* Check the correctness of written data */
-  if (Status == SD_OK)
-  {
-    TransferStatus2 = Buffercmp(Buffer_MultiBlock_Tx, Buffer_MultiBlock_Rx, MULTI_BUFFER_SIZE);
-  }
-  
-  if(TransferStatus2 == PASSED)
-  {
-    STM_EVAL_LEDOn(LED3);
-  }
-  else
-  {
-    STM_EVAL_LEDOff(LED3);
-    STM_EVAL_LEDOn(LED4);    
-  }
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint32_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-/**
-  * @brief  Fills buffer with user predefined data.
-  * @param  pBuffer: pointer on the Buffer to fill
-  * @param  BufferLength: size of the buffer to fill
-  * @param  Offset: first value to fill on the Buffer
-  * @retval None
-  */
-void Fill_Buffer(uint8_t *pBuffer, uint32_t BufferLength, uint32_t Offset)
-{
-  uint16_t index = 0;
-
-  /* Put in global buffer same values */
-  for (index = 0; index < BufferLength; index++)
-  {
-    pBuffer[index] = index + Offset;
-  }
-}
-
-/**
-  * @brief  Checks if a buffer has all its values are equal to zero.
-  * @param  pBuffer: buffer to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer values are zero
-  *         FAILED: At least one value from pBuffer buffer is different from zero.
-  */
-TestStatus eBuffercmp(uint8_t* pBuffer, uint32_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    /* In some SD Cards the erased state is 0xFF, in others it's 0x00 */
-    if ((*pBuffer != 0xFF) && (*pBuffer != 0x00))
-    {
-      return FAILED;
-    }
-
-    pBuffer++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c
deleted file mode 100644
index 769c6d3..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SDIO/uSDCard/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SDIO/uSDCard/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
deleted file mode 100644
index ef642cd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/main.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/CRC/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_CRC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define BufferSize  32
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SPI_InitTypeDef  SPI_InitStructure;
-uint16_t SPI1_Buffer_Tx[BufferSize] = {0x0102, 0x0304, 0x0506, 0x0708, 0x090A, 0x0B0C,
-                                  0x0D0E, 0x0F10, 0x1112, 0x1314, 0x1516, 0x1718,
-                                  0x191A, 0x1B1C, 0x1D1E, 0x1F20, 0x2122, 0x2324,
-                                  0x2526, 0x2728, 0x292A, 0x2B2C, 0x2D2E, 0x2F30,
-                                  0x3132, 0x3334, 0x3536, 0x3738, 0x393A, 0x3B3C,
-                                  0x3D3E, 0x3F40};
-uint16_t SPI2_Buffer_Tx[BufferSize] = {0x5152, 0x5354, 0x5556, 0x5758, 0x595A, 0x5B5C,
-                                  0x5D5E, 0x5F60, 0x6162, 0x6364, 0x6566, 0x6768,
-                                  0x696A, 0x6B6C, 0x6D6E, 0x6F70, 0x7172, 0x7374,
-                                  0x7576, 0x7778, 0x797A, 0x7B7C, 0x7D7E, 0x7F80,
-                                  0x8182, 0x8384, 0x8586, 0x8788, 0x898A, 0x8B8C,
-                                  0x8D8E, 0x8F90};
-uint16_t SPI1_Buffer_Rx[BufferSize], SPI2_Buffer_Rx[BufferSize];
-uint32_t TxIdx = 0, RxIdx = 0;
-__IO uint16_t CRC1Value = 0, CRC2Value = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED;
-
-/* Private functions ---------------------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength);
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System clocks configuration ---------------------------------------------*/
-  RCC_Configuration();
-
-  /* GPIO configuration ------------------------------------------------------*/
-  GPIO_Configuration();
-
-  /* SPI1 configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-  SPI_InitStructure.SPI_CRCPolynomial = 7;
-  SPI_Init(SPI1, &SPI_InitStructure);
-
-  /* SPI2 configuration ------------------------------------------------------*/
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_Init(SPI2, &SPI_InitStructure);
-
-  /* Enable SPI1 CRC calculation */
-  SPI_CalculateCRC(SPI1, ENABLE);
-  /* Enable SPI2 CRC calculation */
-  SPI_CalculateCRC(SPI2, ENABLE);
-
-  /* Enable SPI1 */
-  SPI_Cmd(SPI1, ENABLE);
-  /* Enable SPI2 */
-  SPI_Cmd(SPI2, ENABLE);
-
-  /* Transfer procedure */
-  while (TxIdx < BufferSize - 1)
-  {
-    /* Wait for SPI1 Tx buffer empty */
-    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
-    /* Send SPI2 data */
-    SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
-    /* Send SPI1 data */
-    SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx++]);
-    /* Wait for SPI2 data reception */
-    while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPI2 received data */
-    SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
-    /* Wait for SPI1 data reception */
-    while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-    /* Read SPI1 received data */
-    SPI1_Buffer_Rx[RxIdx++] = SPI_I2S_ReceiveData(SPI1);
-  }
-
-  /* Wait for SPI1 Tx buffer empty */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
-  /* Wait for SPI2 Tx buffer empty */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
-
-  /* Send last SPI2_Buffer_Tx data */
-  SPI_I2S_SendData(SPI2, SPI2_Buffer_Tx[TxIdx]);
-  /* Enable SPI2 CRC transmission */
-  SPI_TransmitCRC(SPI2);
-  /* Send last SPI1_Buffer_Tx data */
-  SPI_I2S_SendData(SPI1, SPI1_Buffer_Tx[TxIdx]);
-  /* Enable SPI1 CRC transmission */
-  SPI_TransmitCRC(SPI1);
-
-  /* Wait for SPI1 last data reception */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Read SPI1 last received data */
-  SPI1_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI1);
-
-  /* Wait for SPI2 last data reception */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Read SPI2 last received data */
-  SPI2_Buffer_Rx[RxIdx] = SPI_I2S_ReceiveData(SPI2);
-
-  /* Wait for SPI1 data reception: CRC transmitted by SPI2 */
-  while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
-  /* Wait for SPI2 data reception: CRC transmitted by SPI1 */
-  while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET);
-
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(SPI2_Buffer_Rx, SPI1_Buffer_Tx, BufferSize);
-  TransferStatus2 = Buffercmp(SPI1_Buffer_Rx, SPI2_Buffer_Tx, BufferSize);
-  /* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
-     are correct */
-  /* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
-     are different */
-
-  /* Test on the SPI1 CRC Error flag */
-  if ((SPI_I2S_GetFlagStatus(SPI1, SPI_FLAG_CRCERR)) == SET)
-  {
-    TransferStatus2 = FAILED;
-  }
-
-  /* Test on the SPI2 CRC Error flag */
-  if ((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_CRCERR)) == SET)
-  {
-    TransferStatus1 = FAILED;
-  }
-
-  /* Read SPI1 received CRC value */
-  CRC1Value = SPI_I2S_ReceiveData(SPI1);
-  /* Read SPI2 received CRC value */
-  CRC2Value = SPI_I2S_ReceiveData(SPI2);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{
-  /* PCLK2 = HCLK/2 */
-  RCC_PCLK2Config(RCC_HCLK_Div2);
-
-  /* Enable peripheral clocks --------------------------------------------------*/
-  /* GPIOA, GPIOB and SPI1 clock enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_SPI1, ENABLE);
-
-  /* SPI2 Periph clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure SPI1 pins: SCK, MISO and MOSI ---------------------------------*/
-  /* Confugure SCK and MOSI pins as Alternate Function Push Pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  /* Confugure MISO pin as Input Floating  */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-  
-  /* Configure SPI2 pins: SCK, MISO and MOSI ---------------------------------*/
-  /* Confugure SCK and MOSI pins as Input Floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-  /* Confugure MISO pin as Alternate Function Push Pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
- 
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint16_t* pBuffer1, uint16_t* pBuffer2, uint16_t BufferLength)
-{
-  while (BufferLength--)
-  {
-    if (*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c
deleted file mode 100644
index 74631fd..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/CRC/stm32f10x_it.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/CRC/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup SPI_CRC
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h
deleted file mode 100644
index 352148a..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/DMA/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/DMA/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c
deleted file mode 100644
index e70492d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/FullDuplex_SoftNSS/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/FullDuplex_SoftNSS/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt
deleted file mode 100644
index 4c6c1da..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/readme.txt
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
-  @page SPI_FLASH SPI SPI_FLASH example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    SPI/SPI_FLASH/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the SPI SPI_FLASH example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a basic example of how to use the SPI firmware library
-and an associate SPI FLASH driver to communicate with an M25P64 or M25P128 FLASH.
-
-The first step consist in reading the SPI Flash ID. A comparison between the ID 
-read from SPI flash and the expected one is done and LED1 is turned on in case
-of success otherwise LED2 is turned on.  
-
-Using this driver the program performs an erase of the sector to be accessed, a 
-write of a Tx_Buffer, defined in the main.c file, to the memory followed by a read
-of the written data. Then data read from the memory stored in the Rx_Buffer are
-compared with the expected values of the Tx_Buffer. The result of this comparison
-is stored in the "TransferStatus1" variable.
-
-A second erase of the same sector is done at the end, and a test is done to be
-sure that all the data written there are erased further to the sector erase. All
-the data location are read and checked with 0xFF value. The result of this test
-is stored in "TransferStatus2" variable which is FAILED in case of error.
-
-The SPI1 is configured as Master with an 8-bit data size. The SPI1 baudrate 
-is set to 18 Mbit/s (for Value line devices the baudrate is set to 12 Mbit/s).
-The FLASH_WriteAddress and the FLASH_ReadAddress where the program start the write 
-and the read operations are defined in the main.c file. 
-
-
-@par Directory contents 
-
-  - SPI/SPI_FLASH/stm32f10x_conf.h     Library Configuration file
-  - SPI/SPI_FLASH/stm32f10x_it.c       Interrupt handlers
-  - SPI/SPI_FLASH/stm32f10x_it.h       Header for stm32f10x_it.c
-  - SPI/SPI_FLASH/main.c               Main program
-  - SPI/SPI_FLASH/system_stm32f10x.c   STM32F10x system source file   
-
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density 
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210E-EVAL 
-    (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) evaluation
-    boards and can be easily tailored to any other supported device 
-    and development board.
-    This example can't be tested with STM3210C-EVAL (Connectivity Line)
-    evaluation board (no SPI FLASH available).
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in stm32_eval.h file.
-
-  - STM32100E-EVAL Set-up 
-    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
-    - M25P128 FLASH is already available on this board.
-@note
-  - The SPI FLASH example is only working on STM32100E-EVAL Rev B.
-        
-  - STM32100B-EVAL Set-up  
-    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
-    - M25P128 FLASH is already available on this board.
-    
-  - STM3210E-EVAL Set-up 
-    - Use LED1 and LED2 connected respectively to PF.06 and PF.07 pins
-    - M25P64 FLASH is already available on this board.
-    @note The jumper 14 (USB Disconnect) must be set in position 1<->2 in order
-          to not interfere with SPI2 MISO pin PB14.
-      
-  - STM3210B-EVAL Set-up  
-    - Use LED1 and LED2 connected respectively to PC.06 and PC.07 pins
-    - M25P64 FLASH is already available on this board.
-
-		  
-  - Other platform Set-up
-    - Use STM3210B-EVAL hardware configuration defines. 
-    - Connect LED1 and LED2 respectively to PD.07 and PD.13 pins
-    - Connect both SPI1 and SPI FLASH pins as following:
-      - Connect SPI1_NSS (PA.04) pin to SPI Flash chip select (pin1)
-      - Connect SPI1_SCLK (PA.05) pin to SPI Flash serial clock (pin6)
-      - Connect SPI1_MISO (PA.06) pin to SPI Flash serial data output (pin2)
-      - Connect SPI1_MOSI (PA.07) pin to SPI Flash serial data input (pin5)
-      - Connect SPI Flash Write Protect (pin3) to Vdd
-      - Connect SPI Flash Hold (pin7) to Vdd
-      - Connect SPI Flash Vcc (pin8) to Vdd
-      - Connect SPI Flash Vss (pin4) to Vss
-
-
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-   
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c
deleted file mode 100644
index b8b6cd7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/SPI_FLASH/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/SPI_FLASH/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 75867c9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file SPI/Simplex_Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c
deleted file mode 100644
index 73a619d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/SPI/Simplex_Interrupt/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    SPI/Simplex_Interrupt/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c
deleted file mode 100644
index 3725d4d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *         This file provides template for all exceptions handler and
-  *         peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_ComplementarySignals
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h
deleted file mode 100644
index b4e5a70..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/ComplementarySignals/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/ComplementarySignals/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h
deleted file mode 100644
index a1b5c9d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/DMABurst/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/DMABurst/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c
deleted file mode 100644
index 4b41133..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/InputCapture/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/InputCapture/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h
deleted file mode 100644
index e93a14c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c
deleted file mode 100644
index 623bf36..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/OnePulse/stm32f10x_it.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/OnePulse/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *        This file provides template for all exceptions handler and 
-  *        peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_OnePulse
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {}
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c
deleted file mode 100644
index 199efb6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/main.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup TIM_Parallel_Synchro
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
-TIM_OCInitTypeDef  TIM_OCInitStructure;
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* GPIO Configuration */
-  GPIO_Configuration();
-
-  /* Timers synchronisation in parallel mode ----------------------------
-     1/TIM2 is configured as Master Timer:
-     - PWM Mode is used
-     - The TIM2 Update event is used as Trigger Output  
-     2/TIM3 and TIM4 are slaves for TIM2,
-     - PWM Mode is used
-     - The ITR1(TIM2) is used as input trigger for both slaves
-     - Gated mode is used, so starts and stops of slaves counters
-      are controlled by the Master trigger output signal(update event).
-
-  * For Low-density, Medium-density, High-density and Connectivity line devices:
-     The TIMxCLK is fixed to 72 MHz, the TIM2 counter clock is 72 MHz.
-     The Master Timer TIM2 is running at 281.250 KHz and the duty cycle
-     is equal to 25%
-     The TIM3 is running:
-     - At (TIM2 frequency)/ (TIM3 period + 1) = 28.125 KHz and a duty cycle
-     equal to TIM3_CCR1/(TIM3_ARR + 1) = 30%
-     The TIM4 is running:
-     - At (TIM2 frequency)/ (TIM4 period + 1) = 56.250 KHz and a duty cycle
-     equal to TIM4_CCR1/(TIM4_ARR + 1) = 60%
-     
-  * For Value line devices:
-     The TIMxCLK is fixed to 24 MHz, the TIM2 counter clock is 24 MHz.
-     TIM2 frequency = 93.750 KHz,
-     TIM3 frequency = 23.437 KHz,
-     TIM4 frequency = 18.75 KHz     
-  -------------------------------------------------------------------- */
-
-  /* Time base configuration */
-  TIM_TimeBaseStructure.TIM_Period = 255;
-  TIM_TimeBaseStructure.TIM_Prescaler = 0;
-  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
-  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
-
-  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 9;
-  TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
-
-  TIM_TimeBaseStructure.TIM_Period = 4;
-  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
-
-  /* Master Configuration in PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 64;
-  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
-
-  TIM_OC1Init(TIM2, &TIM_OCInitStructure);
-
-  /* Select the Master Slave Mode */
-  TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);
-
-  /* Master Mode selection */
-  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);
-
-  /* Slaves Configuration: PWM1 Mode */
-  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-  TIM_OCInitStructure.TIM_Pulse = 3;
-
-  TIM_OC1Init(TIM3, &TIM_OCInitStructure);
-
-  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
-
-  /* Slave Mode selection: TIM3 */
-  TIM_SelectSlaveMode(TIM3, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM3, TIM_TS_ITR1);
-  
-  /* Slave Mode selection: TIM4 */
-  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Gated);
-  TIM_SelectInputTrigger(TIM4, TIM_TS_ITR1);
-  
-  /* TIM enable counter */
-  TIM_Cmd(TIM3, ENABLE);
-  TIM_Cmd(TIM2, ENABLE);
-  TIM_Cmd(TIM4, ENABLE);
-
-  while (1)
-  {}
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{  
-  /* TIM2, TIM3 and TIM4 clock enable */
-  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3 |
-                         RCC_APB1Periph_TIM4, ENABLE);
-
-  /* GPIOA, GPIOB, GPIOC and AFIO clocks enable */
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
-                         RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
-}
-
-/**
-  * @brief  Configure the GPIO Pins.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef STM32F10X_CL
-  /*GPIOB Configuration:  PC6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_6 ;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-  GPIO_PinRemapConfig(GPIO_FullRemap_TIM3, ENABLE);	
-
-#else
-/* GPIOA Configuration: PA6(TIM3 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-#endif
-  /* GPIOA Configuration: PA0(TIM2 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  /* GPIOB Configuration: PB6(TIM4 CH1) as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-
-  GPIO_Init(GPIOB, &GPIO_InitStructure);
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  while (1)
-  {}
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h
deleted file mode 100644
index dd0ad2d..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/Parallel_Synchro/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/Parallel_Synchro/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h
deleted file mode 100644
index 2dfb346..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/TIM/TIM9_OCToggle/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    TIM/TIM9_OCToggle/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c
deleted file mode 100644
index a55707c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HalfDuplex/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HalfDuplex/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h
deleted file mode 100644
index 9bb440b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/HyperTerminal_HwFlowControl/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h
deleted file mode 100644
index b0f39c6..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/platform_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/platform_config.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Evaluation board specific configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __PLATFORM_CONFIG_H
-#define __PLATFORM_CONFIG_H
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line corresponding to the STMicroelectronics evaluation board
-   used to run the example */
-#if !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL) &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32100B_EVAL) &&  !defined (USE_STM32100E_EVAL)
- //#define USE_STM32100B_EVAL  
- //#define USE_STM3210B_EVAL
- //#define USE_STM3210E_EVAL
- //#define USE_STM3210C_EVAL
- #define USE_STM32100E_EVAL 
-#endif
-
-/* Define the STM32F10x hardware depending on the used evaluation board */
-#ifdef USE_STM3210B_EVAL
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-    
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-    
-#elif defined (USE_STM3210E_EVAL) || defined (USE_STM32100E_EVAL)
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-  
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOA
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTz_RxPin             GPIO_Pin_3
-  #define USARTz_TxPin             GPIO_Pin_2
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-  
-#elif defined USE_STM3210C_EVAL
-
-  #define USARTy                   USART2
-  #define USARTy_GPIO              GPIOD
-  #define USARTy_CLK               RCC_APB1Periph_USART2
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTy_RxPin             GPIO_Pin_6
-  #define USARTy_TxPin             GPIO_Pin_5
-  #define USARTy_IRQn              USART2_IRQn
-  #define USARTy_IRQHandler        USART2_IRQHandler
-  
-  #define USARTz                   USART3
-  #define USARTz_GPIO              GPIOC
-  #define USARTz_CLK               RCC_APB1Periph_USART3
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOC
-  #define USARTz_RxPin             GPIO_Pin_11
-  #define USARTz_TxPin             GPIO_Pin_10
-  #define USARTz_IRQn              USART3_IRQn
-  #define USARTz_IRQHandler        USART3_IRQHandler
-  
-#elif defined USE_STM32100B_EVAL
-
-  #define USARTy                   USART1
-  #define USARTy_GPIO              GPIOA
-  #define USARTy_CLK               RCC_APB2Periph_USART1
-  #define USARTy_GPIO_CLK          RCC_APB2Periph_GPIOA
-  #define USARTy_RxPin             GPIO_Pin_10
-  #define USARTy_TxPin             GPIO_Pin_9
-  #define USARTy_IRQn              USART1_IRQn
-  #define USARTy_IRQHandler        USART1_IRQHandler
-    
-  #define USARTz                   USART2
-  #define USARTz_GPIO              GPIOD
-  #define USARTz_CLK               RCC_APB1Periph_USART2
-  #define USARTz_GPIO_CLK          RCC_APB2Periph_GPIOD
-  #define USARTz_RxPin             GPIO_Pin_6
-  #define USARTz_TxPin             GPIO_Pin_5
-  #define USARTz_IRQn              USART2_IRQn
-  #define USARTz_IRQHandler        USART2_IRQHandler
-   
-#endif /* USE_STM3210B_EVAL */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __PLATFORM_CONFIG_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h
deleted file mode 100644
index 96b210c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Interrupt/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Interrupt/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c
deleted file mode 100644
index 99474d7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Receive/system_stm32f10x.c
+++ /dev/null
@@ -1,1094 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Receive/system_stm32f10x.c
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f10x_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
-  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f10x_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F10x_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f10x.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Defines
-  * @{
-  */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
-   frequency (after reset the HSI is used as SYSCLK source)
-   
-   IMPORTANT NOTE:
-   ============== 
-   1. After each device reset the HSI is used as System clock source.
-
-   2. Please make sure that the selected System clock doesn't exceed your device's
-      maximum frequency.
-      
-   3. If none of the define below is enabled, the HSI is used as System clock
-    source.
-
-   4. The System clock configuration functions provided within this file assume that:
-        - For Low, Medium and High density Value line devices an external 8MHz 
-          crystal is used to drive the System clock.
-        - For Low, Medium and High density devices an external 8MHz crystal is
-          used to drive the System clock.
-        - For Connectivity line devices an external 25MHz crystal is used to drive
-          the System clock.
-     If you are using different crystal you have to adapt those functions accordingly.
-    */
-    
-#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
-#else
-/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz  24000000 */ 
-/* #define SYSCLK_FREQ_36MHz  36000000 */
-/* #define SYSCLK_FREQ_48MHz  48000000 */
-/* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
-     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-/* #define DATA_IN_ExtSRAM */
-#endif
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-  static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F10x_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#ifndef STM32F10X_CL
-  RCC->CFGR &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR &= (uint32_t)0xF0FF0000;
-#endif /* STM32F10X_CL */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
-#ifdef STM32F10X_CL
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= (uint32_t)0xEBFFFFFF;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000;
-#endif /* STM32F10X_CL */
-    
-#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
-  /* Configure the Flash Latency cycles and enable prefetch buffer */
-  SetSysClock();
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
-
-#ifdef  STM32F10X_CL
-  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
-#endif /* STM32F10X_CL */
-
-#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-  uint32_t prediv1factor = 0;
-#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#ifndef STM32F10X_CL      
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
- #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18;
-      
-      if (pllmull != 0x0D)
-      {
-         pllmull += 2;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13 / 2; 
-      }
-            
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        
-        if (prediv1source == 0)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F10X_CL */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-  SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#endif
- 
- /* If none of the define above is enabled, the HSI is used as System clock
-    source (default after reset) */ 
-}
-
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
-  * 	      This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-  required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114;
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
-  RCC->APB2ENR = 0x000001E0;
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BB;  
-  GPIOD->CRH = 0xBBBBBBBB;
-
-  GPIOE->CRL = 0xB44444BB;  
-  GPIOE->CRH = 0xBBBBBBBB;
-
-  GPIOF->CRL = 0x44BBBBBB;  
-  GPIOF->CRH = 0xBBBB4444;
-
-  GPIOG->CRL = 0x44BBBBBB;  
-  GPIOG->CRH = 0x44444B44;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4] = 0x00001011;
-  FSMC_Bank1->BTCR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-
-#ifndef STM32F10X_CL
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#else
-    if (HSE_VALUE <= 24000000)
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-	}
-	else
-	{
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-	}
-#endif /* STM32F10X_CL */
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSE as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 0 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
-#endif
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }   
-#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
-#else    
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo36(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-
-	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-#else    
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 1 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-    
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL6); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL7); 
-#else     
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
-
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  } 
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 
-  *          and PCLK1 prescalers. 
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-    /* Flash 2 wait state */
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
-
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK2 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
-    
-    /* PCLK1 = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
-
-#ifdef STM32F10X_CL
-    /* Configure PLLs ------------------------------------------------------*/
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
-        
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
-  
-    /* Enable PLL2 */
-    RCC->CR |= RCC_CR_PLL2ON;
-    /* Wait till PLL2 is ready */
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
-    {
-    }
-    
-   
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
-                            RCC_CFGR_PLLMULL9); 
-#else    
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
-                                        RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
-#endif /* STM32F10X_CL */
-
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-    
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }
-}
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h
deleted file mode 100644
index d40f863..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/IrDA/Transmit/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/IrDA/Transmit/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt
deleted file mode 100644
index 42a715c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/MultiProcessor/readme.txt
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
-  @page USART_MultiProcessor USART Multi Processor example
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    USART/MultiProcessor/readme.txt 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Description of the USART Multi Processor example.
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-   @endverbatim
-
-@par Example Description 
-
-This example provides a description of how to use the USART in multi-processor mode.
-USARTy and USARTz can be USART1 and USART2 or USART2 and USART3 respectively, 
-depending on the STMicroelectronics EVAL board you are using.
-
-First, the USARTy and USARTz address are set to 0x1 and 0x2. The USARTy send 
-continuously the character 0x33 to the USARTz. The USARTz toggle LED1, LED2, LED3 
-and LED4 pins while receiving 0x33.
-
-When a falling edge is applied on BUTTON_KEY EXTI line, an interrupt is generated
-and in the EXTI9_5_IRQHandler routine, the USARTz is entered in mute mode and still
-in this mode (no LED toggling) until a rising edge is applied on BUTTON_WAKEUP 
-EXTI Line 0.
-In this interrupt routine the USARTy send the character of address mark (0x102)
-to wakeup USARTz. The LED restart toggling.
-
-USARTy and USARTz configured as follow:
-  - BaudRate = 9600 baud  
-  - Word Length = 9 Bits
-  - One Stop Bit
-  - No parity
-  - Hardware flow control disabled (RTS and CTS signals)
-  - Receive and transmit enabled
-
-@par Directory contents 
-
-  - USART/MultiProcessor/platform_config.h    Evaluation board specific configuration file
-  - USART/MultiProcessor/stm32f10x_conf.h     Library Configuration file
-  - USART/MultiProcessor/stm32f10x_it.h       Interrupt handlers header file
-  - USART/MultiProcessor/stm32f10x_it.c       Interrupt handlers
-  - USART/MultiProcessor/main.c               Main program
-  - USART/MultiProcessor/system_stm32f10x.c   STM32F10x system source file
-  
-@par Hardware and Software environment 
-
-  - This example runs on STM32F10x Connectivity line, High-Density, High-Density 
-    Value line, Medium-Density, XL-Density, Medium-Density Value line, Low-Density 
-    and Low-Density Value line Devices.
-  
-  - This example has been tested with STMicroelectronics STM32100E-EVAL (High-Density
-    Value line), STM32100B-EVAL (Medium-Density Value line), STM3210C-EVAL (Connectivity line), 
-    STM3210E-EVAL (High-Density and XL-Density) and STM3210B-EVAL (Medium-Density) 
-    evaluation boards and can be easily tailored to any other supported device 
-    and development board.
-    To select the STMicroelectronics evaluation board used to run the example, 
-    uncomment the corresponding line in USART/MultiProcessor/platform_config.h or stm32_eval.h file.
-
-  - STM32100E-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN5 and CN10.
-    - Use Key push-button connected to pin PG.08 (EXTI Line8)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF.07, 
-      PF.08 and PF.09 pins
-      @note Make sure that jumper JP5 is not open.
-            Make sure that jumper JP4 is in position 1<-->2.
-      
-  - STM32100B-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN9 and CN10.
-      @note In this case USART2 Tx and Rx pins are remapped by software on 
-            PD.05 and PD.06 respectively. 
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, 
-      PC.08 and PC.09 pins
-
-  - STM3210C-EVAL Set-up 
-    - Connect USART2 Tx pin (PD.05) to USART3 Rx pin (PC.11)
-    - Connect USART2 Rx pin (PD.06) to USART3 Tx pin	(PC.10)
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0) 
-    - Use LED1, LED2, LED3 and LED4 connected respectively to PD.07, PD.13, PF.03
-      and PD.04 pins   
-      @note In this case USART3 Tx and Rx pins are remapped by software.
-            Make sure that jumpers JP19 and JP18 are open.
-            Make sure that the Jumper 14 (JP14) is in position 2<-->3. 
-    
-  - STM3210E-EVAL Set-up 
-    - Connect a null-modem female/female RS232 cable between CN12 and CN8.
-    - Use Key push-button connected to pin PG.08 (EXTI Line8)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PF.06, PF0.7, PF.08
-      and PF.09 pins
-      @note Make sure that the Jumper 4 (JP4) is in position 1<-->2. 
-
-  - STM3210B-EVAL Set-up  
-    - Connect a null-modem female/female RS232 cable between CN5 and CN6.
-      @note In this case USART2 Tx and Rx pins are remapped by software on 
-            PD.05 and PD.06 respectively. 
-    - Use Key push-button connected to pin PB.09 (EXTI Line9)
-    - Use Wakeup push-button connected to pin PA.00 (EXTI Line0)
-    - Use LED1, LED2, LED3 and LED4 leds connected respectively to PC.06, PC.07, PC.08
-      and PC.09 pins             
-   
-@par How to use it ? 
-
-In order to make the program work, you must do the following :
- - Copy all source files from this example folder to the template folder under
-   Project\STM32F10x_StdPeriph_Template
- - Open your preferred toolchain 
- - Rebuild all files and load your image into target memory
- - Run the example 
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-    
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c
deleted file mode 100644
index eca689b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and peripherals
-  *          interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Polling
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h
deleted file mode 100644
index d3f6cae..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Polling/stm32f10x_it.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Polling/stm32f10x_it.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_IT_H
-#define __STM32F10x_IT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#endif /* __STM32F10x_IT_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h
deleted file mode 100644
index 8e6a316..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Printf/stm32f10x_conf.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
-  ******************************************************************************
-  * @file USART/Printf/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
deleted file mode 100644
index e00afbe..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/main.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/main.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "platform_config.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Examples
-  * @{
-  */
-
-/** @addtogroup USART_Synchronous
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-typedef enum {FAILED = 0, PASSED = !FAILED} TestStatus;
-
-/* Private define ------------------------------------------------------------*/
-#define TxBufferSize1   (countof(TxBuffer1) - 1)
-#define TxBufferSize2   (countof(TxBuffer2) - 1)
-#define DYMMY_BYTE      0x00
-
-/* Private macro -------------------------------------------------------------*/
-#define countof(a)   (sizeof(a) / sizeof(*(a)))
-
-/* Private variables ---------------------------------------------------------*/
-USART_InitTypeDef USART_InitStructure;
-USART_ClockInitTypeDef USART_ClockInitStructure; 
-
-uint8_t TxBuffer1[] = "USART Synchronous Example: USARTy -> SPIy using TXE and RXNE Flags";
-uint8_t TxBuffer2[] = "USART Synchronous Example: SPIy -> USARTy using TXE and RXNE Flags";
-uint8_t RxBuffer1[TxBufferSize2];
-uint8_t RxBuffer2[TxBufferSize1];
-__IO uint8_t NbrOfDataToRead1 = TxBufferSize2;
-__IO uint8_t NbrOfDataToRead2 = TxBufferSize1;
-__IO uint8_t TxCounter1 = 0, RxCounter1 = 0;
-__IO uint8_t TxCounter2 = 0, RxCounter2 = 0;
-volatile TestStatus TransferStatus1 = FAILED, TransferStatus2 = FAILED; 
-
-/* Private function prototypes -----------------------------------------------*/
-void RCC_Configuration(void);
-void GPIO_Configuration(void);
-void SPI_Configuration(void);
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @brief  Main program
-  * @param  None
-  * @retval None
-  */
-int main(void)
-{
-  /*!< At this stage the microcontroller clock setting is already configured, 
-       this is done through SystemInit() function which is called from startup
-       file (startup_stm32f10x_xx.s) before to branch to application main.
-       To reconfigure the default setting of SystemInit() function, refer to
-       system_stm32f10x.c file
-     */     
-       
-  /* System Clocks Configuration */
-  RCC_Configuration();
-
-  /* Configure the GPIO ports */
-  GPIO_Configuration();
-
-  /* Configure the SPI */
-  SPI_Configuration();
-
-/* USARTy configuration ------------------------------------------------------*/
-  /* USARTy configured as follow:
-        - BaudRate = 115200 baud  
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-        - USART Clock Enabled
-        - USART CPOL: Clock is active High
-        - USART CPHA: Data is captured on the second edge 
-        - USART LastBit: The clock pulse of the last data bit is output to 
-                         the SCLK pin
-  */
-  USART_ClockInitStructure.USART_Clock = USART_Clock_Enable;
-  USART_ClockInitStructure.USART_CPOL = USART_CPOL_High;
-  USART_ClockInitStructure.USART_CPHA = USART_CPHA_2Edge;
-  USART_ClockInitStructure.USART_LastBit = USART_LastBit_Enable;
-  USART_ClockInit(USARTy, &USART_ClockInitStructure);
-
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No ;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_Init(USARTy, &USART_InitStructure);
-  
-  /* Configure the USARTy */
-  USART_Init(USARTy, &USART_InitStructure);
-
-  /* Enable the USARTy */
-  USART_Cmd(USARTy, ENABLE);
-
-  while(NbrOfDataToRead2--)
-  {
-    /* Write one byte in the USARTy Transmit Data Register */
-    USART_SendData(USARTy, TxBuffer1[TxCounter1++]);
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
-    {
-    }
-    /* Wait the byte is entirely received by SPIy */  
-    while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer2 */
-    RxBuffer2[RxCounter2++] = SPI_I2S_ReceiveData(SPIy);
-  }
-
-  /* Clear the USARTy Data Register */
-  USART_ReceiveData(USARTy);
-
-  while(NbrOfDataToRead1--)
-  {
-    /* Wait until end of transmit */
-    while(SPI_I2S_GetFlagStatus(SPIy, SPI_I2S_FLAG_TXE)== RESET)
-    {
-    }
-    /* Write one byte in the SPIy Transmit Data Register */
-    SPI_I2S_SendData(SPIy, TxBuffer2[TxCounter2++]);
-
-    /* Send a Dummy byte to generate clock to slave */ 
-    USART_SendData(USARTy, DYMMY_BYTE);
-    /* Wait until end of transmit */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_TC) == RESET)
-    {
-    }
-    /* Wait the byte is entirely received by USARTy */
-    while(USART_GetFlagStatus(USARTy, USART_FLAG_RXNE) == RESET)
-    {
-    }
-    /* Store the received byte in the RxBuffer1 */
-    RxBuffer1[RxCounter1++] = USART_ReceiveData(USARTy);
-  }
-  
-  /* Check the received data with the send ones */
-  TransferStatus1 = Buffercmp(TxBuffer1, RxBuffer2, TxBufferSize1);
-  /* TransferStatus = PASSED, if the data transmitted from USARTy and  
-     received by SPIy are the same */
-  /* TransferStatus = FAILED, if the data transmitted from USARTy and 
-     received by SPIy are different */
-  TransferStatus2 = Buffercmp(TxBuffer2, RxBuffer1, TxBufferSize2);
-  /* TransferStatus = PASSED, if the data transmitted from SPIy and  
-     received by USARTy are the same */
-  /* TransferStatus = FAILED, if the data transmitted from SPIy and 
-     received by USARTy are different */
-
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  Configures the different system clocks.
-  * @param  None
-  * @retval None
-  */
-void RCC_Configuration(void)
-{   
-  /* Enable GPIO clock */
-  RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | SPIy_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
-
-  /* Enable USARTy Clock */
-  RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 
-  /* Enable SPIy Clock */
-  RCC_APB2PeriphClockCmd(SPIy_CLK, ENABLE);    
-}
-
-/**
-  * @brief  Configures the different GPIO ports.
-  * @param  None
-  * @retval None
-  */
-void GPIO_Configuration(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-
-  /* Configure USARTy TX and USARTy CK pins as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = USARTy_TxPin | USARTy_ClkPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-
-  /* Configure SPI1 pins: SCK, MISO and MOSI */
-  GPIO_InitStructure.GPIO_Pin = SPIy_SCKPin | SPIy_MISOPin | SPIy_MOSIPin;
-  GPIO_Init(SPIy_GPIO, &GPIO_InitStructure);
-
-  /* Configure USARTy RX as input floating */
-  GPIO_InitStructure.GPIO_Pin = USARTy_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init(USARTy_GPIO, &GPIO_InitStructure);
-}
-
-/**
-  * @brief  Configures the SPI.
-  * @param  None
-  * @retval None
-  */
-void SPI_Configuration(void)
-{
-  SPI_InitTypeDef SPI_InitStructure;
-
-  SPI_StructInit(&SPI_InitStructure);
-
-  SPI_I2S_DeInit(SPIy);
-
-  /* SPIy Config */
-  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
-  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
-  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
-  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
-  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_LSB;
-  
-  /* Configure SPIy */
-  SPI_Init(SPIy, &SPI_InitStructure);
-
-  /* SPIy enable */
-  SPI_Cmd(SPIy, ENABLE);
-}
-
-/**
-  * @brief  Compares two buffers.
-  * @param  pBuffer1, pBuffer2: buffers to be compared.
-  * @param  BufferLength: buffer's length
-  * @retval PASSED: pBuffer1 identical to pBuffer2
-  *         FAILED: pBuffer1 differs from pBuffer2
-  */
-TestStatus Buffercmp(uint8_t* pBuffer1, uint8_t* pBuffer2, uint16_t BufferLength)
-{
-  while(BufferLength--)
-  {
-    if(*pBuffer1 != *pBuffer2)
-    {
-      return FAILED;
-    }
-
-    pBuffer1++;
-    pBuffer2++;
-  }
-
-  return PASSED;
-}
-
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t* file, uint32_t line)
-{ 
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-
-  /* Infinite loop */
-  while (1)
-  {
-  }
-}
-
-#endif
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h
deleted file mode 100644
index 317f17f..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Examples/USART/Synchronous/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    USART/Synchronous/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt
deleted file mode 100644
index 1127522..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/EWARM/readme.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
-  @page ewarm EWARM Project Template
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with IAR Embedded Workbench for ARM (EWARM)
-  *          software toolchain (version 5.50 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
- @par Directory contents
-
- - project .ewd/.eww/.ewp: A pre-configured project file with the provided library 
-                           structure that produces an executable image with IAR 
-                           Embedded Workbench.
-                
- - stm32f10x_flash.icf : This file is the IAR Linker configuration file used to 
-                         place program code (readonly) in internal FLASH and data
-                         (readwrite, Stack and Heap)in internal SRAM. 
-                         You can customize this file to your need.                    
-                      
- - stm32f10x_flash_extsram.icf: This file is the IAR Linker configuration file 
-                                used to place program code (readonly) in internal 
-                                FLASH and data (readwrite, Stack and Heap)in 
-                                external SRAM. You can customize this file to your need.  
-                                This file is used only with STM32 High-density devices.
-
- - stm32f10x_nor.icf:  This file is the IAR Linker configuration file used to 
-                       place program code (readonly) in external NOR FLASH and data
-                       (readwrite, Stack and Heap)in internal SRAM. 
-                       You can customize this file to your need. 
-                       This file is used only with STM32 High-density devices.                                           
-
- - stm32f10x_ram.icf:  This file is the IAR Linker configuration file used to 
-                       place program code (readonly) and data (readwrite, Stack 
-                       and Heap)in internal SRAM. 
-                       You can customize this file to your need.                    
-                             
- @par How to use it ?
-
- - Open the Project.eww workspace.
- - In the workspace toolbar select the project config:
-     - STM32100B-EVAL: to configure the project for STM32 Medium-density Value 
-       line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD_VL, USE_STM32100B_EVAL
-           
-     - STM3210C-EVAL: to configure the project for STM32 Connectivity line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
-
-     - STM3210B-EVAL: to configure the project for STM32 Medium-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_MD, USE_STM3210B_EVAL
-
-     - STM3210E-EVAL: to configure the project for STM32 High-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD, USE_STM3210E_EVAL
-
-     - STM3210E-EVAL_XL: to configure the project for STM32 XL-density devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_XL, USE_STM3210E_EVAL
-
-     - STM32100E-EVAL: to configure the project for STM32 High-density Value line devices
-     @note The needed define symbols for this config are already declared in the
-           preprocessor section: USE_STDPERIPH_DRIVER, STM32F10X_HD_VL, USE_STM32100E_EVAL           
-
- - Rebuild all files: Project->Rebuild all
- - Load project image: Project->Debug
- - Run program: Debug->Go(F5)
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 32 and 128 Kbytes.
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes. 
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.      
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk
deleted file mode 100644
index 9ac15b9..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/Settings/link_extsram.lnk
+++ /dev/null
@@ -1,4 +0,0 @@
--d"./settings/stm32f10x_hd_vl_extsram.lsl"
---optimize=0
---map-file-format=2
-$(LinkObjects)
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM32100E-EVAL/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp
deleted file mode 100644
index 4c9ed12..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210B-EVAL/Project.htp
+++ /dev/null
@@ -1,1001 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-
-<!-- ======================================================================= -->
-<!-- ** DON'T EDIT THIS FILE! IT WILL BE AUTOMATICALY GENERATED BY HITOP! ** -->
-<!-- ======================================================================= -->
-
-<HiTOPProject>
-	<Windows>
-		<MDIState RTOS="0" Trace="0" Source="1" Maximized="1" SFRWindow="0" CoverageWindow="0"/>
-		<Window Id="SFRWindow">
-			<SFRDefinitions File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\STM32F103VB.xsfr"/>
-			<WindowState State="Normal"/>
-			<Rectangle State="Normal">
-				<Size cx="497" cy="278"/>
-				<Position x="22" y="22"/>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="615" cy="415"/>
-				<Position x="-4" y="-23"/>
-			</Rectangle>
-		</Window>
-		<Window Id="Disassembly">
-			<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-				<Header Bold="1"/>
-				<Column Id="0" Order="0" Title="State" Width="24" Visible="1" Alignment="LEFT"/>
-				<Column Id="11" Order="1" Title="Address" Visible="1" RelWidth="0.1722848" Alignment="LEFT"/>
-				<Column Id="12" Order="2" Title="OpCode" Visible="1" RelWidth="0.1325498" Alignment="LEFT"/>
-				<Column Id="13" Order="3" Title="Instruction" Visible="1" RelWidth="0.6954638" Alignment="LEFT"/>
-			</List>
-			<Tabs Count="0"/>
-		</Window>
-		<Window Id="Source">
-			<UpdateOnRunning Update="0"/>
-			<WindowState State="Maximized"></WindowState>
-			<Rectangle State="Minimized">
-				<Size cx="160" cy="24"></Size>
-				<Position x="0" y="352"></Position>
-			</Rectangle>
-			<Rectangle State="Normal">
-				<Size cx="830" cy="485"></Size>
-				<Position x="-4" y="-30"></Position>
-			</Rectangle>
-			<Rectangle State="Maximized">
-				<Size cx="844" cy="627"></Size>
-				<Position x="-4" y="-30"></Position>
-			</Rectangle>
-			<Tabs Count="0" Active="0"/>
-		</Window>
-		<Window Id="Watch">
-			<Tabs Sel="0" Count="2">
-				<Tab Pos="0" Title="Locals">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="12" Order="0" Title="Variables" Visible="1" RelWidth="0.3722838" Alignment="LEFT"/>
-						<Column Id="13" Order="1" Title="Value" Visible="1" RelWidth="0.6277578" Alignment="LEFT"/>
-						<Column Id="14" Order="2" Title="Type" Visible="1" RelWidth="0.3856508" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Watch1">
-					<UpdateOnRunning Update="0"/>
-					<DisplayMode Mode="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.1941648" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Expression" Visible="1" RelWidth="0.3000468" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Value" Visible="1" RelWidth="0.5059288" Alignment="LEFT"/>
-						<Watches>
-							<Watch Id="O1" Appl="Project"/>
-							<Watch Id="O2" Appl="Project"/>
-							<Watch Id="O3" Appl="Project"/>
-							<Watch Id="O4" Appl="Project"/>
-						</Watches>
-						<Column Id="14" Order="3" Title="Type" Visible="1" RelWidth="0.3359388" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Memory">
-			<Tabs Sel="0" Count="4">
-				<Tab Pos="0" Title="Mem0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x20004C00" Symbol="_lc_ub_stack"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="94" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Flash">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x08000080" Symbol="0x08000080"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="2" Title="RAM">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x200000E0" Symbol="0x200000E0"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-				<Tab Pos="3" Title="Base">
-					<List Id="" BkColor="16777215" TextColor="0" DisableColSizing="0">
-						<Memory Format="DWORD" SymbolicAddresses="1">
-							<Address Hex="0x00000000" Symbol="_lc_t2_longveneertarget"/>
-						</Memory>
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Address" Width="198" Visible="1" Alignment="RIGHT"/>
-						<Column Id="12" Order="1" Title="Data" Width="302" Visible="1" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="ASCII" Width="142" Visible="1" Alignment="LEFT"/>
-					</List>
-					<UpdateOnRunning Update="0"/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Emulator State">
-			<Tabs>
-				<Tab Pos="0">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500128" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occured" Visible="1" RelWidth="0.1250128" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1">
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="10" Order="0" Title="No" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-						<Column Id="11" Order="1" Title="Id" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="12" Order="2" Title="Counter" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="13" Order="3" Title="Use" Visible="1" RelWidth="0.2500008" Alignment="LEFT"/>
-						<Column Id="14" Order="4" Title="Occurred" Visible="1" RelWidth="0.1250008" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Breakpoint">
-			<Tabs Sel="0">
-				<Tab Pos="0" Title="Code">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500088" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106148" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833418" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560698" Alignment="LEFT"/>
-					</List>
-				</Tab>
-				<Tab Pos="1" Title="Data">
-					<Breaks/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="ID" Visible="1" RelWidth="0.2500018" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.3106078" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Length" Visible="1" RelWidth="0.0833348" Alignment="LEFT"/>
-						<Column Id="16" Order="3" Title="Type" Visible="1" RelWidth="0.3560628" Alignment="LEFT"/>
-					</List>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="TraceFilter">
-			<Tabs>
-				<Tab Pos="0">
-					<Triggers/>
-				</Tab>
-				<Tab Pos="1">
-					<Regions/>
-				</Tab>
-			</Tabs>
-		</Window>
-		<Window Id="Profile">
-			<Tabs>
-				<Tab Pos="0">
-					<UpdateOnRunning Update="0"/>
-					<List Id="" BkColor="16777215" SortAsc="1" SortCol="-1" TextColor="0" DisableColSizing="0">
-						<Header Bold="1"/>
-						<Column Id="11" Order="0" Title="Id" Visible="1" RelWidth="0.2275868" Alignment="LEFT"/>
-						<Column Id="12" Order="1" Title="Address" Visible="1" RelWidth="0.2827598" Alignment="LEFT"/>
-						<Column Id="13" Order="2" Title="Activity" Visible="1" RelWidth="0.4000008" Alignment="LEFT"/>
-						<Column Id="14" Order="3" Title="Time" Visible="1" RelWidth="0.0896558" Alignment="LEFT"/>
-					</List>
-					<State ModeAbsolute="0" UpdateEnabled="0"/>
-				</Tab>
-			</Tabs>
-			<List Id=""/>
-		</Window>
-		<Window Id="FileView" RelativePath="Relative2Project">
-			<ApplFolder Id="Project" State="Expanded">
-				<Folder Id="CMSIS" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\core_cm3.c"/>
-					<File Id="..\..\system_stm32f10x.c"/>
-				</Folder>
-				<Folder Id="Doc" State="Not_Expanded">
-					<File Id=".\readme.txt"/>
-				</Folder>
-				<Folder Id="StdPeriph_Driver" State="Not_Expanded">
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c"/>
-					<File Id="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c"/>
-				</Folder>
-				<Folder Id="STM32_EVAL" State="Not_Expanded">
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\stm3210b_eval_lcd.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\stm32_eval.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_i2c_tsensor.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_flash.c"/>
-					<File Id="..\..\..\..\Utilities\STM32_EVAL\Common\stm32_eval_spi_sd.c"/>
-				</Folder>
-				<Folder Id="User" State="Not_Expanded">
-					<File Id="..\..\main.c"/>
-					<File Id="..\..\stm32f10x_it.c"/>
-				</Folder>
-				<Folder Id="HiTOP" State="Not_Expanded">
-					<File Id=".\cstart_thumb2.asm"/>
-				</Folder>
-				<Folder Id="Source Files" State="Not_Expanded" RelativePath=""/>
-			</ApplFolder>
-		</Window>
-	</Windows>
-	<Version>V5.20</Version>
-	<DebugDevice>
-		<TargetProcessor Id="PARM"/>
-		<Derivative Id="STM32F103VB" File="$(SYSTEMDIR)\Derivatives\ST Microelectronics\.\..\Arm\Default.drv" Vendor="ST Microelectronics">
-			<InternalFlash Count="1">
-				<Device Id="STM32F103VB" Index="0" Manufacturer="ST"></Device>
-			</InternalFlash>
-		</Derivative>
-		<Communication>
-			<Port>USB</Port>
-			<DeviceName>Tantino for Cortex-10083</DeviceName>
-			<PortAddress Value="-2147483648"/>
-			<BaudRate Value="0"/>
-		</Communication>
-		<SystemDir Path="C:\Program Files\Hitex\HiTOP54-CTX\Tantino-Cortex"/>TANTINO_CORTEX_M3
-		<RecentDerivative SWJDP="1" Vendor="ST Microelectronics" ProcType="30" Endianess="0" Derivative="STM32F103VB"/>
-		<ARMConfiguration Id="STM32F103VB" SWJDP="1" Vendor="ST Microelectronics" EMB_ICE="0" Endianes="0" ProcType="30" ETM_EXIST="0" MCUFamily="STM32" RTCK_USED="0" Exceptions="STM32xxx" TRACE_AVAIL="1" DeviceToTest="2" ExtMemoryItf="NO" OnChipRAMAdr="0x20000000" OnChipRAMSize="0x5000" EndianessFixed="1" OnChipFlashAdr="0x8000000" OnChipFlashSize="0x20000" IR_CountBitsOfTD="4" CountDevicesInChain="2" IR_CountBitsBeforeTD="5" IR_CountBitsBehindTD="0"/>
-	</DebugDevice>
-	<StartupScript File=".\Settings\StartupScript.scr" Execute="1" ProjRelative="1"/>
-	<EditorOptions Version="1">
-		<Font lfHeight="-12" lfWeight="400" ColorBack="16777215" ColorText="0" lfCharSet="0" lfQuality="0" lfFaceName="Courier New" lfOutPrecision="0" ColorHiLiteBack="12937777" ColorHiLiteText="16777215" lfClipPrecision="0" lfPitchAndFamily="0"/>
-		<Tabulators Size="4" TabWithSpace="0"/>
-		<Options WideCaret="0" AutoIndent="1" AutoReload="1" HScrollBar="1" VScrollBar="1" LineNumbers="0" VirtualSpace="0" SyntaxColoring="1"/>
-	</EditorOptions>
-	<ConfigurationOptions>
-		<ProcessorSettings>
-			<ProcessorSetting Id="TarResHi" Value="0" Element="    50ms"/>
-			<ProcessorSetting Id="DefMemAc" Value="2" Element="   32bit"/>
-			<ProcessorSetting Id="TarReTAP" Value="0" Element="      no"/>
-			<ProcessorSetting Id="TarResLo" Value="1" Element="   100ms"/>
-			<ProcessorSetting Id="IWDGSTOP" Value="0" Element=" running"/>
-			<ProcessorSetting Id="WWDGSTOP" Value="0" Element=" running"/>
-			<ProcessorSetting Id="TIMER1" Value="0" Element=" running"/>
-			<ProcessorSetting Id="TIMER2" Value="0" Element=" running"/>
-			<ProcessorSetting Id="TIMER3" Value="0" Element=" running"/>
-			<ProcessorSetting Id="TIMER4" Value="0" Element=" running"/>
-			<ProcessorSetting Id="DBGSLEEP" Value="1" Element=" enabled"/>
-			<ProcessorSetting Id="DBGSTOP" Value="1" Element=" enabled"/>
-			<ProcessorSetting Id="DBGSTDBY" Value="1" Element=" enabled"/>
-			<ProcessorSetting Id="BXCAN" Value="0" Element="  active"/>
-		</ProcessorSettings>
-		<EmulatorSettings>
-			<EmulatorSetting Id="TAPClk" Value="6" Element="  6.0MHz"/>
-			<EmulatorSetting Id="TARRESTA" Value="1" Element="     yes"/>
-			<EmulatorSetting Id="BREAKSTA" Value="1" Element="     yes"/>
-			<EmulatorSetting Id="UPDWRCTI" Value="1000" Element=""/>
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-			</Windows>
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-					</DockBars>
-				</Layout>
-			</CommandBars>
-		</Layout>
-	</RecentScreenLayouts>
-	<FlashProgramming RAMBase="0x20000000" RAMLength="0x4000" NumDevices="1" SaveRestoreRAM="0" EnableProgramming="1">
-		<FlashDevice Type="STM32F103VB" Index="0" BusWidth="32" DeviceMode="32" BaseAddress="0x08000000" Manufacturer="ST">
-			<Sectors Count="0"/>
-		</FlashDevice>
-	</FlashProgramming>
-	<Component Id="DataTrace"/>
-	<PowerScale EnableInstrumentation="0"/>
-	<LinkerApplications Count="1" RelPath="1" AutoLoad="0" CurrentIdeApp="Project" AutoDetectChanges="1">
-		<Loader Id="TaskingCED"/>
-		<Application Pos="0" Load="1" AppName="Project" CodeFile=".\objects\Project.htx" LinkerFile=".\objects\Project.abs" CurrentBuild="STM3210B-EVAL">
-			<SymbolLoader ProjRel="1" MessageFile="" NeedsSymprepRun="0">
-				<Options Cache="128" Reload="RELOAD" CmdFile="" DestDir=".\objects\" OnlySym="0" StdCode="" Verbose="1" CtrlFile="" WarnLevel="0">
-					<SourcePath>
-						<Path Text=".\Source\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\Core\CM3\"/>
-						<Path Text="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\src\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\"/>
-						<Path Text="..\..\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\"/>
-						<Path Text=".\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\"/>
-						<Path Text="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\"/>
-						<Path Text="..\..\..\..\Utilities\STM32_EVAL\Common\"/>
-					</SourcePath>
-					<ProcessorSpecific>
-						<Option Text="FW_TYPES"/>
-					</ProcessorSpecific>
-					<DebugModules Include="1"/>
-				</Options>
-			</SymbolLoader>
-			<RTOS Id="" Dll=""/>
-			<BuildConfiguration Id="STM3210B-EVAL" File="" ToolId="IdeTaskingARM" BuildCfgChanged="false">
-				<General OutputPath=".\objects\" TargetName="Project.abs" StopBuildOnError="1">
-					<IncludePath Path="..\..\" Position="0"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\" Position="1"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\STM3210B_EVAL\" Position="2"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\" Position="3"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\CoreSupport\" Position="4"></IncludePath>
-					<IncludePath Path="..\..\..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\" Position="5"></IncludePath>
-					<IncludePath Path="..\..\..\..\Utilities\STM32_EVAL\Common\" Position="6"></IncludePath>
-				</General>
-				<Assembler Options="-co -CARMv7M -Wa-il -Wa-gs -v "></Assembler>
-				<Compiler Defines="USE_STDPERIPH_DRIVER;STM32F10X_MD;USE_STM3210B_EVAL" Options="-co -CARMv7M -Wc--align-composites=n -Wc-O1 -Wc-c99 -Wc-AGx -Wc-ga -Wc-I&quot;$(TARGETDIR)\..\library\inc&quot; -v -Wa-L1 -Wc-w557 -Wc-w505 -Wc-w529 -Wc-w560 -Wc-w523  -Wc-t4  "></Compiler>
-				<Linker File=".\Settings\link.lnk" Options="-Wl-L&quot;$(TOOLDIR)..\lib&quot; -Wl-OcLtXy -CARMv7M  -Wl-lfpthumb  -o&quot;$(TargetDir)$(Target)&quot;  " PostBuild=""></Linker>
-			</BuildConfiguration>
-		</Application>
-	</LinkerApplications>
-	<ScriptBarSettings>
-		<ScriptButton Id="1" File=".\Settings\reset_appl.scr" ButtonText="RESET_APPL" ProjRelative="1"/>
-		<ScriptButton Id="2" File=".\Settings\reset_go_main.scr" ButtonText="RESET_GO_MAIN" ProjRelative="1"/>
-		<ScriptButton Id="3" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="4" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="5" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="6" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="7" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="8" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="9" File="" ButtonText="" ProjRelative="1"/>
-		<ScriptButton Id="10" File="" ButtonText="" ProjRelative="1"/>
-	</ScriptBarSettings>
-</HiTOPProject>
-
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt
deleted file mode 100644
index d6e6324..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/readme.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
-  @page HiTOP5_STM3210E_XL HiTOP Project Template for STM32F10x XL-density devices
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    readme.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This sub directory contains all the user modifiable files needed
-  *          to create a new project linked with the STM32F10x Standard Peripheral 
-  *          Library and working with HiTOP software toolchain (version 5.40 and later).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-  @endverbatim
- 
-@par Directory contents
-
- - Project.htp: A pre-configured project file with the provided library 
-                structure that produces an executable image with HiTOP
-
- - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized
-                      sections from ROM to RAM.                 
-
- - Objects: This mandatory directory contains the executable images.
-
- - Settings: This directory contains the linker and script files.                  
-     - arm_arch.lsl: This file is used to place program code (readonly)
-                     in internal FLASH and data (readwrite, Stack and Heap)
-                     in internal SRAM.
-
-     - link.lnk: This file is the HiTOP linker it invokes the STM32F10x_XL.lsl.
-                                   
-     - reset_appl.scr: This file is a HiTOP script it performs a target reset.
-     
-     - reset_go_main.scr: This file is a HiTOP script and it sets the Program 
-                          Counter at the "main" instruction.
-
-     - StartupScript.scr: This file is a HiTOP script and it performs a target 
-                          reset before loading The executable image.
-
-     - STM32F10x_Xl.lsl: This file is used to place program code (readonly)
-                         in internal FLASH and data (readwrite, Stack and Heap)
-                         in internal SRAM.
-                         It contains also the vector table of the STM32 
-                         XL-density line devices.
-                         You can customize this file to your need. 
-
-
-@par How to use it ?
-
-- Open the HiTOP toolchain.
-- Browse to open the project.htp
-- A "Download application" window is displayed, click "cancel".
-- Rebuild all files: Project->Rebuild all
-- Load project image : Click "ok" in the "Download application" window.
-- Run the "RESET_GO_MAIN" script to set the PC at the "main"
-- Run program: Debug->Go(F5).
-
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 64 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
deleted file mode 100644
index 2c11b4c..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL_XL/setstack.asm
+++ /dev/null
@@ -1,4 +0,0 @@
-	.section	.bss.stack
-	.global	_stacklabel
-_stacklabel:
-	.endsec
\ No newline at end of file
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt
deleted file mode 100644
index af8e3e7..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/MDK-ARM/note.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-/**
-  @page note Note for MDK-ARM
-  
-  @verbatim
-  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
-  * @file    note.txt
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   This file contains the needed steps to use the default startup file
-  *          provided by RealView Microcontroller Development Kit(MDK-ARM).
-  ******************************************************************************
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
-  * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
-  * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
-  * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
-  * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  ******************************************************************************
-
-
-With MDK-ARM toolchain, a simple putchar function executes a SWI and activates 
-a low level putchar function. 
-You have to redirect the low level to your own implementation of these functions.
-
-To guarantee that no functions using the semihosting SWI are included in your 
-application, either:
-
-1. Ensure that the MicroLib option is checked since the microlib does not support
-semihosting
-or 
-2. Use
-- IMPORT __use_no_semihosting_swi from assembly language
-- #pragma import(__use_no_semihosting_swi) from C.
- 
- @endverbatim
- 
-@note
- - Low-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 16 and 32 Kbytes.
- - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
- - Medium-density Value line devices are STM32F100xx microcontrollers where
-   the Flash memory density ranges between 32 and 128 Kbytes.  
- - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx 
-   microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes.
- - High-density Value line devices are STM32F100xx microcontrollers where the 
-   Flash memory density ranges between 256 and 512 Kbytes.
- - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 256 and 512 Kbytes.
- - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
-   the Flash memory density ranges between 512 and 1024 Kbytes.
- - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 
-
- * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
- */
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
deleted file mode 100644
index cbb8819..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F10x_CONF_H
-#define __STM32F10x_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
-#include "stm32f10x_adc.h"
-#include "stm32f10x_bkp.h"
-#include "stm32f10x_can.h"
-#include "stm32f10x_cec.h"
-#include "stm32f10x_crc.h"
-#include "stm32f10x_dac.h"
-#include "stm32f10x_dbgmcu.h"
-#include "stm32f10x_dma.h"
-#include "stm32f10x_exti.h"
-#include "stm32f10x_flash.h"
-#include "stm32f10x_fsmc.h"
-#include "stm32f10x_gpio.h"
-#include "stm32f10x_i2c.h"
-#include "stm32f10x_iwdg.h"
-#include "stm32f10x_pwr.h"
-#include "stm32f10x_rcc.h"
-#include "stm32f10x_rtc.h"
-#include "stm32f10x_sdio.h"
-#include "stm32f10x_spi.h"
-#include "stm32f10x_tim.h"
-#include "stm32f10x_usart.h"
-#include "stm32f10x_wwdg.h"
-#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F10x_CONF_H */
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
deleted file mode 100644
index 18acee1..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c 
-  * @author  MCD Application Team
-  * @version V3.5.0
-  * @date    08-April-2011
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x_it.h"
-
-/** @addtogroup STM32F10x_StdPeriph_Template
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M3 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void)
-{
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void)
-{
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void)
-{
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles PendSVC exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void)
-{
-}
-
-/******************************************************************************/
-/*                 STM32F10x Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f10x_xx.s).                                            */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */ 
-
-
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h
deleted file mode 100644
index 3e86c94..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/STM3210E_EVAL/stm3210e_eval_lcd.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm3210e_eval_lcd.h
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   This file contains all the functions prototypes for the stm3210e_eval_lcd
-  *          firmware driver.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM3210E_EVAL_LCD_H
-#define __STM3210E_EVAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f10x.h"
-#include "../Common/fonts.h"
-
-/** @addtogroup Utilities
-  * @{
-  */
-
-/** @addtogroup STM32_EVAL
-  * @{
-  */ 
-
-/** @addtogroup STM3210E_EVAL
-  * @{
-  */
-    
-/** @addtogroup STM3210E_EVAL_LCD
-  * @{
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Types
-  * @{
-  */
-typedef struct 
-{
-  int16_t X;
-  int16_t Y;
-} Point, * pPoint;   
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Constants
-  * @{
-  */ 
-
-/**
- * @brief Uncomment the line below if you want to use user defined Delay function
- *        (for precise timing), otherwise default _delay_ function defined within
- *         this driver is used (less precise timing).  
- */
-/* #define USE_Delay */
-
-#ifdef USE_Delay
-#include "main.h" 
-  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function
-                                   (with 10ms time base), using SysTick for example */
-#else
-  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */
-#endif
- 
-/** 
-  * @brief  LCD Registers  
-  */ 
-#define LCD_REG_0             0x00
-#define LCD_REG_1             0x01
-#define LCD_REG_2             0x02
-#define LCD_REG_3             0x03
-#define LCD_REG_4             0x04
-#define LCD_REG_5             0x05
-#define LCD_REG_6             0x06
-#define LCD_REG_7             0x07
-#define LCD_REG_8             0x08
-#define LCD_REG_9             0x09
-#define LCD_REG_10            0x0A
-#define LCD_REG_12            0x0C
-#define LCD_REG_13            0x0D
-#define LCD_REG_14            0x0E
-#define LCD_REG_15            0x0F
-#define LCD_REG_16            0x10
-#define LCD_REG_17            0x11
-#define LCD_REG_18            0x12
-#define LCD_REG_19            0x13
-#define LCD_REG_20            0x14
-#define LCD_REG_21            0x15
-#define LCD_REG_22            0x16
-#define LCD_REG_23            0x17
-#define LCD_REG_24            0x18
-#define LCD_REG_25            0x19
-#define LCD_REG_26            0x1A
-#define LCD_REG_27            0x1B
-#define LCD_REG_28            0x1C
-#define LCD_REG_29            0x1D
-#define LCD_REG_30            0x1E
-#define LCD_REG_31            0x1F
-#define LCD_REG_32            0x20
-#define LCD_REG_33            0x21
-#define LCD_REG_34            0x22
-#define LCD_REG_36            0x24
-#define LCD_REG_37            0x25
-#define LCD_REG_40            0x28
-#define LCD_REG_41            0x29
-#define LCD_REG_43            0x2B
-#define LCD_REG_45            0x2D
-#define LCD_REG_48            0x30
-#define LCD_REG_49            0x31
-#define LCD_REG_50            0x32
-#define LCD_REG_51            0x33
-#define LCD_REG_52            0x34
-#define LCD_REG_53            0x35
-#define LCD_REG_54            0x36
-#define LCD_REG_55            0x37
-#define LCD_REG_56            0x38
-#define LCD_REG_57            0x39
-#define LCD_REG_58            0x3A
-#define LCD_REG_59            0x3B
-#define LCD_REG_60            0x3C
-#define LCD_REG_61            0x3D
-#define LCD_REG_62            0x3E
-#define LCD_REG_63            0x3F
-#define LCD_REG_64            0x40
-#define LCD_REG_65            0x41
-#define LCD_REG_66            0x42
-#define LCD_REG_67            0x43
-#define LCD_REG_68            0x44
-#define LCD_REG_69            0x45
-#define LCD_REG_70            0x46
-#define LCD_REG_71            0x47
-#define LCD_REG_72            0x48
-#define LCD_REG_73            0x49
-#define LCD_REG_74            0x4A
-#define LCD_REG_75            0x4B
-#define LCD_REG_76            0x4C
-#define LCD_REG_77            0x4D
-#define LCD_REG_78            0x4E
-#define LCD_REG_79            0x4F
-#define LCD_REG_80            0x50
-#define LCD_REG_81            0x51
-#define LCD_REG_82            0x52
-#define LCD_REG_83            0x53
-#define LCD_REG_96            0x60
-#define LCD_REG_97            0x61
-#define LCD_REG_106           0x6A
-#define LCD_REG_118           0x76
-#define LCD_REG_128           0x80
-#define LCD_REG_129           0x81
-#define LCD_REG_130           0x82
-#define LCD_REG_131           0x83
-#define LCD_REG_132           0x84
-#define LCD_REG_133           0x85
-#define LCD_REG_134           0x86
-#define LCD_REG_135           0x87
-#define LCD_REG_136           0x88
-#define LCD_REG_137           0x89
-#define LCD_REG_139           0x8B
-#define LCD_REG_140           0x8C
-#define LCD_REG_141           0x8D
-#define LCD_REG_143           0x8F
-#define LCD_REG_144           0x90
-#define LCD_REG_145           0x91
-#define LCD_REG_146           0x92
-#define LCD_REG_147           0x93
-#define LCD_REG_148           0x94
-#define LCD_REG_149           0x95
-#define LCD_REG_150           0x96
-#define LCD_REG_151           0x97
-#define LCD_REG_152           0x98
-#define LCD_REG_153           0x99
-#define LCD_REG_154           0x9A
-#define LCD_REG_157           0x9D
-#define LCD_REG_192           0xC0
-#define LCD_REG_193           0xC1
-#define LCD_REG_229           0xE5
-
-/** 
-  * @brief  LCD color  
-  */ 
-#define LCD_COLOR_WHITE          0xFFFF
-#define LCD_COLOR_BLACK          0x0000
-#define LCD_COLOR_GREY           0xF7DE
-#define LCD_COLOR_BLUE           0x001F
-#define LCD_COLOR_BLUE2          0x051F
-#define LCD_COLOR_RED            0xF800
-#define LCD_COLOR_MAGENTA        0xF81F
-#define LCD_COLOR_GREEN          0x07E0
-#define LCD_COLOR_CYAN           0x7FFF
-#define LCD_COLOR_YELLOW         0xFFE0
-
-/** 
-  * @brief  LCD Lines depending on the chosen fonts.  
-  */
-#define LCD_LINE_0               LINE(0)
-#define LCD_LINE_1               LINE(1)
-#define LCD_LINE_2               LINE(2)
-#define LCD_LINE_3               LINE(3)
-#define LCD_LINE_4               LINE(4)
-#define LCD_LINE_5               LINE(5)
-#define LCD_LINE_6               LINE(6)
-#define LCD_LINE_7               LINE(7)
-#define LCD_LINE_8               LINE(8)
-#define LCD_LINE_9               LINE(9)
-#define LCD_LINE_10              LINE(10)
-#define LCD_LINE_11              LINE(11)
-#define LCD_LINE_12              LINE(12)
-#define LCD_LINE_13              LINE(13)
-#define LCD_LINE_14              LINE(14)
-#define LCD_LINE_15              LINE(15)
-#define LCD_LINE_16              LINE(16)
-#define LCD_LINE_17              LINE(17)
-#define LCD_LINE_18              LINE(18)
-#define LCD_LINE_19              LINE(19)
-#define LCD_LINE_20              LINE(20)
-#define LCD_LINE_21              LINE(21)
-#define LCD_LINE_22              LINE(22)
-#define LCD_LINE_23              LINE(23)
-#define LCD_LINE_24              LINE(24)
-#define LCD_LINE_25              LINE(25)
-#define LCD_LINE_26              LINE(26)
-#define LCD_LINE_27              LINE(27)
-#define LCD_LINE_28              LINE(28)
-#define LCD_LINE_29              LINE(29)
-
-/** 
-  * @brief LCD default font 
-  */ 
-#define LCD_DEFAULT_FONT         Font16x24
-
-/** 
-  * @brief  LCD Direction  
-  */ 
-#define LCD_DIR_HORIZONTAL       0x0000
-#define LCD_DIR_VERTICAL         0x0001
-
-/** 
-  * @brief  LCD Size (Width and Height)  
-  */ 
-#define LCD_PIXEL_WIDTH          0x0140
-#define LCD_PIXEL_HEIGHT         0x00F0
-
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Macros
-  * @{
-  */ 
-#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))  
-/**
-  * @}
-  */ 
-
-/** @defgroup STM3210E_EVAL_LCD_Exported_Functions
-  * @{
-  */ 
-/** @defgroup  
-  * @{
-  */ 
-void LCD_DeInit(void);  
-void STM3210E_LCD_Init(void);
-void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor); 
-void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);
-void LCD_SetTextColor(__IO uint16_t Color);
-void LCD_SetBackColor(__IO uint16_t Color);
-void LCD_ClearLine(uint8_t Line);
-void LCD_Clear(uint16_t Color);
-void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
-void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
-void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
-void LCD_SetFont(sFONT *fonts);
-sFONT *LCD_GetFont(void);
-void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
-void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_WindowModeDisable(void);
-void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
-void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
-void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_DrawMonoPict(const uint32_t *Pict);
-void LCD_WriteBMP(uint32_t BmpAddress);
-void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);
-void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);
-void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);
-void LCD_PolyLine(pPoint Points, uint16_t PointCount);
-void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);
-void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);
-void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
-uint16_t LCD_ReadReg(uint8_t LCD_Reg);
-void LCD_WriteRAM_Prepare(void);
-void LCD_WriteRAM(uint16_t RGB_Code);
-uint16_t LCD_ReadRAM(void);
-void LCD_PowerOn(void);
-void LCD_DisplayOn(void);
-void LCD_DisplayOff(void);
-/**
-  * @}
-  */ 
-
-/** @defgroup  
-  * @{
-  */ 
-void LCD_CtrlLinesConfig(void);
-void LCD_FSMCConfig(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM3210E_EVAL_LCD_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c b/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c
deleted file mode 100644
index 9b6984b..0000000
--- a/tmp/STM32F10x_StdPeriph_Lib_V3.5.0/Utilities/STM32_EVAL/stm32_eval.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_eval.c
-  * @author  MCD Application Team
-  * @version V4.5.0
-  * @date    07-March-2011
-  * @brief   STM32xx-EVAL abstraction layer. 
-  *          This file should be added to the main application to use the provided
-  *          functions that manage Leds, push-buttons, COM ports and low level 
-  *          HW resources initialization of the different modules available on
-  *          STM32 evaluation boards from STMicroelectronics.
-  ******************************************************************************
-  * @attention
-  *
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-  *
-  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  ******************************************************************************  
-  */ 
-  
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_eval.h"
-
-/** @addtogroup Utilities
-  * @{
-  */ 
-  
-/** @defgroup STM32_EVAL 
-  * @brief This file provides firmware functions to manage Leds, push-buttons, 
-  *        COM ports and low level HW resources initialization of the different 
-  *        modules available on STM32 Evaluation Boards from STMicroelectronics.
-  * @{
-  */ 
-
-/** @defgroup STM32_EVAL_Abstraction_Layer
-  * @{
-  */ 
-  
-#ifdef USE_STM32100B_EVAL
- #include "stm32100b_eval/stm32100b_eval.c"
-#elif defined USE_STM3210B_EVAL
- #include "stm3210b_eval/stm3210b_eval.c" 
-#elif defined USE_STM3210E_EVAL
- #include "stm3210e_eval/stm3210e_eval.c"
-#elif defined USE_STM3210C_EVAL
- #include "stm3210c_eval/stm3210c_eval.c"
-#elif defined USE_STM32L152_EVAL
- #include "stm32l152_eval/stm32l152_eval.c"
-#elif defined USE_STM32100E_EVAL
- #include "stm32100e_eval/stm32100e_eval.c"
-#else 
- #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"
-#endif
-
-/** @defgroup STM32_EVAL_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_FunctionPrototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup STM32_EVAL_Private_Functions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-    
-/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/